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mlxsw: spectrum: Remove VLANs configuration via SELF flag
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
CommitLineData
56ade8fe
JP		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/slab.h>
44#include <linux/device.h>
45#include <linux/skbuff.h>
46#include <linux/if_vlan.h>
47#include <linux/if_bridge.h>
48#include <linux/workqueue.h>
49#include <linux/jiffies.h>
50#include <linux/bitops.h>
7f71eb46 51#include <linux/list.h>
80bedf1a 52#include <linux/notifier.h>
90183b98 53#include <linux/dcbnl.h>
56ade8fe
JP		 54#include <net/switchdev.h>
55#include <generated/utsrelease.h>
56
57#include "spectrum.h"
58#include "core.h"
59#include "reg.h"
60#include "port.h"
61#include "trap.h"
62#include "txheader.h"
63
64static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
65static const char mlxsw_sp_driver_version[] = "1.0";
66
67/* tx_hdr_version
68 * Tx header version.
69 * Must be set to 1.
70 */
71MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
72
73/* tx_hdr_ctl
74 * Packet control type.
75 * 0 - Ethernet control (e.g. EMADs, LACP)
76 * 1 - Ethernet data
77 */
78MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
79
80/* tx_hdr_proto
81 * Packet protocol type. Must be set to 1 (Ethernet).
82 */
83MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
84
85/* tx_hdr_rx_is_router
86 * Packet is sent from the router. Valid for data packets only.
87 */
88MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
89
90/* tx_hdr_fid_valid
91 * Indicates if the 'fid' field is valid and should be used for
92 * forwarding lookup. Valid for data packets only.
93 */
94MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
95
96/* tx_hdr_swid
97 * Switch partition ID. Must be set to 0.
98 */
99MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
100
101/* tx_hdr_control_tclass
102 * Indicates if the packet should use the control TClass and not one
103 * of the data TClasses.
104 */
105MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
106
107/* tx_hdr_etclass
108 * Egress TClass to be used on the egress device on the egress port.
109 */
110MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
111
112/* tx_hdr_port_mid
113 * Destination local port for unicast packets.
114 * Destination multicast ID for multicast packets.
115 *
116 * Control packets are directed to a specific egress port, while data
117 * packets are transmitted through the CPU port (0) into the switch partition,
118 * where forwarding rules are applied.
119 */
120MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
121
122/* tx_hdr_fid
123 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
124 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
125 * Valid for data packets only.
126 */
127MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
128
129/* tx_hdr_type
130 * 0 - Data packets
131 * 6 - Control packets
132 */
133MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
134
135static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
136 const struct mlxsw_tx_info *tx_info)
137{
138 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
139
140 memset(txhdr, 0, MLXSW_TXHDR_LEN);
141
142 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
143 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
144 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
145 mlxsw_tx_hdr_swid_set(txhdr, 0);
146 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
149}
150
151static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
152{
153 char spad_pl[MLXSW_REG_SPAD_LEN];
154 int err;
155
156 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
157 if (err)
158 return err;
159 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
160 return 0;
161}
162
163static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
164 bool is_up)
165{
166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
167 char paos_pl[MLXSW_REG_PAOS_LEN];
168
169 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
170 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
171 MLXSW_PORT_ADMIN_STATUS_DOWN);
172 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
173}
174
175static int mlxsw_sp_port_oper_status_get(struct mlxsw_sp_port *mlxsw_sp_port,
176 bool *p_is_up)
177{
178 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
179 char paos_pl[MLXSW_REG_PAOS_LEN];
180 u8 oper_status;
181 int err;
182
183 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 0);
184 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
185 if (err)
186 return err;
187 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
188 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
189 return 0;
190}
191
56ade8fe
JP		 192static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
193 unsigned char *addr)
194{
195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
196 char ppad_pl[MLXSW_REG_PPAD_LEN];
197
198 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
199 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
201}
202
203static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
204{
205 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
206 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
207
208 ether_addr_copy(addr, mlxsw_sp->base_mac);
209 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
210 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
211}
212
213static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
214 u16 vid, enum mlxsw_reg_spms_state state)
215{
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
217 char *spms_pl;
218 int err;
219
220 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
221 if (!spms_pl)
222 return -ENOMEM;
223 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
224 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
225 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
226 kfree(spms_pl);
227 return err;
228}
229
230static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
231{
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
233 char pmtu_pl[MLXSW_REG_PMTU_LEN];
234 int max_mtu;
235 int err;
236
237 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
238 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
239 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
240 if (err)
241 return err;
242 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
243
244 if (mtu > max_mtu)
245 return -EINVAL;
246
247 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
249}
250
be94535f
IS		 251static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
252 u8 swid)
56ade8fe 253{
56ade8fe
JP		 254 char pspa_pl[MLXSW_REG_PSPA_LEN];
255
be94535f 256 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
56ade8fe
JP		 257 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
258}
259
be94535f
IS		 260static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
261{
262 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
263
264 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
265 swid);
266}
267
56ade8fe
JP		 268static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
269 bool enable)
270{
271 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
272 char svpe_pl[MLXSW_REG_SVPE_LEN];
273
274 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
275 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
276}
277
278int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
279 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
280 u16 vid)
281{
282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
283 char svfa_pl[MLXSW_REG_SVFA_LEN];
284
285 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
286 fid, vid);
287 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
288}
289
290static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
291 u16 vid, bool learn_enable)
292{
293 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
294 char *spvmlr_pl;
295 int err;
296
297 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
298 if (!spvmlr_pl)
299 return -ENOMEM;
300 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
301 learn_enable);
302 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
303 kfree(spvmlr_pl);
304 return err;
305}
306
307static int
308mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
309{
310 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
311 char sspr_pl[MLXSW_REG_SSPR_LEN];
312
313 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
314 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
315}
316
d664b41e
IS		 317static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
318 u8 local_port, u8 *p_module,
319 u8 *p_width, u8 *p_lane)
56ade8fe 320{
56ade8fe
JP		 321 char pmlp_pl[MLXSW_REG_PMLP_LEN];
322 int err;
323
558c2d5e 324 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
56ade8fe
JP		 325 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
326 if (err)
327 return err;
558c2d5e
IS		 328 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
329 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
2bf9a586 330 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
56ade8fe
JP		 331 return 0;
332}
333
18f1e70c
IS		 334static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
335 u8 module, u8 width, u8 lane)
336{
337 char pmlp_pl[MLXSW_REG_PMLP_LEN];
338 int i;
339
340 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
341 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
342 for (i = 0; i < width; i++) {
343 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
344 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
345 }
346
347 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
348}
349
3e9b27b8
IS		 350static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
351{
352 char pmlp_pl[MLXSW_REG_PMLP_LEN];
353
354 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
355 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
356 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
357}
358
56ade8fe
JP		 359static int mlxsw_sp_port_open(struct net_device *dev)
360{
361 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
362 int err;
363
364 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
365 if (err)
366 return err;
367 netif_start_queue(dev);
368 return 0;
369}
370
371static int mlxsw_sp_port_stop(struct net_device *dev)
372{
373 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
374
375 netif_stop_queue(dev);
376 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
377}
378
379static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
380 struct net_device *dev)
381{
382 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
383 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
384 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
385 const struct mlxsw_tx_info tx_info = {
386 .local_port = mlxsw_sp_port->local_port,
387 .is_emad = false,
388 };
389 u64 len;
390 int err;
391
307c2431 392 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
56ade8fe
JP		 393 return NETDEV_TX_BUSY;
394
395 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
396 struct sk_buff *skb_orig = skb;
397
398 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
399 if (!skb) {
400 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
401 dev_kfree_skb_any(skb_orig);
402 return NETDEV_TX_OK;
403 }
404 }
405
406 if (eth_skb_pad(skb)) {
407 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
408 return NETDEV_TX_OK;
409 }
410
411 mlxsw_sp_txhdr_construct(skb, &tx_info);
63dcdd35
NF		 412 /* TX header is consumed by HW on the way so we shouldn't count its
413 * bytes as being sent.
414 */
415 len = skb->len - MLXSW_TXHDR_LEN;
416
56ade8fe
JP		 417 /* Due to a race we might fail here because of a full queue. In that
418 * unlikely case we simply drop the packet.
419 */
307c2431 420 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
56ade8fe
JP		 421
422 if (!err) {
423 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
424 u64_stats_update_begin(&pcpu_stats->syncp);
425 pcpu_stats->tx_packets++;
426 pcpu_stats->tx_bytes += len;
427 u64_stats_update_end(&pcpu_stats->syncp);
428 } else {
429 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
430 dev_kfree_skb_any(skb);
431 }
432 return NETDEV_TX_OK;
433}
434
c5b9b518
JP		 435static void mlxsw_sp_set_rx_mode(struct net_device *dev)
436{
437}
438
56ade8fe
JP		 439static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
440{
441 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
442 struct sockaddr *addr = p;
443 int err;
444
445 if (!is_valid_ether_addr(addr->sa_data))
446 return -EADDRNOTAVAIL;
447
448 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
449 if (err)
450 return err;
451 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
452 return 0;
453}
454
9f7ec052 455static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
d81a6bdb 456 bool pause_en, bool pfc_en, u16 delay)
ff6551ec 457{
ff6551ec 458 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
8e8dfe9f 459
d81a6bdb
IS		 460 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
461 MLXSW_SP_PAUSE_DELAY;
9f7ec052 462
d81a6bdb 463 if (pause_en || pfc_en)
9f7ec052 464 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
d81a6bdb
IS		 465 pg_size + delay, pg_size);
466 else
9f7ec052 467 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
8e8dfe9f
IS		 468}
469
470int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
d81a6bdb
IS		 471 u8 *prio_tc, bool pause_en,
472 struct ieee_pfc *my_pfc)
8e8dfe9f
IS		 473{
474 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
d81a6bdb
IS		 475 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
476 u16 delay = !!my_pfc ? my_pfc->delay : 0;
ff6551ec 477 char pbmc_pl[MLXSW_REG_PBMC_LEN];
8e8dfe9f 478 int i, j, err;
ff6551ec
IS		 479
480 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
481 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
482 if (err)
483 return err;
8e8dfe9f
IS		 484
485 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
486 bool configure = false;
d81a6bdb 487 bool pfc = false;
8e8dfe9f
IS		 488
489 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
490 if (prio_tc[j] == i) {
d81a6bdb 491 pfc = pfc_en & BIT(j);
8e8dfe9f
IS		 492 configure = true;
493 break;
494 }
495 }
496
497 if (!configure)
498 continue;
d81a6bdb 499 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
8e8dfe9f
IS		 500 }
501
ff6551ec
IS		 502 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
503}
504
8e8dfe9f 505static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
9f7ec052 506 int mtu, bool pause_en)
8e8dfe9f
IS		 507{
508 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
509 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
d81a6bdb 510 struct ieee_pfc *my_pfc;
8e8dfe9f
IS		 511 u8 *prio_tc;
512
513 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
d81a6bdb 514 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
8e8dfe9f 515
9f7ec052 516 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
d81a6bdb 517 pause_en, my_pfc);
8e8dfe9f
IS		 518}
519
56ade8fe
JP		 520static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
521{
522 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
9f7ec052 523 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
56ade8fe
JP		 524 int err;
525
9f7ec052 526 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
56ade8fe
JP		 527 if (err)
528 return err;
ff6551ec
IS		 529 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
530 if (err)
531 goto err_port_mtu_set;
56ade8fe
JP		 532 dev->mtu = mtu;
533 return 0;
ff6551ec
IS		 534
535err_port_mtu_set:
9f7ec052 536 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
ff6551ec 537 return err;
56ade8fe
JP		 538}
539
540static struct rtnl_link_stats64 *
541mlxsw_sp_port_get_stats64(struct net_device *dev,
542 struct rtnl_link_stats64 *stats)
543{
544 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
545 struct mlxsw_sp_port_pcpu_stats *p;
546 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
547 u32 tx_dropped = 0;
548 unsigned int start;
549 int i;
550
551 for_each_possible_cpu(i) {
552 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
553 do {
554 start = u64_stats_fetch_begin_irq(&p->syncp);
555 rx_packets = p->rx_packets;
556 rx_bytes = p->rx_bytes;
557 tx_packets = p->tx_packets;
558 tx_bytes = p->tx_bytes;
559 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
560
561 stats->rx_packets += rx_packets;
562 stats->rx_bytes += rx_bytes;
563 stats->tx_packets += tx_packets;
564 stats->tx_bytes += tx_bytes;
565 /* tx_dropped is u32, updated without syncp protection. */
566 tx_dropped += p->tx_dropped;
567 }
568 stats->tx_dropped = tx_dropped;
569 return stats;
570}
571
572int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
573 u16 vid_end, bool is_member, bool untagged)
574{
575 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
576 char *spvm_pl;
577 int err;
578
579 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
580 if (!spvm_pl)
581 return -ENOMEM;
582
583 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
584 vid_end, is_member, untagged);
585 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
586 kfree(spvm_pl);
587 return err;
588}
589
590static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
591{
592 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
593 u16 vid, last_visited_vid;
594 int err;
595
596 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
597 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
598 vid);
599 if (err) {
600 last_visited_vid = vid;
601 goto err_port_vid_to_fid_set;
602 }
603 }
604
605 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
606 if (err) {
607 last_visited_vid = VLAN_N_VID;
608 goto err_port_vid_to_fid_set;
609 }
610
611 return 0;
612
613err_port_vid_to_fid_set:
614 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
615 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
616 vid);
617 return err;
618}
619
620static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
621{
622 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
623 u16 vid;
624 int err;
625
626 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
627 if (err)
628 return err;
629
630 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
631 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
632 vid, vid);
633 if (err)
634 return err;
635 }
636
637 return 0;
638}
639
d0ec875a 640static struct mlxsw_sp_fid *
7f71eb46
IS		 641mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, u16 vid)
642{
d0ec875a 643 struct mlxsw_sp_fid *f;
7f71eb46 644
d0ec875a
IS		 645 list_for_each_entry(f, &mlxsw_sp->port_vfids.list, list) {
646 if (f->vid == vid)
647 return f;
7f71eb46
IS		 648 }
649
650 return NULL;
651}
652
653static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
654{
655 return find_first_zero_bit(mlxsw_sp->port_vfids.mapped,
656 MLXSW_SP_VFID_PORT_MAX);
657}
658
c7e920b5 659static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
7f71eb46 660{
7f71eb46
IS		 661 char sfmr_pl[MLXSW_REG_SFMR_LEN];
662
c7e920b5 663 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
7f71eb46
IS		 664 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
665}
666
1c800759
IS		 667static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
668
d0ec875a
IS		 669static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
670 u16 vid)
7f71eb46
IS		 671{
672 struct device *dev = mlxsw_sp->bus_info->dev;
d0ec875a 673 struct mlxsw_sp_fid *f;
c7e920b5 674 u16 vfid, fid;
7f71eb46
IS		 675 int err;
676
c7e920b5
IS		 677 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
678 if (vfid == MLXSW_SP_VFID_PORT_MAX) {
7f71eb46
IS		 679 dev_err(dev, "No available vFIDs\n");
680 return ERR_PTR(-ERANGE);
681 }
682
c7e920b5
IS		 683 fid = mlxsw_sp_vfid_to_fid(vfid);
684 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
7f71eb46 685 if (err) {
c7e920b5 686 dev_err(dev, "Failed to create FID=%d\n", fid);
7f71eb46
IS		 687 return ERR_PTR(err);
688 }
689
c7e920b5
IS		 690 f = kzalloc(sizeof(*f), GFP_KERNEL);
691 if (!f)
7f71eb46
IS		 692 goto err_allocate_vfid;
693
1c800759 694 f->leave = mlxsw_sp_vport_vfid_leave;
d0ec875a 695 f->fid = fid;
c7e920b5 696 f->vid = vid;
7f71eb46 697
c7e920b5
IS		 698 list_add(&f->list, &mlxsw_sp->port_vfids.list);
699 set_bit(vfid, mlxsw_sp->port_vfids.mapped);
7f71eb46 700
c7e920b5 701 return f;
7f71eb46
IS		 702
703err_allocate_vfid:
c7e920b5 704 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
7f71eb46
IS		 705 return ERR_PTR(-ENOMEM);
706}
707
708static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
d0ec875a 709 struct mlxsw_sp_fid *f)
7f71eb46 710{
d0ec875a 711 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
c7e920b5 712
d0ec875a
IS		 713 clear_bit(vfid, mlxsw_sp->port_vfids.mapped);
714 list_del(&f->list);
7f71eb46 715
d0ec875a 716 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
7f71eb46 717
d0ec875a 718 kfree(f);
7f71eb46
IS		 719}
720
721static struct mlxsw_sp_port *
0355b59f 722mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
7f71eb46
IS		 723{
724 struct mlxsw_sp_port *mlxsw_sp_vport;
725
726 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
727 if (!mlxsw_sp_vport)
728 return NULL;
729
730 /* dev will be set correctly after the VLAN device is linked
731 * with the real device. In case of bridge SELF invocation, dev
732 * will remain as is.
733 */
734 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
735 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
736 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
737 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
272c4470
IS		 738 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
739 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
0355b59f 740 mlxsw_sp_vport->vport.vid = vid;
7f71eb46
IS		 741
742 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
743
744 return mlxsw_sp_vport;
745}
746
747static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
748{
749 list_del(&mlxsw_sp_vport->vport.list);
750 kfree(mlxsw_sp_vport);
751}
752
9c4d4423
IS		 753static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
754 bool valid)
755{
756 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
757 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
758
759 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
760 vid);
761}
762
0355b59f
IS		 763static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport)
764{
765 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
766 struct mlxsw_sp_fid *f;
767 int err;
768
769 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, vid);
770 if (!f) {
771 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, vid);
772 if (IS_ERR(f))
773 return PTR_ERR(f);
774 }
775
776 if (!f->ref_count) {
777 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
778 if (err)
779 goto err_vport_flood_set;
780 }
781
782 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
783 if (err)
784 goto err_vport_fid_map;
785
41b996cc 786 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
0355b59f
IS		 787 f->ref_count++;
788
789 return 0;
790
791err_vport_fid_map:
792 if (!f->ref_count)
793 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
794err_vport_flood_set:
795 if (!f->ref_count)
796 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
797 return err;
798}
799
800static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
801{
41b996cc 802 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
0355b59f 803
41b996cc 804 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
0355b59f
IS		 805
806 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
807
808 if (--f->ref_count == 0) {
809 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
810 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
811 }
812}
813
56ade8fe
JP		 814int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
815 u16 vid)
816{
817 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
7f71eb46 818 struct mlxsw_sp_port *mlxsw_sp_vport;
52697a9e 819 bool untagged = vid == 1;
56ade8fe
JP		 820 int err;
821
822 /* VLAN 0 is added to HW filter when device goes up, but it is
823 * reserved in our case, so simply return.
824 */
825 if (!vid)
826 return 0;
827
7f71eb46 828 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid)) {
56ade8fe
JP		 829 netdev_warn(dev, "VID=%d already configured\n", vid);
830 return 0;
831 }
832
0355b59f 833 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
7f71eb46
IS		 834 if (!mlxsw_sp_vport) {
835 netdev_err(dev, "Failed to create vPort for VID=%d\n", vid);
0355b59f 836 return -ENOMEM;
56ade8fe
JP		 837 }
838
56ade8fe
JP		 839 /* When adding the first VLAN interface on a bridged port we need to
840 * transition all the active 802.1Q bridge VLANs to use explicit
841 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
842 */
7f71eb46 843 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
56ade8fe
JP		 844 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
845 if (err) {
846 netdev_err(dev, "Failed to set to Virtual mode\n");
7f71eb46 847 goto err_port_vp_mode_trans;
56ade8fe
JP		 848 }
849 }
850
0355b59f 851 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
56ade8fe 852 if (err) {
0355b59f
IS		 853 netdev_err(dev, "Failed to join vFID\n");
854 goto err_vport_vfid_join;
56ade8fe
JP		 855 }
856
7f71eb46 857 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
56ade8fe
JP		 858 if (err) {
859 netdev_err(dev, "Failed to disable learning for VID=%d\n", vid);
860 goto err_port_vid_learning_set;
861 }
862
52697a9e 863 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
56ade8fe
JP		 864 if (err) {
865 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
866 vid);
867 goto err_port_add_vid;
868 }
869
7f71eb46 870 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
56ade8fe
JP		 871 MLXSW_REG_SPMS_STATE_FORWARDING);
872 if (err) {
873 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
874 goto err_port_stp_state_set;
875 }
876
56ade8fe
JP		 877 return 0;
878
56ade8fe 879err_port_stp_state_set:
7f71eb46 880 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
56ade8fe 881err_port_add_vid:
7f71eb46 882 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
56ade8fe 883err_port_vid_learning_set:
0355b59f
IS		 884 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
885err_vport_vfid_join:
7f71eb46
IS		 886 if (list_is_singular(&mlxsw_sp_port->vports_list))
887 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
888err_port_vp_mode_trans:
7f71eb46 889 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
56ade8fe
JP		 890 return err;
891}
892
32d863fb
IS		 893static int mlxsw_sp_port_kill_vid(struct net_device *dev,
894 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 895{
896 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
7f71eb46 897 struct mlxsw_sp_port *mlxsw_sp_vport;
1c800759 898 struct mlxsw_sp_fid *f;
56ade8fe
JP		 899 int err;
900
901 /* VLAN 0 is removed from HW filter when device goes down, but
902 * it is reserved in our case, so simply return.
903 */
904 if (!vid)
905 return 0;
906
7f71eb46
IS		 907 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
908 if (!mlxsw_sp_vport) {
56ade8fe
JP		 909 netdev_warn(dev, "VID=%d does not exist\n", vid);
910 return 0;
911 }
912
7f71eb46 913 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
56ade8fe
JP		 914 MLXSW_REG_SPMS_STATE_DISCARDING);
915 if (err) {
916 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
917 return err;
918 }
919
7f71eb46 920 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
56ade8fe
JP		 921 if (err) {
922 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
923 vid);
924 return err;
925 }
926
7f71eb46 927 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
56ade8fe
JP		 928 if (err) {
929 netdev_err(dev, "Failed to enable learning for VID=%d\n", vid);
930 return err;
931 }
932
1c800759
IS		 933 /* Drop FID reference. If this was the last reference the
934 * resources will be freed.
935 */
936 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
937 if (f && !WARN_ON(!f->leave))
938 f->leave(mlxsw_sp_vport);
56ade8fe
JP		 939
940 /* When removing the last VLAN interface on a bridged port we need to
941 * transition all active 802.1Q bridge VLANs to use VID to FID
942 * mappings and set port's mode to VLAN mode.
943 */
7f71eb46 944 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
56ade8fe
JP		 945 err = mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
946 if (err) {
947 netdev_err(dev, "Failed to set to VLAN mode\n");
948 return err;
949 }
950 }
951
7f71eb46
IS		 952 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
953
56ade8fe
JP		 954 return 0;
955}
956
2bf9a586
IS		 957static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
958 size_t len)
959{
960 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
d664b41e
IS		 961 u8 module = mlxsw_sp_port->mapping.module;
962 u8 width = mlxsw_sp_port->mapping.width;
963 u8 lane = mlxsw_sp_port->mapping.lane;
2bf9a586
IS		 964 int err;
965
2bf9a586
IS		 966 if (!mlxsw_sp_port->split)
967 err = snprintf(name, len, "p%d", module + 1);
968 else
969 err = snprintf(name, len, "p%ds%d", module + 1,
970 lane / width);
971
972 if (err >= len)
973 return -EINVAL;
974
975 return 0;
976}
977
56ade8fe
JP		 978static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
979 .ndo_open = mlxsw_sp_port_open,
980 .ndo_stop = mlxsw_sp_port_stop,
981 .ndo_start_xmit = mlxsw_sp_port_xmit,
c5b9b518 982 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
56ade8fe
JP		 983 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
984 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
985 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
986 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
987 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
988 .ndo_fdb_add = switchdev_port_fdb_add,
989 .ndo_fdb_del = switchdev_port_fdb_del,
990 .ndo_fdb_dump = switchdev_port_fdb_dump,
991 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
992 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
993 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
2bf9a586 994 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
56ade8fe
JP		 995};
996
997static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
998 struct ethtool_drvinfo *drvinfo)
999{
1000 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1001 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1002
1003 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1004 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1005 sizeof(drvinfo->version));
1006 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1007 "%d.%d.%d",
1008 mlxsw_sp->bus_info->fw_rev.major,
1009 mlxsw_sp->bus_info->fw_rev.minor,
1010 mlxsw_sp->bus_info->fw_rev.subminor);
1011 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1012 sizeof(drvinfo->bus_info));
1013}
1014
9f7ec052
IS		 1015static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1016 struct ethtool_pauseparam *pause)
1017{
1018 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1019
1020 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1021 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1022}
1023
1024static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1025 struct ethtool_pauseparam *pause)
1026{
1027 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1028
1029 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1030 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1031 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1032
1033 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1034 pfcc_pl);
1035}
1036
1037static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1038 struct ethtool_pauseparam *pause)
1039{
1040 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1041 bool pause_en = pause->tx_pause || pause->rx_pause;
1042 int err;
1043
d81a6bdb
IS		 1044 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1045 netdev_err(dev, "PFC already enabled on port\n");
1046 return -EINVAL;
1047 }
1048
9f7ec052
IS		 1049 if (pause->autoneg) {
1050 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1051 return -EINVAL;
1052 }
1053
1054 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1055 if (err) {
1056 netdev_err(dev, "Failed to configure port's headroom\n");
1057 return err;
1058 }
1059
1060 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1061 if (err) {
1062 netdev_err(dev, "Failed to set PAUSE parameters\n");
1063 goto err_port_pause_configure;
1064 }
1065
1066 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1067 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1068
1069 return 0;
1070
1071err_port_pause_configure:
1072 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1073 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1074 return err;
1075}
1076
56ade8fe
JP		 1077struct mlxsw_sp_port_hw_stats {
1078 char str[ETH_GSTRING_LEN];
1079 u64 (*getter)(char *payload);
1080};
1081
1082static const struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1083 {
1084 .str = "a_frames_transmitted_ok",
1085 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1086 },
1087 {
1088 .str = "a_frames_received_ok",
1089 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1090 },
1091 {
1092 .str = "a_frame_check_sequence_errors",
1093 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1094 },
1095 {
1096 .str = "a_alignment_errors",
1097 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1098 },
1099 {
1100 .str = "a_octets_transmitted_ok",
1101 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1102 },
1103 {
1104 .str = "a_octets_received_ok",
1105 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1106 },
1107 {
1108 .str = "a_multicast_frames_xmitted_ok",
1109 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1110 },
1111 {
1112 .str = "a_broadcast_frames_xmitted_ok",
1113 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1114 },
1115 {
1116 .str = "a_multicast_frames_received_ok",
1117 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1118 },
1119 {
1120 .str = "a_broadcast_frames_received_ok",
1121 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1122 },
1123 {
1124 .str = "a_in_range_length_errors",
1125 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1126 },
1127 {
1128 .str = "a_out_of_range_length_field",
1129 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1130 },
1131 {
1132 .str = "a_frame_too_long_errors",
1133 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1134 },
1135 {
1136 .str = "a_symbol_error_during_carrier",
1137 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1138 },
1139 {
1140 .str = "a_mac_control_frames_transmitted",
1141 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1142 },
1143 {
1144 .str = "a_mac_control_frames_received",
1145 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1146 },
1147 {
1148 .str = "a_unsupported_opcodes_received",
1149 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1150 },
1151 {
1152 .str = "a_pause_mac_ctrl_frames_received",
1153 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1154 },
1155 {
1156 .str = "a_pause_mac_ctrl_frames_xmitted",
1157 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1158 },
1159};
1160
1161#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1162
1163static void mlxsw_sp_port_get_strings(struct net_device *dev,
1164 u32 stringset, u8 *data)
1165{
1166 u8 *p = data;
1167 int i;
1168
1169 switch (stringset) {
1170 case ETH_SS_STATS:
1171 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1172 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1173 ETH_GSTRING_LEN);
1174 p += ETH_GSTRING_LEN;
1175 }
1176 break;
1177 }
1178}
1179
3a66ee38
IS		 1180static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1181 enum ethtool_phys_id_state state)
1182{
1183 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1184 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1185 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1186 bool active;
1187
1188 switch (state) {
1189 case ETHTOOL_ID_ACTIVE:
1190 active = true;
1191 break;
1192 case ETHTOOL_ID_INACTIVE:
1193 active = false;
1194 break;
1195 default:
1196 return -EOPNOTSUPP;
1197 }
1198
1199 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1201}
1202
56ade8fe
JP		 1203static void mlxsw_sp_port_get_stats(struct net_device *dev,
1204 struct ethtool_stats *stats, u64 *data)
1205{
1206 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1207 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1208 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1209 int i;
1210 int err;
1211
34dba0a5
IS		 1212 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port,
1213 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
56ade8fe
JP		 1214 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1215 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++)
1216 data[i] = !err ? mlxsw_sp_port_hw_stats[i].getter(ppcnt_pl) : 0;
1217}
1218
1219static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1220{
1221 switch (sset) {
1222 case ETH_SS_STATS:
1223 return MLXSW_SP_PORT_HW_STATS_LEN;
1224 default:
1225 return -EOPNOTSUPP;
1226 }
1227}
1228
1229struct mlxsw_sp_port_link_mode {
1230 u32 mask;
1231 u32 supported;
1232 u32 advertised;
1233 u32 speed;
1234};
1235
1236static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1237 {
1238 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1239 .supported = SUPPORTED_100baseT_Full,
1240 .advertised = ADVERTISED_100baseT_Full,
1241 .speed = 100,
1242 },
1243 {
1244 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
1245 .speed = 100,
1246 },
1247 {
1248 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1249 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1250 .supported = SUPPORTED_1000baseKX_Full,
1251 .advertised = ADVERTISED_1000baseKX_Full,
1252 .speed = 1000,
1253 },
1254 {
1255 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1256 .supported = SUPPORTED_10000baseT_Full,
1257 .advertised = ADVERTISED_10000baseT_Full,
1258 .speed = 10000,
1259 },
1260 {
1261 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1262 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1263 .supported = SUPPORTED_10000baseKX4_Full,
1264 .advertised = ADVERTISED_10000baseKX4_Full,
1265 .speed = 10000,
1266 },
1267 {
1268 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1269 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1270 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1271 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1272 .supported = SUPPORTED_10000baseKR_Full,
1273 .advertised = ADVERTISED_10000baseKR_Full,
1274 .speed = 10000,
1275 },
1276 {
1277 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1278 .supported = SUPPORTED_20000baseKR2_Full,
1279 .advertised = ADVERTISED_20000baseKR2_Full,
1280 .speed = 20000,
1281 },
1282 {
1283 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1284 .supported = SUPPORTED_40000baseCR4_Full,
1285 .advertised = ADVERTISED_40000baseCR4_Full,
1286 .speed = 40000,
1287 },
1288 {
1289 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1290 .supported = SUPPORTED_40000baseKR4_Full,
1291 .advertised = ADVERTISED_40000baseKR4_Full,
1292 .speed = 40000,
1293 },
1294 {
1295 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1296 .supported = SUPPORTED_40000baseSR4_Full,
1297 .advertised = ADVERTISED_40000baseSR4_Full,
1298 .speed = 40000,
1299 },
1300 {
1301 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1302 .supported = SUPPORTED_40000baseLR4_Full,
1303 .advertised = ADVERTISED_40000baseLR4_Full,
1304 .speed = 40000,
1305 },
1306 {
1307 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
1308 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
1309 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1310 .speed = 25000,
1311 },
1312 {
1313 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
1314 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
1315 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1316 .speed = 50000,
1317 },
1318 {
1319 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1320 .supported = SUPPORTED_56000baseKR4_Full,
1321 .advertised = ADVERTISED_56000baseKR4_Full,
1322 .speed = 56000,
1323 },
1324 {
1325 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
1326 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1327 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1328 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1329 .speed = 100000,
1330 },
1331};
1332
1333#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1334
1335static u32 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto)
1336{
1337 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1338 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1339 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1340 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1341 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1342 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1343 return SUPPORTED_FIBRE;
1344
1345 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1346 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1347 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1348 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1349 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1350 return SUPPORTED_Backplane;
1351 return 0;
1352}
1353
1354static u32 mlxsw_sp_from_ptys_supported_link(u32 ptys_eth_proto)
1355{
1356 u32 modes = 0;
1357 int i;
1358
1359 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1360 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1361 modes |= mlxsw_sp_port_link_mode[i].supported;
1362 }
1363 return modes;
1364}
1365
1366static u32 mlxsw_sp_from_ptys_advert_link(u32 ptys_eth_proto)
1367{
1368 u32 modes = 0;
1369 int i;
1370
1371 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1372 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1373 modes |= mlxsw_sp_port_link_mode[i].advertised;
1374 }
1375 return modes;
1376}
1377
1378static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1379 struct ethtool_cmd *cmd)
1380{
1381 u32 speed = SPEED_UNKNOWN;
1382 u8 duplex = DUPLEX_UNKNOWN;
1383 int i;
1384
1385 if (!carrier_ok)
1386 goto out;
1387
1388 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1389 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1390 speed = mlxsw_sp_port_link_mode[i].speed;
1391 duplex = DUPLEX_FULL;
1392 break;
1393 }
1394 }
1395out:
1396 ethtool_cmd_speed_set(cmd, speed);
1397 cmd->duplex = duplex;
1398}
1399
1400static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1401{
1402 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1403 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1404 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1405 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1406 return PORT_FIBRE;
1407
1408 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1409 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1410 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1411 return PORT_DA;
1412
1413 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1414 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1415 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1416 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1417 return PORT_NONE;
1418
1419 return PORT_OTHER;
1420}
1421
1422static int mlxsw_sp_port_get_settings(struct net_device *dev,
1423 struct ethtool_cmd *cmd)
1424{
1425 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1426 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1427 char ptys_pl[MLXSW_REG_PTYS_LEN];
1428 u32 eth_proto_cap;
1429 u32 eth_proto_admin;
1430 u32 eth_proto_oper;
1431 int err;
1432
1433 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1434 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1435 if (err) {
1436 netdev_err(dev, "Failed to get proto");
1437 return err;
1438 }
1439 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
1440 &eth_proto_admin, &eth_proto_oper);
1441
1442 cmd->supported = mlxsw_sp_from_ptys_supported_port(eth_proto_cap) |
1443 mlxsw_sp_from_ptys_supported_link(eth_proto_cap) |
1444 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1445 cmd->advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_admin);
1446 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev),
1447 eth_proto_oper, cmd);
1448
1449 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1450 cmd->port = mlxsw_sp_port_connector_port(eth_proto_oper);
1451 cmd->lp_advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_oper);
1452
1453 cmd->transceiver = XCVR_INTERNAL;
1454 return 0;
1455}
1456
1457static u32 mlxsw_sp_to_ptys_advert_link(u32 advertising)
1458{
1459 u32 ptys_proto = 0;
1460 int i;
1461
1462 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1463 if (advertising & mlxsw_sp_port_link_mode[i].advertised)
1464 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1465 }
1466 return ptys_proto;
1467}
1468
1469static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1470{
1471 u32 ptys_proto = 0;
1472 int i;
1473
1474 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1475 if (speed == mlxsw_sp_port_link_mode[i].speed)
1476 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1477 }
1478 return ptys_proto;
1479}
1480
18f1e70c
IS		 1481static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1482{
1483 u32 ptys_proto = 0;
1484 int i;
1485
1486 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1487 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1488 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1489 }
1490 return ptys_proto;
1491}
1492
56ade8fe
JP		 1493static int mlxsw_sp_port_set_settings(struct net_device *dev,
1494 struct ethtool_cmd *cmd)
1495{
1496 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1497 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1498 char ptys_pl[MLXSW_REG_PTYS_LEN];
1499 u32 speed;
1500 u32 eth_proto_new;
1501 u32 eth_proto_cap;
1502 u32 eth_proto_admin;
1503 bool is_up;
1504 int err;
1505
1506 speed = ethtool_cmd_speed(cmd);
1507
1508 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
1509 mlxsw_sp_to_ptys_advert_link(cmd->advertising) :
1510 mlxsw_sp_to_ptys_speed(speed);
1511
1512 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1513 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1514 if (err) {
1515 netdev_err(dev, "Failed to get proto");
1516 return err;
1517 }
1518 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
1519
1520 eth_proto_new = eth_proto_new & eth_proto_cap;
1521 if (!eth_proto_new) {
1522 netdev_err(dev, "Not supported proto admin requested");
1523 return -EINVAL;
1524 }
1525 if (eth_proto_new == eth_proto_admin)
1526 return 0;
1527
1528 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
1529 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1530 if (err) {
1531 netdev_err(dev, "Failed to set proto admin");
1532 return err;
1533 }
1534
1535 err = mlxsw_sp_port_oper_status_get(mlxsw_sp_port, &is_up);
1536 if (err) {
1537 netdev_err(dev, "Failed to get oper status");
1538 return err;
1539 }
1540 if (!is_up)
1541 return 0;
1542
1543 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1544 if (err) {
1545 netdev_err(dev, "Failed to set admin status");
1546 return err;
1547 }
1548
1549 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1550 if (err) {
1551 netdev_err(dev, "Failed to set admin status");
1552 return err;
1553 }
1554
1555 return 0;
1556}
1557
1558static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1559 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1560 .get_link = ethtool_op_get_link,
9f7ec052
IS		 1561 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
1562 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
56ade8fe 1563 .get_strings = mlxsw_sp_port_get_strings,
3a66ee38 1564 .set_phys_id = mlxsw_sp_port_set_phys_id,
56ade8fe
JP		 1565 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1566 .get_sset_count = mlxsw_sp_port_get_sset_count,
1567 .get_settings = mlxsw_sp_port_get_settings,
1568 .set_settings = mlxsw_sp_port_set_settings,
1569};
1570
18f1e70c
IS		 1571static int
1572mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
1573{
1574 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1575 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
1576 char ptys_pl[MLXSW_REG_PTYS_LEN];
1577 u32 eth_proto_admin;
1578
1579 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
1580 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
1581 eth_proto_admin);
1582 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1583}
1584
8e8dfe9f
IS		 1585int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1586 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1587 bool dwrr, u8 dwrr_weight)
90183b98
IS		 1588{
1589 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1590 char qeec_pl[MLXSW_REG_QEEC_LEN];
1591
1592 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1593 next_index);
1594 mlxsw_reg_qeec_de_set(qeec_pl, true);
1595 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1596 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1598}
1599
cc7cf517
IS		 1600int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1601 enum mlxsw_reg_qeec_hr hr, u8 index,
1602 u8 next_index, u32 maxrate)
90183b98
IS		 1603{
1604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1605 char qeec_pl[MLXSW_REG_QEEC_LEN];
1606
1607 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1608 next_index);
1609 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1610 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1611 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1612}
1613
8e8dfe9f
IS		 1614int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1615 u8 switch_prio, u8 tclass)
90183b98
IS		 1616{
1617 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1618 char qtct_pl[MLXSW_REG_QTCT_LEN];
1619
1620 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1621 tclass);
1622 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1623}
1624
1625static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1626{
1627 int err, i;
1628
1629 /* Setup the elements hierarcy, so that each TC is linked to
1630 * one subgroup, which are all member in the same group.
1631 */
1632 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1633 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
1634 0);
1635 if (err)
1636 return err;
1637 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1638 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1639 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
1640 0, false, 0);
1641 if (err)
1642 return err;
1643 }
1644 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1645 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1646 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
1647 false, 0);
1648 if (err)
1649 return err;
1650 }
1651
1652 /* Make sure the max shaper is disabled in all hierarcies that
1653 * support it.
1654 */
1655 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1656 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
1657 MLXSW_REG_QEEC_MAS_DIS);
1658 if (err)
1659 return err;
1660 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1661 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1662 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1663 i, 0,
1664 MLXSW_REG_QEEC_MAS_DIS);
1665 if (err)
1666 return err;
1667 }
1668 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1669 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1670 MLXSW_REG_QEEC_HIERARCY_TC,
1671 i, i,
1672 MLXSW_REG_QEEC_MAS_DIS);
1673 if (err)
1674 return err;
1675 }
1676
1677 /* Map all priorities to traffic class 0. */
1678 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1679 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1680 if (err)
1681 return err;
1682 }
1683
1684 return 0;
1685}
1686
be94535f 1687static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
d664b41e 1688 bool split, u8 module, u8 width, u8 lane)
56ade8fe
JP		 1689{
1690 struct mlxsw_sp_port *mlxsw_sp_port;
1691 struct net_device *dev;
bd40e9d6 1692 size_t bytes;
56ade8fe
JP		 1693 int err;
1694
1695 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1696 if (!dev)
1697 return -ENOMEM;
1698 mlxsw_sp_port = netdev_priv(dev);
1699 mlxsw_sp_port->dev = dev;
1700 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1701 mlxsw_sp_port->local_port = local_port;
18f1e70c 1702 mlxsw_sp_port->split = split;
d664b41e
IS		 1703 mlxsw_sp_port->mapping.module = module;
1704 mlxsw_sp_port->mapping.width = width;
1705 mlxsw_sp_port->mapping.lane = lane;
bd40e9d6
IS		 1706 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
1707 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
1708 if (!mlxsw_sp_port->active_vlans) {
1709 err = -ENOMEM;
1710 goto err_port_active_vlans_alloc;
1711 }
fc1273af
ER		 1712 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
1713 if (!mlxsw_sp_port->untagged_vlans) {
1714 err = -ENOMEM;
1715 goto err_port_untagged_vlans_alloc;
1716 }
7f71eb46 1717 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
56ade8fe
JP		 1718
1719 mlxsw_sp_port->pcpu_stats =
1720 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1721 if (!mlxsw_sp_port->pcpu_stats) {
1722 err = -ENOMEM;
1723 goto err_alloc_stats;
1724 }
1725
1726 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1727 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1728
1729 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1730 if (err) {
1731 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1732 mlxsw_sp_port->local_port);
1733 goto err_dev_addr_init;
1734 }
1735
1736 netif_carrier_off(dev);
1737
1738 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1739 NETIF_F_HW_VLAN_CTAG_FILTER;
1740
1741 /* Each packet needs to have a Tx header (metadata) on top all other
1742 * headers.
1743 */
1744 dev->hard_header_len += MLXSW_TXHDR_LEN;
1745
56ade8fe
JP		 1746 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1747 if (err) {
1748 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1749 mlxsw_sp_port->local_port);
1750 goto err_port_system_port_mapping_set;
1751 }
1752
1753 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1754 if (err) {
1755 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1756 mlxsw_sp_port->local_port);
1757 goto err_port_swid_set;
1758 }
1759
18f1e70c
IS		 1760 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
1761 if (err) {
1762 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1763 mlxsw_sp_port->local_port);
1764 goto err_port_speed_by_width_set;
1765 }
1766
56ade8fe
JP		 1767 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1768 if (err) {
1769 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1770 mlxsw_sp_port->local_port);
1771 goto err_port_mtu_set;
1772 }
1773
1774 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1775 if (err)
1776 goto err_port_admin_status_set;
1777
1778 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1779 if (err) {
1780 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1781 mlxsw_sp_port->local_port);
1782 goto err_port_buffers_init;
1783 }
1784
90183b98
IS		 1785 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1786 if (err) {
1787 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1788 mlxsw_sp_port->local_port);
1789 goto err_port_ets_init;
1790 }
1791
f00817df
IS		 1792 /* ETS and buffers must be initialized before DCB. */
1793 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1794 if (err) {
1795 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1796 mlxsw_sp_port->local_port);
1797 goto err_port_dcb_init;
1798 }
1799
56ade8fe
JP		 1800 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
1801 err = register_netdev(dev);
1802 if (err) {
1803 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1804 mlxsw_sp_port->local_port);
1805 goto err_register_netdev;
1806 }
1807
932762b6
JP		 1808 err = mlxsw_core_port_init(mlxsw_sp->core, &mlxsw_sp_port->core_port,
1809 mlxsw_sp_port->local_port, dev,
1810 mlxsw_sp_port->split, module);
1811 if (err) {
1812 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1813 mlxsw_sp_port->local_port);
1814 goto err_core_port_init;
1815 }
c4745500 1816
56ade8fe
JP		 1817 err = mlxsw_sp_port_vlan_init(mlxsw_sp_port);
1818 if (err)
1819 goto err_port_vlan_init;
1820
1821 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1822 return 0;
1823
1824err_port_vlan_init:
932762b6
JP		 1825 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
1826err_core_port_init:
56ade8fe
JP		 1827 unregister_netdev(dev);
1828err_register_netdev:
f00817df 1829err_port_dcb_init:
90183b98 1830err_port_ets_init:
56ade8fe
JP		 1831err_port_buffers_init:
1832err_port_admin_status_set:
1833err_port_mtu_set:
18f1e70c 1834err_port_speed_by_width_set:
56ade8fe
JP		 1835err_port_swid_set:
1836err_port_system_port_mapping_set:
56ade8fe
JP		 1837err_dev_addr_init:
1838 free_percpu(mlxsw_sp_port->pcpu_stats);
1839err_alloc_stats:
fc1273af
ER		 1840 kfree(mlxsw_sp_port->untagged_vlans);
1841err_port_untagged_vlans_alloc:
bd40e9d6
IS		 1842 kfree(mlxsw_sp_port->active_vlans);
1843err_port_active_vlans_alloc:
56ade8fe
JP		 1844 free_netdev(dev);
1845 return err;
1846}
1847
56ade8fe
JP		 1848static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1849{
1850 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1851
1852 if (!mlxsw_sp_port)
1853 return;
a133318c 1854 mlxsw_sp->ports[local_port] = NULL;
932762b6 1855 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
56ade8fe 1856 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
f00817df 1857 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
32d863fb 1858 mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
56ade8fe 1859 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3e9b27b8
IS		 1860 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1861 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
56ade8fe 1862 free_percpu(mlxsw_sp_port->pcpu_stats);
fc1273af 1863 kfree(mlxsw_sp_port->untagged_vlans);
bd40e9d6 1864 kfree(mlxsw_sp_port->active_vlans);
32d863fb 1865 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
56ade8fe
JP		 1866 free_netdev(mlxsw_sp_port->dev);
1867}
1868
1869static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1870{
1871 int i;
1872
1873 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1874 mlxsw_sp_port_remove(mlxsw_sp, i);
1875 kfree(mlxsw_sp->ports);
1876}
1877
1878static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1879{
d664b41e 1880 u8 module, width, lane;
56ade8fe
JP		 1881 size_t alloc_size;
1882 int i;
1883 int err;
1884
1885 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
1886 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1887 if (!mlxsw_sp->ports)
1888 return -ENOMEM;
1889
1890 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
558c2d5e 1891 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
d664b41e 1892 &width, &lane);
558c2d5e
IS		 1893 if (err)
1894 goto err_port_module_info_get;
1895 if (!width)
1896 continue;
1897 mlxsw_sp->port_to_module[i] = module;
d664b41e
IS		 1898 err = mlxsw_sp_port_create(mlxsw_sp, i, false, module, width,
1899 lane);
56ade8fe
JP		 1900 if (err)
1901 goto err_port_create;
1902 }
1903 return 0;
1904
1905err_port_create:
558c2d5e 1906err_port_module_info_get:
56ade8fe
JP		 1907 for (i--; i >= 1; i--)
1908 mlxsw_sp_port_remove(mlxsw_sp, i);
1909 kfree(mlxsw_sp->ports);
1910 return err;
1911}
1912
18f1e70c
IS		 1913static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
1914{
1915 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
1916
1917 return local_port - offset;
1918}
1919
be94535f
IS		 1920static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
1921 u8 module, unsigned int count)
1922{
1923 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
1924 int err, i;
1925
1926 for (i = 0; i < count; i++) {
1927 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
1928 width, i * width);
1929 if (err)
1930 goto err_port_module_map;
1931 }
1932
1933 for (i = 0; i < count; i++) {
1934 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
1935 if (err)
1936 goto err_port_swid_set;
1937 }
1938
1939 for (i = 0; i < count; i++) {
1940 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
d664b41e 1941 module, width, i * width);
be94535f
IS		 1942 if (err)
1943 goto err_port_create;
1944 }
1945
1946 return 0;
1947
1948err_port_create:
1949 for (i--; i >= 0; i--)
1950 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1951 i = count;
1952err_port_swid_set:
1953 for (i--; i >= 0; i--)
1954 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
1955 MLXSW_PORT_SWID_DISABLED_PORT);
1956 i = count;
1957err_port_module_map:
1958 for (i--; i >= 0; i--)
1959 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
1960 return err;
1961}
1962
1963static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
1964 u8 base_port, unsigned int count)
1965{
1966 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
1967 int i;
1968
1969 /* Split by four means we need to re-create two ports, otherwise
1970 * only one.
1971 */
1972 count = count / 2;
1973
1974 for (i = 0; i < count; i++) {
1975 local_port = base_port + i * 2;
1976 module = mlxsw_sp->port_to_module[local_port];
1977
1978 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
1979 0);
1980 }
1981
1982 for (i = 0; i < count; i++)
1983 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
1984
1985 for (i = 0; i < count; i++) {
1986 local_port = base_port + i * 2;
1987 module = mlxsw_sp->port_to_module[local_port];
1988
1989 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
d664b41e 1990 width, 0);
be94535f
IS		 1991 }
1992}
1993
b2f10571
JP		 1994static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
1995 unsigned int count)
18f1e70c 1996{
b2f10571 1997 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 1998 struct mlxsw_sp_port *mlxsw_sp_port;
18f1e70c
IS		 1999 u8 module, cur_width, base_port;
2000 int i;
2001 int err;
2002
2003 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2004 if (!mlxsw_sp_port) {
2005 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2006 local_port);
2007 return -EINVAL;
2008 }
2009
d664b41e
IS		 2010 module = mlxsw_sp_port->mapping.module;
2011 cur_width = mlxsw_sp_port->mapping.width;
2012
18f1e70c
IS		 2013 if (count != 2 && count != 4) {
2014 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2015 return -EINVAL;
2016 }
2017
18f1e70c
IS		 2018 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2019 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2020 return -EINVAL;
2021 }
2022
2023 /* Make sure we have enough slave (even) ports for the split. */
2024 if (count == 2) {
2025 base_port = local_port;
2026 if (mlxsw_sp->ports[base_port + 1]) {
2027 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2028 return -EINVAL;
2029 }
2030 } else {
2031 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2032 if (mlxsw_sp->ports[base_port + 1] ||
2033 mlxsw_sp->ports[base_port + 3]) {
2034 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2035 return -EINVAL;
2036 }
2037 }
2038
2039 for (i = 0; i < count; i++)
2040 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2041
be94535f
IS		 2042 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2043 if (err) {
2044 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2045 goto err_port_split_create;
18f1e70c
IS		 2046 }
2047
2048 return 0;
2049
be94535f
IS		 2050err_port_split_create:
2051 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 2052 return err;
2053}
2054
b2f10571 2055static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
18f1e70c 2056{
b2f10571 2057 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 2058 struct mlxsw_sp_port *mlxsw_sp_port;
d664b41e 2059 u8 cur_width, base_port;
18f1e70c
IS		 2060 unsigned int count;
2061 int i;
18f1e70c
IS		 2062
2063 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2064 if (!mlxsw_sp_port) {
2065 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2066 local_port);
2067 return -EINVAL;
2068 }
2069
2070 if (!mlxsw_sp_port->split) {
2071 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2072 return -EINVAL;
2073 }
2074
d664b41e 2075 cur_width = mlxsw_sp_port->mapping.width;
18f1e70c
IS		 2076 count = cur_width == 1 ? 4 : 2;
2077
2078 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2079
2080 /* Determine which ports to remove. */
2081 if (count == 2 && local_port >= base_port + 2)
2082 base_port = base_port + 2;
2083
2084 for (i = 0; i < count; i++)
2085 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2086
be94535f 2087 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 2088
2089 return 0;
2090}
2091
56ade8fe
JP		 2092static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2093 char *pude_pl, void *priv)
2094{
2095 struct mlxsw_sp *mlxsw_sp = priv;
2096 struct mlxsw_sp_port *mlxsw_sp_port;
2097 enum mlxsw_reg_pude_oper_status status;
2098 u8 local_port;
2099
2100 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2101 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2102 if (!mlxsw_sp_port) {
2103 dev_warn(mlxsw_sp->bus_info->dev, "Port %d: Link event received for non-existent port\n",
2104 local_port);
2105 return;
2106 }
2107
2108 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2109 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2110 netdev_info(mlxsw_sp_port->dev, "link up\n");
2111 netif_carrier_on(mlxsw_sp_port->dev);
2112 } else {
2113 netdev_info(mlxsw_sp_port->dev, "link down\n");
2114 netif_carrier_off(mlxsw_sp_port->dev);
2115 }
2116}
2117
2118static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2119 .func = mlxsw_sp_pude_event_func,
2120 .trap_id = MLXSW_TRAP_ID_PUDE,
2121};
2122
2123static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2124 enum mlxsw_event_trap_id trap_id)
2125{
2126 struct mlxsw_event_listener *el;
2127 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2128 int err;
2129
2130 switch (trap_id) {
2131 case MLXSW_TRAP_ID_PUDE:
2132 el = &mlxsw_sp_pude_event;
2133 break;
2134 }
2135 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2136 if (err)
2137 return err;
2138
2139 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2140 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2141 if (err)
2142 goto err_event_trap_set;
2143
2144 return 0;
2145
2146err_event_trap_set:
2147 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2148 return err;
2149}
2150
2151static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2152 enum mlxsw_event_trap_id trap_id)
2153{
2154 struct mlxsw_event_listener *el;
2155
2156 switch (trap_id) {
2157 case MLXSW_TRAP_ID_PUDE:
2158 el = &mlxsw_sp_pude_event;
2159 break;
2160 }
2161 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2162}
2163
2164static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2165 void *priv)
2166{
2167 struct mlxsw_sp *mlxsw_sp = priv;
2168 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2169 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2170
2171 if (unlikely(!mlxsw_sp_port)) {
2172 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2173 local_port);
2174 return;
2175 }
2176
2177 skb->dev = mlxsw_sp_port->dev;
2178
2179 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2180 u64_stats_update_begin(&pcpu_stats->syncp);
2181 pcpu_stats->rx_packets++;
2182 pcpu_stats->rx_bytes += skb->len;
2183 u64_stats_update_end(&pcpu_stats->syncp);
2184
2185 skb->protocol = eth_type_trans(skb, skb->dev);
2186 netif_receive_skb(skb);
2187}
2188
2189static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
2190 {
2191 .func = mlxsw_sp_rx_listener_func,
2192 .local_port = MLXSW_PORT_DONT_CARE,
2193 .trap_id = MLXSW_TRAP_ID_FDB_MC,
2194 },
2195 /* Traps for specific L2 packet types, not trapped as FDB MC */
2196 {
2197 .func = mlxsw_sp_rx_listener_func,
2198 .local_port = MLXSW_PORT_DONT_CARE,
2199 .trap_id = MLXSW_TRAP_ID_STP,
2200 },
2201 {
2202 .func = mlxsw_sp_rx_listener_func,
2203 .local_port = MLXSW_PORT_DONT_CARE,
2204 .trap_id = MLXSW_TRAP_ID_LACP,
2205 },
2206 {
2207 .func = mlxsw_sp_rx_listener_func,
2208 .local_port = MLXSW_PORT_DONT_CARE,
2209 .trap_id = MLXSW_TRAP_ID_EAPOL,
2210 },
2211 {
2212 .func = mlxsw_sp_rx_listener_func,
2213 .local_port = MLXSW_PORT_DONT_CARE,
2214 .trap_id = MLXSW_TRAP_ID_LLDP,
2215 },
2216 {
2217 .func = mlxsw_sp_rx_listener_func,
2218 .local_port = MLXSW_PORT_DONT_CARE,
2219 .trap_id = MLXSW_TRAP_ID_MMRP,
2220 },
2221 {
2222 .func = mlxsw_sp_rx_listener_func,
2223 .local_port = MLXSW_PORT_DONT_CARE,
2224 .trap_id = MLXSW_TRAP_ID_MVRP,
2225 },
2226 {
2227 .func = mlxsw_sp_rx_listener_func,
2228 .local_port = MLXSW_PORT_DONT_CARE,
2229 .trap_id = MLXSW_TRAP_ID_RPVST,
2230 },
2231 {
2232 .func = mlxsw_sp_rx_listener_func,
2233 .local_port = MLXSW_PORT_DONT_CARE,
2234 .trap_id = MLXSW_TRAP_ID_DHCP,
2235 },
2236 {
2237 .func = mlxsw_sp_rx_listener_func,
2238 .local_port = MLXSW_PORT_DONT_CARE,
2239 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
2240 },
2241 {
2242 .func = mlxsw_sp_rx_listener_func,
2243 .local_port = MLXSW_PORT_DONT_CARE,
2244 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
2245 },
2246 {
2247 .func = mlxsw_sp_rx_listener_func,
2248 .local_port = MLXSW_PORT_DONT_CARE,
2249 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
2250 },
2251 {
2252 .func = mlxsw_sp_rx_listener_func,
2253 .local_port = MLXSW_PORT_DONT_CARE,
2254 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
2255 },
2256 {
2257 .func = mlxsw_sp_rx_listener_func,
2258 .local_port = MLXSW_PORT_DONT_CARE,
2259 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
2260 },
2261};
2262
2263static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2264{
2265 char htgt_pl[MLXSW_REG_HTGT_LEN];
2266 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2267 int i;
2268 int err;
2269
2270 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2271 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2272 if (err)
2273 return err;
2274
2275 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2276 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2277 if (err)
2278 return err;
2279
2280 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2281 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2282 &mlxsw_sp_rx_listener[i],
2283 mlxsw_sp);
2284 if (err)
2285 goto err_rx_listener_register;
2286
2287 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2288 mlxsw_sp_rx_listener[i].trap_id);
2289 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2290 if (err)
2291 goto err_rx_trap_set;
2292 }
2293 return 0;
2294
2295err_rx_trap_set:
2296 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2297 &mlxsw_sp_rx_listener[i],
2298 mlxsw_sp);
2299err_rx_listener_register:
2300 for (i--; i >= 0; i--) {
2301 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2302 mlxsw_sp_rx_listener[i].trap_id);
2303 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2304
2305 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2306 &mlxsw_sp_rx_listener[i],
2307 mlxsw_sp);
2308 }
2309 return err;
2310}
2311
2312static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2313{
2314 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2315 int i;
2316
2317 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2318 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2319 mlxsw_sp_rx_listener[i].trap_id);
2320 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2321
2322 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2323 &mlxsw_sp_rx_listener[i],
2324 mlxsw_sp);
2325 }
2326}
2327
2328static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2329 enum mlxsw_reg_sfgc_type type,
2330 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2331{
2332 enum mlxsw_flood_table_type table_type;
2333 enum mlxsw_sp_flood_table flood_table;
2334 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2335
19ae6124 2336 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
56ade8fe 2337 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
19ae6124 2338 else
56ade8fe 2339 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
19ae6124
IS		 2340
2341 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2342 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2343 else
2344 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
56ade8fe
JP		 2345
2346 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2347 flood_table);
2348 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2349}
2350
2351static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2352{
2353 int type, err;
2354
56ade8fe
JP		 2355 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2356 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2357 continue;
2358
2359 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2360 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2361 if (err)
2362 return err;
56ade8fe
JP		 2363
2364 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2365 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2366 if (err)
2367 return err;
2368 }
2369
2370 return 0;
2371}
2372
0d65fc13
JP		 2373static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2374{
2375 char slcr_pl[MLXSW_REG_SLCR_LEN];
2376
2377 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2378 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2379 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2380 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2381 MLXSW_REG_SLCR_LAG_HASH_SIP |
2382 MLXSW_REG_SLCR_LAG_HASH_DIP |
2383 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2384 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2385 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2386 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2387}
2388
b2f10571 2389static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
56ade8fe
JP		 2390 const struct mlxsw_bus_info *mlxsw_bus_info)
2391{
b2f10571 2392 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe
JP		 2393 int err;
2394
2395 mlxsw_sp->core = mlxsw_core;
2396 mlxsw_sp->bus_info = mlxsw_bus_info;
14d39461 2397 INIT_LIST_HEAD(&mlxsw_sp->fids);
7f71eb46 2398 INIT_LIST_HEAD(&mlxsw_sp->port_vfids.list);
26f0e7fb 2399 INIT_LIST_HEAD(&mlxsw_sp->br_vfids.list);
3a49b4fd 2400 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
56ade8fe
JP		 2401
2402 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2403 if (err) {
2404 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2405 return err;
2406 }
2407
2408 err = mlxsw_sp_ports_create(mlxsw_sp);
2409 if (err) {
2410 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
7f71eb46 2411 return err;
56ade8fe
JP		 2412 }
2413
2414 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2415 if (err) {
2416 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
2417 goto err_event_register;
2418 }
2419
2420 err = mlxsw_sp_traps_init(mlxsw_sp);
2421 if (err) {
2422 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2423 goto err_rx_listener_register;
2424 }
2425
2426 err = mlxsw_sp_flood_init(mlxsw_sp);
2427 if (err) {
2428 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2429 goto err_flood_init;
2430 }
2431
2432 err = mlxsw_sp_buffers_init(mlxsw_sp);
2433 if (err) {
2434 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2435 goto err_buffers_init;
2436 }
2437
0d65fc13
JP		 2438 err = mlxsw_sp_lag_init(mlxsw_sp);
2439 if (err) {
2440 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2441 goto err_lag_init;
2442 }
2443
56ade8fe
JP		 2444 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2445 if (err) {
2446 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2447 goto err_switchdev_init;
2448 }
2449
2450 return 0;
2451
2452err_switchdev_init:
0d65fc13 2453err_lag_init:
0f433fa0 2454 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe
JP		 2455err_buffers_init:
2456err_flood_init:
2457 mlxsw_sp_traps_fini(mlxsw_sp);
2458err_rx_listener_register:
2459 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2460err_event_register:
2461 mlxsw_sp_ports_remove(mlxsw_sp);
56ade8fe
JP		 2462 return err;
2463}
2464
b2f10571 2465static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
56ade8fe 2466{
b2f10571 2467 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe
JP		 2468
2469 mlxsw_sp_switchdev_fini(mlxsw_sp);
5113bfdb 2470 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe
JP		 2471 mlxsw_sp_traps_fini(mlxsw_sp);
2472 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2473 mlxsw_sp_ports_remove(mlxsw_sp);
14d39461 2474 WARN_ON(!list_empty(&mlxsw_sp->fids));
56ade8fe
JP		 2475}
2476
2477static struct mlxsw_config_profile mlxsw_sp_config_profile = {
2478 .used_max_vepa_channels = 1,
2479 .max_vepa_channels = 0,
2480 .used_max_lag = 1,
0d65fc13 2481 .max_lag = MLXSW_SP_LAG_MAX,
56ade8fe 2482 .used_max_port_per_lag = 1,
0d65fc13 2483 .max_port_per_lag = MLXSW_SP_PORT_PER_LAG_MAX,
56ade8fe 2484 .used_max_mid = 1,
53ae6283 2485 .max_mid = MLXSW_SP_MID_MAX,
56ade8fe
JP		 2486 .used_max_pgt = 1,
2487 .max_pgt = 0,
2488 .used_max_system_port = 1,
2489 .max_system_port = 64,
2490 .used_max_vlan_groups = 1,
2491 .max_vlan_groups = 127,
2492 .used_max_regions = 1,
2493 .max_regions = 400,
2494 .used_flood_tables = 1,
2495 .used_flood_mode = 1,
2496 .flood_mode = 3,
2497 .max_fid_offset_flood_tables = 2,
2498 .fid_offset_flood_table_size = VLAN_N_VID - 1,
19ae6124
IS		 2499 .max_fid_flood_tables = 2,
2500 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
56ade8fe
JP		 2501 .used_max_ib_mc = 1,
2502 .max_ib_mc = 0,
2503 .used_max_pkey = 1,
2504 .max_pkey = 0,
2505 .swid_config = {
2506 {
2507 .used_type = 1,
2508 .type = MLXSW_PORT_SWID_TYPE_ETH,
2509 }
2510 },
2511};
2512
2513static struct mlxsw_driver mlxsw_sp_driver = {
2d0ed39f
JP		 2514 .kind = MLXSW_DEVICE_KIND_SPECTRUM,
2515 .owner = THIS_MODULE,
2516 .priv_size = sizeof(struct mlxsw_sp),
2517 .init = mlxsw_sp_init,
2518 .fini = mlxsw_sp_fini,
2519 .port_split = mlxsw_sp_port_split,
2520 .port_unsplit = mlxsw_sp_port_unsplit,
2521 .sb_pool_get = mlxsw_sp_sb_pool_get,
2522 .sb_pool_set = mlxsw_sp_sb_pool_set,
2523 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
2524 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
2525 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
2526 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
2527 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
2528 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
2529 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
2530 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
2531 .txhdr_construct = mlxsw_sp_txhdr_construct,
2532 .txhdr_len = MLXSW_TXHDR_LEN,
2533 .profile = &mlxsw_sp_config_profile,
56ade8fe
JP		 2534};
2535
fe3f6d14
IS		 2536static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
2537 u16 fid)
2538{
2539 if (mlxsw_sp_fid_is_vfid(fid))
2540 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
2541 else
2542 return test_bit(fid, lag_port->active_vlans);
2543}
2544
2545static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
2546 u16 fid)
039c49a6
IS		 2547{
2548 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
fe3f6d14
IS		 2549 u8 local_port = mlxsw_sp_port->local_port;
2550 u16 lag_id = mlxsw_sp_port->lag_id;
2551 int i, count = 0;
039c49a6 2552
fe3f6d14
IS		 2553 if (!mlxsw_sp_port->lagged)
2554 return true;
039c49a6 2555
fe3f6d14
IS		 2556 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2557 struct mlxsw_sp_port *lag_port;
2558
2559 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
2560 if (!lag_port || lag_port->local_port == local_port)
2561 continue;
2562 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
2563 count++;
2564 }
2565
2566 return !count;
039c49a6
IS		 2567}
2568
2569static int
2570mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2571 u16 fid)
2572{
2573 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2574 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2575
2576 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
2577 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2578 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
2579 mlxsw_sp_port->local_port);
2580
22305378
IS		 2581 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
2582 mlxsw_sp_port->local_port, fid);
2583
039c49a6
IS		 2584 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2585}
2586
039c49a6
IS		 2587static int
2588mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2589 u16 fid)
2590{
2591 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2592 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2593
2594 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
2595 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2596 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2597
22305378
IS		 2598 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
2599 mlxsw_sp_port->lag_id, fid);
2600
039c49a6
IS		 2601 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2602}
2603
fe3f6d14 2604int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
039c49a6 2605{
fe3f6d14
IS		 2606 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
2607 return 0;
039c49a6 2608
fe3f6d14
IS		 2609 if (mlxsw_sp_port->lagged)
2610 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
039c49a6
IS		 2611 fid);
2612 else
fe3f6d14 2613 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
039c49a6
IS		 2614}
2615
56ade8fe
JP		 2616static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
2617{
2618 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
2619}
2620
7117a570
IS		 2621static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
2622 struct net_device *br_dev)
2623{
2624 return !mlxsw_sp->master_bridge.dev ||
2625 mlxsw_sp->master_bridge.dev == br_dev;
2626}
2627
2628static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
2629 struct net_device *br_dev)
2630{
2631 mlxsw_sp->master_bridge.dev = br_dev;
2632 mlxsw_sp->master_bridge.ref_count++;
2633}
2634
2635static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
2636{
2637 if (--mlxsw_sp->master_bridge.ref_count == 0)
2638 mlxsw_sp->master_bridge.dev = NULL;
2639}
2640
2641static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
2642 struct net_device *br_dev)
56ade8fe
JP		 2643{
2644 struct net_device *dev = mlxsw_sp_port->dev;
2645 int err;
2646
2647 /* When port is not bridged untagged packets are tagged with
2648 * PVID=VID=1, thereby creating an implicit VLAN interface in
2649 * the device. Remove it and let bridge code take care of its
2650 * own VLANs.
2651 */
2652 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
6c72a3d0
IS		 2653 if (err)
2654 return err;
56ade8fe 2655
7117a570
IS		 2656 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
2657
6c72a3d0
IS		 2658 mlxsw_sp_port->learning = 1;
2659 mlxsw_sp_port->learning_sync = 1;
2660 mlxsw_sp_port->uc_flood = 1;
2661 mlxsw_sp_port->bridged = 1;
2662
2663 return 0;
56ade8fe
JP		 2664}
2665
fe3f6d14 2666static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
56ade8fe
JP		 2667{
2668 struct net_device *dev = mlxsw_sp_port->dev;
5a8f4525 2669
28a01d2d
IS		 2670 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
2671
7117a570
IS		 2672 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
2673
6c72a3d0
IS		 2674 mlxsw_sp_port->learning = 0;
2675 mlxsw_sp_port->learning_sync = 0;
2676 mlxsw_sp_port->uc_flood = 0;
5a8f4525 2677 mlxsw_sp_port->bridged = 0;
56ade8fe
JP		 2678
2679 /* Add implicit VLAN interface in the device, so that untagged
2680 * packets will be classified to the default vFID.
2681 */
82e6db03 2682 mlxsw_sp_port_add_vid(dev, 0, 1);
56ade8fe
JP		 2683}
2684
0d65fc13
JP		 2685static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2686{
2687 char sldr_pl[MLXSW_REG_SLDR_LEN];
2688
2689 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
2690 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2691}
2692
2693static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2694{
2695 char sldr_pl[MLXSW_REG_SLDR_LEN];
2696
2697 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
2698 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2699}
2700
2701static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2702 u16 lag_id, u8 port_index)
2703{
2704 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2705 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2706
2707 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
2708 lag_id, port_index);
2709 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2710}
2711
2712static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2713 u16 lag_id)
2714{
2715 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2716 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2717
2718 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
2719 lag_id);
2720 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2721}
2722
2723static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
2724 u16 lag_id)
2725{
2726 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2727 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2728
2729 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
2730 lag_id);
2731 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2732}
2733
2734static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
2735 u16 lag_id)
2736{
2737 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2738 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2739
2740 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
2741 lag_id);
2742 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2743}
2744
2745static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2746 struct net_device *lag_dev,
2747 u16 *p_lag_id)
2748{
2749 struct mlxsw_sp_upper *lag;
2750 int free_lag_id = -1;
2751 int i;
2752
2753 for (i = 0; i < MLXSW_SP_LAG_MAX; i++) {
2754 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
2755 if (lag->ref_count) {
2756 if (lag->dev == lag_dev) {
2757 *p_lag_id = i;
2758 return 0;
2759 }
2760 } else if (free_lag_id < 0) {
2761 free_lag_id = i;
2762 }
2763 }
2764 if (free_lag_id < 0)
2765 return -EBUSY;
2766 *p_lag_id = free_lag_id;
2767 return 0;
2768}
2769
2770static bool
2771mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
2772 struct net_device *lag_dev,
2773 struct netdev_lag_upper_info *lag_upper_info)
2774{
2775 u16 lag_id;
2776
2777 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
2778 return false;
2779 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2780 return false;
2781 return true;
2782}
2783
2784static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2785 u16 lag_id, u8 *p_port_index)
2786{
2787 int i;
2788
2789 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2790 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
2791 *p_port_index = i;
2792 return 0;
2793 }
2794 }
2795 return -EBUSY;
2796}
2797
2798static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2799 struct net_device *lag_dev)
2800{
2801 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2802 struct mlxsw_sp_upper *lag;
2803 u16 lag_id;
2804 u8 port_index;
2805 int err;
2806
2807 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
2808 if (err)
2809 return err;
2810 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2811 if (!lag->ref_count) {
2812 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
2813 if (err)
2814 return err;
2815 lag->dev = lag_dev;
2816 }
2817
2818 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
2819 if (err)
2820 return err;
2821 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
2822 if (err)
2823 goto err_col_port_add;
2824 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
2825 if (err)
2826 goto err_col_port_enable;
2827
2828 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
2829 mlxsw_sp_port->local_port);
2830 mlxsw_sp_port->lag_id = lag_id;
2831 mlxsw_sp_port->lagged = 1;
2832 lag->ref_count++;
2833 return 0;
2834
51554db2
IS		 2835err_col_port_enable:
2836 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13
JP		 2837err_col_port_add:
2838 if (!lag->ref_count)
2839 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 2840 return err;
2841}
2842
82e6db03
IS		 2843static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2844 struct net_device *lag_dev)
0d65fc13
JP		 2845{
2846 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0d65fc13 2847 u16 lag_id = mlxsw_sp_port->lag_id;
1c800759 2848 struct mlxsw_sp_upper *lag;
0d65fc13
JP		 2849
2850 if (!mlxsw_sp_port->lagged)
82e6db03 2851 return;
0d65fc13
JP		 2852 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2853 WARN_ON(lag->ref_count == 0);
2854
82e6db03
IS		 2855 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
2856 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13 2857
4dc236c3
IS		 2858 if (mlxsw_sp_port->bridged) {
2859 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
fe3f6d14 2860 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
4dc236c3
IS		 2861 }
2862
fe3f6d14 2863 if (lag->ref_count == 1)
82e6db03 2864 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 2865
2866 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
2867 mlxsw_sp_port->local_port);
2868 mlxsw_sp_port->lagged = 0;
2869 lag->ref_count--;
0d65fc13
JP		 2870}
2871
74581206
JP		 2872static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2873 u16 lag_id)
2874{
2875 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2876 char sldr_pl[MLXSW_REG_SLDR_LEN];
2877
2878 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
2879 mlxsw_sp_port->local_port);
2880 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2881}
2882
2883static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2884 u16 lag_id)
2885{
2886 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2887 char sldr_pl[MLXSW_REG_SLDR_LEN];
2888
2889 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
2890 mlxsw_sp_port->local_port);
2891 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2892}
2893
2894static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
2895 bool lag_tx_enabled)
2896{
2897 if (lag_tx_enabled)
2898 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
2899 mlxsw_sp_port->lag_id);
2900 else
2901 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
2902 mlxsw_sp_port->lag_id);
2903}
2904
2905static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
2906 struct netdev_lag_lower_state_info *info)
2907{
2908 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
2909}
2910
9589a7b5
IS		 2911static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
2912 struct net_device *vlan_dev)
2913{
2914 struct mlxsw_sp_port *mlxsw_sp_vport;
2915 u16 vid = vlan_dev_vlan_id(vlan_dev);
2916
2917 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
423b937e 2918 if (WARN_ON(!mlxsw_sp_vport))
9589a7b5 2919 return -EINVAL;
9589a7b5
IS		 2920
2921 mlxsw_sp_vport->dev = vlan_dev;
2922
2923 return 0;
2924}
2925
82e6db03
IS		 2926static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
2927 struct net_device *vlan_dev)
9589a7b5
IS		 2928{
2929 struct mlxsw_sp_port *mlxsw_sp_vport;
2930 u16 vid = vlan_dev_vlan_id(vlan_dev);
2931
2932 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
423b937e 2933 if (WARN_ON(!mlxsw_sp_vport))
82e6db03 2934 return;
9589a7b5
IS		 2935
2936 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
9589a7b5
IS		 2937}
2938
74581206
JP		 2939static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
2940 unsigned long event, void *ptr)
56ade8fe 2941{
56ade8fe
JP		 2942 struct netdev_notifier_changeupper_info *info;
2943 struct mlxsw_sp_port *mlxsw_sp_port;
2944 struct net_device *upper_dev;
2945 struct mlxsw_sp *mlxsw_sp;
80bedf1a 2946 int err = 0;
56ade8fe 2947
56ade8fe
JP		 2948 mlxsw_sp_port = netdev_priv(dev);
2949 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2950 info = ptr;
2951
2952 switch (event) {
2953 case NETDEV_PRECHANGEUPPER:
2954 upper_dev = info->upper_dev;
59fe9b3f
IS		 2955 if (!is_vlan_dev(upper_dev) &&
2956 !netif_is_lag_master(upper_dev) &&
2957 !netif_is_bridge_master(upper_dev))
2958 return -EINVAL;
6ec43904 2959 if (!info->linking)
0d65fc13 2960 break;
56ade8fe 2961 /* HW limitation forbids to put ports to multiple bridges. */
0d65fc13 2962 if (netif_is_bridge_master(upper_dev) &&
56ade8fe 2963 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
80bedf1a 2964 return -EINVAL;
0d65fc13
JP		 2965 if (netif_is_lag_master(upper_dev) &&
2966 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
2967 info->upper_info))
80bedf1a 2968 return -EINVAL;
6ec43904
IS		 2969 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
2970 return -EINVAL;
2971 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
2972 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
2973 return -EINVAL;
56ade8fe
JP		 2974 break;
2975 case NETDEV_CHANGEUPPER:
2976 upper_dev = info->upper_dev;
9589a7b5 2977 if (is_vlan_dev(upper_dev)) {
80bedf1a 2978 if (info->linking)
9589a7b5
IS		 2979 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
2980 upper_dev);
80bedf1a 2981 else
82e6db03
IS		 2982 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
2983 upper_dev);
9589a7b5 2984 } else if (netif_is_bridge_master(upper_dev)) {
7117a570
IS		 2985 if (info->linking)
2986 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
2987 upper_dev);
2988 else
fe3f6d14 2989 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
0d65fc13 2990 } else if (netif_is_lag_master(upper_dev)) {
80bedf1a 2991 if (info->linking)
0d65fc13
JP		 2992 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
2993 upper_dev);
80bedf1a 2994 else
82e6db03
IS		 2995 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
2996 upper_dev);
59fe9b3f
IS		 2997 } else {
2998 err = -EINVAL;
2999 WARN_ON(1);
56ade8fe
JP		 3000 }
3001 break;
3002 }
3003
80bedf1a 3004 return err;
56ade8fe
JP		 3005}
3006
74581206
JP		 3007static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
3008 unsigned long event, void *ptr)
3009{
3010 struct netdev_notifier_changelowerstate_info *info;
3011 struct mlxsw_sp_port *mlxsw_sp_port;
3012 int err;
3013
3014 mlxsw_sp_port = netdev_priv(dev);
3015 info = ptr;
3016
3017 switch (event) {
3018 case NETDEV_CHANGELOWERSTATE:
3019 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3020 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3021 info->lower_state_info);
3022 if (err)
3023 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3024 }
3025 break;
3026 }
3027
80bedf1a 3028 return 0;
74581206
JP		 3029}
3030
3031static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
3032 unsigned long event, void *ptr)
3033{
3034 switch (event) {
3035 case NETDEV_PRECHANGEUPPER:
3036 case NETDEV_CHANGEUPPER:
3037 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
3038 case NETDEV_CHANGELOWERSTATE:
3039 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
3040 }
3041
80bedf1a 3042 return 0;
74581206
JP		 3043}
3044
0d65fc13
JP		 3045static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3046 unsigned long event, void *ptr)
3047{
3048 struct net_device *dev;
3049 struct list_head *iter;
3050 int ret;
3051
3052 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3053 if (mlxsw_sp_port_dev_check(dev)) {
3054 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
80bedf1a 3055 if (ret)
0d65fc13
JP		 3056 return ret;
3057 }
3058 }
3059
80bedf1a 3060 return 0;
0d65fc13
JP		 3061}
3062
d0ec875a 3063static struct mlxsw_sp_fid *
26f0e7fb
IS		 3064mlxsw_sp_br_vfid_find(const struct mlxsw_sp *mlxsw_sp,
3065 const struct net_device *br_dev)
3066{
d0ec875a 3067 struct mlxsw_sp_fid *f;
26f0e7fb 3068
d0ec875a
IS		 3069 list_for_each_entry(f, &mlxsw_sp->br_vfids.list, list) {
3070 if (f->dev == br_dev)
3071 return f;
26f0e7fb
IS		 3072 }
3073
3074 return NULL;
3075}
3076
3077static u16 mlxsw_sp_vfid_to_br_vfid(u16 vfid)
3078{
3079 return vfid - MLXSW_SP_VFID_PORT_MAX;
3080}
3081
3082static u16 mlxsw_sp_br_vfid_to_vfid(u16 br_vfid)
3083{
3084 return MLXSW_SP_VFID_PORT_MAX + br_vfid;
3085}
3086
3087static u16 mlxsw_sp_avail_br_vfid_get(const struct mlxsw_sp *mlxsw_sp)
3088{
3089 return find_first_zero_bit(mlxsw_sp->br_vfids.mapped,
3090 MLXSW_SP_VFID_BR_MAX);
3091}
3092
1c800759
IS		 3093static void mlxsw_sp_vport_br_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
3094
d0ec875a
IS		 3095static struct mlxsw_sp_fid *mlxsw_sp_br_vfid_create(struct mlxsw_sp *mlxsw_sp,
3096 struct net_device *br_dev)
26f0e7fb
IS		 3097{
3098 struct device *dev = mlxsw_sp->bus_info->dev;
d0ec875a 3099 struct mlxsw_sp_fid *f;
c7e920b5 3100 u16 vfid, fid;
26f0e7fb
IS		 3101 int err;
3102
c7e920b5
IS		 3103 vfid = mlxsw_sp_br_vfid_to_vfid(mlxsw_sp_avail_br_vfid_get(mlxsw_sp));
3104 if (vfid == MLXSW_SP_VFID_MAX) {
26f0e7fb
IS		 3105 dev_err(dev, "No available vFIDs\n");
3106 return ERR_PTR(-ERANGE);
3107 }
3108
c7e920b5
IS		 3109 fid = mlxsw_sp_vfid_to_fid(vfid);
3110 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
26f0e7fb 3111 if (err) {
c7e920b5 3112 dev_err(dev, "Failed to create FID=%d\n", fid);
26f0e7fb
IS		 3113 return ERR_PTR(err);
3114 }
3115
c7e920b5
IS		 3116 f = kzalloc(sizeof(*f), GFP_KERNEL);
3117 if (!f)
26f0e7fb
IS		 3118 goto err_allocate_vfid;
3119
1c800759 3120 f->leave = mlxsw_sp_vport_br_vfid_leave;
d0ec875a
IS		 3121 f->fid = fid;
3122 f->dev = br_dev;
26f0e7fb 3123
c7e920b5
IS		 3124 list_add(&f->list, &mlxsw_sp->br_vfids.list);
3125 set_bit(mlxsw_sp_vfid_to_br_vfid(vfid), mlxsw_sp->br_vfids.mapped);
26f0e7fb 3126
c7e920b5 3127 return f;
26f0e7fb
IS		 3128
3129err_allocate_vfid:
c7e920b5 3130 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
26f0e7fb
IS		 3131 return ERR_PTR(-ENOMEM);
3132}
3133
3134static void mlxsw_sp_br_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
d0ec875a 3135 struct mlxsw_sp_fid *f)
26f0e7fb 3136{
d0ec875a
IS		 3137 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
3138 u16 br_vfid = mlxsw_sp_vfid_to_br_vfid(vfid);
26f0e7fb
IS		 3139
3140 clear_bit(br_vfid, mlxsw_sp->br_vfids.mapped);
d0ec875a 3141 list_del(&f->list);
26f0e7fb 3142
d0ec875a 3143 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
26f0e7fb 3144
d0ec875a 3145 kfree(f);
26f0e7fb
IS		 3146}
3147
0355b59f
IS		 3148static int mlxsw_sp_vport_br_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3149 struct net_device *br_dev)
26f0e7fb 3150{
0355b59f 3151 struct mlxsw_sp_fid *f;
26f0e7fb
IS		 3152 int err;
3153
0355b59f
IS		 3154 f = mlxsw_sp_br_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
3155 if (!f) {
3156 f = mlxsw_sp_br_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
3157 if (IS_ERR(f))
3158 return PTR_ERR(f);
26f0e7fb
IS		 3159 }
3160
0355b59f
IS		 3161 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
3162 if (err)
3163 goto err_vport_flood_set;
26f0e7fb 3164
0355b59f
IS		 3165 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
3166 if (err)
9c4d4423 3167 goto err_vport_fid_map;
26f0e7fb 3168
41b996cc 3169 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
0355b59f 3170 f->ref_count++;
6a9863a6 3171
22305378
IS		 3172 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
3173
0355b59f 3174 return 0;
039c49a6 3175
0355b59f
IS		 3176err_vport_fid_map:
3177 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3178err_vport_flood_set:
d0ec875a 3179 if (!f->ref_count)
0355b59f
IS		 3180 mlxsw_sp_br_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
3181 return err;
3182}
26f0e7fb 3183
0355b59f
IS		 3184static void mlxsw_sp_vport_br_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
3185{
41b996cc 3186 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
26f0e7fb 3187
22305378
IS		 3188 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
3189
0355b59f 3190 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
26f0e7fb 3191
0355b59f
IS		 3192 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3193
fe3f6d14
IS		 3194 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
3195
41b996cc 3196 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
0355b59f
IS		 3197 if (--f->ref_count == 0)
3198 mlxsw_sp_br_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
26f0e7fb
IS		 3199}
3200
3201static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3202 struct net_device *br_dev)
3203{
26f0e7fb
IS		 3204 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3205 struct net_device *dev = mlxsw_sp_vport->dev;
26f0e7fb
IS		 3206 int err;
3207
0355b59f 3208 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
26f0e7fb 3209
0355b59f 3210 err = mlxsw_sp_vport_br_vfid_join(mlxsw_sp_vport, br_dev);
26f0e7fb 3211 if (err) {
0355b59f
IS		 3212 netdev_err(dev, "Failed to join vFID\n");
3213 goto err_vport_br_vfid_join;
26f0e7fb
IS		 3214 }
3215
3216 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
3217 if (err) {
3218 netdev_err(dev, "Failed to enable learning\n");
3219 goto err_port_vid_learning_set;
3220 }
3221
26f0e7fb
IS		 3222 mlxsw_sp_vport->learning = 1;
3223 mlxsw_sp_vport->learning_sync = 1;
3224 mlxsw_sp_vport->uc_flood = 1;
3225 mlxsw_sp_vport->bridged = 1;
3226
3227 return 0;
3228
26f0e7fb 3229err_port_vid_learning_set:
0355b59f
IS		 3230 mlxsw_sp_vport_br_vfid_leave(mlxsw_sp_vport);
3231err_vport_br_vfid_join:
3232 mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
26f0e7fb
IS		 3233 return err;
3234}
3235
fe3f6d14 3236static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
0355b59f
IS		 3237{
3238 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
0355b59f
IS		 3239
3240 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3241
3242 mlxsw_sp_vport_br_vfid_leave(mlxsw_sp_vport);
3243
3244 mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
3245
3246 mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
3247 MLXSW_REG_SPMS_STATE_FORWARDING);
3248
0355b59f
IS		 3249 mlxsw_sp_vport->learning = 0;
3250 mlxsw_sp_vport->learning_sync = 0;
3251 mlxsw_sp_vport->uc_flood = 0;
3252 mlxsw_sp_vport->bridged = 0;
3253}
3254
26f0e7fb
IS		 3255static bool
3256mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
3257 const struct net_device *br_dev)
3258{
3259 struct mlxsw_sp_port *mlxsw_sp_vport;
3260
3261 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
3262 vport.list) {
56918b6b
IS		 3263 struct net_device *dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
3264
3265 if (dev && dev == br_dev)
26f0e7fb
IS		 3266 return false;
3267 }
3268
3269 return true;
3270}
3271
3272static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
3273 unsigned long event, void *ptr,
3274 u16 vid)
3275{
3276 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3277 struct netdev_notifier_changeupper_info *info = ptr;
3278 struct mlxsw_sp_port *mlxsw_sp_vport;
3279 struct net_device *upper_dev;
80bedf1a 3280 int err = 0;
26f0e7fb
IS		 3281
3282 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3283
3284 switch (event) {
3285 case NETDEV_PRECHANGEUPPER:
3286 upper_dev = info->upper_dev;
26f0e7fb 3287 if (!netif_is_bridge_master(upper_dev))
80bedf1a 3288 return -EINVAL;
ddbe993d
IS		 3289 if (!info->linking)
3290 break;
26f0e7fb
IS		 3291 /* We can't have multiple VLAN interfaces configured on
3292 * the same port and being members in the same bridge.
3293 */
3294 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
3295 upper_dev))
80bedf1a 3296 return -EINVAL;
26f0e7fb
IS		 3297 break;
3298 case NETDEV_CHANGEUPPER:
3299 upper_dev = info->upper_dev;
26f0e7fb 3300 if (info->linking) {
423b937e 3301 if (WARN_ON(!mlxsw_sp_vport))
80bedf1a 3302 return -EINVAL;
26f0e7fb
IS		 3303 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
3304 upper_dev);
26f0e7fb 3305 } else {
26f0e7fb 3306 if (!mlxsw_sp_vport)
80bedf1a 3307 return 0;
fe3f6d14 3308 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
26f0e7fb
IS		 3309 }
3310 }
3311
80bedf1a 3312 return err;
26f0e7fb
IS		 3313}
3314
272c4470
IS		 3315static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
3316 unsigned long event, void *ptr,
3317 u16 vid)
3318{
3319 struct net_device *dev;
3320 struct list_head *iter;
3321 int ret;
3322
3323 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3324 if (mlxsw_sp_port_dev_check(dev)) {
3325 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
3326 vid);
80bedf1a 3327 if (ret)
272c4470
IS		 3328 return ret;
3329 }
3330 }
3331
80bedf1a 3332 return 0;
272c4470
IS		 3333}
3334
26f0e7fb
IS		 3335static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
3336 unsigned long event, void *ptr)
3337{
3338 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3339 u16 vid = vlan_dev_vlan_id(vlan_dev);
3340
272c4470
IS		 3341 if (mlxsw_sp_port_dev_check(real_dev))
3342 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
3343 vid);
3344 else if (netif_is_lag_master(real_dev))
3345 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
3346 vid);
26f0e7fb 3347
80bedf1a 3348 return 0;
26f0e7fb
IS		 3349}
3350
0d65fc13
JP		 3351static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3352 unsigned long event, void *ptr)
3353{
3354 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
80bedf1a 3355 int err = 0;
0d65fc13
JP		 3356
3357 if (mlxsw_sp_port_dev_check(dev))
80bedf1a
IS		 3358 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3359 else if (netif_is_lag_master(dev))
3360 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
3361 else if (is_vlan_dev(dev))
3362 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
26f0e7fb 3363
80bedf1a 3364 return notifier_from_errno(err);
0d65fc13
JP		 3365}
3366
56ade8fe
JP		 3367static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
3368 .notifier_call = mlxsw_sp_netdevice_event,
3369};
3370
3371static int __init mlxsw_sp_module_init(void)
3372{
3373 int err;
3374
3375 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3376 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
3377 if (err)
3378 goto err_core_driver_register;
3379 return 0;
3380
3381err_core_driver_register:
3382 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3383 return err;
3384}
3385
3386static void __exit mlxsw_sp_module_exit(void)
3387{
3388 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
3389 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3390}
3391
3392module_init(mlxsw_sp_module_init);
3393module_exit(mlxsw_sp_module_exit);
3394
3395MODULE_LICENSE("Dual BSD/GPL");
3396MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
3397MODULE_DESCRIPTION("Mellanox Spectrum driver");
3398MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SPECTRUM);
Linux kernel - Deliverables
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