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56ade8fe JP |
1 | /* |
2 | * drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c | |
3 | * Copyright (c) 2015 Mellanox Technologies. All rights reserved. | |
4 | * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> | |
5 | * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> | |
6 | * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions are met: | |
10 | * | |
11 | * 1. Redistributions of source code must retain the above copyright | |
12 | * notice, this list of conditions and the following disclaimer. | |
13 | * 2. Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in the | |
15 | * documentation and/or other materials provided with the distribution. | |
16 | * 3. Neither the names of the copyright holders nor the names of its | |
17 | * contributors may be used to endorse or promote products derived from | |
18 | * this software without specific prior written permission. | |
19 | * | |
20 | * Alternatively, this software may be distributed under the terms of the | |
21 | * GNU General Public License ("GPL") version 2 as published by the Free | |
22 | * Software Foundation. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
34 | * POSSIBILITY OF SUCH DAMAGE. | |
35 | */ | |
36 | ||
37 | #include <linux/kernel.h> | |
38 | #include <linux/types.h> | |
39 | #include <linux/netdevice.h> | |
40 | #include <linux/etherdevice.h> | |
41 | #include <linux/slab.h> | |
42 | #include <linux/device.h> | |
43 | #include <linux/skbuff.h> | |
44 | #include <linux/if_vlan.h> | |
45 | #include <linux/if_bridge.h> | |
46 | #include <linux/workqueue.h> | |
47 | #include <linux/jiffies.h> | |
48 | #include <net/switchdev.h> | |
49 | ||
50 | #include "spectrum.h" | |
51 | #include "core.h" | |
52 | #include "reg.h" | |
53 | ||
54 | static int mlxsw_sp_port_attr_get(struct net_device *dev, | |
55 | struct switchdev_attr *attr) | |
56 | { | |
57 | struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); | |
58 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
59 | ||
60 | switch (attr->id) { | |
61 | case SWITCHDEV_ATTR_ID_PORT_PARENT_ID: | |
62 | attr->u.ppid.id_len = sizeof(mlxsw_sp->base_mac); | |
63 | memcpy(&attr->u.ppid.id, &mlxsw_sp->base_mac, | |
64 | attr->u.ppid.id_len); | |
65 | break; | |
66 | case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS: | |
67 | attr->u.brport_flags = | |
68 | (mlxsw_sp_port->learning ? BR_LEARNING : 0) | | |
0293038e IS |
69 | (mlxsw_sp_port->learning_sync ? BR_LEARNING_SYNC : 0) | |
70 | (mlxsw_sp_port->uc_flood ? BR_FLOOD : 0); | |
56ade8fe JP |
71 | break; |
72 | default: | |
73 | return -EOPNOTSUPP; | |
74 | } | |
75 | ||
76 | return 0; | |
77 | } | |
78 | ||
79 | static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port, | |
80 | u8 state) | |
81 | { | |
82 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
83 | enum mlxsw_reg_spms_state spms_state; | |
84 | char *spms_pl; | |
85 | u16 vid; | |
86 | int err; | |
87 | ||
88 | switch (state) { | |
89 | case BR_STATE_DISABLED: /* fall-through */ | |
90 | case BR_STATE_FORWARDING: | |
91 | spms_state = MLXSW_REG_SPMS_STATE_FORWARDING; | |
92 | break; | |
93 | case BR_STATE_LISTENING: /* fall-through */ | |
94 | case BR_STATE_LEARNING: | |
95 | spms_state = MLXSW_REG_SPMS_STATE_LEARNING; | |
96 | break; | |
97 | case BR_STATE_BLOCKING: | |
98 | spms_state = MLXSW_REG_SPMS_STATE_DISCARDING; | |
99 | break; | |
100 | default: | |
101 | BUG(); | |
102 | } | |
103 | ||
104 | spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); | |
105 | if (!spms_pl) | |
106 | return -ENOMEM; | |
107 | mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); | |
108 | for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) | |
109 | mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); | |
110 | ||
111 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); | |
112 | kfree(spms_pl); | |
113 | return err; | |
114 | } | |
115 | ||
116 | static int mlxsw_sp_port_attr_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port, | |
117 | struct switchdev_trans *trans, | |
118 | u8 state) | |
119 | { | |
120 | if (switchdev_trans_ph_prepare(trans)) | |
121 | return 0; | |
122 | ||
123 | mlxsw_sp_port->stp_state = state; | |
124 | return mlxsw_sp_port_stp_state_set(mlxsw_sp_port, state); | |
125 | } | |
126 | ||
0293038e IS |
127 | static int __mlxsw_sp_port_flood_set(struct mlxsw_sp_port *mlxsw_sp_port, |
128 | u16 fid_begin, u16 fid_end, bool set, | |
129 | bool only_uc) | |
130 | { | |
131 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
132 | u16 range = fid_end - fid_begin + 1; | |
133 | char *sftr_pl; | |
134 | int err; | |
135 | ||
136 | sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL); | |
137 | if (!sftr_pl) | |
138 | return -ENOMEM; | |
139 | ||
140 | mlxsw_reg_sftr_pack(sftr_pl, MLXSW_SP_FLOOD_TABLE_UC, fid_begin, | |
141 | MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST, range, | |
142 | mlxsw_sp_port->local_port, set); | |
143 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sftr), sftr_pl); | |
144 | if (err) | |
145 | goto buffer_out; | |
146 | ||
147 | /* Flooding control allows one to decide whether a given port will | |
148 | * flood unicast traffic for which there is no FDB entry. | |
149 | */ | |
150 | if (only_uc) | |
151 | goto buffer_out; | |
152 | ||
153 | mlxsw_reg_sftr_pack(sftr_pl, MLXSW_SP_FLOOD_TABLE_BM, fid_begin, | |
154 | MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST, range, | |
155 | mlxsw_sp_port->local_port, set); | |
156 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sftr), sftr_pl); | |
157 | ||
158 | buffer_out: | |
159 | kfree(sftr_pl); | |
160 | return err; | |
161 | } | |
162 | ||
163 | static int mlxsw_sp_port_uc_flood_set(struct mlxsw_sp_port *mlxsw_sp_port, | |
164 | bool set) | |
165 | { | |
166 | struct net_device *dev = mlxsw_sp_port->dev; | |
167 | u16 vid, last_visited_vid; | |
168 | int err; | |
169 | ||
170 | for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) { | |
171 | err = __mlxsw_sp_port_flood_set(mlxsw_sp_port, vid, vid, set, | |
172 | true); | |
173 | if (err) { | |
174 | last_visited_vid = vid; | |
175 | goto err_port_flood_set; | |
176 | } | |
177 | } | |
178 | ||
179 | return 0; | |
180 | ||
181 | err_port_flood_set: | |
182 | for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid) | |
183 | __mlxsw_sp_port_flood_set(mlxsw_sp_port, vid, vid, !set, true); | |
184 | netdev_err(dev, "Failed to configure unicast flooding\n"); | |
185 | return err; | |
186 | } | |
187 | ||
56ade8fe JP |
188 | static int mlxsw_sp_port_attr_br_flags_set(struct mlxsw_sp_port *mlxsw_sp_port, |
189 | struct switchdev_trans *trans, | |
190 | unsigned long brport_flags) | |
191 | { | |
0293038e IS |
192 | unsigned long uc_flood = mlxsw_sp_port->uc_flood ? BR_FLOOD : 0; |
193 | bool set; | |
194 | int err; | |
195 | ||
56ade8fe JP |
196 | if (switchdev_trans_ph_prepare(trans)) |
197 | return 0; | |
198 | ||
0293038e IS |
199 | if ((uc_flood ^ brport_flags) & BR_FLOOD) { |
200 | set = mlxsw_sp_port->uc_flood ? false : true; | |
201 | err = mlxsw_sp_port_uc_flood_set(mlxsw_sp_port, set); | |
202 | if (err) | |
203 | return err; | |
204 | } | |
205 | ||
206 | mlxsw_sp_port->uc_flood = brport_flags & BR_FLOOD ? 1 : 0; | |
56ade8fe JP |
207 | mlxsw_sp_port->learning = brport_flags & BR_LEARNING ? 1 : 0; |
208 | mlxsw_sp_port->learning_sync = brport_flags & BR_LEARNING_SYNC ? 1 : 0; | |
0293038e | 209 | |
56ade8fe JP |
210 | return 0; |
211 | } | |
212 | ||
213 | static int mlxsw_sp_ageing_set(struct mlxsw_sp *mlxsw_sp, u32 ageing_time) | |
214 | { | |
215 | char sfdat_pl[MLXSW_REG_SFDAT_LEN]; | |
216 | int err; | |
217 | ||
218 | mlxsw_reg_sfdat_pack(sfdat_pl, ageing_time); | |
219 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdat), sfdat_pl); | |
220 | if (err) | |
221 | return err; | |
222 | mlxsw_sp->ageing_time = ageing_time; | |
223 | return 0; | |
224 | } | |
225 | ||
226 | static int mlxsw_sp_port_attr_br_ageing_set(struct mlxsw_sp_port *mlxsw_sp_port, | |
227 | struct switchdev_trans *trans, | |
135f9ece | 228 | unsigned long ageing_clock_t) |
56ade8fe JP |
229 | { |
230 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
135f9ece | 231 | unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); |
56ade8fe JP |
232 | u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; |
233 | ||
234 | if (switchdev_trans_ph_prepare(trans)) | |
235 | return 0; | |
236 | ||
237 | return mlxsw_sp_ageing_set(mlxsw_sp, ageing_time); | |
238 | } | |
239 | ||
240 | static int mlxsw_sp_port_attr_set(struct net_device *dev, | |
241 | const struct switchdev_attr *attr, | |
242 | struct switchdev_trans *trans) | |
243 | { | |
244 | struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); | |
245 | int err = 0; | |
246 | ||
247 | switch (attr->id) { | |
248 | case SWITCHDEV_ATTR_ID_PORT_STP_STATE: | |
249 | err = mlxsw_sp_port_attr_stp_state_set(mlxsw_sp_port, trans, | |
250 | attr->u.stp_state); | |
251 | break; | |
252 | case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS: | |
253 | err = mlxsw_sp_port_attr_br_flags_set(mlxsw_sp_port, trans, | |
254 | attr->u.brport_flags); | |
255 | break; | |
256 | case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: | |
257 | err = mlxsw_sp_port_attr_br_ageing_set(mlxsw_sp_port, trans, | |
258 | attr->u.ageing_time); | |
259 | break; | |
260 | default: | |
261 | err = -EOPNOTSUPP; | |
262 | break; | |
263 | } | |
264 | ||
265 | return err; | |
266 | } | |
267 | ||
268 | static int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) | |
269 | { | |
270 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
271 | char spvid_pl[MLXSW_REG_SPVID_LEN]; | |
272 | ||
273 | mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid); | |
274 | return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); | |
275 | } | |
276 | ||
277 | static int mlxsw_sp_fid_create(struct mlxsw_sp *mlxsw_sp, u16 fid) | |
278 | { | |
279 | char sfmr_pl[MLXSW_REG_SFMR_LEN]; | |
280 | int err; | |
281 | ||
282 | mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_CREATE_FID, fid, fid); | |
283 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl); | |
284 | ||
285 | if (err) | |
286 | return err; | |
287 | ||
288 | set_bit(fid, mlxsw_sp->active_fids); | |
289 | return 0; | |
290 | } | |
291 | ||
292 | static void mlxsw_sp_fid_destroy(struct mlxsw_sp *mlxsw_sp, u16 fid) | |
293 | { | |
294 | char sfmr_pl[MLXSW_REG_SFMR_LEN]; | |
295 | ||
296 | clear_bit(fid, mlxsw_sp->active_fids); | |
297 | ||
298 | mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_DESTROY_FID, | |
299 | fid, fid); | |
300 | mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl); | |
301 | } | |
302 | ||
303 | static int mlxsw_sp_port_fid_map(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid) | |
304 | { | |
305 | enum mlxsw_reg_svfa_mt mt; | |
306 | ||
307 | if (mlxsw_sp_port->nr_vfids) | |
308 | mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; | |
309 | else | |
310 | mt = MLXSW_REG_SVFA_MT_VID_TO_FID; | |
311 | ||
312 | return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, fid, fid); | |
313 | } | |
314 | ||
315 | static int mlxsw_sp_port_fid_unmap(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid) | |
316 | { | |
317 | enum mlxsw_reg_svfa_mt mt; | |
318 | ||
319 | if (!mlxsw_sp_port->nr_vfids) | |
320 | return 0; | |
321 | ||
322 | mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; | |
323 | return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, fid, fid); | |
324 | } | |
325 | ||
56ade8fe JP |
326 | static int mlxsw_sp_port_add_vids(struct net_device *dev, u16 vid_begin, |
327 | u16 vid_end) | |
328 | { | |
329 | u16 vid; | |
330 | int err; | |
331 | ||
332 | for (vid = vid_begin; vid <= vid_end; vid++) { | |
333 | err = mlxsw_sp_port_add_vid(dev, 0, vid); | |
334 | if (err) | |
335 | goto err_port_add_vid; | |
336 | } | |
337 | return 0; | |
338 | ||
339 | err_port_add_vid: | |
340 | for (vid--; vid >= vid_begin; vid--) | |
341 | mlxsw_sp_port_kill_vid(dev, 0, vid); | |
342 | return err; | |
343 | } | |
344 | ||
3b7ad5ec IS |
345 | static int __mlxsw_sp_port_vlans_set(struct mlxsw_sp_port *mlxsw_sp_port, |
346 | u16 vid_begin, u16 vid_end, bool is_member, | |
347 | bool untagged) | |
348 | { | |
349 | u16 vid, vid_e; | |
350 | int err; | |
351 | ||
352 | for (vid = vid_begin; vid <= vid_end; | |
353 | vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { | |
354 | vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), | |
355 | vid_end); | |
356 | ||
357 | err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, | |
358 | is_member, untagged); | |
359 | if (err) | |
360 | return err; | |
361 | } | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
56ade8fe JP |
366 | static int __mlxsw_sp_port_vlans_add(struct mlxsw_sp_port *mlxsw_sp_port, |
367 | u16 vid_begin, u16 vid_end, | |
368 | bool flag_untagged, bool flag_pvid) | |
369 | { | |
370 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
371 | struct net_device *dev = mlxsw_sp_port->dev; | |
b07a966c | 372 | u16 vid, last_visited_vid, old_pvid; |
56ade8fe | 373 | enum mlxsw_reg_svfa_mt mt; |
56ade8fe JP |
374 | int err; |
375 | ||
376 | /* In case this is invoked with BRIDGE_FLAGS_SELF and port is | |
377 | * not bridged, then packets ingressing through the port with | |
378 | * the specified VIDs will be directed to CPU. | |
379 | */ | |
380 | if (!mlxsw_sp_port->bridged) | |
381 | return mlxsw_sp_port_add_vids(dev, vid_begin, vid_end); | |
382 | ||
383 | for (vid = vid_begin; vid <= vid_end; vid++) { | |
384 | if (!test_bit(vid, mlxsw_sp->active_fids)) { | |
385 | err = mlxsw_sp_fid_create(mlxsw_sp, vid); | |
386 | if (err) { | |
387 | netdev_err(dev, "Failed to create FID=%d\n", | |
388 | vid); | |
389 | return err; | |
390 | } | |
391 | ||
392 | /* When creating a FID, we set a VID to FID mapping | |
393 | * regardless of the port's mode. | |
394 | */ | |
395 | mt = MLXSW_REG_SVFA_MT_VID_TO_FID; | |
396 | err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, | |
397 | true, vid, vid); | |
398 | if (err) { | |
399 | netdev_err(dev, "Failed to create FID=VID=%d mapping\n", | |
400 | vid); | |
b07a966c | 401 | goto err_port_vid_to_fid_set; |
56ade8fe JP |
402 | } |
403 | } | |
b07a966c | 404 | } |
56ade8fe | 405 | |
b07a966c IS |
406 | /* Set FID mapping according to port's mode */ |
407 | for (vid = vid_begin; vid <= vid_end; vid++) { | |
56ade8fe JP |
408 | err = mlxsw_sp_port_fid_map(mlxsw_sp_port, vid); |
409 | if (err) { | |
410 | netdev_err(dev, "Failed to map FID=%d", vid); | |
b07a966c IS |
411 | last_visited_vid = --vid; |
412 | goto err_port_fid_map; | |
56ade8fe | 413 | } |
1b3433a9 | 414 | } |
56ade8fe | 415 | |
1b3433a9 IS |
416 | err = __mlxsw_sp_port_flood_set(mlxsw_sp_port, vid_begin, vid_end, |
417 | true, false); | |
418 | if (err) { | |
419 | netdev_err(dev, "Failed to configure flooding\n"); | |
b07a966c | 420 | goto err_port_flood_set; |
56ade8fe JP |
421 | } |
422 | ||
3b7ad5ec IS |
423 | err = __mlxsw_sp_port_vlans_set(mlxsw_sp_port, vid_begin, vid_end, |
424 | true, flag_untagged); | |
425 | if (err) { | |
426 | netdev_err(dev, "Unable to add VIDs %d-%d\n", vid_begin, | |
427 | vid_end); | |
b07a966c | 428 | goto err_port_vlans_set; |
56ade8fe JP |
429 | } |
430 | ||
b07a966c IS |
431 | old_pvid = mlxsw_sp_port->pvid; |
432 | if (flag_pvid && old_pvid != vid_begin) { | |
433 | err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid_begin); | |
56ade8fe | 434 | if (err) { |
b07a966c IS |
435 | netdev_err(dev, "Unable to add PVID %d\n", vid_begin); |
436 | goto err_port_pvid_set; | |
56ade8fe | 437 | } |
b07a966c | 438 | mlxsw_sp_port->pvid = vid_begin; |
56ade8fe JP |
439 | } |
440 | ||
441 | /* Changing activity bits only if HW operation succeded */ | |
442 | for (vid = vid_begin; vid <= vid_end; vid++) | |
443 | set_bit(vid, mlxsw_sp_port->active_vlans); | |
444 | ||
b07a966c IS |
445 | /* STP state change must be done after we set active VLANs */ |
446 | err = mlxsw_sp_port_stp_state_set(mlxsw_sp_port, | |
447 | mlxsw_sp_port->stp_state); | |
448 | if (err) { | |
449 | netdev_err(dev, "Failed to set STP state\n"); | |
450 | goto err_port_stp_state_set; | |
451 | } | |
452 | ||
453 | return 0; | |
454 | ||
455 | err_port_vid_to_fid_set: | |
456 | mlxsw_sp_fid_destroy(mlxsw_sp, vid); | |
457 | return err; | |
458 | ||
459 | err_port_stp_state_set: | |
460 | for (vid = vid_begin; vid <= vid_end; vid++) | |
461 | clear_bit(vid, mlxsw_sp_port->active_vlans); | |
462 | if (old_pvid != mlxsw_sp_port->pvid) | |
463 | mlxsw_sp_port_pvid_set(mlxsw_sp_port, old_pvid); | |
464 | err_port_pvid_set: | |
465 | __mlxsw_sp_port_vlans_set(mlxsw_sp_port, vid_begin, vid_end, false, | |
466 | false); | |
467 | err_port_vlans_set: | |
468 | __mlxsw_sp_port_flood_set(mlxsw_sp_port, vid_begin, vid_end, false, | |
469 | false); | |
470 | err_port_flood_set: | |
471 | last_visited_vid = vid_end; | |
472 | err_port_fid_map: | |
473 | for (vid = last_visited_vid; vid >= vid_begin; vid--) | |
474 | mlxsw_sp_port_fid_unmap(mlxsw_sp_port, vid); | |
475 | return err; | |
56ade8fe JP |
476 | } |
477 | ||
478 | static int mlxsw_sp_port_vlans_add(struct mlxsw_sp_port *mlxsw_sp_port, | |
479 | const struct switchdev_obj_port_vlan *vlan, | |
480 | struct switchdev_trans *trans) | |
481 | { | |
482 | bool untagged_flag = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; | |
483 | bool pvid_flag = vlan->flags & BRIDGE_VLAN_INFO_PVID; | |
484 | ||
485 | if (switchdev_trans_ph_prepare(trans)) | |
486 | return 0; | |
487 | ||
488 | return __mlxsw_sp_port_vlans_add(mlxsw_sp_port, | |
489 | vlan->vid_begin, vlan->vid_end, | |
490 | untagged_flag, pvid_flag); | |
491 | } | |
492 | ||
8a1ab5d7 | 493 | static enum mlxsw_reg_sfd_rec_policy mlxsw_sp_sfd_rec_policy(bool dynamic) |
56ade8fe | 494 | { |
8a1ab5d7 JP |
495 | return dynamic ? MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS : |
496 | MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY; | |
497 | } | |
498 | ||
499 | static enum mlxsw_reg_sfd_op mlxsw_sp_sfd_op(bool adding) | |
500 | { | |
501 | return adding ? MLXSW_REG_SFD_OP_WRITE_EDIT : | |
502 | MLXSW_REG_SFD_OP_WRITE_REMOVE; | |
503 | } | |
504 | ||
505 | static int mlxsw_sp_port_fdb_uc_op(struct mlxsw_sp_port *mlxsw_sp_port, | |
506 | const char *mac, u16 vid, bool adding, | |
507 | bool dynamic) | |
508 | { | |
509 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
56ade8fe JP |
510 | char *sfd_pl; |
511 | int err; | |
512 | ||
56ade8fe JP |
513 | sfd_pl = kmalloc(MLXSW_REG_SFD_LEN, GFP_KERNEL); |
514 | if (!sfd_pl) | |
515 | return -ENOMEM; | |
516 | ||
8a1ab5d7 JP |
517 | mlxsw_reg_sfd_pack(sfd_pl, mlxsw_sp_sfd_op(adding), 0); |
518 | mlxsw_reg_sfd_uc_pack(sfd_pl, 0, mlxsw_sp_sfd_rec_policy(dynamic), | |
56ade8fe JP |
519 | mac, vid, MLXSW_REG_SFD_REC_ACTION_NOP, |
520 | mlxsw_sp_port->local_port); | |
8a1ab5d7 JP |
521 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfd), sfd_pl); |
522 | kfree(sfd_pl); | |
523 | ||
524 | return err; | |
525 | } | |
526 | ||
527 | static int mlxsw_sp_port_fdb_uc_lag_op(struct mlxsw_sp *mlxsw_sp, u16 lag_id, | |
528 | const char *mac, u16 vid, bool adding, | |
529 | bool dynamic) | |
530 | { | |
531 | char *sfd_pl; | |
532 | int err; | |
533 | ||
534 | sfd_pl = kmalloc(MLXSW_REG_SFD_LEN, GFP_KERNEL); | |
535 | if (!sfd_pl) | |
536 | return -ENOMEM; | |
537 | ||
538 | mlxsw_reg_sfd_pack(sfd_pl, mlxsw_sp_sfd_op(adding), 0); | |
539 | mlxsw_reg_sfd_uc_lag_pack(sfd_pl, 0, mlxsw_sp_sfd_rec_policy(dynamic), | |
540 | mac, vid, MLXSW_REG_SFD_REC_ACTION_NOP, | |
541 | lag_id); | |
542 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfd), sfd_pl); | |
56ade8fe JP |
543 | kfree(sfd_pl); |
544 | ||
545 | return err; | |
546 | } | |
547 | ||
548 | static int | |
549 | mlxsw_sp_port_fdb_static_add(struct mlxsw_sp_port *mlxsw_sp_port, | |
550 | const struct switchdev_obj_port_fdb *fdb, | |
551 | struct switchdev_trans *trans) | |
552 | { | |
8a1ab5d7 JP |
553 | u16 vid = fdb->vid; |
554 | ||
56ade8fe JP |
555 | if (switchdev_trans_ph_prepare(trans)) |
556 | return 0; | |
557 | ||
8a1ab5d7 JP |
558 | if (!vid) |
559 | vid = mlxsw_sp_port->pvid; | |
560 | ||
561 | if (!mlxsw_sp_port->lagged) | |
562 | return mlxsw_sp_port_fdb_uc_op(mlxsw_sp_port, | |
563 | fdb->addr, vid, true, false); | |
564 | else | |
565 | return mlxsw_sp_port_fdb_uc_lag_op(mlxsw_sp_port->mlxsw_sp, | |
566 | mlxsw_sp_port->lag_id, | |
567 | fdb->addr, vid, true, false); | |
56ade8fe JP |
568 | } |
569 | ||
570 | static int mlxsw_sp_port_obj_add(struct net_device *dev, | |
571 | const struct switchdev_obj *obj, | |
572 | struct switchdev_trans *trans) | |
573 | { | |
574 | struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); | |
575 | int err = 0; | |
576 | ||
577 | switch (obj->id) { | |
578 | case SWITCHDEV_OBJ_ID_PORT_VLAN: | |
579 | err = mlxsw_sp_port_vlans_add(mlxsw_sp_port, | |
580 | SWITCHDEV_OBJ_PORT_VLAN(obj), | |
581 | trans); | |
582 | break; | |
583 | case SWITCHDEV_OBJ_ID_PORT_FDB: | |
584 | err = mlxsw_sp_port_fdb_static_add(mlxsw_sp_port, | |
585 | SWITCHDEV_OBJ_PORT_FDB(obj), | |
586 | trans); | |
587 | break; | |
588 | default: | |
589 | err = -EOPNOTSUPP; | |
590 | break; | |
591 | } | |
592 | ||
593 | return err; | |
594 | } | |
595 | ||
596 | static int mlxsw_sp_port_kill_vids(struct net_device *dev, u16 vid_begin, | |
597 | u16 vid_end) | |
598 | { | |
599 | u16 vid; | |
600 | int err; | |
601 | ||
602 | for (vid = vid_begin; vid <= vid_end; vid++) { | |
603 | err = mlxsw_sp_port_kill_vid(dev, 0, vid); | |
604 | if (err) | |
605 | return err; | |
606 | } | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
611 | static int __mlxsw_sp_port_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port, | |
612 | u16 vid_begin, u16 vid_end, bool init) | |
613 | { | |
614 | struct net_device *dev = mlxsw_sp_port->dev; | |
3b7ad5ec | 615 | u16 vid, pvid; |
56ade8fe JP |
616 | int err; |
617 | ||
618 | /* In case this is invoked with BRIDGE_FLAGS_SELF and port is | |
619 | * not bridged, then prevent packets ingressing through the | |
620 | * port with the specified VIDs from being trapped to CPU. | |
621 | */ | |
622 | if (!init && !mlxsw_sp_port->bridged) | |
623 | return mlxsw_sp_port_kill_vids(dev, vid_begin, vid_end); | |
624 | ||
3b7ad5ec IS |
625 | err = __mlxsw_sp_port_vlans_set(mlxsw_sp_port, vid_begin, vid_end, |
626 | false, false); | |
627 | if (err) { | |
628 | netdev_err(dev, "Unable to del VIDs %d-%d\n", vid_begin, | |
629 | vid_end); | |
630 | return err; | |
56ade8fe JP |
631 | } |
632 | ||
06c071f6 IS |
633 | pvid = mlxsw_sp_port->pvid; |
634 | if (pvid >= vid_begin && pvid <= vid_end && pvid != 1) { | |
56ade8fe | 635 | /* Default VLAN is always 1 */ |
06c071f6 | 636 | err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1); |
56ade8fe | 637 | if (err) { |
06c071f6 | 638 | netdev_err(dev, "Unable to del PVID %d\n", pvid); |
56ade8fe JP |
639 | return err; |
640 | } | |
06c071f6 | 641 | mlxsw_sp_port->pvid = 1; |
56ade8fe JP |
642 | } |
643 | ||
644 | if (init) | |
645 | goto out; | |
646 | ||
1b3433a9 IS |
647 | err = __mlxsw_sp_port_flood_set(mlxsw_sp_port, vid_begin, vid_end, |
648 | false, false); | |
649 | if (err) { | |
650 | netdev_err(dev, "Failed to clear flooding\n"); | |
651 | return err; | |
652 | } | |
56ade8fe | 653 | |
1b3433a9 | 654 | for (vid = vid_begin; vid <= vid_end; vid++) { |
56ade8fe JP |
655 | /* Remove FID mapping in case of Virtual mode */ |
656 | err = mlxsw_sp_port_fid_unmap(mlxsw_sp_port, vid); | |
657 | if (err) { | |
658 | netdev_err(dev, "Failed to unmap FID=%d", vid); | |
659 | return err; | |
660 | } | |
661 | } | |
662 | ||
663 | out: | |
664 | /* Changing activity bits only if HW operation succeded */ | |
665 | for (vid = vid_begin; vid <= vid_end; vid++) | |
666 | clear_bit(vid, mlxsw_sp_port->active_vlans); | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
671 | static int mlxsw_sp_port_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port, | |
672 | const struct switchdev_obj_port_vlan *vlan) | |
673 | { | |
674 | return __mlxsw_sp_port_vlans_del(mlxsw_sp_port, | |
675 | vlan->vid_begin, vlan->vid_end, false); | |
676 | } | |
677 | ||
678 | static int | |
679 | mlxsw_sp_port_fdb_static_del(struct mlxsw_sp_port *mlxsw_sp_port, | |
680 | const struct switchdev_obj_port_fdb *fdb) | |
681 | { | |
8a1ab5d7 JP |
682 | if (!mlxsw_sp_port->lagged) |
683 | return mlxsw_sp_port_fdb_uc_op(mlxsw_sp_port, | |
684 | fdb->addr, fdb->vid, | |
685 | false, false); | |
686 | else | |
687 | return mlxsw_sp_port_fdb_uc_lag_op(mlxsw_sp_port->mlxsw_sp, | |
688 | mlxsw_sp_port->lag_id, | |
689 | fdb->addr, fdb->vid, | |
690 | false, false); | |
56ade8fe JP |
691 | } |
692 | ||
693 | static int mlxsw_sp_port_obj_del(struct net_device *dev, | |
694 | const struct switchdev_obj *obj) | |
695 | { | |
696 | struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); | |
697 | int err = 0; | |
698 | ||
699 | switch (obj->id) { | |
700 | case SWITCHDEV_OBJ_ID_PORT_VLAN: | |
701 | err = mlxsw_sp_port_vlans_del(mlxsw_sp_port, | |
702 | SWITCHDEV_OBJ_PORT_VLAN(obj)); | |
703 | break; | |
704 | case SWITCHDEV_OBJ_ID_PORT_FDB: | |
705 | err = mlxsw_sp_port_fdb_static_del(mlxsw_sp_port, | |
706 | SWITCHDEV_OBJ_PORT_FDB(obj)); | |
707 | break; | |
708 | default: | |
709 | err = -EOPNOTSUPP; | |
710 | break; | |
711 | } | |
712 | ||
713 | return err; | |
714 | } | |
715 | ||
8a1ab5d7 JP |
716 | static struct mlxsw_sp_port *mlxsw_sp_lag_rep_port(struct mlxsw_sp *mlxsw_sp, |
717 | u16 lag_id) | |
718 | { | |
719 | struct mlxsw_sp_port *mlxsw_sp_port; | |
720 | int i; | |
721 | ||
722 | for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) { | |
723 | mlxsw_sp_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i); | |
724 | if (mlxsw_sp_port) | |
725 | return mlxsw_sp_port; | |
726 | } | |
727 | return NULL; | |
728 | } | |
729 | ||
56ade8fe JP |
730 | static int mlxsw_sp_port_fdb_dump(struct mlxsw_sp_port *mlxsw_sp_port, |
731 | struct switchdev_obj_port_fdb *fdb, | |
732 | switchdev_obj_dump_cb_t *cb) | |
733 | { | |
8a1ab5d7 | 734 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; |
56ade8fe JP |
735 | char *sfd_pl; |
736 | char mac[ETH_ALEN]; | |
737 | u16 vid; | |
738 | u8 local_port; | |
8a1ab5d7 | 739 | u16 lag_id; |
56ade8fe JP |
740 | u8 num_rec; |
741 | int stored_err = 0; | |
742 | int i; | |
743 | int err; | |
744 | ||
745 | sfd_pl = kmalloc(MLXSW_REG_SFD_LEN, GFP_KERNEL); | |
746 | if (!sfd_pl) | |
747 | return -ENOMEM; | |
748 | ||
749 | mlxsw_reg_sfd_pack(sfd_pl, MLXSW_REG_SFD_OP_QUERY_DUMP, 0); | |
750 | do { | |
751 | mlxsw_reg_sfd_num_rec_set(sfd_pl, MLXSW_REG_SFD_REC_MAX_COUNT); | |
8a1ab5d7 | 752 | err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(sfd), sfd_pl); |
56ade8fe JP |
753 | if (err) |
754 | goto out; | |
755 | ||
756 | num_rec = mlxsw_reg_sfd_num_rec_get(sfd_pl); | |
757 | ||
758 | /* Even in case of error, we have to run the dump to the end | |
759 | * so the session in firmware is finished. | |
760 | */ | |
761 | if (stored_err) | |
762 | continue; | |
763 | ||
764 | for (i = 0; i < num_rec; i++) { | |
765 | switch (mlxsw_reg_sfd_rec_type_get(sfd_pl, i)) { | |
766 | case MLXSW_REG_SFD_REC_TYPE_UNICAST: | |
767 | mlxsw_reg_sfd_uc_unpack(sfd_pl, i, mac, &vid, | |
768 | &local_port); | |
769 | if (local_port == mlxsw_sp_port->local_port) { | |
770 | ether_addr_copy(fdb->addr, mac); | |
771 | fdb->ndm_state = NUD_REACHABLE; | |
772 | fdb->vid = vid; | |
773 | err = cb(&fdb->obj); | |
774 | if (err) | |
775 | stored_err = err; | |
776 | } | |
8a1ab5d7 JP |
777 | break; |
778 | case MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG: | |
779 | mlxsw_reg_sfd_uc_lag_unpack(sfd_pl, i, | |
780 | mac, &vid, &lag_id); | |
781 | if (mlxsw_sp_port == | |
782 | mlxsw_sp_lag_rep_port(mlxsw_sp, lag_id)) { | |
783 | ether_addr_copy(fdb->addr, mac); | |
784 | fdb->ndm_state = NUD_REACHABLE; | |
785 | fdb->vid = vid; | |
786 | err = cb(&fdb->obj); | |
787 | if (err) | |
788 | stored_err = err; | |
789 | } | |
790 | break; | |
56ade8fe JP |
791 | } |
792 | } | |
793 | } while (num_rec == MLXSW_REG_SFD_REC_MAX_COUNT); | |
794 | ||
795 | out: | |
796 | kfree(sfd_pl); | |
797 | return stored_err ? stored_err : err; | |
798 | } | |
799 | ||
800 | static int mlxsw_sp_port_vlan_dump(struct mlxsw_sp_port *mlxsw_sp_port, | |
801 | struct switchdev_obj_port_vlan *vlan, | |
802 | switchdev_obj_dump_cb_t *cb) | |
803 | { | |
804 | u16 vid; | |
805 | int err = 0; | |
806 | ||
807 | for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) { | |
808 | vlan->flags = 0; | |
809 | if (vid == mlxsw_sp_port->pvid) | |
810 | vlan->flags |= BRIDGE_VLAN_INFO_PVID; | |
811 | vlan->vid_begin = vid; | |
812 | vlan->vid_end = vid; | |
813 | err = cb(&vlan->obj); | |
814 | if (err) | |
815 | break; | |
816 | } | |
817 | return err; | |
818 | } | |
819 | ||
820 | static int mlxsw_sp_port_obj_dump(struct net_device *dev, | |
821 | struct switchdev_obj *obj, | |
822 | switchdev_obj_dump_cb_t *cb) | |
823 | { | |
824 | struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); | |
825 | int err = 0; | |
826 | ||
827 | switch (obj->id) { | |
828 | case SWITCHDEV_OBJ_ID_PORT_VLAN: | |
829 | err = mlxsw_sp_port_vlan_dump(mlxsw_sp_port, | |
830 | SWITCHDEV_OBJ_PORT_VLAN(obj), cb); | |
831 | break; | |
832 | case SWITCHDEV_OBJ_ID_PORT_FDB: | |
833 | err = mlxsw_sp_port_fdb_dump(mlxsw_sp_port, | |
834 | SWITCHDEV_OBJ_PORT_FDB(obj), cb); | |
835 | break; | |
836 | default: | |
837 | err = -EOPNOTSUPP; | |
838 | break; | |
839 | } | |
840 | ||
841 | return err; | |
842 | } | |
843 | ||
c7070fc4 | 844 | static const struct switchdev_ops mlxsw_sp_port_switchdev_ops = { |
56ade8fe JP |
845 | .switchdev_port_attr_get = mlxsw_sp_port_attr_get, |
846 | .switchdev_port_attr_set = mlxsw_sp_port_attr_set, | |
847 | .switchdev_port_obj_add = mlxsw_sp_port_obj_add, | |
848 | .switchdev_port_obj_del = mlxsw_sp_port_obj_del, | |
849 | .switchdev_port_obj_dump = mlxsw_sp_port_obj_dump, | |
850 | }; | |
851 | ||
8a1ab5d7 JP |
852 | static void mlxsw_sp_fdb_call_notifiers(bool learning, bool learning_sync, |
853 | bool adding, char *mac, u16 vid, | |
854 | struct net_device *dev) | |
855 | { | |
856 | struct switchdev_notifier_fdb_info info; | |
857 | unsigned long notifier_type; | |
858 | ||
859 | if (learning && learning_sync) { | |
860 | info.addr = mac; | |
861 | info.vid = vid; | |
862 | notifier_type = adding ? SWITCHDEV_FDB_ADD : SWITCHDEV_FDB_DEL; | |
863 | call_switchdev_notifiers(notifier_type, dev, &info.info); | |
864 | } | |
865 | } | |
866 | ||
56ade8fe JP |
867 | static void mlxsw_sp_fdb_notify_mac_process(struct mlxsw_sp *mlxsw_sp, |
868 | char *sfn_pl, int rec_index, | |
869 | bool adding) | |
870 | { | |
871 | struct mlxsw_sp_port *mlxsw_sp_port; | |
872 | char mac[ETH_ALEN]; | |
873 | u8 local_port; | |
874 | u16 vid; | |
875 | int err; | |
876 | ||
877 | mlxsw_reg_sfn_mac_unpack(sfn_pl, rec_index, mac, &vid, &local_port); | |
878 | mlxsw_sp_port = mlxsw_sp->ports[local_port]; | |
879 | if (!mlxsw_sp_port) { | |
880 | dev_err_ratelimited(mlxsw_sp->bus_info->dev, "Incorrect local port in FDB notification\n"); | |
881 | return; | |
882 | } | |
883 | ||
8a1ab5d7 JP |
884 | err = mlxsw_sp_port_fdb_uc_op(mlxsw_sp_port, mac, vid, |
885 | adding && mlxsw_sp_port->learning, true); | |
56ade8fe JP |
886 | if (err) { |
887 | if (net_ratelimit()) | |
888 | netdev_err(mlxsw_sp_port->dev, "Failed to set FDB entry\n"); | |
889 | return; | |
890 | } | |
891 | ||
8a1ab5d7 JP |
892 | mlxsw_sp_fdb_call_notifiers(mlxsw_sp_port->learning, |
893 | mlxsw_sp_port->learning_sync, | |
894 | adding, mac, vid, mlxsw_sp_port->dev); | |
895 | } | |
56ade8fe | 896 | |
8a1ab5d7 JP |
897 | static void mlxsw_sp_fdb_notify_mac_lag_process(struct mlxsw_sp *mlxsw_sp, |
898 | char *sfn_pl, int rec_index, | |
899 | bool adding) | |
900 | { | |
901 | struct mlxsw_sp_port *mlxsw_sp_port; | |
902 | char mac[ETH_ALEN]; | |
903 | u16 lag_id; | |
904 | u16 vid; | |
905 | int err; | |
906 | ||
907 | mlxsw_reg_sfn_mac_lag_unpack(sfn_pl, rec_index, mac, &vid, &lag_id); | |
908 | mlxsw_sp_port = mlxsw_sp_lag_rep_port(mlxsw_sp, lag_id); | |
909 | if (!mlxsw_sp_port) { | |
910 | dev_err_ratelimited(mlxsw_sp->bus_info->dev, "Cannot find port representor for LAG\n"); | |
911 | return; | |
56ade8fe | 912 | } |
8a1ab5d7 JP |
913 | |
914 | err = mlxsw_sp_port_fdb_uc_lag_op(mlxsw_sp, lag_id, mac, vid, | |
915 | adding && mlxsw_sp_port->learning, | |
916 | true); | |
917 | if (err) { | |
918 | if (net_ratelimit()) | |
919 | netdev_err(mlxsw_sp_port->dev, "Failed to set FDB entry\n"); | |
920 | return; | |
921 | } | |
922 | ||
923 | mlxsw_sp_fdb_call_notifiers(mlxsw_sp_port->learning, | |
924 | mlxsw_sp_port->learning_sync, | |
925 | adding, mac, vid, | |
926 | mlxsw_sp_lag_get(mlxsw_sp, lag_id)->dev); | |
56ade8fe JP |
927 | } |
928 | ||
929 | static void mlxsw_sp_fdb_notify_rec_process(struct mlxsw_sp *mlxsw_sp, | |
930 | char *sfn_pl, int rec_index) | |
931 | { | |
932 | switch (mlxsw_reg_sfn_rec_type_get(sfn_pl, rec_index)) { | |
933 | case MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC: | |
934 | mlxsw_sp_fdb_notify_mac_process(mlxsw_sp, sfn_pl, | |
935 | rec_index, true); | |
936 | break; | |
937 | case MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC: | |
938 | mlxsw_sp_fdb_notify_mac_process(mlxsw_sp, sfn_pl, | |
939 | rec_index, false); | |
940 | break; | |
8a1ab5d7 JP |
941 | case MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG: |
942 | mlxsw_sp_fdb_notify_mac_lag_process(mlxsw_sp, sfn_pl, | |
943 | rec_index, true); | |
944 | break; | |
945 | case MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG: | |
946 | mlxsw_sp_fdb_notify_mac_lag_process(mlxsw_sp, sfn_pl, | |
947 | rec_index, false); | |
948 | break; | |
56ade8fe JP |
949 | } |
950 | } | |
951 | ||
952 | static void mlxsw_sp_fdb_notify_work_schedule(struct mlxsw_sp *mlxsw_sp) | |
953 | { | |
954 | schedule_delayed_work(&mlxsw_sp->fdb_notify.dw, | |
955 | msecs_to_jiffies(mlxsw_sp->fdb_notify.interval)); | |
956 | } | |
957 | ||
958 | static void mlxsw_sp_fdb_notify_work(struct work_struct *work) | |
959 | { | |
960 | struct mlxsw_sp *mlxsw_sp; | |
961 | char *sfn_pl; | |
962 | u8 num_rec; | |
963 | int i; | |
964 | int err; | |
965 | ||
966 | sfn_pl = kmalloc(MLXSW_REG_SFN_LEN, GFP_KERNEL); | |
967 | if (!sfn_pl) | |
968 | return; | |
969 | ||
970 | mlxsw_sp = container_of(work, struct mlxsw_sp, fdb_notify.dw.work); | |
971 | ||
972 | do { | |
973 | mlxsw_reg_sfn_pack(sfn_pl); | |
974 | err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(sfn), sfn_pl); | |
975 | if (err) { | |
976 | dev_err_ratelimited(mlxsw_sp->bus_info->dev, "Failed to get FDB notifications\n"); | |
977 | break; | |
978 | } | |
979 | num_rec = mlxsw_reg_sfn_num_rec_get(sfn_pl); | |
980 | for (i = 0; i < num_rec; i++) | |
981 | mlxsw_sp_fdb_notify_rec_process(mlxsw_sp, sfn_pl, i); | |
982 | ||
983 | } while (num_rec); | |
984 | ||
985 | kfree(sfn_pl); | |
986 | mlxsw_sp_fdb_notify_work_schedule(mlxsw_sp); | |
987 | } | |
988 | ||
989 | static int mlxsw_sp_fdb_init(struct mlxsw_sp *mlxsw_sp) | |
990 | { | |
991 | int err; | |
992 | ||
993 | err = mlxsw_sp_ageing_set(mlxsw_sp, MLXSW_SP_DEFAULT_AGEING_TIME); | |
994 | if (err) { | |
995 | dev_err(mlxsw_sp->bus_info->dev, "Failed to set default ageing time\n"); | |
996 | return err; | |
997 | } | |
998 | INIT_DELAYED_WORK(&mlxsw_sp->fdb_notify.dw, mlxsw_sp_fdb_notify_work); | |
999 | mlxsw_sp->fdb_notify.interval = MLXSW_SP_DEFAULT_LEARNING_INTERVAL; | |
1000 | mlxsw_sp_fdb_notify_work_schedule(mlxsw_sp); | |
1001 | return 0; | |
1002 | } | |
1003 | ||
1004 | static void mlxsw_sp_fdb_fini(struct mlxsw_sp *mlxsw_sp) | |
1005 | { | |
1006 | cancel_delayed_work_sync(&mlxsw_sp->fdb_notify.dw); | |
1007 | } | |
1008 | ||
1009 | static void mlxsw_sp_fids_fini(struct mlxsw_sp *mlxsw_sp) | |
1010 | { | |
1011 | u16 fid; | |
1012 | ||
1013 | for_each_set_bit(fid, mlxsw_sp->active_fids, VLAN_N_VID) | |
1014 | mlxsw_sp_fid_destroy(mlxsw_sp, fid); | |
1015 | } | |
1016 | ||
1017 | int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp) | |
1018 | { | |
1019 | return mlxsw_sp_fdb_init(mlxsw_sp); | |
1020 | } | |
1021 | ||
1022 | void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp) | |
1023 | { | |
1024 | mlxsw_sp_fdb_fini(mlxsw_sp); | |
1025 | mlxsw_sp_fids_fini(mlxsw_sp); | |
1026 | } | |
1027 | ||
1028 | int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port) | |
1029 | { | |
1030 | struct net_device *dev = mlxsw_sp_port->dev; | |
1031 | int err; | |
1032 | ||
1033 | /* Allow only untagged packets to ingress and tag them internally | |
1034 | * with VID 1. | |
1035 | */ | |
1036 | mlxsw_sp_port->pvid = 1; | |
1037 | err = __mlxsw_sp_port_vlans_del(mlxsw_sp_port, 0, VLAN_N_VID, true); | |
1038 | if (err) { | |
1039 | netdev_err(dev, "Unable to init VLANs\n"); | |
1040 | return err; | |
1041 | } | |
1042 | ||
1043 | /* Add implicit VLAN interface in the device, so that untagged | |
1044 | * packets will be classified to the default vFID. | |
1045 | */ | |
1046 | err = mlxsw_sp_port_add_vid(dev, 0, 1); | |
1047 | if (err) | |
1048 | netdev_err(dev, "Failed to configure default vFID\n"); | |
1049 | ||
1050 | return err; | |
1051 | } | |
1052 | ||
1053 | void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port) | |
1054 | { | |
1055 | mlxsw_sp_port->dev->switchdev_ops = &mlxsw_sp_port_switchdev_ops; | |
1056 | } | |
1057 | ||
1058 | void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port) | |
1059 | { | |
1060 | } |