Commit | Line | Data |
---|---|---|
3d396eb1 | 1 | /* |
5d242f1c | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
13af7a6e | 3 | * Copyright (C) 2009 - QLogic Corporation. |
3d396eb1 | 4 | * All rights reserved. |
80922fbc | 5 | * |
3d396eb1 AK |
6 | * This program is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
80922fbc | 10 | * |
3d396eb1 AK |
11 | * This program is distributed in the hope that it will be useful, but |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
80922fbc | 15 | * |
3d396eb1 AK |
16 | * You should have received a copy of the GNU General Public License |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
19 | * MA 02111-1307, USA. | |
80922fbc | 20 | * |
3d396eb1 | 21 | * The full GNU General Public License is included in this distribution |
4d21fef4 | 22 | * in the file called "COPYING". |
80922fbc | 23 | * |
3d396eb1 AK |
24 | */ |
25 | ||
26 | #include <linux/netdevice.h> | |
27 | #include <linux/delay.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
57569d0e | 29 | #include <linux/if_vlan.h> |
3d396eb1 AK |
30 | #include "netxen_nic.h" |
31 | #include "netxen_nic_hw.h" | |
3d396eb1 AK |
32 | |
33 | struct crb_addr_pair { | |
e0e20a1a LCMT |
34 | u32 addr; |
35 | u32 data; | |
3d396eb1 AK |
36 | }; |
37 | ||
38 | #define NETXEN_MAX_CRB_XFORM 60 | |
39 | static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM]; | |
e0e20a1a | 40 | #define NETXEN_ADDR_ERROR (0xffffffff) |
3d396eb1 AK |
41 | |
42 | #define crb_addr_transform(name) \ | |
43 | crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \ | |
44 | NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20 | |
45 | ||
cb8011ad AK |
46 | #define NETXEN_NIC_XDMA_RESET 0x8000ff |
47 | ||
becf46a0 | 48 | static void |
d8b100c5 DP |
49 | netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, |
50 | struct nx_host_rds_ring *rds_ring); | |
f50330f9 | 51 | static int netxen_p3_has_mn(struct netxen_adapter *adapter); |
993fb90c | 52 | |
3d396eb1 AK |
53 | static void crb_addr_transform_setup(void) |
54 | { | |
55 | crb_addr_transform(XDMA); | |
56 | crb_addr_transform(TIMR); | |
57 | crb_addr_transform(SRE); | |
58 | crb_addr_transform(SQN3); | |
59 | crb_addr_transform(SQN2); | |
60 | crb_addr_transform(SQN1); | |
61 | crb_addr_transform(SQN0); | |
62 | crb_addr_transform(SQS3); | |
63 | crb_addr_transform(SQS2); | |
64 | crb_addr_transform(SQS1); | |
65 | crb_addr_transform(SQS0); | |
66 | crb_addr_transform(RPMX7); | |
67 | crb_addr_transform(RPMX6); | |
68 | crb_addr_transform(RPMX5); | |
69 | crb_addr_transform(RPMX4); | |
70 | crb_addr_transform(RPMX3); | |
71 | crb_addr_transform(RPMX2); | |
72 | crb_addr_transform(RPMX1); | |
73 | crb_addr_transform(RPMX0); | |
74 | crb_addr_transform(ROMUSB); | |
75 | crb_addr_transform(SN); | |
76 | crb_addr_transform(QMN); | |
77 | crb_addr_transform(QMS); | |
78 | crb_addr_transform(PGNI); | |
79 | crb_addr_transform(PGND); | |
80 | crb_addr_transform(PGN3); | |
81 | crb_addr_transform(PGN2); | |
82 | crb_addr_transform(PGN1); | |
83 | crb_addr_transform(PGN0); | |
84 | crb_addr_transform(PGSI); | |
85 | crb_addr_transform(PGSD); | |
86 | crb_addr_transform(PGS3); | |
87 | crb_addr_transform(PGS2); | |
88 | crb_addr_transform(PGS1); | |
89 | crb_addr_transform(PGS0); | |
90 | crb_addr_transform(PS); | |
91 | crb_addr_transform(PH); | |
92 | crb_addr_transform(NIU); | |
93 | crb_addr_transform(I2Q); | |
94 | crb_addr_transform(EG); | |
95 | crb_addr_transform(MN); | |
96 | crb_addr_transform(MS); | |
97 | crb_addr_transform(CAS2); | |
98 | crb_addr_transform(CAS1); | |
99 | crb_addr_transform(CAS0); | |
100 | crb_addr_transform(CAM); | |
101 | crb_addr_transform(C2C1); | |
102 | crb_addr_transform(C2C0); | |
1fcca1a5 | 103 | crb_addr_transform(SMB); |
e4c93c81 DP |
104 | crb_addr_transform(OCM0); |
105 | crb_addr_transform(I2C0); | |
3d396eb1 AK |
106 | } |
107 | ||
2956640d | 108 | void netxen_release_rx_buffers(struct netxen_adapter *adapter) |
3d396eb1 | 109 | { |
2956640d | 110 | struct netxen_recv_context *recv_ctx; |
48bfd1e0 | 111 | struct nx_host_rds_ring *rds_ring; |
2956640d | 112 | struct netxen_rx_buffer *rx_buf; |
becf46a0 DP |
113 | int i, ring; |
114 | ||
115 | recv_ctx = &adapter->recv_ctx; | |
116 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
117 | rds_ring = &recv_ctx->rds_rings[ring]; | |
438627c7 | 118 | for (i = 0; i < rds_ring->num_desc; ++i) { |
becf46a0 DP |
119 | rx_buf = &(rds_ring->rx_buf_arr[i]); |
120 | if (rx_buf->state == NETXEN_BUFFER_FREE) | |
121 | continue; | |
122 | pci_unmap_single(adapter->pdev, | |
123 | rx_buf->dma, | |
124 | rds_ring->dma_size, | |
125 | PCI_DMA_FROMDEVICE); | |
126 | if (rx_buf->skb != NULL) | |
127 | dev_kfree_skb_any(rx_buf->skb); | |
2956640d DP |
128 | } |
129 | } | |
130 | } | |
131 | ||
132 | void netxen_release_tx_buffers(struct netxen_adapter *adapter) | |
133 | { | |
134 | struct netxen_cmd_buffer *cmd_buf; | |
135 | struct netxen_skb_frag *buffrag; | |
136 | int i, j; | |
4ea528a1 | 137 | struct nx_host_tx_ring *tx_ring = adapter->tx_ring; |
2956640d | 138 | |
d877f1e3 DP |
139 | cmd_buf = tx_ring->cmd_buf_arr; |
140 | for (i = 0; i < tx_ring->num_desc; i++) { | |
2956640d DP |
141 | buffrag = cmd_buf->frag_array; |
142 | if (buffrag->dma) { | |
143 | pci_unmap_single(adapter->pdev, buffrag->dma, | |
144 | buffrag->length, PCI_DMA_TODEVICE); | |
145 | buffrag->dma = 0ULL; | |
146 | } | |
a05948f2 | 147 | for (j = 1; j < cmd_buf->frag_count; j++) { |
2956640d DP |
148 | buffrag++; |
149 | if (buffrag->dma) { | |
150 | pci_unmap_page(adapter->pdev, buffrag->dma, | |
151 | buffrag->length, | |
152 | PCI_DMA_TODEVICE); | |
153 | buffrag->dma = 0ULL; | |
154 | } | |
155 | } | |
2956640d DP |
156 | if (cmd_buf->skb) { |
157 | dev_kfree_skb_any(cmd_buf->skb); | |
158 | cmd_buf->skb = NULL; | |
159 | } | |
160 | cmd_buf++; | |
161 | } | |
162 | } | |
163 | ||
164 | void netxen_free_sw_resources(struct netxen_adapter *adapter) | |
165 | { | |
166 | struct netxen_recv_context *recv_ctx; | |
48bfd1e0 | 167 | struct nx_host_rds_ring *rds_ring; |
d877f1e3 | 168 | struct nx_host_tx_ring *tx_ring; |
becf46a0 DP |
169 | int ring; |
170 | ||
171 | recv_ctx = &adapter->recv_ctx; | |
4ea528a1 DP |
172 | |
173 | if (recv_ctx->rds_rings == NULL) | |
174 | goto skip_rds; | |
175 | ||
becf46a0 DP |
176 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
177 | rds_ring = &recv_ctx->rds_rings[ring]; | |
f2333a01 F |
178 | vfree(rds_ring->rx_buf_arr); |
179 | rds_ring->rx_buf_arr = NULL; | |
2956640d | 180 | } |
4ea528a1 DP |
181 | kfree(recv_ctx->rds_rings); |
182 | ||
183 | skip_rds: | |
184 | if (adapter->tx_ring == NULL) | |
185 | return; | |
becf46a0 | 186 | |
4ea528a1 | 187 | tx_ring = adapter->tx_ring; |
f2333a01 | 188 | vfree(tx_ring->cmd_buf_arr); |
011f4ea0 AKS |
189 | kfree(tx_ring); |
190 | adapter->tx_ring = NULL; | |
2956640d DP |
191 | } |
192 | ||
193 | int netxen_alloc_sw_resources(struct netxen_adapter *adapter) | |
194 | { | |
195 | struct netxen_recv_context *recv_ctx; | |
48bfd1e0 | 196 | struct nx_host_rds_ring *rds_ring; |
d8b100c5 | 197 | struct nx_host_sds_ring *sds_ring; |
4ea528a1 | 198 | struct nx_host_tx_ring *tx_ring; |
2956640d | 199 | struct netxen_rx_buffer *rx_buf; |
4ea528a1 | 200 | int ring, i, size; |
2956640d DP |
201 | |
202 | struct netxen_cmd_buffer *cmd_buf_arr; | |
203 | struct net_device *netdev = adapter->netdev; | |
d877f1e3 | 204 | struct pci_dev *pdev = adapter->pdev; |
2956640d | 205 | |
4ea528a1 DP |
206 | size = sizeof(struct nx_host_tx_ring); |
207 | tx_ring = kzalloc(size, GFP_KERNEL); | |
208 | if (tx_ring == NULL) { | |
209 | dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n", | |
210 | netdev->name); | |
211 | return -ENOMEM; | |
212 | } | |
213 | adapter->tx_ring = tx_ring; | |
214 | ||
d877f1e3 | 215 | tx_ring->num_desc = adapter->num_txd; |
b2af9cb0 | 216 | tx_ring->txq = netdev_get_tx_queue(netdev, 0); |
4ea528a1 | 217 | |
89bf67f1 | 218 | cmd_buf_arr = vzalloc(TX_BUFF_RINGSIZE(tx_ring)); |
2956640d | 219 | if (cmd_buf_arr == NULL) { |
d877f1e3 | 220 | dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n", |
2956640d | 221 | netdev->name); |
bf445080 | 222 | goto err_out; |
2956640d | 223 | } |
d877f1e3 | 224 | tx_ring->cmd_buf_arr = cmd_buf_arr; |
2956640d | 225 | |
becf46a0 | 226 | recv_ctx = &adapter->recv_ctx; |
4ea528a1 DP |
227 | |
228 | size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring); | |
229 | rds_ring = kzalloc(size, GFP_KERNEL); | |
230 | if (rds_ring == NULL) { | |
231 | dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n", | |
232 | netdev->name); | |
bf445080 | 233 | goto err_out; |
4ea528a1 DP |
234 | } |
235 | recv_ctx->rds_rings = rds_ring; | |
236 | ||
becf46a0 DP |
237 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
238 | rds_ring = &recv_ctx->rds_rings[ring]; | |
438627c7 DP |
239 | switch (ring) { |
240 | case RCV_RING_NORMAL: | |
241 | rds_ring->num_desc = adapter->num_rxd; | |
becf46a0 DP |
242 | if (adapter->ahw.cut_through) { |
243 | rds_ring->dma_size = | |
244 | NX_CT_DEFAULT_RX_BUF_LEN; | |
48bfd1e0 | 245 | rds_ring->skb_size = |
becf46a0 DP |
246 | NX_CT_DEFAULT_RX_BUF_LEN; |
247 | } else { | |
9b08beba DP |
248 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) |
249 | rds_ring->dma_size = | |
250 | NX_P3_RX_BUF_MAX_LEN; | |
251 | else | |
252 | rds_ring->dma_size = | |
253 | NX_P2_RX_BUF_MAX_LEN; | |
becf46a0 | 254 | rds_ring->skb_size = |
9b08beba | 255 | rds_ring->dma_size + NET_IP_ALIGN; |
becf46a0 DP |
256 | } |
257 | break; | |
2956640d | 258 | |
438627c7 DP |
259 | case RCV_RING_JUMBO: |
260 | rds_ring->num_desc = adapter->num_jumbo_rxd; | |
becf46a0 DP |
261 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) |
262 | rds_ring->dma_size = | |
263 | NX_P3_RX_JUMBO_BUF_MAX_LEN; | |
264 | else | |
265 | rds_ring->dma_size = | |
266 | NX_P2_RX_JUMBO_BUF_MAX_LEN; | |
bc75e5bf DP |
267 | |
268 | if (adapter->capabilities & NX_CAP0_HW_LRO) | |
269 | rds_ring->dma_size += NX_LRO_BUFFER_EXTRA; | |
270 | ||
becf46a0 DP |
271 | rds_ring->skb_size = |
272 | rds_ring->dma_size + NET_IP_ALIGN; | |
273 | break; | |
2956640d | 274 | |
becf46a0 | 275 | case RCV_RING_LRO: |
438627c7 | 276 | rds_ring->num_desc = adapter->num_lro_rxd; |
9b08beba DP |
277 | rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH; |
278 | rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN; | |
becf46a0 DP |
279 | break; |
280 | ||
281 | } | |
0acdf68f | 282 | rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring)); |
e404decb | 283 | if (rds_ring->rx_buf_arr == NULL) |
becf46a0 DP |
284 | /* free whatever was already allocated */ |
285 | goto err_out; | |
e404decb | 286 | |
becf46a0 DP |
287 | INIT_LIST_HEAD(&rds_ring->free_list); |
288 | /* | |
289 | * Now go through all of them, set reference handles | |
290 | * and put them in the queues. | |
291 | */ | |
becf46a0 | 292 | rx_buf = rds_ring->rx_buf_arr; |
4ea528a1 | 293 | for (i = 0; i < rds_ring->num_desc; i++) { |
becf46a0 DP |
294 | list_add_tail(&rx_buf->list, |
295 | &rds_ring->free_list); | |
296 | rx_buf->ref_handle = i; | |
297 | rx_buf->state = NETXEN_BUFFER_FREE; | |
298 | rx_buf++; | |
3d396eb1 | 299 | } |
d8b100c5 DP |
300 | spin_lock_init(&rds_ring->lock); |
301 | } | |
302 | ||
303 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { | |
304 | sds_ring = &recv_ctx->sds_rings[ring]; | |
305 | sds_ring->irq = adapter->msix_entries[ring].vector; | |
d8b100c5 DP |
306 | sds_ring->adapter = adapter; |
307 | sds_ring->num_desc = adapter->num_rxd; | |
308 | ||
309 | for (i = 0; i < NUM_RCV_DESC_RINGS; i++) | |
310 | INIT_LIST_HEAD(&sds_ring->free_list[i]); | |
3d396eb1 | 311 | } |
2956640d DP |
312 | |
313 | return 0; | |
314 | ||
315 | err_out: | |
316 | netxen_free_sw_resources(adapter); | |
317 | return -ENOMEM; | |
3d396eb1 AK |
318 | } |
319 | ||
3d396eb1 AK |
320 | /* |
321 | * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB | |
322 | * address to external PCI CRB address. | |
323 | */ | |
993fb90c | 324 | static u32 netxen_decode_crb_addr(u32 addr) |
3d396eb1 AK |
325 | { |
326 | int i; | |
e0e20a1a | 327 | u32 base_addr, offset, pci_base; |
3d396eb1 AK |
328 | |
329 | crb_addr_transform_setup(); | |
330 | ||
331 | pci_base = NETXEN_ADDR_ERROR; | |
332 | base_addr = addr & 0xfff00000; | |
333 | offset = addr & 0x000fffff; | |
334 | ||
335 | for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) { | |
336 | if (crb_addr_xform[i] == base_addr) { | |
337 | pci_base = i << 20; | |
338 | break; | |
339 | } | |
340 | } | |
341 | if (pci_base == NETXEN_ADDR_ERROR) | |
342 | return pci_base; | |
343 | else | |
807540ba | 344 | return pci_base + offset; |
3d396eb1 AK |
345 | } |
346 | ||
c9517e58 | 347 | #define NETXEN_MAX_ROM_WAIT_USEC 100 |
3d396eb1 | 348 | |
993fb90c | 349 | static int netxen_wait_rom_done(struct netxen_adapter *adapter) |
3d396eb1 AK |
350 | { |
351 | long timeout = 0; | |
352 | long done = 0; | |
353 | ||
27c915a4 DP |
354 | cond_resched(); |
355 | ||
3d396eb1 | 356 | while (done == 0) { |
f98a9f69 | 357 | done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS); |
3d396eb1 | 358 | done &= 2; |
c9517e58 DP |
359 | if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) { |
360 | dev_err(&adapter->pdev->dev, | |
361 | "Timeout reached waiting for rom done"); | |
3d396eb1 AK |
362 | return -EIO; |
363 | } | |
c9517e58 | 364 | udelay(1); |
3d396eb1 AK |
365 | } |
366 | return 0; | |
367 | } | |
368 | ||
993fb90c AB |
369 | static int do_rom_fast_read(struct netxen_adapter *adapter, |
370 | int addr, int *valp) | |
3d396eb1 | 371 | { |
f98a9f69 DP |
372 | NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); |
373 | NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); | |
374 | NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); | |
375 | NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb); | |
3d396eb1 AK |
376 | if (netxen_wait_rom_done(adapter)) { |
377 | printk("Error waiting for rom done\n"); | |
378 | return -EIO; | |
379 | } | |
380 | /* reset abyte_cnt and dummy_byte_cnt */ | |
f98a9f69 | 381 | NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); |
27c915a4 | 382 | udelay(10); |
f98a9f69 | 383 | NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
3d396eb1 | 384 | |
f98a9f69 | 385 | *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA); |
3d396eb1 AK |
386 | return 0; |
387 | } | |
388 | ||
993fb90c AB |
389 | static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
390 | u8 *bytes, size_t size) | |
27d2ab54 AK |
391 | { |
392 | int addridx; | |
393 | int ret = 0; | |
394 | ||
395 | for (addridx = addr; addridx < (addr + size); addridx += 4) { | |
f305f789 AV |
396 | int v; |
397 | ret = do_rom_fast_read(adapter, addridx, &v); | |
27d2ab54 AK |
398 | if (ret != 0) |
399 | break; | |
f305f789 | 400 | *(__le32 *)bytes = cpu_to_le32(v); |
27d2ab54 AK |
401 | bytes += 4; |
402 | } | |
403 | ||
404 | return ret; | |
405 | } | |
406 | ||
407 | int | |
4790654c | 408 | netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 AK |
409 | u8 *bytes, size_t size) |
410 | { | |
411 | int ret; | |
412 | ||
c9517e58 | 413 | ret = netxen_rom_lock(adapter); |
27d2ab54 AK |
414 | if (ret < 0) |
415 | return ret; | |
416 | ||
417 | ret = do_rom_fast_read_words(adapter, addr, bytes, size); | |
418 | ||
419 | netxen_rom_unlock(adapter); | |
420 | return ret; | |
421 | } | |
422 | ||
3d396eb1 AK |
423 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp) |
424 | { | |
425 | int ret; | |
426 | ||
c9517e58 | 427 | if (netxen_rom_lock(adapter) != 0) |
3d396eb1 AK |
428 | return -EIO; |
429 | ||
430 | ret = do_rom_fast_read(adapter, addr, valp); | |
cb8011ad AK |
431 | netxen_rom_unlock(adapter); |
432 | return ret; | |
433 | } | |
434 | ||
3d396eb1 AK |
435 | #define NETXEN_BOARDTYPE 0x4008 |
436 | #define NETXEN_BOARDNUM 0x400c | |
437 | #define NETXEN_CHIPNUM 0x4010 | |
3d396eb1 | 438 | |
0be367bd | 439 | int netxen_pinit_from_rom(struct netxen_adapter *adapter) |
3d396eb1 | 440 | { |
dcd56fdb | 441 | int addr, val; |
27c915a4 | 442 | int i, n, init_delay = 0; |
3d396eb1 | 443 | struct crb_addr_pair *buf; |
27c915a4 | 444 | unsigned offset; |
e0e20a1a | 445 | u32 off; |
3d396eb1 AK |
446 | |
447 | /* resetall */ | |
c9517e58 | 448 | netxen_rom_lock(adapter); |
83f18a55 | 449 | NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xfeffffff); |
27c915a4 | 450 | netxen_rom_unlock(adapter); |
3d396eb1 | 451 | |
2956640d DP |
452 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
453 | if (netxen_rom_fast_read(adapter, 0, &n) != 0 || | |
27c915a4 | 454 | (n != 0xcafecafe) || |
2956640d DP |
455 | netxen_rom_fast_read(adapter, 4, &n) != 0) { |
456 | printk(KERN_ERR "%s: ERROR Reading crb_init area: " | |
457 | "n: %08x\n", netxen_nic_driver_name, n); | |
3d396eb1 AK |
458 | return -EIO; |
459 | } | |
2956640d DP |
460 | offset = n & 0xffffU; |
461 | n = (n >> 16) & 0xffffU; | |
462 | } else { | |
463 | if (netxen_rom_fast_read(adapter, 0, &n) != 0 || | |
464 | !(n & 0x80000000)) { | |
465 | printk(KERN_ERR "%s: ERROR Reading crb_init area: " | |
466 | "n: %08x\n", netxen_nic_driver_name, n); | |
467 | return -EIO; | |
3d396eb1 | 468 | } |
2956640d DP |
469 | offset = 1; |
470 | n &= ~0x80000000; | |
471 | } | |
472 | ||
0be367bd | 473 | if (n >= 1024) { |
2956640d DP |
474 | printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not" |
475 | " initialized.\n", __func__, n); | |
476 | return -EIO; | |
477 | } | |
3d396eb1 | 478 | |
2956640d | 479 | buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL); |
e404decb | 480 | if (buf == NULL) |
2956640d | 481 | return -ENOMEM; |
0be367bd | 482 | |
2956640d DP |
483 | for (i = 0; i < n; i++) { |
484 | if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 || | |
584dbe94 DM |
485 | netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) { |
486 | kfree(buf); | |
2956640d | 487 | return -EIO; |
584dbe94 | 488 | } |
2956640d DP |
489 | |
490 | buf[i].addr = addr; | |
491 | buf[i].data = val; | |
492 | ||
2956640d | 493 | } |
0be367bd | 494 | |
2956640d DP |
495 | for (i = 0; i < n; i++) { |
496 | ||
497 | off = netxen_decode_crb_addr(buf[i].addr); | |
498 | if (off == NETXEN_ADDR_ERROR) { | |
499 | printk(KERN_ERR"CRB init value out of range %x\n", | |
1fcca1a5 | 500 | buf[i].addr); |
2956640d DP |
501 | continue; |
502 | } | |
503 | off += NETXEN_PCI_CRBSPACE; | |
0be367bd AKS |
504 | |
505 | if (off & 1) | |
506 | continue; | |
507 | ||
2956640d DP |
508 | /* skipping cold reboot MAGIC */ |
509 | if (off == NETXEN_CAM_RAM(0x1fc)) | |
510 | continue; | |
511 | ||
512 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { | |
8bee0a91 DP |
513 | if (off == (NETXEN_CRB_I2C0 + 0x1c)) |
514 | continue; | |
2956640d DP |
515 | /* do not reset PCI */ |
516 | if (off == (ROMUSB_GLB + 0xbc)) | |
1fcca1a5 | 517 | continue; |
27c915a4 DP |
518 | if (off == (ROMUSB_GLB + 0xa8)) |
519 | continue; | |
520 | if (off == (ROMUSB_GLB + 0xc8)) /* core clock */ | |
521 | continue; | |
522 | if (off == (ROMUSB_GLB + 0x24)) /* MN clock */ | |
523 | continue; | |
524 | if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */ | |
525 | continue; | |
e7473f12 AKS |
526 | if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET) |
527 | continue; | |
0be367bd AKS |
528 | if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) && |
529 | !NX_IS_REVISION_P3P(adapter->ahw.revision_id)) | |
2956640d DP |
530 | buf[i].data = 0x1020; |
531 | /* skip the function enable register */ | |
532 | if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION)) | |
3d396eb1 | 533 | continue; |
2956640d DP |
534 | if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2)) |
535 | continue; | |
536 | if ((off & 0x0ff00000) == NETXEN_CRB_SMB) | |
537 | continue; | |
538 | } | |
3d396eb1 | 539 | |
27c915a4 | 540 | init_delay = 1; |
2956640d DP |
541 | /* After writing this register, HW needs time for CRB */ |
542 | /* to quiet down (else crb_window returns 0xffffffff) */ | |
543 | if (off == NETXEN_ROMUSB_GLB_SW_RESET) { | |
27c915a4 | 544 | init_delay = 1000; |
2956640d | 545 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
3d396eb1 | 546 | /* hold xdma in reset also */ |
cb8011ad | 547 | buf[i].data = NETXEN_NIC_XDMA_RESET; |
27c915a4 | 548 | buf[i].data = 0x8000ff; |
3d396eb1 | 549 | } |
2956640d | 550 | } |
3d396eb1 | 551 | |
f98a9f69 | 552 | NXWR32(adapter, off, buf[i].data); |
3d396eb1 | 553 | |
27c915a4 | 554 | msleep(init_delay); |
2956640d DP |
555 | } |
556 | kfree(buf); | |
3d396eb1 | 557 | |
2956640d | 558 | /* disable_peg_cache_all */ |
3d396eb1 | 559 | |
2956640d DP |
560 | /* unreset_net_cache */ |
561 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
f98a9f69 DP |
562 | val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET); |
563 | NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f)); | |
3d396eb1 | 564 | } |
2956640d DP |
565 | |
566 | /* p2dn replyCount */ | |
f98a9f69 | 567 | NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e); |
2956640d | 568 | /* disable_peg_cache 0 */ |
f98a9f69 | 569 | NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8); |
2956640d | 570 | /* disable_peg_cache 1 */ |
f98a9f69 | 571 | NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8); |
2956640d DP |
572 | |
573 | /* peg_clr_all */ | |
574 | ||
575 | /* peg_clr 0 */ | |
f98a9f69 DP |
576 | NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0); |
577 | NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0); | |
2956640d | 578 | /* peg_clr 1 */ |
f98a9f69 DP |
579 | NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0); |
580 | NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0); | |
2956640d | 581 | /* peg_clr 2 */ |
f98a9f69 DP |
582 | NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0); |
583 | NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0); | |
2956640d | 584 | /* peg_clr 3 */ |
f98a9f69 DP |
585 | NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0); |
586 | NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0); | |
3d396eb1 AK |
587 | return 0; |
588 | } | |
589 | ||
f50330f9 AKS |
590 | static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section) |
591 | { | |
592 | uint32_t i; | |
593 | struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0]; | |
594 | __le32 entries = cpu_to_le32(directory->num_entries); | |
595 | ||
596 | for (i = 0; i < entries; i++) { | |
597 | ||
598 | __le32 offs = cpu_to_le32(directory->findex) + | |
599 | (i * cpu_to_le32(directory->entry_size)); | |
600 | __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8)); | |
601 | ||
602 | if (tab_type == section) | |
603 | return (struct uni_table_desc *) &unirom[offs]; | |
604 | } | |
605 | ||
606 | return NULL; | |
607 | } | |
608 | ||
10c0f2a8 RB |
609 | #define QLCNIC_FILEHEADER_SIZE (14 * 4) |
610 | ||
f50330f9 | 611 | static int |
10c0f2a8 RB |
612 | netxen_nic_validate_header(struct netxen_adapter *adapter) |
613 | { | |
f50330f9 | 614 | const u8 *unirom = adapter->fw->data; |
10c0f2a8 RB |
615 | struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0]; |
616 | u32 fw_file_size = adapter->fw->size; | |
617 | u32 tab_size; | |
f50330f9 | 618 | __le32 entries; |
10c0f2a8 RB |
619 | __le32 entry_size; |
620 | ||
621 | if (fw_file_size < QLCNIC_FILEHEADER_SIZE) | |
622 | return -EINVAL; | |
623 | ||
624 | entries = cpu_to_le32(directory->num_entries); | |
625 | entry_size = cpu_to_le32(directory->entry_size); | |
626 | tab_size = cpu_to_le32(directory->findex) + (entries * entry_size); | |
627 | ||
628 | if (fw_file_size < tab_size) | |
629 | return -EINVAL; | |
630 | ||
631 | return 0; | |
632 | } | |
633 | ||
634 | static int | |
635 | netxen_nic_validate_bootld(struct netxen_adapter *adapter) | |
636 | { | |
637 | struct uni_table_desc *tab_desc; | |
638 | struct uni_data_desc *descr; | |
639 | const u8 *unirom = adapter->fw->data; | |
640 | __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] + | |
641 | NX_UNI_BOOTLD_IDX_OFF)); | |
642 | u32 offs; | |
643 | u32 tab_size; | |
644 | u32 data_size; | |
645 | ||
646 | tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD); | |
647 | ||
648 | if (!tab_desc) | |
649 | return -EINVAL; | |
650 | ||
651 | tab_size = cpu_to_le32(tab_desc->findex) + | |
652 | (cpu_to_le32(tab_desc->entry_size) * (idx + 1)); | |
653 | ||
654 | if (adapter->fw->size < tab_size) | |
655 | return -EINVAL; | |
656 | ||
657 | offs = cpu_to_le32(tab_desc->findex) + | |
658 | (cpu_to_le32(tab_desc->entry_size) * (idx)); | |
659 | descr = (struct uni_data_desc *)&unirom[offs]; | |
660 | ||
661 | data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size); | |
662 | ||
663 | if (adapter->fw->size < data_size) | |
664 | return -EINVAL; | |
665 | ||
666 | return 0; | |
667 | } | |
668 | ||
669 | static int | |
670 | netxen_nic_validate_fw(struct netxen_adapter *adapter) | |
671 | { | |
672 | struct uni_table_desc *tab_desc; | |
673 | struct uni_data_desc *descr; | |
674 | const u8 *unirom = adapter->fw->data; | |
675 | __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] + | |
676 | NX_UNI_FIRMWARE_IDX_OFF)); | |
677 | u32 offs; | |
678 | u32 tab_size; | |
679 | u32 data_size; | |
680 | ||
681 | tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW); | |
682 | ||
683 | if (!tab_desc) | |
684 | return -EINVAL; | |
f50330f9 | 685 | |
10c0f2a8 RB |
686 | tab_size = cpu_to_le32(tab_desc->findex) + |
687 | (cpu_to_le32(tab_desc->entry_size) * (idx + 1)); | |
688 | ||
689 | if (adapter->fw->size < tab_size) | |
690 | return -EINVAL; | |
691 | ||
692 | offs = cpu_to_le32(tab_desc->findex) + | |
693 | (cpu_to_le32(tab_desc->entry_size) * (idx)); | |
694 | descr = (struct uni_data_desc *)&unirom[offs]; | |
695 | data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size); | |
696 | ||
697 | if (adapter->fw->size < data_size) | |
698 | return -EINVAL; | |
699 | ||
700 | return 0; | |
701 | } | |
702 | ||
703 | ||
704 | static int | |
705 | netxen_nic_validate_product_offs(struct netxen_adapter *adapter) | |
706 | { | |
707 | struct uni_table_desc *ptab_descr; | |
708 | const u8 *unirom = adapter->fw->data; | |
634d7df8 DP |
709 | int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ? |
710 | 1 : netxen_p3_has_mn(adapter); | |
10c0f2a8 RB |
711 | __le32 entries; |
712 | __le32 entry_size; | |
713 | u32 tab_size; | |
714 | u32 i; | |
634d7df8 | 715 | |
f50330f9 AKS |
716 | ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL); |
717 | if (ptab_descr == NULL) | |
10c0f2a8 | 718 | return -EINVAL; |
f50330f9 AKS |
719 | |
720 | entries = cpu_to_le32(ptab_descr->num_entries); | |
10c0f2a8 RB |
721 | entry_size = cpu_to_le32(ptab_descr->entry_size); |
722 | tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size); | |
723 | ||
724 | if (adapter->fw->size < tab_size) | |
725 | return -EINVAL; | |
f50330f9 | 726 | |
634d7df8 | 727 | nomn: |
f50330f9 AKS |
728 | for (i = 0; i < entries; i++) { |
729 | ||
730 | __le32 flags, file_chiprev, offs; | |
731 | u8 chiprev = adapter->ahw.revision_id; | |
f50330f9 AKS |
732 | uint32_t flagbit; |
733 | ||
734 | offs = cpu_to_le32(ptab_descr->findex) + | |
735 | (i * cpu_to_le32(ptab_descr->entry_size)); | |
736 | flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF)); | |
737 | file_chiprev = cpu_to_le32(*((int *)&unirom[offs] + | |
738 | NX_UNI_CHIP_REV_OFF)); | |
739 | ||
740 | flagbit = mn_present ? 1 : 2; | |
741 | ||
742 | if ((chiprev == file_chiprev) && | |
743 | ((1ULL << flagbit) & flags)) { | |
744 | adapter->file_prd_off = offs; | |
745 | return 0; | |
746 | } | |
747 | } | |
748 | ||
634d7df8 DP |
749 | if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
750 | mn_present = 0; | |
751 | goto nomn; | |
752 | } | |
753 | ||
10c0f2a8 | 754 | return -EINVAL; |
f50330f9 AKS |
755 | } |
756 | ||
10c0f2a8 RB |
757 | static int |
758 | netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter) | |
759 | { | |
760 | if (netxen_nic_validate_header(adapter)) { | |
761 | dev_err(&adapter->pdev->dev, | |
762 | "unified image: header validation failed\n"); | |
763 | return -EINVAL; | |
764 | } | |
765 | ||
766 | if (netxen_nic_validate_product_offs(adapter)) { | |
767 | dev_err(&adapter->pdev->dev, | |
768 | "unified image: product validation failed\n"); | |
769 | return -EINVAL; | |
770 | } | |
771 | ||
772 | if (netxen_nic_validate_bootld(adapter)) { | |
773 | dev_err(&adapter->pdev->dev, | |
774 | "unified image: bootld validation failed\n"); | |
775 | return -EINVAL; | |
776 | } | |
777 | ||
778 | if (netxen_nic_validate_fw(adapter)) { | |
779 | dev_err(&adapter->pdev->dev, | |
780 | "unified image: firmware validation failed\n"); | |
781 | return -EINVAL; | |
782 | } | |
783 | ||
784 | return 0; | |
785 | } | |
f50330f9 AKS |
786 | |
787 | static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter, | |
788 | u32 section, u32 idx_offset) | |
789 | { | |
790 | const u8 *unirom = adapter->fw->data; | |
791 | int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] + | |
792 | idx_offset)); | |
793 | struct uni_table_desc *tab_desc; | |
794 | __le32 offs; | |
795 | ||
796 | tab_desc = nx_get_table_desc(unirom, section); | |
797 | ||
798 | if (tab_desc == NULL) | |
799 | return NULL; | |
800 | ||
801 | offs = cpu_to_le32(tab_desc->findex) + | |
802 | (cpu_to_le32(tab_desc->entry_size) * idx); | |
803 | ||
804 | return (struct uni_data_desc *)&unirom[offs]; | |
805 | } | |
806 | ||
807 | static u8 * | |
808 | nx_get_bootld_offs(struct netxen_adapter *adapter) | |
809 | { | |
810 | u32 offs = NETXEN_BOOTLD_START; | |
811 | ||
812 | if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) | |
813 | offs = cpu_to_le32((nx_get_data_desc(adapter, | |
814 | NX_UNI_DIR_SECT_BOOTLD, | |
815 | NX_UNI_BOOTLD_IDX_OFF))->findex); | |
816 | ||
817 | return (u8 *)&adapter->fw->data[offs]; | |
818 | } | |
819 | ||
820 | static u8 * | |
821 | nx_get_fw_offs(struct netxen_adapter *adapter) | |
822 | { | |
823 | u32 offs = NETXEN_IMAGE_START; | |
824 | ||
825 | if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) | |
826 | offs = cpu_to_le32((nx_get_data_desc(adapter, | |
827 | NX_UNI_DIR_SECT_FW, | |
828 | NX_UNI_FIRMWARE_IDX_OFF))->findex); | |
829 | ||
830 | return (u8 *)&adapter->fw->data[offs]; | |
831 | } | |
832 | ||
833 | static __le32 | |
834 | nx_get_fw_size(struct netxen_adapter *adapter) | |
835 | { | |
836 | if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) | |
837 | return cpu_to_le32((nx_get_data_desc(adapter, | |
838 | NX_UNI_DIR_SECT_FW, | |
839 | NX_UNI_FIRMWARE_IDX_OFF))->size); | |
840 | else | |
841 | return cpu_to_le32( | |
842 | *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]); | |
843 | } | |
844 | ||
845 | static __le32 | |
846 | nx_get_fw_version(struct netxen_adapter *adapter) | |
847 | { | |
848 | struct uni_data_desc *fw_data_desc; | |
849 | const struct firmware *fw = adapter->fw; | |
850 | __le32 major, minor, sub; | |
851 | const u8 *ver_str; | |
852 | int i, ret = 0; | |
853 | ||
854 | if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) { | |
855 | ||
856 | fw_data_desc = nx_get_data_desc(adapter, | |
857 | NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF); | |
858 | ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) + | |
859 | cpu_to_le32(fw_data_desc->size) - 17; | |
860 | ||
861 | for (i = 0; i < 12; i++) { | |
862 | if (!strncmp(&ver_str[i], "REV=", 4)) { | |
863 | ret = sscanf(&ver_str[i+4], "%u.%u.%u ", | |
864 | &major, &minor, &sub); | |
865 | break; | |
866 | } | |
867 | } | |
868 | ||
869 | if (ret != 3) | |
870 | return 0; | |
871 | ||
872 | return major + (minor << 8) + (sub << 16); | |
873 | ||
874 | } else | |
875 | return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]); | |
876 | } | |
877 | ||
878 | static __le32 | |
879 | nx_get_bios_version(struct netxen_adapter *adapter) | |
880 | { | |
881 | const struct firmware *fw = adapter->fw; | |
882 | __le32 bios_ver, prd_off = adapter->file_prd_off; | |
883 | ||
884 | if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) { | |
885 | bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off]) | |
886 | + NX_UNI_BIOS_VERSION_OFF)); | |
bb2792e0 | 887 | return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) + |
f50330f9 AKS |
888 | (bios_ver >> 24); |
889 | } else | |
890 | return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]); | |
891 | ||
892 | } | |
893 | ||
67c38fc6 DP |
894 | int |
895 | netxen_need_fw_reset(struct netxen_adapter *adapter) | |
896 | { | |
897 | u32 count, old_count; | |
898 | u32 val, version, major, minor, build; | |
899 | int i, timeout; | |
900 | u8 fw_type; | |
901 | ||
902 | /* NX2031 firmware doesn't support heartbit */ | |
903 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
904 | return 1; | |
905 | ||
6a808c6c AKS |
906 | if (adapter->need_fw_reset) |
907 | return 1; | |
908 | ||
67c38fc6 DP |
909 | /* last attempt had failed */ |
910 | if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED) | |
911 | return 1; | |
912 | ||
581e8ae4 | 913 | old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER); |
67c38fc6 DP |
914 | |
915 | for (i = 0; i < 10; i++) { | |
916 | ||
917 | timeout = msleep_interruptible(200); | |
918 | if (timeout) { | |
919 | NXWR32(adapter, CRB_CMDPEG_STATE, | |
920 | PHAN_INITIALIZE_FAILED); | |
921 | return -EINTR; | |
922 | } | |
923 | ||
924 | count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER); | |
925 | if (count != old_count) | |
926 | break; | |
927 | } | |
928 | ||
929 | /* firmware is dead */ | |
930 | if (count == old_count) | |
931 | return 1; | |
932 | ||
933 | /* check if we have got newer or different file firmware */ | |
934 | if (adapter->fw) { | |
935 | ||
f50330f9 | 936 | val = nx_get_fw_version(adapter); |
67c38fc6 | 937 | |
67c38fc6 DP |
938 | version = NETXEN_DECODE_VERSION(val); |
939 | ||
940 | major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR); | |
941 | minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR); | |
942 | build = NXRD32(adapter, NETXEN_FW_VERSION_SUB); | |
943 | ||
944 | if (version > NETXEN_VERSION_CODE(major, minor, build)) | |
945 | return 1; | |
946 | ||
f50330f9 AKS |
947 | if (version == NETXEN_VERSION_CODE(major, minor, build) && |
948 | adapter->fw_type != NX_UNIFIED_ROMIMAGE) { | |
67c38fc6 DP |
949 | |
950 | val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL); | |
951 | fw_type = (val & 0x4) ? | |
952 | NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE; | |
953 | ||
954 | if (adapter->fw_type != fw_type) | |
955 | return 1; | |
956 | } | |
957 | } | |
958 | ||
959 | return 0; | |
960 | } | |
961 | ||
e933d019 AKS |
962 | #define NETXEN_MIN_P3_FW_SUPP NETXEN_VERSION_CODE(4, 0, 505) |
963 | ||
964 | int | |
965 | netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter) | |
966 | { | |
967 | u32 flash_fw_ver, min_fw_ver; | |
968 | ||
969 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
970 | return 0; | |
971 | ||
972 | if (netxen_rom_fast_read(adapter, | |
973 | NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) { | |
974 | dev_err(&adapter->pdev->dev, "Unable to read flash fw" | |
975 | "version\n"); | |
976 | return -EIO; | |
977 | } | |
978 | ||
979 | flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver); | |
980 | min_fw_ver = NETXEN_MIN_P3_FW_SUPP; | |
981 | if (flash_fw_ver >= min_fw_ver) | |
982 | return 0; | |
983 | ||
984 | dev_info(&adapter->pdev->dev, "Flash fw[%d.%d.%d] is < min fw supported" | |
985 | "[4.0.505]. Please update firmware on flash\n", | |
986 | _major(flash_fw_ver), _minor(flash_fw_ver), | |
987 | _build(flash_fw_ver)); | |
988 | return -EINVAL; | |
989 | } | |
990 | ||
67c38fc6 | 991 | static char *fw_name[] = { |
7e8e5d97 DP |
992 | NX_P2_MN_ROMIMAGE_NAME, |
993 | NX_P3_CT_ROMIMAGE_NAME, | |
994 | NX_P3_MN_ROMIMAGE_NAME, | |
995 | NX_UNIFIED_ROMIMAGE_NAME, | |
996 | NX_FLASH_ROMIMAGE_NAME, | |
67c38fc6 DP |
997 | }; |
998 | ||
f7185c71 DP |
999 | int |
1000 | netxen_load_firmware(struct netxen_adapter *adapter) | |
1001 | { | |
1002 | u64 *ptr64; | |
1003 | u32 i, flashaddr, size; | |
1004 | const struct firmware *fw = adapter->fw; | |
67c38fc6 DP |
1005 | struct pci_dev *pdev = adapter->pdev; |
1006 | ||
1007 | dev_info(&pdev->dev, "loading firmware from %s\n", | |
1008 | fw_name[adapter->fw_type]); | |
f7185c71 DP |
1009 | |
1010 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
1011 | NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1); | |
1012 | ||
1013 | if (fw) { | |
1014 | __le64 data; | |
1015 | ||
1016 | size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8; | |
1017 | ||
f50330f9 | 1018 | ptr64 = (u64 *)nx_get_bootld_offs(adapter); |
f7185c71 DP |
1019 | flashaddr = NETXEN_BOOTLD_START; |
1020 | ||
1021 | for (i = 0; i < size; i++) { | |
1022 | data = cpu_to_le64(ptr64[i]); | |
f50330f9 AKS |
1023 | |
1024 | if (adapter->pci_mem_write(adapter, flashaddr, data)) | |
1f5e055d AKS |
1025 | return -EIO; |
1026 | ||
f7185c71 DP |
1027 | flashaddr += 8; |
1028 | } | |
1029 | ||
f50330f9 | 1030 | size = (__force u32)nx_get_fw_size(adapter) / 8; |
f7185c71 | 1031 | |
f50330f9 | 1032 | ptr64 = (u64 *)nx_get_fw_offs(adapter); |
f7185c71 DP |
1033 | flashaddr = NETXEN_IMAGE_START; |
1034 | ||
1035 | for (i = 0; i < size; i++) { | |
1036 | data = cpu_to_le64(ptr64[i]); | |
1037 | ||
1038 | if (adapter->pci_mem_write(adapter, | |
1f5e055d | 1039 | flashaddr, data)) |
f7185c71 DP |
1040 | return -EIO; |
1041 | ||
1042 | flashaddr += 8; | |
1043 | } | |
e270299a AKS |
1044 | |
1045 | size = (__force u32)nx_get_fw_size(adapter) % 8; | |
1046 | if (size) { | |
1047 | data = cpu_to_le64(ptr64[i]); | |
1048 | ||
1049 | if (adapter->pci_mem_write(adapter, | |
1050 | flashaddr, data)) | |
1051 | return -EIO; | |
1052 | } | |
1053 | ||
f7185c71 | 1054 | } else { |
f78c0850 AKS |
1055 | u64 data; |
1056 | u32 hi, lo; | |
f7185c71 | 1057 | |
f78c0850 | 1058 | size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8; |
f7185c71 DP |
1059 | flashaddr = NETXEN_BOOTLD_START; |
1060 | ||
1061 | for (i = 0; i < size; i++) { | |
1062 | if (netxen_rom_fast_read(adapter, | |
1f5e055d | 1063 | flashaddr, (int *)&lo) != 0) |
f78c0850 AKS |
1064 | return -EIO; |
1065 | if (netxen_rom_fast_read(adapter, | |
1f5e055d | 1066 | flashaddr + 4, (int *)&hi) != 0) |
f7185c71 DP |
1067 | return -EIO; |
1068 | ||
f78c0850 AKS |
1069 | /* hi, lo are already in host endian byteorder */ |
1070 | data = (((u64)hi << 32) | lo); | |
1071 | ||
f7185c71 | 1072 | if (adapter->pci_mem_write(adapter, |
1f5e055d | 1073 | flashaddr, data)) |
f7185c71 DP |
1074 | return -EIO; |
1075 | ||
f78c0850 | 1076 | flashaddr += 8; |
f7185c71 DP |
1077 | } |
1078 | } | |
1079 | msleep(1); | |
1080 | ||
0be367bd AKS |
1081 | if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) { |
1082 | NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020); | |
1083 | NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e); | |
1084 | } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | |
f7185c71 DP |
1085 | NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d); |
1086 | else { | |
1087 | NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff); | |
1088 | NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0); | |
1089 | } | |
1090 | ||
1091 | return 0; | |
1092 | } | |
1093 | ||
1094 | static int | |
f50330f9 | 1095 | netxen_validate_firmware(struct netxen_adapter *adapter) |
f7185c71 DP |
1096 | { |
1097 | __le32 val; | |
e933d019 AKS |
1098 | __le32 flash_fw_ver; |
1099 | u32 file_fw_ver, min_ver, bios; | |
f7185c71 DP |
1100 | struct pci_dev *pdev = adapter->pdev; |
1101 | const struct firmware *fw = adapter->fw; | |
f50330f9 | 1102 | u8 fw_type = adapter->fw_type; |
e933d019 | 1103 | u32 crbinit_fix_fw; |
f7185c71 | 1104 | |
f50330f9 | 1105 | if (fw_type == NX_UNIFIED_ROMIMAGE) { |
10c0f2a8 | 1106 | if (netxen_nic_validate_unified_romimage(adapter)) |
f50330f9 | 1107 | return -EINVAL; |
f50330f9 AKS |
1108 | } else { |
1109 | val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]); | |
1110 | if ((__force u32)val != NETXEN_BDINFO_MAGIC) | |
1111 | return -EINVAL; | |
f7185c71 | 1112 | |
10c0f2a8 RB |
1113 | if (fw->size < NX_FW_MIN_SIZE) |
1114 | return -EINVAL; | |
f50330f9 AKS |
1115 | } |
1116 | ||
f50330f9 | 1117 | val = nx_get_fw_version(adapter); |
f7185c71 DP |
1118 | |
1119 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | |
e933d019 | 1120 | min_ver = NETXEN_MIN_P3_FW_SUPP; |
f7185c71 DP |
1121 | else |
1122 | min_ver = NETXEN_VERSION_CODE(3, 4, 216); | |
1123 | ||
e933d019 | 1124 | file_fw_ver = NETXEN_DECODE_VERSION(val); |
f7185c71 | 1125 | |
e933d019 AKS |
1126 | if ((_major(file_fw_ver) > _NETXEN_NIC_LINUX_MAJOR) || |
1127 | (file_fw_ver < min_ver)) { | |
f7185c71 DP |
1128 | dev_err(&pdev->dev, |
1129 | "%s: firmware version %d.%d.%d unsupported\n", | |
e933d019 AKS |
1130 | fw_name[fw_type], _major(file_fw_ver), _minor(file_fw_ver), |
1131 | _build(file_fw_ver)); | |
f7185c71 DP |
1132 | return -EINVAL; |
1133 | } | |
f50330f9 | 1134 | val = nx_get_bios_version(adapter); |
f7185c71 DP |
1135 | netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios); |
1136 | if ((__force u32)val != bios) { | |
1137 | dev_err(&pdev->dev, "%s: firmware bios is incompatible\n", | |
f50330f9 | 1138 | fw_name[fw_type]); |
f7185c71 DP |
1139 | return -EINVAL; |
1140 | } | |
1141 | ||
f7185c71 | 1142 | if (netxen_rom_fast_read(adapter, |
e933d019 AKS |
1143 | NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) { |
1144 | dev_err(&pdev->dev, "Unable to read flash fw version\n"); | |
f7185c71 | 1145 | return -EIO; |
e933d019 AKS |
1146 | } |
1147 | flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver); | |
1148 | ||
1149 | /* New fw from file is not allowed, if fw on flash is < 4.0.554 */ | |
1150 | crbinit_fix_fw = NETXEN_VERSION_CODE(4, 0, 554); | |
1151 | if (file_fw_ver >= crbinit_fix_fw && flash_fw_ver < crbinit_fix_fw && | |
1152 | NX_IS_REVISION_P3(adapter->ahw.revision_id)) { | |
1153 | dev_err(&pdev->dev, "Incompatibility detected between driver " | |
1154 | "and firmware version on flash. This configuration " | |
1155 | "is not recommended. Please update the firmware on " | |
1156 | "flash immediately\n"); | |
f7185c71 | 1157 | return -EINVAL; |
98e31bb0 | 1158 | } |
f7185c71 | 1159 | |
e933d019 AKS |
1160 | /* check if flashed firmware is newer only for no-mn and P2 case*/ |
1161 | if (!netxen_p3_has_mn(adapter) || | |
1162 | NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
1163 | if (flash_fw_ver > file_fw_ver) { | |
1164 | dev_info(&pdev->dev, "%s: firmware is older than flash\n", | |
1165 | fw_name[fw_type]); | |
1166 | return -EINVAL; | |
1167 | } | |
1168 | } | |
1169 | ||
f7185c71 DP |
1170 | NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC); |
1171 | return 0; | |
1172 | } | |
1173 | ||
f50330f9 AKS |
1174 | static void |
1175 | nx_get_next_fwtype(struct netxen_adapter *adapter) | |
1176 | { | |
1177 | u8 fw_type; | |
1178 | ||
1179 | switch (adapter->fw_type) { | |
1180 | case NX_UNKNOWN_ROMIMAGE: | |
1181 | fw_type = NX_UNIFIED_ROMIMAGE; | |
1182 | break; | |
1183 | ||
1184 | case NX_UNIFIED_ROMIMAGE: | |
1185 | if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) | |
1186 | fw_type = NX_FLASH_ROMIMAGE; | |
1187 | else if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
1188 | fw_type = NX_P2_MN_ROMIMAGE; | |
1189 | else if (netxen_p3_has_mn(adapter)) | |
1190 | fw_type = NX_P3_MN_ROMIMAGE; | |
1191 | else | |
1192 | fw_type = NX_P3_CT_ROMIMAGE; | |
1193 | break; | |
1194 | ||
1195 | case NX_P3_MN_ROMIMAGE: | |
1196 | fw_type = NX_P3_CT_ROMIMAGE; | |
1197 | break; | |
1198 | ||
1199 | case NX_P2_MN_ROMIMAGE: | |
1200 | case NX_P3_CT_ROMIMAGE: | |
1201 | default: | |
1202 | fw_type = NX_FLASH_ROMIMAGE; | |
1203 | break; | |
1204 | } | |
1205 | ||
1206 | adapter->fw_type = fw_type; | |
1207 | } | |
1208 | ||
6598b169 DP |
1209 | static int |
1210 | netxen_p3_has_mn(struct netxen_adapter *adapter) | |
f7185c71 DP |
1211 | { |
1212 | u32 capability, flashed_ver; | |
f7185c71 DP |
1213 | capability = 0; |
1214 | ||
634d7df8 DP |
1215 | /* NX2031 always had MN */ |
1216 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
1217 | return 1; | |
1218 | ||
f7185c71 DP |
1219 | netxen_rom_fast_read(adapter, |
1220 | NX_FW_VERSION_OFFSET, (int *)&flashed_ver); | |
98e31bb0 DP |
1221 | flashed_ver = NETXEN_DECODE_VERSION(flashed_ver); |
1222 | ||
f7185c71 | 1223 | if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) { |
6598b169 | 1224 | |
f7185c71 | 1225 | capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY); |
6598b169 DP |
1226 | if (capability & NX_PEG_TUNE_MN_PRESENT) |
1227 | return 1; | |
1228 | } | |
1229 | return 0; | |
1230 | } | |
1231 | ||
1232 | void netxen_request_firmware(struct netxen_adapter *adapter) | |
1233 | { | |
6598b169 DP |
1234 | struct pci_dev *pdev = adapter->pdev; |
1235 | int rc = 0; | |
1236 | ||
f50330f9 | 1237 | adapter->fw_type = NX_UNKNOWN_ROMIMAGE; |
f7185c71 | 1238 | |
f50330f9 AKS |
1239 | next: |
1240 | nx_get_next_fwtype(adapter); | |
f7185c71 | 1241 | |
f50330f9 | 1242 | if (adapter->fw_type == NX_FLASH_ROMIMAGE) { |
f7185c71 | 1243 | adapter->fw = NULL; |
f50330f9 AKS |
1244 | } else { |
1245 | rc = request_firmware(&adapter->fw, | |
1246 | fw_name[adapter->fw_type], &pdev->dev); | |
1247 | if (rc != 0) | |
1248 | goto next; | |
1249 | ||
1250 | rc = netxen_validate_firmware(adapter); | |
1251 | if (rc != 0) { | |
1252 | release_firmware(adapter->fw); | |
f7185c71 | 1253 | msleep(1); |
f50330f9 | 1254 | goto next; |
f7185c71 | 1255 | } |
f7185c71 | 1256 | } |
f7185c71 DP |
1257 | } |
1258 | ||
1259 | ||
1260 | void | |
1261 | netxen_release_firmware(struct netxen_adapter *adapter) | |
1262 | { | |
62baaf34 | 1263 | release_firmware(adapter->fw); |
db4cfd8a | 1264 | adapter->fw = NULL; |
f7185c71 DP |
1265 | } |
1266 | ||
83ac51fa | 1267 | int netxen_init_dummy_dma(struct netxen_adapter *adapter) |
ed25ffa1 | 1268 | { |
83ac51fa DP |
1269 | u64 addr; |
1270 | u32 hi, lo; | |
ed25ffa1 | 1271 | |
83ac51fa DP |
1272 | if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) |
1273 | return 0; | |
1274 | ||
1275 | adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev, | |
ed25ffa1 AK |
1276 | NETXEN_HOST_DUMMY_DMA_SIZE, |
1277 | &adapter->dummy_dma.phys_addr); | |
1278 | if (adapter->dummy_dma.addr == NULL) { | |
83ac51fa DP |
1279 | dev_err(&adapter->pdev->dev, |
1280 | "ERROR: Could not allocate dummy DMA memory\n"); | |
ed25ffa1 AK |
1281 | return -ENOMEM; |
1282 | } | |
1283 | ||
1284 | addr = (uint64_t) adapter->dummy_dma.phys_addr; | |
1285 | hi = (addr >> 32) & 0xffffffff; | |
1286 | lo = addr & 0xffffffff; | |
1287 | ||
f98a9f69 DP |
1288 | NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi); |
1289 | NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo); | |
ed25ffa1 AK |
1290 | |
1291 | return 0; | |
1292 | } | |
1293 | ||
83ac51fa DP |
1294 | /* |
1295 | * NetXen DMA watchdog control: | |
1296 | * | |
1297 | * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive | |
1298 | * Bit 1 : disable_request => 1 req disable dma watchdog | |
1299 | * Bit 2 : enable_request => 1 req enable dma watchdog | |
1300 | * Bit 3-31 : unused | |
1301 | */ | |
1302 | void netxen_free_dummy_dma(struct netxen_adapter *adapter) | |
ed25ffa1 | 1303 | { |
15eef1e1 | 1304 | int i = 100; |
83ac51fa DP |
1305 | u32 ctrl; |
1306 | ||
1307 | if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
1308 | return; | |
15eef1e1 DP |
1309 | |
1310 | if (!adapter->dummy_dma.addr) | |
1311 | return; | |
439b454e | 1312 | |
83ac51fa DP |
1313 | ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL); |
1314 | if ((ctrl & 0x1) != 0) { | |
1315 | NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2)); | |
1316 | ||
1317 | while ((ctrl & 0x1) != 0) { | |
1318 | ||
439b454e | 1319 | msleep(50); |
83ac51fa DP |
1320 | |
1321 | ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL); | |
1322 | ||
1323 | if (--i == 0) | |
439b454e | 1324 | break; |
6403eab1 | 1325 | } |
15eef1e1 | 1326 | } |
439b454e | 1327 | |
15eef1e1 DP |
1328 | if (i) { |
1329 | pci_free_consistent(adapter->pdev, | |
1330 | NETXEN_HOST_DUMMY_DMA_SIZE, | |
1331 | adapter->dummy_dma.addr, | |
1332 | adapter->dummy_dma.phys_addr); | |
1333 | adapter->dummy_dma.addr = NULL; | |
83ac51fa DP |
1334 | } else |
1335 | dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n"); | |
ed25ffa1 AK |
1336 | } |
1337 | ||
96acb6eb | 1338 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val) |
3d396eb1 AK |
1339 | { |
1340 | u32 val = 0; | |
2956640d | 1341 | int retries = 60; |
3d396eb1 | 1342 | |
96f2ebd2 DP |
1343 | if (pegtune_val) |
1344 | return 0; | |
1345 | ||
1346 | do { | |
1347 | val = NXRD32(adapter, CRB_CMDPEG_STATE); | |
96f2ebd2 DP |
1348 | switch (val) { |
1349 | case PHAN_INITIALIZE_COMPLETE: | |
1350 | case PHAN_INITIALIZE_ACK: | |
1351 | return 0; | |
1352 | case PHAN_INITIALIZE_FAILED: | |
1353 | goto out_err; | |
1354 | default: | |
1355 | break; | |
1356 | } | |
96acb6eb | 1357 | |
96f2ebd2 | 1358 | msleep(500); |
2956640d | 1359 | |
96f2ebd2 | 1360 | } while (--retries); |
2956640d | 1361 | |
96f2ebd2 | 1362 | NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); |
96acb6eb | 1363 | |
96f2ebd2 DP |
1364 | out_err: |
1365 | dev_warn(&adapter->pdev->dev, "firmware init failed\n"); | |
1366 | return -EIO; | |
3d396eb1 AK |
1367 | } |
1368 | ||
56a00787 DP |
1369 | static int |
1370 | netxen_receive_peg_ready(struct netxen_adapter *adapter) | |
2956640d DP |
1371 | { |
1372 | u32 val = 0; | |
1373 | int retries = 2000; | |
1374 | ||
1375 | do { | |
f98a9f69 | 1376 | val = NXRD32(adapter, CRB_RCVPEG_STATE); |
2956640d DP |
1377 | |
1378 | if (val == PHAN_PEG_RCV_INITIALIZED) | |
1379 | return 0; | |
1380 | ||
1381 | msleep(10); | |
1382 | ||
1383 | } while (--retries); | |
1384 | ||
1385 | if (!retries) { | |
1386 | printk(KERN_ERR "Receive Peg initialization not " | |
1387 | "complete, state: 0x%x.\n", val); | |
1388 | return -EIO; | |
1389 | } | |
1390 | ||
1391 | return 0; | |
1392 | } | |
1393 | ||
56a00787 DP |
1394 | int netxen_init_firmware(struct netxen_adapter *adapter) |
1395 | { | |
1396 | int err; | |
1397 | ||
1398 | err = netxen_receive_peg_ready(adapter); | |
1399 | if (err) | |
1400 | return err; | |
1401 | ||
f98a9f69 | 1402 | NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT); |
f98a9f69 DP |
1403 | NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE); |
1404 | NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK); | |
56a00787 | 1405 | |
f8e21f8f AKS |
1406 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) |
1407 | NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC); | |
1408 | ||
56a00787 DP |
1409 | return err; |
1410 | } | |
1411 | ||
3bf26ce3 DP |
1412 | static void |
1413 | netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg) | |
1414 | { | |
1415 | u32 cable_OUI; | |
1416 | u16 cable_len; | |
1417 | u16 link_speed; | |
1418 | u8 link_status, module, duplex, autoneg; | |
1419 | struct net_device *netdev = adapter->netdev; | |
1420 | ||
1421 | adapter->has_link_events = 1; | |
1422 | ||
1423 | cable_OUI = msg->body[1] & 0xffffffff; | |
1424 | cable_len = (msg->body[1] >> 32) & 0xffff; | |
1425 | link_speed = (msg->body[1] >> 48) & 0xffff; | |
1426 | ||
1427 | link_status = msg->body[2] & 0xff; | |
1428 | duplex = (msg->body[2] >> 16) & 0xff; | |
1429 | autoneg = (msg->body[2] >> 24) & 0xff; | |
1430 | ||
1431 | module = (msg->body[2] >> 8) & 0xff; | |
1432 | if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) { | |
1433 | printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n", | |
1434 | netdev->name, cable_OUI, cable_len); | |
1435 | } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) { | |
1436 | printk(KERN_INFO "%s: unsupported cable length %d\n", | |
1437 | netdev->name, cable_len); | |
1438 | } | |
1439 | ||
3bf26ce3 DP |
1440 | /* update link parameters */ |
1441 | if (duplex == LINKEVENT_FULL_DUPLEX) | |
1442 | adapter->link_duplex = DUPLEX_FULL; | |
1443 | else | |
1444 | adapter->link_duplex = DUPLEX_HALF; | |
1445 | adapter->module_type = module; | |
1446 | adapter->link_autoneg = autoneg; | |
1447 | adapter->link_speed = link_speed; | |
fa919833 FL |
1448 | |
1449 | netxen_advert_link_change(adapter, link_status); | |
3bf26ce3 DP |
1450 | } |
1451 | ||
1452 | static void | |
1453 | netxen_handle_fw_message(int desc_cnt, int index, | |
1454 | struct nx_host_sds_ring *sds_ring) | |
1455 | { | |
1456 | nx_fw_msg_t msg; | |
1457 | struct status_desc *desc; | |
1458 | int i = 0, opcode; | |
1459 | ||
1460 | while (desc_cnt > 0 && i < 8) { | |
1461 | desc = &sds_ring->desc_head[index]; | |
1462 | msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]); | |
1463 | msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]); | |
1464 | ||
1465 | index = get_next_index(index, sds_ring->num_desc); | |
1466 | desc_cnt--; | |
1467 | } | |
1468 | ||
1469 | opcode = netxen_get_nic_msg_opcode(msg.body[0]); | |
1470 | switch (opcode) { | |
1471 | case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE: | |
1472 | netxen_handle_linkevent(sds_ring->adapter, &msg); | |
1473 | break; | |
1474 | default: | |
1475 | break; | |
1476 | } | |
1477 | } | |
1478 | ||
d8b100c5 DP |
1479 | static int |
1480 | netxen_alloc_rx_skb(struct netxen_adapter *adapter, | |
1481 | struct nx_host_rds_ring *rds_ring, | |
1482 | struct netxen_rx_buffer *buffer) | |
1483 | { | |
1484 | struct sk_buff *skb; | |
1485 | dma_addr_t dma; | |
1486 | struct pci_dev *pdev = adapter->pdev; | |
1487 | ||
dae2e9f4 | 1488 | buffer->skb = netdev_alloc_skb(adapter->netdev, rds_ring->skb_size); |
d8b100c5 DP |
1489 | if (!buffer->skb) |
1490 | return 1; | |
1491 | ||
1492 | skb = buffer->skb; | |
1493 | ||
1494 | if (!adapter->ahw.cut_through) | |
1495 | skb_reserve(skb, 2); | |
1496 | ||
1497 | dma = pci_map_single(pdev, skb->data, | |
1498 | rds_ring->dma_size, PCI_DMA_FROMDEVICE); | |
1499 | ||
1500 | if (pci_dma_mapping_error(pdev, dma)) { | |
1501 | dev_kfree_skb_any(skb); | |
1502 | buffer->skb = NULL; | |
1503 | return 1; | |
1504 | } | |
1505 | ||
1506 | buffer->skb = skb; | |
1507 | buffer->dma = dma; | |
1508 | buffer->state = NETXEN_BUFFER_BUSY; | |
1509 | ||
1510 | return 0; | |
1511 | } | |
1512 | ||
d9e651bc DP |
1513 | static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter, |
1514 | struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum) | |
1515 | { | |
1516 | struct netxen_rx_buffer *buffer; | |
1517 | struct sk_buff *skb; | |
1518 | ||
1519 | buffer = &rds_ring->rx_buf_arr[index]; | |
1520 | ||
1521 | pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size, | |
1522 | PCI_DMA_FROMDEVICE); | |
1523 | ||
1524 | skb = buffer->skb; | |
1525 | if (!skb) | |
1526 | goto no_skb; | |
1527 | ||
066413da MM |
1528 | if (likely((adapter->netdev->features & NETIF_F_RXCSUM) |
1529 | && cksum == STATUS_CKSUM_OK)) { | |
d9e651bc DP |
1530 | adapter->stats.csummed++; |
1531 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1532 | } else | |
1533 | skb->ip_summed = CHECKSUM_NONE; | |
1534 | ||
d9e651bc | 1535 | buffer->skb = NULL; |
d9e651bc DP |
1536 | no_skb: |
1537 | buffer->state = NETXEN_BUFFER_FREE; | |
d9e651bc DP |
1538 | return skb; |
1539 | } | |
1540 | ||
d8b100c5 | 1541 | static struct netxen_rx_buffer * |
9b3ef55c | 1542 | netxen_process_rcv(struct netxen_adapter *adapter, |
c1c00ab8 DP |
1543 | struct nx_host_sds_ring *sds_ring, |
1544 | int ring, u64 sts_data0) | |
3d396eb1 | 1545 | { |
3176ff3e | 1546 | struct net_device *netdev = adapter->netdev; |
becf46a0 | 1547 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; |
3d396eb1 AK |
1548 | struct netxen_rx_buffer *buffer; |
1549 | struct sk_buff *skb; | |
c1c00ab8 DP |
1550 | struct nx_host_rds_ring *rds_ring; |
1551 | int index, length, cksum, pkt_offset; | |
3d396eb1 | 1552 | |
c1c00ab8 DP |
1553 | if (unlikely(ring >= adapter->max_rds_rings)) |
1554 | return NULL; | |
1555 | ||
1556 | rds_ring = &recv_ctx->rds_rings[ring]; | |
1557 | ||
1558 | index = netxen_get_sts_refhandle(sts_data0); | |
1559 | if (unlikely(index >= rds_ring->num_desc)) | |
d8b100c5 | 1560 | return NULL; |
438627c7 | 1561 | |
48bfd1e0 | 1562 | buffer = &rds_ring->rx_buf_arr[index]; |
3d396eb1 | 1563 | |
c1c00ab8 DP |
1564 | length = netxen_get_sts_totallength(sts_data0); |
1565 | cksum = netxen_get_sts_status(sts_data0); | |
1566 | pkt_offset = netxen_get_sts_pkt_offset(sts_data0); | |
1567 | ||
d9e651bc DP |
1568 | skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum); |
1569 | if (!skb) | |
d8b100c5 | 1570 | return buffer; |
200eef20 | 1571 | |
9b3ef55c DP |
1572 | if (length > rds_ring->skb_size) |
1573 | skb_put(skb, rds_ring->skb_size); | |
1574 | else | |
1575 | skb_put(skb, length); | |
d9e651bc | 1576 | |
9b3ef55c DP |
1577 | |
1578 | if (pkt_offset) | |
1579 | skb_pull(skb, pkt_offset); | |
ed25ffa1 | 1580 | |
3d396eb1 AK |
1581 | skb->protocol = eth_type_trans(skb, netdev); |
1582 | ||
a92e9e65 | 1583 | napi_gro_receive(&sds_ring->napi, skb); |
d9e651bc | 1584 | |
1bb482f8 | 1585 | adapter->stats.rx_pkts++; |
0ddc110c | 1586 | adapter->stats.rxbytes += length; |
d8b100c5 DP |
1587 | |
1588 | return buffer; | |
3d396eb1 AK |
1589 | } |
1590 | ||
c1c00ab8 DP |
1591 | #define TCP_HDR_SIZE 20 |
1592 | #define TCP_TS_OPTION_SIZE 12 | |
1593 | #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE) | |
1594 | ||
1595 | static struct netxen_rx_buffer * | |
1596 | netxen_process_lro(struct netxen_adapter *adapter, | |
1597 | struct nx_host_sds_ring *sds_ring, | |
1598 | int ring, u64 sts_data0, u64 sts_data1) | |
1599 | { | |
1600 | struct net_device *netdev = adapter->netdev; | |
1601 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; | |
1602 | struct netxen_rx_buffer *buffer; | |
1603 | struct sk_buff *skb; | |
1604 | struct nx_host_rds_ring *rds_ring; | |
1605 | struct iphdr *iph; | |
1606 | struct tcphdr *th; | |
1607 | bool push, timestamp; | |
1608 | int l2_hdr_offset, l4_hdr_offset; | |
1609 | int index; | |
1610 | u16 lro_length, length, data_offset; | |
1611 | u32 seq_number; | |
a7ffa289 | 1612 | u8 vhdr_len = 0; |
c1c00ab8 DP |
1613 | |
1614 | if (unlikely(ring > adapter->max_rds_rings)) | |
1615 | return NULL; | |
1616 | ||
1617 | rds_ring = &recv_ctx->rds_rings[ring]; | |
1618 | ||
1619 | index = netxen_get_lro_sts_refhandle(sts_data0); | |
1620 | if (unlikely(index > rds_ring->num_desc)) | |
1621 | return NULL; | |
1622 | ||
1623 | buffer = &rds_ring->rx_buf_arr[index]; | |
1624 | ||
1625 | timestamp = netxen_get_lro_sts_timestamp(sts_data0); | |
1626 | lro_length = netxen_get_lro_sts_length(sts_data0); | |
1627 | l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0); | |
1628 | l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0); | |
1629 | push = netxen_get_lro_sts_push_flag(sts_data0); | |
1630 | seq_number = netxen_get_lro_sts_seq_number(sts_data1); | |
1631 | ||
1632 | skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK); | |
1633 | if (!skb) | |
1634 | return buffer; | |
1635 | ||
1636 | if (timestamp) | |
1637 | data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE; | |
1638 | else | |
1639 | data_offset = l4_hdr_offset + TCP_HDR_SIZE; | |
1640 | ||
1641 | skb_put(skb, lro_length + data_offset); | |
1642 | ||
c1c00ab8 DP |
1643 | skb_pull(skb, l2_hdr_offset); |
1644 | skb->protocol = eth_type_trans(skb, netdev); | |
1645 | ||
57569d0e RB |
1646 | if (skb->protocol == htons(ETH_P_8021Q)) |
1647 | vhdr_len = VLAN_HLEN; | |
1648 | iph = (struct iphdr *)(skb->data + vhdr_len); | |
1649 | th = (struct tcphdr *)((skb->data + vhdr_len) + (iph->ihl << 2)); | |
c1c00ab8 DP |
1650 | |
1651 | length = (iph->ihl << 2) + (th->doff << 2) + lro_length; | |
1652 | iph->tot_len = htons(length); | |
1653 | iph->check = 0; | |
1654 | iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl); | |
1655 | th->psh = push; | |
1656 | th->seq = htonl(seq_number); | |
1657 | ||
1bb482f8 NK |
1658 | length = skb->len; |
1659 | ||
01da0c2b RB |
1660 | if (adapter->flags & NETXEN_FW_MSS_CAP) |
1661 | skb_shinfo(skb)->gso_size = netxen_get_lro_sts_mss(sts_data1); | |
1662 | ||
c1c00ab8 DP |
1663 | netif_receive_skb(skb); |
1664 | ||
1bb482f8 NK |
1665 | adapter->stats.lro_pkts++; |
1666 | adapter->stats.rxbytes += length; | |
1667 | ||
c1c00ab8 DP |
1668 | return buffer; |
1669 | } | |
1670 | ||
d8b100c5 DP |
1671 | #define netxen_merge_rx_buffers(list, head) \ |
1672 | do { list_splice_tail_init(list, head); } while (0); | |
1673 | ||
becf46a0 | 1674 | int |
d8b100c5 | 1675 | netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max) |
3d396eb1 | 1676 | { |
d8b100c5 DP |
1677 | struct netxen_adapter *adapter = sds_ring->adapter; |
1678 | ||
1679 | struct list_head *cur; | |
1680 | ||
0ddc110c | 1681 | struct status_desc *desc; |
d8b100c5 DP |
1682 | struct netxen_rx_buffer *rxbuf; |
1683 | ||
1684 | u32 consumer = sds_ring->consumer; | |
1685 | ||
9b3ef55c | 1686 | int count = 0; |
c1c00ab8 DP |
1687 | u64 sts_data0, sts_data1; |
1688 | int opcode, ring = 0, desc_cnt; | |
3d396eb1 | 1689 | |
3d396eb1 | 1690 | while (count < max) { |
d8b100c5 | 1691 | desc = &sds_ring->desc_head[consumer]; |
c1c00ab8 | 1692 | sts_data0 = le64_to_cpu(desc->status_desc_data[0]); |
0ddc110c | 1693 | |
c1c00ab8 | 1694 | if (!(sts_data0 & STATUS_OWNER_HOST)) |
3d396eb1 | 1695 | break; |
d9e651bc | 1696 | |
c1c00ab8 | 1697 | desc_cnt = netxen_get_sts_desc_cnt(sts_data0); |
3bf26ce3 | 1698 | |
c1c00ab8 | 1699 | opcode = netxen_get_sts_opcode(sts_data0); |
d9e651bc | 1700 | |
3bf26ce3 DP |
1701 | switch (opcode) { |
1702 | case NETXEN_NIC_RXPKT_DESC: | |
1703 | case NETXEN_OLD_RXPKT_DESC: | |
6598b169 | 1704 | case NETXEN_NIC_SYN_OFFLOAD: |
c1c00ab8 DP |
1705 | ring = netxen_get_sts_type(sts_data0); |
1706 | rxbuf = netxen_process_rcv(adapter, sds_ring, | |
1707 | ring, sts_data0); | |
1708 | break; | |
1709 | case NETXEN_NIC_LRO_DESC: | |
1710 | ring = netxen_get_lro_sts_type(sts_data0); | |
1711 | sts_data1 = le64_to_cpu(desc->status_desc_data[1]); | |
1712 | rxbuf = netxen_process_lro(adapter, sds_ring, | |
1713 | ring, sts_data0, sts_data1); | |
3bf26ce3 DP |
1714 | break; |
1715 | case NETXEN_NIC_RESPONSE_DESC: | |
1716 | netxen_handle_fw_message(desc_cnt, consumer, sds_ring); | |
1717 | default: | |
1718 | goto skip; | |
1719 | } | |
1720 | ||
1721 | WARN_ON(desc_cnt > 1); | |
1722 | ||
d8b100c5 DP |
1723 | if (rxbuf) |
1724 | list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]); | |
1725 | ||
3bf26ce3 DP |
1726 | skip: |
1727 | for (; desc_cnt > 0; desc_cnt--) { | |
1728 | desc = &sds_ring->desc_head[consumer]; | |
1729 | desc->status_desc_data[0] = | |
1730 | cpu_to_le64(STATUS_OWNER_PHANTOM); | |
1731 | consumer = get_next_index(consumer, sds_ring->num_desc); | |
1732 | } | |
3d396eb1 AK |
1733 | count++; |
1734 | } | |
0ddc110c | 1735 | |
d8b100c5 DP |
1736 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
1737 | struct nx_host_rds_ring *rds_ring = | |
1738 | &adapter->recv_ctx.rds_rings[ring]; | |
1739 | ||
1740 | if (!list_empty(&sds_ring->free_list[ring])) { | |
1741 | list_for_each(cur, &sds_ring->free_list[ring]) { | |
1742 | rxbuf = list_entry(cur, | |
1743 | struct netxen_rx_buffer, list); | |
1744 | netxen_alloc_rx_skb(adapter, rds_ring, rxbuf); | |
1745 | } | |
1746 | spin_lock(&rds_ring->lock); | |
1747 | netxen_merge_rx_buffers(&sds_ring->free_list[ring], | |
1748 | &rds_ring->free_list); | |
1749 | spin_unlock(&rds_ring->lock); | |
1750 | } | |
1751 | ||
1752 | netxen_post_rx_buffers_nodb(adapter, rds_ring); | |
1753 | } | |
3d396eb1 | 1754 | |
3d396eb1 | 1755 | if (count) { |
d8b100c5 | 1756 | sds_ring->consumer = consumer; |
195c5f98 | 1757 | NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer); |
3d396eb1 AK |
1758 | } |
1759 | ||
1760 | return count; | |
1761 | } | |
1762 | ||
1763 | /* Process Command status ring */ | |
05aaa02d | 1764 | int netxen_process_cmd_ring(struct netxen_adapter *adapter) |
3d396eb1 | 1765 | { |
d877f1e3 | 1766 | u32 sw_consumer, hw_consumer; |
ba53e6b4 | 1767 | int count = 0, i; |
3d396eb1 | 1768 | struct netxen_cmd_buffer *buffer; |
ba53e6b4 DP |
1769 | struct pci_dev *pdev = adapter->pdev; |
1770 | struct net_device *netdev = adapter->netdev; | |
3d396eb1 | 1771 | struct netxen_skb_frag *frag; |
ba53e6b4 | 1772 | int done = 0; |
4ea528a1 | 1773 | struct nx_host_tx_ring *tx_ring = adapter->tx_ring; |
3d396eb1 | 1774 | |
d8b100c5 DP |
1775 | if (!spin_trylock(&adapter->tx_clean_lock)) |
1776 | return 1; | |
1777 | ||
d877f1e3 | 1778 | sw_consumer = tx_ring->sw_consumer; |
d877f1e3 | 1779 | hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer)); |
3d396eb1 | 1780 | |
d877f1e3 DP |
1781 | while (sw_consumer != hw_consumer) { |
1782 | buffer = &tx_ring->cmd_buf_arr[sw_consumer]; | |
53a01e00 | 1783 | if (buffer->skb) { |
1784 | frag = &buffer->frag_array[0]; | |
3d396eb1 AK |
1785 | pci_unmap_single(pdev, frag->dma, frag->length, |
1786 | PCI_DMA_TODEVICE); | |
96acb6eb | 1787 | frag->dma = 0ULL; |
3d396eb1 | 1788 | for (i = 1; i < buffer->frag_count; i++) { |
3d396eb1 AK |
1789 | frag++; /* Get the next frag */ |
1790 | pci_unmap_page(pdev, frag->dma, frag->length, | |
1791 | PCI_DMA_TODEVICE); | |
96acb6eb | 1792 | frag->dma = 0ULL; |
3d396eb1 AK |
1793 | } |
1794 | ||
ba53e6b4 | 1795 | adapter->stats.xmitfinished++; |
53a01e00 | 1796 | dev_kfree_skb_any(buffer->skb); |
1797 | buffer->skb = NULL; | |
3d396eb1 AK |
1798 | } |
1799 | ||
d877f1e3 | 1800 | sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc); |
ba53e6b4 DP |
1801 | if (++count >= MAX_STATUS_HANDLE) |
1802 | break; | |
3d396eb1 | 1803 | } |
3d396eb1 | 1804 | |
22527864 | 1805 | if (count && netif_running(netdev)) { |
cb2107be DP |
1806 | tx_ring->sw_consumer = sw_consumer; |
1807 | ||
ba53e6b4 | 1808 | smp_mb(); |
cb2107be | 1809 | |
7a9905e6 RB |
1810 | if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) |
1811 | if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) | |
cb2107be | 1812 | netif_wake_queue(netdev); |
7a9905e6 | 1813 | adapter->tx_timeo_cnt = 0; |
3d396eb1 | 1814 | } |
ed25ffa1 AK |
1815 | /* |
1816 | * If everything is freed up to consumer then check if the ring is full | |
1817 | * If the ring is full then check if more needs to be freed and | |
1818 | * schedule the call back again. | |
1819 | * | |
1820 | * This happens when there are 2 CPUs. One could be freeing and the | |
1821 | * other filling it. If the ring is full when we get out of here and | |
1822 | * the card has already interrupted the host then the host can miss the | |
1823 | * interrupt. | |
1824 | * | |
1825 | * There is still a possible race condition and the host could miss an | |
1826 | * interrupt. The card has to take care of this. | |
1827 | */ | |
d877f1e3 DP |
1828 | hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer)); |
1829 | done = (sw_consumer == hw_consumer); | |
d8b100c5 | 1830 | spin_unlock(&adapter->tx_clean_lock); |
3d396eb1 | 1831 | |
807540ba | 1832 | return done; |
3d396eb1 AK |
1833 | } |
1834 | ||
becf46a0 | 1835 | void |
d8b100c5 DP |
1836 | netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid, |
1837 | struct nx_host_rds_ring *rds_ring) | |
3d396eb1 | 1838 | { |
3d396eb1 AK |
1839 | struct rcv_desc *pdesc; |
1840 | struct netxen_rx_buffer *buffer; | |
d8b100c5 | 1841 | int producer, count = 0; |
ed25ffa1 | 1842 | netxen_ctx_msg msg = 0; |
d9e651bc | 1843 | struct list_head *head; |
3d396eb1 | 1844 | |
48bfd1e0 | 1845 | producer = rds_ring->producer; |
d9e651bc | 1846 | |
d8b100c5 | 1847 | head = &rds_ring->free_list; |
d9e651bc DP |
1848 | while (!list_empty(head)) { |
1849 | ||
d8b100c5 | 1850 | buffer = list_entry(head->next, struct netxen_rx_buffer, list); |
6f703406 | 1851 | |
d8b100c5 DP |
1852 | if (!buffer->skb) { |
1853 | if (netxen_alloc_rx_skb(adapter, rds_ring, buffer)) | |
1854 | break; | |
6f703406 DP |
1855 | } |
1856 | ||
1857 | count++; | |
d9e651bc DP |
1858 | list_del(&buffer->list); |
1859 | ||
ed25ffa1 | 1860 | /* make a rcv descriptor */ |
6f703406 | 1861 | pdesc = &rds_ring->desc_head[producer]; |
d8b100c5 | 1862 | pdesc->addr_buffer = cpu_to_le64(buffer->dma); |
ed33ebe4 | 1863 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
48bfd1e0 | 1864 | pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size); |
6f703406 | 1865 | |
438627c7 | 1866 | producer = get_next_index(producer, rds_ring->num_desc); |
ed25ffa1 | 1867 | } |
9b3ef55c | 1868 | |
ed25ffa1 | 1869 | if (count) { |
48bfd1e0 | 1870 | rds_ring->producer = producer; |
195c5f98 | 1871 | NXWRIO(adapter, rds_ring->crb_rcv_producer, |
438627c7 | 1872 | (producer-1) & (rds_ring->num_desc-1)); |
48bfd1e0 | 1873 | |
4f96b988 | 1874 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
ed25ffa1 AK |
1875 | /* |
1876 | * Write a doorbell msg to tell phanmon of change in | |
1877 | * receive ring producer | |
48bfd1e0 | 1878 | * Only for firmware version < 4.0.0 |
ed25ffa1 AK |
1879 | */ |
1880 | netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID); | |
1881 | netxen_set_msg_privid(msg); | |
1882 | netxen_set_msg_count(msg, | |
438627c7 DP |
1883 | ((producer - 1) & |
1884 | (rds_ring->num_desc - 1))); | |
3176ff3e | 1885 | netxen_set_msg_ctxid(msg, adapter->portnum); |
ed25ffa1 | 1886 | netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid)); |
f03b0ebd DP |
1887 | NXWRIO(adapter, DB_NORMALIZE(adapter, |
1888 | NETXEN_RCV_PRODUCER_OFFSET), msg); | |
48bfd1e0 | 1889 | } |
ed25ffa1 AK |
1890 | } |
1891 | } | |
1892 | ||
becf46a0 | 1893 | static void |
d8b100c5 DP |
1894 | netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, |
1895 | struct nx_host_rds_ring *rds_ring) | |
ed25ffa1 | 1896 | { |
ed25ffa1 AK |
1897 | struct rcv_desc *pdesc; |
1898 | struct netxen_rx_buffer *buffer; | |
d8b100c5 | 1899 | int producer, count = 0; |
d9e651bc | 1900 | struct list_head *head; |
ed25ffa1 | 1901 | |
d8b100c5 DP |
1902 | if (!spin_trylock(&rds_ring->lock)) |
1903 | return; | |
1904 | ||
2227bae2 AKS |
1905 | producer = rds_ring->producer; |
1906 | ||
d9e651bc | 1907 | head = &rds_ring->free_list; |
d9e651bc DP |
1908 | while (!list_empty(head)) { |
1909 | ||
d8b100c5 | 1910 | buffer = list_entry(head->next, struct netxen_rx_buffer, list); |
6f703406 | 1911 | |
d8b100c5 DP |
1912 | if (!buffer->skb) { |
1913 | if (netxen_alloc_rx_skb(adapter, rds_ring, buffer)) | |
1914 | break; | |
6f703406 DP |
1915 | } |
1916 | ||
1917 | count++; | |
d9e651bc DP |
1918 | list_del(&buffer->list); |
1919 | ||
3d396eb1 | 1920 | /* make a rcv descriptor */ |
6f703406 | 1921 | pdesc = &rds_ring->desc_head[producer]; |
ed33ebe4 | 1922 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
48bfd1e0 | 1923 | pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size); |
3d396eb1 | 1924 | pdesc->addr_buffer = cpu_to_le64(buffer->dma); |
6f703406 | 1925 | |
438627c7 | 1926 | producer = get_next_index(producer, rds_ring->num_desc); |
3d396eb1 AK |
1927 | } |
1928 | ||
3d396eb1 | 1929 | if (count) { |
48bfd1e0 | 1930 | rds_ring->producer = producer; |
195c5f98 | 1931 | NXWRIO(adapter, rds_ring->crb_rcv_producer, |
438627c7 | 1932 | (producer - 1) & (rds_ring->num_desc - 1)); |
3d396eb1 | 1933 | } |
d8b100c5 | 1934 | spin_unlock(&rds_ring->lock); |
3d396eb1 AK |
1935 | } |
1936 | ||
3d396eb1 AK |
1937 | void netxen_nic_clear_stats(struct netxen_adapter *adapter) |
1938 | { | |
3d396eb1 | 1939 | memset(&adapter->stats, 0, sizeof(adapter->stats)); |
3d396eb1 AK |
1940 | } |
1941 |