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fe56b9e6 YM |
1 | /* QLogic qed NIC Driver |
2 | * Copyright (c) 2015 QLogic Corporation | |
3 | * | |
4 | * This software is available under the terms of the GNU General Public License | |
5 | * (GPL) Version 2, available from the file COPYING in the main directory of | |
6 | * this source tree. | |
7 | */ | |
8 | ||
9 | #include <linux/types.h> | |
10 | #include <linux/bitops.h> | |
11 | #include <linux/dma-mapping.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/log2.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/bitops.h> | |
20 | #include "qed.h" | |
21 | #include "qed_cxt.h" | |
22 | #include "qed_dev_api.h" | |
23 | #include "qed_hsi.h" | |
24 | #include "qed_hw.h" | |
25 | #include "qed_init_ops.h" | |
26 | #include "qed_reg_addr.h" | |
1408cc1f | 27 | #include "qed_sriov.h" |
fe56b9e6 YM |
28 | |
29 | /* Max number of connection types in HW (DQ/CDU etc.) */ | |
30 | #define MAX_CONN_TYPES PROTOCOLID_COMMON | |
31 | #define NUM_TASK_TYPES 2 | |
32 | #define NUM_TASK_PF_SEGMENTS 4 | |
1408cc1f | 33 | #define NUM_TASK_VF_SEGMENTS 1 |
fe56b9e6 YM |
34 | |
35 | /* QM constants */ | |
36 | #define QM_PQ_ELEMENT_SIZE 4 /* in bytes */ | |
37 | ||
38 | /* Doorbell-Queue constants */ | |
39 | #define DQ_RANGE_SHIFT 4 | |
40 | #define DQ_RANGE_ALIGN BIT(DQ_RANGE_SHIFT) | |
41 | ||
dbb799c3 YM |
42 | /* Searcher constants */ |
43 | #define SRC_MIN_NUM_ELEMS 256 | |
44 | ||
45 | /* Timers constants */ | |
46 | #define TM_SHIFT 7 | |
47 | #define TM_ALIGN BIT(TM_SHIFT) | |
48 | #define TM_ELEM_SIZE 4 | |
49 | ||
fe56b9e6 YM |
50 | /* ILT constants */ |
51 | #define ILT_DEFAULT_HW_P_SIZE 3 | |
52 | #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12)) | |
53 | #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET | |
54 | ||
55 | /* ILT entry structure */ | |
56 | #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL | |
57 | #define ILT_ENTRY_PHY_ADDR_SHIFT 0 | |
58 | #define ILT_ENTRY_VALID_MASK 0x1ULL | |
59 | #define ILT_ENTRY_VALID_SHIFT 52 | |
60 | #define ILT_ENTRY_IN_REGS 2 | |
61 | #define ILT_REG_SIZE_IN_BYTES 4 | |
62 | ||
63 | /* connection context union */ | |
64 | union conn_context { | |
65 | struct core_conn_context core_ctx; | |
66 | struct eth_conn_context eth_ctx; | |
dbb799c3 YM |
67 | struct iscsi_conn_context iscsi_ctx; |
68 | struct roce_conn_context roce_ctx; | |
69 | }; | |
70 | ||
71 | /* TYPE-0 task context - iSCSI */ | |
72 | union type0_task_context { | |
73 | struct iscsi_task_context iscsi_ctx; | |
fe56b9e6 YM |
74 | }; |
75 | ||
dbb799c3 YM |
76 | /* TYPE-1 task context - ROCE */ |
77 | union type1_task_context { | |
78 | struct rdma_task_context roce_ctx; | |
79 | }; | |
80 | ||
81 | struct src_ent { | |
82 | u8 opaque[56]; | |
83 | u64 next; | |
84 | }; | |
85 | ||
86 | #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */ | |
87 | #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12)) | |
88 | ||
fe56b9e6 YM |
89 | #define CONN_CXT_SIZE(p_hwfn) \ |
90 | ALIGNED_TYPE_SIZE(union conn_context, p_hwfn) | |
91 | ||
dbb799c3 YM |
92 | #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context)) |
93 | ||
94 | #define TYPE0_TASK_CXT_SIZE(p_hwfn) \ | |
95 | ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn) | |
96 | ||
97 | /* Alignment is inherent to the type1_task_context structure */ | |
98 | #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context) | |
99 | ||
fe56b9e6 | 100 | /* PF per protocl configuration object */ |
dbb799c3 YM |
101 | #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS) |
102 | #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS) | |
103 | ||
104 | struct qed_tid_seg { | |
105 | u32 count; | |
106 | u8 type; | |
107 | bool has_fl_mem; | |
108 | }; | |
109 | ||
fe56b9e6 YM |
110 | struct qed_conn_type_cfg { |
111 | u32 cid_count; | |
112 | u32 cid_start; | |
1408cc1f | 113 | u32 cids_per_vf; |
dbb799c3 | 114 | struct qed_tid_seg tid_seg[TASK_SEGMENTS]; |
fe56b9e6 YM |
115 | }; |
116 | ||
117 | /* ILT Client configuration, Per connection type (protocol) resources. */ | |
118 | #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2) | |
1408cc1f | 119 | #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2) |
fe56b9e6 | 120 | #define CDUC_BLK (0) |
dbb799c3 YM |
121 | #define SRQ_BLK (0) |
122 | #define CDUT_SEG_BLK(n) (1 + (u8)(n)) | |
123 | #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_ ## X ## _SEGMENTS) | |
fe56b9e6 YM |
124 | |
125 | enum ilt_clients { | |
126 | ILT_CLI_CDUC, | |
dbb799c3 | 127 | ILT_CLI_CDUT, |
fe56b9e6 | 128 | ILT_CLI_QM, |
dbb799c3 YM |
129 | ILT_CLI_TM, |
130 | ILT_CLI_SRC, | |
131 | ILT_CLI_TSDM, | |
fe56b9e6 YM |
132 | ILT_CLI_MAX |
133 | }; | |
134 | ||
135 | struct ilt_cfg_pair { | |
136 | u32 reg; | |
137 | u32 val; | |
138 | }; | |
139 | ||
140 | struct qed_ilt_cli_blk { | |
141 | u32 total_size; /* 0 means not active */ | |
142 | u32 real_size_in_page; | |
143 | u32 start_line; | |
dbb799c3 | 144 | u32 dynamic_line_cnt; |
fe56b9e6 YM |
145 | }; |
146 | ||
147 | struct qed_ilt_client_cfg { | |
148 | bool active; | |
149 | ||
150 | /* ILT boundaries */ | |
151 | struct ilt_cfg_pair first; | |
152 | struct ilt_cfg_pair last; | |
153 | struct ilt_cfg_pair p_size; | |
154 | ||
155 | /* ILT client blocks for PF */ | |
156 | struct qed_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS]; | |
157 | u32 pf_total_lines; | |
1408cc1f YM |
158 | |
159 | /* ILT client blocks for VFs */ | |
160 | struct qed_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS]; | |
161 | u32 vf_total_lines; | |
fe56b9e6 YM |
162 | }; |
163 | ||
164 | /* Per Path - | |
165 | * ILT shadow table | |
166 | * Protocol acquired CID lists | |
167 | * PF start line in ILT | |
168 | */ | |
169 | struct qed_dma_mem { | |
170 | dma_addr_t p_phys; | |
171 | void *p_virt; | |
172 | size_t size; | |
173 | }; | |
174 | ||
175 | struct qed_cid_acquired_map { | |
176 | u32 start_cid; | |
177 | u32 max_count; | |
178 | unsigned long *cid_map; | |
179 | }; | |
180 | ||
181 | struct qed_cxt_mngr { | |
182 | /* Per protocl configuration */ | |
183 | struct qed_conn_type_cfg conn_cfg[MAX_CONN_TYPES]; | |
184 | ||
185 | /* computed ILT structure */ | |
186 | struct qed_ilt_client_cfg clients[ILT_CLI_MAX]; | |
187 | ||
dbb799c3 YM |
188 | /* Task type sizes */ |
189 | u32 task_type_size[NUM_TASK_TYPES]; | |
190 | ||
1408cc1f YM |
191 | /* total number of VFs for this hwfn - |
192 | * ALL VFs are symmetric in terms of HW resources | |
193 | */ | |
194 | u32 vf_count; | |
195 | ||
dbb799c3 YM |
196 | /* total number of SRQ's for this hwfn */ |
197 | u32 srq_count; | |
198 | ||
fe56b9e6 YM |
199 | /* Acquired CIDs */ |
200 | struct qed_cid_acquired_map acquired[MAX_CONN_TYPES]; | |
201 | ||
202 | /* ILT shadow table */ | |
203 | struct qed_dma_mem *ilt_shadow; | |
204 | u32 pf_start_line; | |
dbb799c3 YM |
205 | |
206 | /* Mutex for a dynamic ILT allocation */ | |
207 | struct mutex mutex; | |
208 | ||
209 | /* SRC T2 */ | |
210 | struct qed_dma_mem *t2; | |
211 | u32 t2_num_pages; | |
212 | u64 first_free; | |
213 | u64 last_free; | |
fe56b9e6 | 214 | }; |
dbb799c3 YM |
215 | static bool src_proto(enum protocol_type type) |
216 | { | |
217 | return type == PROTOCOLID_ISCSI || | |
218 | type == PROTOCOLID_ROCE; | |
219 | } | |
220 | ||
221 | static bool tm_cid_proto(enum protocol_type type) | |
222 | { | |
223 | return type == PROTOCOLID_ISCSI || | |
224 | type == PROTOCOLID_ROCE; | |
225 | } | |
fe56b9e6 | 226 | |
1408cc1f YM |
227 | /* counts the iids for the CDU/CDUC ILT client configuration */ |
228 | struct qed_cdu_iids { | |
229 | u32 pf_cids; | |
230 | u32 per_vf_cids; | |
231 | }; | |
fe56b9e6 | 232 | |
1408cc1f YM |
233 | static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr, |
234 | struct qed_cdu_iids *iids) | |
235 | { | |
236 | u32 type; | |
fe56b9e6 | 237 | |
1408cc1f YM |
238 | for (type = 0; type < MAX_CONN_TYPES; type++) { |
239 | iids->pf_cids += p_mngr->conn_cfg[type].cid_count; | |
240 | iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf; | |
241 | } | |
fe56b9e6 YM |
242 | } |
243 | ||
dbb799c3 YM |
244 | /* counts the iids for the Searcher block configuration */ |
245 | struct qed_src_iids { | |
246 | u32 pf_cids; | |
247 | u32 per_vf_cids; | |
248 | }; | |
249 | ||
250 | static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr, | |
251 | struct qed_src_iids *iids) | |
252 | { | |
253 | u32 i; | |
254 | ||
255 | for (i = 0; i < MAX_CONN_TYPES; i++) { | |
256 | if (!src_proto(i)) | |
257 | continue; | |
258 | ||
259 | iids->pf_cids += p_mngr->conn_cfg[i].cid_count; | |
260 | iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf; | |
261 | } | |
262 | } | |
263 | ||
264 | /* counts the iids for the Timers block configuration */ | |
265 | struct qed_tm_iids { | |
266 | u32 pf_cids; | |
267 | u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */ | |
268 | u32 pf_tids_total; | |
269 | u32 per_vf_cids; | |
270 | u32 per_vf_tids; | |
271 | }; | |
272 | ||
273 | static void qed_cxt_tm_iids(struct qed_cxt_mngr *p_mngr, | |
274 | struct qed_tm_iids *iids) | |
275 | { | |
276 | u32 i, j; | |
277 | ||
278 | for (i = 0; i < MAX_CONN_TYPES; i++) { | |
279 | struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i]; | |
280 | ||
281 | if (tm_cid_proto(i)) { | |
282 | iids->pf_cids += p_cfg->cid_count; | |
283 | iids->per_vf_cids += p_cfg->cids_per_vf; | |
284 | } | |
285 | } | |
286 | ||
287 | iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN); | |
288 | iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN); | |
289 | iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN); | |
290 | ||
291 | for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) { | |
292 | iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN); | |
293 | iids->pf_tids_total += iids->pf_tids[j]; | |
294 | } | |
295 | } | |
296 | ||
fe56b9e6 YM |
297 | static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn, |
298 | struct qed_qm_iids *iids) | |
299 | { | |
300 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
dbb799c3 YM |
301 | struct qed_tid_seg *segs; |
302 | u32 vf_cids = 0, type, j; | |
303 | u32 vf_tids = 0; | |
fe56b9e6 | 304 | |
1408cc1f | 305 | for (type = 0; type < MAX_CONN_TYPES; type++) { |
fe56b9e6 | 306 | iids->cids += p_mngr->conn_cfg[type].cid_count; |
1408cc1f | 307 | vf_cids += p_mngr->conn_cfg[type].cids_per_vf; |
dbb799c3 YM |
308 | |
309 | segs = p_mngr->conn_cfg[type].tid_seg; | |
310 | /* for each segment there is at most one | |
311 | * protocol for which count is not 0. | |
312 | */ | |
313 | for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) | |
314 | iids->tids += segs[j].count; | |
315 | ||
316 | /* The last array elelment is for the VFs. As for PF | |
317 | * segments there can be only one protocol for | |
318 | * which this value is not 0. | |
319 | */ | |
320 | vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; | |
1408cc1f | 321 | } |
fe56b9e6 | 322 | |
1408cc1f | 323 | iids->vf_cids += vf_cids * p_mngr->vf_count; |
dbb799c3 YM |
324 | iids->tids += vf_tids * p_mngr->vf_count; |
325 | ||
1408cc1f | 326 | DP_VERBOSE(p_hwfn, QED_MSG_ILT, |
dbb799c3 YM |
327 | "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n", |
328 | iids->cids, iids->vf_cids, iids->tids, vf_tids); | |
329 | } | |
330 | ||
331 | static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn, | |
332 | u32 seg) | |
333 | { | |
334 | struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr; | |
335 | u32 i; | |
336 | ||
337 | /* Find the protocol with tid count > 0 for this segment. | |
338 | * Note: there can only be one and this is already validated. | |
339 | */ | |
340 | for (i = 0; i < MAX_CONN_TYPES; i++) | |
341 | if (p_cfg->conn_cfg[i].tid_seg[seg].count) | |
342 | return &p_cfg->conn_cfg[i].tid_seg[seg]; | |
343 | return NULL; | |
344 | } | |
345 | ||
346 | void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, u32 num_srqs) | |
347 | { | |
348 | struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; | |
349 | ||
350 | p_mgr->srq_count = num_srqs; | |
351 | } | |
352 | ||
353 | u32 qed_cxt_get_srq_count(struct qed_hwfn *p_hwfn) | |
354 | { | |
355 | struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; | |
356 | ||
357 | return p_mgr->srq_count; | |
fe56b9e6 YM |
358 | } |
359 | ||
360 | /* set the iids count per protocol */ | |
361 | static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn, | |
362 | enum protocol_type type, | |
1408cc1f | 363 | u32 cid_count, u32 vf_cid_cnt) |
fe56b9e6 YM |
364 | { |
365 | struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; | |
366 | struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type]; | |
367 | ||
368 | p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN); | |
1408cc1f | 369 | p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN); |
dbb799c3 YM |
370 | |
371 | if (type == PROTOCOLID_ROCE) { | |
372 | u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val; | |
373 | u32 cxt_size = CONN_CXT_SIZE(p_hwfn); | |
374 | u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; | |
375 | ||
376 | p_conn->cid_count = roundup(p_conn->cid_count, elems_per_page); | |
377 | } | |
1408cc1f YM |
378 | } |
379 | ||
380 | u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn, | |
381 | enum protocol_type type, | |
382 | u32 *vf_cid) | |
383 | { | |
384 | if (vf_cid) | |
385 | *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf; | |
386 | ||
387 | return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count; | |
fe56b9e6 YM |
388 | } |
389 | ||
dbb799c3 YM |
390 | u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn, |
391 | enum protocol_type type) | |
392 | { | |
393 | return p_hwfn->p_cxt_mngr->acquired[type].start_cid; | |
394 | } | |
395 | ||
396 | u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn, | |
397 | enum protocol_type type) | |
398 | { | |
399 | u32 cnt = 0; | |
400 | int i; | |
401 | ||
402 | for (i = 0; i < TASK_SEGMENTS; i++) | |
403 | cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count; | |
404 | ||
405 | return cnt; | |
406 | } | |
407 | ||
408 | static void | |
409 | qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn, | |
410 | enum protocol_type proto, | |
411 | u8 seg, u8 seg_type, u32 count, bool has_fl) | |
412 | { | |
413 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
414 | struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg]; | |
415 | ||
416 | p_seg->count = count; | |
417 | p_seg->has_fl_mem = has_fl; | |
418 | p_seg->type = seg_type; | |
419 | } | |
420 | ||
fe56b9e6 YM |
421 | static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli, |
422 | struct qed_ilt_cli_blk *p_blk, | |
423 | u32 start_line, u32 total_size, | |
424 | u32 elem_size) | |
425 | { | |
426 | u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); | |
427 | ||
428 | /* verify thatits called only once for each block */ | |
429 | if (p_blk->total_size) | |
430 | return; | |
431 | ||
432 | p_blk->total_size = total_size; | |
433 | p_blk->real_size_in_page = 0; | |
434 | if (elem_size) | |
435 | p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size; | |
436 | p_blk->start_line = start_line; | |
437 | } | |
438 | ||
439 | static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn, | |
440 | struct qed_ilt_client_cfg *p_cli, | |
441 | struct qed_ilt_cli_blk *p_blk, | |
442 | u32 *p_line, enum ilt_clients client_id) | |
443 | { | |
444 | if (!p_blk->total_size) | |
445 | return; | |
446 | ||
447 | if (!p_cli->active) | |
448 | p_cli->first.val = *p_line; | |
449 | ||
450 | p_cli->active = true; | |
451 | *p_line += DIV_ROUND_UP(p_blk->total_size, | |
452 | p_blk->real_size_in_page); | |
453 | p_cli->last.val = *p_line - 1; | |
454 | ||
455 | DP_VERBOSE(p_hwfn, QED_MSG_ILT, | |
456 | "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n", | |
457 | client_id, p_cli->first.val, | |
458 | p_cli->last.val, p_blk->total_size, | |
459 | p_blk->real_size_in_page, p_blk->start_line); | |
460 | } | |
461 | ||
dbb799c3 YM |
462 | static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn, |
463 | enum ilt_clients ilt_client) | |
464 | { | |
465 | u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count; | |
466 | struct qed_ilt_client_cfg *p_cli; | |
467 | u32 lines_to_skip = 0; | |
468 | u32 cxts_per_p; | |
469 | ||
470 | if (ilt_client == ILT_CLI_CDUC) { | |
471 | p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; | |
472 | ||
473 | cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) / | |
474 | (u32) CONN_CXT_SIZE(p_hwfn); | |
475 | ||
476 | lines_to_skip = cid_count / cxts_per_p; | |
477 | } | |
478 | ||
479 | return lines_to_skip; | |
480 | } | |
481 | ||
fe56b9e6 YM |
482 | int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn) |
483 | { | |
484 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
dbb799c3 | 485 | u32 curr_line, total, i, task_size, line; |
fe56b9e6 YM |
486 | struct qed_ilt_client_cfg *p_cli; |
487 | struct qed_ilt_cli_blk *p_blk; | |
1408cc1f | 488 | struct qed_cdu_iids cdu_iids; |
dbb799c3 | 489 | struct qed_src_iids src_iids; |
fe56b9e6 | 490 | struct qed_qm_iids qm_iids; |
dbb799c3 YM |
491 | struct qed_tm_iids tm_iids; |
492 | struct qed_tid_seg *p_seg; | |
fe56b9e6 YM |
493 | |
494 | memset(&qm_iids, 0, sizeof(qm_iids)); | |
1408cc1f | 495 | memset(&cdu_iids, 0, sizeof(cdu_iids)); |
dbb799c3 YM |
496 | memset(&src_iids, 0, sizeof(src_iids)); |
497 | memset(&tm_iids, 0, sizeof(tm_iids)); | |
fe56b9e6 YM |
498 | |
499 | p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT); | |
500 | ||
501 | DP_VERBOSE(p_hwfn, QED_MSG_ILT, | |
502 | "hwfn [%d] - Set context manager starting line to be 0x%08x\n", | |
503 | p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line); | |
504 | ||
505 | /* CDUC */ | |
506 | p_cli = &p_mngr->clients[ILT_CLI_CDUC]; | |
507 | curr_line = p_mngr->pf_start_line; | |
1408cc1f YM |
508 | |
509 | /* CDUC PF */ | |
fe56b9e6 YM |
510 | p_cli->pf_total_lines = 0; |
511 | ||
512 | /* get the counters for the CDUC and QM clients */ | |
1408cc1f | 513 | qed_cxt_cdu_iids(p_mngr, &cdu_iids); |
fe56b9e6 YM |
514 | |
515 | p_blk = &p_cli->pf_blks[CDUC_BLK]; | |
516 | ||
1408cc1f | 517 | total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn); |
fe56b9e6 YM |
518 | |
519 | qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, | |
520 | total, CONN_CXT_SIZE(p_hwfn)); | |
521 | ||
522 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); | |
523 | p_cli->pf_total_lines = curr_line - p_blk->start_line; | |
524 | ||
dbb799c3 YM |
525 | p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn, |
526 | ILT_CLI_CDUC); | |
527 | ||
1408cc1f YM |
528 | /* CDUC VF */ |
529 | p_blk = &p_cli->vf_blks[CDUC_BLK]; | |
530 | total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn); | |
531 | ||
532 | qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, | |
533 | total, CONN_CXT_SIZE(p_hwfn)); | |
534 | ||
535 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); | |
536 | p_cli->vf_total_lines = curr_line - p_blk->start_line; | |
537 | ||
538 | for (i = 1; i < p_mngr->vf_count; i++) | |
539 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, | |
540 | ILT_CLI_CDUC); | |
541 | ||
dbb799c3 YM |
542 | /* CDUT PF */ |
543 | p_cli = &p_mngr->clients[ILT_CLI_CDUT]; | |
544 | p_cli->first.val = curr_line; | |
545 | ||
546 | /* first the 'working' task memory */ | |
547 | for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { | |
548 | p_seg = qed_cxt_tid_seg_info(p_hwfn, i); | |
549 | if (!p_seg || p_seg->count == 0) | |
550 | continue; | |
551 | ||
552 | p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)]; | |
553 | total = p_seg->count * p_mngr->task_type_size[p_seg->type]; | |
554 | qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total, | |
555 | p_mngr->task_type_size[p_seg->type]); | |
556 | ||
557 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, | |
558 | ILT_CLI_CDUT); | |
559 | } | |
560 | ||
561 | /* next the 'init' task memory (forced load memory) */ | |
562 | for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { | |
563 | p_seg = qed_cxt_tid_seg_info(p_hwfn, i); | |
564 | if (!p_seg || p_seg->count == 0) | |
565 | continue; | |
566 | ||
567 | p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]; | |
568 | ||
569 | if (!p_seg->has_fl_mem) { | |
570 | /* The segment is active (total size pf 'working' | |
571 | * memory is > 0) but has no FL (forced-load, Init) | |
572 | * memory. Thus: | |
573 | * | |
574 | * 1. The total-size in the corrsponding FL block of | |
575 | * the ILT client is set to 0 - No ILT line are | |
576 | * provisioned and no ILT memory allocated. | |
577 | * | |
578 | * 2. The start-line of said block is set to the | |
579 | * start line of the matching working memory | |
580 | * block in the ILT client. This is later used to | |
581 | * configure the CDU segment offset registers and | |
582 | * results in an FL command for TIDs of this | |
583 | * segement behaves as regular load commands | |
584 | * (loading TIDs from the working memory). | |
585 | */ | |
586 | line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line; | |
587 | ||
588 | qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); | |
589 | continue; | |
590 | } | |
591 | total = p_seg->count * p_mngr->task_type_size[p_seg->type]; | |
592 | ||
593 | qed_ilt_cli_blk_fill(p_cli, p_blk, | |
594 | curr_line, total, | |
595 | p_mngr->task_type_size[p_seg->type]); | |
596 | ||
597 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, | |
598 | ILT_CLI_CDUT); | |
599 | } | |
600 | p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line; | |
601 | ||
602 | /* CDUT VF */ | |
603 | p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF); | |
604 | if (p_seg && p_seg->count) { | |
605 | /* Stricly speaking we need to iterate over all VF | |
606 | * task segment types, but a VF has only 1 segment | |
607 | */ | |
608 | ||
609 | /* 'working' memory */ | |
610 | total = p_seg->count * p_mngr->task_type_size[p_seg->type]; | |
611 | ||
612 | p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)]; | |
613 | qed_ilt_cli_blk_fill(p_cli, p_blk, | |
614 | curr_line, total, | |
615 | p_mngr->task_type_size[p_seg->type]); | |
616 | ||
617 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, | |
618 | ILT_CLI_CDUT); | |
619 | ||
620 | /* 'init' memory */ | |
621 | p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]; | |
622 | if (!p_seg->has_fl_mem) { | |
623 | /* see comment above */ | |
624 | line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line; | |
625 | qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); | |
626 | } else { | |
627 | task_size = p_mngr->task_type_size[p_seg->type]; | |
628 | qed_ilt_cli_blk_fill(p_cli, p_blk, | |
629 | curr_line, total, task_size); | |
630 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, | |
631 | ILT_CLI_CDUT); | |
632 | } | |
633 | p_cli->vf_total_lines = curr_line - | |
634 | p_cli->vf_blks[0].start_line; | |
635 | ||
636 | /* Now for the rest of the VFs */ | |
637 | for (i = 1; i < p_mngr->vf_count; i++) { | |
638 | p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)]; | |
639 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, | |
640 | ILT_CLI_CDUT); | |
641 | ||
642 | p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]; | |
643 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, | |
644 | ILT_CLI_CDUT); | |
645 | } | |
646 | } | |
647 | ||
fe56b9e6 YM |
648 | /* QM */ |
649 | p_cli = &p_mngr->clients[ILT_CLI_QM]; | |
650 | p_blk = &p_cli->pf_blks[0]; | |
651 | ||
652 | qed_cxt_qm_iids(p_hwfn, &qm_iids); | |
1408cc1f | 653 | total = qed_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids, |
dbb799c3 | 654 | qm_iids.vf_cids, qm_iids.tids, |
1408cc1f YM |
655 | p_hwfn->qm_info.num_pqs, |
656 | p_hwfn->qm_info.num_vf_pqs); | |
657 | ||
658 | DP_VERBOSE(p_hwfn, | |
659 | QED_MSG_ILT, | |
dbb799c3 | 660 | "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n", |
1408cc1f YM |
661 | qm_iids.cids, |
662 | qm_iids.vf_cids, | |
dbb799c3 | 663 | qm_iids.tids, |
1408cc1f | 664 | p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total); |
fe56b9e6 YM |
665 | |
666 | qed_ilt_cli_blk_fill(p_cli, p_blk, | |
667 | curr_line, total * 0x1000, | |
668 | QM_PQ_ELEMENT_SIZE); | |
669 | ||
670 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM); | |
671 | p_cli->pf_total_lines = curr_line - p_blk->start_line; | |
672 | ||
dbb799c3 YM |
673 | /* SRC */ |
674 | p_cli = &p_mngr->clients[ILT_CLI_SRC]; | |
675 | qed_cxt_src_iids(p_mngr, &src_iids); | |
676 | ||
677 | /* Both the PF and VFs searcher connections are stored in the per PF | |
678 | * database. Thus sum the PF searcher cids and all the VFs searcher | |
679 | * cids. | |
680 | */ | |
681 | total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; | |
682 | if (total) { | |
683 | u32 local_max = max_t(u32, total, | |
684 | SRC_MIN_NUM_ELEMS); | |
685 | ||
686 | total = roundup_pow_of_two(local_max); | |
687 | ||
688 | p_blk = &p_cli->pf_blks[0]; | |
689 | qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, | |
690 | total * sizeof(struct src_ent), | |
691 | sizeof(struct src_ent)); | |
692 | ||
693 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, | |
694 | ILT_CLI_SRC); | |
695 | p_cli->pf_total_lines = curr_line - p_blk->start_line; | |
696 | } | |
697 | ||
698 | /* TM PF */ | |
699 | p_cli = &p_mngr->clients[ILT_CLI_TM]; | |
700 | qed_cxt_tm_iids(p_mngr, &tm_iids); | |
701 | total = tm_iids.pf_cids + tm_iids.pf_tids_total; | |
702 | if (total) { | |
703 | p_blk = &p_cli->pf_blks[0]; | |
704 | qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, | |
705 | total * TM_ELEM_SIZE, TM_ELEM_SIZE); | |
706 | ||
707 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, | |
708 | ILT_CLI_TM); | |
709 | p_cli->pf_total_lines = curr_line - p_blk->start_line; | |
710 | } | |
711 | ||
712 | /* TM VF */ | |
713 | total = tm_iids.per_vf_cids + tm_iids.per_vf_tids; | |
714 | if (total) { | |
715 | p_blk = &p_cli->vf_blks[0]; | |
716 | qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, | |
717 | total * TM_ELEM_SIZE, TM_ELEM_SIZE); | |
718 | ||
719 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, | |
720 | ILT_CLI_TM); | |
721 | p_cli->pf_total_lines = curr_line - p_blk->start_line; | |
722 | ||
723 | for (i = 1; i < p_mngr->vf_count; i++) | |
724 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, | |
725 | ILT_CLI_TM); | |
726 | } | |
727 | ||
728 | /* TSDM (SRQ CONTEXT) */ | |
729 | total = qed_cxt_get_srq_count(p_hwfn); | |
730 | ||
731 | if (total) { | |
732 | p_cli = &p_mngr->clients[ILT_CLI_TSDM]; | |
733 | p_blk = &p_cli->pf_blks[SRQ_BLK]; | |
734 | qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, | |
735 | total * SRQ_CXT_SIZE, SRQ_CXT_SIZE); | |
736 | ||
737 | qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, | |
738 | ILT_CLI_TSDM); | |
739 | p_cli->pf_total_lines = curr_line - p_blk->start_line; | |
740 | } | |
741 | ||
fe56b9e6 YM |
742 | if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line > |
743 | RESC_NUM(p_hwfn, QED_ILT)) { | |
744 | DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n", | |
745 | curr_line - p_hwfn->p_cxt_mngr->pf_start_line); | |
746 | return -EINVAL; | |
747 | } | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
dbb799c3 YM |
752 | static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn) |
753 | { | |
754 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
755 | u32 i; | |
756 | ||
757 | if (!p_mngr->t2) | |
758 | return; | |
759 | ||
760 | for (i = 0; i < p_mngr->t2_num_pages; i++) | |
761 | if (p_mngr->t2[i].p_virt) | |
762 | dma_free_coherent(&p_hwfn->cdev->pdev->dev, | |
763 | p_mngr->t2[i].size, | |
764 | p_mngr->t2[i].p_virt, | |
765 | p_mngr->t2[i].p_phys); | |
766 | ||
767 | kfree(p_mngr->t2); | |
768 | p_mngr->t2 = NULL; | |
769 | } | |
770 | ||
771 | static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn) | |
772 | { | |
773 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
774 | u32 conn_num, total_size, ent_per_page, psz, i; | |
775 | struct qed_ilt_client_cfg *p_src; | |
776 | struct qed_src_iids src_iids; | |
777 | struct qed_dma_mem *p_t2; | |
778 | int rc; | |
779 | ||
780 | memset(&src_iids, 0, sizeof(src_iids)); | |
781 | ||
782 | /* if the SRC ILT client is inactive - there are no connection | |
783 | * requiring the searcer, leave. | |
784 | */ | |
785 | p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC]; | |
786 | if (!p_src->active) | |
787 | return 0; | |
788 | ||
789 | qed_cxt_src_iids(p_mngr, &src_iids); | |
790 | conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; | |
791 | total_size = conn_num * sizeof(struct src_ent); | |
792 | ||
793 | /* use the same page size as the SRC ILT client */ | |
794 | psz = ILT_PAGE_IN_BYTES(p_src->p_size.val); | |
795 | p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz); | |
796 | ||
797 | /* allocate t2 */ | |
798 | p_mngr->t2 = kzalloc(p_mngr->t2_num_pages * sizeof(struct qed_dma_mem), | |
799 | GFP_KERNEL); | |
800 | if (!p_mngr->t2) { | |
801 | DP_NOTICE(p_hwfn, "Failed to allocate t2 table\n"); | |
802 | rc = -ENOMEM; | |
803 | goto t2_fail; | |
804 | } | |
805 | ||
806 | /* allocate t2 pages */ | |
807 | for (i = 0; i < p_mngr->t2_num_pages; i++) { | |
808 | u32 size = min_t(u32, total_size, psz); | |
809 | void **p_virt = &p_mngr->t2[i].p_virt; | |
810 | ||
811 | *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, | |
812 | size, | |
813 | &p_mngr->t2[i].p_phys, GFP_KERNEL); | |
814 | if (!p_mngr->t2[i].p_virt) { | |
815 | rc = -ENOMEM; | |
816 | goto t2_fail; | |
817 | } | |
818 | memset(*p_virt, 0, size); | |
819 | p_mngr->t2[i].size = size; | |
820 | total_size -= size; | |
821 | } | |
822 | ||
823 | /* Set the t2 pointers */ | |
824 | ||
825 | /* entries per page - must be a power of two */ | |
826 | ent_per_page = psz / sizeof(struct src_ent); | |
827 | ||
828 | p_mngr->first_free = (u64) p_mngr->t2[0].p_phys; | |
829 | ||
830 | p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page]; | |
831 | p_mngr->last_free = (u64) p_t2->p_phys + | |
832 | ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent); | |
833 | ||
834 | for (i = 0; i < p_mngr->t2_num_pages; i++) { | |
835 | u32 ent_num = min_t(u32, | |
836 | ent_per_page, | |
837 | conn_num); | |
838 | struct src_ent *entries = p_mngr->t2[i].p_virt; | |
839 | u64 p_ent_phys = (u64) p_mngr->t2[i].p_phys, val; | |
840 | u32 j; | |
841 | ||
842 | for (j = 0; j < ent_num - 1; j++) { | |
843 | val = p_ent_phys + (j + 1) * sizeof(struct src_ent); | |
844 | entries[j].next = cpu_to_be64(val); | |
845 | } | |
846 | ||
847 | if (i < p_mngr->t2_num_pages - 1) | |
848 | val = (u64) p_mngr->t2[i + 1].p_phys; | |
849 | else | |
850 | val = 0; | |
851 | entries[j].next = cpu_to_be64(val); | |
852 | ||
01e517f1 | 853 | conn_num -= ent_num; |
dbb799c3 YM |
854 | } |
855 | ||
856 | return 0; | |
857 | ||
858 | t2_fail: | |
859 | qed_cxt_src_t2_free(p_hwfn); | |
860 | return rc; | |
861 | } | |
862 | ||
fe56b9e6 | 863 | #define for_each_ilt_valid_client(pos, clients) \ |
dbb799c3 YM |
864 | for (pos = 0; pos < ILT_CLI_MAX; pos++) \ |
865 | if (!clients[pos].active) { \ | |
866 | continue; \ | |
867 | } else \ | |
fe56b9e6 YM |
868 | |
869 | /* Total number of ILT lines used by this PF */ | |
870 | static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients) | |
871 | { | |
872 | u32 size = 0; | |
873 | u32 i; | |
874 | ||
dbb799c3 YM |
875 | for_each_ilt_valid_client(i, ilt_clients) |
876 | size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1); | |
fe56b9e6 YM |
877 | |
878 | return size; | |
879 | } | |
880 | ||
881 | static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn) | |
882 | { | |
883 | struct qed_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients; | |
884 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
885 | u32 ilt_size, i; | |
886 | ||
887 | ilt_size = qed_cxt_ilt_shadow_size(p_cli); | |
888 | ||
889 | for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) { | |
890 | struct qed_dma_mem *p_dma = &p_mngr->ilt_shadow[i]; | |
891 | ||
892 | if (p_dma->p_virt) | |
893 | dma_free_coherent(&p_hwfn->cdev->pdev->dev, | |
894 | p_dma->size, p_dma->p_virt, | |
895 | p_dma->p_phys); | |
896 | p_dma->p_virt = NULL; | |
897 | } | |
898 | kfree(p_mngr->ilt_shadow); | |
899 | } | |
900 | ||
901 | static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn, | |
902 | struct qed_ilt_cli_blk *p_blk, | |
903 | enum ilt_clients ilt_client, | |
904 | u32 start_line_offset) | |
905 | { | |
906 | struct qed_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow; | |
dbb799c3 YM |
907 | u32 lines, line, sz_left, lines_to_skip = 0; |
908 | ||
909 | /* Special handling for RoCE that supports dynamic allocation */ | |
910 | if ((p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) && | |
911 | ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM)) | |
912 | return 0; | |
913 | ||
914 | lines_to_skip = p_blk->dynamic_line_cnt; | |
fe56b9e6 YM |
915 | |
916 | if (!p_blk->total_size) | |
917 | return 0; | |
918 | ||
919 | sz_left = p_blk->total_size; | |
dbb799c3 | 920 | lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip; |
fe56b9e6 | 921 | line = p_blk->start_line + start_line_offset - |
dbb799c3 | 922 | p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip; |
fe56b9e6 YM |
923 | |
924 | for (; lines; lines--) { | |
925 | dma_addr_t p_phys; | |
926 | void *p_virt; | |
927 | u32 size; | |
928 | ||
929 | size = min_t(u32, sz_left, | |
930 | p_blk->real_size_in_page); | |
931 | p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, | |
932 | size, | |
933 | &p_phys, | |
934 | GFP_KERNEL); | |
935 | if (!p_virt) | |
936 | return -ENOMEM; | |
937 | memset(p_virt, 0, size); | |
938 | ||
939 | ilt_shadow[line].p_phys = p_phys; | |
940 | ilt_shadow[line].p_virt = p_virt; | |
941 | ilt_shadow[line].size = size; | |
942 | ||
943 | DP_VERBOSE(p_hwfn, QED_MSG_ILT, | |
944 | "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n", | |
945 | line, (u64)p_phys, p_virt, size); | |
946 | ||
947 | sz_left -= size; | |
948 | line++; | |
949 | } | |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
954 | static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn) | |
955 | { | |
956 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
957 | struct qed_ilt_client_cfg *clients = p_mngr->clients; | |
958 | struct qed_ilt_cli_blk *p_blk; | |
1408cc1f | 959 | u32 size, i, j, k; |
fe56b9e6 YM |
960 | int rc; |
961 | ||
962 | size = qed_cxt_ilt_shadow_size(clients); | |
963 | p_mngr->ilt_shadow = kcalloc(size, sizeof(struct qed_dma_mem), | |
964 | GFP_KERNEL); | |
965 | if (!p_mngr->ilt_shadow) { | |
966 | DP_NOTICE(p_hwfn, "Failed to allocate ilt shadow table\n"); | |
967 | rc = -ENOMEM; | |
968 | goto ilt_shadow_fail; | |
969 | } | |
970 | ||
971 | DP_VERBOSE(p_hwfn, QED_MSG_ILT, | |
972 | "Allocated 0x%x bytes for ilt shadow\n", | |
973 | (u32)(size * sizeof(struct qed_dma_mem))); | |
974 | ||
975 | for_each_ilt_valid_client(i, clients) { | |
fe56b9e6 YM |
976 | for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) { |
977 | p_blk = &clients[i].pf_blks[j]; | |
978 | rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0); | |
979 | if (rc != 0) | |
980 | goto ilt_shadow_fail; | |
981 | } | |
1408cc1f YM |
982 | for (k = 0; k < p_mngr->vf_count; k++) { |
983 | for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) { | |
984 | u32 lines = clients[i].vf_total_lines * k; | |
985 | ||
986 | p_blk = &clients[i].vf_blks[j]; | |
987 | rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines); | |
988 | if (rc != 0) | |
989 | goto ilt_shadow_fail; | |
990 | } | |
991 | } | |
fe56b9e6 YM |
992 | } |
993 | ||
994 | return 0; | |
995 | ||
996 | ilt_shadow_fail: | |
997 | qed_ilt_shadow_free(p_hwfn); | |
998 | return rc; | |
999 | } | |
1000 | ||
1001 | static void qed_cid_map_free(struct qed_hwfn *p_hwfn) | |
1002 | { | |
1003 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
1004 | u32 type; | |
1005 | ||
1006 | for (type = 0; type < MAX_CONN_TYPES; type++) { | |
1007 | kfree(p_mngr->acquired[type].cid_map); | |
1008 | p_mngr->acquired[type].max_count = 0; | |
1009 | p_mngr->acquired[type].start_cid = 0; | |
1010 | } | |
1011 | } | |
1012 | ||
1013 | static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn) | |
1014 | { | |
1015 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
1016 | u32 start_cid = 0; | |
1017 | u32 type; | |
1018 | ||
1019 | for (type = 0; type < MAX_CONN_TYPES; type++) { | |
1020 | u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count; | |
1021 | u32 size; | |
1022 | ||
1023 | if (cid_cnt == 0) | |
1024 | continue; | |
1025 | ||
1026 | size = DIV_ROUND_UP(cid_cnt, | |
1027 | sizeof(unsigned long) * BITS_PER_BYTE) * | |
1028 | sizeof(unsigned long); | |
1029 | p_mngr->acquired[type].cid_map = kzalloc(size, GFP_KERNEL); | |
1030 | if (!p_mngr->acquired[type].cid_map) | |
1031 | goto cid_map_fail; | |
1032 | ||
1033 | p_mngr->acquired[type].max_count = cid_cnt; | |
1034 | p_mngr->acquired[type].start_cid = start_cid; | |
1035 | ||
1036 | p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid; | |
1037 | ||
1038 | DP_VERBOSE(p_hwfn, QED_MSG_CXT, | |
1039 | "Type %08x start: %08x count %08x\n", | |
1040 | type, p_mngr->acquired[type].start_cid, | |
1041 | p_mngr->acquired[type].max_count); | |
1042 | start_cid += cid_cnt; | |
1043 | } | |
1044 | ||
1045 | return 0; | |
1046 | ||
1047 | cid_map_fail: | |
1048 | qed_cid_map_free(p_hwfn); | |
1049 | return -ENOMEM; | |
1050 | } | |
1051 | ||
1052 | int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn) | |
1053 | { | |
dbb799c3 | 1054 | struct qed_ilt_client_cfg *clients; |
fe56b9e6 YM |
1055 | struct qed_cxt_mngr *p_mngr; |
1056 | u32 i; | |
1057 | ||
60fffb3b | 1058 | p_mngr = kzalloc(sizeof(*p_mngr), GFP_KERNEL); |
fe56b9e6 YM |
1059 | if (!p_mngr) { |
1060 | DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_cxt_mngr'\n"); | |
1061 | return -ENOMEM; | |
1062 | } | |
1063 | ||
1064 | /* Initialize ILT client registers */ | |
dbb799c3 YM |
1065 | clients = p_mngr->clients; |
1066 | clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT); | |
1067 | clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT); | |
1068 | clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE); | |
1069 | ||
1070 | clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT); | |
1071 | clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT); | |
1072 | clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE); | |
1073 | ||
1074 | clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT); | |
1075 | clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT); | |
1076 | clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE); | |
1077 | ||
1078 | clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT); | |
1079 | clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT); | |
1080 | clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE); | |
1081 | ||
1082 | clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT); | |
1083 | clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT); | |
1084 | clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE); | |
1085 | ||
1086 | clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT); | |
1087 | clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT); | |
1088 | clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE); | |
fe56b9e6 YM |
1089 | /* default ILT page size for all clients is 32K */ |
1090 | for (i = 0; i < ILT_CLI_MAX; i++) | |
1091 | p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE; | |
1092 | ||
dbb799c3 YM |
1093 | /* Initialize task sizes */ |
1094 | p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn); | |
1095 | p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn); | |
1096 | ||
1408cc1f YM |
1097 | if (p_hwfn->cdev->p_iov_info) |
1098 | p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs; | |
dbb799c3 YM |
1099 | /* Initialize the dynamic ILT allocation mutex */ |
1100 | mutex_init(&p_mngr->mutex); | |
1408cc1f | 1101 | |
fe56b9e6 YM |
1102 | /* Set the cxt mangr pointer priori to further allocations */ |
1103 | p_hwfn->p_cxt_mngr = p_mngr; | |
1104 | ||
1105 | return 0; | |
1106 | } | |
1107 | ||
1108 | int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn) | |
1109 | { | |
1110 | int rc; | |
1111 | ||
1112 | /* Allocate the ILT shadow table */ | |
1113 | rc = qed_ilt_shadow_alloc(p_hwfn); | |
1114 | if (rc) { | |
1115 | DP_NOTICE(p_hwfn, "Failed to allocate ilt memory\n"); | |
1116 | goto tables_alloc_fail; | |
1117 | } | |
1118 | ||
dbb799c3 YM |
1119 | /* Allocate the T2 table */ |
1120 | rc = qed_cxt_src_t2_alloc(p_hwfn); | |
1121 | if (rc) { | |
1122 | DP_NOTICE(p_hwfn, "Failed to allocate T2 memory\n"); | |
1123 | goto tables_alloc_fail; | |
1124 | } | |
1125 | ||
fe56b9e6 YM |
1126 | /* Allocate and initialize the acquired cids bitmaps */ |
1127 | rc = qed_cid_map_alloc(p_hwfn); | |
1128 | if (rc) { | |
1129 | DP_NOTICE(p_hwfn, "Failed to allocate cid maps\n"); | |
1130 | goto tables_alloc_fail; | |
1131 | } | |
1132 | ||
1133 | return 0; | |
1134 | ||
1135 | tables_alloc_fail: | |
1136 | qed_cxt_mngr_free(p_hwfn); | |
1137 | return rc; | |
1138 | } | |
1139 | ||
1140 | void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn) | |
1141 | { | |
1142 | if (!p_hwfn->p_cxt_mngr) | |
1143 | return; | |
1144 | ||
1145 | qed_cid_map_free(p_hwfn); | |
dbb799c3 | 1146 | qed_cxt_src_t2_free(p_hwfn); |
fe56b9e6 YM |
1147 | qed_ilt_shadow_free(p_hwfn); |
1148 | kfree(p_hwfn->p_cxt_mngr); | |
1149 | ||
1150 | p_hwfn->p_cxt_mngr = NULL; | |
1151 | } | |
1152 | ||
1153 | void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn) | |
1154 | { | |
1155 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
1156 | int type; | |
1157 | ||
1158 | /* Reset acquired cids */ | |
1159 | for (type = 0; type < MAX_CONN_TYPES; type++) { | |
1160 | u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count; | |
1161 | ||
1162 | if (cid_cnt == 0) | |
1163 | continue; | |
1164 | ||
1165 | memset(p_mngr->acquired[type].cid_map, 0, | |
1166 | DIV_ROUND_UP(cid_cnt, | |
1167 | sizeof(unsigned long) * BITS_PER_BYTE) * | |
1168 | sizeof(unsigned long)); | |
1169 | } | |
1170 | } | |
1171 | ||
1172 | /* CDU Common */ | |
1173 | #define CDUC_CXT_SIZE_SHIFT \ | |
1174 | CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT | |
1175 | ||
1176 | #define CDUC_CXT_SIZE_MASK \ | |
1177 | (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT) | |
1178 | ||
1179 | #define CDUC_BLOCK_WASTE_SHIFT \ | |
1180 | CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT | |
1181 | ||
1182 | #define CDUC_BLOCK_WASTE_MASK \ | |
1183 | (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT) | |
1184 | ||
1185 | #define CDUC_NCIB_SHIFT \ | |
1186 | CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT | |
1187 | ||
1188 | #define CDUC_NCIB_MASK \ | |
1189 | (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT) | |
1190 | ||
dbb799c3 YM |
1191 | #define CDUT_TYPE0_CXT_SIZE_SHIFT \ |
1192 | CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT | |
1193 | ||
1194 | #define CDUT_TYPE0_CXT_SIZE_MASK \ | |
1195 | (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \ | |
1196 | CDUT_TYPE0_CXT_SIZE_SHIFT) | |
1197 | ||
1198 | #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \ | |
1199 | CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT | |
1200 | ||
1201 | #define CDUT_TYPE0_BLOCK_WASTE_MASK \ | |
1202 | (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \ | |
1203 | CDUT_TYPE0_BLOCK_WASTE_SHIFT) | |
1204 | ||
1205 | #define CDUT_TYPE0_NCIB_SHIFT \ | |
1206 | CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT | |
1207 | ||
1208 | #define CDUT_TYPE0_NCIB_MASK \ | |
1209 | (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \ | |
1210 | CDUT_TYPE0_NCIB_SHIFT) | |
1211 | ||
1212 | #define CDUT_TYPE1_CXT_SIZE_SHIFT \ | |
1213 | CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT | |
1214 | ||
1215 | #define CDUT_TYPE1_CXT_SIZE_MASK \ | |
1216 | (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \ | |
1217 | CDUT_TYPE1_CXT_SIZE_SHIFT) | |
1218 | ||
1219 | #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \ | |
1220 | CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT | |
1221 | ||
1222 | #define CDUT_TYPE1_BLOCK_WASTE_MASK \ | |
1223 | (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \ | |
1224 | CDUT_TYPE1_BLOCK_WASTE_SHIFT) | |
1225 | ||
1226 | #define CDUT_TYPE1_NCIB_SHIFT \ | |
1227 | CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT | |
1228 | ||
1229 | #define CDUT_TYPE1_NCIB_MASK \ | |
1230 | (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \ | |
1231 | CDUT_TYPE1_NCIB_SHIFT) | |
1232 | ||
fe56b9e6 YM |
1233 | static void qed_cdu_init_common(struct qed_hwfn *p_hwfn) |
1234 | { | |
1235 | u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0; | |
1236 | ||
1237 | /* CDUC - connection configuration */ | |
1238 | page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; | |
1239 | cxt_size = CONN_CXT_SIZE(p_hwfn); | |
1240 | elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; | |
1241 | block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; | |
1242 | ||
1243 | SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size); | |
1244 | SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste); | |
1245 | SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page); | |
1246 | STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params); | |
dbb799c3 YM |
1247 | |
1248 | /* CDUT - type-0 tasks configuration */ | |
1249 | page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val; | |
1250 | cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0]; | |
1251 | elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; | |
1252 | block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; | |
1253 | ||
1254 | /* cxt size and block-waste are multipes of 8 */ | |
1255 | cdu_params = 0; | |
1256 | SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3)); | |
1257 | SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3)); | |
1258 | SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page); | |
1259 | STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params); | |
1260 | ||
1261 | /* CDUT - type-1 tasks configuration */ | |
1262 | cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1]; | |
1263 | elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; | |
1264 | block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; | |
1265 | ||
1266 | /* cxt size and block-waste are multipes of 8 */ | |
1267 | cdu_params = 0; | |
1268 | SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3)); | |
1269 | SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3)); | |
1270 | SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page); | |
1271 | STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params); | |
1272 | } | |
1273 | ||
1274 | /* CDU PF */ | |
1275 | #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT | |
1276 | #define CDU_SEG_REG_TYPE_MASK 0x1 | |
1277 | #define CDU_SEG_REG_OFFSET_SHIFT 0 | |
1278 | #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK | |
1279 | ||
1280 | static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn) | |
1281 | { | |
1282 | struct qed_ilt_client_cfg *p_cli; | |
1283 | struct qed_tid_seg *p_seg; | |
1284 | u32 cdu_seg_params, offset; | |
1285 | int i; | |
1286 | ||
1287 | static const u32 rt_type_offset_arr[] = { | |
1288 | CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET, | |
1289 | CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET, | |
1290 | CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET, | |
1291 | CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET | |
1292 | }; | |
1293 | ||
1294 | static const u32 rt_type_offset_fl_arr[] = { | |
1295 | CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET, | |
1296 | CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET, | |
1297 | CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET, | |
1298 | CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET | |
1299 | }; | |
1300 | ||
1301 | p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; | |
1302 | ||
1303 | /* There are initializations only for CDUT during pf Phase */ | |
1304 | for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { | |
1305 | /* Segment 0 */ | |
1306 | p_seg = qed_cxt_tid_seg_info(p_hwfn, i); | |
1307 | if (!p_seg) | |
1308 | continue; | |
1309 | ||
1310 | /* Note: start_line is already adjusted for the CDU | |
1311 | * segment register granularity, so we just need to | |
1312 | * divide. Adjustment is implicit as we assume ILT | |
1313 | * Page size is larger than 32K! | |
1314 | */ | |
1315 | offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * | |
1316 | (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line - | |
1317 | p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; | |
1318 | ||
1319 | cdu_seg_params = 0; | |
1320 | SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); | |
1321 | SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); | |
1322 | STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params); | |
1323 | ||
1324 | offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * | |
1325 | (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line - | |
1326 | p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; | |
1327 | ||
1328 | cdu_seg_params = 0; | |
1329 | SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); | |
1330 | SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); | |
1331 | STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params); | |
1332 | } | |
fe56b9e6 YM |
1333 | } |
1334 | ||
1335 | void qed_qm_init_pf(struct qed_hwfn *p_hwfn) | |
1336 | { | |
1337 | struct qed_qm_pf_rt_init_params params; | |
1338 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; | |
1339 | struct qed_qm_iids iids; | |
1340 | ||
1341 | memset(&iids, 0, sizeof(iids)); | |
1342 | qed_cxt_qm_iids(p_hwfn, &iids); | |
1343 | ||
1344 | memset(¶ms, 0, sizeof(params)); | |
1345 | params.port_id = p_hwfn->port_id; | |
1346 | params.pf_id = p_hwfn->rel_pf_id; | |
1347 | params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; | |
1348 | params.is_first_pf = p_hwfn->first_on_engine; | |
1349 | params.num_pf_cids = iids.cids; | |
1408cc1f | 1350 | params.num_vf_cids = iids.vf_cids; |
fe56b9e6 | 1351 | params.start_pq = qm_info->start_pq; |
1408cc1f YM |
1352 | params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs; |
1353 | params.num_vf_pqs = qm_info->num_vf_pqs; | |
fc48b7a6 YM |
1354 | params.start_vport = qm_info->start_vport; |
1355 | params.num_vports = qm_info->num_vports; | |
fe56b9e6 YM |
1356 | params.pf_wfq = qm_info->pf_wfq; |
1357 | params.pf_rl = qm_info->pf_rl; | |
1358 | params.pq_params = qm_info->qm_pq_params; | |
1359 | params.vport_params = qm_info->qm_vport_params; | |
1360 | ||
1361 | qed_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, ¶ms); | |
1362 | } | |
1363 | ||
1364 | /* CM PF */ | |
1365 | static int qed_cm_init_pf(struct qed_hwfn *p_hwfn) | |
1366 | { | |
1367 | union qed_qm_pq_params pq_params; | |
1368 | u16 pq; | |
1369 | ||
1370 | /* XCM pure-LB queue */ | |
1371 | memset(&pq_params, 0, sizeof(pq_params)); | |
1372 | pq_params.core.tc = LB_TC; | |
1373 | pq = qed_get_qm_pq(p_hwfn, PROTOCOLID_CORE, &pq_params); | |
1374 | STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, pq); | |
1375 | ||
1376 | return 0; | |
1377 | } | |
1378 | ||
1379 | /* DQ PF */ | |
1380 | static void qed_dq_init_pf(struct qed_hwfn *p_hwfn) | |
1381 | { | |
1382 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
1408cc1f | 1383 | u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0; |
fe56b9e6 YM |
1384 | |
1385 | dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT); | |
1386 | STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid); | |
1387 | ||
1408cc1f YM |
1388 | dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT); |
1389 | STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid); | |
1390 | ||
fe56b9e6 YM |
1391 | dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT); |
1392 | STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid); | |
1393 | ||
1408cc1f YM |
1394 | dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT); |
1395 | STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid); | |
1396 | ||
fe56b9e6 YM |
1397 | dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT); |
1398 | STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid); | |
1399 | ||
1408cc1f YM |
1400 | dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT); |
1401 | STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid); | |
1402 | ||
fe56b9e6 YM |
1403 | dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT); |
1404 | STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid); | |
1405 | ||
1408cc1f YM |
1406 | dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT); |
1407 | STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid); | |
1408 | ||
fe56b9e6 YM |
1409 | dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT); |
1410 | STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid); | |
1411 | ||
1408cc1f YM |
1412 | dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT); |
1413 | STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid); | |
1414 | ||
fe56b9e6 YM |
1415 | dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT); |
1416 | STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid); | |
1408cc1f YM |
1417 | |
1418 | dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT); | |
1419 | STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid); | |
1420 | ||
1421 | /* Connection types 6 & 7 are not in use, yet they must be configured | |
1422 | * as the highest possible connection. Not configuring them means the | |
1423 | * defaults will be used, and with a large number of cids a bug may | |
1424 | * occur, if the defaults will be smaller than dq_pf_max_cid / | |
1425 | * dq_vf_max_cid. | |
1426 | */ | |
1427 | STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid); | |
1428 | STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid); | |
1429 | ||
1430 | STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid); | |
1431 | STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid); | |
fe56b9e6 YM |
1432 | } |
1433 | ||
1434 | static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn) | |
1435 | { | |
1436 | struct qed_ilt_client_cfg *ilt_clients; | |
1437 | int i; | |
1438 | ||
1439 | ilt_clients = p_hwfn->p_cxt_mngr->clients; | |
1440 | for_each_ilt_valid_client(i, ilt_clients) { | |
fe56b9e6 YM |
1441 | STORE_RT_REG(p_hwfn, |
1442 | ilt_clients[i].first.reg, | |
1443 | ilt_clients[i].first.val); | |
1444 | STORE_RT_REG(p_hwfn, | |
dbb799c3 | 1445 | ilt_clients[i].last.reg, ilt_clients[i].last.val); |
fe56b9e6 YM |
1446 | STORE_RT_REG(p_hwfn, |
1447 | ilt_clients[i].p_size.reg, | |
1448 | ilt_clients[i].p_size.val); | |
1449 | } | |
1450 | } | |
1451 | ||
1408cc1f YM |
1452 | static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn) |
1453 | { | |
1454 | struct qed_ilt_client_cfg *p_cli; | |
1455 | u32 blk_factor; | |
1456 | ||
1457 | /* For simplicty we set the 'block' to be an ILT page */ | |
1458 | if (p_hwfn->cdev->p_iov_info) { | |
1459 | struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; | |
1460 | ||
1461 | STORE_RT_REG(p_hwfn, | |
1462 | PSWRQ2_REG_VF_BASE_RT_OFFSET, | |
1463 | p_iov->first_vf_in_pf); | |
1464 | STORE_RT_REG(p_hwfn, | |
1465 | PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET, | |
1466 | p_iov->first_vf_in_pf + p_iov->total_vfs); | |
1467 | } | |
1468 | ||
1469 | p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; | |
1470 | blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); | |
1471 | if (p_cli->active) { | |
1472 | STORE_RT_REG(p_hwfn, | |
1473 | PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET, | |
1474 | blk_factor); | |
1475 | STORE_RT_REG(p_hwfn, | |
1476 | PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET, | |
1477 | p_cli->pf_total_lines); | |
1478 | STORE_RT_REG(p_hwfn, | |
1479 | PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET, | |
1480 | p_cli->vf_total_lines); | |
1481 | } | |
dbb799c3 YM |
1482 | |
1483 | p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; | |
1484 | blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); | |
1485 | if (p_cli->active) { | |
1486 | STORE_RT_REG(p_hwfn, | |
1487 | PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET, | |
1488 | blk_factor); | |
1489 | STORE_RT_REG(p_hwfn, | |
1490 | PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET, | |
1491 | p_cli->pf_total_lines); | |
1492 | STORE_RT_REG(p_hwfn, | |
1493 | PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET, | |
1494 | p_cli->vf_total_lines); | |
1495 | } | |
1496 | ||
1497 | p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM]; | |
1498 | blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); | |
1499 | if (p_cli->active) { | |
1500 | STORE_RT_REG(p_hwfn, | |
1501 | PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor); | |
1502 | STORE_RT_REG(p_hwfn, | |
1503 | PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET, | |
1504 | p_cli->pf_total_lines); | |
1505 | STORE_RT_REG(p_hwfn, | |
1506 | PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET, | |
1507 | p_cli->vf_total_lines); | |
1508 | } | |
1408cc1f YM |
1509 | } |
1510 | ||
fe56b9e6 YM |
1511 | /* ILT (PSWRQ2) PF */ |
1512 | static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn) | |
1513 | { | |
1514 | struct qed_ilt_client_cfg *clients; | |
1515 | struct qed_cxt_mngr *p_mngr; | |
1516 | struct qed_dma_mem *p_shdw; | |
1517 | u32 line, rt_offst, i; | |
1518 | ||
1519 | qed_ilt_bounds_init(p_hwfn); | |
1408cc1f | 1520 | qed_ilt_vf_bounds_init(p_hwfn); |
fe56b9e6 YM |
1521 | |
1522 | p_mngr = p_hwfn->p_cxt_mngr; | |
1523 | p_shdw = p_mngr->ilt_shadow; | |
1524 | clients = p_hwfn->p_cxt_mngr->clients; | |
1525 | ||
1526 | for_each_ilt_valid_client(i, clients) { | |
fe56b9e6 YM |
1527 | /** Client's 1st val and RT array are absolute, ILT shadows' |
1528 | * lines are relative. | |
1529 | */ | |
1530 | line = clients[i].first.val - p_mngr->pf_start_line; | |
1531 | rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET + | |
1532 | clients[i].first.val * ILT_ENTRY_IN_REGS; | |
1533 | ||
1534 | for (; line <= clients[i].last.val - p_mngr->pf_start_line; | |
1535 | line++, rt_offst += ILT_ENTRY_IN_REGS) { | |
1536 | u64 ilt_hw_entry = 0; | |
1537 | ||
1538 | /** p_virt could be NULL incase of dynamic | |
1539 | * allocation | |
1540 | */ | |
1541 | if (p_shdw[line].p_virt) { | |
1542 | SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); | |
1543 | SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, | |
1544 | (p_shdw[line].p_phys >> 12)); | |
1545 | ||
1546 | DP_VERBOSE(p_hwfn, QED_MSG_ILT, | |
1547 | "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n", | |
1548 | rt_offst, line, i, | |
1549 | (u64)(p_shdw[line].p_phys >> 12)); | |
1550 | } | |
1551 | ||
1552 | STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry); | |
1553 | } | |
1554 | } | |
1555 | } | |
1556 | ||
dbb799c3 YM |
1557 | /* SRC (Searcher) PF */ |
1558 | static void qed_src_init_pf(struct qed_hwfn *p_hwfn) | |
1559 | { | |
1560 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
1561 | u32 rounded_conn_num, conn_num, conn_max; | |
1562 | struct qed_src_iids src_iids; | |
1563 | ||
1564 | memset(&src_iids, 0, sizeof(src_iids)); | |
1565 | qed_cxt_src_iids(p_mngr, &src_iids); | |
1566 | conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; | |
1567 | if (!conn_num) | |
1568 | return; | |
1569 | ||
1570 | conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS); | |
1571 | rounded_conn_num = roundup_pow_of_two(conn_max); | |
1572 | ||
1573 | STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num); | |
1574 | STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET, | |
1575 | ilog2(rounded_conn_num)); | |
1576 | ||
1577 | STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET, | |
1578 | p_hwfn->p_cxt_mngr->first_free); | |
1579 | STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET, | |
1580 | p_hwfn->p_cxt_mngr->last_free); | |
1581 | } | |
1582 | ||
1583 | /* Timers PF */ | |
1584 | #define TM_CFG_NUM_IDS_SHIFT 0 | |
1585 | #define TM_CFG_NUM_IDS_MASK 0xFFFFULL | |
1586 | #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16 | |
1587 | #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL | |
1588 | #define TM_CFG_PARENT_PF_SHIFT 25 | |
1589 | #define TM_CFG_PARENT_PF_MASK 0x7ULL | |
1590 | ||
1591 | #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30 | |
1592 | #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL | |
1593 | ||
1594 | #define TM_CFG_TID_OFFSET_SHIFT 30 | |
1595 | #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL | |
1596 | #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49 | |
1597 | #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL | |
1598 | ||
1599 | static void qed_tm_init_pf(struct qed_hwfn *p_hwfn) | |
1600 | { | |
1601 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
1602 | u32 active_seg_mask = 0, tm_offset, rt_reg; | |
1603 | struct qed_tm_iids tm_iids; | |
1604 | u64 cfg_word; | |
1605 | u8 i; | |
1606 | ||
1607 | memset(&tm_iids, 0, sizeof(tm_iids)); | |
1608 | qed_cxt_tm_iids(p_mngr, &tm_iids); | |
1609 | ||
1610 | /* @@@TBD No pre-scan for now */ | |
1611 | ||
1612 | /* Note: We assume consecutive VFs for a PF */ | |
1613 | for (i = 0; i < p_mngr->vf_count; i++) { | |
1614 | cfg_word = 0; | |
1615 | SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids); | |
1616 | SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); | |
1617 | SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); | |
1618 | SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); | |
1619 | rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + | |
1620 | (sizeof(cfg_word) / sizeof(u32)) * | |
1621 | (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i); | |
1622 | STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); | |
1623 | } | |
1624 | ||
1625 | cfg_word = 0; | |
1626 | SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids); | |
1627 | SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); | |
1628 | SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */ | |
1629 | SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */ | |
1630 | ||
1631 | rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + | |
1632 | (sizeof(cfg_word) / sizeof(u32)) * | |
1633 | (NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id); | |
1634 | STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); | |
1635 | ||
1636 | /* enale scan */ | |
1637 | STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET, | |
1638 | tm_iids.pf_cids ? 0x1 : 0x0); | |
1639 | ||
1640 | /* @@@TBD how to enable the scan for the VFs */ | |
1641 | ||
1642 | tm_offset = tm_iids.per_vf_cids; | |
1643 | ||
1644 | /* Note: We assume consecutive VFs for a PF */ | |
1645 | for (i = 0; i < p_mngr->vf_count; i++) { | |
1646 | cfg_word = 0; | |
1647 | SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids); | |
1648 | SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); | |
1649 | SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); | |
1650 | SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); | |
1651 | SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0); | |
1652 | ||
1653 | rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + | |
1654 | (sizeof(cfg_word) / sizeof(u32)) * | |
1655 | (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i); | |
1656 | ||
1657 | STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); | |
1658 | } | |
1659 | ||
1660 | tm_offset = tm_iids.pf_cids; | |
1661 | for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { | |
1662 | cfg_word = 0; | |
1663 | SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]); | |
1664 | SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); | |
1665 | SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); | |
1666 | SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); | |
1667 | SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0); | |
1668 | ||
1669 | rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + | |
1670 | (sizeof(cfg_word) / sizeof(u32)) * | |
1671 | (NUM_OF_VFS(p_hwfn->cdev) + | |
1672 | p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i); | |
1673 | ||
1674 | STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); | |
1675 | active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0); | |
1676 | ||
1677 | tm_offset += tm_iids.pf_tids[i]; | |
1678 | } | |
1679 | ||
1680 | if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) | |
1681 | active_seg_mask = 0; | |
1682 | ||
1683 | STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask); | |
1684 | ||
1685 | /* @@@TBD how to enable the scan for the VFs */ | |
1686 | } | |
1687 | ||
fe56b9e6 YM |
1688 | void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn) |
1689 | { | |
1690 | qed_cdu_init_common(p_hwfn); | |
1691 | } | |
1692 | ||
1693 | void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn) | |
1694 | { | |
1695 | qed_qm_init_pf(p_hwfn); | |
1696 | qed_cm_init_pf(p_hwfn); | |
1697 | qed_dq_init_pf(p_hwfn); | |
dbb799c3 | 1698 | qed_cdu_init_pf(p_hwfn); |
fe56b9e6 | 1699 | qed_ilt_init_pf(p_hwfn); |
dbb799c3 YM |
1700 | qed_src_init_pf(p_hwfn); |
1701 | qed_tm_init_pf(p_hwfn); | |
fe56b9e6 YM |
1702 | } |
1703 | ||
1704 | int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn, | |
1705 | enum protocol_type type, | |
1706 | u32 *p_cid) | |
1707 | { | |
1708 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
1709 | u32 rel_cid; | |
1710 | ||
1711 | if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) { | |
1712 | DP_NOTICE(p_hwfn, "Invalid protocol type %d", type); | |
1713 | return -EINVAL; | |
1714 | } | |
1715 | ||
1716 | rel_cid = find_first_zero_bit(p_mngr->acquired[type].cid_map, | |
1717 | p_mngr->acquired[type].max_count); | |
1718 | ||
1719 | if (rel_cid >= p_mngr->acquired[type].max_count) { | |
1720 | DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", | |
1721 | type); | |
1722 | return -EINVAL; | |
1723 | } | |
1724 | ||
1725 | __set_bit(rel_cid, p_mngr->acquired[type].cid_map); | |
1726 | ||
1727 | *p_cid = rel_cid + p_mngr->acquired[type].start_cid; | |
1728 | ||
1729 | return 0; | |
1730 | } | |
1731 | ||
1732 | static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn, | |
1733 | u32 cid, | |
1734 | enum protocol_type *p_type) | |
1735 | { | |
1736 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
1737 | struct qed_cid_acquired_map *p_map; | |
1738 | enum protocol_type p; | |
1739 | u32 rel_cid; | |
1740 | ||
1741 | /* Iterate over protocols and find matching cid range */ | |
1742 | for (p = 0; p < MAX_CONN_TYPES; p++) { | |
1743 | p_map = &p_mngr->acquired[p]; | |
1744 | ||
1745 | if (!p_map->cid_map) | |
1746 | continue; | |
1747 | if (cid >= p_map->start_cid && | |
1748 | cid < p_map->start_cid + p_map->max_count) | |
1749 | break; | |
1750 | } | |
1751 | *p_type = p; | |
1752 | ||
1753 | if (p == MAX_CONN_TYPES) { | |
1754 | DP_NOTICE(p_hwfn, "Invalid CID %d", cid); | |
1755 | return false; | |
1756 | } | |
1757 | ||
1758 | rel_cid = cid - p_map->start_cid; | |
1759 | if (!test_bit(rel_cid, p_map->cid_map)) { | |
1760 | DP_NOTICE(p_hwfn, "CID %d not acquired", cid); | |
1761 | return false; | |
1762 | } | |
1763 | return true; | |
1764 | } | |
1765 | ||
1766 | void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, | |
1767 | u32 cid) | |
1768 | { | |
1769 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
1770 | enum protocol_type type; | |
1771 | bool b_acquired; | |
1772 | u32 rel_cid; | |
1773 | ||
1774 | /* Test acquired and find matching per-protocol map */ | |
1775 | b_acquired = qed_cxt_test_cid_acquired(p_hwfn, cid, &type); | |
1776 | ||
1777 | if (!b_acquired) | |
1778 | return; | |
1779 | ||
1780 | rel_cid = cid - p_mngr->acquired[type].start_cid; | |
1781 | __clear_bit(rel_cid, p_mngr->acquired[type].cid_map); | |
1782 | } | |
1783 | ||
1784 | int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, | |
1785 | struct qed_cxt_info *p_info) | |
1786 | { | |
1787 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
1788 | u32 conn_cxt_size, hw_p_size, cxts_per_p, line; | |
1789 | enum protocol_type type; | |
1790 | bool b_acquired; | |
1791 | ||
1792 | /* Test acquired and find matching per-protocol map */ | |
1793 | b_acquired = qed_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type); | |
1794 | ||
1795 | if (!b_acquired) | |
1796 | return -EINVAL; | |
1797 | ||
1798 | /* set the protocl type */ | |
1799 | p_info->type = type; | |
1800 | ||
1801 | /* compute context virtual pointer */ | |
1802 | hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; | |
1803 | ||
1804 | conn_cxt_size = CONN_CXT_SIZE(p_hwfn); | |
1805 | cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size; | |
1806 | line = p_info->iid / cxts_per_p; | |
1807 | ||
1808 | /* Make sure context is allocated (dynamic allocation) */ | |
1809 | if (!p_mngr->ilt_shadow[line].p_virt) | |
1810 | return -EINVAL; | |
1811 | ||
1812 | p_info->p_cxt = p_mngr->ilt_shadow[line].p_virt + | |
1813 | p_info->iid % cxts_per_p * conn_cxt_size; | |
1814 | ||
1815 | DP_VERBOSE(p_hwfn, (QED_MSG_ILT | QED_MSG_CXT), | |
1816 | "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n", | |
1817 | p_info->iid / cxts_per_p, p_info->p_cxt, p_info->iid); | |
1818 | ||
1819 | return 0; | |
1820 | } | |
1821 | ||
dbb799c3 YM |
1822 | void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn, |
1823 | struct qed_rdma_pf_params *p_params) | |
fe56b9e6 | 1824 | { |
dbb799c3 YM |
1825 | u32 num_cons, num_tasks, num_qps, num_mrs, num_srqs; |
1826 | enum protocol_type proto; | |
1827 | ||
1828 | num_mrs = min_t(u32, RDMA_MAX_TIDS, p_params->num_mrs); | |
1829 | num_tasks = num_mrs; /* each mr uses a single task id */ | |
1830 | num_srqs = min_t(u32, 32 * 1024, p_params->num_srqs); | |
1831 | ||
1832 | switch (p_hwfn->hw_info.personality) { | |
1833 | case QED_PCI_ETH_ROCE: | |
1834 | num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps); | |
1835 | num_cons = num_qps * 2; /* each QP requires two connections */ | |
1836 | proto = PROTOCOLID_ROCE; | |
1837 | break; | |
1838 | default: | |
1839 | return; | |
1840 | } | |
1841 | ||
1842 | if (num_cons && num_tasks) { | |
1843 | qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0); | |
1844 | ||
1845 | /* Deliberatly passing ROCE for tasks id. This is because | |
1846 | * iWARP / RoCE share the task id. | |
1847 | */ | |
1848 | qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE, | |
1849 | QED_CXT_ROCE_TID_SEG, 1, | |
1850 | num_tasks, false); | |
1851 | qed_cxt_set_srq_count(p_hwfn, num_srqs); | |
1852 | } else { | |
1853 | DP_INFO(p_hwfn->cdev, | |
1854 | "RDMA personality used without setting params!\n"); | |
1855 | } | |
1856 | } | |
fe56b9e6 | 1857 | |
dbb799c3 YM |
1858 | int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn) |
1859 | { | |
fe56b9e6 YM |
1860 | /* Set the number of required CORE connections */ |
1861 | u32 core_cids = 1; /* SPQ */ | |
1862 | ||
1408cc1f | 1863 | qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0); |
fe56b9e6 | 1864 | |
dbb799c3 YM |
1865 | switch (p_hwfn->hw_info.personality) { |
1866 | case QED_PCI_ETH_ROCE: | |
1867 | { | |
1868 | qed_rdma_set_pf_params(p_hwfn, | |
1869 | &p_hwfn-> | |
1870 | pf_params.rdma_pf_params); | |
1871 | /* no need for break since RoCE coexist with Ethernet */ | |
1872 | } | |
1873 | case QED_PCI_ETH: | |
1874 | { | |
1875 | struct qed_eth_pf_params *p_params = | |
1876 | &p_hwfn->pf_params.eth_pf_params; | |
1877 | ||
1878 | qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH, | |
1879 | p_params->num_cons, 1); | |
1880 | break; | |
1881 | } | |
1882 | case QED_PCI_ISCSI: | |
1883 | { | |
1884 | struct qed_iscsi_pf_params *p_params; | |
1885 | ||
1886 | p_params = &p_hwfn->pf_params.iscsi_pf_params; | |
1887 | ||
1888 | if (p_params->num_cons && p_params->num_tasks) { | |
1889 | qed_cxt_set_proto_cid_count(p_hwfn, | |
1890 | PROTOCOLID_ISCSI, | |
1891 | p_params->num_cons, | |
1892 | 0); | |
1893 | ||
1894 | qed_cxt_set_proto_tid_count(p_hwfn, | |
1895 | PROTOCOLID_ISCSI, | |
1896 | QED_CXT_ISCSI_TID_SEG, | |
1897 | 0, | |
1898 | p_params->num_tasks, | |
1899 | true); | |
1900 | } else { | |
1901 | DP_INFO(p_hwfn->cdev, | |
1902 | "Iscsi personality used without setting params!\n"); | |
1903 | } | |
1904 | break; | |
1905 | } | |
1906 | default: | |
1907 | return -EINVAL; | |
1908 | } | |
1909 | ||
1910 | return 0; | |
1911 | } | |
1912 | ||
1913 | int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn, | |
1914 | struct qed_tid_mem *p_info) | |
1915 | { | |
1916 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
1917 | u32 proto, seg, total_lines, i, shadow_line; | |
1918 | struct qed_ilt_client_cfg *p_cli; | |
1919 | struct qed_ilt_cli_blk *p_fl_seg; | |
1920 | struct qed_tid_seg *p_seg_info; | |
1921 | ||
1922 | /* Verify the personality */ | |
1923 | switch (p_hwfn->hw_info.personality) { | |
1924 | case QED_PCI_ISCSI: | |
1925 | proto = PROTOCOLID_ISCSI; | |
1926 | seg = QED_CXT_ISCSI_TID_SEG; | |
1927 | break; | |
1928 | default: | |
1929 | return -EINVAL; | |
1930 | } | |
1931 | ||
1932 | p_cli = &p_mngr->clients[ILT_CLI_CDUT]; | |
1933 | if (!p_cli->active) | |
1934 | return -EINVAL; | |
1935 | ||
1936 | p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; | |
1937 | if (!p_seg_info->has_fl_mem) | |
1938 | return -EINVAL; | |
1939 | ||
1940 | p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; | |
1941 | total_lines = DIV_ROUND_UP(p_fl_seg->total_size, | |
1942 | p_fl_seg->real_size_in_page); | |
1943 | ||
1944 | for (i = 0; i < total_lines; i++) { | |
1945 | shadow_line = i + p_fl_seg->start_line - | |
1946 | p_hwfn->p_cxt_mngr->pf_start_line; | |
1947 | p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt; | |
1948 | } | |
1949 | p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) - | |
1950 | p_fl_seg->real_size_in_page; | |
1951 | p_info->tid_size = p_mngr->task_type_size[p_seg_info->type]; | |
1952 | p_info->num_tids_per_block = p_fl_seg->real_size_in_page / | |
1953 | p_info->tid_size; | |
1954 | ||
1955 | return 0; | |
1956 | } | |
1957 | ||
1958 | /* This function is very RoCE oriented, if another protocol in the future | |
1959 | * will want this feature we'll need to modify the function to be more generic | |
1960 | */ | |
1961 | int | |
1962 | qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn, | |
1963 | enum qed_cxt_elem_type elem_type, u32 iid) | |
1964 | { | |
1965 | u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; | |
1966 | struct qed_ilt_client_cfg *p_cli; | |
1967 | struct qed_ilt_cli_blk *p_blk; | |
1968 | struct qed_ptt *p_ptt; | |
1969 | dma_addr_t p_phys; | |
1970 | u64 ilt_hw_entry; | |
1971 | void *p_virt; | |
1972 | int rc = 0; | |
1973 | ||
1974 | switch (elem_type) { | |
1975 | case QED_ELEM_CXT: | |
1976 | p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; | |
1977 | elem_size = CONN_CXT_SIZE(p_hwfn); | |
1978 | p_blk = &p_cli->pf_blks[CDUC_BLK]; | |
1979 | break; | |
1980 | case QED_ELEM_SRQ: | |
1981 | p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; | |
1982 | elem_size = SRQ_CXT_SIZE; | |
1983 | p_blk = &p_cli->pf_blks[SRQ_BLK]; | |
1984 | break; | |
1985 | case QED_ELEM_TASK: | |
1986 | p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; | |
1987 | elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); | |
1988 | p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)]; | |
1989 | break; | |
1990 | default: | |
1991 | DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type); | |
1992 | return -EINVAL; | |
1993 | } | |
1994 | ||
1995 | /* Calculate line in ilt */ | |
1996 | hw_p_size = p_cli->p_size.val; | |
1997 | elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; | |
1998 | line = p_blk->start_line + (iid / elems_per_p); | |
1999 | shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line; | |
2000 | ||
2001 | /* If line is already allocated, do nothing, otherwise allocate it and | |
2002 | * write it to the PSWRQ2 registers. | |
2003 | * This section can be run in parallel from different contexts and thus | |
2004 | * a mutex protection is needed. | |
2005 | */ | |
2006 | ||
2007 | mutex_lock(&p_hwfn->p_cxt_mngr->mutex); | |
2008 | ||
2009 | if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt) | |
2010 | goto out0; | |
2011 | ||
2012 | p_ptt = qed_ptt_acquire(p_hwfn); | |
2013 | if (!p_ptt) { | |
2014 | DP_NOTICE(p_hwfn, | |
2015 | "QED_TIME_OUT on ptt acquire - dynamic allocation"); | |
2016 | rc = -EBUSY; | |
2017 | goto out0; | |
2018 | } | |
2019 | ||
2020 | p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, | |
2021 | p_blk->real_size_in_page, | |
2022 | &p_phys, GFP_KERNEL); | |
2023 | if (!p_virt) { | |
2024 | rc = -ENOMEM; | |
2025 | goto out1; | |
2026 | } | |
2027 | memset(p_virt, 0, p_blk->real_size_in_page); | |
2028 | ||
2029 | /* configuration of refTagMask to 0xF is required for RoCE DIF MR only, | |
2030 | * to compensate for a HW bug, but it is configured even if DIF is not | |
2031 | * enabled. This is harmless and allows us to avoid a dedicated API. We | |
2032 | * configure the field for all of the contexts on the newly allocated | |
2033 | * page. | |
2034 | */ | |
2035 | if (elem_type == QED_ELEM_TASK) { | |
2036 | u32 elem_i; | |
2037 | u8 *elem_start = (u8 *)p_virt; | |
2038 | union type1_task_context *elem; | |
2039 | ||
2040 | for (elem_i = 0; elem_i < elems_per_p; elem_i++) { | |
2041 | elem = (union type1_task_context *)elem_start; | |
2042 | SET_FIELD(elem->roce_ctx.tdif_context.flags1, | |
2043 | TDIF_TASK_CONTEXT_REFTAGMASK, 0xf); | |
2044 | elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn); | |
2045 | } | |
2046 | } | |
2047 | ||
2048 | p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt; | |
2049 | p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys; | |
2050 | p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size = | |
2051 | p_blk->real_size_in_page; | |
2052 | ||
2053 | /* compute absolute offset */ | |
2054 | reg_offset = PSWRQ2_REG_ILT_MEMORY + | |
2055 | (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS); | |
2056 | ||
2057 | ilt_hw_entry = 0; | |
2058 | SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); | |
2059 | SET_FIELD(ilt_hw_entry, | |
2060 | ILT_ENTRY_PHY_ADDR, | |
2061 | (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12)); | |
2062 | ||
2063 | /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */ | |
2064 | qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry, | |
2065 | reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 0); | |
2066 | ||
2067 | if (elem_type == QED_ELEM_CXT) { | |
2068 | u32 last_cid_allocated = (1 + (iid / elems_per_p)) * | |
2069 | elems_per_p; | |
2070 | ||
2071 | /* Update the relevant register in the parser */ | |
2072 | qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, | |
2073 | last_cid_allocated - 1); | |
2074 | ||
2075 | if (!p_hwfn->b_rdma_enabled_in_prs) { | |
2076 | /* Enable RoCE search */ | |
2077 | qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1); | |
2078 | p_hwfn->b_rdma_enabled_in_prs = true; | |
2079 | } | |
2080 | } | |
2081 | ||
2082 | out1: | |
2083 | qed_ptt_release(p_hwfn, p_ptt); | |
2084 | out0: | |
2085 | mutex_unlock(&p_hwfn->p_cxt_mngr->mutex); | |
2086 | ||
2087 | return rc; | |
2088 | } | |
2089 | ||
2090 | /* This function is very RoCE oriented, if another protocol in the future | |
2091 | * will want this feature we'll need to modify the function to be more generic | |
2092 | */ | |
2093 | static int | |
2094 | qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn, | |
2095 | enum qed_cxt_elem_type elem_type, | |
2096 | u32 start_iid, u32 count) | |
2097 | { | |
2098 | u32 start_line, end_line, shadow_start_line, shadow_end_line; | |
2099 | u32 reg_offset, elem_size, hw_p_size, elems_per_p; | |
2100 | struct qed_ilt_client_cfg *p_cli; | |
2101 | struct qed_ilt_cli_blk *p_blk; | |
2102 | u32 end_iid = start_iid + count; | |
2103 | struct qed_ptt *p_ptt; | |
2104 | u64 ilt_hw_entry = 0; | |
2105 | u32 i; | |
2106 | ||
2107 | switch (elem_type) { | |
2108 | case QED_ELEM_CXT: | |
2109 | p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; | |
2110 | elem_size = CONN_CXT_SIZE(p_hwfn); | |
2111 | p_blk = &p_cli->pf_blks[CDUC_BLK]; | |
2112 | break; | |
2113 | case QED_ELEM_SRQ: | |
2114 | p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; | |
2115 | elem_size = SRQ_CXT_SIZE; | |
2116 | p_blk = &p_cli->pf_blks[SRQ_BLK]; | |
2117 | break; | |
2118 | case QED_ELEM_TASK: | |
2119 | p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; | |
2120 | elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); | |
2121 | p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)]; | |
2122 | break; | |
2123 | default: | |
2124 | DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type); | |
2125 | return -EINVAL; | |
2126 | } | |
2127 | ||
2128 | /* Calculate line in ilt */ | |
2129 | hw_p_size = p_cli->p_size.val; | |
2130 | elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; | |
2131 | start_line = p_blk->start_line + (start_iid / elems_per_p); | |
2132 | end_line = p_blk->start_line + (end_iid / elems_per_p); | |
2133 | if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p)) | |
2134 | end_line--; | |
2135 | ||
2136 | shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line; | |
2137 | shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line; | |
2138 | ||
2139 | p_ptt = qed_ptt_acquire(p_hwfn); | |
2140 | if (!p_ptt) { | |
2141 | DP_NOTICE(p_hwfn, | |
2142 | "QED_TIME_OUT on ptt acquire - dynamic allocation"); | |
2143 | return -EBUSY; | |
2144 | } | |
2145 | ||
2146 | for (i = shadow_start_line; i < shadow_end_line; i++) { | |
2147 | if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt) | |
2148 | continue; | |
2149 | ||
2150 | dma_free_coherent(&p_hwfn->cdev->pdev->dev, | |
2151 | p_hwfn->p_cxt_mngr->ilt_shadow[i].size, | |
2152 | p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt, | |
2153 | p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys); | |
2154 | ||
2155 | p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = NULL; | |
2156 | p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0; | |
2157 | p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0; | |
2158 | ||
2159 | /* compute absolute offset */ | |
2160 | reg_offset = PSWRQ2_REG_ILT_MEMORY + | |
2161 | ((start_line++) * ILT_REG_SIZE_IN_BYTES * | |
2162 | ILT_ENTRY_IN_REGS); | |
2163 | ||
2164 | /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a | |
2165 | * wide-bus. | |
2166 | */ | |
2167 | qed_dmae_host2grc(p_hwfn, p_ptt, | |
2168 | (u64) (uintptr_t) &ilt_hw_entry, | |
2169 | reg_offset, | |
2170 | sizeof(ilt_hw_entry) / sizeof(u32), | |
2171 | 0); | |
2172 | } | |
2173 | ||
2174 | qed_ptt_release(p_hwfn, p_ptt); | |
2175 | ||
2176 | return 0; | |
2177 | } | |
2178 | ||
2179 | int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto) | |
2180 | { | |
2181 | int rc; | |
2182 | u32 cid; | |
2183 | ||
2184 | /* Free Connection CXT */ | |
2185 | rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT, | |
2186 | qed_cxt_get_proto_cid_start(p_hwfn, | |
2187 | proto), | |
2188 | qed_cxt_get_proto_cid_count(p_hwfn, | |
2189 | proto, &cid)); | |
2190 | ||
2191 | if (rc) | |
2192 | return rc; | |
2193 | ||
2194 | /* Free Task CXT */ | |
2195 | rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0, | |
2196 | qed_cxt_get_proto_tid_count(p_hwfn, proto)); | |
2197 | if (rc) | |
2198 | return rc; | |
2199 | ||
2200 | /* Free TSDM CXT */ | |
2201 | rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 0, | |
2202 | qed_cxt_get_srq_count(p_hwfn)); | |
2203 | ||
2204 | return rc; | |
2205 | } | |
2206 | ||
2207 | int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn, | |
2208 | u32 tid, u8 ctx_type, void **pp_task_ctx) | |
2209 | { | |
2210 | struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; | |
2211 | struct qed_ilt_client_cfg *p_cli; | |
2212 | struct qed_ilt_cli_blk *p_seg; | |
2213 | struct qed_tid_seg *p_seg_info; | |
2214 | u32 proto, seg; | |
2215 | u32 total_lines; | |
2216 | u32 tid_size, ilt_idx; | |
2217 | u32 num_tids_per_block; | |
2218 | ||
2219 | /* Verify the personality */ | |
2220 | switch (p_hwfn->hw_info.personality) { | |
2221 | case QED_PCI_ISCSI: | |
2222 | proto = PROTOCOLID_ISCSI; | |
2223 | seg = QED_CXT_ISCSI_TID_SEG; | |
2224 | break; | |
2225 | default: | |
2226 | return -EINVAL; | |
2227 | } | |
2228 | ||
2229 | p_cli = &p_mngr->clients[ILT_CLI_CDUT]; | |
2230 | if (!p_cli->active) | |
2231 | return -EINVAL; | |
2232 | ||
2233 | p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; | |
2234 | ||
2235 | if (ctx_type == QED_CTX_WORKING_MEM) { | |
2236 | p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)]; | |
2237 | } else if (ctx_type == QED_CTX_FL_MEM) { | |
2238 | if (!p_seg_info->has_fl_mem) | |
2239 | return -EINVAL; | |
2240 | p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; | |
2241 | } else { | |
2242 | return -EINVAL; | |
2243 | } | |
2244 | total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page); | |
2245 | tid_size = p_mngr->task_type_size[p_seg_info->type]; | |
2246 | num_tids_per_block = p_seg->real_size_in_page / tid_size; | |
2247 | ||
2248 | if (total_lines < tid / num_tids_per_block) | |
2249 | return -EINVAL; | |
2250 | ||
2251 | ilt_idx = tid / num_tids_per_block + p_seg->start_line - | |
2252 | p_mngr->pf_start_line; | |
2253 | *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt + | |
2254 | (tid % num_tids_per_block) * tid_size; | |
fe56b9e6 YM |
2255 | |
2256 | return 0; | |
2257 | } |