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qed: Utilize FW 8.10.3.0
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qed / qed_dev.c
CommitLineData
fe56b9e6
YM		 1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#include <linux/types.h>
10#include <asm/byteorder.h>
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/dma-mapping.h>
14#include <linux/errno.h>
15#include <linux/kernel.h>
16#include <linux/mutex.h>
17#include <linux/pci.h>
18#include <linux/slab.h>
19#include <linux/string.h>
20#include <linux/etherdevice.h>
21#include <linux/qed/qed_chain.h>
22#include <linux/qed/qed_if.h>
23#include "qed.h"
24#include "qed_cxt.h"
39651abd 25#include "qed_dcbx.h"
fe56b9e6
YM		 26#include "qed_dev_api.h"
27#include "qed_hsi.h"
28#include "qed_hw.h"
29#include "qed_init_ops.h"
30#include "qed_int.h"
31#include "qed_mcp.h"
32#include "qed_reg_addr.h"
33#include "qed_sp.h"
32a47e72 34#include "qed_sriov.h"
0b55e27d 35#include "qed_vf.h"
fe56b9e6 36
39651abd
SRK		 37static spinlock_t qm_lock;
38static bool qm_lock_init = false;
39
fe56b9e6 40/* API common to all protocols */
c2035eea
RA		 41enum BAR_ID {
42 BAR_ID_0, /* used for GRC */
43 BAR_ID_1 /* Used for doorbells */
44};
45
46static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
47 enum BAR_ID bar_id)
48{
1408cc1f
YM		 49 u32 bar_reg = (bar_id == BAR_ID_0 ?
50 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
51 u32 val;
c2035eea 52
1408cc1f
YM		 53 if (IS_VF(p_hwfn->cdev))
54 return 1 << 17;
55
56 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
c2035eea
RA		 57 if (val)
58 return 1 << (val + 15);
59
60 /* Old MFW initialized above registered only conditionally */
61 if (p_hwfn->cdev->num_hwfns > 1) {
62 DP_INFO(p_hwfn,
63 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
64 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
65 } else {
66 DP_INFO(p_hwfn,
67 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
68 return 512 * 1024;
69 }
70}
71
fe56b9e6
YM		 72void qed_init_dp(struct qed_dev *cdev,
73 u32 dp_module, u8 dp_level)
74{
75 u32 i;
76
77 cdev->dp_level = dp_level;
78 cdev->dp_module = dp_module;
79 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
80 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
81
82 p_hwfn->dp_level = dp_level;
83 p_hwfn->dp_module = dp_module;
84 }
85}
86
87void qed_init_struct(struct qed_dev *cdev)
88{
89 u8 i;
90
91 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
92 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
93
94 p_hwfn->cdev = cdev;
95 p_hwfn->my_id = i;
96 p_hwfn->b_active = false;
97
98 mutex_init(&p_hwfn->dmae_info.mutex);
99 }
100
101 /* hwfn 0 is always active */
102 cdev->hwfns[0].b_active = true;
103
104 /* set the default cache alignment to 128 */
105 cdev->cache_shift = 7;
106}
107
108static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
109{
110 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
111
112 kfree(qm_info->qm_pq_params);
113 qm_info->qm_pq_params = NULL;
114 kfree(qm_info->qm_vport_params);
115 qm_info->qm_vport_params = NULL;
116 kfree(qm_info->qm_port_params);
117 qm_info->qm_port_params = NULL;
bcd197c8
MC		 118 kfree(qm_info->wfq_data);
119 qm_info->wfq_data = NULL;
fe56b9e6
YM		 120}
121
122void qed_resc_free(struct qed_dev *cdev)
123{
124 int i;
125
1408cc1f
YM		 126 if (IS_VF(cdev))
127 return;
128
fe56b9e6
YM		 129 kfree(cdev->fw_data);
130 cdev->fw_data = NULL;
131
132 kfree(cdev->reset_stats);
133
25c089d7
YM		 134 for_each_hwfn(cdev, i) {
135 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
136
137 kfree(p_hwfn->p_tx_cids);
138 p_hwfn->p_tx_cids = NULL;
139 kfree(p_hwfn->p_rx_cids);
140 p_hwfn->p_rx_cids = NULL;
141 }
142
fe56b9e6
YM		 143 for_each_hwfn(cdev, i) {
144 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
145
146 qed_cxt_mngr_free(p_hwfn);
147 qed_qm_info_free(p_hwfn);
148 qed_spq_free(p_hwfn);
149 qed_eq_free(p_hwfn, p_hwfn->p_eq);
150 qed_consq_free(p_hwfn, p_hwfn->p_consq);
151 qed_int_free(p_hwfn);
32a47e72 152 qed_iov_free(p_hwfn);
fe56b9e6 153 qed_dmae_info_free(p_hwfn);
39651abd 154 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
fe56b9e6
YM		 155 }
156}
157
79529291 158static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
fe56b9e6 159{
1408cc1f 160 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
fe56b9e6
YM		 161 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
162 struct init_qm_port_params *p_qm_port;
fe56b9e6 163 u16 num_pqs, multi_cos_tcs = 1;
cc3d5eb0
YM		 164 u8 pf_wfq = qm_info->pf_wfq;
165 u32 pf_rl = qm_info->pf_rl;
1408cc1f 166 u16 num_vfs = 0;
fe56b9e6 167
1408cc1f
YM		 168#ifdef CONFIG_QED_SRIOV
169 if (p_hwfn->cdev->p_iov_info)
170 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
171#endif
fe56b9e6
YM		 172 memset(qm_info, 0, sizeof(*qm_info));
173
1408cc1f 174 num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */
fe56b9e6
YM		 175 num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
176
177 /* Sanity checking that setup requires legal number of resources */
178 if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
179 DP_ERR(p_hwfn,
180 "Need too many Physical queues - 0x%04x when only %04x are available\n",
181 num_pqs, RESC_NUM(p_hwfn, QED_PQ));
182 return -EINVAL;
183 }
184
185 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
186 */
79529291
SRK		 187 qm_info->qm_pq_params = kcalloc(num_pqs,
188 sizeof(struct init_qm_pq_params),
189 b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
fe56b9e6
YM		 190 if (!qm_info->qm_pq_params)
191 goto alloc_err;
192
79529291
SRK		 193 qm_info->qm_vport_params = kcalloc(num_vports,
194 sizeof(struct init_qm_vport_params),
195 b_sleepable ? GFP_KERNEL
196 : GFP_ATOMIC);
fe56b9e6
YM		 197 if (!qm_info->qm_vport_params)
198 goto alloc_err;
199
79529291
SRK		 200 qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS,
201 sizeof(struct init_qm_port_params),
202 b_sleepable ? GFP_KERNEL
203 : GFP_ATOMIC);
fe56b9e6
YM		 204 if (!qm_info->qm_port_params)
205 goto alloc_err;
206
79529291
SRK		 207 qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data),
208 b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
bcd197c8
MC		 209 if (!qm_info->wfq_data)
210 goto alloc_err;
211
fe56b9e6
YM		 212 vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
213
214 /* First init per-TC PQs */
39651abd 215 for (i = 0; i < multi_cos_tcs; i++) {
1408cc1f 216 struct init_qm_pq_params *params =
39651abd
SRK		 217 &qm_info->qm_pq_params[curr_queue++];
218
219 if (p_hwfn->hw_info.personality == QED_PCI_ETH) {
220 params->vport_id = vport_id;
221 params->tc_id = p_hwfn->hw_info.non_offload_tc;
222 params->wrr_group = 1;
223 } else {
224 params->vport_id = vport_id;
225 params->tc_id = p_hwfn->hw_info.offload_tc;
226 params->wrr_group = 1;
227 }
fe56b9e6
YM		 228 }
229
230 /* Then init pure-LB PQ */
1408cc1f
YM		 231 qm_info->pure_lb_pq = curr_queue;
232 qm_info->qm_pq_params[curr_queue].vport_id =
233 (u8) RESC_START(p_hwfn, QED_VPORT);
234 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
235 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
236 curr_queue++;
fe56b9e6
YM		 237
238 qm_info->offload_pq = 0;
1408cc1f
YM		 239 /* Then init per-VF PQs */
240 vf_offset = curr_queue;
241 for (i = 0; i < num_vfs; i++) {
242 /* First vport is used by the PF */
243 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
244 qm_info->qm_pq_params[curr_queue].tc_id =
245 p_hwfn->hw_info.non_offload_tc;
246 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
351a4ded 247 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
1408cc1f
YM		 248 curr_queue++;
249 }
250
251 qm_info->vf_queues_offset = vf_offset;
fe56b9e6
YM		 252 qm_info->num_pqs = num_pqs;
253 qm_info->num_vports = num_vports;
254
255 /* Initialize qm port parameters */
256 num_ports = p_hwfn->cdev->num_ports_in_engines;
257 for (i = 0; i < num_ports; i++) {
258 p_qm_port = &qm_info->qm_port_params[i];
259 p_qm_port->active = 1;
351a4ded
YM		 260 if (num_ports == 4)
261 p_qm_port->active_phys_tcs = 0x7;
262 else
263 p_qm_port->active_phys_tcs = 0x9f;
fe56b9e6
YM		 264 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
265 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
266 }
267
268 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
269
270 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
271
1408cc1f
YM		 272 qm_info->num_vf_pqs = num_vfs;
273 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
fe56b9e6 274
a64b02d5
MC		 275 for (i = 0; i < qm_info->num_vports; i++)
276 qm_info->qm_vport_params[i].vport_wfq = 1;
277
fe56b9e6 278 qm_info->vport_rl_en = 1;
a64b02d5 279 qm_info->vport_wfq_en = 1;
cc3d5eb0
YM		 280 qm_info->pf_rl = pf_rl;
281 qm_info->pf_wfq = pf_wfq;
fe56b9e6
YM		 282
283 return 0;
284
285alloc_err:
286 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
bcd197c8 287 qed_qm_info_free(p_hwfn);
fe56b9e6
YM		 288 return -ENOMEM;
289}
290
39651abd
SRK		 291/* This function reconfigures the QM pf on the fly.
292 * For this purpose we:
293 * 1. reconfigure the QM database
294 * 2. set new values to runtime arrat
295 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
296 * 4. activate init tool in QM_PF stage
297 * 5. send an sdm_qm_cmd through rbc interface to release the QM
298 */
299int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
300{
301 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
302 bool b_rc;
303 int rc;
304
305 /* qm_info is allocated in qed_init_qm_info() which is already called
306 * from qed_resc_alloc() or previous call of qed_qm_reconf().
307 * The allocated size may change each init, so we free it before next
308 * allocation.
309 */
310 qed_qm_info_free(p_hwfn);
311
312 /* initialize qed's qm data structure */
79529291 313 rc = qed_init_qm_info(p_hwfn, false);
39651abd
SRK		 314 if (rc)
315 return rc;
316
317 /* stop PF's qm queues */
318 spin_lock_bh(&qm_lock);
319 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
320 qm_info->start_pq, qm_info->num_pqs);
321 spin_unlock_bh(&qm_lock);
322 if (!b_rc)
323 return -EINVAL;
324
325 /* clear the QM_PF runtime phase leftovers from previous init */
326 qed_init_clear_rt_data(p_hwfn);
327
328 /* prepare QM portion of runtime array */
329 qed_qm_init_pf(p_hwfn);
330
331 /* activate init tool on runtime array */
332 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
333 p_hwfn->hw_info.hw_mode);
334 if (rc)
335 return rc;
336
337 /* start PF's qm queues */
338 spin_lock_bh(&qm_lock);
339 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
340 qm_info->start_pq, qm_info->num_pqs);
341 spin_unlock_bh(&qm_lock);
342 if (!b_rc)
343 return -EINVAL;
344
345 return 0;
346}
347
fe56b9e6
YM		 348int qed_resc_alloc(struct qed_dev *cdev)
349{
350 struct qed_consq *p_consq;
351 struct qed_eq *p_eq;
352 int i, rc = 0;
353
1408cc1f
YM		 354 if (IS_VF(cdev))
355 return rc;
356
fe56b9e6
YM		 357 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
358 if (!cdev->fw_data)
359 return -ENOMEM;
360
25c089d7
YM		 361 /* Allocate Memory for the Queue->CID mapping */
362 for_each_hwfn(cdev, i) {
363 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
364 int tx_size = sizeof(struct qed_hw_cid_data) *
365 RESC_NUM(p_hwfn, QED_L2_QUEUE);
366 int rx_size = sizeof(struct qed_hw_cid_data) *
367 RESC_NUM(p_hwfn, QED_L2_QUEUE);
368
369 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL);
370 if (!p_hwfn->p_tx_cids) {
371 DP_NOTICE(p_hwfn,
372 "Failed to allocate memory for Tx Cids\n");
9b15acbf 373 rc = -ENOMEM;
25c089d7
YM		 374 goto alloc_err;
375 }
376
377 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
378 if (!p_hwfn->p_rx_cids) {
379 DP_NOTICE(p_hwfn,
380 "Failed to allocate memory for Rx Cids\n");
9b15acbf 381 rc = -ENOMEM;
25c089d7
YM		 382 goto alloc_err;
383 }
384 }
385
fe56b9e6
YM		 386 for_each_hwfn(cdev, i) {
387 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
388
389 /* First allocate the context manager structure */
390 rc = qed_cxt_mngr_alloc(p_hwfn);
391 if (rc)
392 goto alloc_err;
393
394 /* Set the HW cid/tid numbers (in the contest manager)
395 * Must be done prior to any further computations.
396 */
397 rc = qed_cxt_set_pf_params(p_hwfn);
398 if (rc)
399 goto alloc_err;
400
401 /* Prepare and process QM requirements */
79529291 402 rc = qed_init_qm_info(p_hwfn, true);
fe56b9e6
YM		 403 if (rc)
404 goto alloc_err;
405
406 /* Compute the ILT client partition */
407 rc = qed_cxt_cfg_ilt_compute(p_hwfn);
408 if (rc)
409 goto alloc_err;
410
411 /* CID map / ILT shadow table / T2
412 * The talbes sizes are determined by the computations above
413 */
414 rc = qed_cxt_tables_alloc(p_hwfn);
415 if (rc)
416 goto alloc_err;
417
418 /* SPQ, must follow ILT because initializes SPQ context */
419 rc = qed_spq_alloc(p_hwfn);
420 if (rc)
421 goto alloc_err;
422
423 /* SP status block allocation */
424 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
425 RESERVED_PTT_DPC);
426
427 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
428 if (rc)
429 goto alloc_err;
430
32a47e72
YM		 431 rc = qed_iov_alloc(p_hwfn);
432 if (rc)
433 goto alloc_err;
434
fe56b9e6
YM		 435 /* EQ */
436 p_eq = qed_eq_alloc(p_hwfn, 256);
9b15acbf
DC		 437 if (!p_eq) {
438 rc = -ENOMEM;
fe56b9e6 439 goto alloc_err;
9b15acbf 440 }
fe56b9e6
YM		 441 p_hwfn->p_eq = p_eq;
442
443 p_consq = qed_consq_alloc(p_hwfn);
9b15acbf
DC		 444 if (!p_consq) {
445 rc = -ENOMEM;
fe56b9e6 446 goto alloc_err;
9b15acbf 447 }
fe56b9e6
YM		 448 p_hwfn->p_consq = p_consq;
449
450 /* DMA info initialization */
451 rc = qed_dmae_info_alloc(p_hwfn);
452 if (rc) {
453 DP_NOTICE(p_hwfn,
454 "Failed to allocate memory for dmae_info structure\n");
455 goto alloc_err;
456 }
39651abd
SRK		 457
458 /* DCBX initialization */
459 rc = qed_dcbx_info_alloc(p_hwfn);
460 if (rc) {
461 DP_NOTICE(p_hwfn,
462 "Failed to allocate memory for dcbx structure\n");
463 goto alloc_err;
464 }
fe56b9e6
YM		 465 }
466
467 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
468 if (!cdev->reset_stats) {
469 DP_NOTICE(cdev, "Failed to allocate reset statistics\n");
9b15acbf 470 rc = -ENOMEM;
fe56b9e6
YM		 471 goto alloc_err;
472 }
473
474 return 0;
475
476alloc_err:
477 qed_resc_free(cdev);
478 return rc;
479}
480
481void qed_resc_setup(struct qed_dev *cdev)
482{
483 int i;
484
1408cc1f
YM		 485 if (IS_VF(cdev))
486 return;
487
fe56b9e6
YM		 488 for_each_hwfn(cdev, i) {
489 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
490
491 qed_cxt_mngr_setup(p_hwfn);
492 qed_spq_setup(p_hwfn);
493 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
494 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
495
496 /* Read shadow of current MFW mailbox */
497 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
498 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
499 p_hwfn->mcp_info->mfw_mb_cur,
500 p_hwfn->mcp_info->mfw_mb_length);
501
502 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
32a47e72
YM		 503
504 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
fe56b9e6
YM		 505 }
506}
507
fe56b9e6
YM		 508#define FINAL_CLEANUP_POLL_CNT (100)
509#define FINAL_CLEANUP_POLL_TIME (10)
510int qed_final_cleanup(struct qed_hwfn *p_hwfn,
0b55e27d 511 struct qed_ptt *p_ptt, u16 id, bool is_vf)
fe56b9e6
YM		 512{
513 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
514 int rc = -EBUSY;
515
fc48b7a6
YM		 516 addr = GTT_BAR0_MAP_REG_USDM_RAM +
517 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
fe56b9e6 518
0b55e27d
YM		 519 if (is_vf)
520 id += 0x10;
521
fc48b7a6
YM		 522 command |= X_FINAL_CLEANUP_AGG_INT <<
523 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
524 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
525 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
526 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
fe56b9e6
YM		 527
528 /* Make sure notification is not set before initiating final cleanup */
529 if (REG_RD(p_hwfn, addr)) {
530 DP_NOTICE(
531 p_hwfn,
532 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
533 REG_WR(p_hwfn, addr, 0);
534 }
535
536 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
537 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
538 id, command);
539
540 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
541
542 /* Poll until completion */
543 while (!REG_RD(p_hwfn, addr) && count--)
544 msleep(FINAL_CLEANUP_POLL_TIME);
545
546 if (REG_RD(p_hwfn, addr))
547 rc = 0;
548 else
549 DP_NOTICE(p_hwfn,
550 "Failed to receive FW final cleanup notification\n");
551
552 /* Cleanup afterwards */
553 REG_WR(p_hwfn, addr, 0);
554
555 return rc;
556}
557
558static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
559{
560 int hw_mode = 0;
561
12e09c69 562 hw_mode = (1 << MODE_BB_B0);
fe56b9e6
YM		 563
564 switch (p_hwfn->cdev->num_ports_in_engines) {
565 case 1:
566 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
567 break;
568 case 2:
569 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
570 break;
571 case 4:
572 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
573 break;
574 default:
575 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
576 p_hwfn->cdev->num_ports_in_engines);
577 return;
578 }
579
580 switch (p_hwfn->cdev->mf_mode) {
fc48b7a6
YM		 581 case QED_MF_DEFAULT:
582 case QED_MF_NPAR:
583 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6 584 break;
fc48b7a6 585 case QED_MF_OVLAN:
fe56b9e6
YM		 586 hw_mode |= 1 << MODE_MF_SD;
587 break;
fe56b9e6 588 default:
fc48b7a6
YM		 589 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
590 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6
YM		 591 }
592
593 hw_mode |= 1 << MODE_ASIC;
594
1af9dcf7
YM		 595 if (p_hwfn->cdev->num_hwfns > 1)
596 hw_mode |= 1 << MODE_100G;
597
fe56b9e6 598 p_hwfn->hw_info.hw_mode = hw_mode;
1af9dcf7
YM		 599
600 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
601 "Configuring function for hw_mode: 0x%08x\n",
602 p_hwfn->hw_info.hw_mode);
fe56b9e6
YM		 603}
604
605/* Init run time data for all PFs on an engine. */
606static void qed_init_cau_rt_data(struct qed_dev *cdev)
607{
608 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
609 int i, sb_id;
610
611 for_each_hwfn(cdev, i) {
612 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
613 struct qed_igu_info *p_igu_info;
614 struct qed_igu_block *p_block;
615 struct cau_sb_entry sb_entry;
616
617 p_igu_info = p_hwfn->hw_info.p_igu_info;
618
619 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
620 sb_id++) {
621 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
622 if (!p_block->is_pf)
623 continue;
624
625 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
626 p_block->function_id,
627 0, 0);
628 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2,
629 sb_entry);
630 }
631 }
632}
633
634static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
635 struct qed_ptt *p_ptt,
636 int hw_mode)
637{
638 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
639 struct qed_qm_common_rt_init_params params;
640 struct qed_dev *cdev = p_hwfn->cdev;
1408cc1f 641 u32 concrete_fid;
fe56b9e6 642 int rc = 0;
1408cc1f 643 u8 vf_id;
fe56b9e6
YM		 644
645 qed_init_cau_rt_data(cdev);
646
647 /* Program GTT windows */
648 qed_gtt_init(p_hwfn);
649
650 if (p_hwfn->mcp_info) {
651 if (p_hwfn->mcp_info->func_info.bandwidth_max)
652 qm_info->pf_rl_en = 1;
653 if (p_hwfn->mcp_info->func_info.bandwidth_min)
654 qm_info->pf_wfq_en = 1;
655 }
656
657 memset(&params, 0, sizeof(params));
658 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
659 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
660 params.pf_rl_en = qm_info->pf_rl_en;
661 params.pf_wfq_en = qm_info->pf_wfq_en;
662 params.vport_rl_en = qm_info->vport_rl_en;
663 params.vport_wfq_en = qm_info->vport_wfq_en;
664 params.port_params = qm_info->qm_port_params;
665
666 qed_qm_common_rt_init(p_hwfn, &params);
667
668 qed_cxt_hw_init_common(p_hwfn);
669
670 /* Close gate from NIG to BRB/Storm; By default they are open, but
671 * we close them to prevent NIG from passing data to reset blocks.
672 * Should have been done in the ENGINE phase, but init-tool lacks
673 * proper port-pretend capabilities.
674 */
675 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
676 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
677 qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
678 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
679 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
680 qed_port_unpretend(p_hwfn, p_ptt);
681
682 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
683 if (rc != 0)
684 return rc;
685
686 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
687 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
688
689 /* Disable relaxed ordering in the PCI config space */
690 qed_wr(p_hwfn, p_ptt, 0x20b4,
691 qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10);
692
1408cc1f
YM		 693 for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
694 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
695 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
696 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
697 }
698 /* pretend to original PF */
699 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
700
fe56b9e6
YM		 701 return rc;
702}
703
704static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
705 struct qed_ptt *p_ptt,
706 int hw_mode)
707{
708 int rc = 0;
709
351a4ded
YM		 710 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
711 if (rc != 0)
712 return rc;
713
714 if (hw_mode & (1 << MODE_MF_SI)) {
715 u8 pf_id = 0;
716
717 if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) {
718 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
719 "PF[%08x] is first eth on engine\n", pf_id);
720
721 /* We should have configured BIT for ppfid, i.e., the
722 * relative function number in the port. But there's a
723 * bug in LLH in BB where the ppfid is actually engine
724 * based, so we need to take this into account.
725 */
726 qed_wr(p_hwfn, p_ptt,
727 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id);
728 }
729
730 /* Take the protocol-based hit vector if there is a hit,
731 * otherwise take the other vector.
732 */
733 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_CLS_TYPE_DUALMODE, 0x2);
734 }
fe56b9e6
YM		 735 return rc;
736}
737
738static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
739 struct qed_ptt *p_ptt,
464f6645 740 struct qed_tunn_start_params *p_tunn,
fe56b9e6
YM		 741 int hw_mode,
742 bool b_hw_start,
743 enum qed_int_mode int_mode,
744 bool allow_npar_tx_switch)
745{
746 u8 rel_pf_id = p_hwfn->rel_pf_id;
747 int rc = 0;
748
749 if (p_hwfn->mcp_info) {
750 struct qed_mcp_function_info *p_info;
751
752 p_info = &p_hwfn->mcp_info->func_info;
753 if (p_info->bandwidth_min)
754 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
755
756 /* Update rate limit once we'll actually have a link */
4b01e519 757 p_hwfn->qm_info.pf_rl = 100000;
fe56b9e6
YM		 758 }
759
760 qed_cxt_hw_init_pf(p_hwfn);
761
762 qed_int_igu_init_rt(p_hwfn);
763
764 /* Set VLAN in NIG if needed */
765 if (hw_mode & (1 << MODE_MF_SD)) {
766 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
767 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
768 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
769 p_hwfn->hw_info.ovlan);
770 }
771
772 /* Enable classification by MAC if needed */
87aec47d 773 if (hw_mode & (1 << MODE_MF_SI)) {
fe56b9e6
YM		 774 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
775 "Configuring TAGMAC_CLS_TYPE\n");
776 STORE_RT_REG(p_hwfn,
777 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
778 }
779
780 /* Protocl Configuration */
781 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0);
782 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
783 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
784
785 /* Cleanup chip from previous driver if such remains exist */
0b55e27d 786 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
fe56b9e6
YM		 787 if (rc != 0)
788 return rc;
789
790 /* PF Init sequence */
791 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
792 if (rc)
793 return rc;
794
795 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
796 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
797 if (rc)
798 return rc;
799
800 /* Pure runtime initializations - directly to the HW */
801 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
802
351a4ded
YM		 803 if (hw_mode & (1 << MODE_MF_SI)) {
804 u8 pf_id = 0;
805 u32 val;
806
807 if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) {
808 if (p_hwfn->rel_pf_id == pf_id) {
809 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
810 "PF[%d] is first ETH on engine\n",
811 pf_id);
812 val = 1;
813 }
814 qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, val);
815 }
816 }
817
fe56b9e6
YM		 818 if (b_hw_start) {
819 /* enable interrupts */
820 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
821
822 /* send function start command */
831bfb0e
YM		 823 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
824 allow_npar_tx_switch);
fe56b9e6
YM		 825 if (rc)
826 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
827 }
828 return rc;
829}
830
831static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
832 struct qed_ptt *p_ptt,
833 u8 enable)
834{
835 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
836
837 /* Change PF in PXP */
838 qed_wr(p_hwfn, p_ptt,
839 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
840
841 /* wait until value is set - try for 1 second every 50us */
842 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
843 val = qed_rd(p_hwfn, p_ptt,
844 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
845 if (val == set_val)
846 break;
847
848 usleep_range(50, 60);
849 }
850
851 if (val != set_val) {
852 DP_NOTICE(p_hwfn,
853 "PFID_ENABLE_MASTER wasn't changed after a second\n");
854 return -EAGAIN;
855 }
856
857 return 0;
858}
859
860static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
861 struct qed_ptt *p_main_ptt)
862{
863 /* Read shadow of current MFW mailbox */
864 qed_mcp_read_mb(p_hwfn, p_main_ptt);
865 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
866 p_hwfn->mcp_info->mfw_mb_cur,
867 p_hwfn->mcp_info->mfw_mb_length);
868}
869
870int qed_hw_init(struct qed_dev *cdev,
464f6645 871 struct qed_tunn_start_params *p_tunn,
fe56b9e6
YM		 872 bool b_hw_start,
873 enum qed_int_mode int_mode,
874 bool allow_npar_tx_switch,
875 const u8 *bin_fw_data)
876{
86622ee7 877 u32 load_code, param;
fe56b9e6
YM		 878 int rc, mfw_rc, i;
879
bb13ace7
SRK		 880 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
881 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
882 return -EINVAL;
883 }
884
1408cc1f
YM		 885 if (IS_PF(cdev)) {
886 rc = qed_init_fw_data(cdev, bin_fw_data);
887 if (rc != 0)
888 return rc;
889 }
fe56b9e6
YM		 890
891 for_each_hwfn(cdev, i) {
892 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
893
1408cc1f
YM		 894 if (IS_VF(cdev)) {
895 p_hwfn->b_int_enabled = 1;
896 continue;
897 }
898
fe56b9e6
YM		 899 /* Enable DMAE in PXP */
900 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
901
902 qed_calc_hw_mode(p_hwfn);
903
904 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
905 &load_code);
906 if (rc) {
907 DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n");
908 return rc;
909 }
910
911 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
912
913 DP_VERBOSE(p_hwfn, QED_MSG_SP,
914 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
915 rc, load_code);
916
917 p_hwfn->first_on_engine = (load_code ==
918 FW_MSG_CODE_DRV_LOAD_ENGINE);
919
39651abd
SRK		 920 if (!qm_lock_init) {
921 spin_lock_init(&qm_lock);
922 qm_lock_init = true;
923 }
924
fe56b9e6
YM		 925 switch (load_code) {
926 case FW_MSG_CODE_DRV_LOAD_ENGINE:
927 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
928 p_hwfn->hw_info.hw_mode);
929 if (rc)
930 break;
931 /* Fall into */
932 case FW_MSG_CODE_DRV_LOAD_PORT:
933 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
934 p_hwfn->hw_info.hw_mode);
935 if (rc)
936 break;
937
938 /* Fall into */
939 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
940 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
464f6645 941 p_tunn, p_hwfn->hw_info.hw_mode,
fe56b9e6
YM		 942 b_hw_start, int_mode,
943 allow_npar_tx_switch);
944 break;
945 default:
946 rc = -EINVAL;
947 break;
948 }
949
950 if (rc)
951 DP_NOTICE(p_hwfn,
952 "init phase failed for loadcode 0x%x (rc %d)\n",
953 load_code, rc);
954
955 /* ACK mfw regardless of success or failure of initialization */
956 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
957 DRV_MSG_CODE_LOAD_DONE,
958 0, &load_code, &param);
959 if (rc)
960 return rc;
961 if (mfw_rc) {
962 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
963 return mfw_rc;
964 }
965
39651abd
SRK		 966 /* send DCBX attention request command */
967 DP_VERBOSE(p_hwfn,
968 QED_MSG_DCB,
969 "sending phony dcbx set command to trigger DCBx attention handling\n");
970 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
971 DRV_MSG_CODE_SET_DCBX,
972 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
973 &load_code, &param);
974 if (mfw_rc) {
975 DP_NOTICE(p_hwfn,
976 "Failed to send DCBX attention request\n");
977 return mfw_rc;
978 }
979
fe56b9e6
YM		 980 p_hwfn->hw_init_done = true;
981 }
982
983 return 0;
984}
985
986#define QED_HW_STOP_RETRY_LIMIT (10)
8c925c44
YM		 987static inline void qed_hw_timers_stop(struct qed_dev *cdev,
988 struct qed_hwfn *p_hwfn,
989 struct qed_ptt *p_ptt)
990{
991 int i;
992
993 /* close timers */
994 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
995 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
996
997 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
998 if ((!qed_rd(p_hwfn, p_ptt,
999 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1000 (!qed_rd(p_hwfn, p_ptt,
1001 TM_REG_PF_SCAN_ACTIVE_TASK)))
1002 break;
1003
1004 /* Dependent on number of connection/tasks, possibly
1005 * 1ms sleep is required between polls
1006 */
1007 usleep_range(1000, 2000);
1008 }
1009
1010 if (i < QED_HW_STOP_RETRY_LIMIT)
1011 return;
1012
1013 DP_NOTICE(p_hwfn,
1014 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1015 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1016 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1017}
1018
1019void qed_hw_timers_stop_all(struct qed_dev *cdev)
1020{
1021 int j;
1022
1023 for_each_hwfn(cdev, j) {
1024 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1025 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1026
1027 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1028 }
1029}
1030
fe56b9e6
YM		 1031int qed_hw_stop(struct qed_dev *cdev)
1032{
1033 int rc = 0, t_rc;
8c925c44 1034 int j;
fe56b9e6
YM		 1035
1036 for_each_hwfn(cdev, j) {
1037 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1038 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1039
1040 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1041
1408cc1f 1042 if (IS_VF(cdev)) {
0b55e27d 1043 qed_vf_pf_int_cleanup(p_hwfn);
1408cc1f
YM		 1044 continue;
1045 }
1046
fe56b9e6
YM		 1047 /* mark the hw as uninitialized... */
1048 p_hwfn->hw_init_done = false;
1049
1050 rc = qed_sp_pf_stop(p_hwfn);
1051 if (rc)
8c925c44
YM		 1052 DP_NOTICE(p_hwfn,
1053 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
fe56b9e6
YM		 1054
1055 qed_wr(p_hwfn, p_ptt,
1056 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1057
1058 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1059 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1060 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1061 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1062 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1063
8c925c44 1064 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
fe56b9e6
YM		 1065
1066 /* Disable Attention Generation */
1067 qed_int_igu_disable_int(p_hwfn, p_ptt);
1068
1069 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1070 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1071
1072 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1073
1074 /* Need to wait 1ms to guarantee SBs are cleared */
1075 usleep_range(1000, 2000);
1076 }
1077
1408cc1f
YM		 1078 if (IS_PF(cdev)) {
1079 /* Disable DMAE in PXP - in CMT, this should only be done for
1080 * first hw-function, and only after all transactions have
1081 * stopped for all active hw-functions.
1082 */
1083 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0],
1084 cdev->hwfns[0].p_main_ptt, false);
1085 if (t_rc != 0)
1086 rc = t_rc;
1087 }
fe56b9e6
YM		 1088
1089 return rc;
1090}
1091
cee4d264
MC		 1092void qed_hw_stop_fastpath(struct qed_dev *cdev)
1093{
8c925c44 1094 int j;
cee4d264
MC		 1095
1096 for_each_hwfn(cdev, j) {
1097 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
dacd88d6
YM		 1098 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1099
1100 if (IS_VF(cdev)) {
1101 qed_vf_pf_int_cleanup(p_hwfn);
1102 continue;
1103 }
cee4d264
MC		 1104
1105 DP_VERBOSE(p_hwfn,
1106 NETIF_MSG_IFDOWN,
1107 "Shutting down the fastpath\n");
1108
1109 qed_wr(p_hwfn, p_ptt,
1110 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1111
1112 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1113 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1114 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1115 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1116 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1117
cee4d264
MC		 1118 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1119
1120 /* Need to wait 1ms to guarantee SBs are cleared */
1121 usleep_range(1000, 2000);
1122 }
1123}
1124
1125void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1126{
dacd88d6
YM		 1127 if (IS_VF(p_hwfn->cdev))
1128 return;
1129
cee4d264
MC		 1130 /* Re-open incoming traffic */
1131 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1132 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1133}
1134
fe56b9e6
YM		 1135static int qed_reg_assert(struct qed_hwfn *hwfn,
1136 struct qed_ptt *ptt, u32 reg,
1137 bool expected)
1138{
1139 u32 assert_val = qed_rd(hwfn, ptt, reg);
1140
1141 if (assert_val != expected) {
1142 DP_NOTICE(hwfn, "Value at address 0x%x != 0x%08x\n",
1143 reg, expected);
1144 return -EINVAL;
1145 }
1146
1147 return 0;
1148}
1149
1150int qed_hw_reset(struct qed_dev *cdev)
1151{
1152 int rc = 0;
1153 u32 unload_resp, unload_param;
1154 int i;
1155
1156 for_each_hwfn(cdev, i) {
1157 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1158
1408cc1f 1159 if (IS_VF(cdev)) {
0b55e27d
YM		 1160 rc = qed_vf_pf_reset(p_hwfn);
1161 if (rc)
1162 return rc;
1408cc1f
YM		 1163 continue;
1164 }
1165
fe56b9e6
YM		 1166 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n");
1167
1168 /* Check for incorrect states */
1169 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1170 QM_REG_USG_CNT_PF_TX, 0);
1171 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1172 QM_REG_USG_CNT_PF_OTHER, 0);
1173
1174 /* Disable PF in HW blocks */
1175 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1176 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1177 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1178 TCFC_REG_STRONG_ENABLE_PF, 0);
1179 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1180 CCFC_REG_STRONG_ENABLE_PF, 0);
1181
1182 /* Send unload command to MCP */
1183 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1184 DRV_MSG_CODE_UNLOAD_REQ,
1185 DRV_MB_PARAM_UNLOAD_WOL_MCP,
1186 &unload_resp, &unload_param);
1187 if (rc) {
1188 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n");
1189 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1190 }
1191
1192 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1193 DRV_MSG_CODE_UNLOAD_DONE,
1194 0, &unload_resp, &unload_param);
1195 if (rc) {
1196 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n");
1197 return rc;
1198 }
1199 }
1200
1201 return rc;
1202}
1203
1204/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1205static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1206{
1207 qed_ptt_pool_free(p_hwfn);
1208 kfree(p_hwfn->hw_info.p_igu_info);
1209}
1210
1211/* Setup bar access */
12e09c69 1212static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
fe56b9e6 1213{
fe56b9e6
YM		 1214 /* clear indirect access */
1215 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1216 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1217 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1218 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1219
1220 /* Clean Previous errors if such exist */
1221 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1222 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
1223 1 << p_hwfn->abs_pf_id);
1224
1225 /* enable internal target-read */
1226 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1227 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
fe56b9e6
YM		 1228}
1229
1230static void get_function_id(struct qed_hwfn *p_hwfn)
1231{
1232 /* ME Register */
1233 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR);
1234
1235 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1236
1237 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1238 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1239 PXP_CONCRETE_FID_PFID);
1240 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1241 PXP_CONCRETE_FID_PORT);
1242}
1243
25c089d7
YM		 1244static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1245{
1246 u32 *feat_num = p_hwfn->hw_info.feat_num;
1247 int num_features = 1;
1248
1249 feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
1250 num_features,
1251 RESC_NUM(p_hwfn, QED_L2_QUEUE));
1252 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1253 "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1254 feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB),
1255 num_features);
1256}
1257
fe56b9e6
YM		 1258static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
1259{
1260 u32 *resc_start = p_hwfn->hw_info.resc_start;
1408cc1f 1261 u8 num_funcs = p_hwfn->num_funcs_on_engine;
fe56b9e6 1262 u32 *resc_num = p_hwfn->hw_info.resc_num;
4ac801b7 1263 struct qed_sb_cnt_info sb_cnt_info;
08feecd7 1264 int i, max_vf_vlan_filters;
fe56b9e6 1265
4ac801b7 1266 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
08feecd7
YM		 1267
1268#ifdef CONFIG_QED_SRIOV
1269 max_vf_vlan_filters = QED_ETH_MAX_VF_NUM_VLAN_FILTERS;
1270#else
1271 max_vf_vlan_filters = 0;
1272#endif
1273
4ac801b7
YM		 1274 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1275
fe56b9e6
YM		 1276 resc_num[QED_SB] = min_t(u32,
1277 (MAX_SB_PER_PATH_BB / num_funcs),
4ac801b7 1278 sb_cnt_info.sb_cnt);
25c089d7 1279 resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;
fe56b9e6 1280 resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
25c089d7 1281 resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
fe56b9e6
YM		 1282 resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
1283 resc_num[QED_RL] = 8;
25c089d7
YM		 1284 resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1285 resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
1286 num_funcs;
fe56b9e6
YM		 1287 resc_num[QED_ILT] = 950;
1288
1289 for (i = 0; i < QED_MAX_RESC; i++)
1290 resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
1291
25c089d7
YM		 1292 qed_hw_set_feat(p_hwfn);
1293
fe56b9e6
YM		 1294 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1295 "The numbers for each resource are:\n"
1296 "SB = %d start = %d\n"
25c089d7 1297 "L2_QUEUE = %d start = %d\n"
fe56b9e6
YM		 1298 "VPORT = %d start = %d\n"
1299 "PQ = %d start = %d\n"
1300 "RL = %d start = %d\n"
25c089d7
YM		 1301 "MAC = %d start = %d\n"
1302 "VLAN = %d start = %d\n"
fe56b9e6
YM		 1303 "ILT = %d start = %d\n",
1304 p_hwfn->hw_info.resc_num[QED_SB],
1305 p_hwfn->hw_info.resc_start[QED_SB],
25c089d7
YM		 1306 p_hwfn->hw_info.resc_num[QED_L2_QUEUE],
1307 p_hwfn->hw_info.resc_start[QED_L2_QUEUE],
fe56b9e6
YM		 1308 p_hwfn->hw_info.resc_num[QED_VPORT],
1309 p_hwfn->hw_info.resc_start[QED_VPORT],
1310 p_hwfn->hw_info.resc_num[QED_PQ],
1311 p_hwfn->hw_info.resc_start[QED_PQ],
1312 p_hwfn->hw_info.resc_num[QED_RL],
1313 p_hwfn->hw_info.resc_start[QED_RL],
25c089d7
YM		 1314 p_hwfn->hw_info.resc_num[QED_MAC],
1315 p_hwfn->hw_info.resc_start[QED_MAC],
1316 p_hwfn->hw_info.resc_num[QED_VLAN],
1317 p_hwfn->hw_info.resc_start[QED_VLAN],
fe56b9e6
YM		 1318 p_hwfn->hw_info.resc_num[QED_ILT],
1319 p_hwfn->hw_info.resc_start[QED_ILT]);
1320}
1321
1322static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn,
1323 struct qed_ptt *p_ptt)
1324{
cc875c2e 1325 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
fc48b7a6 1326 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
cc875c2e 1327 struct qed_mcp_link_params *link;
fe56b9e6
YM		 1328
1329 /* Read global nvm_cfg address */
1330 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1331
1332 /* Verify MCP has initialized it */
1333 if (!nvm_cfg_addr) {
1334 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1335 return -EINVAL;
1336 }
1337
1338 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
1339 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1340
cc875c2e
YM		 1341 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1342 offsetof(struct nvm_cfg1, glob) +
1343 offsetof(struct nvm_cfg1_glob, core_cfg);
1344
1345 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
1346
1347 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1348 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
351a4ded 1349 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
cc875c2e
YM		 1350 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
1351 break;
351a4ded 1352 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
cc875c2e
YM		 1353 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
1354 break;
351a4ded 1355 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
cc875c2e
YM		 1356 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
1357 break;
351a4ded 1358 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
cc875c2e
YM		 1359 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
1360 break;
351a4ded 1361 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
cc875c2e
YM		 1362 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
1363 break;
351a4ded 1364 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
cc875c2e
YM		 1365 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
1366 break;
351a4ded 1367 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
cc875c2e
YM		 1368 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
1369 break;
351a4ded 1370 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
cc875c2e
YM		 1371 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
1372 break;
351a4ded 1373 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
cc875c2e
YM		 1374 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
1375 break;
1376 default:
1377 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n",
1378 core_cfg);
1379 break;
1380 }
1381
cc875c2e
YM		 1382 /* Read default link configuration */
1383 link = &p_hwfn->mcp_info->link_input;
1384 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1385 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1386 link_temp = qed_rd(p_hwfn, p_ptt,
1387 port_cfg_addr +
1388 offsetof(struct nvm_cfg1_port, speed_cap_mask));
1389 link->speed.advertised_speeds =
1390 link_temp & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1391
1392 p_hwfn->mcp_info->link_capabilities.speed_capabilities =
1393 link->speed.advertised_speeds;
1394
1395 link_temp = qed_rd(p_hwfn, p_ptt,
1396 port_cfg_addr +
1397 offsetof(struct nvm_cfg1_port, link_settings));
1398 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1399 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1400 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1401 link->speed.autoneg = true;
1402 break;
1403 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1404 link->speed.forced_speed = 1000;
1405 break;
1406 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1407 link->speed.forced_speed = 10000;
1408 break;
1409 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1410 link->speed.forced_speed = 25000;
1411 break;
1412 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1413 link->speed.forced_speed = 40000;
1414 break;
1415 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1416 link->speed.forced_speed = 50000;
1417 break;
351a4ded 1418 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
cc875c2e
YM		 1419 link->speed.forced_speed = 100000;
1420 break;
1421 default:
1422 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n",
1423 link_temp);
1424 }
1425
1426 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1427 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1428 link->pause.autoneg = !!(link_temp &
1429 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1430 link->pause.forced_rx = !!(link_temp &
1431 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1432 link->pause.forced_tx = !!(link_temp &
1433 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1434 link->loopback_mode = 0;
1435
1436 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1437 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1438 link->speed.forced_speed, link->speed.advertised_speeds,
1439 link->speed.autoneg, link->pause.autoneg);
1440
fe56b9e6
YM		 1441 /* Read Multi-function information from shmem */
1442 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1443 offsetof(struct nvm_cfg1, glob) +
1444 offsetof(struct nvm_cfg1_glob, generic_cont0);
1445
1446 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
1447
1448 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1449 NVM_CFG1_GLOB_MF_MODE_OFFSET;
1450
1451 switch (mf_mode) {
1452 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
fc48b7a6 1453 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
fe56b9e6
YM		 1454 break;
1455 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
fc48b7a6 1456 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
fe56b9e6 1457 break;
fc48b7a6
YM		 1458 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1459 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
fe56b9e6
YM		 1460 break;
1461 }
1462 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1463 p_hwfn->cdev->mf_mode);
1464
fc48b7a6
YM		 1465 /* Read Multi-function information from shmem */
1466 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1467 offsetof(struct nvm_cfg1, glob) +
1468 offsetof(struct nvm_cfg1_glob, device_capabilities);
1469
1470 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
1471 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1472 __set_bit(QED_DEV_CAP_ETH,
1473 &p_hwfn->hw_info.device_capabilities);
1474
fe56b9e6
YM		 1475 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1476}
1477
1408cc1f
YM		 1478static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1479{
1480 u32 reg_function_hide, tmp, eng_mask;
1481 u8 num_funcs;
1482
1483 num_funcs = MAX_NUM_PFS_BB;
1484
1485 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1486 * in the other bits are selected.
1487 * Bits 1-15 are for functions 1-15, respectively, and their value is
1488 * '0' only for enabled functions (function 0 always exists and
1489 * enabled).
1490 * In case of CMT, only the "even" functions are enabled, and thus the
1491 * number of functions for both hwfns is learnt from the same bits.
1492 */
1493 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
1494
1495 if (reg_function_hide & 0x1) {
1496 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) {
1497 num_funcs = 0;
1498 eng_mask = 0xaaaa;
1499 } else {
1500 num_funcs = 1;
1501 eng_mask = 0x5554;
1502 }
1503
1504 /* Get the number of the enabled functions on the engine */
1505 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
1506 while (tmp) {
1507 if (tmp & 0x1)
1508 num_funcs++;
1509 tmp >>= 0x1;
1510 }
1511 }
1512
1513 p_hwfn->num_funcs_on_engine = num_funcs;
1514
1515 DP_VERBOSE(p_hwfn,
1516 NETIF_MSG_PROBE,
1517 "PF [rel_id %d, abs_id %d] within the %d enabled functions on the engine\n",
1518 p_hwfn->rel_pf_id,
1519 p_hwfn->abs_pf_id,
1520 p_hwfn->num_funcs_on_engine);
1521}
1522
fe56b9e6
YM		 1523static int
1524qed_get_hw_info(struct qed_hwfn *p_hwfn,
1525 struct qed_ptt *p_ptt,
1526 enum qed_pci_personality personality)
1527{
1528 u32 port_mode;
1529 int rc;
1530
32a47e72
YM		 1531 /* Since all information is common, only first hwfns should do this */
1532 if (IS_LEAD_HWFN(p_hwfn)) {
1533 rc = qed_iov_hw_info(p_hwfn);
1534 if (rc)
1535 return rc;
1536 }
1537
fe56b9e6
YM		 1538 /* Read the port mode */
1539 port_mode = qed_rd(p_hwfn, p_ptt,
1540 CNIG_REG_NW_PORT_MODE_BB_B0);
1541
1542 if (port_mode < 3) {
1543 p_hwfn->cdev->num_ports_in_engines = 1;
1544 } else if (port_mode <= 5) {
1545 p_hwfn->cdev->num_ports_in_engines = 2;
1546 } else {
1547 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
1548 p_hwfn->cdev->num_ports_in_engines);
1549
1550 /* Default num_ports_in_engines to something */
1551 p_hwfn->cdev->num_ports_in_engines = 1;
1552 }
1553
1554 qed_hw_get_nvm_info(p_hwfn, p_ptt);
1555
1556 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
1557 if (rc)
1558 return rc;
1559
1560 if (qed_mcp_is_init(p_hwfn))
1561 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
1562 p_hwfn->mcp_info->func_info.mac);
1563 else
1564 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
1565
1566 if (qed_mcp_is_init(p_hwfn)) {
1567 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
1568 p_hwfn->hw_info.ovlan =
1569 p_hwfn->mcp_info->func_info.ovlan;
1570
1571 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
1572 }
1573
1574 if (qed_mcp_is_init(p_hwfn)) {
1575 enum qed_pci_personality protocol;
1576
1577 protocol = p_hwfn->mcp_info->func_info.protocol;
1578 p_hwfn->hw_info.personality = protocol;
1579 }
1580
1408cc1f
YM		 1581 qed_get_num_funcs(p_hwfn, p_ptt);
1582
fe56b9e6
YM		 1583 qed_hw_get_resc(p_hwfn);
1584
1585 return rc;
1586}
1587
12e09c69 1588static int qed_get_dev_info(struct qed_dev *cdev)
fe56b9e6 1589{
fc48b7a6 1590 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
fe56b9e6
YM		 1591 u32 tmp;
1592
fc48b7a6
YM		 1593 /* Read Vendor Id / Device Id */
1594 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID,
1595 &cdev->vendor_id);
1596 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID,
1597 &cdev->device_id);
1598 cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6 1599 MISCS_REG_CHIP_NUM);
fc48b7a6 1600 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 1601 MISCS_REG_CHIP_REV);
1602 MASK_FIELD(CHIP_REV, cdev->chip_rev);
1603
fc48b7a6 1604 cdev->type = QED_DEV_TYPE_BB;
fe56b9e6 1605 /* Learn number of HW-functions */
fc48b7a6 1606 tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 1607 MISCS_REG_CMT_ENABLED_FOR_PAIR);
1608
fc48b7a6 1609 if (tmp & (1 << p_hwfn->rel_pf_id)) {
fe56b9e6
YM		 1610 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
1611 cdev->num_hwfns = 2;
1612 } else {
1613 cdev->num_hwfns = 1;
1614 }
1615
fc48b7a6 1616 cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 1617 MISCS_REG_CHIP_TEST_REG) >> 4;
1618 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
fc48b7a6 1619 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 1620 MISCS_REG_CHIP_METAL);
1621 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
1622
1623 DP_INFO(cdev->hwfns,
1624 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
1625 cdev->chip_num, cdev->chip_rev,
1626 cdev->chip_bond_id, cdev->chip_metal);
12e09c69
YM		 1627
1628 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
1629 DP_NOTICE(cdev->hwfns,
1630 "The chip type/rev (BB A0) is not supported!\n");
1631 return -EINVAL;
1632 }
1633
1634 return 0;
fe56b9e6
YM		 1635}
1636
1637static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
1638 void __iomem *p_regview,
1639 void __iomem *p_doorbells,
1640 enum qed_pci_personality personality)
1641{
1642 int rc = 0;
1643
1644 /* Split PCI bars evenly between hwfns */
1645 p_hwfn->regview = p_regview;
1646 p_hwfn->doorbells = p_doorbells;
1647
1408cc1f
YM		 1648 if (IS_VF(p_hwfn->cdev))
1649 return qed_vf_hw_prepare(p_hwfn);
1650
fe56b9e6
YM		 1651 /* Validate that chip access is feasible */
1652 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
1653 DP_ERR(p_hwfn,
1654 "Reading the ME register returns all Fs; Preventing further chip access\n");
1655 return -EINVAL;
1656 }
1657
1658 get_function_id(p_hwfn);
1659
12e09c69
YM		 1660 /* Allocate PTT pool */
1661 rc = qed_ptt_pool_alloc(p_hwfn);
fe56b9e6
YM		 1662 if (rc) {
1663 DP_NOTICE(p_hwfn, "Failed to prepare hwfn's hw\n");
1664 goto err0;
1665 }
1666
12e09c69
YM		 1667 /* Allocate the main PTT */
1668 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
1669
fe56b9e6 1670 /* First hwfn learns basic information, e.g., number of hwfns */
12e09c69
YM		 1671 if (!p_hwfn->my_id) {
1672 rc = qed_get_dev_info(p_hwfn->cdev);
1673 if (rc != 0)
1674 goto err1;
1675 }
1676
1677 qed_hw_hwfn_prepare(p_hwfn);
fe56b9e6
YM		 1678
1679 /* Initialize MCP structure */
1680 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
1681 if (rc) {
1682 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
1683 goto err1;
1684 }
1685
1686 /* Read the device configuration information from the HW and SHMEM */
1687 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
1688 if (rc) {
1689 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
1690 goto err2;
1691 }
1692
1693 /* Allocate the init RT array and initialize the init-ops engine */
1694 rc = qed_init_alloc(p_hwfn);
1695 if (rc) {
1696 DP_NOTICE(p_hwfn, "Failed to allocate the init array\n");
1697 goto err2;
1698 }
1699
1700 return rc;
1701err2:
32a47e72
YM		 1702 if (IS_LEAD_HWFN(p_hwfn))
1703 qed_iov_free_hw_info(p_hwfn->cdev);
fe56b9e6
YM		 1704 qed_mcp_free(p_hwfn);
1705err1:
1706 qed_hw_hwfn_free(p_hwfn);
1707err0:
1708 return rc;
1709}
1710
fe56b9e6
YM		 1711int qed_hw_prepare(struct qed_dev *cdev,
1712 int personality)
1713{
c78df14e
AE		 1714 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1715 int rc;
fe56b9e6
YM		 1716
1717 /* Store the precompiled init data ptrs */
1408cc1f
YM		 1718 if (IS_PF(cdev))
1719 qed_init_iro_array(cdev);
fe56b9e6
YM		 1720
1721 /* Initialize the first hwfn - will learn number of hwfns */
c78df14e
AE		 1722 rc = qed_hw_prepare_single(p_hwfn,
1723 cdev->regview,
fe56b9e6
YM		 1724 cdev->doorbells, personality);
1725 if (rc)
1726 return rc;
1727
c78df14e 1728 personality = p_hwfn->hw_info.personality;
fe56b9e6
YM		 1729
1730 /* Initialize the rest of the hwfns */
c78df14e 1731 if (cdev->num_hwfns > 1) {
fe56b9e6 1732 void __iomem *p_regview, *p_doorbell;
c78df14e
AE		 1733 u8 __iomem *addr;
1734
1735 /* adjust bar offset for second engine */
c2035eea 1736 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
c78df14e 1737 p_regview = addr;
fe56b9e6 1738
c78df14e 1739 /* adjust doorbell bar offset for second engine */
c2035eea 1740 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
c78df14e
AE		 1741 p_doorbell = addr;
1742
1743 /* prepare second hw function */
1744 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
fe56b9e6 1745 p_doorbell, personality);
c78df14e
AE		 1746
1747 /* in case of error, need to free the previously
1748 * initiliazed hwfn 0.
1749 */
fe56b9e6 1750 if (rc) {
1408cc1f
YM		 1751 if (IS_PF(cdev)) {
1752 qed_init_free(p_hwfn);
1753 qed_mcp_free(p_hwfn);
1754 qed_hw_hwfn_free(p_hwfn);
1755 }
fe56b9e6
YM		 1756 }
1757 }
1758
c78df14e 1759 return rc;
fe56b9e6
YM		 1760}
1761
1762void qed_hw_remove(struct qed_dev *cdev)
1763{
1764 int i;
1765
1766 for_each_hwfn(cdev, i) {
1767 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1768
1408cc1f 1769 if (IS_VF(cdev)) {
0b55e27d 1770 qed_vf_pf_release(p_hwfn);
1408cc1f
YM		 1771 continue;
1772 }
1773
fe56b9e6
YM		 1774 qed_init_free(p_hwfn);
1775 qed_hw_hwfn_free(p_hwfn);
1776 qed_mcp_free(p_hwfn);
1777 }
32a47e72
YM		 1778
1779 qed_iov_free_hw_info(cdev);
fe56b9e6
YM		 1780}
1781
1782int qed_chain_alloc(struct qed_dev *cdev,
1783 enum qed_chain_use_mode intended_use,
1784 enum qed_chain_mode mode,
1785 u16 num_elems,
1786 size_t elem_size,
1787 struct qed_chain *p_chain)
1788{
1789 dma_addr_t p_pbl_phys = 0;
1790 void *p_pbl_virt = NULL;
1791 dma_addr_t p_phys = 0;
1792 void *p_virt = NULL;
1793 u16 page_cnt = 0;
1794 size_t size;
1795
1796 if (mode == QED_CHAIN_MODE_SINGLE)
1797 page_cnt = 1;
1798 else
1799 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
1800
1801 size = page_cnt * QED_CHAIN_PAGE_SIZE;
1802 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
1803 size, &p_phys, GFP_KERNEL);
1804 if (!p_virt) {
1805 DP_NOTICE(cdev, "Failed to allocate chain mem\n");
1806 goto nomem;
1807 }
1808
1809 if (mode == QED_CHAIN_MODE_PBL) {
1810 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
1811 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
1812 size, &p_pbl_phys,
1813 GFP_KERNEL);
1814 if (!p_pbl_virt) {
1815 DP_NOTICE(cdev, "Failed to allocate chain pbl mem\n");
1816 goto nomem;
1817 }
1818
1819 qed_chain_pbl_init(p_chain, p_virt, p_phys, page_cnt,
1820 (u8)elem_size, intended_use,
1821 p_pbl_phys, p_pbl_virt);
1822 } else {
1823 qed_chain_init(p_chain, p_virt, p_phys, page_cnt,
1824 (u8)elem_size, intended_use, mode);
1825 }
1826
1827 return 0;
1828
1829nomem:
1830 dma_free_coherent(&cdev->pdev->dev,
1831 page_cnt * QED_CHAIN_PAGE_SIZE,
1832 p_virt, p_phys);
1833 dma_free_coherent(&cdev->pdev->dev,
1834 page_cnt * QED_CHAIN_PBL_ENTRY_SIZE,
1835 p_pbl_virt, p_pbl_phys);
1836
1837 return -ENOMEM;
1838}
1839
1840void qed_chain_free(struct qed_dev *cdev,
1841 struct qed_chain *p_chain)
1842{
1843 size_t size;
1844
1845 if (!p_chain->p_virt_addr)
1846 return;
1847
1848 if (p_chain->mode == QED_CHAIN_MODE_PBL) {
1849 size = p_chain->page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
1850 dma_free_coherent(&cdev->pdev->dev, size,
1851 p_chain->pbl.p_virt_table,
1852 p_chain->pbl.p_phys_table);
1853 }
1854
1855 size = p_chain->page_cnt * QED_CHAIN_PAGE_SIZE;
1856 dma_free_coherent(&cdev->pdev->dev, size,
1857 p_chain->p_virt_addr,
1858 p_chain->p_phys_addr);
1859}
cee4d264
MC		 1860
1861int qed_fw_l2_queue(struct qed_hwfn *p_hwfn,
1862 u16 src_id, u16 *dst_id)
1863{
1864 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
1865 u16 min, max;
1866
1867 min = (u16)RESC_START(p_hwfn, QED_L2_QUEUE);
1868 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
1869 DP_NOTICE(p_hwfn,
1870 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
1871 src_id, min, max);
1872
1873 return -EINVAL;
1874 }
1875
1876 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
1877
1878 return 0;
1879}
1880
1881int qed_fw_vport(struct qed_hwfn *p_hwfn,
1882 u8 src_id, u8 *dst_id)
1883{
1884 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
1885 u8 min, max;
1886
1887 min = (u8)RESC_START(p_hwfn, QED_VPORT);
1888 max = min + RESC_NUM(p_hwfn, QED_VPORT);
1889 DP_NOTICE(p_hwfn,
1890 "vport id [%d] is not valid, available indices [%d - %d]\n",
1891 src_id, min, max);
1892
1893 return -EINVAL;
1894 }
1895
1896 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
1897
1898 return 0;
1899}
1900
1901int qed_fw_rss_eng(struct qed_hwfn *p_hwfn,
1902 u8 src_id, u8 *dst_id)
1903{
1904 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
1905 u8 min, max;
1906
1907 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
1908 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
1909 DP_NOTICE(p_hwfn,
1910 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
1911 src_id, min, max);
1912
1913 return -EINVAL;
1914 }
1915
1916 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
1917
1918 return 0;
1919}
bcd197c8
MC		 1920
1921/* Calculate final WFQ values for all vports and configure them.
1922 * After this configuration each vport will have
1923 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
1924 */
1925static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
1926 struct qed_ptt *p_ptt,
1927 u32 min_pf_rate)
1928{
1929 struct init_qm_vport_params *vport_params;
1930 int i;
1931
1932 vport_params = p_hwfn->qm_info.qm_vport_params;
1933
1934 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
1935 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
1936
1937 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
1938 min_pf_rate;
1939 qed_init_vport_wfq(p_hwfn, p_ptt,
1940 vport_params[i].first_tx_pq_id,
1941 vport_params[i].vport_wfq);
1942 }
1943}
1944
1945static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
1946 u32 min_pf_rate)
1947
1948{
1949 int i;
1950
1951 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
1952 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
1953}
1954
1955static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
1956 struct qed_ptt *p_ptt,
1957 u32 min_pf_rate)
1958{
1959 struct init_qm_vport_params *vport_params;
1960 int i;
1961
1962 vport_params = p_hwfn->qm_info.qm_vport_params;
1963
1964 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
1965 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
1966 qed_init_vport_wfq(p_hwfn, p_ptt,
1967 vport_params[i].first_tx_pq_id,
1968 vport_params[i].vport_wfq);
1969 }
1970}
1971
1972/* This function performs several validations for WFQ
1973 * configuration and required min rate for a given vport
1974 * 1. req_rate must be greater than one percent of min_pf_rate.
1975 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
1976 * rates to get less than one percent of min_pf_rate.
1977 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
1978 */
1979static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
1980 u16 vport_id, u32 req_rate,
1981 u32 min_pf_rate)
1982{
1983 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
1984 int non_requested_count = 0, req_count = 0, i, num_vports;
1985
1986 num_vports = p_hwfn->qm_info.num_vports;
1987
1988 /* Accounting for the vports which are configured for WFQ explicitly */
1989 for (i = 0; i < num_vports; i++) {
1990 u32 tmp_speed;
1991
1992 if ((i != vport_id) &&
1993 p_hwfn->qm_info.wfq_data[i].configured) {
1994 req_count++;
1995 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
1996 total_req_min_rate += tmp_speed;
1997 }
1998 }
1999
2000 /* Include current vport data as well */
2001 req_count++;
2002 total_req_min_rate += req_rate;
2003 non_requested_count = num_vports - req_count;
2004
2005 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
2006 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2007 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2008 vport_id, req_rate, min_pf_rate);
2009 return -EINVAL;
2010 }
2011
2012 if (num_vports > QED_WFQ_UNIT) {
2013 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2014 "Number of vports is greater than %d\n",
2015 QED_WFQ_UNIT);
2016 return -EINVAL;
2017 }
2018
2019 if (total_req_min_rate > min_pf_rate) {
2020 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2021 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
2022 total_req_min_rate, min_pf_rate);
2023 return -EINVAL;
2024 }
2025
2026 total_left_rate = min_pf_rate - total_req_min_rate;
2027
2028 left_rate_per_vp = total_left_rate / non_requested_count;
2029 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
2030 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2031 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2032 left_rate_per_vp, min_pf_rate);
2033 return -EINVAL;
2034 }
2035
2036 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
2037 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
2038
2039 for (i = 0; i < num_vports; i++) {
2040 if (p_hwfn->qm_info.wfq_data[i].configured)
2041 continue;
2042
2043 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
2044 }
2045
2046 return 0;
2047}
2048
733def6a
YM		 2049static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
2050 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
2051{
2052 struct qed_mcp_link_state *p_link;
2053 int rc = 0;
2054
2055 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
2056
2057 if (!p_link->min_pf_rate) {
2058 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
2059 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
2060 return rc;
2061 }
2062
2063 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
2064
2065 if (rc == 0)
2066 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
2067 p_link->min_pf_rate);
2068 else
2069 DP_NOTICE(p_hwfn,
2070 "Validation failed while configuring min rate\n");
2071
2072 return rc;
2073}
2074
bcd197c8
MC		 2075static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
2076 struct qed_ptt *p_ptt,
2077 u32 min_pf_rate)
2078{
2079 bool use_wfq = false;
2080 int rc = 0;
2081 u16 i;
2082
2083 /* Validate all pre configured vports for wfq */
2084 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2085 u32 rate;
2086
2087 if (!p_hwfn->qm_info.wfq_data[i].configured)
2088 continue;
2089
2090 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
2091 use_wfq = true;
2092
2093 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
2094 if (rc) {
2095 DP_NOTICE(p_hwfn,
2096 "WFQ validation failed while configuring min rate\n");
2097 break;
2098 }
2099 }
2100
2101 if (!rc && use_wfq)
2102 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2103 else
2104 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2105
2106 return rc;
2107}
2108
733def6a
YM		 2109/* Main API for qed clients to configure vport min rate.
2110 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
2111 * rate - Speed in Mbps needs to be assigned to a given vport.
2112 */
2113int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
2114{
2115 int i, rc = -EINVAL;
2116
2117 /* Currently not supported; Might change in future */
2118 if (cdev->num_hwfns > 1) {
2119 DP_NOTICE(cdev,
2120 "WFQ configuration is not supported for this device\n");
2121 return rc;
2122 }
2123
2124 for_each_hwfn(cdev, i) {
2125 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2126 struct qed_ptt *p_ptt;
2127
2128 p_ptt = qed_ptt_acquire(p_hwfn);
2129 if (!p_ptt)
2130 return -EBUSY;
2131
2132 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
2133
2134 if (!rc) {
2135 qed_ptt_release(p_hwfn, p_ptt);
2136 return rc;
2137 }
2138
2139 qed_ptt_release(p_hwfn, p_ptt);
2140 }
2141
2142 return rc;
2143}
2144
bcd197c8
MC		 2145/* API to configure WFQ from mcp link change */
2146void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate)
2147{
2148 int i;
2149
3e7cfce2
YM		 2150 if (cdev->num_hwfns > 1) {
2151 DP_VERBOSE(cdev,
2152 NETIF_MSG_LINK,
2153 "WFQ configuration is not supported for this device\n");
2154 return;
2155 }
2156
bcd197c8
MC		 2157 for_each_hwfn(cdev, i) {
2158 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2159
2160 __qed_configure_vp_wfq_on_link_change(p_hwfn,
2161 p_hwfn->p_dpc_ptt,
2162 min_pf_rate);
2163 }
2164}
4b01e519
MC		 2165
2166int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
2167 struct qed_ptt *p_ptt,
2168 struct qed_mcp_link_state *p_link,
2169 u8 max_bw)
2170{
2171 int rc = 0;
2172
2173 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
2174
2175 if (!p_link->line_speed && (max_bw != 100))
2176 return rc;
2177
2178 p_link->speed = (p_link->line_speed * max_bw) / 100;
2179 p_hwfn->qm_info.pf_rl = p_link->speed;
2180
2181 /* Since the limiter also affects Tx-switched traffic, we don't want it
2182 * to limit such traffic in case there's no actual limit.
2183 * In that case, set limit to imaginary high boundary.
2184 */
2185 if (max_bw == 100)
2186 p_hwfn->qm_info.pf_rl = 100000;
2187
2188 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
2189 p_hwfn->qm_info.pf_rl);
2190
2191 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2192 "Configured MAX bandwidth to be %08x Mb/sec\n",
2193 p_link->speed);
2194
2195 return rc;
2196}
2197
2198/* Main API to configure PF max bandwidth where bw range is [1 - 100] */
2199int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
2200{
2201 int i, rc = -EINVAL;
2202
2203 if (max_bw < 1 || max_bw > 100) {
2204 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
2205 return rc;
2206 }
2207
2208 for_each_hwfn(cdev, i) {
2209 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2210 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2211 struct qed_mcp_link_state *p_link;
2212 struct qed_ptt *p_ptt;
2213
2214 p_link = &p_lead->mcp_info->link_output;
2215
2216 p_ptt = qed_ptt_acquire(p_hwfn);
2217 if (!p_ptt)
2218 return -EBUSY;
2219
2220 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
2221 p_link, max_bw);
2222
2223 qed_ptt_release(p_hwfn, p_ptt);
2224
2225 if (rc)
2226 break;
2227 }
2228
2229 return rc;
2230}
a64b02d5
MC		 2231
2232int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
2233 struct qed_ptt *p_ptt,
2234 struct qed_mcp_link_state *p_link,
2235 u8 min_bw)
2236{
2237 int rc = 0;
2238
2239 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
2240 p_hwfn->qm_info.pf_wfq = min_bw;
2241
2242 if (!p_link->line_speed)
2243 return rc;
2244
2245 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
2246
2247 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
2248
2249 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2250 "Configured MIN bandwidth to be %d Mb/sec\n",
2251 p_link->min_pf_rate);
2252
2253 return rc;
2254}
2255
2256/* Main API to configure PF min bandwidth where bw range is [1-100] */
2257int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
2258{
2259 int i, rc = -EINVAL;
2260
2261 if (min_bw < 1 || min_bw > 100) {
2262 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
2263 return rc;
2264 }
2265
2266 for_each_hwfn(cdev, i) {
2267 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2268 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2269 struct qed_mcp_link_state *p_link;
2270 struct qed_ptt *p_ptt;
2271
2272 p_link = &p_lead->mcp_info->link_output;
2273
2274 p_ptt = qed_ptt_acquire(p_hwfn);
2275 if (!p_ptt)
2276 return -EBUSY;
2277
2278 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
2279 p_link, min_bw);
2280 if (rc) {
2281 qed_ptt_release(p_hwfn, p_ptt);
2282 return rc;
2283 }
2284
2285 if (p_link->min_pf_rate) {
2286 u32 min_rate = p_link->min_pf_rate;
2287
2288 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
2289 p_ptt,
2290 min_rate);
2291 }
2292
2293 qed_ptt_release(p_hwfn, p_ptt);
2294 }
2295
2296 return rc;
2297}
733def6a
YM		 2298
2299void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2300{
2301 struct qed_mcp_link_state *p_link;
2302
2303 p_link = &p_hwfn->mcp_info->link_output;
2304
2305 if (p_link->min_pf_rate)
2306 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
2307 p_link->min_pf_rate);
2308
2309 memset(p_hwfn->qm_info.wfq_data, 0,
2310 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
2311}
Linux kernel - Deliverables
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