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Merge branch 'cpsw-refactor'
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qed / qed_main.c
CommitLineData
fe56b9e6
YM		 1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#include <linux/stddef.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/version.h>
14#include <linux/delay.h>
15#include <asm/byteorder.h>
16#include <linux/dma-mapping.h>
17#include <linux/string.h>
18#include <linux/module.h>
19#include <linux/interrupt.h>
20#include <linux/workqueue.h>
21#include <linux/ethtool.h>
22#include <linux/etherdevice.h>
23#include <linux/vmalloc.h>
24#include <linux/qed/qed_if.h>
25
26#include "qed.h"
37bff2b9 27#include "qed_sriov.h"
fe56b9e6
YM		 28#include "qed_sp.h"
29#include "qed_dev_api.h"
30#include "qed_mcp.h"
31#include "qed_hw.h"
03dc76ca 32#include "qed_selftest.h"
fe56b9e6 33
5abd7e92
YM		 34static char version[] =
35 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
fe56b9e6 36
5abd7e92 37MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module");
fe56b9e6
YM		 38MODULE_LICENSE("GPL");
39MODULE_VERSION(DRV_MODULE_VERSION);
40
41#define FW_FILE_VERSION \
42 __stringify(FW_MAJOR_VERSION) "." \
43 __stringify(FW_MINOR_VERSION) "." \
44 __stringify(FW_REVISION_VERSION) "." \
45 __stringify(FW_ENGINEERING_VERSION)
46
47#define QED_FW_FILE_NAME \
48 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
49
d43d3f0f
YM		 50MODULE_FIRMWARE(QED_FW_FILE_NAME);
51
fe56b9e6
YM		 52static int __init qed_init(void)
53{
54 pr_notice("qed_init called\n");
55
56 pr_info("%s", version);
57
58 return 0;
59}
60
61static void __exit qed_cleanup(void)
62{
63 pr_notice("qed_cleanup called\n");
64}
65
66module_init(qed_init);
67module_exit(qed_cleanup);
68
69/* Check if the DMA controller on the machine can properly handle the DMA
70 * addressing required by the device.
71*/
72static int qed_set_coherency_mask(struct qed_dev *cdev)
73{
74 struct device *dev = &cdev->pdev->dev;
75
76 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
77 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
78 DP_NOTICE(cdev,
79 "Can't request 64-bit consistent allocations\n");
80 return -EIO;
81 }
82 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
83 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
84 return -EIO;
85 }
86
87 return 0;
88}
89
90static void qed_free_pci(struct qed_dev *cdev)
91{
92 struct pci_dev *pdev = cdev->pdev;
93
94 if (cdev->doorbells)
95 iounmap(cdev->doorbells);
96 if (cdev->regview)
97 iounmap(cdev->regview);
98 if (atomic_read(&pdev->enable_cnt) == 1)
99 pci_release_regions(pdev);
100
101 pci_disable_device(pdev);
102}
103
0dfaba6d
YM		 104#define PCI_REVISION_ID_ERROR_VAL 0xff
105
fe56b9e6
YM		 106/* Performs PCI initializations as well as initializing PCI-related parameters
107 * in the device structrue. Returns 0 in case of success.
108 */
109static int qed_init_pci(struct qed_dev *cdev,
110 struct pci_dev *pdev)
111{
0dfaba6d 112 u8 rev_id;
fe56b9e6
YM		 113 int rc;
114
115 cdev->pdev = pdev;
116
117 rc = pci_enable_device(pdev);
118 if (rc) {
119 DP_NOTICE(cdev, "Cannot enable PCI device\n");
120 goto err0;
121 }
122
123 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
124 DP_NOTICE(cdev, "No memory region found in bar #0\n");
125 rc = -EIO;
126 goto err1;
127 }
128
1408cc1f 129 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
fe56b9e6
YM		 130 DP_NOTICE(cdev, "No memory region found in bar #2\n");
131 rc = -EIO;
132 goto err1;
133 }
134
135 if (atomic_read(&pdev->enable_cnt) == 1) {
136 rc = pci_request_regions(pdev, "qed");
137 if (rc) {
138 DP_NOTICE(cdev,
139 "Failed to request PCI memory resources\n");
140 goto err1;
141 }
142 pci_set_master(pdev);
143 pci_save_state(pdev);
144 }
145
0dfaba6d
YM		 146 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
147 if (rev_id == PCI_REVISION_ID_ERROR_VAL) {
148 DP_NOTICE(cdev,
149 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n",
150 rev_id);
151 rc = -ENODEV;
152 goto err2;
153 }
fe56b9e6
YM		 154 if (!pci_is_pcie(pdev)) {
155 DP_NOTICE(cdev, "The bus is not PCI Express\n");
156 rc = -EIO;
157 goto err2;
158 }
159
160 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
416cdf06 161 if (IS_PF(cdev) && !cdev->pci_params.pm_cap)
fe56b9e6
YM		 162 DP_NOTICE(cdev, "Cannot find power management capability\n");
163
164 rc = qed_set_coherency_mask(cdev);
165 if (rc)
166 goto err2;
167
168 cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
169 cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
170 cdev->pci_params.irq = pdev->irq;
171
172 cdev->regview = pci_ioremap_bar(pdev, 0);
173 if (!cdev->regview) {
174 DP_NOTICE(cdev, "Cannot map register space, aborting\n");
175 rc = -ENOMEM;
176 goto err2;
177 }
178
1408cc1f 179 if (IS_PF(cdev)) {
f82731b4 180 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
1408cc1f
YM		 181 cdev->db_size = pci_resource_len(cdev->pdev, 2);
182 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
183 if (!cdev->doorbells) {
184 DP_NOTICE(cdev, "Cannot map doorbell space\n");
185 return -ENOMEM;
186 }
fe56b9e6
YM		 187 }
188
189 return 0;
190
191err2:
192 pci_release_regions(pdev);
193err1:
194 pci_disable_device(pdev);
195err0:
196 return rc;
197}
198
199int qed_fill_dev_info(struct qed_dev *cdev,
200 struct qed_dev_info *dev_info)
201{
cee4d264
MC		 202 struct qed_ptt *ptt;
203
fe56b9e6
YM		 204 memset(dev_info, 0, sizeof(struct qed_dev_info));
205
206 dev_info->num_hwfns = cdev->num_hwfns;
207 dev_info->pci_mem_start = cdev->pci_params.mem_start;
208 dev_info->pci_mem_end = cdev->pci_params.mem_end;
209 dev_info->pci_irq = cdev->pci_params.irq;
c5ac9319
YM		 210 dev_info->rdma_supported =
211 (cdev->hwfns[0].hw_info.personality == QED_PCI_ETH_ROCE);
fc48b7a6 212 dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]);
fe56b9e6
YM		 213 ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr);
214
1408cc1f
YM		 215 if (IS_PF(cdev)) {
216 dev_info->fw_major = FW_MAJOR_VERSION;
217 dev_info->fw_minor = FW_MINOR_VERSION;
218 dev_info->fw_rev = FW_REVISION_VERSION;
219 dev_info->fw_eng = FW_ENGINEERING_VERSION;
220 dev_info->mf_mode = cdev->mf_mode;
831bfb0e 221 dev_info->tx_switching = true;
1408cc1f
YM		 222 } else {
223 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major,
224 &dev_info->fw_minor, &dev_info->fw_rev,
225 &dev_info->fw_eng);
226 }
fe56b9e6 227
1408cc1f
YM		 228 if (IS_PF(cdev)) {
229 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
230 if (ptt) {
231 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt,
232 &dev_info->mfw_rev, NULL);
fe56b9e6 233
1408cc1f
YM		 234 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
235 &dev_info->flash_size);
cee4d264 236
1408cc1f
YM		 237 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
238 }
239 } else {
240 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL,
241 &dev_info->mfw_rev, NULL);
cee4d264
MC		 242 }
243
fe56b9e6
YM		 244 return 0;
245}
246
247static void qed_free_cdev(struct qed_dev *cdev)
248{
249 kfree((void *)cdev);
250}
251
252static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
253{
254 struct qed_dev *cdev;
255
256 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
257 if (!cdev)
258 return cdev;
259
260 qed_init_struct(cdev);
261
262 return cdev;
263}
264
265/* Sets the requested power state */
266static int qed_set_power_state(struct qed_dev *cdev,
267 pci_power_t state)
268{
269 if (!cdev)
270 return -ENODEV;
271
272 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
273 return 0;
274}
275
276/* probing */
277static struct qed_dev *qed_probe(struct pci_dev *pdev,
1408cc1f 278 struct qed_probe_params *params)
fe56b9e6
YM		 279{
280 struct qed_dev *cdev;
281 int rc;
282
283 cdev = qed_alloc_cdev(pdev);
284 if (!cdev)
285 goto err0;
286
1408cc1f 287 cdev->protocol = params->protocol;
fe56b9e6 288
1408cc1f
YM		 289 if (params->is_vf)
290 cdev->b_is_vf = true;
291
292 qed_init_dp(cdev, params->dp_module, params->dp_level);
fe56b9e6
YM		 293
294 rc = qed_init_pci(cdev, pdev);
295 if (rc) {
296 DP_ERR(cdev, "init pci failed\n");
297 goto err1;
298 }
299 DP_INFO(cdev, "PCI init completed successfully\n");
300
301 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
302 if (rc) {
303 DP_ERR(cdev, "hw prepare failed\n");
304 goto err2;
305 }
306
307 DP_INFO(cdev, "qed_probe completed successffuly\n");
308
309 return cdev;
310
311err2:
312 qed_free_pci(cdev);
313err1:
314 qed_free_cdev(cdev);
315err0:
316 return NULL;
317}
318
319static void qed_remove(struct qed_dev *cdev)
320{
321 if (!cdev)
322 return;
323
324 qed_hw_remove(cdev);
325
326 qed_free_pci(cdev);
327
328 qed_set_power_state(cdev, PCI_D3hot);
329
330 qed_free_cdev(cdev);
331}
332
333static void qed_disable_msix(struct qed_dev *cdev)
334{
335 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
336 pci_disable_msix(cdev->pdev);
337 kfree(cdev->int_params.msix_table);
338 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
339 pci_disable_msi(cdev->pdev);
340 }
341
342 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
343}
344
345static int qed_enable_msix(struct qed_dev *cdev,
346 struct qed_int_params *int_params)
347{
348 int i, rc, cnt;
349
350 cnt = int_params->in.num_vectors;
351
352 for (i = 0; i < cnt; i++)
353 int_params->msix_table[i].entry = i;
354
355 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
356 int_params->in.min_msix_cnt, cnt);
357 if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
358 (rc % cdev->num_hwfns)) {
359 pci_disable_msix(cdev->pdev);
360
361 /* If fastpath is initialized, we need at least one interrupt
362 * per hwfn [and the slow path interrupts]. New requested number
363 * should be a multiple of the number of hwfns.
364 */
365 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
366 DP_NOTICE(cdev,
367 "Trying to enable MSI-X with less vectors (%d out of %d)\n",
368 cnt, int_params->in.num_vectors);
369 rc = pci_enable_msix_exact(cdev->pdev,
370 int_params->msix_table, cnt);
371 if (!rc)
372 rc = cnt;
373 }
374
375 if (rc > 0) {
376 /* MSI-x configuration was achieved */
377 int_params->out.int_mode = QED_INT_MODE_MSIX;
378 int_params->out.num_vectors = rc;
379 rc = 0;
380 } else {
381 DP_NOTICE(cdev,
382 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
383 cnt, rc);
384 }
385
386 return rc;
387}
388
389/* This function outputs the int mode and the number of enabled msix vector */
390static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
391{
392 struct qed_int_params *int_params = &cdev->int_params;
393 struct msix_entry *tbl;
394 int rc = 0, cnt;
395
396 switch (int_params->in.int_mode) {
397 case QED_INT_MODE_MSIX:
398 /* Allocate MSIX table */
399 cnt = int_params->in.num_vectors;
400 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
401 if (!int_params->msix_table) {
402 rc = -ENOMEM;
403 goto out;
404 }
405
406 /* Enable MSIX */
407 rc = qed_enable_msix(cdev, int_params);
408 if (!rc)
409 goto out;
410
411 DP_NOTICE(cdev, "Failed to enable MSI-X\n");
412 kfree(int_params->msix_table);
413 if (force_mode)
414 goto out;
415 /* Fallthrough */
416
417 case QED_INT_MODE_MSI:
bb13ace7
SRK		 418 if (cdev->num_hwfns == 1) {
419 rc = pci_enable_msi(cdev->pdev);
420 if (!rc) {
421 int_params->out.int_mode = QED_INT_MODE_MSI;
422 goto out;
423 }
424
425 DP_NOTICE(cdev, "Failed to enable MSI\n");
426 if (force_mode)
427 goto out;
fe56b9e6 428 }
fe56b9e6
YM		 429 /* Fallthrough */
430
431 case QED_INT_MODE_INTA:
432 int_params->out.int_mode = QED_INT_MODE_INTA;
433 rc = 0;
434 goto out;
435 default:
436 DP_NOTICE(cdev, "Unknown int_mode value %d\n",
437 int_params->in.int_mode);
438 rc = -EINVAL;
439 }
440
441out:
442 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
443
444 return rc;
445}
446
447static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
448 int index, void(*handler)(void *))
449{
450 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
451 int relative_idx = index / cdev->num_hwfns;
452
453 hwfn->simd_proto_handler[relative_idx].func = handler;
454 hwfn->simd_proto_handler[relative_idx].token = token;
455}
456
457static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
458{
459 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
460 int relative_idx = index / cdev->num_hwfns;
461
462 memset(&hwfn->simd_proto_handler[relative_idx], 0,
463 sizeof(struct qed_simd_fp_handler));
464}
465
466static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
467{
468 tasklet_schedule((struct tasklet_struct *)tasklet);
469 return IRQ_HANDLED;
470}
471
472static irqreturn_t qed_single_int(int irq, void *dev_instance)
473{
474 struct qed_dev *cdev = (struct qed_dev *)dev_instance;
475 struct qed_hwfn *hwfn;
476 irqreturn_t rc = IRQ_NONE;
477 u64 status;
478 int i, j;
479
480 for (i = 0; i < cdev->num_hwfns; i++) {
481 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
482
483 if (!status)
484 continue;
485
486 hwfn = &cdev->hwfns[i];
487
488 /* Slowpath interrupt */
489 if (unlikely(status & 0x1)) {
490 tasklet_schedule(hwfn->sp_dpc);
491 status &= ~0x1;
492 rc = IRQ_HANDLED;
493 }
494
495 /* Fastpath interrupts */
496 for (j = 0; j < 64; j++) {
497 if ((0x2ULL << j) & status) {
498 hwfn->simd_proto_handler[j].func(
499 hwfn->simd_proto_handler[j].token);
500 status &= ~(0x2ULL << j);
501 rc = IRQ_HANDLED;
502 }
503 }
504
505 if (unlikely(status))
506 DP_VERBOSE(hwfn, NETIF_MSG_INTR,
507 "got an unknown interrupt status 0x%llx\n",
508 status);
509 }
510
511 return rc;
512}
513
8f16bc97 514int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
fe56b9e6 515{
8f16bc97
SK		 516 struct qed_dev *cdev = hwfn->cdev;
517 int rc = 0;
518 u8 id;
fe56b9e6
YM		 519
520 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
8f16bc97
SK		 521 id = hwfn->my_id;
522 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
523 id, cdev->pdev->bus->number,
524 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
525 rc = request_irq(cdev->int_params.msix_table[id].vector,
526 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
527 if (!rc)
528 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
fe56b9e6 529 "Requested slowpath MSI-X\n");
fe56b9e6
YM		 530 } else {
531 unsigned long flags = 0;
532
533 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
534 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
535 PCI_FUNC(cdev->pdev->devfn));
536
537 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
538 flags |= IRQF_SHARED;
539
540 rc = request_irq(cdev->pdev->irq, qed_single_int,
541 flags, cdev->name, cdev);
542 }
543
544 return rc;
545}
546
547static void qed_slowpath_irq_free(struct qed_dev *cdev)
548{
549 int i;
550
551 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
552 for_each_hwfn(cdev, i) {
8f16bc97
SK		 553 if (!cdev->hwfns[i].b_int_requested)
554 break;
fe56b9e6
YM		 555 synchronize_irq(cdev->int_params.msix_table[i].vector);
556 free_irq(cdev->int_params.msix_table[i].vector,
557 cdev->hwfns[i].sp_dpc);
558 }
559 } else {
8f16bc97
SK		 560 if (QED_LEADING_HWFN(cdev)->b_int_requested)
561 free_irq(cdev->pdev->irq, cdev);
fe56b9e6 562 }
8f16bc97 563 qed_int_disable_post_isr_release(cdev);
fe56b9e6
YM		 564}
565
566static int qed_nic_stop(struct qed_dev *cdev)
567{
568 int i, rc;
569
570 rc = qed_hw_stop(cdev);
571
572 for (i = 0; i < cdev->num_hwfns; i++) {
573 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
574
575 if (p_hwfn->b_sp_dpc_enabled) {
576 tasklet_disable(p_hwfn->sp_dpc);
577 p_hwfn->b_sp_dpc_enabled = false;
578 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
579 "Disabled sp taskelt [hwfn %d] at %p\n",
580 i, p_hwfn->sp_dpc);
581 }
582 }
583
584 return rc;
585}
586
587static int qed_nic_reset(struct qed_dev *cdev)
588{
589 int rc;
590
591 rc = qed_hw_reset(cdev);
592 if (rc)
593 return rc;
594
595 qed_resc_free(cdev);
596
597 return 0;
598}
599
600static int qed_nic_setup(struct qed_dev *cdev)
601{
602 int rc;
603
604 rc = qed_resc_alloc(cdev);
605 if (rc)
606 return rc;
607
608 DP_INFO(cdev, "Allocated qed resources\n");
609
610 qed_resc_setup(cdev);
611
612 return rc;
613}
614
615static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
616{
617 int limit = 0;
618
619 /* Mark the fastpath as free/used */
620 cdev->int_params.fp_initialized = cnt ? true : false;
621
622 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
623 limit = cdev->num_hwfns * 63;
624 else if (cdev->int_params.fp_msix_cnt)
625 limit = cdev->int_params.fp_msix_cnt;
626
627 if (!limit)
628 return -ENOMEM;
629
630 return min_t(int, cnt, limit);
631}
632
633static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
634{
635 memset(info, 0, sizeof(struct qed_int_info));
636
637 if (!cdev->int_params.fp_initialized) {
638 DP_INFO(cdev,
639 "Protocol driver requested interrupt information, but its support is not yet configured\n");
640 return -EINVAL;
641 }
642
643 /* Need to expose only MSI-X information; Single IRQ is handled solely
644 * by qed.
645 */
646 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
647 int msix_base = cdev->int_params.fp_msix_base;
648
649 info->msix_cnt = cdev->int_params.fp_msix_cnt;
650 info->msix = &cdev->int_params.msix_table[msix_base];
651 }
652
653 return 0;
654}
655
656static int qed_slowpath_setup_int(struct qed_dev *cdev,
657 enum qed_int_mode int_mode)
658{
4ac801b7
YM		 659 struct qed_sb_cnt_info sb_cnt_info;
660 int rc;
661 int i;
fe56b9e6 662
1d2c2024
SRK		 663 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
664 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
665 return -EINVAL;
666 }
667
668 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
fe56b9e6 669 cdev->int_params.in.int_mode = int_mode;
4ac801b7
YM		 670 for_each_hwfn(cdev, i) {
671 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
672 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info);
673 cdev->int_params.in.num_vectors += sb_cnt_info.sb_cnt;
674 cdev->int_params.in.num_vectors++; /* slowpath */
675 }
fe56b9e6
YM		 676
677 /* We want a minimum of one slowpath and one fastpath vector per hwfn */
678 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
679
680 rc = qed_set_int_mode(cdev, false);
681 if (rc) {
682 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
683 return rc;
684 }
685
686 cdev->int_params.fp_msix_base = cdev->num_hwfns;
687 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
688 cdev->num_hwfns;
689
690 return 0;
691}
692
1408cc1f
YM		 693static int qed_slowpath_vf_setup_int(struct qed_dev *cdev)
694{
695 int rc;
696
697 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
698 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX;
699
700 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev),
701 &cdev->int_params.in.num_vectors);
702 if (cdev->num_hwfns > 1) {
703 u8 vectors = 0;
704
705 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors);
706 cdev->int_params.in.num_vectors += vectors;
707 }
708
709 /* We want a minimum of one fastpath vector per vf hwfn */
710 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns;
711
712 rc = qed_set_int_mode(cdev, true);
713 if (rc)
714 return rc;
715
716 cdev->int_params.fp_msix_base = 0;
717 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors;
718
719 return 0;
720}
721
fe56b9e6
YM		 722u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
723 u8 *input_buf, u32 max_size, u8 *unzip_buf)
724{
725 int rc;
726
727 p_hwfn->stream->next_in = input_buf;
728 p_hwfn->stream->avail_in = input_len;
729 p_hwfn->stream->next_out = unzip_buf;
730 p_hwfn->stream->avail_out = max_size;
731
732 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
733
734 if (rc != Z_OK) {
735 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
736 rc);
737 return 0;
738 }
739
740 rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
741 zlib_inflateEnd(p_hwfn->stream);
742
743 if (rc != Z_OK && rc != Z_STREAM_END) {
744 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
745 p_hwfn->stream->msg, rc);
746 return 0;
747 }
748
749 return p_hwfn->stream->total_out / 4;
750}
751
752static int qed_alloc_stream_mem(struct qed_dev *cdev)
753{
754 int i;
755 void *workspace;
756
757 for_each_hwfn(cdev, i) {
758 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
759
760 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
761 if (!p_hwfn->stream)
762 return -ENOMEM;
763
764 workspace = vzalloc(zlib_inflate_workspacesize());
765 if (!workspace)
766 return -ENOMEM;
767 p_hwfn->stream->workspace = workspace;
768 }
769
770 return 0;
771}
772
773static void qed_free_stream_mem(struct qed_dev *cdev)
774{
775 int i;
776
777 for_each_hwfn(cdev, i) {
778 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
779
780 if (!p_hwfn->stream)
781 return;
782
783 vfree(p_hwfn->stream->workspace);
784 kfree(p_hwfn->stream);
785 }
786}
787
788static void qed_update_pf_params(struct qed_dev *cdev,
789 struct qed_pf_params *params)
790{
791 int i;
792
793 for (i = 0; i < cdev->num_hwfns; i++) {
794 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
795
796 p_hwfn->pf_params = *params;
797 }
798}
799
800static int qed_slowpath_start(struct qed_dev *cdev,
801 struct qed_slowpath_params *params)
802{
b18e170c 803 struct qed_tunn_start_params tunn_info;
fe56b9e6
YM		 804 struct qed_mcp_drv_version drv_version;
805 const u8 *data = NULL;
806 struct qed_hwfn *hwfn;
37bff2b9
YM		 807 int rc = -EINVAL;
808
809 if (qed_iov_wq_start(cdev))
810 goto err;
fe56b9e6 811
1408cc1f
YM		 812 if (IS_PF(cdev)) {
813 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME,
814 &cdev->pdev->dev);
815 if (rc) {
816 DP_NOTICE(cdev,
817 "Failed to find fw file - /lib/firmware/%s\n",
818 QED_FW_FILE_NAME);
819 goto err;
820 }
fe56b9e6
YM		 821 }
822
823 rc = qed_nic_setup(cdev);
824 if (rc)
825 goto err;
826
1408cc1f
YM		 827 if (IS_PF(cdev))
828 rc = qed_slowpath_setup_int(cdev, params->int_mode);
829 else
830 rc = qed_slowpath_vf_setup_int(cdev);
fe56b9e6
YM		 831 if (rc)
832 goto err1;
833
1408cc1f
YM		 834 if (IS_PF(cdev)) {
835 /* Allocate stream for unzipping */
836 rc = qed_alloc_stream_mem(cdev);
837 if (rc) {
838 DP_NOTICE(cdev, "Failed to allocate stream memory\n");
839 goto err2;
840 }
fe56b9e6 841
351a4ded
YM		 842 /* First Dword used to diffrentiate between various sources */
843 data = cdev->firmware->data + sizeof(u32);
1408cc1f 844 }
fe56b9e6 845
b18e170c 846 memset(&tunn_info, 0, sizeof(tunn_info));
9a109dd0 847 tunn_info.tunn_mode |= 1 << QED_MODE_VXLAN_TUNN |
f7985869
MC		 848 1 << QED_MODE_L2GRE_TUNN |
849 1 << QED_MODE_IPGRE_TUNN |
9a109dd0
MC		 850 1 << QED_MODE_L2GENEVE_TUNN |
851 1 << QED_MODE_IPGENEVE_TUNN;
852
b18e170c 853 tunn_info.tunn_clss_vxlan = QED_TUNN_CLSS_MAC_VLAN;
f7985869
MC		 854 tunn_info.tunn_clss_l2gre = QED_TUNN_CLSS_MAC_VLAN;
855 tunn_info.tunn_clss_ipgre = QED_TUNN_CLSS_MAC_VLAN;
b18e170c 856
1408cc1f 857 /* Start the slowpath */
b18e170c
MC		 858 rc = qed_hw_init(cdev, &tunn_info, true,
859 cdev->int_params.out.int_mode,
fe56b9e6
YM		 860 true, data);
861 if (rc)
8c925c44 862 goto err2;
fe56b9e6
YM		 863
864 DP_INFO(cdev,
865 "HW initialization and function start completed successfully\n");
866
1408cc1f
YM		 867 if (IS_PF(cdev)) {
868 hwfn = QED_LEADING_HWFN(cdev);
869 drv_version.version = (params->drv_major << 24) |
870 (params->drv_minor << 16) |
871 (params->drv_rev << 8) |
872 (params->drv_eng);
873 strlcpy(drv_version.name, params->name,
874 MCP_DRV_VER_STR_SIZE - 4);
875 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
876 &drv_version);
877 if (rc) {
878 DP_NOTICE(cdev, "Failed sending drv version command\n");
879 return rc;
880 }
fe56b9e6
YM		 881 }
882
8c925c44
YM		 883 qed_reset_vport_stats(cdev);
884
fe56b9e6
YM		 885 return 0;
886
fe56b9e6 887err2:
8c925c44 888 qed_hw_timers_stop_all(cdev);
1408cc1f
YM		 889 if (IS_PF(cdev))
890 qed_slowpath_irq_free(cdev);
8c925c44 891 qed_free_stream_mem(cdev);
fe56b9e6
YM		 892 qed_disable_msix(cdev);
893err1:
894 qed_resc_free(cdev);
895err:
1408cc1f
YM		 896 if (IS_PF(cdev))
897 release_firmware(cdev->firmware);
fe56b9e6 898
37bff2b9
YM		 899 qed_iov_wq_stop(cdev, false);
900
fe56b9e6
YM		 901 return rc;
902}
903
904static int qed_slowpath_stop(struct qed_dev *cdev)
905{
906 if (!cdev)
907 return -ENODEV;
908
1408cc1f
YM		 909 if (IS_PF(cdev)) {
910 qed_free_stream_mem(cdev);
c5ac9319
YM		 911 if (IS_QED_ETH_IF(cdev))
912 qed_sriov_disable(cdev, true);
fe56b9e6 913
1408cc1f
YM		 914 qed_nic_stop(cdev);
915 qed_slowpath_irq_free(cdev);
916 }
fe56b9e6
YM		 917
918 qed_disable_msix(cdev);
919 qed_nic_reset(cdev);
920
37bff2b9
YM		 921 qed_iov_wq_stop(cdev, true);
922
1408cc1f
YM		 923 if (IS_PF(cdev))
924 release_firmware(cdev->firmware);
fe56b9e6
YM		 925
926 return 0;
927}
928
929static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE],
930 char ver_str[VER_SIZE])
931{
932 int i;
933
934 memcpy(cdev->name, name, NAME_SIZE);
935 for_each_hwfn(cdev, i)
936 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
937
938 memcpy(cdev->ver_str, ver_str, VER_SIZE);
939 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
940}
941
942static u32 qed_sb_init(struct qed_dev *cdev,
943 struct qed_sb_info *sb_info,
944 void *sb_virt_addr,
945 dma_addr_t sb_phy_addr, u16 sb_id,
946 enum qed_sb_type type)
947{
948 struct qed_hwfn *p_hwfn;
949 int hwfn_index;
950 u16 rel_sb_id;
951 u8 n_hwfns;
952 u32 rc;
953
954 /* RoCE uses single engine and CMT uses two engines. When using both
955 * we force only a single engine. Storage uses only engine 0 too.
956 */
957 if (type == QED_SB_TYPE_L2_QUEUE)
958 n_hwfns = cdev->num_hwfns;
959 else
960 n_hwfns = 1;
961
962 hwfn_index = sb_id % n_hwfns;
963 p_hwfn = &cdev->hwfns[hwfn_index];
964 rel_sb_id = sb_id / n_hwfns;
965
966 DP_VERBOSE(cdev, NETIF_MSG_INTR,
967 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
968 hwfn_index, rel_sb_id, sb_id);
969
970 rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info,
971 sb_virt_addr, sb_phy_addr, rel_sb_id);
972
973 return rc;
974}
975
976static u32 qed_sb_release(struct qed_dev *cdev,
977 struct qed_sb_info *sb_info,
978 u16 sb_id)
979{
980 struct qed_hwfn *p_hwfn;
981 int hwfn_index;
982 u16 rel_sb_id;
983 u32 rc;
984
985 hwfn_index = sb_id % cdev->num_hwfns;
986 p_hwfn = &cdev->hwfns[hwfn_index];
987 rel_sb_id = sb_id / cdev->num_hwfns;
988
989 DP_VERBOSE(cdev, NETIF_MSG_INTR,
990 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
991 hwfn_index, rel_sb_id, sb_id);
992
993 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
994
995 return rc;
996}
997
fe7cd2bf
YM		 998static bool qed_can_link_change(struct qed_dev *cdev)
999{
1000 return true;
1001}
1002
351a4ded 1003static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
cc875c2e
YM		 1004{
1005 struct qed_hwfn *hwfn;
1006 struct qed_mcp_link_params *link_params;
1007 struct qed_ptt *ptt;
1008 int rc;
1009
1010 if (!cdev)
1011 return -ENODEV;
1012
1408cc1f
YM		 1013 if (IS_VF(cdev))
1014 return 0;
1015
cc875c2e
YM		 1016 /* The link should be set only once per PF */
1017 hwfn = &cdev->hwfns[0];
1018
1019 ptt = qed_ptt_acquire(hwfn);
1020 if (!ptt)
1021 return -EBUSY;
1022
1023 link_params = qed_mcp_get_link_params(hwfn);
1024 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
1025 link_params->speed.autoneg = params->autoneg;
1026 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
1027 link_params->speed.advertised_speeds = 0;
1028 if ((params->adv_speeds & SUPPORTED_1000baseT_Half) ||
1029 (params->adv_speeds & SUPPORTED_1000baseT_Full))
1030 link_params->speed.advertised_speeds |=
1031 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
1032 if (params->adv_speeds & SUPPORTED_10000baseKR_Full)
1033 link_params->speed.advertised_speeds |=
1034 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
1035 if (params->adv_speeds & SUPPORTED_40000baseLR4_Full)
1036 link_params->speed.advertised_speeds |=
1037 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
1038 if (params->adv_speeds & 0)
1039 link_params->speed.advertised_speeds |=
1040 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
1041 if (params->adv_speeds & 0)
1042 link_params->speed.advertised_speeds |=
351a4ded 1043 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G;
cc875c2e
YM		 1044 }
1045 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
1046 link_params->speed.forced_speed = params->forced_speed;
a43f235f
SRK		 1047 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
1048 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1049 link_params->pause.autoneg = true;
1050 else
1051 link_params->pause.autoneg = false;
1052 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
1053 link_params->pause.forced_rx = true;
1054 else
1055 link_params->pause.forced_rx = false;
1056 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
1057 link_params->pause.forced_tx = true;
1058 else
1059 link_params->pause.forced_tx = false;
1060 }
03dc76ca
SRK		 1061 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) {
1062 switch (params->loopback_mode) {
1063 case QED_LINK_LOOPBACK_INT_PHY:
351a4ded 1064 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY;
03dc76ca
SRK		 1065 break;
1066 case QED_LINK_LOOPBACK_EXT_PHY:
351a4ded 1067 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY;
03dc76ca
SRK		 1068 break;
1069 case QED_LINK_LOOPBACK_EXT:
351a4ded 1070 link_params->loopback_mode = ETH_LOOPBACK_EXT;
03dc76ca
SRK		 1071 break;
1072 case QED_LINK_LOOPBACK_MAC:
351a4ded 1073 link_params->loopback_mode = ETH_LOOPBACK_MAC;
03dc76ca
SRK		 1074 break;
1075 default:
351a4ded 1076 link_params->loopback_mode = ETH_LOOPBACK_NONE;
03dc76ca
SRK		 1077 break;
1078 }
1079 }
cc875c2e
YM		 1080
1081 rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
1082
1083 qed_ptt_release(hwfn, ptt);
1084
1085 return rc;
1086}
1087
1088static int qed_get_port_type(u32 media_type)
1089{
1090 int port_type;
1091
1092 switch (media_type) {
1093 case MEDIA_SFPP_10G_FIBER:
1094 case MEDIA_SFP_1G_FIBER:
1095 case MEDIA_XFP_FIBER:
b639f197 1096 case MEDIA_MODULE_FIBER:
cc875c2e
YM		 1097 case MEDIA_KR:
1098 port_type = PORT_FIBRE;
1099 break;
1100 case MEDIA_DA_TWINAX:
1101 port_type = PORT_DA;
1102 break;
1103 case MEDIA_BASE_T:
1104 port_type = PORT_TP;
1105 break;
1106 case MEDIA_NOT_PRESENT:
1107 port_type = PORT_NONE;
1108 break;
1109 case MEDIA_UNSPECIFIED:
1110 default:
1111 port_type = PORT_OTHER;
1112 break;
1113 }
1114 return port_type;
1115}
1116
14b84e86
AB		 1117static int qed_get_link_data(struct qed_hwfn *hwfn,
1118 struct qed_mcp_link_params *params,
1119 struct qed_mcp_link_state *link,
1120 struct qed_mcp_link_capabilities *link_caps)
1121{
1122 void *p;
1123
1124 if (!IS_PF(hwfn->cdev)) {
1125 qed_vf_get_link_params(hwfn, params);
1126 qed_vf_get_link_state(hwfn, link);
1127 qed_vf_get_link_caps(hwfn, link_caps);
1128
1129 return 0;
1130 }
1131
1132 p = qed_mcp_get_link_params(hwfn);
1133 if (!p)
1134 return -ENXIO;
1135 memcpy(params, p, sizeof(*params));
1136
1137 p = qed_mcp_get_link_state(hwfn);
1138 if (!p)
1139 return -ENXIO;
1140 memcpy(link, p, sizeof(*link));
1141
1142 p = qed_mcp_get_link_capabilities(hwfn);
1143 if (!p)
1144 return -ENXIO;
1145 memcpy(link_caps, p, sizeof(*link_caps));
1146
1147 return 0;
1148}
1149
cc875c2e
YM		 1150static void qed_fill_link(struct qed_hwfn *hwfn,
1151 struct qed_link_output *if_link)
1152{
1153 struct qed_mcp_link_params params;
1154 struct qed_mcp_link_state link;
1155 struct qed_mcp_link_capabilities link_caps;
1156 u32 media_type;
1157
1158 memset(if_link, 0, sizeof(*if_link));
1159
1160 /* Prepare source inputs */
14b84e86
AB		 1161 if (qed_get_link_data(hwfn, &params, &link, &link_caps)) {
1162 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n");
1163 return;
1408cc1f 1164 }
cc875c2e
YM		 1165
1166 /* Set the link parameters to pass to protocol driver */
1167 if (link.link_up)
1168 if_link->link_up = true;
1169
1170 /* TODO - at the moment assume supported and advertised speed equal */
1171 if_link->supported_caps = SUPPORTED_FIBRE;
1172 if (params.speed.autoneg)
1173 if_link->supported_caps |= SUPPORTED_Autoneg;
1174 if (params.pause.autoneg ||
1175 (params.pause.forced_rx && params.pause.forced_tx))
1176 if_link->supported_caps |= SUPPORTED_Asym_Pause;
1177 if (params.pause.autoneg || params.pause.forced_rx ||
1178 params.pause.forced_tx)
1179 if_link->supported_caps |= SUPPORTED_Pause;
1180
1181 if_link->advertised_caps = if_link->supported_caps;
1182 if (params.speed.advertised_speeds &
1183 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1184 if_link->advertised_caps |= SUPPORTED_1000baseT_Half |
1185 SUPPORTED_1000baseT_Full;
1186 if (params.speed.advertised_speeds &
1187 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1188 if_link->advertised_caps |= SUPPORTED_10000baseKR_Full;
1189 if (params.speed.advertised_speeds &
1190 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1191 if_link->advertised_caps |= SUPPORTED_40000baseLR4_Full;
1192 if (params.speed.advertised_speeds &
1193 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1194 if_link->advertised_caps |= 0;
1195 if (params.speed.advertised_speeds &
351a4ded 1196 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
cc875c2e
YM		 1197 if_link->advertised_caps |= 0;
1198
1199 if (link_caps.speed_capabilities &
1200 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1201 if_link->supported_caps |= SUPPORTED_1000baseT_Half |
1202 SUPPORTED_1000baseT_Full;
1203 if (link_caps.speed_capabilities &
1204 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1205 if_link->supported_caps |= SUPPORTED_10000baseKR_Full;
1206 if (link_caps.speed_capabilities &
1207 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1208 if_link->supported_caps |= SUPPORTED_40000baseLR4_Full;
1209 if (link_caps.speed_capabilities &
1210 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1211 if_link->supported_caps |= 0;
1212 if (link_caps.speed_capabilities &
351a4ded 1213 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
cc875c2e
YM		 1214 if_link->supported_caps |= 0;
1215
1216 if (link.link_up)
1217 if_link->speed = link.speed;
1218
1219 /* TODO - fill duplex properly */
1220 if_link->duplex = DUPLEX_FULL;
1221 qed_mcp_get_media_type(hwfn->cdev, &media_type);
1222 if_link->port = qed_get_port_type(media_type);
1223
1224 if_link->autoneg = params.speed.autoneg;
1225
1226 if (params.pause.autoneg)
1227 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1228 if (params.pause.forced_rx)
1229 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1230 if (params.pause.forced_tx)
1231 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1232
1233 /* Link partner capabilities */
1234 if (link.partner_adv_speed &
1235 QED_LINK_PARTNER_SPEED_1G_HD)
1236 if_link->lp_caps |= SUPPORTED_1000baseT_Half;
1237 if (link.partner_adv_speed &
1238 QED_LINK_PARTNER_SPEED_1G_FD)
1239 if_link->lp_caps |= SUPPORTED_1000baseT_Full;
1240 if (link.partner_adv_speed &
1241 QED_LINK_PARTNER_SPEED_10G)
1242 if_link->lp_caps |= SUPPORTED_10000baseKR_Full;
1243 if (link.partner_adv_speed &
1244 QED_LINK_PARTNER_SPEED_40G)
1245 if_link->lp_caps |= SUPPORTED_40000baseLR4_Full;
1246 if (link.partner_adv_speed &
1247 QED_LINK_PARTNER_SPEED_50G)
1248 if_link->lp_caps |= 0;
1249 if (link.partner_adv_speed &
1250 QED_LINK_PARTNER_SPEED_100G)
1251 if_link->lp_caps |= 0;
1252
1253 if (link.an_complete)
1254 if_link->lp_caps |= SUPPORTED_Autoneg;
1255
1256 if (link.partner_adv_pause)
1257 if_link->lp_caps |= SUPPORTED_Pause;
1258 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
1259 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
1260 if_link->lp_caps |= SUPPORTED_Asym_Pause;
1261}
1262
1263static void qed_get_current_link(struct qed_dev *cdev,
1264 struct qed_link_output *if_link)
1265{
36558c3d
YM		 1266 int i;
1267
cc875c2e 1268 qed_fill_link(&cdev->hwfns[0], if_link);
36558c3d
YM		 1269
1270 for_each_hwfn(cdev, i)
1271 qed_inform_vf_link_state(&cdev->hwfns[i]);
cc875c2e
YM		 1272}
1273
1274void qed_link_update(struct qed_hwfn *hwfn)
1275{
1276 void *cookie = hwfn->cdev->ops_cookie;
1277 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
1278 struct qed_link_output if_link;
1279
1280 qed_fill_link(hwfn, &if_link);
36558c3d 1281 qed_inform_vf_link_state(hwfn);
cc875c2e
YM		 1282
1283 if (IS_LEAD_HWFN(hwfn) && cookie)
1284 op->link_update(cookie, &if_link);
1285}
1286
fe56b9e6
YM		 1287static int qed_drain(struct qed_dev *cdev)
1288{
1289 struct qed_hwfn *hwfn;
1290 struct qed_ptt *ptt;
1291 int i, rc;
1292
1408cc1f
YM		 1293 if (IS_VF(cdev))
1294 return 0;
1295
fe56b9e6
YM		 1296 for_each_hwfn(cdev, i) {
1297 hwfn = &cdev->hwfns[i];
1298 ptt = qed_ptt_acquire(hwfn);
1299 if (!ptt) {
1300 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
1301 return -EBUSY;
1302 }
1303 rc = qed_mcp_drain(hwfn, ptt);
1304 if (rc)
1305 return rc;
1306 qed_ptt_release(hwfn, ptt);
1307 }
1308
1309 return 0;
1310}
1311
722003ac
SRK		 1312static void qed_get_coalesce(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal)
1313{
1314 *rx_coal = cdev->rx_coalesce_usecs;
1315 *tx_coal = cdev->tx_coalesce_usecs;
1316}
1317
1318static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
1319 u8 qid, u16 sb_id)
1320{
1321 struct qed_hwfn *hwfn;
1322 struct qed_ptt *ptt;
1323 int hwfn_index;
1324 int status = 0;
1325
1326 hwfn_index = qid % cdev->num_hwfns;
1327 hwfn = &cdev->hwfns[hwfn_index];
1328 ptt = qed_ptt_acquire(hwfn);
1329 if (!ptt)
1330 return -EAGAIN;
1331
1332 status = qed_set_rxq_coalesce(hwfn, ptt, rx_coal,
1333 qid / cdev->num_hwfns, sb_id);
1334 if (status)
1335 goto out;
1336 status = qed_set_txq_coalesce(hwfn, ptt, tx_coal,
1337 qid / cdev->num_hwfns, sb_id);
1338out:
1339 qed_ptt_release(hwfn, ptt);
1340
1341 return status;
1342}
1343
91420b83
SK		 1344static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
1345{
1346 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1347 struct qed_ptt *ptt;
1348 int status = 0;
1349
1350 ptt = qed_ptt_acquire(hwfn);
1351 if (!ptt)
1352 return -EAGAIN;
1353
1354 status = qed_mcp_set_led(hwfn, ptt, mode);
1355
1356 qed_ptt_release(hwfn, ptt);
1357
1358 return status;
1359}
1360
03dc76ca
SRK		 1361struct qed_selftest_ops qed_selftest_ops_pass = {
1362 .selftest_memory = &qed_selftest_memory,
1363 .selftest_interrupt = &qed_selftest_interrupt,
1364 .selftest_register = &qed_selftest_register,
1365 .selftest_clock = &qed_selftest_clock,
1366};
1367
fe56b9e6 1368const struct qed_common_ops qed_common_ops_pass = {
03dc76ca 1369 .selftest = &qed_selftest_ops_pass,
fe56b9e6
YM		 1370 .probe = &qed_probe,
1371 .remove = &qed_remove,
1372 .set_power_state = &qed_set_power_state,
1373 .set_id = &qed_set_id,
1374 .update_pf_params = &qed_update_pf_params,
1375 .slowpath_start = &qed_slowpath_start,
1376 .slowpath_stop = &qed_slowpath_stop,
1377 .set_fp_int = &qed_set_int_fp,
1378 .get_fp_int = &qed_get_int_fp,
1379 .sb_init = &qed_sb_init,
1380 .sb_release = &qed_sb_release,
1381 .simd_handler_config = &qed_simd_handler_config,
1382 .simd_handler_clean = &qed_simd_handler_clean,
fe7cd2bf 1383 .can_link_change = &qed_can_link_change,
cc875c2e
YM		 1384 .set_link = &qed_set_link,
1385 .get_link = &qed_get_current_link,
fe56b9e6
YM		 1386 .drain = &qed_drain,
1387 .update_msglvl = &qed_init_dp,
1388 .chain_alloc = &qed_chain_alloc,
1389 .chain_free = &qed_chain_free,
722003ac
SRK		 1390 .get_coalesce = &qed_get_coalesce,
1391 .set_coalesce = &qed_set_coalesce,
91420b83 1392 .set_led = &qed_set_led,
fe56b9e6 1393};
Linux kernel - Deliverables
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