[deliverable/linux.git] / drivers / net / ethernet / qlogic / qede / qede.h

/* QLogic qede NIC Driver
* Copyright (c) 2015 QLogic Corporation
*
* This software is available under the terms of the GNU General Public License
* (GPL) Version 2, available from the file COPYING in the main directory of
* this source tree.
*/

#ifndef _QEDE_H_
#define _QEDE_H_
#include <linux/compiler.h>
#include <linux/version.h>
#include <linux/workqueue.h>
#include <linux/netdevice.h>
#include <linux/interrupt.h>
#include <linux/bitmap.h>
#include <linux/kernel.h>
#include <linux/mutex.h>
#include <linux/io.h>
#include <linux/qed/common_hsi.h>
#include <linux/qed/eth_common.h>
#include <linux/qed/qed_if.h>
#include <linux/qed/qed_chain.h>
#include <linux/qed/qed_eth_if.h>

#define QEDE_MAJOR_VERSION		8
#define QEDE_MINOR_VERSION		10
#define QEDE_REVISION_VERSION		1
#define QEDE_ENGINEERING_VERSION	20
#define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "."	\
		__stringify(QEDE_MINOR_VERSION) "."		\
		__stringify(QEDE_REVISION_VERSION) "."		\
		__stringify(QEDE_ENGINEERING_VERSION)

#define DRV_MODULE_SYM		qede

struct qede_stats {
	u64 no_buff_discards;
	u64 rx_ucast_bytes;
	u64 rx_mcast_bytes;
	u64 rx_bcast_bytes;
	u64 rx_ucast_pkts;
	u64 rx_mcast_pkts;
	u64 rx_bcast_pkts;
	u64 mftag_filter_discards;
	u64 mac_filter_discards;
	u64 tx_ucast_bytes;
	u64 tx_mcast_bytes;
	u64 tx_bcast_bytes;
	u64 tx_ucast_pkts;
	u64 tx_mcast_pkts;
	u64 tx_bcast_pkts;
	u64 tx_err_drop_pkts;
	u64 coalesced_pkts;
	u64 coalesced_events;
	u64 coalesced_aborts_num;
	u64 non_coalesced_pkts;
	u64 coalesced_bytes;

	/* port */
	u64 rx_64_byte_packets;
	u64 rx_65_to_127_byte_packets;
	u64 rx_128_to_255_byte_packets;
	u64 rx_256_to_511_byte_packets;
	u64 rx_512_to_1023_byte_packets;
	u64 rx_1024_to_1518_byte_packets;
	u64 rx_1519_to_1522_byte_packets;
	u64 rx_1519_to_2047_byte_packets;
	u64 rx_2048_to_4095_byte_packets;
	u64 rx_4096_to_9216_byte_packets;
	u64 rx_9217_to_16383_byte_packets;
	u64 rx_crc_errors;
	u64 rx_mac_crtl_frames;
	u64 rx_pause_frames;
	u64 rx_pfc_frames;
	u64 rx_align_errors;
	u64 rx_carrier_errors;
	u64 rx_oversize_packets;
	u64 rx_jabbers;
	u64 rx_undersize_packets;
	u64 rx_fragments;
	u64 tx_64_byte_packets;
	u64 tx_65_to_127_byte_packets;
	u64 tx_128_to_255_byte_packets;
	u64 tx_256_to_511_byte_packets;
	u64 tx_512_to_1023_byte_packets;
	u64 tx_1024_to_1518_byte_packets;
	u64 tx_1519_to_2047_byte_packets;
	u64 tx_2048_to_4095_byte_packets;
	u64 tx_4096_to_9216_byte_packets;
	u64 tx_9217_to_16383_byte_packets;
	u64 tx_pause_frames;
	u64 tx_pfc_frames;
	u64 tx_lpi_entry_count;
	u64 tx_total_collisions;
	u64 brb_truncates;
	u64 brb_discards;
	u64 tx_mac_ctrl_frames;
};

struct qede_vlan {
	struct list_head list;
	u16 vid;
	bool configured;
};

struct qede_dev {
	struct qed_dev			*cdev;
	struct net_device		*ndev;
	struct pci_dev			*pdev;

	u32				dp_module;
	u8				dp_level;

	u32 flags;
#define QEDE_FLAG_IS_VF	BIT(0)
#define IS_VF(edev)	(!!((edev)->flags & QEDE_FLAG_IS_VF))

	const struct qed_eth_ops	*ops;

	struct qed_dev_eth_info	dev_info;
#define QEDE_MAX_RSS_CNT(edev)	((edev)->dev_info.num_queues)
#define QEDE_MAX_TSS_CNT(edev)	((edev)->dev_info.num_queues * \
				 (edev)->dev_info.num_tc)

	struct qede_fastpath		*fp_array;
	u16				req_rss;
	u16				num_rss;
	u8				num_tc;
#define QEDE_RSS_CNT(edev)		((edev)->num_rss)
#define QEDE_TSS_CNT(edev)		((edev)->num_rss *	\
					 (edev)->num_tc)
#define QEDE_TSS_IDX(edev, txqidx)	((txqidx) % (edev)->num_rss)
#define QEDE_TC_IDX(edev, txqidx)	((txqidx) / (edev)->num_rss)
#define QEDE_TX_QUEUE(edev, txqidx)	\
	(&(edev)->fp_array[QEDE_TSS_IDX((edev), (txqidx))].txqs[QEDE_TC_IDX( \
							(edev), (txqidx))])

	struct qed_int_info		int_info;
	unsigned char			primary_mac[ETH_ALEN];

	/* Smaller private varaiant of the RTNL lock */
	struct mutex			qede_lock;
	u32				state; /* Protected by qede_lock */
	u16				rx_buf_size;
	u32				rx_copybreak;

	/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
#define ETH_OVERHEAD			(ETH_HLEN + 8 + 8)
	/* Max supported alignment is 256 (8 shift)
	 * minimal alignment shift 6 is optimal for 57xxx HW performance
	 */
#define QEDE_RX_ALIGN_SHIFT		max(6, min(8, L1_CACHE_SHIFT))
	/* We assume skb_build() uses sizeof(struct skb_shared_info) bytes
	 * at the end of skb->data, to avoid wasting a full cache line.
	 * This reduces memory use (skb->truesize).
	 */
#define QEDE_FW_RX_ALIGN_END					\
	max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT,			\
	      SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))

	struct qede_stats		stats;
#define QEDE_RSS_INDIR_INITED	BIT(0)
#define QEDE_RSS_KEY_INITED	BIT(1)
#define QEDE_RSS_CAPS_INITED	BIT(2)
	u32 rss_params_inited; /* bit-field to track initialized rss params */
	struct qed_update_vport_rss_params	rss_params;
	u16			q_num_rx_buffers; /* Must be a power of two */
	u16			q_num_tx_buffers; /* Must be a power of two */

	bool gro_disable;
	struct list_head vlan_list;
	u16 configured_vlans;
	u16 non_configured_vlans;
	bool accept_any_vlan;
	struct delayed_work		sp_task;
	unsigned long			sp_flags;
	u16				vxlan_dst_port;
	u16				geneve_dst_port;
};

enum QEDE_STATE {
	QEDE_STATE_CLOSED,
	QEDE_STATE_OPEN,
};

#define HILO_U64(hi, lo)		((((u64)(hi)) << 32) + (lo))

#define	MAX_NUM_TC	8
#define	MAX_NUM_PRI	8

/* The driver supports the new build_skb() API:
 * RX ring buffer contains pointer to kmalloc() data only,
 * skb are built only after the frame was DMA-ed.
 */
struct sw_rx_data {
	struct page *data;
	dma_addr_t mapping;
	unsigned int page_offset;
};

enum qede_agg_state {
	QEDE_AGG_STATE_NONE  = 0,
	QEDE_AGG_STATE_START = 1,
	QEDE_AGG_STATE_ERROR = 2
};

struct qede_agg_info {
	struct sw_rx_data replace_buf;
	dma_addr_t replace_buf_mapping;
	struct sw_rx_data start_buf;
	dma_addr_t start_buf_mapping;
	struct eth_fast_path_rx_tpa_start_cqe start_cqe;
	enum qede_agg_state agg_state;
	struct sk_buff *skb;
	int frag_id;
	u16 vlan_tag;
};

struct qede_rx_queue {
	__le16			*hw_cons_ptr;
	struct sw_rx_data	*sw_rx_ring;
	u16			sw_rx_cons;
	u16			sw_rx_prod;
	struct qed_chain	rx_bd_ring;
	struct qed_chain	rx_comp_ring;
	void __iomem		*hw_rxq_prod_addr;

	/* GRO */
	struct qede_agg_info	tpa_info[ETH_TPA_MAX_AGGS_NUM];

	int			rx_buf_size;
	unsigned int		rx_buf_seg_size;

	u16			num_rx_buffers;
	u16			rxq_id;

	u64			rx_hw_errors;
	u64			rx_alloc_errors;
	u64			rx_ip_frags;
};

union db_prod {
	struct eth_db_data data;
	u32		raw;
};

struct sw_tx_bd {
	struct sk_buff *skb;
	u8 flags;
/* Set on the first BD descriptor when there is a split BD */
#define QEDE_TSO_SPLIT_BD		BIT(0)
};

struct qede_tx_queue {
	int			index; /* Queue index */
	__le16			*hw_cons_ptr;
	struct sw_tx_bd		*sw_tx_ring;
	u16			sw_tx_cons;
	u16			sw_tx_prod;
	struct qed_chain	tx_pbl;
	void __iomem		*doorbell_addr;
	union db_prod		tx_db;

	u16			num_tx_buffers;
};

#define BD_UNMAP_ADDR(bd)		HILO_U64(le32_to_cpu((bd)->addr.hi), \
						 le32_to_cpu((bd)->addr.lo))
#define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len)				\
	do {								\
		(bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr));	\
		(bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr));	\
		(bd)->nbytes = cpu_to_le16(len);			\
	} while (0)
#define BD_UNMAP_LEN(bd)		(le16_to_cpu((bd)->nbytes))

struct qede_fastpath {
	struct qede_dev	*edev;
	u8			rss_id;
	struct napi_struct	napi;
	struct qed_sb_info	*sb_info;
	struct qede_rx_queue	*rxq;
	struct qede_tx_queue	*txqs;

#define VEC_NAME_SIZE	(sizeof(((struct net_device *)0)->name) + 8)
	char	name[VEC_NAME_SIZE];
};

/* Debug print definitions */
#define DP_NAME(edev) ((edev)->ndev->name)

#define XMIT_PLAIN		0
#define XMIT_L4_CSUM		BIT(0)
#define XMIT_LSO		BIT(1)
#define XMIT_ENC		BIT(2)

#define QEDE_CSUM_ERROR			BIT(0)
#define QEDE_CSUM_UNNECESSARY		BIT(1)
#define QEDE_TUNN_CSUM_UNNECESSARY	BIT(2)

#define QEDE_SP_RX_MODE			1
#define QEDE_SP_VXLAN_PORT_CONFIG	2
#define QEDE_SP_GENEVE_PORT_CONFIG	3

union qede_reload_args {
	u16 mtu;
};

#ifdef CONFIG_DCB
void qede_set_dcbnl_ops(struct net_device *ndev);
#endif
void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level);
void qede_set_ethtool_ops(struct net_device *netdev);
void qede_reload(struct qede_dev *edev,
		 void (*func)(struct qede_dev *edev,
			      union qede_reload_args *args),
		 union qede_reload_args *args);
int qede_change_mtu(struct net_device *dev, int new_mtu);
void qede_fill_by_demand_stats(struct qede_dev *edev);
bool qede_has_rx_work(struct qede_rx_queue *rxq);
int qede_txq_has_work(struct qede_tx_queue *txq);
void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, struct qede_dev *edev,
			     u8 count);

#define RX_RING_SIZE_POW	13
#define RX_RING_SIZE		((u16)BIT(RX_RING_SIZE_POW))
#define NUM_RX_BDS_MAX		(RX_RING_SIZE - 1)
#define NUM_RX_BDS_MIN		128
#define NUM_RX_BDS_DEF		NUM_RX_BDS_MAX

#define TX_RING_SIZE_POW	13
#define TX_RING_SIZE		((u16)BIT(TX_RING_SIZE_POW))
#define NUM_TX_BDS_MAX		(TX_RING_SIZE - 1)
#define NUM_TX_BDS_MIN		128
#define NUM_TX_BDS_DEF		NUM_TX_BDS_MAX

#define QEDE_MIN_PKT_LEN	64
#define QEDE_RX_HDR_SIZE	256
#define	for_each_rss(i) for (i = 0; i < edev->num_rss; i++)

#endif /* _QEDE_H_ */
Commit	Line	Data
e712d52b YM	1	/* QLogic qede NIC Driver
	2	* Copyright (c) 2015 QLogic Corporation
	3	*
	4	* This software is available under the terms of the GNU General Public License
	5	* (GPL) Version 2, available from the file COPYING in the main directory of
	6	* this source tree.
	7	*/
	8
	9	#ifndef _QEDE_H_
	10	#define _QEDE_H_
	11	#include <linux/compiler.h>
	12	#include <linux/version.h>
	13	#include <linux/workqueue.h>
	14	#include <linux/netdevice.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/bitmap.h>
	17	#include <linux/kernel.h>
	18	#include <linux/mutex.h>
	19	#include <linux/io.h>
	20	#include <linux/qed/common_hsi.h>
	21	#include <linux/qed/eth_common.h>
	22	#include <linux/qed/qed_if.h>
	23	#include <linux/qed/qed_chain.h>
	24	#include <linux/qed/qed_eth_if.h>
	25
	26	#define QEDE_MAJOR_VERSION 8
831a8e6c	27	#define QEDE_MINOR_VERSION 10
7c2d7d74 YM	28	#define QEDE_REVISION_VERSION 1
7c2d7d74 YM	29	#define QEDE_ENGINEERING_VERSION 20
e712d52b YM	30	#define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \
	31	__stringify(QEDE_MINOR_VERSION) "." \
	32	__stringify(QEDE_REVISION_VERSION) "." \
	33	__stringify(QEDE_ENGINEERING_VERSION)
	34
e712d52b YM	35	#define DRV_MODULE_SYM qede
e712d52b YM	36
133fac0e SK	37	struct qede_stats {
	38	u64 no_buff_discards;
	39	u64 rx_ucast_bytes;
	40	u64 rx_mcast_bytes;
	41	u64 rx_bcast_bytes;
	42	u64 rx_ucast_pkts;
	43	u64 rx_mcast_pkts;
	44	u64 rx_bcast_pkts;
	45	u64 mftag_filter_discards;
	46	u64 mac_filter_discards;
	47	u64 tx_ucast_bytes;
	48	u64 tx_mcast_bytes;
	49	u64 tx_bcast_bytes;
	50	u64 tx_ucast_pkts;
	51	u64 tx_mcast_pkts;
	52	u64 tx_bcast_pkts;
	53	u64 tx_err_drop_pkts;
	54	u64 coalesced_pkts;
	55	u64 coalesced_events;
	56	u64 coalesced_aborts_num;
	57	u64 non_coalesced_pkts;
	58	u64 coalesced_bytes;
	59
	60	/* port */
	61	u64 rx_64_byte_packets;
d4967cf3 YM	62	u64 rx_65_to_127_byte_packets;
	63	u64 rx_128_to_255_byte_packets;
	64	u64 rx_256_to_511_byte_packets;
	65	u64 rx_512_to_1023_byte_packets;
	66	u64 rx_1024_to_1518_byte_packets;
	67	u64 rx_1519_to_1522_byte_packets;
	68	u64 rx_1519_to_2047_byte_packets;
	69	u64 rx_2048_to_4095_byte_packets;
	70	u64 rx_4096_to_9216_byte_packets;
	71	u64 rx_9217_to_16383_byte_packets;
133fac0e SK	72	u64 rx_crc_errors;
	73	u64 rx_mac_crtl_frames;
	74	u64 rx_pause_frames;
	75	u64 rx_pfc_frames;
	76	u64 rx_align_errors;
	77	u64 rx_carrier_errors;
	78	u64 rx_oversize_packets;
	79	u64 rx_jabbers;
	80	u64 rx_undersize_packets;
	81	u64 rx_fragments;
	82	u64 tx_64_byte_packets;
	83	u64 tx_65_to_127_byte_packets;
	84	u64 tx_128_to_255_byte_packets;
	85	u64 tx_256_to_511_byte_packets;
	86	u64 tx_512_to_1023_byte_packets;
	87	u64 tx_1024_to_1518_byte_packets;
	88	u64 tx_1519_to_2047_byte_packets;
	89	u64 tx_2048_to_4095_byte_packets;
	90	u64 tx_4096_to_9216_byte_packets;
	91	u64 tx_9217_to_16383_byte_packets;
	92	u64 tx_pause_frames;
	93	u64 tx_pfc_frames;
	94	u64 tx_lpi_entry_count;
	95	u64 tx_total_collisions;
	96	u64 brb_truncates;
	97	u64 brb_discards;
	98	u64 tx_mac_ctrl_frames;
	99	};
	100
7c1bfcad SRK	101	struct qede_vlan {
	102	struct list_head list;
	103	u16 vid;
	104	bool configured;
	105	};
	106
e712d52b YM	107	struct qede_dev {
	108	struct qed_dev *cdev;
	109	struct net_device *ndev;
	110	struct pci_dev *pdev;
	111
	112	u32 dp_module;
	113	u8 dp_level;
	114
fefb0202 YM	115	u32 flags;
	116	#define QEDE_FLAG_IS_VF BIT(0)
	117	#define IS_VF(edev) (!!((edev)->flags & QEDE_FLAG_IS_VF))
	118
e712d52b YM	119	const struct qed_eth_ops *ops;
	120
	121	struct qed_dev_eth_info dev_info;
	122	#define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues)
	123	#define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues * \
	124	(edev)->dev_info.num_tc)
	125
2950219d	126	struct qede_fastpath *fp_array;
8edf049d	127	u16 req_rss;
e712d52b YM	128	u16 num_rss;
	129	u8 num_tc;
	130	#define QEDE_RSS_CNT(edev) ((edev)->num_rss)
	131	#define QEDE_TSS_CNT(edev) ((edev)->num_rss * \
	132	(edev)->num_tc)
	133	#define QEDE_TSS_IDX(edev, txqidx) ((txqidx) % (edev)->num_rss)
	134	#define QEDE_TC_IDX(edev, txqidx) ((txqidx) / (edev)->num_rss)
2950219d YM	135	#define QEDE_TX_QUEUE(edev, txqidx) \
	136	(&(edev)->fp_array[QEDE_TSS_IDX((edev), (txqidx))].txqs[QEDE_TC_IDX( \
	137	(edev), (txqidx))])
e712d52b YM	138
	139	struct qed_int_info int_info;
	140	unsigned char primary_mac[ETH_ALEN];
	141
	142	/* Smaller private varaiant of the RTNL lock */
	143	struct mutex qede_lock;
	144	u32 state; /* Protected by qede_lock */
2950219d	145	u16 rx_buf_size;
3d789994 MC	146	u32 rx_copybreak;
3d789994 MC	147
2950219d YM	148	/* L2 header size + 2VLANs (8 bytes) + LLC SNAP (8 bytes) /
	149	#define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
	150	/* Max supported alignment is 256 (8 shift)
	151	* minimal alignment shift 6 is optimal for 57xxx HW performance
	152	*/
	153	#define QEDE_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))
	154	/* We assume skb_build() uses sizeof(struct skb_shared_info) bytes
	155	* at the end of skb->data, to avoid wasting a full cache line.
	156	* This reduces memory use (skb->truesize).
	157	*/
	158	#define QEDE_FW_RX_ALIGN_END \
	159	max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT, \
	160	SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
	161
133fac0e	162	struct qede_stats stats;
961acdea SRK	163	#define QEDE_RSS_INDIR_INITED BIT(0)
	164	#define QEDE_RSS_KEY_INITED BIT(1)
	165	#define QEDE_RSS_CAPS_INITED BIT(2)
	166	u32 rss_params_inited; /* bit-field to track initialized rss params */
2950219d YM	167	struct qed_update_vport_rss_params rss_params;
	168	u16 q_num_rx_buffers; /* Must be a power of two */
	169	u16 q_num_tx_buffers; /* Must be a power of two */
0d8e0aa0	170
55482edc	171	bool gro_disable;
7c1bfcad SRK	172	struct list_head vlan_list;
	173	u16 configured_vlans;
	174	u16 non_configured_vlans;
	175	bool accept_any_vlan;
0d8e0aa0 SK	176	struct delayed_work sp_task;
0d8e0aa0 SK	177	unsigned long sp_flags;
b18e170c	178	u16 vxlan_dst_port;
9a109dd0	179	u16 geneve_dst_port;
2950219d YM	180	};
	181
	182	enum QEDE_STATE {
	183	QEDE_STATE_CLOSED,
	184	QEDE_STATE_OPEN,
	185	};
	186
	187	#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
	188
	189	#define MAX_NUM_TC 8
	190	#define MAX_NUM_PRI 8
	191
	192	/* The driver supports the new build_skb() API:
	193	* RX ring buffer contains pointer to kmalloc() data only,
	194	* skb are built only after the frame was DMA-ed.
	195	*/
	196	struct sw_rx_data {
fc48b7a6 YM	197	struct page *data;
	198	dma_addr_t mapping;
	199	unsigned int page_offset;
2950219d YM	200	};
2950219d YM	201
55482edc MC	202	enum qede_agg_state {
	203	QEDE_AGG_STATE_NONE = 0,
	204	QEDE_AGG_STATE_START = 1,
	205	QEDE_AGG_STATE_ERROR = 2
	206	};
	207
	208	struct qede_agg_info {
	209	struct sw_rx_data replace_buf;
	210	dma_addr_t replace_buf_mapping;
	211	struct sw_rx_data start_buf;
	212	dma_addr_t start_buf_mapping;
	213	struct eth_fast_path_rx_tpa_start_cqe start_cqe;
	214	enum qede_agg_state agg_state;
	215	struct sk_buff *skb;
	216	int frag_id;
	217	u16 vlan_tag;
	218	};
	219
2950219d YM	220	struct qede_rx_queue {
	221	__le16 *hw_cons_ptr;
	222	struct sw_rx_data *sw_rx_ring;
	223	u16 sw_rx_cons;
	224	u16 sw_rx_prod;
	225	struct qed_chain rx_bd_ring;
	226	struct qed_chain rx_comp_ring;
	227	void __iomem *hw_rxq_prod_addr;
	228
55482edc MC	229	/* GRO */
	230	struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM];
	231
2950219d	232	int rx_buf_size;
fc48b7a6	233	unsigned int rx_buf_seg_size;
2950219d YM	234
	235	u16 num_rx_buffers;
	236	u16 rxq_id;
	237
	238	u64 rx_hw_errors;
	239	u64 rx_alloc_errors;
c72a6125	240	u64 rx_ip_frags;
2950219d YM	241	};
	242
	243	union db_prod {
	244	struct eth_db_data data;
	245	u32 raw;
	246	};
	247
	248	struct sw_tx_bd {
	249	struct sk_buff *skb;
	250	u8 flags;
	251	/* Set on the first BD descriptor when there is a split BD */
	252	#define QEDE_TSO_SPLIT_BD BIT(0)
	253	};
	254
	255	struct qede_tx_queue {
	256	int index; /* Queue index */
	257	__le16 *hw_cons_ptr;
	258	struct sw_tx_bd *sw_tx_ring;
	259	u16 sw_tx_cons;
	260	u16 sw_tx_prod;
	261	struct qed_chain tx_pbl;
	262	void __iomem *doorbell_addr;
	263	union db_prod tx_db;
	264
	265	u16 num_tx_buffers;
	266	};
	267
	268	#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr.hi), \
	269	le32_to_cpu((bd)->addr.lo))
	270	#define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len) \
	271	do { \
	272	(bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr)); \
	273	(bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr)); \
	274	(bd)->nbytes = cpu_to_le16(len); \
	275	} while (0)
	276	#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
	277
	278	struct qede_fastpath {
	279	struct qede_dev *edev;
	280	u8 rss_id;
	281	struct napi_struct napi;
	282	struct qed_sb_info *sb_info;
	283	struct qede_rx_queue *rxq;
	284	struct qede_tx_queue *txqs;
	285
	286	#define VEC_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
	287	char name[VEC_NAME_SIZE];
e712d52b YM	288	};
	289
	290	/* Debug print definitions */
	291	#define DP_NAME(edev) ((edev)->ndev->name)
	292
2950219d YM	293	#define XMIT_PLAIN 0
	294	#define XMIT_L4_CSUM BIT(0)
	295	#define XMIT_LSO BIT(1)
	296	#define XMIT_ENC BIT(2)
	297
	298	#define QEDE_CSUM_ERROR BIT(0)
	299	#define QEDE_CSUM_UNNECESSARY BIT(1)
14db81de	300	#define QEDE_TUNN_CSUM_UNNECESSARY BIT(2)
0d8e0aa0	301
b18e170c MC	302	#define QEDE_SP_RX_MODE 1
b18e170c MC	303	#define QEDE_SP_VXLAN_PORT_CONFIG 2
9a109dd0	304	#define QEDE_SP_GENEVE_PORT_CONFIG 3
0d8e0aa0 SK	305
	306	union qede_reload_args {
	307	u16 mtu;
	308	};
	309
489e45ae SRK	310	#ifdef CONFIG_DCB
	311	void qede_set_dcbnl_ops(struct net_device *ndev);
	312	#endif
133fac0e SK	313	void qede_config_debug(uint debug, u32 p_dp_module, u8 p_dp_level);
	314	void qede_set_ethtool_ops(struct net_device *netdev);
	315	void qede_reload(struct qede_dev *edev,
	316	void (func)(struct qede_dev edev,
	317	union qede_reload_args *args),
	318	union qede_reload_args *args);
	319	int qede_change_mtu(struct net_device *dev, int new_mtu);
	320	void qede_fill_by_demand_stats(struct qede_dev *edev);
16f46bf0 SRK	321	bool qede_has_rx_work(struct qede_rx_queue *rxq);
	322	int qede_txq_has_work(struct qede_tx_queue *txq);
	323	void qede_recycle_rx_bd_ring(struct qede_rx_queue rxq, struct qede_dev edev,
	324	u8 count);
133fac0e	325
2950219d	326	#define RX_RING_SIZE_POW 13
01ef7e05	327	#define RX_RING_SIZE ((u16)BIT(RX_RING_SIZE_POW))
2950219d YM	328	#define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
	329	#define NUM_RX_BDS_MIN 128
	330	#define NUM_RX_BDS_DEF NUM_RX_BDS_MAX
	331
	332	#define TX_RING_SIZE_POW 13
01ef7e05	333	#define TX_RING_SIZE ((u16)BIT(TX_RING_SIZE_POW))
2950219d YM	334	#define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
	335	#define NUM_TX_BDS_MIN 128
	336	#define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
	337
3d789994	338	#define QEDE_MIN_PKT_LEN 64
fc48b7a6	339	#define QEDE_RX_HDR_SIZE 256
2950219d YM	340	#define for_each_rss(i) for (i = 0; i < edev->num_rss; i++)
2950219d YM	341
e712d52b	342	#endif /* _QEDE_H_ */