[deliverable/linux.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_minidump.c

#include "qlcnic.h"
#include "qlcnic_hdr.h"

#include <net/ip.h>

#define QLCNIC_DUMP_WCRB	BIT_0
#define QLCNIC_DUMP_RWCRB	BIT_1
#define QLCNIC_DUMP_ANDCRB	BIT_2
#define QLCNIC_DUMP_ORCRB	BIT_3
#define QLCNIC_DUMP_POLLCRB	BIT_4
#define QLCNIC_DUMP_RD_SAVE	BIT_5
#define QLCNIC_DUMP_WRT_SAVED	BIT_6
#define QLCNIC_DUMP_MOD_SAVE_ST	BIT_7
#define QLCNIC_DUMP_SKIP	BIT_7

#define QLCNIC_DUMP_MASK_MAX	0xff

struct qlcnic_common_entry_hdr {
	u32     type;
	u32     offset;
	u32     cap_size;
	u8      mask;
	u8      rsvd[2];
	u8      flags;
} __packed;

struct __crb {
	u32	addr;
	u8	stride;
	u8	rsvd1[3];
	u32	data_size;
	u32	no_ops;
	u32	rsvd2[4];
} __packed;

struct __ctrl {
	u32	addr;
	u8	stride;
	u8	index_a;
	u16	timeout;
	u32	data_size;
	u32	no_ops;
	u8	opcode;
	u8	index_v;
	u8	shl_val;
	u8	shr_val;
	u32	val1;
	u32	val2;
	u32	val3;
} __packed;

struct __cache {
	u32	addr;
	u16	stride;
	u16	init_tag_val;
	u32	size;
	u32	no_ops;
	u32	ctrl_addr;
	u32	ctrl_val;
	u32	read_addr;
	u8	read_addr_stride;
	u8	read_addr_num;
	u8	rsvd1[2];
} __packed;

struct __ocm {
	u8	rsvd[8];
	u32	size;
	u32	no_ops;
	u8	rsvd1[8];
	u32	read_addr;
	u32	read_addr_stride;
} __packed;

struct __mem {
	u8	rsvd[24];
	u32	addr;
	u32	size;
} __packed;

struct __mux {
	u32	addr;
	u8	rsvd[4];
	u32	size;
	u32	no_ops;
	u32	val;
	u32	val_stride;
	u32	read_addr;
	u8	rsvd2[4];
} __packed;

struct __queue {
	u32	sel_addr;
	u16	stride;
	u8	rsvd[2];
	u32	size;
	u32	no_ops;
	u8	rsvd2[8];
	u32	read_addr;
	u8	read_addr_stride;
	u8	read_addr_cnt;
	u8	rsvd3[2];
} __packed;

struct qlcnic_dump_entry {
	struct qlcnic_common_entry_hdr hdr;
	union {
		struct __crb	crb;
		struct __cache	cache;
		struct __ocm	ocm;
		struct __mem	mem;
		struct __mux	mux;
		struct __queue	que;
		struct __ctrl	ctrl;
	} region;
} __packed;

enum op_codes {
	QLCNIC_DUMP_NOP		= 0,
	QLCNIC_DUMP_READ_CRB	= 1,
	QLCNIC_DUMP_READ_MUX	= 2,
	QLCNIC_DUMP_QUEUE	= 3,
	QLCNIC_DUMP_BRD_CONFIG	= 4,
	QLCNIC_DUMP_READ_OCM	= 6,
	QLCNIC_DUMP_PEG_REG	= 7,
	QLCNIC_DUMP_L1_DTAG	= 8,
	QLCNIC_DUMP_L1_ITAG	= 9,
	QLCNIC_DUMP_L1_DATA	= 11,
	QLCNIC_DUMP_L1_INST	= 12,
	QLCNIC_DUMP_L2_DTAG	= 21,
	QLCNIC_DUMP_L2_ITAG	= 22,
	QLCNIC_DUMP_L2_DATA	= 23,
	QLCNIC_DUMP_L2_INST	= 24,
	QLCNIC_DUMP_READ_ROM	= 71,
	QLCNIC_DUMP_READ_MEM	= 72,
	QLCNIC_DUMP_READ_CTRL	= 98,
	QLCNIC_DUMP_TLHDR	= 99,
	QLCNIC_DUMP_RDEND	= 255
};

struct qlcnic_dump_operations {
	enum op_codes opcode;
	u32 (*handler)(struct qlcnic_adapter *, struct qlcnic_dump_entry *,
		       __le32 *);
};

static void qlcnic_read_dump_reg(u32 addr, void __iomem *bar0, u32 *data)
{
	u32 dest;
	void __iomem *window_reg;

	dest = addr & 0xFFFF0000;
	window_reg = bar0 + QLCNIC_FW_DUMP_REG1;
	writel(dest, window_reg);
	readl(window_reg);
	window_reg = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
	*data = readl(window_reg);
}

static void qlcnic_write_dump_reg(u32 addr, void __iomem *bar0, u32 data)
{
	u32 dest;
	void __iomem *window_reg;

	dest = addr & 0xFFFF0000;
	window_reg = bar0 + QLCNIC_FW_DUMP_REG1;
	writel(dest, window_reg);
	readl(window_reg);
	window_reg = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
	writel(data, window_reg);
	readl(window_reg);
}

/* FW dump related functions */
static u32 qlcnic_dump_crb(struct qlcnic_adapter *adapter,
			   struct qlcnic_dump_entry *entry, __le32 *buffer)
{
	int i;
	u32 addr, data;
	struct __crb *crb = &entry->region.crb;
	void __iomem *base = adapter->ahw->pci_base0;

	addr = crb->addr;

	for (i = 0; i < crb->no_ops; i++) {
		qlcnic_read_dump_reg(addr, base, &data);
		*buffer++ = cpu_to_le32(addr);
		*buffer++ = cpu_to_le32(data);
		addr += crb->stride;
	}
	return crb->no_ops * 2 * sizeof(u32);
}

static u32 qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
			    struct qlcnic_dump_entry *entry, __le32 *buffer)
{
	int i, k, timeout = 0;
	void __iomem *base = adapter->ahw->pci_base0;
	u32 addr, data;
	u8 opcode, no_ops;
	struct __ctrl *ctr = &entry->region.ctrl;
	struct qlcnic_dump_template_hdr *t_hdr = adapter->ahw->fw_dump.tmpl_hdr;

	addr = ctr->addr;
	no_ops = ctr->no_ops;

	for (i = 0; i < no_ops; i++) {
		k = 0;
		opcode = 0;
		for (k = 0; k < 8; k++) {
			if (!(ctr->opcode & (1 << k)))
				continue;
			switch (1 << k) {
			case QLCNIC_DUMP_WCRB:
				qlcnic_write_dump_reg(addr, base, ctr->val1);
				break;
			case QLCNIC_DUMP_RWCRB:
				qlcnic_read_dump_reg(addr, base, &data);
				qlcnic_write_dump_reg(addr, base, data);
				break;
			case QLCNIC_DUMP_ANDCRB:
				qlcnic_read_dump_reg(addr, base, &data);
				qlcnic_write_dump_reg(addr, base,
						      data & ctr->val2);
				break;
			case QLCNIC_DUMP_ORCRB:
				qlcnic_read_dump_reg(addr, base, &data);
				qlcnic_write_dump_reg(addr, base,
						      data | ctr->val3);
				break;
			case QLCNIC_DUMP_POLLCRB:
				while (timeout <= ctr->timeout) {
					qlcnic_read_dump_reg(addr, base, &data);
					if ((data & ctr->val2) == ctr->val1)
						break;
					msleep(1);
					timeout++;
				}
				if (timeout > ctr->timeout) {
					dev_info(&adapter->pdev->dev,
					"Timed out, aborting poll CRB\n");
					return -EINVAL;
				}
				break;
			case QLCNIC_DUMP_RD_SAVE:
				if (ctr->index_a)
					addr = t_hdr->saved_state[ctr->index_a];
				qlcnic_read_dump_reg(addr, base, &data);
				t_hdr->saved_state[ctr->index_v] = data;
				break;
			case QLCNIC_DUMP_WRT_SAVED:
				if (ctr->index_v)
					data = t_hdr->saved_state[ctr->index_v];
				else
					data = ctr->val1;
				if (ctr->index_a)
					addr = t_hdr->saved_state[ctr->index_a];
				qlcnic_write_dump_reg(addr, base, data);
				break;
			case QLCNIC_DUMP_MOD_SAVE_ST:
				data = t_hdr->saved_state[ctr->index_v];
				data <<= ctr->shl_val;
				data >>= ctr->shr_val;
				if (ctr->val2)
					data &= ctr->val2;
				data |= ctr->val3;
				data += ctr->val1;
				t_hdr->saved_state[ctr->index_v] = data;
				break;
			default:
				dev_info(&adapter->pdev->dev,
					"Unknown opcode\n");
				break;
			}
		}
		addr += ctr->stride;
	}
	return 0;
}

static u32 qlcnic_dump_mux(struct qlcnic_adapter *adapter,
			   struct qlcnic_dump_entry *entry, __le32 *buffer)
{
	int loop;
	u32 val, data = 0;
	struct __mux *mux = &entry->region.mux;
	void __iomem *base = adapter->ahw->pci_base0;

	val = mux->val;
	for (loop = 0; loop < mux->no_ops; loop++) {
		qlcnic_write_dump_reg(mux->addr, base, val);
		qlcnic_read_dump_reg(mux->read_addr, base, &data);
		*buffer++ = cpu_to_le32(val);
		*buffer++ = cpu_to_le32(data);
		val += mux->val_stride;
	}
	return 2 * mux->no_ops * sizeof(u32);
}

static u32 qlcnic_dump_que(struct qlcnic_adapter *adapter,
			   struct qlcnic_dump_entry *entry, __le32 *buffer)
{
	int i, loop;
	u32 cnt, addr, data, que_id = 0;
	void __iomem *base = adapter->ahw->pci_base0;
	struct __queue *que = &entry->region.que;

	addr = que->read_addr;
	cnt = que->read_addr_cnt;

	for (loop = 0; loop < que->no_ops; loop++) {
		qlcnic_write_dump_reg(que->sel_addr, base, que_id);
		addr = que->read_addr;
		for (i = 0; i < cnt; i++) {
			qlcnic_read_dump_reg(addr, base, &data);
			*buffer++ = cpu_to_le32(data);
			addr += que->read_addr_stride;
		}
		que_id += que->stride;
	}
	return que->no_ops * cnt * sizeof(u32);
}

static u32 qlcnic_dump_ocm(struct qlcnic_adapter *adapter,
			   struct qlcnic_dump_entry *entry, __le32 *buffer)
{
	int i;
	u32 data;
	void __iomem *addr;
	struct __ocm *ocm = &entry->region.ocm;

	addr = adapter->ahw->pci_base0 + ocm->read_addr;
	for (i = 0; i < ocm->no_ops; i++) {
		data = readl(addr);
		*buffer++ = cpu_to_le32(data);
		addr += ocm->read_addr_stride;
	}
	return ocm->no_ops * sizeof(u32);
}

static u32 qlcnic_read_rom(struct qlcnic_adapter *adapter,
			   struct qlcnic_dump_entry *entry, __le32 *buffer)
{
	int i, count = 0;
	u32 fl_addr, size, val, lck_val, addr;
	struct __mem *rom = &entry->region.mem;
	void __iomem *base = adapter->ahw->pci_base0;

	fl_addr = rom->addr;
	size = rom->size/4;
lock_try:
	lck_val = readl(base + QLCNIC_FLASH_SEM2_LK);
	if (!lck_val && count < MAX_CTL_CHECK) {
		msleep(10);
		count++;
		goto lock_try;
	}
	writel(adapter->ahw->pci_func, (base + QLCNIC_FLASH_LOCK_ID));
	for (i = 0; i < size; i++) {
		addr = fl_addr & 0xFFFF0000;
		qlcnic_write_dump_reg(FLASH_ROM_WINDOW, base, addr);
		addr = LSW(fl_addr) + FLASH_ROM_DATA;
		qlcnic_read_dump_reg(addr, base, &val);
		fl_addr += 4;
		*buffer++ = cpu_to_le32(val);
	}
	readl(base + QLCNIC_FLASH_SEM2_ULK);
	return rom->size;
}

static u32 qlcnic_dump_l1_cache(struct qlcnic_adapter *adapter,
				struct qlcnic_dump_entry *entry, __le32 *buffer)
{
	int i;
	u32 cnt, val, data, addr;
	void __iomem *base = adapter->ahw->pci_base0;
	struct __cache *l1 = &entry->region.cache;

	val = l1->init_tag_val;

	for (i = 0; i < l1->no_ops; i++) {
		qlcnic_write_dump_reg(l1->addr, base, val);
		qlcnic_write_dump_reg(l1->ctrl_addr, base, LSW(l1->ctrl_val));
		addr = l1->read_addr;
		cnt = l1->read_addr_num;
		while (cnt) {
			qlcnic_read_dump_reg(addr, base, &data);
			*buffer++ = cpu_to_le32(data);
			addr += l1->read_addr_stride;
			cnt--;
		}
		val += l1->stride;
	}
	return l1->no_ops * l1->read_addr_num * sizeof(u32);
}

static u32 qlcnic_dump_l2_cache(struct qlcnic_adapter *adapter,
				struct qlcnic_dump_entry *entry, __le32 *buffer)
{
	int i;
	u32 cnt, val, data, addr;
	u8 poll_mask, poll_to, time_out = 0;
	void __iomem *base = adapter->ahw->pci_base0;
	struct __cache *l2 = &entry->region.cache;

	val = l2->init_tag_val;
	poll_mask = LSB(MSW(l2->ctrl_val));
	poll_to = MSB(MSW(l2->ctrl_val));

	for (i = 0; i < l2->no_ops; i++) {
		qlcnic_write_dump_reg(l2->addr, base, val);
		if (LSW(l2->ctrl_val))
			qlcnic_write_dump_reg(l2->ctrl_addr, base,
					      LSW(l2->ctrl_val));
		if (!poll_mask)
			goto skip_poll;
		do {
			qlcnic_read_dump_reg(l2->ctrl_addr, base, &data);
			if (!(data & poll_mask))
				break;
			msleep(1);
			time_out++;
		} while (time_out <= poll_to);

		if (time_out > poll_to) {
			dev_err(&adapter->pdev->dev,
				"Timeout exceeded in %s, aborting dump\n",
				__func__);
			return -EINVAL;
		}
skip_poll:
		addr = l2->read_addr;
		cnt = l2->read_addr_num;
		while (cnt) {
			qlcnic_read_dump_reg(addr, base, &data);
			*buffer++ = cpu_to_le32(data);
			addr += l2->read_addr_stride;
			cnt--;
		}
		val += l2->stride;
	}
	return l2->no_ops * l2->read_addr_num * sizeof(u32);
}

static u32 qlcnic_read_memory(struct qlcnic_adapter *adapter,
			      struct qlcnic_dump_entry *entry, __le32 *buffer)
{
	u32 addr, data, test, ret = 0;
	int i, reg_read;
	struct __mem *mem = &entry->region.mem;
	void __iomem *base = adapter->ahw->pci_base0;

	reg_read = mem->size;
	addr = mem->addr;
	/* check for data size of multiple of 16 and 16 byte alignment */
	if ((addr & 0xf) || (reg_read%16)) {
		dev_info(&adapter->pdev->dev,
			"Unaligned memory addr:0x%x size:0x%x\n",
			addr, reg_read);
		return -EINVAL;
	}

	mutex_lock(&adapter->ahw->mem_lock);

	while (reg_read != 0) {
		qlcnic_write_dump_reg(MIU_TEST_ADDR_LO, base, addr);
		qlcnic_write_dump_reg(MIU_TEST_ADDR_HI, base, 0);
		qlcnic_write_dump_reg(MIU_TEST_CTR, base,
				      TA_CTL_ENABLE | TA_CTL_START);

		for (i = 0; i < MAX_CTL_CHECK; i++) {
			qlcnic_read_dump_reg(MIU_TEST_CTR, base, &test);
			if (!(test & TA_CTL_BUSY))
				break;
		}
		if (i == MAX_CTL_CHECK) {
			if (printk_ratelimit()) {
				dev_err(&adapter->pdev->dev,
					"failed to read through agent\n");
				ret = -EINVAL;
				goto out;
			}
		}
		for (i = 0; i < 4; i++) {
			qlcnic_read_dump_reg(MIU_TEST_READ_DATA[i], base,
					     &data);
			*buffer++ = cpu_to_le32(data);
		}
		addr += 16;
		reg_read -= 16;
		ret += 16;
	}
out:
	mutex_unlock(&adapter->ahw->mem_lock);
	return mem->size;
}

static u32 qlcnic_dump_nop(struct qlcnic_adapter *adapter,
			   struct qlcnic_dump_entry *entry, __le32 *buffer)
{
	entry->hdr.flags |= QLCNIC_DUMP_SKIP;
	return 0;
}

static const struct qlcnic_dump_operations fw_dump_ops[] = {
	{ QLCNIC_DUMP_NOP, qlcnic_dump_nop },
	{ QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb },
	{ QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux },
	{ QLCNIC_DUMP_QUEUE, qlcnic_dump_que },
	{ QLCNIC_DUMP_BRD_CONFIG, qlcnic_read_rom },
	{ QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm },
	{ QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl },
	{ QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache },
	{ QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache },
	{ QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache },
	{ QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache },
	{ QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache },
	{ QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache },
	{ QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache },
	{ QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache },
	{ QLCNIC_DUMP_READ_ROM, qlcnic_read_rom },
	{ QLCNIC_DUMP_READ_MEM, qlcnic_read_memory },
	{ QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl },
	{ QLCNIC_DUMP_TLHDR, qlcnic_dump_nop },
	{ QLCNIC_DUMP_RDEND, qlcnic_dump_nop },
};

/* Walk the template and collect dump for each entry in the dump template */
static int
qlcnic_valid_dump_entry(struct device *dev, struct qlcnic_dump_entry *entry,
	u32 size)
{
	int ret = 1;
	if (size != entry->hdr.cap_size) {
		dev_info(dev,
		"Invalidate dump, Type:%d\tMask:%d\tSize:%dCap_size:%d\n",
		entry->hdr.type, entry->hdr.mask, size, entry->hdr.cap_size);
		dev_info(dev, "Aborting further dump capture\n");
		ret = 0;
	}
	return ret;
}

int qlcnic_dump_fw(struct qlcnic_adapter *adapter)
{
	__le32 *buffer;
	char mesg[64];
	char *msg[] = {mesg, NULL};
	int i, k, ops_cnt, ops_index, dump_size = 0;
	u32 entry_offset, dump, no_entries, buf_offset = 0;
	struct qlcnic_dump_entry *entry;
	struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
	struct qlcnic_dump_template_hdr *tmpl_hdr = fw_dump->tmpl_hdr;

	if (fw_dump->clr) {
		dev_info(&adapter->pdev->dev,
			"Previous dump not cleared, not capturing dump\n");
		return -EIO;
	}
	/* Calculate the size for dump data area only */
	for (i = 2, k = 1; (i & QLCNIC_DUMP_MASK_MAX); i <<= 1, k++)
		if (i & tmpl_hdr->drv_cap_mask)
			dump_size += tmpl_hdr->cap_sizes[k];
	if (!dump_size)
		return -EIO;

	fw_dump->data = vzalloc(dump_size);
	if (!fw_dump->data) {
		dev_info(&adapter->pdev->dev,
			"Unable to allocate (%d KB) for fw dump\n",
			dump_size/1024);
		return -ENOMEM;
	}
	buffer = fw_dump->data;
	fw_dump->size = dump_size;
	no_entries = tmpl_hdr->num_entries;
	ops_cnt = ARRAY_SIZE(fw_dump_ops);
	entry_offset = tmpl_hdr->offset;
	tmpl_hdr->sys_info[0] = QLCNIC_DRIVER_VERSION;
	tmpl_hdr->sys_info[1] = adapter->fw_version;

	for (i = 0; i < no_entries; i++) {
		entry = (void *)tmpl_hdr + entry_offset;
		if (!(entry->hdr.mask & tmpl_hdr->drv_cap_mask)) {
			entry->hdr.flags |= QLCNIC_DUMP_SKIP;
			entry_offset += entry->hdr.offset;
			continue;
		}
		/* Find the handler for this entry */
		ops_index = 0;
		while (ops_index < ops_cnt) {
			if (entry->hdr.type == fw_dump_ops[ops_index].opcode)
				break;
			ops_index++;
		}
		if (ops_index == ops_cnt) {
			dev_info(&adapter->pdev->dev,
				"Invalid entry type %d, exiting dump\n",
				entry->hdr.type);
			goto error;
		}
		/* Collect dump for this entry */
		dump = fw_dump_ops[ops_index].handler(adapter, entry, buffer);
		if (dump && !qlcnic_valid_dump_entry(&adapter->pdev->dev, entry,
			dump))
			entry->hdr.flags |= QLCNIC_DUMP_SKIP;
		buf_offset += entry->hdr.cap_size;
		entry_offset += entry->hdr.offset;
		buffer = fw_dump->data + buf_offset;
	}
	if (dump_size != buf_offset) {
		dev_info(&adapter->pdev->dev,
			"Captured(%d) and expected size(%d) do not match\n",
			buf_offset, dump_size);
		goto error;
	} else {
		fw_dump->clr = 1;
		snprintf(mesg, sizeof(mesg), "FW_DUMP=%s",
			adapter->netdev->name);
		dev_info(&adapter->pdev->dev, "Dump data, %d bytes captured\n",
			fw_dump->size);
		/* Send a udev event to notify availability of FW dump */
		kobject_uevent_env(&adapter->pdev->dev.kobj, KOBJ_CHANGE, msg);
		return 0;
	}
error:
	vfree(fw_dump->data);
	return -EINVAL;
}
Commit	Line	Data
58634e74 SC	1	#include "qlcnic.h"
	2	#include "qlcnic_hdr.h"
	3
	4	#include <net/ip.h>
	5
	6	#define QLCNIC_DUMP_WCRB BIT_0
	7	#define QLCNIC_DUMP_RWCRB BIT_1
	8	#define QLCNIC_DUMP_ANDCRB BIT_2
	9	#define QLCNIC_DUMP_ORCRB BIT_3
	10	#define QLCNIC_DUMP_POLLCRB BIT_4
	11	#define QLCNIC_DUMP_RD_SAVE BIT_5
	12	#define QLCNIC_DUMP_WRT_SAVED BIT_6
	13	#define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
	14	#define QLCNIC_DUMP_SKIP BIT_7
	15
	16	#define QLCNIC_DUMP_MASK_MAX 0xff
	17
	18	struct qlcnic_common_entry_hdr {
	19	u32 type;
	20	u32 offset;
	21	u32 cap_size;
	22	u8 mask;
	23	u8 rsvd[2];
	24	u8 flags;
	25	} __packed;
	26
	27	struct __crb {
	28	u32 addr;
	29	u8 stride;
	30	u8 rsvd1[3];
	31	u32 data_size;
	32	u32 no_ops;
	33	u32 rsvd2[4];
	34	} __packed;
	35
	36	struct __ctrl {
	37	u32 addr;
	38	u8 stride;
	39	u8 index_a;
	40	u16 timeout;
	41	u32 data_size;
	42	u32 no_ops;
	43	u8 opcode;
	44	u8 index_v;
	45	u8 shl_val;
	46	u8 shr_val;
	47	u32 val1;
	48	u32 val2;
	49	u32 val3;
	50	} __packed;
	51
	52	struct __cache {
	53	u32 addr;
	54	u16 stride;
	55	u16 init_tag_val;
	56	u32 size;
	57	u32 no_ops;
	58	u32 ctrl_addr;
	59	u32 ctrl_val;
	60	u32 read_addr;
	61	u8 read_addr_stride;
	62	u8 read_addr_num;
	63	u8 rsvd1[2];
	64	} __packed;
65
66	struct __ocm {
67	u8 rsvd[8];
68	u32 size;
69	u32 no_ops;
70	u8 rsvd1[8];
71	u32 read_addr;
72	u32 read_addr_stride;
73	} __packed;
74
75	struct __mem {
76	u8 rsvd[24];
77	u32 addr;
78	u32 size;
79	} __packed;
80
81	struct __mux {
82	u32 addr;
83	u8 rsvd[4];
84	u32 size;
85	u32 no_ops;
86	u32 val;
87	u32 val_stride;
88	u32 read_addr;
89	u8 rsvd2[4];
90	} __packed;
91
92	struct __queue {
93	u32 sel_addr;
94	u16 stride;
95	u8 rsvd[2];
96	u32 size;
97	u32 no_ops;
98	u8 rsvd2[8];
99	u32 read_addr;
100	u8 read_addr_stride;
101	u8 read_addr_cnt;
102	u8 rsvd3[2];
103	} __packed;
104
105	struct qlcnic_dump_entry {
106	struct qlcnic_common_entry_hdr hdr;
107	union {
108	struct __crb crb;
109	struct __cache cache;
110	struct __ocm ocm;
111	struct __mem mem;
112	struct __mux mux;
113	struct __queue que;
114	struct __ctrl ctrl;
115	} region;
116	} __packed;
117
118	enum op_codes {
119	QLCNIC_DUMP_NOP = 0,
120	QLCNIC_DUMP_READ_CRB = 1,
121	QLCNIC_DUMP_READ_MUX = 2,
122	QLCNIC_DUMP_QUEUE = 3,
123	QLCNIC_DUMP_BRD_CONFIG = 4,
124	QLCNIC_DUMP_READ_OCM = 6,
125	QLCNIC_DUMP_PEG_REG = 7,
126	QLCNIC_DUMP_L1_DTAG = 8,
127	QLCNIC_DUMP_L1_ITAG = 9,
128	QLCNIC_DUMP_L1_DATA = 11,
129	QLCNIC_DUMP_L1_INST = 12,
130	QLCNIC_DUMP_L2_DTAG = 21,
131	QLCNIC_DUMP_L2_ITAG = 22,
132	QLCNIC_DUMP_L2_DATA = 23,
133	QLCNIC_DUMP_L2_INST = 24,
134	QLCNIC_DUMP_READ_ROM = 71,
135	QLCNIC_DUMP_READ_MEM = 72,
136	QLCNIC_DUMP_READ_CTRL = 98,
137	QLCNIC_DUMP_TLHDR = 99,
138	QLCNIC_DUMP_RDEND = 255
139	};
140
141	struct qlcnic_dump_operations {
142	enum op_codes opcode;
143	u32 (handler)(struct qlcnic_adapter , struct qlcnic_dump_entry *,
144	__le32 *);
145	};
146
147	static void qlcnic_read_dump_reg(u32 addr, void __iomem bar0, u32 data)
148	{
149	u32 dest;
150	void __iomem *window_reg;
151
152	dest = addr & 0xFFFF0000;
153	window_reg = bar0 + QLCNIC_FW_DUMP_REG1;
154	writel(dest, window_reg);
155	readl(window_reg);
156	window_reg = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
157	*data = readl(window_reg);
158	}
159
160	static void qlcnic_write_dump_reg(u32 addr, void __iomem *bar0, u32 data)
161	{
162	u32 dest;
163	void __iomem *window_reg;
164
165	dest = addr & 0xFFFF0000;
166	window_reg = bar0 + QLCNIC_FW_DUMP_REG1;
167	writel(dest, window_reg);
168	readl(window_reg);
169	window_reg = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
170	writel(data, window_reg);
171	readl(window_reg);
172	}
173
174	/* FW dump related functions */
175	static u32 qlcnic_dump_crb(struct qlcnic_adapter *adapter,
176	struct qlcnic_dump_entry entry, __le32 buffer)
177	{
178	int i;
179	u32 addr, data;
180	struct __crb *crb = &entry->region.crb;
181	void __iomem *base = adapter->ahw->pci_base0;
182
183	addr = crb->addr;
184
185	for (i = 0; i < crb->no_ops; i++) {
186	qlcnic_read_dump_reg(addr, base, &data);
187	*buffer++ = cpu_to_le32(addr);
188	*buffer++ = cpu_to_le32(data);
189	addr += crb->stride;
190	}
191	return crb->no_ops * 2 * sizeof(u32);
192	}
193
194	static u32 qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
195	struct qlcnic_dump_entry entry, __le32 buffer)
196	{
197	int i, k, timeout = 0;
198	void __iomem *base = adapter->ahw->pci_base0;
199	u32 addr, data;
200	u8 opcode, no_ops;
201	struct __ctrl *ctr = &entry->region.ctrl;
202	struct qlcnic_dump_template_hdr *t_hdr = adapter->ahw->fw_dump.tmpl_hdr;
203
204	addr = ctr->addr;
205	no_ops = ctr->no_ops;
206
207	for (i = 0; i < no_ops; i++) {
208	k = 0;
209	opcode = 0;
210	for (k = 0; k < 8; k++) {
211	if (!(ctr->opcode & (1 << k)))
212	continue;
213	switch (1 << k) {
214	case QLCNIC_DUMP_WCRB:
215	qlcnic_write_dump_reg(addr, base, ctr->val1);
216	break;
217	case QLCNIC_DUMP_RWCRB:
218	qlcnic_read_dump_reg(addr, base, &data);
219	qlcnic_write_dump_reg(addr, base, data);
220	break;
221	case QLCNIC_DUMP_ANDCRB:
222	qlcnic_read_dump_reg(addr, base, &data);
223	qlcnic_write_dump_reg(addr, base,
224	data & ctr->val2);
225	break;
226	case QLCNIC_DUMP_ORCRB:
227	qlcnic_read_dump_reg(addr, base, &data);
228	qlcnic_write_dump_reg(addr, base,
229	data \| ctr->val3);
230	break;
231	case QLCNIC_DUMP_POLLCRB:
232	while (timeout <= ctr->timeout) {
233	qlcnic_read_dump_reg(addr, base, &data);
234	if ((data & ctr->val2) == ctr->val1)
235	break;
236	msleep(1);
237	timeout++;
238	}
239	if (timeout > ctr->timeout) {
240	dev_info(&adapter->pdev->dev,
241	"Timed out, aborting poll CRB\n");
242	return -EINVAL;
243	}
244	break;
245	case QLCNIC_DUMP_RD_SAVE:
246	if (ctr->index_a)
247	addr = t_hdr->saved_state[ctr->index_a];
248	qlcnic_read_dump_reg(addr, base, &data);
249	t_hdr->saved_state[ctr->index_v] = data;
250	break;
251	case QLCNIC_DUMP_WRT_SAVED:
252	if (ctr->index_v)
253	data = t_hdr->saved_state[ctr->index_v];
254	else
255	data = ctr->val1;
256	if (ctr->index_a)
257	addr = t_hdr->saved_state[ctr->index_a];
258	qlcnic_write_dump_reg(addr, base, data);
259	break;
260	case QLCNIC_DUMP_MOD_SAVE_ST:
261	data = t_hdr->saved_state[ctr->index_v];
262	data <<= ctr->shl_val;
263	data >>= ctr->shr_val;
264	if (ctr->val2)
265	data &= ctr->val2;
266	data \|= ctr->val3;
267	data += ctr->val1;
268	t_hdr->saved_state[ctr->index_v] = data;
269	break;
270	default:
271	dev_info(&adapter->pdev->dev,
272	"Unknown opcode\n");
273	break;
274	}
275	}
276	addr += ctr->stride;
277	}
278	return 0;
279	}
280
281	static u32 qlcnic_dump_mux(struct qlcnic_adapter *adapter,
282	struct qlcnic_dump_entry entry, __le32 buffer)
283	{
284	int loop;
285	u32 val, data = 0;
286	struct __mux *mux = &entry->region.mux;
287	void __iomem *base = adapter->ahw->pci_base0;
288
289	val = mux->val;
290	for (loop = 0; loop < mux->no_ops; loop++) {
291	qlcnic_write_dump_reg(mux->addr, base, val);
292	qlcnic_read_dump_reg(mux->read_addr, base, &data);
293	*buffer++ = cpu_to_le32(val);
294	*buffer++ = cpu_to_le32(data);
295	val += mux->val_stride;
296	}
297	return 2 * mux->no_ops * sizeof(u32);
298	}
299
300	static u32 qlcnic_dump_que(struct qlcnic_adapter *adapter,
301	struct qlcnic_dump_entry entry, __le32 buffer)
302	{
303	int i, loop;
304	u32 cnt, addr, data, que_id = 0;
305	void __iomem *base = adapter->ahw->pci_base0;
306	struct __queue *que = &entry->region.que;
307
308	addr = que->read_addr;
309	cnt = que->read_addr_cnt;
310
311	for (loop = 0; loop < que->no_ops; loop++) {
312	qlcnic_write_dump_reg(que->sel_addr, base, que_id);
313	addr = que->read_addr;
314	for (i = 0; i < cnt; i++) {
315	qlcnic_read_dump_reg(addr, base, &data);
316	*buffer++ = cpu_to_le32(data);
317	addr += que->read_addr_stride;
318	}
319	que_id += que->stride;
320	}
321	return que->no_ops * cnt * sizeof(u32);
322	}
323
324	static u32 qlcnic_dump_ocm(struct qlcnic_adapter *adapter,
325	struct qlcnic_dump_entry entry, __le32 buffer)
326	{
327	int i;
328	u32 data;
329	void __iomem *addr;
330	struct __ocm *ocm = &entry->region.ocm;
331
332	addr = adapter->ahw->pci_base0 + ocm->read_addr;
333	for (i = 0; i < ocm->no_ops; i++) {
334	data = readl(addr);
335	*buffer++ = cpu_to_le32(data);
336	addr += ocm->read_addr_stride;
337	}
338	return ocm->no_ops * sizeof(u32);
339	}
340
341	static u32 qlcnic_read_rom(struct qlcnic_adapter *adapter,
342	struct qlcnic_dump_entry entry, __le32 buffer)
343	{
344	int i, count = 0;
345	u32 fl_addr, size, val, lck_val, addr;
346	struct __mem *rom = &entry->region.mem;
347	void __iomem *base = adapter->ahw->pci_base0;
348
349	fl_addr = rom->addr;
350	size = rom->size/4;
351	lock_try:
352	lck_val = readl(base + QLCNIC_FLASH_SEM2_LK);
353	if (!lck_val && count < MAX_CTL_CHECK) {
354	msleep(10);
355	count++;
356	goto lock_try;
357	}
358	writel(adapter->ahw->pci_func, (base + QLCNIC_FLASH_LOCK_ID));
359	for (i = 0; i < size; i++) {
360	addr = fl_addr & 0xFFFF0000;
361	qlcnic_write_dump_reg(FLASH_ROM_WINDOW, base, addr);
362	addr = LSW(fl_addr) + FLASH_ROM_DATA;
363	qlcnic_read_dump_reg(addr, base, &val);
364	fl_addr += 4;
365	*buffer++ = cpu_to_le32(val);
366	}
367	readl(base + QLCNIC_FLASH_SEM2_ULK);
368	return rom->size;
369	}
370
371	static u32 qlcnic_dump_l1_cache(struct qlcnic_adapter *adapter,
372	struct qlcnic_dump_entry entry, __le32 buffer)
373	{
374	int i;
375	u32 cnt, val, data, addr;
376	void __iomem *base = adapter->ahw->pci_base0;
377	struct __cache *l1 = &entry->region.cache;
378
379	val = l1->init_tag_val;
380
381	for (i = 0; i < l1->no_ops; i++) {
382	qlcnic_write_dump_reg(l1->addr, base, val);
383	qlcnic_write_dump_reg(l1->ctrl_addr, base, LSW(l1->ctrl_val));
384	addr = l1->read_addr;
385	cnt = l1->read_addr_num;
386	while (cnt) {
387	qlcnic_read_dump_reg(addr, base, &data);
388	*buffer++ = cpu_to_le32(data);
389	addr += l1->read_addr_stride;
390	cnt--;
391	}
392	val += l1->stride;
393	}
394	return l1->no_ops * l1->read_addr_num * sizeof(u32);
395	}
396
397	static u32 qlcnic_dump_l2_cache(struct qlcnic_adapter *adapter,
398	struct qlcnic_dump_entry entry, __le32 buffer)
399	{
400	int i;
401	u32 cnt, val, data, addr;
402	u8 poll_mask, poll_to, time_out = 0;
403	void __iomem *base = adapter->ahw->pci_base0;
404	struct __cache *l2 = &entry->region.cache;
405
406	val = l2->init_tag_val;
407	poll_mask = LSB(MSW(l2->ctrl_val));
408	poll_to = MSB(MSW(l2->ctrl_val));
409
410	for (i = 0; i < l2->no_ops; i++) {
411	qlcnic_write_dump_reg(l2->addr, base, val);
412	if (LSW(l2->ctrl_val))
413	qlcnic_write_dump_reg(l2->ctrl_addr, base,
414	LSW(l2->ctrl_val));
415	if (!poll_mask)
416	goto skip_poll;
417	do {
418	qlcnic_read_dump_reg(l2->ctrl_addr, base, &data);
419	if (!(data & poll_mask))
420	break;
421	msleep(1);
422	time_out++;
423	} while (time_out <= poll_to);
424
425	if (time_out > poll_to) {
426	dev_err(&adapter->pdev->dev,
427	"Timeout exceeded in %s, aborting dump\n",
428	__func__);
429	return -EINVAL;
430	}
431	skip_poll:
432	addr = l2->read_addr;
433	cnt = l2->read_addr_num;
434	while (cnt) {
435	qlcnic_read_dump_reg(addr, base, &data);
436	*buffer++ = cpu_to_le32(data);
437	addr += l2->read_addr_stride;
438	cnt--;
439	}
440	val += l2->stride;
441	}
442	return l2->no_ops * l2->read_addr_num * sizeof(u32);
443	}
444
445	static u32 qlcnic_read_memory(struct qlcnic_adapter *adapter,
446	struct qlcnic_dump_entry entry, __le32 buffer)
447	{
448	u32 addr, data, test, ret = 0;
449	int i, reg_read;
450	struct __mem *mem = &entry->region.mem;
451	void __iomem *base = adapter->ahw->pci_base0;
452
453	reg_read = mem->size;
454	addr = mem->addr;
455	/* check for data size of multiple of 16 and 16 byte alignment */
456	if ((addr & 0xf) \|\| (reg_read%16)) {
457	dev_info(&adapter->pdev->dev,
458	"Unaligned memory addr:0x%x size:0x%x\n",
459	addr, reg_read);
460	return -EINVAL;
461	}
462
463	mutex_lock(&adapter->ahw->mem_lock);
464
465	while (reg_read != 0) {
466	qlcnic_write_dump_reg(MIU_TEST_ADDR_LO, base, addr);
467	qlcnic_write_dump_reg(MIU_TEST_ADDR_HI, base, 0);
468	qlcnic_write_dump_reg(MIU_TEST_CTR, base,
469	TA_CTL_ENABLE \| TA_CTL_START);
470
471	for (i = 0; i < MAX_CTL_CHECK; i++) {
472	qlcnic_read_dump_reg(MIU_TEST_CTR, base, &test);
473	if (!(test & TA_CTL_BUSY))
474	break;
475	}
476	if (i == MAX_CTL_CHECK) {
477	if (printk_ratelimit()) {
478	dev_err(&adapter->pdev->dev,
479	"failed to read through agent\n");
480	ret = -EINVAL;
481	goto out;
482	}
483	}
484	for (i = 0; i < 4; i++) {
485	qlcnic_read_dump_reg(MIU_TEST_READ_DATA[i], base,
486	&data);
487	*buffer++ = cpu_to_le32(data);
488	}
489	addr += 16;
490	reg_read -= 16;
491	ret += 16;
492	}
493	out:
494	mutex_unlock(&adapter->ahw->mem_lock);
495	return mem->size;
496	}
497
498	static u32 qlcnic_dump_nop(struct qlcnic_adapter *adapter,
499	struct qlcnic_dump_entry entry, __le32 buffer)
500	{
501	entry->hdr.flags \|= QLCNIC_DUMP_SKIP;
502	return 0;
503	}
504
505	static const struct qlcnic_dump_operations fw_dump_ops[] = {
506	{ QLCNIC_DUMP_NOP, qlcnic_dump_nop },
507	{ QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb },
508	{ QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux },
509	{ QLCNIC_DUMP_QUEUE, qlcnic_dump_que },
510	{ QLCNIC_DUMP_BRD_CONFIG, qlcnic_read_rom },
511	{ QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm },
512	{ QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl },
513	{ QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache },
514	{ QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache },
515	{ QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache },
516	{ QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache },
517	{ QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache },
518	{ QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache },
519	{ QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache },
520	{ QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache },
521	{ QLCNIC_DUMP_READ_ROM, qlcnic_read_rom },
522	{ QLCNIC_DUMP_READ_MEM, qlcnic_read_memory },
523	{ QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl },
524	{ QLCNIC_DUMP_TLHDR, qlcnic_dump_nop },
525	{ QLCNIC_DUMP_RDEND, qlcnic_dump_nop },
526	};
527
528	/* Walk the template and collect dump for each entry in the dump template */
529	static int
530	qlcnic_valid_dump_entry(struct device dev, struct qlcnic_dump_entry entry,
531	u32 size)
532	{
533	int ret = 1;
534	if (size != entry->hdr.cap_size) {
535	dev_info(dev,
536	"Invalidate dump, Type:%d\tMask:%d\tSize:%dCap_size:%d\n",
537	entry->hdr.type, entry->hdr.mask, size, entry->hdr.cap_size);
538	dev_info(dev, "Aborting further dump capture\n");
539	ret = 0;
540	}
541	return ret;
542	}
543
544	int qlcnic_dump_fw(struct qlcnic_adapter *adapter)
545	{
546	__le32 *buffer;
547	char mesg[64];
548	char *msg[] = {mesg, NULL};
549	int i, k, ops_cnt, ops_index, dump_size = 0;
550	u32 entry_offset, dump, no_entries, buf_offset = 0;
551	struct qlcnic_dump_entry *entry;
552	struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
553	struct qlcnic_dump_template_hdr *tmpl_hdr = fw_dump->tmpl_hdr;
554
555	if (fw_dump->clr) {
556	dev_info(&adapter->pdev->dev,
557	"Previous dump not cleared, not capturing dump\n");
558	return -EIO;
559	}
560	/* Calculate the size for dump data area only */
561	for (i = 2, k = 1; (i & QLCNIC_DUMP_MASK_MAX); i <<= 1, k++)
562	if (i & tmpl_hdr->drv_cap_mask)
563	dump_size += tmpl_hdr->cap_sizes[k];
564	if (!dump_size)
565	return -EIO;
566
567	fw_dump->data = vzalloc(dump_size);
568	if (!fw_dump->data) {
569	dev_info(&adapter->pdev->dev,
570	"Unable to allocate (%d KB) for fw dump\n",
571	dump_size/1024);
572	return -ENOMEM;
573	}
574	buffer = fw_dump->data;
575	fw_dump->size = dump_size;
576	no_entries = tmpl_hdr->num_entries;
577	ops_cnt = ARRAY_SIZE(fw_dump_ops);
578	entry_offset = tmpl_hdr->offset;
579	tmpl_hdr->sys_info[0] = QLCNIC_DRIVER_VERSION;
580	tmpl_hdr->sys_info[1] = adapter->fw_version;
581
582	for (i = 0; i < no_entries; i++) {
583	entry = (void *)tmpl_hdr + entry_offset;
584	if (!(entry->hdr.mask & tmpl_hdr->drv_cap_mask)) {
585	entry->hdr.flags \|= QLCNIC_DUMP_SKIP;
586	entry_offset += entry->hdr.offset;
587	continue;
588	}
589	/* Find the handler for this entry */
590	ops_index = 0;
591	while (ops_index < ops_cnt) {
592	if (entry->hdr.type == fw_dump_ops[ops_index].opcode)
593	break;
594	ops_index++;
595	}
596	if (ops_index == ops_cnt) {
597	dev_info(&adapter->pdev->dev,
598	"Invalid entry type %d, exiting dump\n",
599	entry->hdr.type);
600	goto error;
601	}
602	/* Collect dump for this entry */
603	dump = fw_dump_ops[ops_index].handler(adapter, entry, buffer);
604	if (dump && !qlcnic_valid_dump_entry(&adapter->pdev->dev, entry,
605	dump))
606	entry->hdr.flags \|= QLCNIC_DUMP_SKIP;
607	buf_offset += entry->hdr.cap_size;
608	entry_offset += entry->hdr.offset;
609	buffer = fw_dump->data + buf_offset;
610	}
611	if (dump_size != buf_offset) {
612	dev_info(&adapter->pdev->dev,
613	"Captured(%d) and expected size(%d) do not match\n",
614	buf_offset, dump_size);
615	goto error;
616	} else {
617	fw_dump->clr = 1;
618	snprintf(mesg, sizeof(mesg), "FW_DUMP=%s",
619	adapter->netdev->name);
620	dev_info(&adapter->pdev->dev, "Dump data, %d bytes captured\n",
621	fw_dump->size);
622	/* Send a udev event to notify availability of FW dump */
623	kobject_uevent_env(&adapter->pdev->dev.kobj, KOBJ_CHANGE, msg);
624	return 0;
625	}
626	error:
627	vfree(fw_dump->data);
628	return -EINVAL;
629	}