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net: sh_eth: Fix receive packet "exceeded" condition in sh_eth_rx()
[deliverable/linux.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
f0e81fec 3 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978
SS		 4 * Copyright (C) 2008-2014 Renesas Solutions Corp.
5 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
702eca02 6 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
86a74ff2
NI		 16 *
17 * The full GNU General Public License is included in this distribution in
18 * the file called "COPYING".
19 */
20
0654011d
YS		 21#include <linux/module.h>
22#include <linux/kernel.h>
23#include <linux/spinlock.h>
6a27cded 24#include <linux/interrupt.h>
86a74ff2
NI		 25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/delay.h>
28#include <linux/platform_device.h>
29#include <linux/mdio-bitbang.h>
30#include <linux/netdevice.h>
b356e978
SS		 31#include <linux/of.h>
32#include <linux/of_device.h>
33#include <linux/of_irq.h>
34#include <linux/of_net.h>
86a74ff2
NI		 35#include <linux/phy.h>
36#include <linux/cache.h>
37#include <linux/io.h>
bcd5149d 38#include <linux/pm_runtime.h>
5a0e3ad6 39#include <linux/slab.h>
dc19e4e5 40#include <linux/ethtool.h>
fdb37a7f 41#include <linux/if_vlan.h>
f0e81fec 42#include <linux/clk.h>
d4fa0e35 43#include <linux/sh_eth.h>
702eca02 44#include <linux/of_mdio.h>
86a74ff2
NI		 45
46#include "sh_eth.h"
47
dc19e4e5
NI		 48#define SH_ETH_DEF_MSG_ENABLE \
49 (NETIF_MSG_LINK | \
50 NETIF_MSG_TIMER | \
51 NETIF_MSG_RX_ERR| \
52 NETIF_MSG_TX_ERR)
53
c0013f6f
SS		 54static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
55 [EDSR] = 0x0000,
56 [EDMR] = 0x0400,
57 [EDTRR] = 0x0408,
58 [EDRRR] = 0x0410,
59 [EESR] = 0x0428,
60 [EESIPR] = 0x0430,
61 [TDLAR] = 0x0010,
62 [TDFAR] = 0x0014,
63 [TDFXR] = 0x0018,
64 [TDFFR] = 0x001c,
65 [RDLAR] = 0x0030,
66 [RDFAR] = 0x0034,
67 [RDFXR] = 0x0038,
68 [RDFFR] = 0x003c,
69 [TRSCER] = 0x0438,
70 [RMFCR] = 0x0440,
71 [TFTR] = 0x0448,
72 [FDR] = 0x0450,
73 [RMCR] = 0x0458,
74 [RPADIR] = 0x0460,
75 [FCFTR] = 0x0468,
76 [CSMR] = 0x04E4,
77
78 [ECMR] = 0x0500,
79 [ECSR] = 0x0510,
80 [ECSIPR] = 0x0518,
81 [PIR] = 0x0520,
82 [PSR] = 0x0528,
83 [PIPR] = 0x052c,
84 [RFLR] = 0x0508,
85 [APR] = 0x0554,
86 [MPR] = 0x0558,
87 [PFTCR] = 0x055c,
88 [PFRCR] = 0x0560,
89 [TPAUSER] = 0x0564,
90 [GECMR] = 0x05b0,
91 [BCULR] = 0x05b4,
92 [MAHR] = 0x05c0,
93 [MALR] = 0x05c8,
94 [TROCR] = 0x0700,
95 [CDCR] = 0x0708,
96 [LCCR] = 0x0710,
97 [CEFCR] = 0x0740,
98 [FRECR] = 0x0748,
99 [TSFRCR] = 0x0750,
100 [TLFRCR] = 0x0758,
101 [RFCR] = 0x0760,
102 [CERCR] = 0x0768,
103 [CEECR] = 0x0770,
104 [MAFCR] = 0x0778,
105 [RMII_MII] = 0x0790,
106
107 [ARSTR] = 0x0000,
108 [TSU_CTRST] = 0x0004,
109 [TSU_FWEN0] = 0x0010,
110 [TSU_FWEN1] = 0x0014,
111 [TSU_FCM] = 0x0018,
112 [TSU_BSYSL0] = 0x0020,
113 [TSU_BSYSL1] = 0x0024,
114 [TSU_PRISL0] = 0x0028,
115 [TSU_PRISL1] = 0x002c,
116 [TSU_FWSL0] = 0x0030,
117 [TSU_FWSL1] = 0x0034,
118 [TSU_FWSLC] = 0x0038,
119 [TSU_QTAG0] = 0x0040,
120 [TSU_QTAG1] = 0x0044,
121 [TSU_FWSR] = 0x0050,
122 [TSU_FWINMK] = 0x0054,
123 [TSU_ADQT0] = 0x0048,
124 [TSU_ADQT1] = 0x004c,
125 [TSU_VTAG0] = 0x0058,
126 [TSU_VTAG1] = 0x005c,
127 [TSU_ADSBSY] = 0x0060,
128 [TSU_TEN] = 0x0064,
129 [TSU_POST1] = 0x0070,
130 [TSU_POST2] = 0x0074,
131 [TSU_POST3] = 0x0078,
132 [TSU_POST4] = 0x007c,
133 [TSU_ADRH0] = 0x0100,
134 [TSU_ADRL0] = 0x0104,
135 [TSU_ADRH31] = 0x01f8,
136 [TSU_ADRL31] = 0x01fc,
137
138 [TXNLCR0] = 0x0080,
139 [TXALCR0] = 0x0084,
140 [RXNLCR0] = 0x0088,
141 [RXALCR0] = 0x008c,
142 [FWNLCR0] = 0x0090,
143 [FWALCR0] = 0x0094,
144 [TXNLCR1] = 0x00a0,
145 [TXALCR1] = 0x00a0,
146 [RXNLCR1] = 0x00a8,
147 [RXALCR1] = 0x00ac,
148 [FWNLCR1] = 0x00b0,
149 [FWALCR1] = 0x00b4,
150};
151
db893473
SH		 152static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
153 [EDSR] = 0x0000,
154 [EDMR] = 0x0400,
155 [EDTRR] = 0x0408,
156 [EDRRR] = 0x0410,
157 [EESR] = 0x0428,
158 [EESIPR] = 0x0430,
159 [TDLAR] = 0x0010,
160 [TDFAR] = 0x0014,
161 [TDFXR] = 0x0018,
162 [TDFFR] = 0x001c,
163 [RDLAR] = 0x0030,
164 [RDFAR] = 0x0034,
165 [RDFXR] = 0x0038,
166 [RDFFR] = 0x003c,
167 [TRSCER] = 0x0438,
168 [RMFCR] = 0x0440,
169 [TFTR] = 0x0448,
170 [FDR] = 0x0450,
171 [RMCR] = 0x0458,
172 [RPADIR] = 0x0460,
173 [FCFTR] = 0x0468,
174 [CSMR] = 0x04E4,
175
176 [ECMR] = 0x0500,
177 [RFLR] = 0x0508,
178 [ECSR] = 0x0510,
179 [ECSIPR] = 0x0518,
180 [PIR] = 0x0520,
181 [APR] = 0x0554,
182 [MPR] = 0x0558,
183 [PFTCR] = 0x055c,
184 [PFRCR] = 0x0560,
185 [TPAUSER] = 0x0564,
186 [MAHR] = 0x05c0,
187 [MALR] = 0x05c8,
188 [CEFCR] = 0x0740,
189 [FRECR] = 0x0748,
190 [TSFRCR] = 0x0750,
191 [TLFRCR] = 0x0758,
192 [RFCR] = 0x0760,
193 [MAFCR] = 0x0778,
194
195 [ARSTR] = 0x0000,
196 [TSU_CTRST] = 0x0004,
197 [TSU_VTAG0] = 0x0058,
198 [TSU_ADSBSY] = 0x0060,
199 [TSU_TEN] = 0x0064,
200 [TSU_ADRH0] = 0x0100,
201 [TSU_ADRL0] = 0x0104,
202 [TSU_ADRH31] = 0x01f8,
203 [TSU_ADRL31] = 0x01fc,
204
205 [TXNLCR0] = 0x0080,
206 [TXALCR0] = 0x0084,
207 [RXNLCR0] = 0x0088,
208 [RXALCR0] = 0x008C,
209};
210
a3f109bd
SS		 211static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
212 [ECMR] = 0x0300,
213 [RFLR] = 0x0308,
214 [ECSR] = 0x0310,
215 [ECSIPR] = 0x0318,
216 [PIR] = 0x0320,
217 [PSR] = 0x0328,
218 [RDMLR] = 0x0340,
219 [IPGR] = 0x0350,
220 [APR] = 0x0354,
221 [MPR] = 0x0358,
222 [RFCF] = 0x0360,
223 [TPAUSER] = 0x0364,
224 [TPAUSECR] = 0x0368,
225 [MAHR] = 0x03c0,
226 [MALR] = 0x03c8,
227 [TROCR] = 0x03d0,
228 [CDCR] = 0x03d4,
229 [LCCR] = 0x03d8,
230 [CNDCR] = 0x03dc,
231 [CEFCR] = 0x03e4,
232 [FRECR] = 0x03e8,
233 [TSFRCR] = 0x03ec,
234 [TLFRCR] = 0x03f0,
235 [RFCR] = 0x03f4,
236 [MAFCR] = 0x03f8,
237
238 [EDMR] = 0x0200,
239 [EDTRR] = 0x0208,
240 [EDRRR] = 0x0210,
241 [TDLAR] = 0x0218,
242 [RDLAR] = 0x0220,
243 [EESR] = 0x0228,
244 [EESIPR] = 0x0230,
245 [TRSCER] = 0x0238,
246 [RMFCR] = 0x0240,
247 [TFTR] = 0x0248,
248 [FDR] = 0x0250,
249 [RMCR] = 0x0258,
250 [TFUCR] = 0x0264,
251 [RFOCR] = 0x0268,
55754f19 252 [RMIIMODE] = 0x026c,
a3f109bd
SS		 253 [FCFTR] = 0x0270,
254 [TRIMD] = 0x027c,
255};
256
c0013f6f
SS		 257static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
258 [ECMR] = 0x0100,
259 [RFLR] = 0x0108,
260 [ECSR] = 0x0110,
261 [ECSIPR] = 0x0118,
262 [PIR] = 0x0120,
263 [PSR] = 0x0128,
264 [RDMLR] = 0x0140,
265 [IPGR] = 0x0150,
266 [APR] = 0x0154,
267 [MPR] = 0x0158,
268 [TPAUSER] = 0x0164,
269 [RFCF] = 0x0160,
270 [TPAUSECR] = 0x0168,
271 [BCFRR] = 0x016c,
272 [MAHR] = 0x01c0,
273 [MALR] = 0x01c8,
274 [TROCR] = 0x01d0,
275 [CDCR] = 0x01d4,
276 [LCCR] = 0x01d8,
277 [CNDCR] = 0x01dc,
278 [CEFCR] = 0x01e4,
279 [FRECR] = 0x01e8,
280 [TSFRCR] = 0x01ec,
281 [TLFRCR] = 0x01f0,
282 [RFCR] = 0x01f4,
283 [MAFCR] = 0x01f8,
284 [RTRATE] = 0x01fc,
285
286 [EDMR] = 0x0000,
287 [EDTRR] = 0x0008,
288 [EDRRR] = 0x0010,
289 [TDLAR] = 0x0018,
290 [RDLAR] = 0x0020,
291 [EESR] = 0x0028,
292 [EESIPR] = 0x0030,
293 [TRSCER] = 0x0038,
294 [RMFCR] = 0x0040,
295 [TFTR] = 0x0048,
296 [FDR] = 0x0050,
297 [RMCR] = 0x0058,
298 [TFUCR] = 0x0064,
299 [RFOCR] = 0x0068,
300 [FCFTR] = 0x0070,
301 [RPADIR] = 0x0078,
302 [TRIMD] = 0x007c,
303 [RBWAR] = 0x00c8,
304 [RDFAR] = 0x00cc,
305 [TBRAR] = 0x00d4,
306 [TDFAR] = 0x00d8,
307};
308
309static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
d8b0426a
SS		 310 [EDMR] = 0x0000,
311 [EDTRR] = 0x0004,
312 [EDRRR] = 0x0008,
313 [TDLAR] = 0x000c,
314 [RDLAR] = 0x0010,
315 [EESR] = 0x0014,
316 [EESIPR] = 0x0018,
317 [TRSCER] = 0x001c,
318 [RMFCR] = 0x0020,
319 [TFTR] = 0x0024,
320 [FDR] = 0x0028,
321 [RMCR] = 0x002c,
322 [EDOCR] = 0x0030,
323 [FCFTR] = 0x0034,
324 [RPADIR] = 0x0038,
325 [TRIMD] = 0x003c,
326 [RBWAR] = 0x0040,
327 [RDFAR] = 0x0044,
328 [TBRAR] = 0x004c,
329 [TDFAR] = 0x0050,
330
c0013f6f
SS		 331 [ECMR] = 0x0160,
332 [ECSR] = 0x0164,
333 [ECSIPR] = 0x0168,
334 [PIR] = 0x016c,
335 [MAHR] = 0x0170,
336 [MALR] = 0x0174,
337 [RFLR] = 0x0178,
338 [PSR] = 0x017c,
339 [TROCR] = 0x0180,
340 [CDCR] = 0x0184,
341 [LCCR] = 0x0188,
342 [CNDCR] = 0x018c,
343 [CEFCR] = 0x0194,
344 [FRECR] = 0x0198,
345 [TSFRCR] = 0x019c,
346 [TLFRCR] = 0x01a0,
347 [RFCR] = 0x01a4,
348 [MAFCR] = 0x01a8,
349 [IPGR] = 0x01b4,
350 [APR] = 0x01b8,
351 [MPR] = 0x01bc,
352 [TPAUSER] = 0x01c4,
353 [BCFR] = 0x01cc,
354
355 [ARSTR] = 0x0000,
356 [TSU_CTRST] = 0x0004,
357 [TSU_FWEN0] = 0x0010,
358 [TSU_FWEN1] = 0x0014,
359 [TSU_FCM] = 0x0018,
360 [TSU_BSYSL0] = 0x0020,
361 [TSU_BSYSL1] = 0x0024,
362 [TSU_PRISL0] = 0x0028,
363 [TSU_PRISL1] = 0x002c,
364 [TSU_FWSL0] = 0x0030,
365 [TSU_FWSL1] = 0x0034,
366 [TSU_FWSLC] = 0x0038,
367 [TSU_QTAGM0] = 0x0040,
368 [TSU_QTAGM1] = 0x0044,
369 [TSU_ADQT0] = 0x0048,
370 [TSU_ADQT1] = 0x004c,
371 [TSU_FWSR] = 0x0050,
372 [TSU_FWINMK] = 0x0054,
373 [TSU_ADSBSY] = 0x0060,
374 [TSU_TEN] = 0x0064,
375 [TSU_POST1] = 0x0070,
376 [TSU_POST2] = 0x0074,
377 [TSU_POST3] = 0x0078,
378 [TSU_POST4] = 0x007c,
379
380 [TXNLCR0] = 0x0080,
381 [TXALCR0] = 0x0084,
382 [RXNLCR0] = 0x0088,
383 [RXALCR0] = 0x008c,
384 [FWNLCR0] = 0x0090,
385 [FWALCR0] = 0x0094,
386 [TXNLCR1] = 0x00a0,
387 [TXALCR1] = 0x00a0,
388 [RXNLCR1] = 0x00a8,
389 [RXALCR1] = 0x00ac,
390 [FWNLCR1] = 0x00b0,
391 [FWALCR1] = 0x00b4,
392
393 [TSU_ADRH0] = 0x0100,
394 [TSU_ADRL0] = 0x0104,
395 [TSU_ADRL31] = 0x01fc,
396};
397
504c8ca5 398static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 399{
504c8ca5 400 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 401}
402
db893473
SH		 403static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
404{
405 return mdp->reg_offset == sh_eth_offset_fast_rz;
406}
407
8e994402 408static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 409{
410 u32 value = 0x0;
411 struct sh_eth_private *mdp = netdev_priv(ndev);
412
413 switch (mdp->phy_interface) {
414 case PHY_INTERFACE_MODE_GMII:
415 value = 0x2;
416 break;
417 case PHY_INTERFACE_MODE_MII:
418 value = 0x1;
419 break;
420 case PHY_INTERFACE_MODE_RMII:
421 value = 0x0;
422 break;
423 default:
f75f14ec
SS		 424 netdev_warn(ndev,
425 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 426 value = 0x1;
427 break;
428 }
429
430 sh_eth_write(ndev, value, RMII_MII);
431}
5e7a76be 432
8e994402 433static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 434{
435 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 436
437 if (mdp->duplex) /* Full */
4a55530f 438 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 439 else /* Half */
4a55530f 440 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 441}
442
04b0ed2a 443/* There is CPU dependent code */
589ebdef 444static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 445{
446 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 447
a3f109bd
SS		 448 switch (mdp->speed) {
449 case 10: /* 10BASE */
450 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
451 break;
452 case 100:/* 100BASE */
453 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
454 break;
455 default:
456 break;
457 }
458}
459
674853b2 460/* R8A7778/9 */
589ebdef 461static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 462 .set_duplex = sh_eth_set_duplex,
589ebdef 463 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 464
a3153d8c
SS		 465 .register_type = SH_ETH_REG_FAST_RCAR,
466
a3f109bd
SS		 467 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
468 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
469 .eesipr_value = 0x01ff009f,
470
471 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 472 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
473 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
474 EESR_ECI,
a3f109bd
SS		 475
476 .apr = 1,
477 .mpr = 1,
478 .tpauser = 1,
479 .hw_swap = 1,
480};
a3f109bd 481
94a12b15
SS		 482/* R8A7790/1 */
483static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 484 .set_duplex = sh_eth_set_duplex,
485 .set_rate = sh_eth_set_rate_r8a777x,
486
a3153d8c
SS		 487 .register_type = SH_ETH_REG_FAST_RCAR,
488
e18dbf7e
SH		 489 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
490 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
491 .eesipr_value = 0x01ff009f,
492
493 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 494 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
495 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
496 EESR_ECI,
e18dbf7e
SH		 497
498 .apr = 1,
499 .mpr = 1,
500 .tpauser = 1,
501 .hw_swap = 1,
502 .rmiimode = 1,
fd9af07c 503 .shift_rd0 = 1,
e18dbf7e
SH		 504};
505
9c3beaab 506static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 507{
508 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 509
510 switch (mdp->speed) {
511 case 10: /* 10BASE */
a3f109bd 512 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 513 break;
514 case 100:/* 100BASE */
a3f109bd 515 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 516 break;
517 default:
518 break;
519 }
520}
521
522/* SH7724 */
9c3beaab 523static struct sh_eth_cpu_data sh7724_data = {
65ac8851 524 .set_duplex = sh_eth_set_duplex,
9c3beaab 525 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 526
a3153d8c
SS		 527 .register_type = SH_ETH_REG_FAST_SH4,
528
65ac8851
YS		 529 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
530 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 531 .eesipr_value = 0x01ff009f,
65ac8851
YS		 532
533 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 534 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
535 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
536 EESR_ECI,
65ac8851
YS		 537
538 .apr = 1,
539 .mpr = 1,
540 .tpauser = 1,
541 .hw_swap = 1,
503914cf
MD		 542 .rpadir = 1,
543 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 544};
5cee1d37 545
24549e2a 546static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 547{
548 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 549
550 switch (mdp->speed) {
551 case 10: /* 10BASE */
4a55530f 552 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 553 break;
554 case 100:/* 100BASE */
4a55530f 555 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 556 break;
557 default:
558 break;
559 }
560}
561
562/* SH7757 */
24549e2a
SS		 563static struct sh_eth_cpu_data sh7757_data = {
564 .set_duplex = sh_eth_set_duplex,
565 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 566
a3153d8c
SS		 567 .register_type = SH_ETH_REG_FAST_SH4,
568
f29a3d04 569 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 570
571 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 572 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
573 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
574 EESR_ECI,
f29a3d04 575
5b3dfd13 576 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 577 .apr = 1,
578 .mpr = 1,
579 .tpauser = 1,
580 .hw_swap = 1,
581 .no_ade = 1,
2e98e797
YS		 582 .rpadir = 1,
583 .rpadir_value = 2 << 16,
f29a3d04 584};
65ac8851 585
e403d295 586#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 587#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
588#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
589static void sh_eth_chip_reset_giga(struct net_device *ndev)
590{
591 int i;
592 unsigned long mahr[2], malr[2];
593
594 /* save MAHR and MALR */
595 for (i = 0; i < 2; i++) {
ae70644d
YS		 596 malr[i] = ioread32((void *)GIGA_MALR(i));
597 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 598 }
599
600 /* reset device */
ae70644d 601 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 602 mdelay(1);
603
604 /* restore MAHR and MALR */
605 for (i = 0; i < 2; i++) {
ae70644d
YS		 606 iowrite32(malr[i], (void *)GIGA_MALR(i));
607 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 608 }
609}
610
8fcd4961
YS		 611static void sh_eth_set_rate_giga(struct net_device *ndev)
612{
613 struct sh_eth_private *mdp = netdev_priv(ndev);
614
615 switch (mdp->speed) {
616 case 10: /* 10BASE */
617 sh_eth_write(ndev, 0x00000000, GECMR);
618 break;
619 case 100:/* 100BASE */
620 sh_eth_write(ndev, 0x00000010, GECMR);
621 break;
622 case 1000: /* 1000BASE */
623 sh_eth_write(ndev, 0x00000020, GECMR);
624 break;
625 default:
626 break;
627 }
628}
629
630/* SH7757(GETHERC) */
24549e2a 631static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 632 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 633 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 634 .set_rate = sh_eth_set_rate_giga,
635
a3153d8c
SS		 636 .register_type = SH_ETH_REG_GIGABIT,
637
8fcd4961
YS		 638 .ecsr_value = ECSR_ICD | ECSR_MPD,
639 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
640 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
641
642 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 643 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
644 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
645 EESR_TDE | EESR_ECI,
8fcd4961 646 .fdr_value = 0x0000072f,
8fcd4961 647
5b3dfd13 648 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 649 .apr = 1,
650 .mpr = 1,
651 .tpauser = 1,
652 .bculr = 1,
653 .hw_swap = 1,
654 .rpadir = 1,
655 .rpadir_value = 2 << 16,
656 .no_trimd = 1,
657 .no_ade = 1,
3acbc971 658 .tsu = 1,
8fcd4961
YS		 659};
660
380af9e3
YS		 661static void sh_eth_chip_reset(struct net_device *ndev)
662{
4986b996
YS		 663 struct sh_eth_private *mdp = netdev_priv(ndev);
664
380af9e3 665 /* reset device */
4986b996 666 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 667 mdelay(1);
668}
669
f5d12767 670static void sh_eth_set_rate_gether(struct net_device *ndev)
380af9e3
YS		 671{
672 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 673
674 switch (mdp->speed) {
675 case 10: /* 10BASE */
4a55530f 676 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 677 break;
678 case 100:/* 100BASE */
4a55530f 679 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 680 break;
681 case 1000: /* 1000BASE */
4a55530f 682 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 683 break;
684 default:
685 break;
686 }
687}
688
f5d12767
SS		 689/* SH7734 */
690static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 691 .chip_reset = sh_eth_chip_reset,
692 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 693 .set_rate = sh_eth_set_rate_gether,
694
a3153d8c
SS		 695 .register_type = SH_ETH_REG_GIGABIT,
696
f5d12767
SS		 697 .ecsr_value = ECSR_ICD | ECSR_MPD,
698 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
699 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
700
701 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 702 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
703 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
704 EESR_TDE | EESR_ECI,
f5d12767
SS		 705
706 .apr = 1,
707 .mpr = 1,
708 .tpauser = 1,
709 .bculr = 1,
710 .hw_swap = 1,
711 .no_trimd = 1,
712 .no_ade = 1,
713 .tsu = 1,
714 .hw_crc = 1,
715 .select_mii = 1,
716};
717
718/* SH7763 */
719static struct sh_eth_cpu_data sh7763_data = {
720 .chip_reset = sh_eth_chip_reset,
721 .set_duplex = sh_eth_set_duplex,
722 .set_rate = sh_eth_set_rate_gether,
380af9e3 723
a3153d8c
SS		 724 .register_type = SH_ETH_REG_GIGABIT,
725
380af9e3
YS		 726 .ecsr_value = ECSR_ICD | ECSR_MPD,
727 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
728 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
729
730 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 731 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
732 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 733 EESR_ECI,
380af9e3
YS		 734
735 .apr = 1,
736 .mpr = 1,
737 .tpauser = 1,
738 .bculr = 1,
739 .hw_swap = 1,
380af9e3
YS		 740 .no_trimd = 1,
741 .no_ade = 1,
4986b996 742 .tsu = 1,
5b3dfd13 743 .irq_flags = IRQF_SHARED,
380af9e3
YS		 744};
745
e5c9b4cd 746static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
73a0d907
YS		 747{
748 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 749
750 /* reset device */
751 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
752 mdelay(1);
753
5e7a76be 754 sh_eth_select_mii(ndev);
73a0d907
YS		 755}
756
73a0d907 757/* R8A7740 */
e5c9b4cd
SS		 758static struct sh_eth_cpu_data r8a7740_data = {
759 .chip_reset = sh_eth_chip_reset_r8a7740,
73a0d907 760 .set_duplex = sh_eth_set_duplex,
e5c9b4cd 761 .set_rate = sh_eth_set_rate_gether,
73a0d907 762
a3153d8c
SS		 763 .register_type = SH_ETH_REG_GIGABIT,
764
73a0d907
YS		 765 .ecsr_value = ECSR_ICD | ECSR_MPD,
766 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
767 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
768
769 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 770 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
771 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
772 EESR_TDE | EESR_ECI,
cc23528d 773 .fdr_value = 0x0000070f,
73a0d907
YS		 774
775 .apr = 1,
776 .mpr = 1,
777 .tpauser = 1,
778 .bculr = 1,
779 .hw_swap = 1,
cc23528d
SH		 780 .rpadir = 1,
781 .rpadir_value = 2 << 16,
73a0d907
YS		 782 .no_trimd = 1,
783 .no_ade = 1,
784 .tsu = 1,
5e7a76be 785 .select_mii = 1,
ac8025a6 786 .shift_rd0 = 1,
73a0d907
YS		 787};
788
db893473
SH		 789/* R7S72100 */
790static struct sh_eth_cpu_data r7s72100_data = {
791 .chip_reset = sh_eth_chip_reset,
792 .set_duplex = sh_eth_set_duplex,
793
794 .register_type = SH_ETH_REG_FAST_RZ,
795
796 .ecsr_value = ECSR_ICD,
797 .ecsipr_value = ECSIPR_ICDIP,
798 .eesipr_value = 0xff7f009f,
799
800 .tx_check = EESR_TC1 | EESR_FTC,
801 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
802 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
803 EESR_TDE | EESR_ECI,
804 .fdr_value = 0x0000070f,
db893473
SH		 805
806 .no_psr = 1,
807 .apr = 1,
808 .mpr = 1,
809 .tpauser = 1,
810 .hw_swap = 1,
811 .rpadir = 1,
812 .rpadir_value = 2 << 16,
813 .no_trimd = 1,
814 .no_ade = 1,
815 .hw_crc = 1,
816 .tsu = 1,
817 .shift_rd0 = 1,
818};
819
c18a79ab 820static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 821 .register_type = SH_ETH_REG_FAST_SH3_SH2,
822
380af9e3
YS		 823 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
824
825 .apr = 1,
826 .mpr = 1,
827 .tpauser = 1,
828 .hw_swap = 1,
829};
7bbe150d
SS		 830
831static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 832 .register_type = SH_ETH_REG_FAST_SH3_SH2,
833
380af9e3 834 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 835 .tsu = 1,
380af9e3 836};
380af9e3
YS		 837
838static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
839{
840 if (!cd->ecsr_value)
841 cd->ecsr_value = DEFAULT_ECSR_INIT;
842
843 if (!cd->ecsipr_value)
844 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
845
846 if (!cd->fcftr_value)
128296fc 847 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 848 DEFAULT_FIFO_F_D_RFD;
849
850 if (!cd->fdr_value)
851 cd->fdr_value = DEFAULT_FDR_INIT;
852
380af9e3
YS		 853 if (!cd->tx_check)
854 cd->tx_check = DEFAULT_TX_CHECK;
855
856 if (!cd->eesr_err_check)
857 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
380af9e3
YS		 858}
859
5cee1d37
NI		 860static int sh_eth_check_reset(struct net_device *ndev)
861{
862 int ret = 0;
863 int cnt = 100;
864
865 while (cnt > 0) {
866 if (!(sh_eth_read(ndev, EDMR) & 0x3))
867 break;
868 mdelay(1);
869 cnt--;
870 }
9f8c4265 871 if (cnt <= 0) {
f75f14ec 872 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 873 ret = -ETIMEDOUT;
874 }
875 return ret;
380af9e3 876}
dabdde9e
NI		 877
878static int sh_eth_reset(struct net_device *ndev)
879{
880 struct sh_eth_private *mdp = netdev_priv(ndev);
881 int ret = 0;
882
db893473 883 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e
NI		 884 sh_eth_write(ndev, EDSR_ENALL, EDSR);
885 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
886 EDMR);
887
888 ret = sh_eth_check_reset(ndev);
889 if (ret)
f738a13d 890 return ret;
dabdde9e
NI		 891
892 /* Table Init */
893 sh_eth_write(ndev, 0x0, TDLAR);
894 sh_eth_write(ndev, 0x0, TDFAR);
895 sh_eth_write(ndev, 0x0, TDFXR);
896 sh_eth_write(ndev, 0x0, TDFFR);
897 sh_eth_write(ndev, 0x0, RDLAR);
898 sh_eth_write(ndev, 0x0, RDFAR);
899 sh_eth_write(ndev, 0x0, RDFXR);
900 sh_eth_write(ndev, 0x0, RDFFR);
901
902 /* Reset HW CRC register */
903 if (mdp->cd->hw_crc)
904 sh_eth_write(ndev, 0x0, CSMR);
905
906 /* Select MII mode */
907 if (mdp->cd->select_mii)
908 sh_eth_select_mii(ndev);
909 } else {
910 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
911 EDMR);
912 mdelay(3);
913 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
914 EDMR);
915 }
916
dabdde9e
NI		 917 return ret;
918}
380af9e3 919
73a0d907 920#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
380af9e3
YS		 921static void sh_eth_set_receive_align(struct sk_buff *skb)
922{
923 int reserve;
924
925 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
926 if (reserve)
927 skb_reserve(skb, reserve);
928}
929#else
930static void sh_eth_set_receive_align(struct sk_buff *skb)
931{
932 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
933}
934#endif
935
936
71557a37
YS		 937/* CPU <-> EDMAC endian convert */
938static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
939{
940 switch (mdp->edmac_endian) {
941 case EDMAC_LITTLE_ENDIAN:
942 return cpu_to_le32(x);
943 case EDMAC_BIG_ENDIAN:
944 return cpu_to_be32(x);
945 }
946 return x;
947}
948
949static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
950{
951 switch (mdp->edmac_endian) {
952 case EDMAC_LITTLE_ENDIAN:
953 return le32_to_cpu(x);
954 case EDMAC_BIG_ENDIAN:
955 return be32_to_cpu(x);
956 }
957 return x;
958}
959
128296fc 960/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 961static void update_mac_address(struct net_device *ndev)
962{
4a55530f 963 sh_eth_write(ndev,
128296fc
SS		 964 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
965 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 966 sh_eth_write(ndev,
128296fc 967 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 968}
969
128296fc 970/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 971 *
972 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
973 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
974 * When you want use this device, you must set MAC address in bootloader.
975 *
976 */
748031f9 977static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 978{
748031f9 979 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 980 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 981 } else {
4a55530f
YS		 982 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
983 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
984 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
985 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
986 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
987 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 988 }
86a74ff2
NI		 989}
990
c5ed5368
YS		 991static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
992{
db893473 993 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 994 return EDTRR_TRNS_GETHER;
995 else
996 return EDTRR_TRNS_ETHER;
997}
998
86a74ff2 999struct bb_info {
ae70644d 1000 void (*set_gate)(void *addr);
86a74ff2 1001 struct mdiobb_ctrl ctrl;
ae70644d 1002 void *addr;
86a74ff2
NI		 1003 u32 mmd_msk;/* MMD */
1004 u32 mdo_msk;
1005 u32 mdi_msk;
1006 u32 mdc_msk;
1007};
1008
1009/* PHY bit set */
ae70644d 1010static void bb_set(void *addr, u32 msk)
86a74ff2 1011{
ae70644d 1012 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 1013}
1014
1015/* PHY bit clear */
ae70644d 1016static void bb_clr(void *addr, u32 msk)
86a74ff2 1017{
ae70644d 1018 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 1019}
1020
1021/* PHY bit read */
ae70644d 1022static int bb_read(void *addr, u32 msk)
86a74ff2 1023{
ae70644d 1024 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 1025}
1026
1027/* Data I/O pin control */
1028static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1029{
1030 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1031
1032 if (bitbang->set_gate)
1033 bitbang->set_gate(bitbang->addr);
1034
86a74ff2
NI		 1035 if (bit)
1036 bb_set(bitbang->addr, bitbang->mmd_msk);
1037 else
1038 bb_clr(bitbang->addr, bitbang->mmd_msk);
1039}
1040
1041/* Set bit data*/
1042static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1043{
1044 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1045
b3017e6a
YS		 1046 if (bitbang->set_gate)
1047 bitbang->set_gate(bitbang->addr);
1048
86a74ff2
NI		 1049 if (bit)
1050 bb_set(bitbang->addr, bitbang->mdo_msk);
1051 else
1052 bb_clr(bitbang->addr, bitbang->mdo_msk);
1053}
1054
1055/* Get bit data*/
1056static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1057{
1058 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1059
1060 if (bitbang->set_gate)
1061 bitbang->set_gate(bitbang->addr);
1062
86a74ff2
NI		 1063 return bb_read(bitbang->addr, bitbang->mdi_msk);
1064}
1065
1066/* MDC pin control */
1067static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1068{
1069 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1070
b3017e6a
YS		 1071 if (bitbang->set_gate)
1072 bitbang->set_gate(bitbang->addr);
1073
86a74ff2
NI		 1074 if (bit)
1075 bb_set(bitbang->addr, bitbang->mdc_msk);
1076 else
1077 bb_clr(bitbang->addr, bitbang->mdc_msk);
1078}
1079
1080/* mdio bus control struct */
1081static struct mdiobb_ops bb_ops = {
1082 .owner = THIS_MODULE,
1083 .set_mdc = sh_mdc_ctrl,
1084 .set_mdio_dir = sh_mmd_ctrl,
1085 .set_mdio_data = sh_set_mdio,
1086 .get_mdio_data = sh_get_mdio,
1087};
1088
86a74ff2
NI		 1089/* free skb and descriptor buffer */
1090static void sh_eth_ring_free(struct net_device *ndev)
1091{
1092 struct sh_eth_private *mdp = netdev_priv(ndev);
1093 int i;
1094
1095 /* Free Rx skb ringbuffer */
1096 if (mdp->rx_skbuff) {
525b8075 1097 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1098 if (mdp->rx_skbuff[i])
1099 dev_kfree_skb(mdp->rx_skbuff[i]);
1100 }
1101 }
1102 kfree(mdp->rx_skbuff);
91c77550 1103 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1104
1105 /* Free Tx skb ringbuffer */
1106 if (mdp->tx_skbuff) {
525b8075 1107 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1108 if (mdp->tx_skbuff[i])
1109 dev_kfree_skb(mdp->tx_skbuff[i]);
1110 }
1111 }
1112 kfree(mdp->tx_skbuff);
91c77550 1113 mdp->tx_skbuff = NULL;
86a74ff2
NI		 1114}
1115
1116/* format skb and descriptor buffer */
1117static void sh_eth_ring_format(struct net_device *ndev)
1118{
1119 struct sh_eth_private *mdp = netdev_priv(ndev);
1120 int i;
1121 struct sk_buff *skb;
1122 struct sh_eth_rxdesc *rxdesc = NULL;
1123 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1124 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1125 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
86a74ff2 1126
128296fc
SS		 1127 mdp->cur_rx = 0;
1128 mdp->cur_tx = 0;
1129 mdp->dirty_rx = 0;
1130 mdp->dirty_tx = 0;
86a74ff2
NI		 1131
1132 memset(mdp->rx_ring, 0, rx_ringsize);
1133
1134 /* build Rx ring buffer */
525b8075 1135 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1136 /* skb */
1137 mdp->rx_skbuff[i] = NULL;
dae2e9f4 1138 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1139 mdp->rx_skbuff[i] = skb;
1140 if (skb == NULL)
1141 break;
bb7d92e3 1142 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
128296fc 1143 DMA_FROM_DEVICE);
380af9e3
YS		 1144 sh_eth_set_receive_align(skb);
1145
86a74ff2
NI		 1146 /* RX descriptor */
1147 rxdesc = &mdp->rx_ring[i];
0029d64a 1148 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 1149 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1150
1151 /* The size of the buffer is 16 byte boundary. */
0029d64a 1152 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 1153 /* Rx descriptor address set */
1154 if (i == 0) {
4a55530f 1155 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1156 if (sh_eth_is_gether(mdp) ||
1157 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1158 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1159 }
86a74ff2
NI		 1160 }
1161
525b8075 1162 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1163
1164 /* Mark the last entry as wrapping the ring. */
71557a37 1165 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 1166
1167 memset(mdp->tx_ring, 0, tx_ringsize);
1168
1169 /* build Tx ring buffer */
525b8075 1170 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1171 mdp->tx_skbuff[i] = NULL;
1172 txdesc = &mdp->tx_ring[i];
71557a37 1173 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1174 txdesc->buffer_length = 0;
b0ca2a21 1175 if (i == 0) {
71557a37 1176 /* Tx descriptor address set */
4a55530f 1177 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1178 if (sh_eth_is_gether(mdp) ||
1179 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1180 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1181 }
86a74ff2
NI		 1182 }
1183
71557a37 1184 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1185}
1186
1187/* Get skb and descriptor buffer */
1188static int sh_eth_ring_init(struct net_device *ndev)
1189{
1190 struct sh_eth_private *mdp = netdev_priv(ndev);
1191 int rx_ringsize, tx_ringsize, ret = 0;
1192
128296fc 1193 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1194 * card needs room to do 8 byte alignment, +2 so we can reserve
1195 * the first 2 bytes, and +16 gets room for the status word from the
1196 * card.
1197 */
1198 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1199 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1200 if (mdp->cd->rpadir)
1201 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1202
1203 /* Allocate RX and TX skb rings */
b2adaca9
JP		 1204 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1205 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
86a74ff2 1206 if (!mdp->rx_skbuff) {
86a74ff2
NI		 1207 ret = -ENOMEM;
1208 return ret;
1209 }
1210
b2adaca9
JP		 1211 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1212 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
86a74ff2 1213 if (!mdp->tx_skbuff) {
86a74ff2
NI		 1214 ret = -ENOMEM;
1215 goto skb_ring_free;
1216 }
1217
1218 /* Allocate all Rx descriptors. */
525b8075 1219 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1220 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1221 GFP_KERNEL);
86a74ff2 1222 if (!mdp->rx_ring) {
86a74ff2
NI		 1223 ret = -ENOMEM;
1224 goto desc_ring_free;
1225 }
1226
1227 mdp->dirty_rx = 0;
1228
1229 /* Allocate all Tx descriptors. */
525b8075 1230 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1231 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1232 GFP_KERNEL);
86a74ff2 1233 if (!mdp->tx_ring) {
86a74ff2
NI		 1234 ret = -ENOMEM;
1235 goto desc_ring_free;
1236 }
1237 return ret;
1238
1239desc_ring_free:
1240 /* free DMA buffer */
1241 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1242
1243skb_ring_free:
1244 /* Free Rx and Tx skb ring buffer */
1245 sh_eth_ring_free(ndev);
91c77550
YS		 1246 mdp->tx_ring = NULL;
1247 mdp->rx_ring = NULL;
86a74ff2
NI		 1248
1249 return ret;
1250}
1251
91c77550
YS		 1252static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1253{
1254 int ringsize;
1255
1256 if (mdp->rx_ring) {
525b8075 1257 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 1258 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1259 mdp->rx_desc_dma);
1260 mdp->rx_ring = NULL;
1261 }
1262
1263 if (mdp->tx_ring) {
525b8075 1264 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 1265 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1266 mdp->tx_desc_dma);
1267 mdp->tx_ring = NULL;
1268 }
1269}
1270
525b8075 1271static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1272{
1273 int ret = 0;
1274 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1275 u32 val;
1276
1277 /* Soft Reset */
5cee1d37
NI		 1278 ret = sh_eth_reset(ndev);
1279 if (ret)
f738a13d 1280 return ret;
86a74ff2 1281
55754f19
SH		 1282 if (mdp->cd->rmiimode)
1283 sh_eth_write(ndev, 0x1, RMIIMODE);
1284
b0ca2a21
NI		 1285 /* Descriptor format */
1286 sh_eth_ring_format(ndev);
380af9e3 1287 if (mdp->cd->rpadir)
4a55530f 1288 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1289
1290 /* all sh_eth int mask */
4a55530f 1291 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1292
10b9194f 1293#if defined(__LITTLE_ENDIAN)
380af9e3 1294 if (mdp->cd->hw_swap)
4a55530f 1295 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1296 else
b0ca2a21 1297#endif
4a55530f 1298 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1299
b0ca2a21 1300 /* FIFO size set */
4a55530f
YS		 1301 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1302 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1303
530aa2d0
BD		 1304 /* Frame recv control (enable multiple-packets per rx irq) */
1305 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1306
2ecbb783 1307 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
86a74ff2 1308
380af9e3 1309 if (mdp->cd->bculr)
4a55530f 1310 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1311
4a55530f 1312 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1313
380af9e3 1314 if (!mdp->cd->no_trimd)
4a55530f 1315 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1316
b0ca2a21 1317 /* Recv frame limit set register */
fdb37a7f
YS		 1318 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1319 RFLR);
86a74ff2 1320
4a55530f 1321 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
525b8075
YS		 1322 if (start)
1323 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1324
1325 /* PAUSE Prohibition */
4a55530f 1326 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1327 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1328
4a55530f 1329 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1330
380af9e3
YS		 1331 if (mdp->cd->set_rate)
1332 mdp->cd->set_rate(ndev);
1333
b0ca2a21 1334 /* E-MAC Status Register clear */
4a55530f 1335 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1336
1337 /* E-MAC Interrupt Enable register */
525b8075
YS		 1338 if (start)
1339 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1340
1341 /* Set MAC address */
1342 update_mac_address(ndev);
1343
1344 /* mask reset */
380af9e3 1345 if (mdp->cd->apr)
4a55530f 1346 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1347 if (mdp->cd->mpr)
4a55530f 1348 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1349 if (mdp->cd->tpauser)
4a55530f 1350 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1351
525b8075
YS		 1352 if (start) {
1353 /* Setting the Rx mode will start the Rx process. */
1354 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1355
525b8075
YS		 1356 netif_start_queue(ndev);
1357 }
86a74ff2
NI		 1358
1359 return ret;
1360}
1361
1362/* free Tx skb function */
1363static int sh_eth_txfree(struct net_device *ndev)
1364{
1365 struct sh_eth_private *mdp = netdev_priv(ndev);
1366 struct sh_eth_txdesc *txdesc;
128296fc 1367 int free_num = 0;
86a74ff2
NI		 1368 int entry = 0;
1369
1370 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1371 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1372 txdesc = &mdp->tx_ring[entry];
71557a37 1373 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 1374 break;
1375 /* Free the original skb. */
1376 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1377 dma_unmap_single(&ndev->dev, txdesc->addr,
1378 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1379 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1380 mdp->tx_skbuff[entry] = NULL;
128296fc 1381 free_num++;
86a74ff2 1382 }
71557a37 1383 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1384 if (entry >= mdp->num_tx_ring - 1)
71557a37 1385 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1386
bb7d92e3
ED		 1387 ndev->stats.tx_packets++;
1388 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2 1389 }
128296fc 1390 return free_num;
86a74ff2
NI		 1391}
1392
1393/* Packet receive function */
3719109d 1394static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1395{
1396 struct sh_eth_private *mdp = netdev_priv(ndev);
1397 struct sh_eth_rxdesc *rxdesc;
1398
525b8075
YS		 1399 int entry = mdp->cur_rx % mdp->num_rx_ring;
1400 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
86a74ff2
NI		 1401 struct sk_buff *skb;
1402 u16 pkt_len = 0;
380af9e3 1403 u32 desc_status;
86a74ff2
NI		 1404
1405 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 1406 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1407 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1408 pkt_len = rxdesc->frame_length;
1409
1410 if (--boguscnt < 0)
1411 break;
1412
4f809cea 1413 if (*quota <= 0)
3719109d 1414 break;
4f809cea 1415
3719109d
SS		 1416 (*quota)--;
1417
86a74ff2 1418 if (!(desc_status & RDFEND))
bb7d92e3 1419 ndev->stats.rx_length_errors++;
86a74ff2 1420
128296fc 1421 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1422 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
db893473
SH		 1423 * bit 0. However, in case of the R8A7740, R8A779x, and
1424 * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1425 * driver needs right shifting by 16.
dd019897 1426 */
ac8025a6
SS		 1427 if (mdp->cd->shift_rd0)
1428 desc_status >>= 16;
dd019897 1429
86a74ff2
NI		 1430 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1431 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1432 ndev->stats.rx_errors++;
86a74ff2 1433 if (desc_status & RD_RFS1)
bb7d92e3 1434 ndev->stats.rx_crc_errors++;
86a74ff2 1435 if (desc_status & RD_RFS2)
bb7d92e3 1436 ndev->stats.rx_frame_errors++;
86a74ff2 1437 if (desc_status & RD_RFS3)
bb7d92e3 1438 ndev->stats.rx_length_errors++;
86a74ff2 1439 if (desc_status & RD_RFS4)
bb7d92e3 1440 ndev->stats.rx_length_errors++;
86a74ff2 1441 if (desc_status & RD_RFS6)
bb7d92e3 1442 ndev->stats.rx_missed_errors++;
86a74ff2 1443 if (desc_status & RD_RFS10)
bb7d92e3 1444 ndev->stats.rx_over_errors++;
86a74ff2 1445 } else {
380af9e3
YS		 1446 if (!mdp->cd->hw_swap)
1447 sh_eth_soft_swap(
1448 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1449 pkt_len + 2);
86a74ff2
NI		 1450 skb = mdp->rx_skbuff[entry];
1451 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1452 if (mdp->cd->rpadir)
1453 skb_reserve(skb, NET_IP_ALIGN);
7db8e0c1
KA		 1454 dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1455 mdp->rx_buf_sz,
1456 DMA_FROM_DEVICE);
86a74ff2
NI		 1457 skb_put(skb, pkt_len);
1458 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1459 netif_receive_skb(skb);
bb7d92e3
ED		 1460 ndev->stats.rx_packets++;
1461 ndev->stats.rx_bytes += pkt_len;
86a74ff2 1462 }
71557a37 1463 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
525b8075 1464 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1465 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1466 }
1467
1468 /* Refill the Rx ring buffers. */
1469 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1470 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1471 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 1472 /* The size of the buffer is 16 byte boundary. */
0029d64a 1473 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 1474
86a74ff2 1475 if (mdp->rx_skbuff[entry] == NULL) {
dae2e9f4 1476 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1477 mdp->rx_skbuff[entry] = skb;
1478 if (skb == NULL)
1479 break; /* Better luck next round. */
bb7d92e3 1480 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
128296fc 1481 DMA_FROM_DEVICE);
380af9e3
YS		 1482 sh_eth_set_receive_align(skb);
1483
bc8acf2c 1484 skb_checksum_none_assert(skb);
0029d64a 1485 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 1486 }
525b8075 1487 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1488 rxdesc->status |=
71557a37 1489 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 1490 else
1491 rxdesc->status |=
71557a37 1492 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1493 }
1494
1495 /* Restart Rx engine if stopped. */
1496 /* If we don't need to check status, don't. -KDU */
79fba9f5 1497 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1498 /* fix the values for the next receiving if RDE is set */
128296fc
SS		 1499 if (intr_status & EESR_RDE) {
1500 u32 count = (sh_eth_read(ndev, RDFAR) -
1501 sh_eth_read(ndev, RDLAR)) >> 4;
1502
1503 mdp->cur_rx = count;
1504 mdp->dirty_rx = count;
1505 }
4a55530f 1506 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1507 }
86a74ff2 1508
4f809cea 1509 return *quota <= 0;
86a74ff2
NI		 1510}
1511
4a55530f 1512static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1513{
1514 /* disable tx and rx */
4a55530f
YS		 1515 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1516 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1517}
1518
4a55530f 1519static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1520{
1521 /* enable tx and rx */
4a55530f
YS		 1522 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1523 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1524}
1525
86a74ff2
NI		 1526/* error control function */
1527static void sh_eth_error(struct net_device *ndev, int intr_status)
1528{
1529 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1530 u32 felic_stat;
380af9e3
YS		 1531 u32 link_stat;
1532 u32 mask;
86a74ff2
NI		 1533
1534 if (intr_status & EESR_ECI) {
4a55530f
YS		 1535 felic_stat = sh_eth_read(ndev, ECSR);
1536 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1537 if (felic_stat & ECSR_ICD)
bb7d92e3 1538 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1539 if (felic_stat & ECSR_LCHNG) {
1540 /* Link Changed */
4923576b 1541 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1542 goto ignore_link;
380af9e3 1543 } else {
4a55530f 1544 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1545 if (mdp->ether_link_active_low)
1546 link_stat = ~link_stat;
380af9e3 1547 }
128296fc 1548 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1549 sh_eth_rcv_snd_disable(ndev);
128296fc 1550 } else {
86a74ff2 1551 /* Link Up */
4a55530f 1552 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
128296fc
SS		 1553 ~DMAC_M_ECI, EESIPR);
1554 /* clear int */
4a55530f 1555 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
128296fc 1556 ECSR);
4a55530f 1557 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
128296fc 1558 DMAC_M_ECI, EESIPR);
86a74ff2 1559 /* enable tx and rx */
4a55530f 1560 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1561 }
1562 }
1563 }
1564
1e1b812b 1565ignore_link:
86a74ff2 1566 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1567 /* Unused write back interrupt */
1568 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1569 ndev->stats.tx_aborted_errors++;
8d5009f6 1570 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1571 }
86a74ff2
NI		 1572 }
1573
1574 if (intr_status & EESR_RABT) {
1575 /* Receive Abort int */
1576 if (intr_status & EESR_RFRMER) {
1577 /* Receive Frame Overflow int */
bb7d92e3 1578 ndev->stats.rx_frame_errors++;
8d5009f6 1579 netif_err(mdp, rx_err, ndev, "Receive Abort\n");
86a74ff2
NI		 1580 }
1581 }
380af9e3 1582
dc19e4e5
NI		 1583 if (intr_status & EESR_TDE) {
1584 /* Transmit Descriptor Empty int */
bb7d92e3 1585 ndev->stats.tx_fifo_errors++;
8d5009f6 1586 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1587 }
1588
1589 if (intr_status & EESR_TFE) {
1590 /* FIFO under flow */
bb7d92e3 1591 ndev->stats.tx_fifo_errors++;
8d5009f6 1592 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1593 }
1594
1595 if (intr_status & EESR_RDE) {
1596 /* Receive Descriptor Empty int */
bb7d92e3 1597 ndev->stats.rx_over_errors++;
8d5009f6 1598 netif_err(mdp, rx_err, ndev, "Receive Descriptor Empty\n");
86a74ff2 1599 }
dc19e4e5 1600
86a74ff2
NI		 1601 if (intr_status & EESR_RFE) {
1602 /* Receive FIFO Overflow int */
bb7d92e3 1603 ndev->stats.rx_fifo_errors++;
8d5009f6 1604 netif_err(mdp, rx_err, ndev, "Receive FIFO Overflow\n");
dc19e4e5
NI		 1605 }
1606
1607 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1608 /* Address Error */
bb7d92e3 1609 ndev->stats.tx_fifo_errors++;
8d5009f6 1610 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1611 }
380af9e3
YS		 1612
1613 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1614 if (mdp->cd->no_ade)
1615 mask &= ~EESR_ADE;
1616 if (intr_status & mask) {
86a74ff2 1617 /* Tx error */
4a55530f 1618 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1619
86a74ff2 1620 /* dmesg */
da246855
SS		 1621 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1622 intr_status, mdp->cur_tx, mdp->dirty_tx,
1623 (u32)ndev->state, edtrr);
86a74ff2
NI		 1624 /* dirty buffer free */
1625 sh_eth_txfree(ndev);
1626
1627 /* SH7712 BUG */
c5ed5368 1628 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1629 /* tx dma start */
c5ed5368 1630 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1631 }
1632 /* wakeup */
1633 netif_wake_queue(ndev);
1634 }
1635}
1636
1637static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1638{
1639 struct net_device *ndev = netdev;
1640 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1641 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1642 irqreturn_t ret = IRQ_NONE;
3719109d 1643 unsigned long intr_status, intr_enable;
86a74ff2 1644
86a74ff2
NI		 1645 spin_lock(&mdp->lock);
1646
3893b273 1647 /* Get interrupt status */
4a55530f 1648 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1649 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1650 * enabled since it's the one that comes thru regardless of the mask,
1651 * and we need to fully handle it in sh_eth_error() in order to quench
1652 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1653 */
3719109d
SS		 1654 intr_enable = sh_eth_read(ndev, EESIPR);
1655 intr_status &= intr_enable | DMAC_M_ECI;
1656 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1657 ret = IRQ_HANDLED;
3719109d 1658 else
0e0fde3c 1659 goto other_irq;
86a74ff2 1660
3719109d
SS		 1661 if (intr_status & EESR_RX_CHECK) {
1662 if (napi_schedule_prep(&mdp->napi)) {
1663 /* Mask Rx interrupts */
1664 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1665 EESIPR);
1666 __napi_schedule(&mdp->napi);
1667 } else {
da246855
SS		 1668 netdev_warn(ndev,
1669 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1670 intr_status, intr_enable);
3719109d
SS		 1671 }
1672 }
86a74ff2 1673
b0ca2a21 1674 /* Tx Check */
380af9e3 1675 if (intr_status & cd->tx_check) {
3719109d
SS		 1676 /* Clear Tx interrupts */
1677 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1678
86a74ff2
NI		 1679 sh_eth_txfree(ndev);
1680 netif_wake_queue(ndev);
1681 }
1682
3719109d
SS		 1683 if (intr_status & cd->eesr_err_check) {
1684 /* Clear error interrupts */
1685 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1686
86a74ff2 1687 sh_eth_error(ndev, intr_status);
3719109d 1688 }
86a74ff2 1689
0e0fde3c 1690other_irq:
86a74ff2
NI		 1691 spin_unlock(&mdp->lock);
1692
0e0fde3c 1693 return ret;
86a74ff2
NI		 1694}
1695
3719109d
SS		 1696static int sh_eth_poll(struct napi_struct *napi, int budget)
1697{
1698 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1699 napi);
1700 struct net_device *ndev = napi->dev;
1701 int quota = budget;
1702 unsigned long intr_status;
1703
1704 for (;;) {
1705 intr_status = sh_eth_read(ndev, EESR);
1706 if (!(intr_status & EESR_RX_CHECK))
1707 break;
1708 /* Clear Rx interrupts */
1709 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1710
1711 if (sh_eth_rx(ndev, intr_status, &quota))
1712 goto out;
1713 }
1714
1715 napi_complete(napi);
1716
1717 /* Reenable Rx interrupts */
1718 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1719out:
1720 return budget - quota;
1721}
1722
86a74ff2
NI		 1723/* PHY state control function */
1724static void sh_eth_adjust_link(struct net_device *ndev)
1725{
1726 struct sh_eth_private *mdp = netdev_priv(ndev);
1727 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1728 int new_state = 0;
1729
3340d2aa 1730 if (phydev->link) {
86a74ff2
NI		 1731 if (phydev->duplex != mdp->duplex) {
1732 new_state = 1;
1733 mdp->duplex = phydev->duplex;
380af9e3
YS		 1734 if (mdp->cd->set_duplex)
1735 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1736 }
1737
1738 if (phydev->speed != mdp->speed) {
1739 new_state = 1;
1740 mdp->speed = phydev->speed;
380af9e3
YS		 1741 if (mdp->cd->set_rate)
1742 mdp->cd->set_rate(ndev);
86a74ff2 1743 }
3340d2aa 1744 if (!mdp->link) {
91a56152 1745 sh_eth_write(ndev,
128296fc
SS		 1746 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1747 ECMR);
86a74ff2
NI		 1748 new_state = 1;
1749 mdp->link = phydev->link;
1e1b812b
SS		 1750 if (mdp->cd->no_psr || mdp->no_ether_link)
1751 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1752 }
1753 } else if (mdp->link) {
1754 new_state = 1;
3340d2aa 1755 mdp->link = 0;
86a74ff2
NI		 1756 mdp->speed = 0;
1757 mdp->duplex = -1;
1e1b812b
SS		 1758 if (mdp->cd->no_psr || mdp->no_ether_link)
1759 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1760 }
1761
dc19e4e5 1762 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1763 phy_print_status(phydev);
1764}
1765
1766/* PHY init function */
1767static int sh_eth_phy_init(struct net_device *ndev)
1768{
702eca02 1769 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1770 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1771 struct phy_device *phydev = NULL;
1772
3340d2aa 1773 mdp->link = 0;
86a74ff2
NI		 1774 mdp->speed = 0;
1775 mdp->duplex = -1;
1776
1777 /* Try connect to PHY */
702eca02
BD		 1778 if (np) {
1779 struct device_node *pn;
1780
1781 pn = of_parse_phandle(np, "phy-handle", 0);
1782 phydev = of_phy_connect(ndev, pn,
1783 sh_eth_adjust_link, 0,
1784 mdp->phy_interface);
1785
1786 if (!phydev)
1787 phydev = ERR_PTR(-ENOENT);
1788 } else {
1789 char phy_id[MII_BUS_ID_SIZE + 3];
1790
1791 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1792 mdp->mii_bus->id, mdp->phy_id);
1793
1794 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1795 mdp->phy_interface);
1796 }
1797
86a74ff2 1798 if (IS_ERR(phydev)) {
da246855 1799 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1800 return PTR_ERR(phydev);
1801 }
380af9e3 1802
da246855
SS		 1803 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1804 phydev->addr, phydev->irq, phydev->drv->name);
86a74ff2
NI		 1805
1806 mdp->phydev = phydev;
1807
1808 return 0;
1809}
1810
1811/* PHY control start function */
1812static int sh_eth_phy_start(struct net_device *ndev)
1813{
1814 struct sh_eth_private *mdp = netdev_priv(ndev);
1815 int ret;
1816
1817 ret = sh_eth_phy_init(ndev);
1818 if (ret)
1819 return ret;
1820
86a74ff2
NI		 1821 phy_start(mdp->phydev);
1822
1823 return 0;
1824}
1825
dc19e4e5 1826static int sh_eth_get_settings(struct net_device *ndev,
128296fc 1827 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1828{
1829 struct sh_eth_private *mdp = netdev_priv(ndev);
1830 unsigned long flags;
1831 int ret;
1832
1833 spin_lock_irqsave(&mdp->lock, flags);
1834 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1835 spin_unlock_irqrestore(&mdp->lock, flags);
1836
1837 return ret;
1838}
1839
1840static int sh_eth_set_settings(struct net_device *ndev,
128296fc 1841 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1842{
1843 struct sh_eth_private *mdp = netdev_priv(ndev);
1844 unsigned long flags;
1845 int ret;
dc19e4e5
NI		 1846
1847 spin_lock_irqsave(&mdp->lock, flags);
1848
1849 /* disable tx and rx */
4a55530f 1850 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1851
1852 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1853 if (ret)
1854 goto error_exit;
1855
1856 if (ecmd->duplex == DUPLEX_FULL)
1857 mdp->duplex = 1;
1858 else
1859 mdp->duplex = 0;
1860
1861 if (mdp->cd->set_duplex)
1862 mdp->cd->set_duplex(ndev);
1863
1864error_exit:
1865 mdelay(1);
1866
1867 /* enable tx and rx */
4a55530f 1868 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1869
1870 spin_unlock_irqrestore(&mdp->lock, flags);
1871
1872 return ret;
1873}
1874
1875static int sh_eth_nway_reset(struct net_device *ndev)
1876{
1877 struct sh_eth_private *mdp = netdev_priv(ndev);
1878 unsigned long flags;
1879 int ret;
1880
1881 spin_lock_irqsave(&mdp->lock, flags);
1882 ret = phy_start_aneg(mdp->phydev);
1883 spin_unlock_irqrestore(&mdp->lock, flags);
1884
1885 return ret;
1886}
1887
1888static u32 sh_eth_get_msglevel(struct net_device *ndev)
1889{
1890 struct sh_eth_private *mdp = netdev_priv(ndev);
1891 return mdp->msg_enable;
1892}
1893
1894static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1895{
1896 struct sh_eth_private *mdp = netdev_priv(ndev);
1897 mdp->msg_enable = value;
1898}
1899
1900static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1901 "rx_current", "tx_current",
1902 "rx_dirty", "tx_dirty",
1903};
1904#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1905
1906static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1907{
1908 switch (sset) {
1909 case ETH_SS_STATS:
1910 return SH_ETH_STATS_LEN;
1911 default:
1912 return -EOPNOTSUPP;
1913 }
1914}
1915
1916static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 1917 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 1918{
1919 struct sh_eth_private *mdp = netdev_priv(ndev);
1920 int i = 0;
1921
1922 /* device-specific stats */
1923 data[i++] = mdp->cur_rx;
1924 data[i++] = mdp->cur_tx;
1925 data[i++] = mdp->dirty_rx;
1926 data[i++] = mdp->dirty_tx;
1927}
1928
1929static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1930{
1931 switch (stringset) {
1932 case ETH_SS_STATS:
1933 memcpy(data, *sh_eth_gstrings_stats,
128296fc 1934 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 1935 break;
1936 }
1937}
1938
525b8075
YS		 1939static void sh_eth_get_ringparam(struct net_device *ndev,
1940 struct ethtool_ringparam *ring)
1941{
1942 struct sh_eth_private *mdp = netdev_priv(ndev);
1943
1944 ring->rx_max_pending = RX_RING_MAX;
1945 ring->tx_max_pending = TX_RING_MAX;
1946 ring->rx_pending = mdp->num_rx_ring;
1947 ring->tx_pending = mdp->num_tx_ring;
1948}
1949
1950static int sh_eth_set_ringparam(struct net_device *ndev,
1951 struct ethtool_ringparam *ring)
1952{
1953 struct sh_eth_private *mdp = netdev_priv(ndev);
1954 int ret;
1955
1956 if (ring->tx_pending > TX_RING_MAX ||
1957 ring->rx_pending > RX_RING_MAX ||
1958 ring->tx_pending < TX_RING_MIN ||
1959 ring->rx_pending < RX_RING_MIN)
1960 return -EINVAL;
1961 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1962 return -EINVAL;
1963
1964 if (netif_running(ndev)) {
1965 netif_tx_disable(ndev);
1966 /* Disable interrupts by clearing the interrupt mask. */
1967 sh_eth_write(ndev, 0x0000, EESIPR);
1968 /* Stop the chip's Tx and Rx processes. */
1969 sh_eth_write(ndev, 0, EDTRR);
1970 sh_eth_write(ndev, 0, EDRRR);
1971 synchronize_irq(ndev->irq);
1972 }
1973
1974 /* Free all the skbuffs in the Rx queue. */
1975 sh_eth_ring_free(ndev);
1976 /* Free DMA buffer */
1977 sh_eth_free_dma_buffer(mdp);
1978
1979 /* Set new parameters */
1980 mdp->num_rx_ring = ring->rx_pending;
1981 mdp->num_tx_ring = ring->tx_pending;
1982
1983 ret = sh_eth_ring_init(ndev);
1984 if (ret < 0) {
da246855 1985 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", __func__);
525b8075
YS		 1986 return ret;
1987 }
1988 ret = sh_eth_dev_init(ndev, false);
1989 if (ret < 0) {
da246855 1990 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", __func__);
525b8075
YS		 1991 return ret;
1992 }
1993
1994 if (netif_running(ndev)) {
1995 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1996 /* Setting the Rx mode will start the Rx process. */
1997 sh_eth_write(ndev, EDRRR_R, EDRRR);
1998 netif_wake_queue(ndev);
1999 }
2000
2001 return 0;
2002}
2003
9b07be4b 2004static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 2005 .get_settings = sh_eth_get_settings,
2006 .set_settings = sh_eth_set_settings,
9b07be4b 2007 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2008 .get_msglevel = sh_eth_get_msglevel,
2009 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2010 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2011 .get_strings = sh_eth_get_strings,
2012 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2013 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2014 .get_ringparam = sh_eth_get_ringparam,
2015 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 2016};
2017
86a74ff2
NI		 2018/* network device open function */
2019static int sh_eth_open(struct net_device *ndev)
2020{
2021 int ret = 0;
2022 struct sh_eth_private *mdp = netdev_priv(ndev);
2023
bcd5149d
MD		 2024 pm_runtime_get_sync(&mdp->pdev->dev);
2025
d2779e99
SS		 2026 napi_enable(&mdp->napi);
2027
a0607fd3 2028 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2029 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2030 if (ret) {
da246855 2031 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2032 goto out_napi_off;
86a74ff2
NI		 2033 }
2034
2035 /* Descriptor set */
2036 ret = sh_eth_ring_init(ndev);
2037 if (ret)
2038 goto out_free_irq;
2039
2040 /* device init */
525b8075 2041 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2042 if (ret)
2043 goto out_free_irq;
2044
2045 /* PHY control start*/
2046 ret = sh_eth_phy_start(ndev);
2047 if (ret)
2048 goto out_free_irq;
2049
86a74ff2
NI		 2050 return ret;
2051
2052out_free_irq:
2053 free_irq(ndev->irq, ndev);
d2779e99
SS		 2054out_napi_off:
2055 napi_disable(&mdp->napi);
bcd5149d 2056 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2057 return ret;
2058}
2059
2060/* Timeout function */
2061static void sh_eth_tx_timeout(struct net_device *ndev)
2062{
2063 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2064 struct sh_eth_rxdesc *rxdesc;
2065 int i;
2066
2067 netif_stop_queue(ndev);
2068
8d5009f6
SS		 2069 netif_err(mdp, timer, ndev,
2070 "transmit timed out, status %8.8x, resetting...\n",
2071 (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 2072
2073 /* tx_errors count up */
bb7d92e3 2074 ndev->stats.tx_errors++;
86a74ff2 2075
86a74ff2 2076 /* Free all the skbuffs in the Rx queue. */
525b8075 2077 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 2078 rxdesc = &mdp->rx_ring[i];
2079 rxdesc->status = 0;
2080 rxdesc->addr = 0xBADF00D0;
2081 if (mdp->rx_skbuff[i])
2082 dev_kfree_skb(mdp->rx_skbuff[i]);
2083 mdp->rx_skbuff[i] = NULL;
2084 }
525b8075 2085 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 2086 if (mdp->tx_skbuff[i])
2087 dev_kfree_skb(mdp->tx_skbuff[i]);
2088 mdp->tx_skbuff[i] = NULL;
2089 }
2090
2091 /* device init */
525b8075 2092 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2093}
2094
2095/* Packet transmit function */
2096static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2097{
2098 struct sh_eth_private *mdp = netdev_priv(ndev);
2099 struct sh_eth_txdesc *txdesc;
2100 u32 entry;
fb5e2f9b 2101 unsigned long flags;
86a74ff2
NI		 2102
2103 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2104 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2105 if (!sh_eth_txfree(ndev)) {
8d5009f6 2106 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2107 netif_stop_queue(ndev);
2108 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2109 return NETDEV_TX_BUSY;
86a74ff2
NI		 2110 }
2111 }
2112 spin_unlock_irqrestore(&mdp->lock, flags);
2113
525b8075 2114 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2115 mdp->tx_skbuff[entry] = skb;
2116 txdesc = &mdp->tx_ring[entry];
86a74ff2 2117 /* soft swap. */
380af9e3
YS		 2118 if (!mdp->cd->hw_swap)
2119 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2120 skb->len + 2);
31fcb99d
YS		 2121 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2122 DMA_TO_DEVICE);
730c8c69
SS		 2123 if (skb->len < ETH_ZLEN)
2124 txdesc->buffer_length = ETH_ZLEN;
86a74ff2
NI		 2125 else
2126 txdesc->buffer_length = skb->len;
2127
525b8075 2128 if (entry >= mdp->num_tx_ring - 1)
71557a37 2129 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 2130 else
71557a37 2131 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 2132
2133 mdp->cur_tx++;
2134
c5ed5368
YS		 2135 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2136 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2137
6ed10654 2138 return NETDEV_TX_OK;
86a74ff2
NI		 2139}
2140
2141/* device close function */
2142static int sh_eth_close(struct net_device *ndev)
2143{
2144 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2145
2146 netif_stop_queue(ndev);
2147
2148 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 2149 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 2150
2151 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 2152 sh_eth_write(ndev, 0, EDTRR);
2153 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 2154
2155 /* PHY Disconnect */
2156 if (mdp->phydev) {
2157 phy_stop(mdp->phydev);
2158 phy_disconnect(mdp->phydev);
2159 }
2160
2161 free_irq(ndev->irq, ndev);
2162
d2779e99
SS		 2163 napi_disable(&mdp->napi);
2164
86a74ff2
NI		 2165 /* Free all the skbuffs in the Rx queue. */
2166 sh_eth_ring_free(ndev);
2167
2168 /* free DMA buffer */
91c77550 2169 sh_eth_free_dma_buffer(mdp);
86a74ff2 2170
bcd5149d
MD		 2171 pm_runtime_put_sync(&mdp->pdev->dev);
2172
86a74ff2
NI		 2173 return 0;
2174}
2175
2176static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2177{
2178 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 2179
db893473
SH		 2180 if (sh_eth_is_rz_fast_ether(mdp))
2181 return &ndev->stats;
2182
bcd5149d
MD		 2183 pm_runtime_get_sync(&mdp->pdev->dev);
2184
bb7d92e3 2185 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
4a55530f 2186 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
bb7d92e3 2187 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
4a55530f 2188 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
bb7d92e3 2189 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
4a55530f 2190 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
c5ed5368 2191 if (sh_eth_is_gether(mdp)) {
bb7d92e3 2192 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
c5ed5368 2193 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
bb7d92e3 2194 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
c5ed5368
YS		 2195 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2196 } else {
bb7d92e3 2197 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
c5ed5368
YS		 2198 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2199 }
bcd5149d
MD		 2200 pm_runtime_put_sync(&mdp->pdev->dev);
2201
bb7d92e3 2202 return &ndev->stats;
86a74ff2
NI		 2203}
2204
bb7d92e3 2205/* ioctl to device function */
128296fc 2206static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2
NI		 2207{
2208 struct sh_eth_private *mdp = netdev_priv(ndev);
2209 struct phy_device *phydev = mdp->phydev;
2210
2211 if (!netif_running(ndev))
2212 return -EINVAL;
2213
2214 if (!phydev)
2215 return -ENODEV;
2216
28b04113 2217 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2218}
2219
6743fe6d
YS		 2220/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2221static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2222 int entry)
2223{
2224 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2225}
2226
2227static u32 sh_eth_tsu_get_post_mask(int entry)
2228{
2229 return 0x0f << (28 - ((entry % 8) * 4));
2230}
2231
2232static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2233{
2234 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2235}
2236
2237static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2238 int entry)
2239{
2240 struct sh_eth_private *mdp = netdev_priv(ndev);
2241 u32 tmp;
2242 void *reg_offset;
2243
2244 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2245 tmp = ioread32(reg_offset);
2246 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2247}
2248
2249static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2250 int entry)
2251{
2252 struct sh_eth_private *mdp = netdev_priv(ndev);
2253 u32 post_mask, ref_mask, tmp;
2254 void *reg_offset;
2255
2256 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2257 post_mask = sh_eth_tsu_get_post_mask(entry);
2258 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2259
2260 tmp = ioread32(reg_offset);
2261 iowrite32(tmp & ~post_mask, reg_offset);
2262
2263 /* If other port enables, the function returns "true" */
2264 return tmp & ref_mask;
2265}
2266
2267static int sh_eth_tsu_busy(struct net_device *ndev)
2268{
2269 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2270 struct sh_eth_private *mdp = netdev_priv(ndev);
2271
2272 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2273 udelay(10);
2274 timeout--;
2275 if (timeout <= 0) {
da246855 2276 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2277 return -ETIMEDOUT;
2278 }
2279 }
2280
2281 return 0;
2282}
2283
2284static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2285 const u8 *addr)
2286{
2287 u32 val;
2288
2289 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2290 iowrite32(val, reg);
2291 if (sh_eth_tsu_busy(ndev) < 0)
2292 return -EBUSY;
2293
2294 val = addr[4] << 8 | addr[5];
2295 iowrite32(val, reg + 4);
2296 if (sh_eth_tsu_busy(ndev) < 0)
2297 return -EBUSY;
2298
2299 return 0;
2300}
2301
2302static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2303{
2304 u32 val;
2305
2306 val = ioread32(reg);
2307 addr[0] = (val >> 24) & 0xff;
2308 addr[1] = (val >> 16) & 0xff;
2309 addr[2] = (val >> 8) & 0xff;
2310 addr[3] = val & 0xff;
2311 val = ioread32(reg + 4);
2312 addr[4] = (val >> 8) & 0xff;
2313 addr[5] = val & 0xff;
2314}
2315
2316
2317static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2318{
2319 struct sh_eth_private *mdp = netdev_priv(ndev);
2320 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2321 int i;
2322 u8 c_addr[ETH_ALEN];
2323
2324 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2325 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2326 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2327 return i;
2328 }
2329
2330 return -ENOENT;
2331}
2332
2333static int sh_eth_tsu_find_empty(struct net_device *ndev)
2334{
2335 u8 blank[ETH_ALEN];
2336 int entry;
2337
2338 memset(blank, 0, sizeof(blank));
2339 entry = sh_eth_tsu_find_entry(ndev, blank);
2340 return (entry < 0) ? -ENOMEM : entry;
2341}
2342
2343static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2344 int entry)
2345{
2346 struct sh_eth_private *mdp = netdev_priv(ndev);
2347 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2348 int ret;
2349 u8 blank[ETH_ALEN];
2350
2351 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2352 ~(1 << (31 - entry)), TSU_TEN);
2353
2354 memset(blank, 0, sizeof(blank));
2355 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2356 if (ret < 0)
2357 return ret;
2358 return 0;
2359}
2360
2361static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2362{
2363 struct sh_eth_private *mdp = netdev_priv(ndev);
2364 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2365 int i, ret;
2366
2367 if (!mdp->cd->tsu)
2368 return 0;
2369
2370 i = sh_eth_tsu_find_entry(ndev, addr);
2371 if (i < 0) {
2372 /* No entry found, create one */
2373 i = sh_eth_tsu_find_empty(ndev);
2374 if (i < 0)
2375 return -ENOMEM;
2376 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2377 if (ret < 0)
2378 return ret;
2379
2380 /* Enable the entry */
2381 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2382 (1 << (31 - i)), TSU_TEN);
2383 }
2384
2385 /* Entry found or created, enable POST */
2386 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2387
2388 return 0;
2389}
2390
2391static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2392{
2393 struct sh_eth_private *mdp = netdev_priv(ndev);
2394 int i, ret;
2395
2396 if (!mdp->cd->tsu)
2397 return 0;
2398
2399 i = sh_eth_tsu_find_entry(ndev, addr);
2400 if (i) {
2401 /* Entry found */
2402 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2403 goto done;
2404
2405 /* Disable the entry if both ports was disabled */
2406 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2407 if (ret < 0)
2408 return ret;
2409 }
2410done:
2411 return 0;
2412}
2413
2414static int sh_eth_tsu_purge_all(struct net_device *ndev)
2415{
2416 struct sh_eth_private *mdp = netdev_priv(ndev);
2417 int i, ret;
2418
2419 if (unlikely(!mdp->cd->tsu))
2420 return 0;
2421
2422 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2423 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2424 continue;
2425
2426 /* Disable the entry if both ports was disabled */
2427 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2428 if (ret < 0)
2429 return ret;
2430 }
2431
2432 return 0;
2433}
2434
2435static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2436{
2437 struct sh_eth_private *mdp = netdev_priv(ndev);
2438 u8 addr[ETH_ALEN];
2439 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2440 int i;
2441
2442 if (unlikely(!mdp->cd->tsu))
2443 return;
2444
2445 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2446 sh_eth_tsu_read_entry(reg_offset, addr);
2447 if (is_multicast_ether_addr(addr))
2448 sh_eth_tsu_del_entry(ndev, addr);
2449 }
2450}
2451
86a74ff2
NI		 2452/* Multicast reception directions set */
2453static void sh_eth_set_multicast_list(struct net_device *ndev)
2454{
6743fe6d
YS		 2455 struct sh_eth_private *mdp = netdev_priv(ndev);
2456 u32 ecmr_bits;
2457 int mcast_all = 0;
2458 unsigned long flags;
2459
2460 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2461 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2462 * Depending on ndev->flags, set PRM or clear MCT
2463 */
2464 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2465
2466 if (!(ndev->flags & IFF_MULTICAST)) {
2467 sh_eth_tsu_purge_mcast(ndev);
2468 mcast_all = 1;
2469 }
2470 if (ndev->flags & IFF_ALLMULTI) {
2471 sh_eth_tsu_purge_mcast(ndev);
2472 ecmr_bits &= ~ECMR_MCT;
2473 mcast_all = 1;
2474 }
2475
86a74ff2 2476 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2477 sh_eth_tsu_purge_all(ndev);
2478 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2479 } else if (mdp->cd->tsu) {
2480 struct netdev_hw_addr *ha;
2481 netdev_for_each_mc_addr(ha, ndev) {
2482 if (mcast_all && is_multicast_ether_addr(ha->addr))
2483 continue;
2484
2485 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2486 if (!mcast_all) {
2487 sh_eth_tsu_purge_mcast(ndev);
2488 ecmr_bits &= ~ECMR_MCT;
2489 mcast_all = 1;
2490 }
2491 }
2492 }
86a74ff2
NI		 2493 } else {
2494 /* Normal, unicast/broadcast-only mode. */
6743fe6d 2495 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
86a74ff2 2496 }
6743fe6d
YS		 2497
2498 /* update the ethernet mode */
2499 sh_eth_write(ndev, ecmr_bits, ECMR);
2500
2501 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2502}
71cc7c37
YS		 2503
2504static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2505{
2506 if (!mdp->port)
2507 return TSU_VTAG0;
2508 else
2509 return TSU_VTAG1;
2510}
2511
80d5c368
PM		 2512static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2513 __be16 proto, u16 vid)
71cc7c37
YS		 2514{
2515 struct sh_eth_private *mdp = netdev_priv(ndev);
2516 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2517
2518 if (unlikely(!mdp->cd->tsu))
2519 return -EPERM;
2520
2521 /* No filtering if vid = 0 */
2522 if (!vid)
2523 return 0;
2524
2525 mdp->vlan_num_ids++;
2526
128296fc 2527 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2528 * already enabled, the driver disables it and the filte
2529 */
2530 if (mdp->vlan_num_ids > 1) {
2531 /* disable VLAN filter */
2532 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2533 return 0;
2534 }
2535
2536 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2537 vtag_reg_index);
2538
2539 return 0;
2540}
2541
80d5c368
PM		 2542static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2543 __be16 proto, u16 vid)
71cc7c37
YS		 2544{
2545 struct sh_eth_private *mdp = netdev_priv(ndev);
2546 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2547
2548 if (unlikely(!mdp->cd->tsu))
2549 return -EPERM;
2550
2551 /* No filtering if vid = 0 */
2552 if (!vid)
2553 return 0;
2554
2555 mdp->vlan_num_ids--;
2556 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2557
2558 return 0;
2559}
86a74ff2
NI		 2560
2561/* SuperH's TSU register init function */
4a55530f 2562static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2563{
db893473
SH		 2564 if (sh_eth_is_rz_fast_ether(mdp)) {
2565 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2566 return;
2567 }
2568
4a55530f
YS		 2569 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2570 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2571 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2572 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2573 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2574 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2575 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2576 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2577 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2578 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2579 if (sh_eth_is_gether(mdp)) {
2580 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2581 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2582 } else {
2583 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2584 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2585 }
4a55530f
YS		 2586 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2587 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2588 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2589 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2590 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2591 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2592 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2593}
2594
2595/* MDIO bus release function */
bd920ff5 2596static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2597{
86a74ff2 2598 /* unregister mdio bus */
bd920ff5 2599 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2600
2601 /* free bitbang info */
bd920ff5 2602 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2603
2604 return 0;
2605}
2606
2607/* MDIO bus init function */
bd920ff5 2608static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2609 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2610{
2611 int ret, i;
2612 struct bb_info *bitbang;
bd920ff5 2613 struct platform_device *pdev = mdp->pdev;
aa8d4225 2614 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2615
2616 /* create bit control struct for PHY */
aa8d4225 2617 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2618 if (!bitbang)
2619 return -ENOMEM;
86a74ff2
NI		 2620
2621 /* bitbang init */
ae70644d 2622 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2623 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2624 bitbang->mdi_msk = PIR_MDI;
2625 bitbang->mdo_msk = PIR_MDO;
2626 bitbang->mmd_msk = PIR_MMD;
2627 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2628 bitbang->ctrl.ops = &bb_ops;
2629
c2e07b3a 2630 /* MII controller setting */
86a74ff2 2631 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2632 if (!mdp->mii_bus)
2633 return -ENOMEM;
86a74ff2
NI		 2634
2635 /* Hook up MII support for ethtool */
2636 mdp->mii_bus->name = "sh_mii";
a5bd6060 2637 mdp->mii_bus->parent = dev;
5278fb54 2638 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2639 pdev->name, pdev->id);
86a74ff2
NI		 2640
2641 /* PHY IRQ */
86b5d251
SS		 2642 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2643 GFP_KERNEL);
86a74ff2
NI		 2644 if (!mdp->mii_bus->irq) {
2645 ret = -ENOMEM;
2646 goto out_free_bus;
2647 }
2648
bd920ff5
LP		 2649 /* register MDIO bus */
2650 if (dev->of_node) {
2651 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02
BD		 2652 } else {
2653 for (i = 0; i < PHY_MAX_ADDR; i++)
2654 mdp->mii_bus->irq[i] = PHY_POLL;
2655 if (pd->phy_irq > 0)
2656 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2657
2658 ret = mdiobus_register(mdp->mii_bus);
2659 }
2660
86a74ff2 2661 if (ret)
d5e07e69 2662 goto out_free_bus;
86a74ff2 2663
86a74ff2
NI		 2664 return 0;
2665
86a74ff2 2666out_free_bus:
298cf9be 2667 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2668 return ret;
2669}
2670
4a55530f
YS		 2671static const u16 *sh_eth_get_register_offset(int register_type)
2672{
2673 const u16 *reg_offset = NULL;
2674
2675 switch (register_type) {
2676 case SH_ETH_REG_GIGABIT:
2677 reg_offset = sh_eth_offset_gigabit;
2678 break;
db893473
SH		 2679 case SH_ETH_REG_FAST_RZ:
2680 reg_offset = sh_eth_offset_fast_rz;
2681 break;
a3f109bd
SS		 2682 case SH_ETH_REG_FAST_RCAR:
2683 reg_offset = sh_eth_offset_fast_rcar;
2684 break;
4a55530f
YS		 2685 case SH_ETH_REG_FAST_SH4:
2686 reg_offset = sh_eth_offset_fast_sh4;
2687 break;
2688 case SH_ETH_REG_FAST_SH3_SH2:
2689 reg_offset = sh_eth_offset_fast_sh3_sh2;
2690 break;
2691 default:
4a55530f
YS		 2692 break;
2693 }
2694
2695 return reg_offset;
2696}
2697
8f728d79 2698static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2699 .ndo_open = sh_eth_open,
2700 .ndo_stop = sh_eth_close,
2701 .ndo_start_xmit = sh_eth_start_xmit,
2702 .ndo_get_stats = sh_eth_get_stats,
ebf84eaa
AB		 2703 .ndo_tx_timeout = sh_eth_tx_timeout,
2704 .ndo_do_ioctl = sh_eth_do_ioctl,
2705 .ndo_validate_addr = eth_validate_addr,
2706 .ndo_set_mac_address = eth_mac_addr,
2707 .ndo_change_mtu = eth_change_mtu,
2708};
2709
8f728d79
SS		 2710static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2711 .ndo_open = sh_eth_open,
2712 .ndo_stop = sh_eth_close,
2713 .ndo_start_xmit = sh_eth_start_xmit,
2714 .ndo_get_stats = sh_eth_get_stats,
2715 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2716 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2717 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2718 .ndo_tx_timeout = sh_eth_tx_timeout,
2719 .ndo_do_ioctl = sh_eth_do_ioctl,
2720 .ndo_validate_addr = eth_validate_addr,
2721 .ndo_set_mac_address = eth_mac_addr,
2722 .ndo_change_mtu = eth_change_mtu,
2723};
2724
b356e978
SS		 2725#ifdef CONFIG_OF
2726static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2727{
2728 struct device_node *np = dev->of_node;
2729 struct sh_eth_plat_data *pdata;
b356e978
SS		 2730 const char *mac_addr;
2731
2732 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2733 if (!pdata)
2734 return NULL;
2735
2736 pdata->phy_interface = of_get_phy_mode(np);
2737
b356e978
SS		 2738 mac_addr = of_get_mac_address(np);
2739 if (mac_addr)
2740 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2741
2742 pdata->no_ether_link =
2743 of_property_read_bool(np, "renesas,no-ether-link");
2744 pdata->ether_link_active_low =
2745 of_property_read_bool(np, "renesas,ether-link-active-low");
2746
2747 return pdata;
2748}
2749
2750static const struct of_device_id sh_eth_match_table[] = {
2751 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2752 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2753 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2754 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2755 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2756 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2757 { }
2758};
2759MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2760#else
2761static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2762{
2763 return NULL;
2764}
2765#endif
2766
86a74ff2
NI		 2767static int sh_eth_drv_probe(struct platform_device *pdev)
2768{
9c38657c 2769 int ret, devno = 0;
86a74ff2
NI		 2770 struct resource *res;
2771 struct net_device *ndev = NULL;
ec0d7551 2772 struct sh_eth_private *mdp = NULL;
0b76b862 2773 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 2774 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 2775
2776 /* get base addr */
2777 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2778 if (unlikely(res == NULL)) {
2779 dev_err(&pdev->dev, "invalid resource\n");
f738a13d 2780 return -EINVAL;
86a74ff2
NI		 2781 }
2782
2783 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 2784 if (!ndev)
2785 return -ENOMEM;
86a74ff2 2786
b5893a08
BD		 2787 pm_runtime_enable(&pdev->dev);
2788 pm_runtime_get_sync(&pdev->dev);
2789
86a74ff2
NI		 2790 /* The sh Ether-specific entries in the device structure. */
2791 ndev->base_addr = res->start;
2792 devno = pdev->id;
2793 if (devno < 0)
2794 devno = 0;
2795
2796 ndev->dma = -1;
cc3c080d 2797 ret = platform_get_irq(pdev, 0);
2798 if (ret < 0) {
86a74ff2
NI		 2799 ret = -ENODEV;
2800 goto out_release;
2801 }
cc3c080d 2802 ndev->irq = ret;
86a74ff2
NI		 2803
2804 SET_NETDEV_DEV(ndev, &pdev->dev);
2805
86a74ff2 2806 mdp = netdev_priv(ndev);
525b8075
YS		 2807 mdp->num_tx_ring = TX_RING_SIZE;
2808 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 2809 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2810 if (IS_ERR(mdp->addr)) {
2811 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 2812 goto out_release;
2813 }
2814
86a74ff2 2815 spin_lock_init(&mdp->lock);
bcd5149d 2816 mdp->pdev = pdev;
86a74ff2 2817
b356e978
SS		 2818 if (pdev->dev.of_node)
2819 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 2820 if (!pd) {
2821 dev_err(&pdev->dev, "no platform data\n");
2822 ret = -EINVAL;
2823 goto out_release;
2824 }
2825
86a74ff2 2826 /* get PHY ID */
71557a37 2827 mdp->phy_id = pd->phy;
e47c9052 2828 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 2829 /* EDMAC endian */
2830 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 2831 mdp->no_ether_link = pd->no_ether_link;
2832 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 2833
380af9e3 2834 /* set cpu data */
b356e978
SS		 2835 if (id) {
2836 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2837 } else {
2838 const struct of_device_id *match;
2839
2840 match = of_match_device(of_match_ptr(sh_eth_match_table),
2841 &pdev->dev);
2842 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2843 }
a3153d8c 2844 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 2845 if (!mdp->reg_offset) {
2846 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2847 mdp->cd->register_type);
2848 ret = -EINVAL;
2849 goto out_release;
2850 }
380af9e3
YS		 2851 sh_eth_set_default_cpu_data(mdp->cd);
2852
86a74ff2 2853 /* set function */
8f728d79
SS		 2854 if (mdp->cd->tsu)
2855 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2856 else
2857 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 2858 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 2859 ndev->watchdog_timeo = TX_TIMEOUT;
2860
dc19e4e5
NI		 2861 /* debug message level */
2862 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 2863
2864 /* read and set MAC address */
748031f9 2865 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 2866 if (!is_valid_ether_addr(ndev->dev_addr)) {
2867 dev_warn(&pdev->dev,
2868 "no valid MAC address supplied, using a random one.\n");
2869 eth_hw_addr_random(ndev);
2870 }
86a74ff2 2871
6ba88021
YS		 2872 /* ioremap the TSU registers */
2873 if (mdp->cd->tsu) {
2874 struct resource *rtsu;
2875 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 2876 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2877 if (IS_ERR(mdp->tsu_addr)) {
2878 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 2879 goto out_release;
2880 }
6743fe6d 2881 mdp->port = devno % 2;
f646968f 2882 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 2883 }
2884
150647fb
YS		 2885 /* initialize first or needed device */
2886 if (!devno || pd->needs_init) {
380af9e3
YS		 2887 if (mdp->cd->chip_reset)
2888 mdp->cd->chip_reset(ndev);
86a74ff2 2889
4986b996
YS		 2890 if (mdp->cd->tsu) {
2891 /* TSU init (Init only)*/
2892 sh_eth_tsu_init(mdp);
2893 }
86a74ff2
NI		 2894 }
2895
daacf03f
LP		 2896 /* MDIO bus init */
2897 ret = sh_mdio_init(mdp, pd);
2898 if (ret) {
2899 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2900 goto out_release;
2901 }
2902
3719109d
SS		 2903 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2904
86a74ff2
NI		 2905 /* network device register */
2906 ret = register_netdev(ndev);
2907 if (ret)
3719109d 2908 goto out_napi_del;
86a74ff2 2909
25985edc 2910 /* print device information */
f75f14ec
SS		 2911 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
2912 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 2913
b5893a08 2914 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 2915 platform_set_drvdata(pdev, ndev);
2916
2917 return ret;
2918
3719109d
SS		 2919out_napi_del:
2920 netif_napi_del(&mdp->napi);
daacf03f 2921 sh_mdio_release(mdp);
3719109d 2922
86a74ff2
NI		 2923out_release:
2924 /* net_dev free */
2925 if (ndev)
2926 free_netdev(ndev);
2927
b5893a08
BD		 2928 pm_runtime_put(&pdev->dev);
2929 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 2930 return ret;
2931}
2932
2933static int sh_eth_drv_remove(struct platform_device *pdev)
2934{
2935 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 2936 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 2937
86a74ff2 2938 unregister_netdev(ndev);
3719109d 2939 netif_napi_del(&mdp->napi);
daacf03f 2940 sh_mdio_release(mdp);
bcd5149d 2941 pm_runtime_disable(&pdev->dev);
86a74ff2 2942 free_netdev(ndev);
86a74ff2
NI		 2943
2944 return 0;
2945}
2946
540ad1b8 2947#ifdef CONFIG_PM
bcd5149d
MD		 2948static int sh_eth_runtime_nop(struct device *dev)
2949{
128296fc 2950 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 2951 * and ->runtime_resume(). Simply returns success.
2952 *
2953 * This driver re-initializes all registers after
2954 * pm_runtime_get_sync() anyway so there is no need
2955 * to save and restore registers here.
2956 */
2957 return 0;
2958}
2959
540ad1b8 2960static const struct dev_pm_ops sh_eth_dev_pm_ops = {
bcd5149d
MD		 2961 .runtime_suspend = sh_eth_runtime_nop,
2962 .runtime_resume = sh_eth_runtime_nop,
2963};
540ad1b8
NI		 2964#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2965#else
2966#define SH_ETH_PM_OPS NULL
2967#endif
bcd5149d 2968
afe391ad 2969static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 2970 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 2971 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 2972 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 2973 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 2974 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2975 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 2976 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
db893473 2977 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
e5c9b4cd 2978 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
589ebdef 2979 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
94a12b15
SS		 2980 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
2981 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
afe391ad
SS		 2982 { }
2983};
2984MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2985
86a74ff2
NI		 2986static struct platform_driver sh_eth_driver = {
2987 .probe = sh_eth_drv_probe,
2988 .remove = sh_eth_drv_remove,
afe391ad 2989 .id_table = sh_eth_id_table,
86a74ff2
NI		 2990 .driver = {
2991 .name = CARDNAME,
540ad1b8 2992 .pm = SH_ETH_PM_OPS,
b356e978 2993 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 2994 },
2995};
2996
db62f684 2997module_platform_driver(sh_eth_driver);
86a74ff2
NI		 2998
2999MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3000MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3001MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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