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sh_eth: Remove obsolete r8a779x-ether platform_device_id entries
[deliverable/linux.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
966d6dbb 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978
SS		 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
3365711d
BH		 55#define SH_ETH_OFFSET_DEFAULTS \
56 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
57
c0013f6f 58static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 59 SH_ETH_OFFSET_DEFAULTS,
60
c0013f6f
SS		 61 [EDSR] = 0x0000,
62 [EDMR] = 0x0400,
63 [EDTRR] = 0x0408,
64 [EDRRR] = 0x0410,
65 [EESR] = 0x0428,
66 [EESIPR] = 0x0430,
67 [TDLAR] = 0x0010,
68 [TDFAR] = 0x0014,
69 [TDFXR] = 0x0018,
70 [TDFFR] = 0x001c,
71 [RDLAR] = 0x0030,
72 [RDFAR] = 0x0034,
73 [RDFXR] = 0x0038,
74 [RDFFR] = 0x003c,
75 [TRSCER] = 0x0438,
76 [RMFCR] = 0x0440,
77 [TFTR] = 0x0448,
78 [FDR] = 0x0450,
79 [RMCR] = 0x0458,
80 [RPADIR] = 0x0460,
81 [FCFTR] = 0x0468,
82 [CSMR] = 0x04E4,
83
84 [ECMR] = 0x0500,
85 [ECSR] = 0x0510,
86 [ECSIPR] = 0x0518,
87 [PIR] = 0x0520,
88 [PSR] = 0x0528,
89 [PIPR] = 0x052c,
90 [RFLR] = 0x0508,
91 [APR] = 0x0554,
92 [MPR] = 0x0558,
93 [PFTCR] = 0x055c,
94 [PFRCR] = 0x0560,
95 [TPAUSER] = 0x0564,
96 [GECMR] = 0x05b0,
97 [BCULR] = 0x05b4,
98 [MAHR] = 0x05c0,
99 [MALR] = 0x05c8,
100 [TROCR] = 0x0700,
101 [CDCR] = 0x0708,
102 [LCCR] = 0x0710,
103 [CEFCR] = 0x0740,
104 [FRECR] = 0x0748,
105 [TSFRCR] = 0x0750,
106 [TLFRCR] = 0x0758,
107 [RFCR] = 0x0760,
108 [CERCR] = 0x0768,
109 [CEECR] = 0x0770,
110 [MAFCR] = 0x0778,
111 [RMII_MII] = 0x0790,
112
113 [ARSTR] = 0x0000,
114 [TSU_CTRST] = 0x0004,
115 [TSU_FWEN0] = 0x0010,
116 [TSU_FWEN1] = 0x0014,
117 [TSU_FCM] = 0x0018,
118 [TSU_BSYSL0] = 0x0020,
119 [TSU_BSYSL1] = 0x0024,
120 [TSU_PRISL0] = 0x0028,
121 [TSU_PRISL1] = 0x002c,
122 [TSU_FWSL0] = 0x0030,
123 [TSU_FWSL1] = 0x0034,
124 [TSU_FWSLC] = 0x0038,
125 [TSU_QTAG0] = 0x0040,
126 [TSU_QTAG1] = 0x0044,
127 [TSU_FWSR] = 0x0050,
128 [TSU_FWINMK] = 0x0054,
129 [TSU_ADQT0] = 0x0048,
130 [TSU_ADQT1] = 0x004c,
131 [TSU_VTAG0] = 0x0058,
132 [TSU_VTAG1] = 0x005c,
133 [TSU_ADSBSY] = 0x0060,
134 [TSU_TEN] = 0x0064,
135 [TSU_POST1] = 0x0070,
136 [TSU_POST2] = 0x0074,
137 [TSU_POST3] = 0x0078,
138 [TSU_POST4] = 0x007c,
139 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 140
141 [TXNLCR0] = 0x0080,
142 [TXALCR0] = 0x0084,
143 [RXNLCR0] = 0x0088,
144 [RXALCR0] = 0x008c,
145 [FWNLCR0] = 0x0090,
146 [FWALCR0] = 0x0094,
147 [TXNLCR1] = 0x00a0,
148 [TXALCR1] = 0x00a0,
149 [RXNLCR1] = 0x00a8,
150 [RXALCR1] = 0x00ac,
151 [FWNLCR1] = 0x00b0,
152 [FWALCR1] = 0x00b4,
153};
154
db893473 155static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 156 SH_ETH_OFFSET_DEFAULTS,
157
db893473
SH		 158 [EDSR] = 0x0000,
159 [EDMR] = 0x0400,
160 [EDTRR] = 0x0408,
161 [EDRRR] = 0x0410,
162 [EESR] = 0x0428,
163 [EESIPR] = 0x0430,
164 [TDLAR] = 0x0010,
165 [TDFAR] = 0x0014,
166 [TDFXR] = 0x0018,
167 [TDFFR] = 0x001c,
168 [RDLAR] = 0x0030,
169 [RDFAR] = 0x0034,
170 [RDFXR] = 0x0038,
171 [RDFFR] = 0x003c,
172 [TRSCER] = 0x0438,
173 [RMFCR] = 0x0440,
174 [TFTR] = 0x0448,
175 [FDR] = 0x0450,
176 [RMCR] = 0x0458,
177 [RPADIR] = 0x0460,
178 [FCFTR] = 0x0468,
179 [CSMR] = 0x04E4,
180
181 [ECMR] = 0x0500,
182 [RFLR] = 0x0508,
183 [ECSR] = 0x0510,
184 [ECSIPR] = 0x0518,
185 [PIR] = 0x0520,
186 [APR] = 0x0554,
187 [MPR] = 0x0558,
188 [PFTCR] = 0x055c,
189 [PFRCR] = 0x0560,
190 [TPAUSER] = 0x0564,
191 [MAHR] = 0x05c0,
192 [MALR] = 0x05c8,
193 [CEFCR] = 0x0740,
194 [FRECR] = 0x0748,
195 [TSFRCR] = 0x0750,
196 [TLFRCR] = 0x0758,
197 [RFCR] = 0x0760,
198 [MAFCR] = 0x0778,
199
200 [ARSTR] = 0x0000,
201 [TSU_CTRST] = 0x0004,
202 [TSU_VTAG0] = 0x0058,
203 [TSU_ADSBSY] = 0x0060,
204 [TSU_TEN] = 0x0064,
205 [TSU_ADRH0] = 0x0100,
db893473
SH		 206
207 [TXNLCR0] = 0x0080,
208 [TXALCR0] = 0x0084,
209 [RXNLCR0] = 0x0088,
210 [RXALCR0] = 0x008C,
211};
212
a3f109bd 213static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 214 SH_ETH_OFFSET_DEFAULTS,
215
a3f109bd
SS		 216 [ECMR] = 0x0300,
217 [RFLR] = 0x0308,
218 [ECSR] = 0x0310,
219 [ECSIPR] = 0x0318,
220 [PIR] = 0x0320,
221 [PSR] = 0x0328,
222 [RDMLR] = 0x0340,
223 [IPGR] = 0x0350,
224 [APR] = 0x0354,
225 [MPR] = 0x0358,
226 [RFCF] = 0x0360,
227 [TPAUSER] = 0x0364,
228 [TPAUSECR] = 0x0368,
229 [MAHR] = 0x03c0,
230 [MALR] = 0x03c8,
231 [TROCR] = 0x03d0,
232 [CDCR] = 0x03d4,
233 [LCCR] = 0x03d8,
234 [CNDCR] = 0x03dc,
235 [CEFCR] = 0x03e4,
236 [FRECR] = 0x03e8,
237 [TSFRCR] = 0x03ec,
238 [TLFRCR] = 0x03f0,
239 [RFCR] = 0x03f4,
240 [MAFCR] = 0x03f8,
241
242 [EDMR] = 0x0200,
243 [EDTRR] = 0x0208,
244 [EDRRR] = 0x0210,
245 [TDLAR] = 0x0218,
246 [RDLAR] = 0x0220,
247 [EESR] = 0x0228,
248 [EESIPR] = 0x0230,
249 [TRSCER] = 0x0238,
250 [RMFCR] = 0x0240,
251 [TFTR] = 0x0248,
252 [FDR] = 0x0250,
253 [RMCR] = 0x0258,
254 [TFUCR] = 0x0264,
255 [RFOCR] = 0x0268,
55754f19 256 [RMIIMODE] = 0x026c,
a3f109bd
SS		 257 [FCFTR] = 0x0270,
258 [TRIMD] = 0x027c,
259};
260
c0013f6f 261static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 262 SH_ETH_OFFSET_DEFAULTS,
263
c0013f6f
SS		 264 [ECMR] = 0x0100,
265 [RFLR] = 0x0108,
266 [ECSR] = 0x0110,
267 [ECSIPR] = 0x0118,
268 [PIR] = 0x0120,
269 [PSR] = 0x0128,
270 [RDMLR] = 0x0140,
271 [IPGR] = 0x0150,
272 [APR] = 0x0154,
273 [MPR] = 0x0158,
274 [TPAUSER] = 0x0164,
275 [RFCF] = 0x0160,
276 [TPAUSECR] = 0x0168,
277 [BCFRR] = 0x016c,
278 [MAHR] = 0x01c0,
279 [MALR] = 0x01c8,
280 [TROCR] = 0x01d0,
281 [CDCR] = 0x01d4,
282 [LCCR] = 0x01d8,
283 [CNDCR] = 0x01dc,
284 [CEFCR] = 0x01e4,
285 [FRECR] = 0x01e8,
286 [TSFRCR] = 0x01ec,
287 [TLFRCR] = 0x01f0,
288 [RFCR] = 0x01f4,
289 [MAFCR] = 0x01f8,
290 [RTRATE] = 0x01fc,
291
292 [EDMR] = 0x0000,
293 [EDTRR] = 0x0008,
294 [EDRRR] = 0x0010,
295 [TDLAR] = 0x0018,
296 [RDLAR] = 0x0020,
297 [EESR] = 0x0028,
298 [EESIPR] = 0x0030,
299 [TRSCER] = 0x0038,
300 [RMFCR] = 0x0040,
301 [TFTR] = 0x0048,
302 [FDR] = 0x0050,
303 [RMCR] = 0x0058,
304 [TFUCR] = 0x0064,
305 [RFOCR] = 0x0068,
306 [FCFTR] = 0x0070,
307 [RPADIR] = 0x0078,
308 [TRIMD] = 0x007c,
309 [RBWAR] = 0x00c8,
310 [RDFAR] = 0x00cc,
311 [TBRAR] = 0x00d4,
312 [TDFAR] = 0x00d8,
313};
314
315static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 316 SH_ETH_OFFSET_DEFAULTS,
317
d8b0426a
SS		 318 [EDMR] = 0x0000,
319 [EDTRR] = 0x0004,
320 [EDRRR] = 0x0008,
321 [TDLAR] = 0x000c,
322 [RDLAR] = 0x0010,
323 [EESR] = 0x0014,
324 [EESIPR] = 0x0018,
325 [TRSCER] = 0x001c,
326 [RMFCR] = 0x0020,
327 [TFTR] = 0x0024,
328 [FDR] = 0x0028,
329 [RMCR] = 0x002c,
330 [EDOCR] = 0x0030,
331 [FCFTR] = 0x0034,
332 [RPADIR] = 0x0038,
333 [TRIMD] = 0x003c,
334 [RBWAR] = 0x0040,
335 [RDFAR] = 0x0044,
336 [TBRAR] = 0x004c,
337 [TDFAR] = 0x0050,
338
c0013f6f
SS		 339 [ECMR] = 0x0160,
340 [ECSR] = 0x0164,
341 [ECSIPR] = 0x0168,
342 [PIR] = 0x016c,
343 [MAHR] = 0x0170,
344 [MALR] = 0x0174,
345 [RFLR] = 0x0178,
346 [PSR] = 0x017c,
347 [TROCR] = 0x0180,
348 [CDCR] = 0x0184,
349 [LCCR] = 0x0188,
350 [CNDCR] = 0x018c,
351 [CEFCR] = 0x0194,
352 [FRECR] = 0x0198,
353 [TSFRCR] = 0x019c,
354 [TLFRCR] = 0x01a0,
355 [RFCR] = 0x01a4,
356 [MAFCR] = 0x01a8,
357 [IPGR] = 0x01b4,
358 [APR] = 0x01b8,
359 [MPR] = 0x01bc,
360 [TPAUSER] = 0x01c4,
361 [BCFR] = 0x01cc,
362
363 [ARSTR] = 0x0000,
364 [TSU_CTRST] = 0x0004,
365 [TSU_FWEN0] = 0x0010,
366 [TSU_FWEN1] = 0x0014,
367 [TSU_FCM] = 0x0018,
368 [TSU_BSYSL0] = 0x0020,
369 [TSU_BSYSL1] = 0x0024,
370 [TSU_PRISL0] = 0x0028,
371 [TSU_PRISL1] = 0x002c,
372 [TSU_FWSL0] = 0x0030,
373 [TSU_FWSL1] = 0x0034,
374 [TSU_FWSLC] = 0x0038,
375 [TSU_QTAGM0] = 0x0040,
376 [TSU_QTAGM1] = 0x0044,
377 [TSU_ADQT0] = 0x0048,
378 [TSU_ADQT1] = 0x004c,
379 [TSU_FWSR] = 0x0050,
380 [TSU_FWINMK] = 0x0054,
381 [TSU_ADSBSY] = 0x0060,
382 [TSU_TEN] = 0x0064,
383 [TSU_POST1] = 0x0070,
384 [TSU_POST2] = 0x0074,
385 [TSU_POST3] = 0x0078,
386 [TSU_POST4] = 0x007c,
387
388 [TXNLCR0] = 0x0080,
389 [TXALCR0] = 0x0084,
390 [RXNLCR0] = 0x0088,
391 [RXALCR0] = 0x008c,
392 [FWNLCR0] = 0x0090,
393 [FWALCR0] = 0x0094,
394 [TXNLCR1] = 0x00a0,
395 [TXALCR1] = 0x00a0,
396 [RXNLCR1] = 0x00a8,
397 [RXALCR1] = 0x00ac,
398 [FWNLCR1] = 0x00b0,
399 [FWALCR1] = 0x00b4,
400
401 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 402};
403
740c7f31
BH		 404static void sh_eth_rcv_snd_disable(struct net_device *ndev);
405static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
406
504c8ca5 407static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 408{
504c8ca5 409 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 410}
411
db893473
SH		 412static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
413{
414 return mdp->reg_offset == sh_eth_offset_fast_rz;
415}
416
8e994402 417static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 418{
419 u32 value = 0x0;
420 struct sh_eth_private *mdp = netdev_priv(ndev);
421
422 switch (mdp->phy_interface) {
423 case PHY_INTERFACE_MODE_GMII:
424 value = 0x2;
425 break;
426 case PHY_INTERFACE_MODE_MII:
427 value = 0x1;
428 break;
429 case PHY_INTERFACE_MODE_RMII:
430 value = 0x0;
431 break;
432 default:
f75f14ec
SS		 433 netdev_warn(ndev,
434 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 435 value = 0x1;
436 break;
437 }
438
439 sh_eth_write(ndev, value, RMII_MII);
440}
5e7a76be 441
8e994402 442static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 443{
444 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 445
446 if (mdp->duplex) /* Full */
4a55530f 447 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 448 else /* Half */
4a55530f 449 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 450}
451
99f84be6
GU		 452static void sh_eth_chip_reset(struct net_device *ndev)
453{
454 struct sh_eth_private *mdp = netdev_priv(ndev);
455
456 /* reset device */
457 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
458 mdelay(1);
459}
460
461#ifdef CONFIG_OF
462/* R7S72100 */
463static struct sh_eth_cpu_data r7s72100_data = {
464 .chip_reset = sh_eth_chip_reset,
465 .set_duplex = sh_eth_set_duplex,
466
467 .register_type = SH_ETH_REG_FAST_RZ,
468
469 .ecsr_value = ECSR_ICD,
470 .ecsipr_value = ECSIPR_ICDIP,
471 .eesipr_value = 0xff7f009f,
472
473 .tx_check = EESR_TC1 | EESR_FTC,
474 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
475 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
476 EESR_TDE | EESR_ECI,
477 .fdr_value = 0x0000070f,
478
479 .no_psr = 1,
480 .apr = 1,
481 .mpr = 1,
482 .tpauser = 1,
483 .hw_swap = 1,
484 .rpadir = 1,
485 .rpadir_value = 2 << 16,
486 .no_trimd = 1,
487 .no_ade = 1,
488 .hw_crc = 1,
489 .tsu = 1,
490 .shift_rd0 = 1,
491};
492#endif /* CONFIG_OF */
493
04b0ed2a 494/* There is CPU dependent code */
589ebdef 495static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 496{
497 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 498
a3f109bd
SS		 499 switch (mdp->speed) {
500 case 10: /* 10BASE */
501 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
502 break;
503 case 100:/* 100BASE */
504 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
505 break;
506 default:
507 break;
508 }
509}
510
674853b2 511/* R8A7778/9 */
589ebdef 512static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 513 .set_duplex = sh_eth_set_duplex,
589ebdef 514 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 515
a3153d8c
SS		 516 .register_type = SH_ETH_REG_FAST_RCAR,
517
a3f109bd
SS		 518 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
519 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
520 .eesipr_value = 0x01ff009f,
521
522 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 523 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
524 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
525 EESR_ECI,
d407bc02 526 .fdr_value = 0x00000f0f,
a3f109bd
SS		 527
528 .apr = 1,
529 .mpr = 1,
530 .tpauser = 1,
531 .hw_swap = 1,
532};
a3f109bd 533
c74a2248 534#ifdef CONFIG_OF
94a12b15
SS		 535/* R8A7790/1 */
536static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 537 .set_duplex = sh_eth_set_duplex,
538 .set_rate = sh_eth_set_rate_r8a777x,
539
a3153d8c
SS		 540 .register_type = SH_ETH_REG_FAST_RCAR,
541
e18dbf7e
SH		 542 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
543 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
544 .eesipr_value = 0x01ff009f,
545
546 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 547 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
548 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
549 EESR_ECI,
d407bc02 550 .fdr_value = 0x00000f0f,
e18dbf7e 551
01fbd3f5
GU		 552 .trscer_err_mask = DESC_I_RINT8,
553
e18dbf7e
SH		 554 .apr = 1,
555 .mpr = 1,
556 .tpauser = 1,
557 .hw_swap = 1,
558 .rmiimode = 1,
559};
c74a2248 560#endif /* CONFIG_OF */
e18dbf7e 561
9c3beaab 562static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 563{
564 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 565
566 switch (mdp->speed) {
567 case 10: /* 10BASE */
a3f109bd 568 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 569 break;
570 case 100:/* 100BASE */
a3f109bd 571 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 572 break;
573 default:
574 break;
575 }
576}
577
578/* SH7724 */
9c3beaab 579static struct sh_eth_cpu_data sh7724_data = {
65ac8851 580 .set_duplex = sh_eth_set_duplex,
9c3beaab 581 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 582
a3153d8c
SS		 583 .register_type = SH_ETH_REG_FAST_SH4,
584
65ac8851
YS		 585 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
586 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 587 .eesipr_value = 0x01ff009f,
65ac8851
YS		 588
589 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 590 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
591 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
592 EESR_ECI,
65ac8851
YS		 593
594 .apr = 1,
595 .mpr = 1,
596 .tpauser = 1,
597 .hw_swap = 1,
503914cf
MD		 598 .rpadir = 1,
599 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 600};
5cee1d37 601
24549e2a 602static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 603{
604 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 605
606 switch (mdp->speed) {
607 case 10: /* 10BASE */
4a55530f 608 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 609 break;
610 case 100:/* 100BASE */
4a55530f 611 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 612 break;
613 default:
614 break;
615 }
616}
617
618/* SH7757 */
24549e2a
SS		 619static struct sh_eth_cpu_data sh7757_data = {
620 .set_duplex = sh_eth_set_duplex,
621 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 622
a3153d8c
SS		 623 .register_type = SH_ETH_REG_FAST_SH4,
624
f29a3d04 625 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 626
627 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 628 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
629 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
630 EESR_ECI,
f29a3d04 631
5b3dfd13 632 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 633 .apr = 1,
634 .mpr = 1,
635 .tpauser = 1,
636 .hw_swap = 1,
637 .no_ade = 1,
2e98e797
YS		 638 .rpadir = 1,
639 .rpadir_value = 2 << 16,
6b4b4fea 640 .rtrate = 1,
f29a3d04 641};
65ac8851 642
e403d295 643#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 644#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
645#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
646static void sh_eth_chip_reset_giga(struct net_device *ndev)
647{
648 int i;
0799c2d6 649 u32 mahr[2], malr[2];
8fcd4961
YS		 650
651 /* save MAHR and MALR */
652 for (i = 0; i < 2; i++) {
ae70644d
YS		 653 malr[i] = ioread32((void *)GIGA_MALR(i));
654 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 655 }
656
657 /* reset device */
ae70644d 658 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 659 mdelay(1);
660
661 /* restore MAHR and MALR */
662 for (i = 0; i < 2; i++) {
ae70644d
YS		 663 iowrite32(malr[i], (void *)GIGA_MALR(i));
664 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 665 }
666}
667
8fcd4961
YS		 668static void sh_eth_set_rate_giga(struct net_device *ndev)
669{
670 struct sh_eth_private *mdp = netdev_priv(ndev);
671
672 switch (mdp->speed) {
673 case 10: /* 10BASE */
674 sh_eth_write(ndev, 0x00000000, GECMR);
675 break;
676 case 100:/* 100BASE */
677 sh_eth_write(ndev, 0x00000010, GECMR);
678 break;
679 case 1000: /* 1000BASE */
680 sh_eth_write(ndev, 0x00000020, GECMR);
681 break;
682 default:
683 break;
684 }
685}
686
687/* SH7757(GETHERC) */
24549e2a 688static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 689 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 690 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 691 .set_rate = sh_eth_set_rate_giga,
692
a3153d8c
SS		 693 .register_type = SH_ETH_REG_GIGABIT,
694
8fcd4961
YS		 695 .ecsr_value = ECSR_ICD | ECSR_MPD,
696 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
697 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
698
699 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 700 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
701 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
702 EESR_TDE | EESR_ECI,
8fcd4961 703 .fdr_value = 0x0000072f,
8fcd4961 704
5b3dfd13 705 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 706 .apr = 1,
707 .mpr = 1,
708 .tpauser = 1,
709 .bculr = 1,
710 .hw_swap = 1,
711 .rpadir = 1,
712 .rpadir_value = 2 << 16,
713 .no_trimd = 1,
714 .no_ade = 1,
3acbc971 715 .tsu = 1,
8fcd4961
YS		 716};
717
f5d12767 718static void sh_eth_set_rate_gether(struct net_device *ndev)
380af9e3
YS		 719{
720 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 721
722 switch (mdp->speed) {
723 case 10: /* 10BASE */
4a55530f 724 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 725 break;
726 case 100:/* 100BASE */
4a55530f 727 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 728 break;
729 case 1000: /* 1000BASE */
4a55530f 730 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 731 break;
732 default:
733 break;
734 }
735}
736
f5d12767
SS		 737/* SH7734 */
738static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 739 .chip_reset = sh_eth_chip_reset,
740 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 741 .set_rate = sh_eth_set_rate_gether,
742
a3153d8c
SS		 743 .register_type = SH_ETH_REG_GIGABIT,
744
f5d12767
SS		 745 .ecsr_value = ECSR_ICD | ECSR_MPD,
746 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
747 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
748
749 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 750 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
751 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
752 EESR_TDE | EESR_ECI,
f5d12767
SS		 753
754 .apr = 1,
755 .mpr = 1,
756 .tpauser = 1,
757 .bculr = 1,
758 .hw_swap = 1,
759 .no_trimd = 1,
760 .no_ade = 1,
761 .tsu = 1,
762 .hw_crc = 1,
763 .select_mii = 1,
764};
765
766/* SH7763 */
767static struct sh_eth_cpu_data sh7763_data = {
768 .chip_reset = sh_eth_chip_reset,
769 .set_duplex = sh_eth_set_duplex,
770 .set_rate = sh_eth_set_rate_gether,
380af9e3 771
a3153d8c
SS		 772 .register_type = SH_ETH_REG_GIGABIT,
773
380af9e3
YS		 774 .ecsr_value = ECSR_ICD | ECSR_MPD,
775 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
776 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
777
778 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 779 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
780 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 781 EESR_ECI,
380af9e3
YS		 782
783 .apr = 1,
784 .mpr = 1,
785 .tpauser = 1,
786 .bculr = 1,
787 .hw_swap = 1,
380af9e3
YS		 788 .no_trimd = 1,
789 .no_ade = 1,
4986b996 790 .tsu = 1,
5b3dfd13 791 .irq_flags = IRQF_SHARED,
380af9e3
YS		 792};
793
e5c9b4cd 794static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
73a0d907
YS		 795{
796 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 797
798 /* reset device */
799 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
800 mdelay(1);
801
5e7a76be 802 sh_eth_select_mii(ndev);
73a0d907
YS		 803}
804
73a0d907 805/* R8A7740 */
e5c9b4cd
SS		 806static struct sh_eth_cpu_data r8a7740_data = {
807 .chip_reset = sh_eth_chip_reset_r8a7740,
73a0d907 808 .set_duplex = sh_eth_set_duplex,
e5c9b4cd 809 .set_rate = sh_eth_set_rate_gether,
73a0d907 810
a3153d8c
SS		 811 .register_type = SH_ETH_REG_GIGABIT,
812
73a0d907
YS		 813 .ecsr_value = ECSR_ICD | ECSR_MPD,
814 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
815 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
816
817 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 818 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
819 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
820 EESR_TDE | EESR_ECI,
cc23528d 821 .fdr_value = 0x0000070f,
73a0d907
YS		 822
823 .apr = 1,
824 .mpr = 1,
825 .tpauser = 1,
826 .bculr = 1,
827 .hw_swap = 1,
cc23528d
SH		 828 .rpadir = 1,
829 .rpadir_value = 2 << 16,
73a0d907
YS		 830 .no_trimd = 1,
831 .no_ade = 1,
832 .tsu = 1,
5e7a76be 833 .select_mii = 1,
ac8025a6 834 .shift_rd0 = 1,
73a0d907
YS		 835};
836
c18a79ab 837static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 838 .register_type = SH_ETH_REG_FAST_SH3_SH2,
839
380af9e3
YS		 840 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
841
842 .apr = 1,
843 .mpr = 1,
844 .tpauser = 1,
845 .hw_swap = 1,
846};
7bbe150d
SS		 847
848static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 849 .register_type = SH_ETH_REG_FAST_SH3_SH2,
850
380af9e3 851 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 852 .tsu = 1,
380af9e3 853};
380af9e3
YS		 854
855static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
856{
857 if (!cd->ecsr_value)
858 cd->ecsr_value = DEFAULT_ECSR_INIT;
859
860 if (!cd->ecsipr_value)
861 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
862
863 if (!cd->fcftr_value)
128296fc 864 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 865 DEFAULT_FIFO_F_D_RFD;
866
867 if (!cd->fdr_value)
868 cd->fdr_value = DEFAULT_FDR_INIT;
869
380af9e3
YS		 870 if (!cd->tx_check)
871 cd->tx_check = DEFAULT_TX_CHECK;
872
873 if (!cd->eesr_err_check)
874 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 875
876 if (!cd->trscer_err_mask)
877 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 878}
879
5cee1d37
NI		 880static int sh_eth_check_reset(struct net_device *ndev)
881{
882 int ret = 0;
883 int cnt = 100;
884
885 while (cnt > 0) {
886 if (!(sh_eth_read(ndev, EDMR) & 0x3))
887 break;
888 mdelay(1);
889 cnt--;
890 }
9f8c4265 891 if (cnt <= 0) {
f75f14ec 892 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 893 ret = -ETIMEDOUT;
894 }
895 return ret;
380af9e3 896}
dabdde9e
NI		 897
898static int sh_eth_reset(struct net_device *ndev)
899{
900 struct sh_eth_private *mdp = netdev_priv(ndev);
901 int ret = 0;
902
db893473 903 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e
NI		 904 sh_eth_write(ndev, EDSR_ENALL, EDSR);
905 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
906 EDMR);
907
908 ret = sh_eth_check_reset(ndev);
909 if (ret)
f738a13d 910 return ret;
dabdde9e
NI		 911
912 /* Table Init */
913 sh_eth_write(ndev, 0x0, TDLAR);
914 sh_eth_write(ndev, 0x0, TDFAR);
915 sh_eth_write(ndev, 0x0, TDFXR);
916 sh_eth_write(ndev, 0x0, TDFFR);
917 sh_eth_write(ndev, 0x0, RDLAR);
918 sh_eth_write(ndev, 0x0, RDFAR);
919 sh_eth_write(ndev, 0x0, RDFXR);
920 sh_eth_write(ndev, 0x0, RDFFR);
921
922 /* Reset HW CRC register */
923 if (mdp->cd->hw_crc)
924 sh_eth_write(ndev, 0x0, CSMR);
925
926 /* Select MII mode */
927 if (mdp->cd->select_mii)
928 sh_eth_select_mii(ndev);
929 } else {
930 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
931 EDMR);
932 mdelay(3);
933 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
934 EDMR);
935 }
936
dabdde9e
NI		 937 return ret;
938}
380af9e3 939
380af9e3
YS		 940static void sh_eth_set_receive_align(struct sk_buff *skb)
941{
4d6a949c 942 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 943
380af9e3 944 if (reserve)
4d6a949c 945 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 946}
380af9e3
YS		 947
948
71557a37
YS		 949/* CPU <-> EDMAC endian convert */
950static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
951{
952 switch (mdp->edmac_endian) {
953 case EDMAC_LITTLE_ENDIAN:
954 return cpu_to_le32(x);
955 case EDMAC_BIG_ENDIAN:
956 return cpu_to_be32(x);
957 }
958 return x;
959}
960
961static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
962{
963 switch (mdp->edmac_endian) {
964 case EDMAC_LITTLE_ENDIAN:
965 return le32_to_cpu(x);
966 case EDMAC_BIG_ENDIAN:
967 return be32_to_cpu(x);
968 }
969 return x;
970}
971
128296fc 972/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 973static void update_mac_address(struct net_device *ndev)
974{
4a55530f 975 sh_eth_write(ndev,
128296fc
SS		 976 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
977 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 978 sh_eth_write(ndev,
128296fc 979 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 980}
981
128296fc 982/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 983 *
984 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
985 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
986 * When you want use this device, you must set MAC address in bootloader.
987 *
988 */
748031f9 989static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 990{
748031f9 991 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 992 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 993 } else {
4a55530f
YS		 994 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
995 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
996 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
997 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
998 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
999 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 1000 }
86a74ff2
NI		 1001}
1002
0799c2d6 1003static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 1004{
db893473 1005 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 1006 return EDTRR_TRNS_GETHER;
1007 else
1008 return EDTRR_TRNS_ETHER;
1009}
1010
86a74ff2 1011struct bb_info {
ae70644d 1012 void (*set_gate)(void *addr);
86a74ff2 1013 struct mdiobb_ctrl ctrl;
ae70644d 1014 void *addr;
86a74ff2
NI		 1015 u32 mmd_msk;/* MMD */
1016 u32 mdo_msk;
1017 u32 mdi_msk;
1018 u32 mdc_msk;
1019};
1020
1021/* PHY bit set */
ae70644d 1022static void bb_set(void *addr, u32 msk)
86a74ff2 1023{
ae70644d 1024 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 1025}
1026
1027/* PHY bit clear */
ae70644d 1028static void bb_clr(void *addr, u32 msk)
86a74ff2 1029{
ae70644d 1030 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 1031}
1032
1033/* PHY bit read */
ae70644d 1034static int bb_read(void *addr, u32 msk)
86a74ff2 1035{
ae70644d 1036 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 1037}
1038
1039/* Data I/O pin control */
1040static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1041{
1042 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1043
1044 if (bitbang->set_gate)
1045 bitbang->set_gate(bitbang->addr);
1046
86a74ff2
NI		 1047 if (bit)
1048 bb_set(bitbang->addr, bitbang->mmd_msk);
1049 else
1050 bb_clr(bitbang->addr, bitbang->mmd_msk);
1051}
1052
1053/* Set bit data*/
1054static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1055{
1056 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1057
b3017e6a
YS		 1058 if (bitbang->set_gate)
1059 bitbang->set_gate(bitbang->addr);
1060
86a74ff2
NI		 1061 if (bit)
1062 bb_set(bitbang->addr, bitbang->mdo_msk);
1063 else
1064 bb_clr(bitbang->addr, bitbang->mdo_msk);
1065}
1066
1067/* Get bit data*/
1068static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1069{
1070 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1071
1072 if (bitbang->set_gate)
1073 bitbang->set_gate(bitbang->addr);
1074
86a74ff2
NI		 1075 return bb_read(bitbang->addr, bitbang->mdi_msk);
1076}
1077
1078/* MDC pin control */
1079static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1080{
1081 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1082
b3017e6a
YS		 1083 if (bitbang->set_gate)
1084 bitbang->set_gate(bitbang->addr);
1085
86a74ff2
NI		 1086 if (bit)
1087 bb_set(bitbang->addr, bitbang->mdc_msk);
1088 else
1089 bb_clr(bitbang->addr, bitbang->mdc_msk);
1090}
1091
1092/* mdio bus control struct */
1093static struct mdiobb_ops bb_ops = {
1094 .owner = THIS_MODULE,
1095 .set_mdc = sh_mdc_ctrl,
1096 .set_mdio_dir = sh_mmd_ctrl,
1097 .set_mdio_data = sh_set_mdio,
1098 .get_mdio_data = sh_get_mdio,
1099};
1100
86a74ff2
NI		 1101/* free skb and descriptor buffer */
1102static void sh_eth_ring_free(struct net_device *ndev)
1103{
1104 struct sh_eth_private *mdp = netdev_priv(ndev);
8e03a5e7 1105 int ringsize, i;
86a74ff2
NI		 1106
1107 /* Free Rx skb ringbuffer */
1108 if (mdp->rx_skbuff) {
179d80af
SS		 1109 for (i = 0; i < mdp->num_rx_ring; i++)
1110 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1111 }
1112 kfree(mdp->rx_skbuff);
91c77550 1113 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1114
1115 /* Free Tx skb ringbuffer */
1116 if (mdp->tx_skbuff) {
179d80af
SS		 1117 for (i = 0; i < mdp->num_tx_ring; i++)
1118 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 1119 }
1120 kfree(mdp->tx_skbuff);
91c77550 1121 mdp->tx_skbuff = NULL;
8e03a5e7
SS		 1122
1123 if (mdp->rx_ring) {
1124 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1125 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1126 mdp->rx_desc_dma);
1127 mdp->rx_ring = NULL;
1128 }
1129
1130 if (mdp->tx_ring) {
1131 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1132 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1133 mdp->tx_desc_dma);
1134 mdp->tx_ring = NULL;
1135 }
86a74ff2
NI		 1136}
1137
1138/* format skb and descriptor buffer */
1139static void sh_eth_ring_format(struct net_device *ndev)
1140{
1141 struct sh_eth_private *mdp = netdev_priv(ndev);
1142 int i;
1143 struct sk_buff *skb;
1144 struct sh_eth_rxdesc *rxdesc = NULL;
1145 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1146 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1147 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1148 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1149 dma_addr_t dma_addr;
86a74ff2 1150
128296fc
SS		 1151 mdp->cur_rx = 0;
1152 mdp->cur_tx = 0;
1153 mdp->dirty_rx = 0;
1154 mdp->dirty_tx = 0;
86a74ff2
NI		 1155
1156 memset(mdp->rx_ring, 0, rx_ringsize);
1157
1158 /* build Rx ring buffer */
525b8075 1159 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1160 /* skb */
1161 mdp->rx_skbuff[i] = NULL;
4d6a949c 1162 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1163 if (skb == NULL)
1164 break;
380af9e3
YS		 1165 sh_eth_set_receive_align(skb);
1166
86a74ff2
NI		 1167 /* RX descriptor */
1168 rxdesc = &mdp->rx_ring[i];
ab857916
SS		 1169 /* The size of the buffer is a multiple of 32 bytes. */
1170 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
52b9fa36
BH		 1171 dma_addr = dma_map_single(&ndev->dev, skb->data,
1172 rxdesc->buffer_length,
1173 DMA_FROM_DEVICE);
1174 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1175 kfree_skb(skb);
1176 break;
1177 }
1178 mdp->rx_skbuff[i] = skb;
1179 rxdesc->addr = dma_addr;
71557a37 1180 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2 1181
b0ca2a21
NI		 1182 /* Rx descriptor address set */
1183 if (i == 0) {
4a55530f 1184 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1185 if (sh_eth_is_gether(mdp) ||
1186 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1187 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1188 }
86a74ff2
NI		 1189 }
1190
525b8075 1191 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1192
1193 /* Mark the last entry as wrapping the ring. */
c238041f 1194 rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
86a74ff2
NI		 1195
1196 memset(mdp->tx_ring, 0, tx_ringsize);
1197
1198 /* build Tx ring buffer */
525b8075 1199 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1200 mdp->tx_skbuff[i] = NULL;
1201 txdesc = &mdp->tx_ring[i];
71557a37 1202 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1203 txdesc->buffer_length = 0;
b0ca2a21 1204 if (i == 0) {
71557a37 1205 /* Tx descriptor address set */
4a55530f 1206 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1207 if (sh_eth_is_gether(mdp) ||
1208 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1209 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1210 }
86a74ff2
NI		 1211 }
1212
71557a37 1213 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1214}
1215
1216/* Get skb and descriptor buffer */
1217static int sh_eth_ring_init(struct net_device *ndev)
1218{
1219 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1220 int rx_ringsize, tx_ringsize;
86a74ff2 1221
128296fc 1222 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1223 * card needs room to do 8 byte alignment, +2 so we can reserve
1224 * the first 2 bytes, and +16 gets room for the status word from the
1225 * card.
1226 */
1227 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1228 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1229 if (mdp->cd->rpadir)
1230 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1231
1232 /* Allocate RX and TX skb rings */
2c94e856
SS		 1233 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1234 GFP_KERNEL);
91d80683
SS		 1235 if (!mdp->rx_skbuff)
1236 return -ENOMEM;
86a74ff2 1237
2c94e856
SS		 1238 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1239 GFP_KERNEL);
91d80683 1240 if (!mdp->tx_skbuff)
8e03a5e7 1241 goto ring_free;
86a74ff2
NI		 1242
1243 /* Allocate all Rx descriptors. */
525b8075 1244 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1245 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1246 GFP_KERNEL);
91d80683 1247 if (!mdp->rx_ring)
8e03a5e7 1248 goto ring_free;
86a74ff2
NI		 1249
1250 mdp->dirty_rx = 0;
1251
1252 /* Allocate all Tx descriptors. */
525b8075 1253 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1254 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1255 GFP_KERNEL);
91d80683 1256 if (!mdp->tx_ring)
8e03a5e7 1257 goto ring_free;
91d80683 1258 return 0;
86a74ff2 1259
8e03a5e7
SS		 1260ring_free:
1261 /* Free Rx and Tx skb ring buffer and DMA buffer */
86a74ff2
NI		 1262 sh_eth_ring_free(ndev);
1263
91d80683 1264 return -ENOMEM;
86a74ff2
NI		 1265}
1266
525b8075 1267static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1268{
1269 int ret = 0;
1270 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1271 u32 val;
1272
1273 /* Soft Reset */
5cee1d37
NI		 1274 ret = sh_eth_reset(ndev);
1275 if (ret)
f738a13d 1276 return ret;
86a74ff2 1277
55754f19
SH		 1278 if (mdp->cd->rmiimode)
1279 sh_eth_write(ndev, 0x1, RMIIMODE);
1280
b0ca2a21
NI		 1281 /* Descriptor format */
1282 sh_eth_ring_format(ndev);
380af9e3 1283 if (mdp->cd->rpadir)
4a55530f 1284 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1285
1286 /* all sh_eth int mask */
4a55530f 1287 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1288
10b9194f 1289#if defined(__LITTLE_ENDIAN)
380af9e3 1290 if (mdp->cd->hw_swap)
4a55530f 1291 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1292 else
b0ca2a21 1293#endif
4a55530f 1294 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1295
b0ca2a21 1296 /* FIFO size set */
4a55530f
YS		 1297 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1298 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1299
530aa2d0
BD		 1300 /* Frame recv control (enable multiple-packets per rx irq) */
1301 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1302
b284fbe3 1303 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1304
380af9e3 1305 if (mdp->cd->bculr)
4a55530f 1306 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1307
4a55530f 1308 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1309
380af9e3 1310 if (!mdp->cd->no_trimd)
4a55530f 1311 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1312
b0ca2a21 1313 /* Recv frame limit set register */
fdb37a7f
YS		 1314 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1315 RFLR);
86a74ff2 1316
4a55530f 1317 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
283e38db
BH		 1318 if (start) {
1319 mdp->irq_enabled = true;
525b8075 1320 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
283e38db 1321 }
86a74ff2
NI		 1322
1323 /* PAUSE Prohibition */
4a55530f 1324 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1325 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1326
4a55530f 1327 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1328
380af9e3
YS		 1329 if (mdp->cd->set_rate)
1330 mdp->cd->set_rate(ndev);
1331
b0ca2a21 1332 /* E-MAC Status Register clear */
4a55530f 1333 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1334
1335 /* E-MAC Interrupt Enable register */
525b8075
YS		 1336 if (start)
1337 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1338
1339 /* Set MAC address */
1340 update_mac_address(ndev);
1341
1342 /* mask reset */
380af9e3 1343 if (mdp->cd->apr)
4a55530f 1344 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1345 if (mdp->cd->mpr)
4a55530f 1346 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1347 if (mdp->cd->tpauser)
4a55530f 1348 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1349
525b8075
YS		 1350 if (start) {
1351 /* Setting the Rx mode will start the Rx process. */
1352 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1353
525b8075
YS		 1354 netif_start_queue(ndev);
1355 }
86a74ff2
NI		 1356
1357 return ret;
1358}
1359
740c7f31
BH		 1360static void sh_eth_dev_exit(struct net_device *ndev)
1361{
1362 struct sh_eth_private *mdp = netdev_priv(ndev);
1363 int i;
1364
1365 /* Deactivate all TX descriptors, so DMA should stop at next
1366 * packet boundary if it's currently running
1367 */
1368 for (i = 0; i < mdp->num_tx_ring; i++)
1369 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1370
1371 /* Disable TX FIFO egress to MAC */
1372 sh_eth_rcv_snd_disable(ndev);
1373
1374 /* Stop RX DMA at next packet boundary */
1375 sh_eth_write(ndev, 0, EDRRR);
1376
1377 /* Aside from TX DMA, we can't tell when the hardware is
1378 * really stopped, so we need to reset to make sure.
1379 * Before doing that, wait for long enough to *probably*
1380 * finish transmitting the last packet and poll stats.
1381 */
1382 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1383 sh_eth_get_stats(ndev);
1384 sh_eth_reset(ndev);
a14c7d15
GU		 1385
1386 /* Set MAC address again */
1387 update_mac_address(ndev);
740c7f31
BH		 1388}
1389
86a74ff2
NI		 1390/* free Tx skb function */
1391static int sh_eth_txfree(struct net_device *ndev)
1392{
1393 struct sh_eth_private *mdp = netdev_priv(ndev);
1394 struct sh_eth_txdesc *txdesc;
128296fc 1395 int free_num = 0;
86a74ff2
NI		 1396 int entry = 0;
1397
1398 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1399 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1400 txdesc = &mdp->tx_ring[entry];
71557a37 1401 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2 1402 break;
7d7355f5 1403 /* TACT bit must be checked before all the following reads */
f32bfb9a 1404 dma_rmb();
e5fd13f4
BH		 1405 netif_info(mdp, tx_done, ndev,
1406 "tx entry %d status 0x%08x\n",
1407 entry, edmac_to_cpu(mdp, txdesc->status));
86a74ff2
NI		 1408 /* Free the original skb. */
1409 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1410 dma_unmap_single(&ndev->dev, txdesc->addr,
1411 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1412 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1413 mdp->tx_skbuff[entry] = NULL;
128296fc 1414 free_num++;
86a74ff2 1415 }
71557a37 1416 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1417 if (entry >= mdp->num_tx_ring - 1)
71557a37 1418 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1419
bb7d92e3
ED		 1420 ndev->stats.tx_packets++;
1421 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2 1422 }
128296fc 1423 return free_num;
86a74ff2
NI		 1424}
1425
1426/* Packet receive function */
3719109d 1427static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1428{
1429 struct sh_eth_private *mdp = netdev_priv(ndev);
1430 struct sh_eth_rxdesc *rxdesc;
1431
525b8075
YS		 1432 int entry = mdp->cur_rx % mdp->num_rx_ring;
1433 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1434 int limit;
86a74ff2
NI		 1435 struct sk_buff *skb;
1436 u16 pkt_len = 0;
380af9e3 1437 u32 desc_status;
cb368595 1438 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1439 dma_addr_t dma_addr;
86a74ff2 1440
319cd520
MK		 1441 boguscnt = min(boguscnt, *quota);
1442 limit = boguscnt;
86a74ff2 1443 rxdesc = &mdp->rx_ring[entry];
71557a37 1444 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
7d7355f5 1445 /* RACT bit must be checked before all the following reads */
f32bfb9a 1446 dma_rmb();
71557a37 1447 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1448 pkt_len = rxdesc->frame_length;
1449
1450 if (--boguscnt < 0)
1451 break;
1452
e5fd13f4
BH		 1453 netif_info(mdp, rx_status, ndev,
1454 "rx entry %d status 0x%08x len %d\n",
1455 entry, desc_status, pkt_len);
1456
86a74ff2 1457 if (!(desc_status & RDFEND))
bb7d92e3 1458 ndev->stats.rx_length_errors++;
86a74ff2 1459
128296fc 1460 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1461 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1462 * bit 0. However, in case of the R8A7740 and R7S72100
1463 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1464 * driver needs right shifting by 16.
dd019897 1465 */
ac8025a6
SS		 1466 if (mdp->cd->shift_rd0)
1467 desc_status >>= 16;
dd019897 1468
86a74ff2
NI		 1469 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1470 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1471 ndev->stats.rx_errors++;
86a74ff2 1472 if (desc_status & RD_RFS1)
bb7d92e3 1473 ndev->stats.rx_crc_errors++;
86a74ff2 1474 if (desc_status & RD_RFS2)
bb7d92e3 1475 ndev->stats.rx_frame_errors++;
86a74ff2 1476 if (desc_status & RD_RFS3)
bb7d92e3 1477 ndev->stats.rx_length_errors++;
86a74ff2 1478 if (desc_status & RD_RFS4)
bb7d92e3 1479 ndev->stats.rx_length_errors++;
86a74ff2 1480 if (desc_status & RD_RFS6)
bb7d92e3 1481 ndev->stats.rx_missed_errors++;
86a74ff2 1482 if (desc_status & RD_RFS10)
bb7d92e3 1483 ndev->stats.rx_over_errors++;
86a74ff2 1484 } else {
380af9e3
YS		 1485 if (!mdp->cd->hw_swap)
1486 sh_eth_soft_swap(
1487 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1488 pkt_len + 2);
86a74ff2
NI		 1489 skb = mdp->rx_skbuff[entry];
1490 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1491 if (mdp->cd->rpadir)
1492 skb_reserve(skb, NET_IP_ALIGN);
52b9fa36 1493 dma_unmap_single(&ndev->dev, rxdesc->addr,
ab857916 1494 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1495 DMA_FROM_DEVICE);
86a74ff2
NI		 1496 skb_put(skb, pkt_len);
1497 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1498 netif_receive_skb(skb);
bb7d92e3
ED		 1499 ndev->stats.rx_packets++;
1500 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1501 if (desc_status & RD_RFS8)
1502 ndev->stats.multicast++;
86a74ff2 1503 }
525b8075 1504 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1505 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1506 }
1507
1508 /* Refill the Rx ring buffers. */
1509 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1510 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1511 rxdesc = &mdp->rx_ring[entry];
ab857916
SS		 1512 /* The size of the buffer is 32 byte boundary. */
1513 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
b0ca2a21 1514
86a74ff2 1515 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1516 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1517 if (skb == NULL)
1518 break; /* Better luck next round. */
380af9e3 1519 sh_eth_set_receive_align(skb);
52b9fa36
BH		 1520 dma_addr = dma_map_single(&ndev->dev, skb->data,
1521 rxdesc->buffer_length,
1522 DMA_FROM_DEVICE);
1523 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1524 kfree_skb(skb);
1525 break;
1526 }
1527 mdp->rx_skbuff[entry] = skb;
380af9e3 1528
bc8acf2c 1529 skb_checksum_none_assert(skb);
52b9fa36 1530 rxdesc->addr = dma_addr;
86a74ff2 1531 }
f32bfb9a 1532 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1533 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1534 rxdesc->status |=
c238041f 1535 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
86a74ff2
NI		 1536 else
1537 rxdesc->status |=
71557a37 1538 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1539 }
1540
1541 /* Restart Rx engine if stopped. */
1542 /* If we don't need to check status, don't. -KDU */
79fba9f5 1543 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1544 /* fix the values for the next receiving if RDE is set */
3365711d
BH		 1545 if (intr_status & EESR_RDE &&
1546 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
128296fc
SS		 1547 u32 count = (sh_eth_read(ndev, RDFAR) -
1548 sh_eth_read(ndev, RDLAR)) >> 4;
1549
1550 mdp->cur_rx = count;
1551 mdp->dirty_rx = count;
1552 }
4a55530f 1553 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1554 }
86a74ff2 1555
319cd520
MK		 1556 *quota -= limit - boguscnt - 1;
1557
4f809cea 1558 return *quota <= 0;
86a74ff2
NI		 1559}
1560
4a55530f 1561static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1562{
1563 /* disable tx and rx */
4a55530f
YS		 1564 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1565 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1566}
1567
4a55530f 1568static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1569{
1570 /* enable tx and rx */
4a55530f
YS		 1571 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1572 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1573}
1574
86a74ff2 1575/* error control function */
0799c2d6 1576static void sh_eth_error(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1577{
1578 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1579 u32 felic_stat;
380af9e3
YS		 1580 u32 link_stat;
1581 u32 mask;
86a74ff2
NI		 1582
1583 if (intr_status & EESR_ECI) {
4a55530f
YS		 1584 felic_stat = sh_eth_read(ndev, ECSR);
1585 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1586 if (felic_stat & ECSR_ICD)
bb7d92e3 1587 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1588 if (felic_stat & ECSR_LCHNG) {
1589 /* Link Changed */
4923576b 1590 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1591 goto ignore_link;
380af9e3 1592 } else {
4a55530f 1593 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1594 if (mdp->ether_link_active_low)
1595 link_stat = ~link_stat;
380af9e3 1596 }
128296fc 1597 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1598 sh_eth_rcv_snd_disable(ndev);
128296fc 1599 } else {
86a74ff2 1600 /* Link Up */
4a55530f 1601 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
128296fc
SS		 1602 ~DMAC_M_ECI, EESIPR);
1603 /* clear int */
4a55530f 1604 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
128296fc 1605 ECSR);
4a55530f 1606 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
128296fc 1607 DMAC_M_ECI, EESIPR);
86a74ff2 1608 /* enable tx and rx */
4a55530f 1609 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1610 }
1611 }
1612 }
1613
1e1b812b 1614ignore_link:
86a74ff2 1615 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1616 /* Unused write back interrupt */
1617 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1618 ndev->stats.tx_aborted_errors++;
8d5009f6 1619 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1620 }
86a74ff2
NI		 1621 }
1622
1623 if (intr_status & EESR_RABT) {
1624 /* Receive Abort int */
1625 if (intr_status & EESR_RFRMER) {
1626 /* Receive Frame Overflow int */
bb7d92e3 1627 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1628 }
1629 }
380af9e3 1630
dc19e4e5
NI		 1631 if (intr_status & EESR_TDE) {
1632 /* Transmit Descriptor Empty int */
bb7d92e3 1633 ndev->stats.tx_fifo_errors++;
8d5009f6 1634 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1635 }
1636
1637 if (intr_status & EESR_TFE) {
1638 /* FIFO under flow */
bb7d92e3 1639 ndev->stats.tx_fifo_errors++;
8d5009f6 1640 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1641 }
1642
1643 if (intr_status & EESR_RDE) {
1644 /* Receive Descriptor Empty int */
bb7d92e3 1645 ndev->stats.rx_over_errors++;
86a74ff2 1646 }
dc19e4e5 1647
86a74ff2
NI		 1648 if (intr_status & EESR_RFE) {
1649 /* Receive FIFO Overflow int */
bb7d92e3 1650 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1651 }
1652
1653 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1654 /* Address Error */
bb7d92e3 1655 ndev->stats.tx_fifo_errors++;
8d5009f6 1656 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1657 }
380af9e3
YS		 1658
1659 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1660 if (mdp->cd->no_ade)
1661 mask &= ~EESR_ADE;
1662 if (intr_status & mask) {
86a74ff2 1663 /* Tx error */
4a55530f 1664 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1665
86a74ff2 1666 /* dmesg */
da246855
SS		 1667 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1668 intr_status, mdp->cur_tx, mdp->dirty_tx,
1669 (u32)ndev->state, edtrr);
86a74ff2
NI		 1670 /* dirty buffer free */
1671 sh_eth_txfree(ndev);
1672
1673 /* SH7712 BUG */
c5ed5368 1674 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1675 /* tx dma start */
c5ed5368 1676 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1677 }
1678 /* wakeup */
1679 netif_wake_queue(ndev);
1680 }
1681}
1682
1683static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1684{
1685 struct net_device *ndev = netdev;
1686 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1687 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1688 irqreturn_t ret = IRQ_NONE;
0799c2d6 1689 u32 intr_status, intr_enable;
86a74ff2 1690
86a74ff2
NI		 1691 spin_lock(&mdp->lock);
1692
3893b273 1693 /* Get interrupt status */
4a55530f 1694 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1695 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1696 * enabled since it's the one that comes thru regardless of the mask,
1697 * and we need to fully handle it in sh_eth_error() in order to quench
1698 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1699 */
3719109d
SS		 1700 intr_enable = sh_eth_read(ndev, EESIPR);
1701 intr_status &= intr_enable | DMAC_M_ECI;
1702 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1703 ret = IRQ_HANDLED;
3719109d 1704 else
283e38db
BH		 1705 goto out;
1706
1707 if (!likely(mdp->irq_enabled)) {
1708 sh_eth_write(ndev, 0, EESIPR);
1709 goto out;
1710 }
86a74ff2 1711
3719109d
SS		 1712 if (intr_status & EESR_RX_CHECK) {
1713 if (napi_schedule_prep(&mdp->napi)) {
1714 /* Mask Rx interrupts */
1715 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1716 EESIPR);
1717 __napi_schedule(&mdp->napi);
1718 } else {
da246855 1719 netdev_warn(ndev,
0799c2d6 1720 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1721 intr_status, intr_enable);
3719109d
SS		 1722 }
1723 }
86a74ff2 1724
b0ca2a21 1725 /* Tx Check */
380af9e3 1726 if (intr_status & cd->tx_check) {
3719109d
SS		 1727 /* Clear Tx interrupts */
1728 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1729
86a74ff2
NI		 1730 sh_eth_txfree(ndev);
1731 netif_wake_queue(ndev);
1732 }
1733
3719109d
SS		 1734 if (intr_status & cd->eesr_err_check) {
1735 /* Clear error interrupts */
1736 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1737
86a74ff2 1738 sh_eth_error(ndev, intr_status);
3719109d 1739 }
86a74ff2 1740
283e38db 1741out:
86a74ff2
NI		 1742 spin_unlock(&mdp->lock);
1743
0e0fde3c 1744 return ret;
86a74ff2
NI		 1745}
1746
3719109d
SS		 1747static int sh_eth_poll(struct napi_struct *napi, int budget)
1748{
1749 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1750 napi);
1751 struct net_device *ndev = napi->dev;
1752 int quota = budget;
0799c2d6 1753 u32 intr_status;
3719109d
SS		 1754
1755 for (;;) {
1756 intr_status = sh_eth_read(ndev, EESR);
1757 if (!(intr_status & EESR_RX_CHECK))
1758 break;
1759 /* Clear Rx interrupts */
1760 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1761
1762 if (sh_eth_rx(ndev, intr_status, &quota))
1763 goto out;
1764 }
1765
1766 napi_complete(napi);
1767
1768 /* Reenable Rx interrupts */
283e38db
BH		 1769 if (mdp->irq_enabled)
1770 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1771out:
1772 return budget - quota;
1773}
1774
86a74ff2
NI		 1775/* PHY state control function */
1776static void sh_eth_adjust_link(struct net_device *ndev)
1777{
1778 struct sh_eth_private *mdp = netdev_priv(ndev);
1779 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1780 int new_state = 0;
1781
3340d2aa 1782 if (phydev->link) {
86a74ff2
NI		 1783 if (phydev->duplex != mdp->duplex) {
1784 new_state = 1;
1785 mdp->duplex = phydev->duplex;
380af9e3
YS		 1786 if (mdp->cd->set_duplex)
1787 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1788 }
1789
1790 if (phydev->speed != mdp->speed) {
1791 new_state = 1;
1792 mdp->speed = phydev->speed;
380af9e3
YS		 1793 if (mdp->cd->set_rate)
1794 mdp->cd->set_rate(ndev);
86a74ff2 1795 }
3340d2aa 1796 if (!mdp->link) {
91a56152 1797 sh_eth_write(ndev,
128296fc
SS		 1798 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1799 ECMR);
86a74ff2
NI		 1800 new_state = 1;
1801 mdp->link = phydev->link;
1e1b812b
SS		 1802 if (mdp->cd->no_psr || mdp->no_ether_link)
1803 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1804 }
1805 } else if (mdp->link) {
1806 new_state = 1;
3340d2aa 1807 mdp->link = 0;
86a74ff2
NI		 1808 mdp->speed = 0;
1809 mdp->duplex = -1;
1e1b812b
SS		 1810 if (mdp->cd->no_psr || mdp->no_ether_link)
1811 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1812 }
1813
dc19e4e5 1814 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1815 phy_print_status(phydev);
1816}
1817
1818/* PHY init function */
1819static int sh_eth_phy_init(struct net_device *ndev)
1820{
702eca02 1821 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1822 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1823 struct phy_device *phydev = NULL;
1824
3340d2aa 1825 mdp->link = 0;
86a74ff2
NI		 1826 mdp->speed = 0;
1827 mdp->duplex = -1;
1828
1829 /* Try connect to PHY */
702eca02
BD		 1830 if (np) {
1831 struct device_node *pn;
1832
1833 pn = of_parse_phandle(np, "phy-handle", 0);
1834 phydev = of_phy_connect(ndev, pn,
1835 sh_eth_adjust_link, 0,
1836 mdp->phy_interface);
1837
1838 if (!phydev)
1839 phydev = ERR_PTR(-ENOENT);
1840 } else {
1841 char phy_id[MII_BUS_ID_SIZE + 3];
1842
1843 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1844 mdp->mii_bus->id, mdp->phy_id);
1845
1846 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1847 mdp->phy_interface);
1848 }
1849
86a74ff2 1850 if (IS_ERR(phydev)) {
da246855 1851 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1852 return PTR_ERR(phydev);
1853 }
380af9e3 1854
da246855
SS		 1855 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1856 phydev->addr, phydev->irq, phydev->drv->name);
86a74ff2
NI		 1857
1858 mdp->phydev = phydev;
1859
1860 return 0;
1861}
1862
1863/* PHY control start function */
1864static int sh_eth_phy_start(struct net_device *ndev)
1865{
1866 struct sh_eth_private *mdp = netdev_priv(ndev);
1867 int ret;
1868
1869 ret = sh_eth_phy_init(ndev);
1870 if (ret)
1871 return ret;
1872
86a74ff2
NI		 1873 phy_start(mdp->phydev);
1874
1875 return 0;
1876}
1877
dc19e4e5 1878static int sh_eth_get_settings(struct net_device *ndev,
128296fc 1879 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1880{
1881 struct sh_eth_private *mdp = netdev_priv(ndev);
1882 unsigned long flags;
1883 int ret;
1884
4f9dce23
BH		 1885 if (!mdp->phydev)
1886 return -ENODEV;
1887
dc19e4e5
NI		 1888 spin_lock_irqsave(&mdp->lock, flags);
1889 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1890 spin_unlock_irqrestore(&mdp->lock, flags);
1891
1892 return ret;
1893}
1894
1895static int sh_eth_set_settings(struct net_device *ndev,
128296fc 1896 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1897{
1898 struct sh_eth_private *mdp = netdev_priv(ndev);
1899 unsigned long flags;
1900 int ret;
dc19e4e5 1901
4f9dce23
BH		 1902 if (!mdp->phydev)
1903 return -ENODEV;
1904
dc19e4e5
NI		 1905 spin_lock_irqsave(&mdp->lock, flags);
1906
1907 /* disable tx and rx */
4a55530f 1908 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1909
1910 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1911 if (ret)
1912 goto error_exit;
1913
1914 if (ecmd->duplex == DUPLEX_FULL)
1915 mdp->duplex = 1;
1916 else
1917 mdp->duplex = 0;
1918
1919 if (mdp->cd->set_duplex)
1920 mdp->cd->set_duplex(ndev);
1921
1922error_exit:
1923 mdelay(1);
1924
1925 /* enable tx and rx */
4a55530f 1926 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1927
1928 spin_unlock_irqrestore(&mdp->lock, flags);
1929
1930 return ret;
1931}
1932
6b4b4fea
BH		 1933/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1934 * version must be bumped as well. Just adding registers up to that
1935 * limit is fine, as long as the existing register indices don't
1936 * change.
1937 */
1938#define SH_ETH_REG_DUMP_VERSION 1
1939#define SH_ETH_REG_DUMP_MAX_REGS 256
1940
1941static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1942{
1943 struct sh_eth_private *mdp = netdev_priv(ndev);
1944 struct sh_eth_cpu_data *cd = mdp->cd;
1945 u32 *valid_map;
1946 size_t len;
1947
1948 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1949
1950 /* Dump starts with a bitmap that tells ethtool which
1951 * registers are defined for this chip.
1952 */
1953 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1954 if (buf) {
1955 valid_map = buf;
1956 buf += len;
1957 } else {
1958 valid_map = NULL;
1959 }
1960
1961 /* Add a register to the dump, if it has a defined offset.
1962 * This automatically skips most undefined registers, but for
1963 * some it is also necessary to check a capability flag in
1964 * struct sh_eth_cpu_data.
1965 */
1966#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1967#define add_reg_from(reg, read_expr) do { \
1968 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1969 if (buf) { \
1970 mark_reg_valid(reg); \
1971 *buf++ = read_expr; \
1972 } \
1973 ++len; \
1974 } \
1975 } while (0)
1976#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1977#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1978
1979 add_reg(EDSR);
1980 add_reg(EDMR);
1981 add_reg(EDTRR);
1982 add_reg(EDRRR);
1983 add_reg(EESR);
1984 add_reg(EESIPR);
1985 add_reg(TDLAR);
1986 add_reg(TDFAR);
1987 add_reg(TDFXR);
1988 add_reg(TDFFR);
1989 add_reg(RDLAR);
1990 add_reg(RDFAR);
1991 add_reg(RDFXR);
1992 add_reg(RDFFR);
1993 add_reg(TRSCER);
1994 add_reg(RMFCR);
1995 add_reg(TFTR);
1996 add_reg(FDR);
1997 add_reg(RMCR);
1998 add_reg(TFUCR);
1999 add_reg(RFOCR);
2000 if (cd->rmiimode)
2001 add_reg(RMIIMODE);
2002 add_reg(FCFTR);
2003 if (cd->rpadir)
2004 add_reg(RPADIR);
2005 if (!cd->no_trimd)
2006 add_reg(TRIMD);
2007 add_reg(ECMR);
2008 add_reg(ECSR);
2009 add_reg(ECSIPR);
2010 add_reg(PIR);
2011 if (!cd->no_psr)
2012 add_reg(PSR);
2013 add_reg(RDMLR);
2014 add_reg(RFLR);
2015 add_reg(IPGR);
2016 if (cd->apr)
2017 add_reg(APR);
2018 if (cd->mpr)
2019 add_reg(MPR);
2020 add_reg(RFCR);
2021 add_reg(RFCF);
2022 if (cd->tpauser)
2023 add_reg(TPAUSER);
2024 add_reg(TPAUSECR);
2025 add_reg(GECMR);
2026 if (cd->bculr)
2027 add_reg(BCULR);
2028 add_reg(MAHR);
2029 add_reg(MALR);
2030 add_reg(TROCR);
2031 add_reg(CDCR);
2032 add_reg(LCCR);
2033 add_reg(CNDCR);
2034 add_reg(CEFCR);
2035 add_reg(FRECR);
2036 add_reg(TSFRCR);
2037 add_reg(TLFRCR);
2038 add_reg(CERCR);
2039 add_reg(CEECR);
2040 add_reg(MAFCR);
2041 if (cd->rtrate)
2042 add_reg(RTRATE);
2043 if (cd->hw_crc)
2044 add_reg(CSMR);
2045 if (cd->select_mii)
2046 add_reg(RMII_MII);
2047 add_reg(ARSTR);
2048 if (cd->tsu) {
2049 add_tsu_reg(TSU_CTRST);
2050 add_tsu_reg(TSU_FWEN0);
2051 add_tsu_reg(TSU_FWEN1);
2052 add_tsu_reg(TSU_FCM);
2053 add_tsu_reg(TSU_BSYSL0);
2054 add_tsu_reg(TSU_BSYSL1);
2055 add_tsu_reg(TSU_PRISL0);
2056 add_tsu_reg(TSU_PRISL1);
2057 add_tsu_reg(TSU_FWSL0);
2058 add_tsu_reg(TSU_FWSL1);
2059 add_tsu_reg(TSU_FWSLC);
2060 add_tsu_reg(TSU_QTAG0);
2061 add_tsu_reg(TSU_QTAG1);
2062 add_tsu_reg(TSU_QTAGM0);
2063 add_tsu_reg(TSU_QTAGM1);
2064 add_tsu_reg(TSU_FWSR);
2065 add_tsu_reg(TSU_FWINMK);
2066 add_tsu_reg(TSU_ADQT0);
2067 add_tsu_reg(TSU_ADQT1);
2068 add_tsu_reg(TSU_VTAG0);
2069 add_tsu_reg(TSU_VTAG1);
2070 add_tsu_reg(TSU_ADSBSY);
2071 add_tsu_reg(TSU_TEN);
2072 add_tsu_reg(TSU_POST1);
2073 add_tsu_reg(TSU_POST2);
2074 add_tsu_reg(TSU_POST3);
2075 add_tsu_reg(TSU_POST4);
2076 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2077 /* This is the start of a table, not just a single
2078 * register.
2079 */
2080 if (buf) {
2081 unsigned int i;
2082
2083 mark_reg_valid(TSU_ADRH0);
2084 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2085 *buf++ = ioread32(
2086 mdp->tsu_addr +
2087 mdp->reg_offset[TSU_ADRH0] +
2088 i * 4);
2089 }
2090 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2091 }
2092 }
2093
2094#undef mark_reg_valid
2095#undef add_reg_from
2096#undef add_reg
2097#undef add_tsu_reg
2098
2099 return len * 4;
2100}
2101
2102static int sh_eth_get_regs_len(struct net_device *ndev)
2103{
2104 return __sh_eth_get_regs(ndev, NULL);
2105}
2106
2107static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2108 void *buf)
2109{
2110 struct sh_eth_private *mdp = netdev_priv(ndev);
2111
2112 regs->version = SH_ETH_REG_DUMP_VERSION;
2113
2114 pm_runtime_get_sync(&mdp->pdev->dev);
2115 __sh_eth_get_regs(ndev, buf);
2116 pm_runtime_put_sync(&mdp->pdev->dev);
2117}
2118
dc19e4e5
NI		 2119static int sh_eth_nway_reset(struct net_device *ndev)
2120{
2121 struct sh_eth_private *mdp = netdev_priv(ndev);
2122 unsigned long flags;
2123 int ret;
2124
4f9dce23
BH		 2125 if (!mdp->phydev)
2126 return -ENODEV;
2127
dc19e4e5
NI		 2128 spin_lock_irqsave(&mdp->lock, flags);
2129 ret = phy_start_aneg(mdp->phydev);
2130 spin_unlock_irqrestore(&mdp->lock, flags);
2131
2132 return ret;
2133}
2134
2135static u32 sh_eth_get_msglevel(struct net_device *ndev)
2136{
2137 struct sh_eth_private *mdp = netdev_priv(ndev);
2138 return mdp->msg_enable;
2139}
2140
2141static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2142{
2143 struct sh_eth_private *mdp = netdev_priv(ndev);
2144 mdp->msg_enable = value;
2145}
2146
2147static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2148 "rx_current", "tx_current",
2149 "rx_dirty", "tx_dirty",
2150};
2151#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2152
2153static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2154{
2155 switch (sset) {
2156 case ETH_SS_STATS:
2157 return SH_ETH_STATS_LEN;
2158 default:
2159 return -EOPNOTSUPP;
2160 }
2161}
2162
2163static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2164 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2165{
2166 struct sh_eth_private *mdp = netdev_priv(ndev);
2167 int i = 0;
2168
2169 /* device-specific stats */
2170 data[i++] = mdp->cur_rx;
2171 data[i++] = mdp->cur_tx;
2172 data[i++] = mdp->dirty_rx;
2173 data[i++] = mdp->dirty_tx;
2174}
2175
2176static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2177{
2178 switch (stringset) {
2179 case ETH_SS_STATS:
2180 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2181 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2182 break;
2183 }
2184}
2185
525b8075
YS		 2186static void sh_eth_get_ringparam(struct net_device *ndev,
2187 struct ethtool_ringparam *ring)
2188{
2189 struct sh_eth_private *mdp = netdev_priv(ndev);
2190
2191 ring->rx_max_pending = RX_RING_MAX;
2192 ring->tx_max_pending = TX_RING_MAX;
2193 ring->rx_pending = mdp->num_rx_ring;
2194 ring->tx_pending = mdp->num_tx_ring;
2195}
2196
2197static int sh_eth_set_ringparam(struct net_device *ndev,
2198 struct ethtool_ringparam *ring)
2199{
2200 struct sh_eth_private *mdp = netdev_priv(ndev);
2201 int ret;
2202
2203 if (ring->tx_pending > TX_RING_MAX ||
2204 ring->rx_pending > RX_RING_MAX ||
2205 ring->tx_pending < TX_RING_MIN ||
2206 ring->rx_pending < RX_RING_MIN)
2207 return -EINVAL;
2208 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2209 return -EINVAL;
2210
2211 if (netif_running(ndev)) {
bd888916 2212 netif_device_detach(ndev);
525b8075 2213 netif_tx_disable(ndev);
283e38db
BH		 2214
2215 /* Serialise with the interrupt handler and NAPI, then
2216 * disable interrupts. We have to clear the
2217 * irq_enabled flag first to ensure that interrupts
2218 * won't be re-enabled.
2219 */
2220 mdp->irq_enabled = false;
525b8075 2221 synchronize_irq(ndev->irq);
283e38db 2222 napi_synchronize(&mdp->napi);
525b8075 2223 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2224
740c7f31 2225 sh_eth_dev_exit(ndev);
525b8075 2226
8e03a5e7 2227 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
084236d8 2228 sh_eth_ring_free(ndev);
084236d8 2229 }
525b8075
YS		 2230
2231 /* Set new parameters */
2232 mdp->num_rx_ring = ring->rx_pending;
2233 mdp->num_tx_ring = ring->tx_pending;
2234
525b8075 2235 if (netif_running(ndev)) {
084236d8
BH		 2236 ret = sh_eth_ring_init(ndev);
2237 if (ret < 0) {
2238 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2239 __func__);
2240 return ret;
2241 }
2242 ret = sh_eth_dev_init(ndev, false);
2243 if (ret < 0) {
2244 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2245 __func__);
2246 return ret;
2247 }
2248
283e38db 2249 mdp->irq_enabled = true;
525b8075
YS		 2250 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2251 /* Setting the Rx mode will start the Rx process. */
2252 sh_eth_write(ndev, EDRRR_R, EDRRR);
bd888916 2253 netif_device_attach(ndev);
525b8075
YS		 2254 }
2255
2256 return 0;
2257}
2258
9b07be4b 2259static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 2260 .get_settings = sh_eth_get_settings,
2261 .set_settings = sh_eth_set_settings,
6b4b4fea
BH		 2262 .get_regs_len = sh_eth_get_regs_len,
2263 .get_regs = sh_eth_get_regs,
9b07be4b 2264 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2265 .get_msglevel = sh_eth_get_msglevel,
2266 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2267 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2268 .get_strings = sh_eth_get_strings,
2269 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2270 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2271 .get_ringparam = sh_eth_get_ringparam,
2272 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 2273};
2274
86a74ff2
NI		 2275/* network device open function */
2276static int sh_eth_open(struct net_device *ndev)
2277{
2278 int ret = 0;
2279 struct sh_eth_private *mdp = netdev_priv(ndev);
2280
bcd5149d
MD		 2281 pm_runtime_get_sync(&mdp->pdev->dev);
2282
d2779e99
SS		 2283 napi_enable(&mdp->napi);
2284
a0607fd3 2285 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2286 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2287 if (ret) {
da246855 2288 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2289 goto out_napi_off;
86a74ff2
NI		 2290 }
2291
2292 /* Descriptor set */
2293 ret = sh_eth_ring_init(ndev);
2294 if (ret)
2295 goto out_free_irq;
2296
2297 /* device init */
525b8075 2298 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2299 if (ret)
2300 goto out_free_irq;
2301
2302 /* PHY control start*/
2303 ret = sh_eth_phy_start(ndev);
2304 if (ret)
2305 goto out_free_irq;
2306
7fa2955f
MK		 2307 mdp->is_opened = 1;
2308
86a74ff2
NI		 2309 return ret;
2310
2311out_free_irq:
2312 free_irq(ndev->irq, ndev);
d2779e99
SS		 2313out_napi_off:
2314 napi_disable(&mdp->napi);
bcd5149d 2315 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2316 return ret;
2317}
2318
2319/* Timeout function */
2320static void sh_eth_tx_timeout(struct net_device *ndev)
2321{
2322 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2323 struct sh_eth_rxdesc *rxdesc;
2324 int i;
2325
2326 netif_stop_queue(ndev);
2327
8d5009f6
SS		 2328 netif_err(mdp, timer, ndev,
2329 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2330 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2331
2332 /* tx_errors count up */
bb7d92e3 2333 ndev->stats.tx_errors++;
86a74ff2 2334
86a74ff2 2335 /* Free all the skbuffs in the Rx queue. */
525b8075 2336 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 2337 rxdesc = &mdp->rx_ring[i];
2338 rxdesc->status = 0;
2339 rxdesc->addr = 0xBADF00D0;
179d80af 2340 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2341 mdp->rx_skbuff[i] = NULL;
2342 }
525b8075 2343 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2344 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2345 mdp->tx_skbuff[i] = NULL;
2346 }
2347
2348 /* device init */
525b8075 2349 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2350}
2351
2352/* Packet transmit function */
2353static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2354{
2355 struct sh_eth_private *mdp = netdev_priv(ndev);
2356 struct sh_eth_txdesc *txdesc;
2357 u32 entry;
fb5e2f9b 2358 unsigned long flags;
86a74ff2
NI		 2359
2360 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2361 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2362 if (!sh_eth_txfree(ndev)) {
8d5009f6 2363 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2364 netif_stop_queue(ndev);
2365 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2366 return NETDEV_TX_BUSY;
86a74ff2
NI		 2367 }
2368 }
2369 spin_unlock_irqrestore(&mdp->lock, flags);
2370
dacc73e0 2371 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2372 return NETDEV_TX_OK;
2373
525b8075 2374 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2375 mdp->tx_skbuff[entry] = skb;
2376 txdesc = &mdp->tx_ring[entry];
86a74ff2 2377 /* soft swap. */
380af9e3
YS		 2378 if (!mdp->cd->hw_swap)
2379 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2380 skb->len + 2);
31fcb99d
YS		 2381 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2382 DMA_TO_DEVICE);
aa3933b8
BH		 2383 if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2384 kfree_skb(skb);
2385 return NETDEV_TX_OK;
2386 }
eebfb643 2387 txdesc->buffer_length = skb->len;
86a74ff2 2388
f32bfb9a 2389 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2390 if (entry >= mdp->num_tx_ring - 1)
71557a37 2391 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 2392 else
71557a37 2393 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 2394
2395 mdp->cur_tx++;
2396
c5ed5368
YS		 2397 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2398 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2399
6ed10654 2400 return NETDEV_TX_OK;
86a74ff2
NI		 2401}
2402
4398f9c8
BH		 2403/* The statistics registers have write-clear behaviour, which means we
2404 * will lose any increment between the read and write. We mitigate
2405 * this by only clearing when we read a non-zero value, so we will
2406 * never falsely report a total of zero.
2407 */
2408static void
2409sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2410{
2411 u32 delta = sh_eth_read(ndev, reg);
2412
2413 if (delta) {
2414 *stat += delta;
2415 sh_eth_write(ndev, 0, reg);
2416 }
2417}
2418
7fa2955f
MK		 2419static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2420{
2421 struct sh_eth_private *mdp = netdev_priv(ndev);
2422
2423 if (sh_eth_is_rz_fast_ether(mdp))
2424 return &ndev->stats;
2425
2426 if (!mdp->is_opened)
2427 return &ndev->stats;
2428
4398f9c8
BH		 2429 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2430 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2431 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f
MK		 2432
2433 if (sh_eth_is_gether(mdp)) {
4398f9c8
BH		 2434 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2435 CERCR);
2436 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2437 CEECR);
7fa2955f 2438 } else {
4398f9c8
BH		 2439 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2440 CNDCR);
7fa2955f
MK		 2441 }
2442
2443 return &ndev->stats;
2444}
2445
86a74ff2
NI		 2446/* device close function */
2447static int sh_eth_close(struct net_device *ndev)
2448{
2449 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2450
2451 netif_stop_queue(ndev);
2452
283e38db
BH		 2453 /* Serialise with the interrupt handler and NAPI, then disable
2454 * interrupts. We have to clear the irq_enabled flag first to
2455 * ensure that interrupts won't be re-enabled.
2456 */
2457 mdp->irq_enabled = false;
2458 synchronize_irq(ndev->irq);
2459 napi_disable(&mdp->napi);
4a55530f 2460 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2461
740c7f31 2462 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2463
2464 /* PHY Disconnect */
2465 if (mdp->phydev) {
2466 phy_stop(mdp->phydev);
2467 phy_disconnect(mdp->phydev);
4f9dce23 2468 mdp->phydev = NULL;
86a74ff2
NI		 2469 }
2470
2471 free_irq(ndev->irq, ndev);
2472
8e03a5e7 2473 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
86a74ff2
NI		 2474 sh_eth_ring_free(ndev);
2475
bcd5149d
MD		 2476 pm_runtime_put_sync(&mdp->pdev->dev);
2477
7fa2955f 2478 mdp->is_opened = 0;
bcd5149d 2479
7fa2955f 2480 return 0;
86a74ff2
NI		 2481}
2482
bb7d92e3 2483/* ioctl to device function */
128296fc 2484static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2
NI		 2485{
2486 struct sh_eth_private *mdp = netdev_priv(ndev);
2487 struct phy_device *phydev = mdp->phydev;
2488
2489 if (!netif_running(ndev))
2490 return -EINVAL;
2491
2492 if (!phydev)
2493 return -ENODEV;
2494
28b04113 2495 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2496}
2497
6743fe6d
YS		 2498/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2499static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2500 int entry)
2501{
2502 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2503}
2504
2505static u32 sh_eth_tsu_get_post_mask(int entry)
2506{
2507 return 0x0f << (28 - ((entry % 8) * 4));
2508}
2509
2510static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2511{
2512 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2513}
2514
2515static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2516 int entry)
2517{
2518 struct sh_eth_private *mdp = netdev_priv(ndev);
2519 u32 tmp;
2520 void *reg_offset;
2521
2522 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2523 tmp = ioread32(reg_offset);
2524 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2525}
2526
2527static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2528 int entry)
2529{
2530 struct sh_eth_private *mdp = netdev_priv(ndev);
2531 u32 post_mask, ref_mask, tmp;
2532 void *reg_offset;
2533
2534 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2535 post_mask = sh_eth_tsu_get_post_mask(entry);
2536 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2537
2538 tmp = ioread32(reg_offset);
2539 iowrite32(tmp & ~post_mask, reg_offset);
2540
2541 /* If other port enables, the function returns "true" */
2542 return tmp & ref_mask;
2543}
2544
2545static int sh_eth_tsu_busy(struct net_device *ndev)
2546{
2547 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2548 struct sh_eth_private *mdp = netdev_priv(ndev);
2549
2550 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2551 udelay(10);
2552 timeout--;
2553 if (timeout <= 0) {
da246855 2554 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2555 return -ETIMEDOUT;
2556 }
2557 }
2558
2559 return 0;
2560}
2561
2562static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2563 const u8 *addr)
2564{
2565 u32 val;
2566
2567 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2568 iowrite32(val, reg);
2569 if (sh_eth_tsu_busy(ndev) < 0)
2570 return -EBUSY;
2571
2572 val = addr[4] << 8 | addr[5];
2573 iowrite32(val, reg + 4);
2574 if (sh_eth_tsu_busy(ndev) < 0)
2575 return -EBUSY;
2576
2577 return 0;
2578}
2579
2580static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2581{
2582 u32 val;
2583
2584 val = ioread32(reg);
2585 addr[0] = (val >> 24) & 0xff;
2586 addr[1] = (val >> 16) & 0xff;
2587 addr[2] = (val >> 8) & 0xff;
2588 addr[3] = val & 0xff;
2589 val = ioread32(reg + 4);
2590 addr[4] = (val >> 8) & 0xff;
2591 addr[5] = val & 0xff;
2592}
2593
2594
2595static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2596{
2597 struct sh_eth_private *mdp = netdev_priv(ndev);
2598 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2599 int i;
2600 u8 c_addr[ETH_ALEN];
2601
2602 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2603 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2604 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2605 return i;
2606 }
2607
2608 return -ENOENT;
2609}
2610
2611static int sh_eth_tsu_find_empty(struct net_device *ndev)
2612{
2613 u8 blank[ETH_ALEN];
2614 int entry;
2615
2616 memset(blank, 0, sizeof(blank));
2617 entry = sh_eth_tsu_find_entry(ndev, blank);
2618 return (entry < 0) ? -ENOMEM : entry;
2619}
2620
2621static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2622 int entry)
2623{
2624 struct sh_eth_private *mdp = netdev_priv(ndev);
2625 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2626 int ret;
2627 u8 blank[ETH_ALEN];
2628
2629 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2630 ~(1 << (31 - entry)), TSU_TEN);
2631
2632 memset(blank, 0, sizeof(blank));
2633 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2634 if (ret < 0)
2635 return ret;
2636 return 0;
2637}
2638
2639static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2640{
2641 struct sh_eth_private *mdp = netdev_priv(ndev);
2642 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2643 int i, ret;
2644
2645 if (!mdp->cd->tsu)
2646 return 0;
2647
2648 i = sh_eth_tsu_find_entry(ndev, addr);
2649 if (i < 0) {
2650 /* No entry found, create one */
2651 i = sh_eth_tsu_find_empty(ndev);
2652 if (i < 0)
2653 return -ENOMEM;
2654 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2655 if (ret < 0)
2656 return ret;
2657
2658 /* Enable the entry */
2659 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2660 (1 << (31 - i)), TSU_TEN);
2661 }
2662
2663 /* Entry found or created, enable POST */
2664 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2665
2666 return 0;
2667}
2668
2669static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2670{
2671 struct sh_eth_private *mdp = netdev_priv(ndev);
2672 int i, ret;
2673
2674 if (!mdp->cd->tsu)
2675 return 0;
2676
2677 i = sh_eth_tsu_find_entry(ndev, addr);
2678 if (i) {
2679 /* Entry found */
2680 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2681 goto done;
2682
2683 /* Disable the entry if both ports was disabled */
2684 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2685 if (ret < 0)
2686 return ret;
2687 }
2688done:
2689 return 0;
2690}
2691
2692static int sh_eth_tsu_purge_all(struct net_device *ndev)
2693{
2694 struct sh_eth_private *mdp = netdev_priv(ndev);
2695 int i, ret;
2696
b37feed7 2697 if (!mdp->cd->tsu)
6743fe6d
YS		 2698 return 0;
2699
2700 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2701 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2702 continue;
2703
2704 /* Disable the entry if both ports was disabled */
2705 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2706 if (ret < 0)
2707 return ret;
2708 }
2709
2710 return 0;
2711}
2712
2713static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2714{
2715 struct sh_eth_private *mdp = netdev_priv(ndev);
2716 u8 addr[ETH_ALEN];
2717 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2718 int i;
2719
b37feed7 2720 if (!mdp->cd->tsu)
6743fe6d
YS		 2721 return;
2722
2723 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2724 sh_eth_tsu_read_entry(reg_offset, addr);
2725 if (is_multicast_ether_addr(addr))
2726 sh_eth_tsu_del_entry(ndev, addr);
2727 }
2728}
2729
b37feed7
BH		 2730/* Update promiscuous flag and multicast filter */
2731static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2732{
6743fe6d
YS		 2733 struct sh_eth_private *mdp = netdev_priv(ndev);
2734 u32 ecmr_bits;
2735 int mcast_all = 0;
2736 unsigned long flags;
2737
2738 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2739 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2740 * Depending on ndev->flags, set PRM or clear MCT
2741 */
b37feed7
BH		 2742 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2743 if (mdp->cd->tsu)
2744 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2745
2746 if (!(ndev->flags & IFF_MULTICAST)) {
2747 sh_eth_tsu_purge_mcast(ndev);
2748 mcast_all = 1;
2749 }
2750 if (ndev->flags & IFF_ALLMULTI) {
2751 sh_eth_tsu_purge_mcast(ndev);
2752 ecmr_bits &= ~ECMR_MCT;
2753 mcast_all = 1;
2754 }
2755
86a74ff2 2756 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2757 sh_eth_tsu_purge_all(ndev);
2758 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2759 } else if (mdp->cd->tsu) {
2760 struct netdev_hw_addr *ha;
2761 netdev_for_each_mc_addr(ha, ndev) {
2762 if (mcast_all && is_multicast_ether_addr(ha->addr))
2763 continue;
2764
2765 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2766 if (!mcast_all) {
2767 sh_eth_tsu_purge_mcast(ndev);
2768 ecmr_bits &= ~ECMR_MCT;
2769 mcast_all = 1;
2770 }
2771 }
2772 }
86a74ff2 2773 }
6743fe6d
YS		 2774
2775 /* update the ethernet mode */
2776 sh_eth_write(ndev, ecmr_bits, ECMR);
2777
2778 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2779}
71cc7c37
YS		 2780
2781static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2782{
2783 if (!mdp->port)
2784 return TSU_VTAG0;
2785 else
2786 return TSU_VTAG1;
2787}
2788
80d5c368
PM		 2789static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2790 __be16 proto, u16 vid)
71cc7c37
YS		 2791{
2792 struct sh_eth_private *mdp = netdev_priv(ndev);
2793 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2794
2795 if (unlikely(!mdp->cd->tsu))
2796 return -EPERM;
2797
2798 /* No filtering if vid = 0 */
2799 if (!vid)
2800 return 0;
2801
2802 mdp->vlan_num_ids++;
2803
128296fc 2804 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2805 * already enabled, the driver disables it and the filte
2806 */
2807 if (mdp->vlan_num_ids > 1) {
2808 /* disable VLAN filter */
2809 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2810 return 0;
2811 }
2812
2813 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2814 vtag_reg_index);
2815
2816 return 0;
2817}
2818
80d5c368
PM		 2819static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2820 __be16 proto, u16 vid)
71cc7c37
YS		 2821{
2822 struct sh_eth_private *mdp = netdev_priv(ndev);
2823 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2824
2825 if (unlikely(!mdp->cd->tsu))
2826 return -EPERM;
2827
2828 /* No filtering if vid = 0 */
2829 if (!vid)
2830 return 0;
2831
2832 mdp->vlan_num_ids--;
2833 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2834
2835 return 0;
2836}
86a74ff2
NI		 2837
2838/* SuperH's TSU register init function */
4a55530f 2839static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2840{
db893473
SH		 2841 if (sh_eth_is_rz_fast_ether(mdp)) {
2842 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2843 return;
2844 }
2845
4a55530f
YS		 2846 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2847 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2848 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2849 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2850 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2851 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2852 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2853 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2854 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2855 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2856 if (sh_eth_is_gether(mdp)) {
2857 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2858 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2859 } else {
2860 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2861 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2862 }
4a55530f
YS		 2863 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2864 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2865 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2866 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2867 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2868 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2869 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2870}
2871
2872/* MDIO bus release function */
bd920ff5 2873static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2874{
86a74ff2 2875 /* unregister mdio bus */
bd920ff5 2876 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2877
2878 /* free bitbang info */
bd920ff5 2879 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2880
2881 return 0;
2882}
2883
2884/* MDIO bus init function */
bd920ff5 2885static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2886 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2887{
2888 int ret, i;
2889 struct bb_info *bitbang;
bd920ff5 2890 struct platform_device *pdev = mdp->pdev;
aa8d4225 2891 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2892
2893 /* create bit control struct for PHY */
aa8d4225 2894 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2895 if (!bitbang)
2896 return -ENOMEM;
86a74ff2
NI		 2897
2898 /* bitbang init */
ae70644d 2899 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2900 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2901 bitbang->mdi_msk = PIR_MDI;
2902 bitbang->mdo_msk = PIR_MDO;
2903 bitbang->mmd_msk = PIR_MMD;
2904 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2905 bitbang->ctrl.ops = &bb_ops;
2906
c2e07b3a 2907 /* MII controller setting */
86a74ff2 2908 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2909 if (!mdp->mii_bus)
2910 return -ENOMEM;
86a74ff2
NI		 2911
2912 /* Hook up MII support for ethtool */
2913 mdp->mii_bus->name = "sh_mii";
a5bd6060 2914 mdp->mii_bus->parent = dev;
5278fb54 2915 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2916 pdev->name, pdev->id);
86a74ff2
NI		 2917
2918 /* PHY IRQ */
86b5d251
SS		 2919 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2920 GFP_KERNEL);
86a74ff2
NI		 2921 if (!mdp->mii_bus->irq) {
2922 ret = -ENOMEM;
2923 goto out_free_bus;
2924 }
2925
bd920ff5
LP		 2926 /* register MDIO bus */
2927 if (dev->of_node) {
2928 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02
BD		 2929 } else {
2930 for (i = 0; i < PHY_MAX_ADDR; i++)
2931 mdp->mii_bus->irq[i] = PHY_POLL;
2932 if (pd->phy_irq > 0)
2933 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2934
2935 ret = mdiobus_register(mdp->mii_bus);
2936 }
2937
86a74ff2 2938 if (ret)
d5e07e69 2939 goto out_free_bus;
86a74ff2 2940
86a74ff2
NI		 2941 return 0;
2942
86a74ff2 2943out_free_bus:
298cf9be 2944 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2945 return ret;
2946}
2947
4a55530f
YS		 2948static const u16 *sh_eth_get_register_offset(int register_type)
2949{
2950 const u16 *reg_offset = NULL;
2951
2952 switch (register_type) {
2953 case SH_ETH_REG_GIGABIT:
2954 reg_offset = sh_eth_offset_gigabit;
2955 break;
db893473
SH		 2956 case SH_ETH_REG_FAST_RZ:
2957 reg_offset = sh_eth_offset_fast_rz;
2958 break;
a3f109bd
SS		 2959 case SH_ETH_REG_FAST_RCAR:
2960 reg_offset = sh_eth_offset_fast_rcar;
2961 break;
4a55530f
YS		 2962 case SH_ETH_REG_FAST_SH4:
2963 reg_offset = sh_eth_offset_fast_sh4;
2964 break;
2965 case SH_ETH_REG_FAST_SH3_SH2:
2966 reg_offset = sh_eth_offset_fast_sh3_sh2;
2967 break;
2968 default:
4a55530f
YS		 2969 break;
2970 }
2971
2972 return reg_offset;
2973}
2974
8f728d79 2975static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2976 .ndo_open = sh_eth_open,
2977 .ndo_stop = sh_eth_close,
2978 .ndo_start_xmit = sh_eth_start_xmit,
2979 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2980 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 2981 .ndo_tx_timeout = sh_eth_tx_timeout,
2982 .ndo_do_ioctl = sh_eth_do_ioctl,
2983 .ndo_validate_addr = eth_validate_addr,
2984 .ndo_set_mac_address = eth_mac_addr,
2985 .ndo_change_mtu = eth_change_mtu,
2986};
2987
8f728d79
SS		 2988static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2989 .ndo_open = sh_eth_open,
2990 .ndo_stop = sh_eth_close,
2991 .ndo_start_xmit = sh_eth_start_xmit,
2992 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2993 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 2994 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2995 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2996 .ndo_tx_timeout = sh_eth_tx_timeout,
2997 .ndo_do_ioctl = sh_eth_do_ioctl,
2998 .ndo_validate_addr = eth_validate_addr,
2999 .ndo_set_mac_address = eth_mac_addr,
3000 .ndo_change_mtu = eth_change_mtu,
3001};
3002
b356e978
SS		 3003#ifdef CONFIG_OF
3004static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3005{
3006 struct device_node *np = dev->of_node;
3007 struct sh_eth_plat_data *pdata;
b356e978
SS		 3008 const char *mac_addr;
3009
3010 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3011 if (!pdata)
3012 return NULL;
3013
3014 pdata->phy_interface = of_get_phy_mode(np);
3015
b356e978
SS		 3016 mac_addr = of_get_mac_address(np);
3017 if (mac_addr)
3018 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3019
3020 pdata->no_ether_link =
3021 of_property_read_bool(np, "renesas,no-ether-link");
3022 pdata->ether_link_active_low =
3023 of_property_read_bool(np, "renesas,ether-link-active-low");
3024
3025 return pdata;
3026}
3027
3028static const struct of_device_id sh_eth_match_table[] = {
3029 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3030 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3031 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3032 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3033 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 3034 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 3035 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 3036 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3037 { }
3038};
3039MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3040#else
3041static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3042{
3043 return NULL;
3044}
3045#endif
3046
86a74ff2
NI		 3047static int sh_eth_drv_probe(struct platform_device *pdev)
3048{
9c38657c 3049 int ret, devno = 0;
86a74ff2
NI		 3050 struct resource *res;
3051 struct net_device *ndev = NULL;
ec0d7551 3052 struct sh_eth_private *mdp = NULL;
0b76b862 3053 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 3054 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 3055
3056 /* get base addr */
3057 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 3058
3059 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 3060 if (!ndev)
3061 return -ENOMEM;
86a74ff2 3062
b5893a08
BD		 3063 pm_runtime_enable(&pdev->dev);
3064 pm_runtime_get_sync(&pdev->dev);
3065
86a74ff2
NI		 3066 devno = pdev->id;
3067 if (devno < 0)
3068 devno = 0;
3069
3070 ndev->dma = -1;
cc3c080d 3071 ret = platform_get_irq(pdev, 0);
7a468ac6 3072 if (ret < 0)
86a74ff2 3073 goto out_release;
cc3c080d 3074 ndev->irq = ret;
86a74ff2
NI		 3075
3076 SET_NETDEV_DEV(ndev, &pdev->dev);
3077
86a74ff2 3078 mdp = netdev_priv(ndev);
525b8075
YS		 3079 mdp->num_tx_ring = TX_RING_SIZE;
3080 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3081 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3082 if (IS_ERR(mdp->addr)) {
3083 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3084 goto out_release;
3085 }
3086
c960804f
VB		 3087 ndev->base_addr = res->start;
3088
86a74ff2 3089 spin_lock_init(&mdp->lock);
bcd5149d 3090 mdp->pdev = pdev;
86a74ff2 3091
b356e978
SS		 3092 if (pdev->dev.of_node)
3093 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3094 if (!pd) {
3095 dev_err(&pdev->dev, "no platform data\n");
3096 ret = -EINVAL;
3097 goto out_release;
3098 }
3099
86a74ff2 3100 /* get PHY ID */
71557a37 3101 mdp->phy_id = pd->phy;
e47c9052 3102 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 3103 /* EDMAC endian */
3104 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 3105 mdp->no_ether_link = pd->no_ether_link;
3106 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3107
380af9e3 3108 /* set cpu data */
b356e978
SS		 3109 if (id) {
3110 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3111 } else {
3112 const struct of_device_id *match;
3113
3114 match = of_match_device(of_match_ptr(sh_eth_match_table),
3115 &pdev->dev);
3116 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3117 }
a3153d8c 3118 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3119 if (!mdp->reg_offset) {
3120 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3121 mdp->cd->register_type);
3122 ret = -EINVAL;
3123 goto out_release;
3124 }
380af9e3
YS		 3125 sh_eth_set_default_cpu_data(mdp->cd);
3126
86a74ff2 3127 /* set function */
8f728d79
SS		 3128 if (mdp->cd->tsu)
3129 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3130 else
3131 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3132 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3133 ndev->watchdog_timeo = TX_TIMEOUT;
3134
dc19e4e5
NI		 3135 /* debug message level */
3136 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3137
3138 /* read and set MAC address */
748031f9 3139 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3140 if (!is_valid_ether_addr(ndev->dev_addr)) {
3141 dev_warn(&pdev->dev,
3142 "no valid MAC address supplied, using a random one.\n");
3143 eth_hw_addr_random(ndev);
3144 }
86a74ff2 3145
6ba88021
YS		 3146 /* ioremap the TSU registers */
3147 if (mdp->cd->tsu) {
3148 struct resource *rtsu;
3149 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 3150 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3151 if (IS_ERR(mdp->tsu_addr)) {
3152 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 3153 goto out_release;
3154 }
6743fe6d 3155 mdp->port = devno % 2;
f646968f 3156 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 3157 }
3158
150647fb
YS		 3159 /* initialize first or needed device */
3160 if (!devno || pd->needs_init) {
380af9e3
YS		 3161 if (mdp->cd->chip_reset)
3162 mdp->cd->chip_reset(ndev);
86a74ff2 3163
4986b996
YS		 3164 if (mdp->cd->tsu) {
3165 /* TSU init (Init only)*/
3166 sh_eth_tsu_init(mdp);
3167 }
86a74ff2
NI		 3168 }
3169
966d6dbb
HN		 3170 if (mdp->cd->rmiimode)
3171 sh_eth_write(ndev, 0x1, RMIIMODE);
3172
daacf03f
LP		 3173 /* MDIO bus init */
3174 ret = sh_mdio_init(mdp, pd);
3175 if (ret) {
3176 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3177 goto out_release;
3178 }
3179
3719109d
SS		 3180 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3181
86a74ff2
NI		 3182 /* network device register */
3183 ret = register_netdev(ndev);
3184 if (ret)
3719109d 3185 goto out_napi_del;
86a74ff2 3186
25985edc 3187 /* print device information */
f75f14ec
SS		 3188 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3189 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3190
b5893a08 3191 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3192 platform_set_drvdata(pdev, ndev);
3193
3194 return ret;
3195
3719109d
SS		 3196out_napi_del:
3197 netif_napi_del(&mdp->napi);
daacf03f 3198 sh_mdio_release(mdp);
3719109d 3199
86a74ff2
NI		 3200out_release:
3201 /* net_dev free */
3202 if (ndev)
3203 free_netdev(ndev);
3204
b5893a08
BD		 3205 pm_runtime_put(&pdev->dev);
3206 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3207 return ret;
3208}
3209
3210static int sh_eth_drv_remove(struct platform_device *pdev)
3211{
3212 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3213 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3214
86a74ff2 3215 unregister_netdev(ndev);
3719109d 3216 netif_napi_del(&mdp->napi);
daacf03f 3217 sh_mdio_release(mdp);
bcd5149d 3218 pm_runtime_disable(&pdev->dev);
86a74ff2 3219 free_netdev(ndev);
86a74ff2
NI		 3220
3221 return 0;
3222}
3223
540ad1b8 3224#ifdef CONFIG_PM
b71af046
MU		 3225#ifdef CONFIG_PM_SLEEP
3226static int sh_eth_suspend(struct device *dev)
3227{
3228 struct net_device *ndev = dev_get_drvdata(dev);
3229 int ret = 0;
3230
3231 if (netif_running(ndev)) {
3232 netif_device_detach(ndev);
3233 ret = sh_eth_close(ndev);
3234 }
3235
3236 return ret;
3237}
3238
3239static int sh_eth_resume(struct device *dev)
3240{
3241 struct net_device *ndev = dev_get_drvdata(dev);
3242 int ret = 0;
3243
3244 if (netif_running(ndev)) {
3245 ret = sh_eth_open(ndev);
3246 if (ret < 0)
3247 return ret;
3248 netif_device_attach(ndev);
3249 }
3250
3251 return ret;
3252}
3253#endif
3254
bcd5149d
MD		 3255static int sh_eth_runtime_nop(struct device *dev)
3256{
128296fc 3257 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3258 * and ->runtime_resume(). Simply returns success.
3259 *
3260 * This driver re-initializes all registers after
3261 * pm_runtime_get_sync() anyway so there is no need
3262 * to save and restore registers here.
3263 */
3264 return 0;
3265}
3266
540ad1b8 3267static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3268 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3269 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3270};
540ad1b8
NI		 3271#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3272#else
3273#define SH_ETH_PM_OPS NULL
3274#endif
bcd5149d 3275
afe391ad 3276static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3277 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3278 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3279 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3280 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3281 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3282 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3283 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
e5c9b4cd 3284 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
589ebdef 3285 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
afe391ad
SS		 3286 { }
3287};
3288MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3289
86a74ff2
NI		 3290static struct platform_driver sh_eth_driver = {
3291 .probe = sh_eth_drv_probe,
3292 .remove = sh_eth_drv_remove,
afe391ad 3293 .id_table = sh_eth_id_table,
86a74ff2
NI		 3294 .driver = {
3295 .name = CARDNAME,
540ad1b8 3296 .pm = SH_ETH_PM_OPS,
b356e978 3297 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3298 },
3299};
3300
db62f684 3301module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3302
3303MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3304MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3305MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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