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sfc: Allow event queue initialisation to fail
[deliverable/linux.git] / drivers / net / ethernet / sfc / efx.c
CommitLineData
8ceee660
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
0a6f40c6 4 * Copyright 2005-2011 Solarflare Communications Inc.
8ceee660
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
8ceee660 20#include <linux/ethtool.h>
aa6ef27e 21#include <linux/topology.h>
5a0e3ad6 22#include <linux/gfp.h>
626950db 23#include <linux/aer.h>
b28405b0 24#include <linux/interrupt.h>
8ceee660 25#include "net_driver.h"
8ceee660 26#include "efx.h"
744093c9 27#include "nic.h"
dd40781e 28#include "selftest.h"
8ceee660 29
8880f4ec 30#include "mcdi.h"
fd371e32 31#include "workarounds.h"
8880f4ec 32
c459302d
BH		 33/**************************************************************************
34 *
35 * Type name strings
36 *
37 **************************************************************************
38 */
39
40/* Loopback mode names (see LOOPBACK_MODE()) */
41const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
18e83e4c 42const char *const efx_loopback_mode_names[] = {
c459302d 43 [LOOPBACK_NONE] = "NONE",
e58f69f4 44 [LOOPBACK_DATA] = "DATAPATH",
c459302d
BH		 45 [LOOPBACK_GMAC] = "GMAC",
46 [LOOPBACK_XGMII] = "XGMII",
47 [LOOPBACK_XGXS] = "XGXS",
9c636baf
BH		 48 [LOOPBACK_XAUI] = "XAUI",
49 [LOOPBACK_GMII] = "GMII",
50 [LOOPBACK_SGMII] = "SGMII",
e58f69f4
BH		 51 [LOOPBACK_XGBR] = "XGBR",
52 [LOOPBACK_XFI] = "XFI",
53 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
54 [LOOPBACK_GMII_FAR] = "GMII_FAR",
55 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
56 [LOOPBACK_XFI_FAR] = "XFI_FAR",
c459302d
BH		 57 [LOOPBACK_GPHY] = "GPHY",
58 [LOOPBACK_PHYXS] = "PHYXS",
9c636baf
BH		 59 [LOOPBACK_PCS] = "PCS",
60 [LOOPBACK_PMAPMD] = "PMA/PMD",
e58f69f4
BH		 61 [LOOPBACK_XPORT] = "XPORT",
62 [LOOPBACK_XGMII_WS] = "XGMII_WS",
9c636baf 63 [LOOPBACK_XAUI_WS] = "XAUI_WS",
e58f69f4
BH		 64 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
65 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
9c636baf 66 [LOOPBACK_GMII_WS] = "GMII_WS",
e58f69f4
BH		 67 [LOOPBACK_XFI_WS] = "XFI_WS",
68 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
9c636baf 69 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
c459302d
BH		 70};
71
c459302d 72const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
18e83e4c 73const char *const efx_reset_type_names[] = {
626950db
AR		 74 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
75 [RESET_TYPE_ALL] = "ALL",
76 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
77 [RESET_TYPE_WORLD] = "WORLD",
78 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
79 [RESET_TYPE_DISABLE] = "DISABLE",
80 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
81 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
82 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
3de82b91 83 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR",
626950db
AR		 84 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
85 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
c459302d
BH		 86};
87
1ab00629
SH		 88/* Reset workqueue. If any NIC has a hardware failure then a reset will be
89 * queued onto this work queue. This is not a per-nic work queue, because
90 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
91 */
92static struct workqueue_struct *reset_workqueue;
93
8ceee660
BH		 94/**************************************************************************
95 *
96 * Configurable values
97 *
98 *************************************************************************/
99
8ceee660
BH		 100/*
101 * Use separate channels for TX and RX events
102 *
28b581ab
NT		 103 * Set this to 1 to use separate channels for TX and RX. It allows us
104 * to control interrupt affinity separately for TX and RX.
8ceee660 105 *
28b581ab 106 * This is only used in MSI-X interrupt mode
8ceee660 107 */
b9cc977d
BH		 108static bool separate_tx_channels;
109module_param(separate_tx_channels, bool, 0444);
28b581ab
NT		 110MODULE_PARM_DESC(separate_tx_channels,
111 "Use separate channels for TX and RX");
8ceee660
BH		 112
113/* This is the weight assigned to each of the (per-channel) virtual
114 * NAPI devices.
115 */
116static int napi_weight = 64;
117
118/* This is the time (in jiffies) between invocations of the hardware
626950db
AR		 119 * monitor.
120 * On Falcon-based NICs, this will:
e254c274
BH		 121 * - Check the on-board hardware monitor;
122 * - Poll the link state and reconfigure the hardware as necessary.
626950db
AR		 123 * On Siena-based NICs for power systems with EEH support, this will give EEH a
124 * chance to start.
8ceee660 125 */
d215697f 126static unsigned int efx_monitor_interval = 1 * HZ;
8ceee660 127
8ceee660
BH		 128/* Initial interrupt moderation settings. They can be modified after
129 * module load with ethtool.
130 *
131 * The default for RX should strike a balance between increasing the
132 * round-trip latency and reducing overhead.
133 */
134static unsigned int rx_irq_mod_usec = 60;
135
136/* Initial interrupt moderation settings. They can be modified after
137 * module load with ethtool.
138 *
139 * This default is chosen to ensure that a 10G link does not go idle
140 * while a TX queue is stopped after it has become full. A queue is
141 * restarted when it drops below half full. The time this takes (assuming
142 * worst case 3 descriptors per packet and 1024 descriptors) is
143 * 512 / 3 * 1.2 = 205 usec.
144 */
145static unsigned int tx_irq_mod_usec = 150;
146
147/* This is the first interrupt mode to try out of:
148 * 0 => MSI-X
149 * 1 => MSI
150 * 2 => legacy
151 */
152static unsigned int interrupt_mode;
153
154/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
155 * i.e. the number of CPUs among which we may distribute simultaneous
156 * interrupt handling.
157 *
158 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
cdb08f8f 159 * The default (0) means to assign an interrupt to each core.
8ceee660
BH		 160 */
161static unsigned int rss_cpus;
162module_param(rss_cpus, uint, 0444);
163MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
164
b9cc977d
BH		 165static bool phy_flash_cfg;
166module_param(phy_flash_cfg, bool, 0644);
84ae48fe
BH		 167MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
168
e7bed9c8 169static unsigned irq_adapt_low_thresh = 8000;
6fb70fd1
BH		 170module_param(irq_adapt_low_thresh, uint, 0644);
171MODULE_PARM_DESC(irq_adapt_low_thresh,
172 "Threshold score for reducing IRQ moderation");
173
e7bed9c8 174static unsigned irq_adapt_high_thresh = 16000;
6fb70fd1
BH		 175module_param(irq_adapt_high_thresh, uint, 0644);
176MODULE_PARM_DESC(irq_adapt_high_thresh,
177 "Threshold score for increasing IRQ moderation");
178
62776d03
BH		 179static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
180 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
181 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
182 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
183module_param(debug, uint, 0);
184MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
185
8ceee660
BH		 186/**************************************************************************
187 *
188 * Utility functions and prototypes
189 *
190 *************************************************************************/
4642610c 191
261e4d96 192static int efx_soft_enable_interrupts(struct efx_nic *efx);
d8291187 193static void efx_soft_disable_interrupts(struct efx_nic *efx);
7f967c01 194static void efx_remove_channel(struct efx_channel *channel);
4642610c 195static void efx_remove_channels(struct efx_nic *efx);
7f967c01 196static const struct efx_channel_type efx_default_channel_type;
8ceee660 197static void efx_remove_port(struct efx_nic *efx);
7f967c01 198static void efx_init_napi_channel(struct efx_channel *channel);
8ceee660 199static void efx_fini_napi(struct efx_nic *efx);
e8f14992 200static void efx_fini_napi_channel(struct efx_channel *channel);
4642610c
BH		 201static void efx_fini_struct(struct efx_nic *efx);
202static void efx_start_all(struct efx_nic *efx);
203static void efx_stop_all(struct efx_nic *efx);
8ceee660
BH		 204
205#define EFX_ASSERT_RESET_SERIALISED(efx) \
206 do { \
f16aeea0 207 if ((efx->state == STATE_READY) || \
626950db 208 (efx->state == STATE_RECOVERY) || \
332c1ce9 209 (efx->state == STATE_DISABLED)) \
8ceee660
BH		 210 ASSERT_RTNL(); \
211 } while (0)
212
8b7325b4
BH		 213static int efx_check_disabled(struct efx_nic *efx)
214{
626950db 215 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) {
8b7325b4
BH		 216 netif_err(efx, drv, efx->net_dev,
217 "device is disabled due to earlier errors\n");
218 return -EIO;
219 }
220 return 0;
221}
222
8ceee660
BH		 223/**************************************************************************
224 *
225 * Event queue processing
226 *
227 *************************************************************************/
228
229/* Process channel's event queue
230 *
231 * This function is responsible for processing the event queue of a
232 * single channel. The caller must guarantee that this function will
233 * never be concurrently called more than once on the same channel,
234 * though different channels may be being processed concurrently.
235 */
fa236e18 236static int efx_process_channel(struct efx_channel *channel, int budget)
8ceee660 237{
fa236e18 238 int spent;
8ceee660 239
9f2cb71c 240 if (unlikely(!channel->enabled))
42cbe2d7 241 return 0;
8ceee660 242
fa236e18 243 spent = efx_nic_process_eventq(channel, budget);
d9ab7007
BH		 244 if (spent && efx_channel_has_rx_queue(channel)) {
245 struct efx_rx_queue *rx_queue =
246 efx_channel_get_rx_queue(channel);
247
ff734ef4 248 efx_rx_flush_packet(channel);
d8aec745 249 efx_fast_push_rx_descriptors(rx_queue);
8ceee660
BH		 250 }
251
fa236e18 252 return spent;
8ceee660
BH		 253}
254
8ceee660
BH		 255/* NAPI poll handler
256 *
257 * NAPI guarantees serialisation of polls of the same device, which
258 * provides the guarantee required by efx_process_channel().
259 */
260static int efx_poll(struct napi_struct *napi, int budget)
261{
262 struct efx_channel *channel =
263 container_of(napi, struct efx_channel, napi_str);
62776d03 264 struct efx_nic *efx = channel->efx;
fa236e18 265 int spent;
8ceee660 266
62776d03
BH		 267 netif_vdbg(efx, intr, efx->net_dev,
268 "channel %d NAPI poll executing on CPU %d\n",
269 channel->channel, raw_smp_processor_id());
8ceee660 270
fa236e18 271 spent = efx_process_channel(channel, budget);
8ceee660 272
fa236e18 273 if (spent < budget) {
9d9a6973 274 if (efx_channel_has_rx_queue(channel) &&
6fb70fd1
BH		 275 efx->irq_rx_adaptive &&
276 unlikely(++channel->irq_count == 1000)) {
6fb70fd1
BH		 277 if (unlikely(channel->irq_mod_score <
278 irq_adapt_low_thresh)) {
0d86ebd8
BH		 279 if (channel->irq_moderation > 1) {
280 channel->irq_moderation -= 1;
ef2b90ee 281 efx->type->push_irq_moderation(channel);
0d86ebd8 282 }
6fb70fd1
BH		 283 } else if (unlikely(channel->irq_mod_score >
284 irq_adapt_high_thresh)) {
0d86ebd8
BH		 285 if (channel->irq_moderation <
286 efx->irq_rx_moderation) {
287 channel->irq_moderation += 1;
ef2b90ee 288 efx->type->push_irq_moderation(channel);
0d86ebd8 289 }
6fb70fd1 290 }
6fb70fd1
BH		 291 channel->irq_count = 0;
292 channel->irq_mod_score = 0;
293 }
294
64d8ad6d
BH		 295 efx_filter_rfs_expire(channel);
296
8ceee660 297 /* There is no race here; although napi_disable() will
288379f0 298 * only wait for napi_complete(), this isn't a problem
514bedbc 299 * since efx_nic_eventq_read_ack() will have no effect if
8ceee660
BH		 300 * interrupts have already been disabled.
301 */
288379f0 302 napi_complete(napi);
514bedbc 303 efx_nic_eventq_read_ack(channel);
8ceee660
BH		 304 }
305
fa236e18 306 return spent;
8ceee660
BH		 307}
308
8ceee660
BH		 309/* Create event queue
310 * Event queue memory allocations are done only once. If the channel
311 * is reset, the memory buffer will be reused; this guards against
312 * errors during channel reset and also simplifies interrupt handling.
313 */
314static int efx_probe_eventq(struct efx_channel *channel)
315{
ecc910f5
SH		 316 struct efx_nic *efx = channel->efx;
317 unsigned long entries;
318
86ee5302 319 netif_dbg(efx, probe, efx->net_dev,
62776d03 320 "chan %d create event queue\n", channel->channel);
8ceee660 321
ecc910f5
SH		 322 /* Build an event queue with room for one event per tx and rx buffer,
323 * plus some extra for link state events and MCDI completions. */
324 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
325 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
326 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
327
152b6a62 328 return efx_nic_probe_eventq(channel);
8ceee660
BH		 329}
330
331/* Prepare channel's event queue */
261e4d96 332static int efx_init_eventq(struct efx_channel *channel)
8ceee660 333{
261e4d96
JC		 334 int rc;
335
336 EFX_WARN_ON_PARANOID(channel->eventq_init);
337
62776d03
BH		 338 netif_dbg(channel->efx, drv, channel->efx->net_dev,
339 "chan %d init event queue\n", channel->channel);
8ceee660 340
261e4d96
JC		 341 rc = efx_nic_init_eventq(channel);
342 if (rc == 0) {
343 channel->eventq_read_ptr = 0;
344 channel->eventq_init = true;
345 }
346 return rc;
8ceee660
BH		 347}
348
9f2cb71c
BH		 349/* Enable event queue processing and NAPI */
350static void efx_start_eventq(struct efx_channel *channel)
351{
352 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
353 "chan %d start event queue\n", channel->channel);
354
514bedbc 355 /* Make sure the NAPI handler sees the enabled flag set */
9f2cb71c
BH		 356 channel->enabled = true;
357 smp_wmb();
358
359 napi_enable(&channel->napi_str);
360 efx_nic_eventq_read_ack(channel);
361}
362
363/* Disable event queue processing and NAPI */
364static void efx_stop_eventq(struct efx_channel *channel)
365{
366 if (!channel->enabled)
367 return;
368
369 napi_disable(&channel->napi_str);
370 channel->enabled = false;
371}
372
8ceee660
BH		 373static void efx_fini_eventq(struct efx_channel *channel)
374{
be3fc09c
BH		 375 if (!channel->eventq_init)
376 return;
377
62776d03
BH		 378 netif_dbg(channel->efx, drv, channel->efx->net_dev,
379 "chan %d fini event queue\n", channel->channel);
8ceee660 380
152b6a62 381 efx_nic_fini_eventq(channel);
be3fc09c 382 channel->eventq_init = false;
8ceee660
BH		 383}
384
385static void efx_remove_eventq(struct efx_channel *channel)
386{
62776d03
BH		 387 netif_dbg(channel->efx, drv, channel->efx->net_dev,
388 "chan %d remove event queue\n", channel->channel);
8ceee660 389
152b6a62 390 efx_nic_remove_eventq(channel);
8ceee660
BH		 391}
392
393/**************************************************************************
394 *
395 * Channel handling
396 *
397 *************************************************************************/
398
7f967c01 399/* Allocate and initialise a channel structure. */
4642610c
BH		 400static struct efx_channel *
401efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
402{
403 struct efx_channel *channel;
404 struct efx_rx_queue *rx_queue;
405 struct efx_tx_queue *tx_queue;
406 int j;
407
7f967c01
BH		 408 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
409 if (!channel)
410 return NULL;
4642610c 411
7f967c01
BH		 412 channel->efx = efx;
413 channel->channel = i;
414 channel->type = &efx_default_channel_type;
4642610c 415
7f967c01
BH		 416 for (j = 0; j < EFX_TXQ_TYPES; j++) {
417 tx_queue = &channel->tx_queue[j];
418 tx_queue->efx = efx;
419 tx_queue->queue = i * EFX_TXQ_TYPES + j;
420 tx_queue->channel = channel;
421 }
4642610c 422
7f967c01
BH		 423 rx_queue = &channel->rx_queue;
424 rx_queue->efx = efx;
425 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
426 (unsigned long)rx_queue);
4642610c 427
7f967c01
BH		 428 return channel;
429}
430
431/* Allocate and initialise a channel structure, copying parameters
432 * (but not resources) from an old channel structure.
433 */
434static struct efx_channel *
435efx_copy_channel(const struct efx_channel *old_channel)
436{
437 struct efx_channel *channel;
438 struct efx_rx_queue *rx_queue;
439 struct efx_tx_queue *tx_queue;
440 int j;
4642610c 441
7f967c01
BH		 442 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
443 if (!channel)
444 return NULL;
445
446 *channel = *old_channel;
447
448 channel->napi_dev = NULL;
449 memset(&channel->eventq, 0, sizeof(channel->eventq));
4642610c 450
7f967c01
BH		 451 for (j = 0; j < EFX_TXQ_TYPES; j++) {
452 tx_queue = &channel->tx_queue[j];
453 if (tx_queue->channel)
4642610c 454 tx_queue->channel = channel;
7f967c01
BH		 455 tx_queue->buffer = NULL;
456 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
4642610c
BH		 457 }
458
4642610c 459 rx_queue = &channel->rx_queue;
7f967c01
BH		 460 rx_queue->buffer = NULL;
461 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
4642610c
BH		 462 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
463 (unsigned long)rx_queue);
464
465 return channel;
466}
467
8ceee660
BH		 468static int efx_probe_channel(struct efx_channel *channel)
469{
470 struct efx_tx_queue *tx_queue;
471 struct efx_rx_queue *rx_queue;
472 int rc;
473
62776d03
BH		 474 netif_dbg(channel->efx, probe, channel->efx->net_dev,
475 "creating channel %d\n", channel->channel);
8ceee660 476
7f967c01
BH		 477 rc = channel->type->pre_probe(channel);
478 if (rc)
479 goto fail;
480
8ceee660
BH		 481 rc = efx_probe_eventq(channel);
482 if (rc)
7f967c01 483 goto fail;
8ceee660
BH		 484
485 efx_for_each_channel_tx_queue(tx_queue, channel) {
486 rc = efx_probe_tx_queue(tx_queue);
487 if (rc)
7f967c01 488 goto fail;
8ceee660
BH		 489 }
490
491 efx_for_each_channel_rx_queue(rx_queue, channel) {
492 rc = efx_probe_rx_queue(rx_queue);
493 if (rc)
7f967c01 494 goto fail;
8ceee660
BH		 495 }
496
497 channel->n_rx_frm_trunc = 0;
498
499 return 0;
500
7f967c01
BH		 501fail:
502 efx_remove_channel(channel);
8ceee660
BH		 503 return rc;
504}
505
7f967c01
BH		 506static void
507efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
508{
509 struct efx_nic *efx = channel->efx;
510 const char *type;
511 int number;
512
513 number = channel->channel;
514 if (efx->tx_channel_offset == 0) {
515 type = "";
516 } else if (channel->channel < efx->tx_channel_offset) {
517 type = "-rx";
518 } else {
519 type = "-tx";
520 number -= efx->tx_channel_offset;
521 }
522 snprintf(buf, len, "%s%s-%d", efx->name, type, number);
523}
8ceee660 524
56536e9c
BH		 525static void efx_set_channel_names(struct efx_nic *efx)
526{
527 struct efx_channel *channel;
56536e9c 528
7f967c01
BH		 529 efx_for_each_channel(channel, efx)
530 channel->type->get_name(channel,
d8291187
BH		 531 efx->msi_context[channel->channel].name,
532 sizeof(efx->msi_context[0].name));
56536e9c
BH		 533}
534
4642610c
BH		 535static int efx_probe_channels(struct efx_nic *efx)
536{
537 struct efx_channel *channel;
538 int rc;
539
540 /* Restart special buffer allocation */
541 efx->next_buffer_table = 0;
542
c92aaff1
BH		 543 /* Probe channels in reverse, so that any 'extra' channels
544 * use the start of the buffer table. This allows the traffic
545 * channels to be resized without moving them or wasting the
546 * entries before them.
547 */
548 efx_for_each_channel_rev(channel, efx) {
4642610c
BH		 549 rc = efx_probe_channel(channel);
550 if (rc) {
551 netif_err(efx, probe, efx->net_dev,
552 "failed to create channel %d\n",
553 channel->channel);
554 goto fail;
555 }
556 }
557 efx_set_channel_names(efx);
558
559 return 0;
560
561fail:
562 efx_remove_channels(efx);
563 return rc;
564}
565
8ceee660
BH		 566/* Channels are shutdown and reinitialised whilst the NIC is running
567 * to propagate configuration changes (mtu, checksum offload), or
568 * to clear hardware error conditions
569 */
9f2cb71c 570static void efx_start_datapath(struct efx_nic *efx)
8ceee660 571{
85740cdf 572 bool old_rx_scatter = efx->rx_scatter;
8ceee660
BH		 573 struct efx_tx_queue *tx_queue;
574 struct efx_rx_queue *rx_queue;
575 struct efx_channel *channel;
85740cdf 576 size_t rx_buf_len;
8ceee660 577
f7f13b0b
BH		 578 /* Calculate the rx buffer allocation parameters required to
579 * support the current MTU, including padding for header
580 * alignment and overruns.
581 */
43a3739d 582 efx->rx_dma_len = (efx->rx_prefix_size +
272baeeb
BH		 583 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
584 efx->type->rx_buffer_padding);
85740cdf 585 rx_buf_len = (sizeof(struct efx_rx_page_state) +
c14ff2ea 586 NET_IP_ALIGN + efx->rx_dma_len);
85740cdf
BH		 587 if (rx_buf_len <= PAGE_SIZE) {
588 efx->rx_scatter = false;
589 efx->rx_buffer_order = 0;
85740cdf 590 } else if (efx->type->can_rx_scatter) {
950c54df 591 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
85740cdf 592 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
950c54df
BH		 593 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
594 EFX_RX_BUF_ALIGNMENT) >
595 PAGE_SIZE);
85740cdf
BH		 596 efx->rx_scatter = true;
597 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
598 efx->rx_buffer_order = 0;
85740cdf
BH		 599 } else {
600 efx->rx_scatter = false;
601 efx->rx_buffer_order = get_order(rx_buf_len);
85740cdf
BH		 602 }
603
1648a23f
DP		 604 efx_rx_config_page_split(efx);
605 if (efx->rx_buffer_order)
606 netif_dbg(efx, drv, efx->net_dev,
607 "RX buf len=%u; page order=%u batch=%u\n",
608 efx->rx_dma_len, efx->rx_buffer_order,
609 efx->rx_pages_per_batch);
610 else
611 netif_dbg(efx, drv, efx->net_dev,
612 "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
613 efx->rx_dma_len, efx->rx_page_buf_step,
614 efx->rx_bufs_per_page, efx->rx_pages_per_batch);
2768935a 615
85740cdf
BH		 616 /* RX filters also have scatter-enabled flags */
617 if (efx->rx_scatter != old_rx_scatter)
add72477 618 efx->type->filter_update_rx_scatter(efx);
8ceee660 619
14bf718f
BH		 620 /* We must keep at least one descriptor in a TX ring empty.
621 * We could avoid this when the queue size does not exactly
622 * match the hardware ring size, but it's not that important.
623 * Therefore we stop the queue when one more skb might fill
624 * the ring completely. We wake it when half way back to
625 * empty.
626 */
627 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
628 efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
629
8ceee660
BH		 630 /* Initialise the channels */
631 efx_for_each_channel(channel, efx) {
bc3c90a2
BH		 632 efx_for_each_channel_tx_queue(tx_queue, channel)
633 efx_init_tx_queue(tx_queue);
8ceee660 634
9f2cb71c 635 efx_for_each_channel_rx_queue(rx_queue, channel) {
bc3c90a2 636 efx_init_rx_queue(rx_queue);
9f2cb71c
BH		 637 efx_nic_generate_fill_event(rx_queue);
638 }
8ceee660 639
85740cdf 640 WARN_ON(channel->rx_pkt_n_frags);
8ceee660 641 }
8ceee660 642
9f2cb71c
BH		 643 if (netif_device_present(efx->net_dev))
644 netif_tx_wake_all_queues(efx->net_dev);
8ceee660
BH		 645}
646
9f2cb71c 647static void efx_stop_datapath(struct efx_nic *efx)
8ceee660
BH		 648{
649 struct efx_channel *channel;
650 struct efx_tx_queue *tx_queue;
651 struct efx_rx_queue *rx_queue;
6bc5d3a9 652 int rc;
8ceee660
BH		 653
654 EFX_ASSERT_RESET_SERIALISED(efx);
655 BUG_ON(efx->port_enabled);
656
d8aec745
BH		 657 /* Stop RX refill */
658 efx_for_each_channel(channel, efx) {
659 efx_for_each_channel_rx_queue(rx_queue, channel)
660 rx_queue->refill_enabled = false;
661 }
662
8ceee660 663 efx_for_each_channel(channel, efx) {
9f2cb71c
BH		 664 /* RX packet processing is pipelined, so wait for the
665 * NAPI handler to complete. At least event queue 0
666 * might be kept active by non-data events, so don't
667 * use napi_synchronize() but actually disable NAPI
668 * temporarily.
669 */
670 if (efx_channel_has_rx_queue(channel)) {
671 efx_stop_eventq(channel);
672 efx_start_eventq(channel);
673 }
e42c3d85 674 }
8ceee660 675
e42c3d85
BH		 676 rc = efx->type->fini_dmaq(efx);
677 if (rc && EFX_WORKAROUND_7803(efx)) {
678 /* Schedule a reset to recover from the flush failure. The
679 * descriptor caches reference memory we're about to free,
680 * but falcon_reconfigure_mac_wrapper() won't reconnect
681 * the MACs because of the pending reset.
682 */
683 netif_err(efx, drv, efx->net_dev,
684 "Resetting to recover from flush failure\n");
685 efx_schedule_reset(efx, RESET_TYPE_ALL);
686 } else if (rc) {
687 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
688 } else {
689 netif_dbg(efx, drv, efx->net_dev,
690 "successfully flushed all queues\n");
691 }
692
693 efx_for_each_channel(channel, efx) {
8ceee660
BH		 694 efx_for_each_channel_rx_queue(rx_queue, channel)
695 efx_fini_rx_queue(rx_queue);
94b274bf 696 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660 697 efx_fini_tx_queue(tx_queue);
8ceee660
BH		 698 }
699}
700
701static void efx_remove_channel(struct efx_channel *channel)
702{
703 struct efx_tx_queue *tx_queue;
704 struct efx_rx_queue *rx_queue;
705
62776d03
BH		 706 netif_dbg(channel->efx, drv, channel->efx->net_dev,
707 "destroy chan %d\n", channel->channel);
8ceee660
BH		 708
709 efx_for_each_channel_rx_queue(rx_queue, channel)
710 efx_remove_rx_queue(rx_queue);
94b274bf 711 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660
BH		 712 efx_remove_tx_queue(tx_queue);
713 efx_remove_eventq(channel);
c31e5f9f 714 channel->type->post_remove(channel);
8ceee660
BH		 715}
716
4642610c
BH		 717static void efx_remove_channels(struct efx_nic *efx)
718{
719 struct efx_channel *channel;
720
721 efx_for_each_channel(channel, efx)
722 efx_remove_channel(channel);
723}
724
725int
726efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
727{
728 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
729 u32 old_rxq_entries, old_txq_entries;
7f967c01 730 unsigned i, next_buffer_table = 0;
261e4d96 731 int rc, rc2;
8b7325b4
BH		 732
733 rc = efx_check_disabled(efx);
734 if (rc)
735 return rc;
7f967c01
BH		 736
737 /* Not all channels should be reallocated. We must avoid
738 * reallocating their buffer table entries.
739 */
740 efx_for_each_channel(channel, efx) {
741 struct efx_rx_queue *rx_queue;
742 struct efx_tx_queue *tx_queue;
743
744 if (channel->type->copy)
745 continue;
746 next_buffer_table = max(next_buffer_table,
747 channel->eventq.index +
748 channel->eventq.entries);
749 efx_for_each_channel_rx_queue(rx_queue, channel)
750 next_buffer_table = max(next_buffer_table,
751 rx_queue->rxd.index +
752 rx_queue->rxd.entries);
753 efx_for_each_channel_tx_queue(tx_queue, channel)
754 next_buffer_table = max(next_buffer_table,
755 tx_queue->txd.index +
756 tx_queue->txd.entries);
757 }
4642610c 758
29c69a48 759 efx_device_detach_sync(efx);
4642610c 760 efx_stop_all(efx);
d8291187 761 efx_soft_disable_interrupts(efx);
4642610c 762
7f967c01 763 /* Clone channels (where possible) */
4642610c
BH		 764 memset(other_channel, 0, sizeof(other_channel));
765 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 766 channel = efx->channel[i];
767 if (channel->type->copy)
768 channel = channel->type->copy(channel);
4642610c
BH		 769 if (!channel) {
770 rc = -ENOMEM;
771 goto out;
772 }
773 other_channel[i] = channel;
774 }
775
776 /* Swap entry counts and channel pointers */
777 old_rxq_entries = efx->rxq_entries;
778 old_txq_entries = efx->txq_entries;
779 efx->rxq_entries = rxq_entries;
780 efx->txq_entries = txq_entries;
781 for (i = 0; i < efx->n_channels; i++) {
782 channel = efx->channel[i];
783 efx->channel[i] = other_channel[i];
784 other_channel[i] = channel;
785 }
786
7f967c01
BH		 787 /* Restart buffer table allocation */
788 efx->next_buffer_table = next_buffer_table;
e8f14992 789
e8f14992 790 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 791 channel = efx->channel[i];
792 if (!channel->type->copy)
793 continue;
794 rc = efx_probe_channel(channel);
795 if (rc)
796 goto rollback;
797 efx_init_napi_channel(efx->channel[i]);
e8f14992 798 }
7f967c01 799
4642610c 800out:
7f967c01
BH		 801 /* Destroy unused channel structures */
802 for (i = 0; i < efx->n_channels; i++) {
803 channel = other_channel[i];
804 if (channel && channel->type->copy) {
805 efx_fini_napi_channel(channel);
806 efx_remove_channel(channel);
807 kfree(channel);
808 }
809 }
4642610c 810
261e4d96
JC		 811 rc2 = efx_soft_enable_interrupts(efx);
812 if (rc2) {
813 rc = rc ? rc : rc2;
814 netif_err(efx, drv, efx->net_dev,
815 "unable to restart interrupts on channel reallocation\n");
816 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
817 } else {
818 efx_start_all(efx);
819 netif_device_attach(efx->net_dev);
820 }
4642610c
BH		 821 return rc;
822
823rollback:
824 /* Swap back */
825 efx->rxq_entries = old_rxq_entries;
826 efx->txq_entries = old_txq_entries;
827 for (i = 0; i < efx->n_channels; i++) {
828 channel = efx->channel[i];
829 efx->channel[i] = other_channel[i];
830 other_channel[i] = channel;
831 }
832 goto out;
833}
834
90d683af 835void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
8ceee660 836{
90d683af 837 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
8ceee660
BH		 838}
839
7f967c01
BH		 840static const struct efx_channel_type efx_default_channel_type = {
841 .pre_probe = efx_channel_dummy_op_int,
c31e5f9f 842 .post_remove = efx_channel_dummy_op_void,
7f967c01
BH		 843 .get_name = efx_get_channel_name,
844 .copy = efx_copy_channel,
845 .keep_eventq = false,
846};
847
848int efx_channel_dummy_op_int(struct efx_channel *channel)
849{
850 return 0;
851}
852
c31e5f9f
SH		 853void efx_channel_dummy_op_void(struct efx_channel *channel)
854{
855}
856
8ceee660
BH		 857/**************************************************************************
858 *
859 * Port handling
860 *
861 **************************************************************************/
862
863/* This ensures that the kernel is kept informed (via
864 * netif_carrier_on/off) of the link status, and also maintains the
865 * link status's stop on the port's TX queue.
866 */
fdaa9aed 867void efx_link_status_changed(struct efx_nic *efx)
8ceee660 868{
eb50c0d6
BH		 869 struct efx_link_state *link_state = &efx->link_state;
870
8ceee660
BH		 871 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
872 * that no events are triggered between unregister_netdev() and the
873 * driver unloading. A more general condition is that NETDEV_CHANGE
874 * can only be generated between NETDEV_UP and NETDEV_DOWN */
875 if (!netif_running(efx->net_dev))
876 return;
877
eb50c0d6 878 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
8ceee660
BH		 879 efx->n_link_state_changes++;
880
eb50c0d6 881 if (link_state->up)
8ceee660
BH		 882 netif_carrier_on(efx->net_dev);
883 else
884 netif_carrier_off(efx->net_dev);
885 }
886
887 /* Status message for kernel log */
2aa9ef11 888 if (link_state->up)
62776d03 889 netif_info(efx, link, efx->net_dev,
964e6135 890 "link up at %uMbps %s-duplex (MTU %d)\n",
62776d03 891 link_state->speed, link_state->fd ? "full" : "half",
964e6135 892 efx->net_dev->mtu);
2aa9ef11 893 else
62776d03 894 netif_info(efx, link, efx->net_dev, "link down\n");
8ceee660
BH		 895}
896
d3245b28
BH		 897void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
898{
899 efx->link_advertising = advertising;
900 if (advertising) {
901 if (advertising & ADVERTISED_Pause)
902 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
903 else
904 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
905 if (advertising & ADVERTISED_Asym_Pause)
906 efx->wanted_fc ^= EFX_FC_TX;
907 }
908}
909
b5626946 910void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
d3245b28
BH		 911{
912 efx->wanted_fc = wanted_fc;
913 if (efx->link_advertising) {
914 if (wanted_fc & EFX_FC_RX)
915 efx->link_advertising |= (ADVERTISED_Pause |
916 ADVERTISED_Asym_Pause);
917 else
918 efx->link_advertising &= ~(ADVERTISED_Pause |
919 ADVERTISED_Asym_Pause);
920 if (wanted_fc & EFX_FC_TX)
921 efx->link_advertising ^= ADVERTISED_Asym_Pause;
922 }
923}
924
115122af
BH		 925static void efx_fini_port(struct efx_nic *efx);
926
d3245b28
BH		 927/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
928 * the MAC appropriately. All other PHY configuration changes are pushed
929 * through phy_op->set_settings(), and pushed asynchronously to the MAC
930 * through efx_monitor().
931 *
932 * Callers must hold the mac_lock
933 */
934int __efx_reconfigure_port(struct efx_nic *efx)
8ceee660 935{
d3245b28
BH		 936 enum efx_phy_mode phy_mode;
937 int rc;
8ceee660 938
d3245b28 939 WARN_ON(!mutex_is_locked(&efx->mac_lock));
8ceee660 940
d3245b28
BH		 941 /* Disable PHY transmit in mac level loopbacks */
942 phy_mode = efx->phy_mode;
177dfcd8
BH		 943 if (LOOPBACK_INTERNAL(efx))
944 efx->phy_mode |= PHY_MODE_TX_DISABLED;
945 else
946 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
177dfcd8 947
d3245b28 948 rc = efx->type->reconfigure_port(efx);
8ceee660 949
d3245b28
BH		 950 if (rc)
951 efx->phy_mode = phy_mode;
177dfcd8 952
d3245b28 953 return rc;
8ceee660
BH		 954}
955
956/* Reinitialise the MAC to pick up new PHY settings, even if the port is
957 * disabled. */
d3245b28 958int efx_reconfigure_port(struct efx_nic *efx)
8ceee660 959{
d3245b28
BH		 960 int rc;
961
8ceee660
BH		 962 EFX_ASSERT_RESET_SERIALISED(efx);
963
964 mutex_lock(&efx->mac_lock);
d3245b28 965 rc = __efx_reconfigure_port(efx);
8ceee660 966 mutex_unlock(&efx->mac_lock);
d3245b28
BH		 967
968 return rc;
8ceee660
BH		 969}
970
8be4f3e6
BH		 971/* Asynchronous work item for changing MAC promiscuity and multicast
972 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
973 * MAC directly. */
766ca0fa
BH		 974static void efx_mac_work(struct work_struct *data)
975{
976 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
977
978 mutex_lock(&efx->mac_lock);
30b81cda 979 if (efx->port_enabled)
710b208d 980 efx->type->reconfigure_mac(efx);
766ca0fa
BH		 981 mutex_unlock(&efx->mac_lock);
982}
983
8ceee660
BH		 984static int efx_probe_port(struct efx_nic *efx)
985{
986 int rc;
987
62776d03 988 netif_dbg(efx, probe, efx->net_dev, "create port\n");
8ceee660 989
ff3b00a0
SH		 990 if (phy_flash_cfg)
991 efx->phy_mode = PHY_MODE_SPECIAL;
992
ef2b90ee
BH		 993 /* Connect up MAC/PHY operations table */
994 rc = efx->type->probe_port(efx);
8ceee660 995 if (rc)
e42de262 996 return rc;
8ceee660 997
e332bcb3
BH		 998 /* Initialise MAC address to permanent address */
999 memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN);
8ceee660
BH		 1000
1001 return 0;
8ceee660
BH		 1002}
1003
1004static int efx_init_port(struct efx_nic *efx)
1005{
1006 int rc;
1007
62776d03 1008 netif_dbg(efx, drv, efx->net_dev, "init port\n");
8ceee660 1009
1dfc5cea
BH		 1010 mutex_lock(&efx->mac_lock);
1011
177dfcd8 1012 rc = efx->phy_op->init(efx);
8ceee660 1013 if (rc)
1dfc5cea 1014 goto fail1;
8ceee660 1015
dc8cfa55 1016 efx->port_initialized = true;
1dfc5cea 1017
d3245b28
BH		 1018 /* Reconfigure the MAC before creating dma queues (required for
1019 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
710b208d 1020 efx->type->reconfigure_mac(efx);
d3245b28
BH		 1021
1022 /* Ensure the PHY advertises the correct flow control settings */
1023 rc = efx->phy_op->reconfigure(efx);
1024 if (rc)
1025 goto fail2;
1026
1dfc5cea 1027 mutex_unlock(&efx->mac_lock);
8ceee660 1028 return 0;
177dfcd8 1029
1dfc5cea 1030fail2:
177dfcd8 1031 efx->phy_op->fini(efx);
1dfc5cea
BH		 1032fail1:
1033 mutex_unlock(&efx->mac_lock);
177dfcd8 1034 return rc;
8ceee660
BH		 1035}
1036
8ceee660
BH		 1037static void efx_start_port(struct efx_nic *efx)
1038{
62776d03 1039 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
8ceee660
BH		 1040 BUG_ON(efx->port_enabled);
1041
1042 mutex_lock(&efx->mac_lock);
dc8cfa55 1043 efx->port_enabled = true;
8be4f3e6
BH		 1044
1045 /* efx_mac_work() might have been scheduled after efx_stop_port(),
1046 * and then cancelled by efx_flush_all() */
710b208d 1047 efx->type->reconfigure_mac(efx);
8be4f3e6 1048
8ceee660
BH		 1049 mutex_unlock(&efx->mac_lock);
1050}
1051
fdaa9aed 1052/* Prevent efx_mac_work() and efx_monitor() from working */
8ceee660
BH		 1053static void efx_stop_port(struct efx_nic *efx)
1054{
62776d03 1055 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
8ceee660
BH		 1056
1057 mutex_lock(&efx->mac_lock);
dc8cfa55 1058 efx->port_enabled = false;
8ceee660
BH		 1059 mutex_unlock(&efx->mac_lock);
1060
1061 /* Serialise against efx_set_multicast_list() */
73ba7b68
BH		 1062 netif_addr_lock_bh(efx->net_dev);
1063 netif_addr_unlock_bh(efx->net_dev);
8ceee660
BH		 1064}
1065
1066static void efx_fini_port(struct efx_nic *efx)
1067{
62776d03 1068 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
8ceee660
BH		 1069
1070 if (!efx->port_initialized)
1071 return;
1072
177dfcd8 1073 efx->phy_op->fini(efx);
dc8cfa55 1074 efx->port_initialized = false;
8ceee660 1075
eb50c0d6 1076 efx->link_state.up = false;
8ceee660
BH		 1077 efx_link_status_changed(efx);
1078}
1079
1080static void efx_remove_port(struct efx_nic *efx)
1081{
62776d03 1082 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
8ceee660 1083
ef2b90ee 1084 efx->type->remove_port(efx);
8ceee660
BH		 1085}
1086
1087/**************************************************************************
1088 *
1089 * NIC handling
1090 *
1091 **************************************************************************/
1092
1093/* This configures the PCI device to enable I/O and DMA. */
1094static int efx_init_io(struct efx_nic *efx)
1095{
1096 struct pci_dev *pci_dev = efx->pci_dev;
1097 dma_addr_t dma_mask = efx->type->max_dma_mask;
b105798f 1098 unsigned int mem_map_size = efx->type->mem_map_size(efx);
8ceee660
BH		 1099 int rc;
1100
62776d03 1101 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
8ceee660
BH		 1102
1103 rc = pci_enable_device(pci_dev);
1104 if (rc) {
62776d03
BH		 1105 netif_err(efx, probe, efx->net_dev,
1106 "failed to enable PCI device\n");
8ceee660
BH		 1107 goto fail1;
1108 }
1109
1110 pci_set_master(pci_dev);
1111
1112 /* Set the PCI DMA mask. Try all possibilities from our
1113 * genuine mask down to 32 bits, because some architectures
1114 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1115 * masks event though they reject 46 bit masks.
1116 */
1117 while (dma_mask > 0x7fffffffUL) {
0e33d870
BH		 1118 if (dma_supported(&pci_dev->dev, dma_mask)) {
1119 rc = dma_set_mask(&pci_dev->dev, dma_mask);
e9e01846
BH		 1120 if (rc == 0)
1121 break;
1122 }
8ceee660
BH		 1123 dma_mask >>= 1;
1124 }
1125 if (rc) {
62776d03
BH		 1126 netif_err(efx, probe, efx->net_dev,
1127 "could not find a suitable DMA mask\n");
8ceee660
BH		 1128 goto fail2;
1129 }
62776d03
BH		 1130 netif_dbg(efx, probe, efx->net_dev,
1131 "using DMA mask %llx\n", (unsigned long long) dma_mask);
0e33d870 1132 rc = dma_set_coherent_mask(&pci_dev->dev, dma_mask);
8ceee660 1133 if (rc) {
0e33d870
BH		 1134 /* dma_set_coherent_mask() is not *allowed* to
1135 * fail with a mask that dma_set_mask() accepted,
8ceee660
BH		 1136 * but just in case...
1137 */
62776d03
BH		 1138 netif_err(efx, probe, efx->net_dev,
1139 "failed to set consistent DMA mask\n");
8ceee660
BH		 1140 goto fail2;
1141 }
1142
dc803df8
BH		 1143 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
1144 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
8ceee660 1145 if (rc) {
62776d03
BH		 1146 netif_err(efx, probe, efx->net_dev,
1147 "request for memory BAR failed\n");
8ceee660
BH		 1148 rc = -EIO;
1149 goto fail3;
1150 }
b105798f 1151 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size);
8ceee660 1152 if (!efx->membase) {
62776d03
BH		 1153 netif_err(efx, probe, efx->net_dev,
1154 "could not map memory BAR at %llx+%x\n",
b105798f 1155 (unsigned long long)efx->membase_phys, mem_map_size);
8ceee660
BH		 1156 rc = -ENOMEM;
1157 goto fail4;
1158 }
62776d03
BH		 1159 netif_dbg(efx, probe, efx->net_dev,
1160 "memory BAR at %llx+%x (virtual %p)\n",
b105798f
BH		 1161 (unsigned long long)efx->membase_phys, mem_map_size,
1162 efx->membase);
8ceee660
BH		 1163
1164 return 0;
1165
1166 fail4:
dc803df8 1167 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
8ceee660 1168 fail3:
2c118e0f 1169 efx->membase_phys = 0;
8ceee660
BH		 1170 fail2:
1171 pci_disable_device(efx->pci_dev);
1172 fail1:
1173 return rc;
1174}
1175
1176static void efx_fini_io(struct efx_nic *efx)
1177{
62776d03 1178 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
8ceee660
BH		 1179
1180 if (efx->membase) {
1181 iounmap(efx->membase);
1182 efx->membase = NULL;
1183 }
1184
1185 if (efx->membase_phys) {
dc803df8 1186 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
2c118e0f 1187 efx->membase_phys = 0;
8ceee660
BH		 1188 }
1189
1190 pci_disable_device(efx->pci_dev);
1191}
1192
a9a52506 1193static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
46123d04 1194{
cdb08f8f 1195 cpumask_var_t thread_mask;
a16e5b24 1196 unsigned int count;
46123d04 1197 int cpu;
5b874e25 1198
cd2d5b52
BH		 1199 if (rss_cpus) {
1200 count = rss_cpus;
1201 } else {
1202 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
1203 netif_warn(efx, probe, efx->net_dev,
1204 "RSS disabled due to allocation failure\n");
1205 return 1;
1206 }
46123d04 1207
cd2d5b52
BH		 1208 count = 0;
1209 for_each_online_cpu(cpu) {
1210 if (!cpumask_test_cpu(cpu, thread_mask)) {
1211 ++count;
1212 cpumask_or(thread_mask, thread_mask,
1213 topology_thread_cpumask(cpu));
1214 }
1215 }
1216
1217 free_cpumask_var(thread_mask);
2f8975fb
RR		 1218 }
1219
cd2d5b52
BH		 1220 /* If RSS is requested for the PF *and* VFs then we can't write RSS
1221 * table entries that are inaccessible to VFs
1222 */
1223 if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
1224 count > efx_vf_size(efx)) {
1225 netif_warn(efx, probe, efx->net_dev,
1226 "Reducing number of RSS channels from %u to %u for "
1227 "VF support. Increase vf-msix-limit to use more "
1228 "channels on the PF.\n",
1229 count, efx_vf_size(efx));
1230 count = efx_vf_size(efx);
46123d04
BH		 1231 }
1232
1233 return count;
1234}
1235
1236/* Probe the number and type of interrupts we are able to obtain, and
1237 * the resulting numbers of channels and RX queues.
1238 */
64d8ad6d 1239static int efx_probe_interrupts(struct efx_nic *efx)
8ceee660 1240{
7f967c01
BH		 1241 unsigned int extra_channels = 0;
1242 unsigned int i, j;
a16e5b24 1243 int rc;
8ceee660 1244
7f967c01
BH		 1245 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
1246 if (efx->extra_channel_type[i])
1247 ++extra_channels;
1248
8ceee660 1249 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
46123d04 1250 struct msix_entry xentries[EFX_MAX_CHANNELS];
a16e5b24 1251 unsigned int n_channels;
aa6ef27e 1252
a9a52506 1253 n_channels = efx_wanted_parallelism(efx);
a4900ac9
BH		 1254 if (separate_tx_channels)
1255 n_channels *= 2;
7f967c01 1256 n_channels += extra_channels;
b105798f 1257 n_channels = min(n_channels, efx->max_channels);
8ceee660 1258
a4900ac9 1259 for (i = 0; i < n_channels; i++)
8ceee660 1260 xentries[i].entry = i;
a4900ac9 1261 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels);
8ceee660 1262 if (rc > 0) {
62776d03
BH		 1263 netif_err(efx, drv, efx->net_dev,
1264 "WARNING: Insufficient MSI-X vectors"
a16e5b24 1265 " available (%d < %u).\n", rc, n_channels);
62776d03
BH		 1266 netif_err(efx, drv, efx->net_dev,
1267 "WARNING: Performance may be reduced.\n");
a4900ac9
BH		 1268 EFX_BUG_ON_PARANOID(rc >= n_channels);
1269 n_channels = rc;
8ceee660 1270 rc = pci_enable_msix(efx->pci_dev, xentries,
a4900ac9 1271 n_channels);
8ceee660
BH		 1272 }
1273
1274 if (rc == 0) {
a4900ac9 1275 efx->n_channels = n_channels;
7f967c01
BH		 1276 if (n_channels > extra_channels)
1277 n_channels -= extra_channels;
a4900ac9 1278 if (separate_tx_channels) {
7f967c01
BH		 1279 efx->n_tx_channels = max(n_channels / 2, 1U);
1280 efx->n_rx_channels = max(n_channels -
1281 efx->n_tx_channels,
1282 1U);
a4900ac9 1283 } else {
7f967c01
BH		 1284 efx->n_tx_channels = n_channels;
1285 efx->n_rx_channels = n_channels;
a4900ac9 1286 }
7f967c01 1287 for (i = 0; i < efx->n_channels; i++)
f7d12cdc
BH		 1288 efx_get_channel(efx, i)->irq =
1289 xentries[i].vector;
8ceee660
BH		 1290 } else {
1291 /* Fall back to single channel MSI */
1292 efx->interrupt_mode = EFX_INT_MODE_MSI;
62776d03
BH		 1293 netif_err(efx, drv, efx->net_dev,
1294 "could not enable MSI-X\n");
8ceee660
BH		 1295 }
1296 }
1297
1298 /* Try single interrupt MSI */
1299 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
28b581ab 1300 efx->n_channels = 1;
a4900ac9
BH		 1301 efx->n_rx_channels = 1;
1302 efx->n_tx_channels = 1;
8ceee660
BH		 1303 rc = pci_enable_msi(efx->pci_dev);
1304 if (rc == 0) {
f7d12cdc 1305 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
8ceee660 1306 } else {
62776d03
BH		 1307 netif_err(efx, drv, efx->net_dev,
1308 "could not enable MSI\n");
8ceee660
BH		 1309 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1310 }
1311 }
1312
1313 /* Assume legacy interrupts */
1314 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
28b581ab 1315 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
a4900ac9
BH		 1316 efx->n_rx_channels = 1;
1317 efx->n_tx_channels = 1;
8ceee660
BH		 1318 efx->legacy_irq = efx->pci_dev->irq;
1319 }
64d8ad6d 1320
7f967c01
BH		 1321 /* Assign extra channels if possible */
1322 j = efx->n_channels;
1323 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
1324 if (!efx->extra_channel_type[i])
1325 continue;
1326 if (efx->interrupt_mode != EFX_INT_MODE_MSIX ||
1327 efx->n_channels <= extra_channels) {
1328 efx->extra_channel_type[i]->handle_no_channel(efx);
1329 } else {
1330 --j;
1331 efx_get_channel(efx, j)->type =
1332 efx->extra_channel_type[i];
1333 }
1334 }
1335
cd2d5b52 1336 /* RSS might be usable on VFs even if it is disabled on the PF */
3132d282 1337 efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ?
cd2d5b52
BH		 1338 efx->n_rx_channels : efx_vf_size(efx));
1339
64d8ad6d 1340 return 0;
8ceee660
BH		 1341}
1342
261e4d96 1343static int efx_soft_enable_interrupts(struct efx_nic *efx)
9f2cb71c 1344{
261e4d96
JC		 1345 struct efx_channel *channel, *end_channel;
1346 int rc;
9f2cb71c 1347
8b7325b4
BH		 1348 BUG_ON(efx->state == STATE_DISABLED);
1349
d8291187
BH		 1350 efx->irq_soft_enabled = true;
1351 smp_wmb();
9f2cb71c
BH		 1352
1353 efx_for_each_channel(channel, efx) {
261e4d96
JC		 1354 if (!channel->type->keep_eventq) {
1355 rc = efx_init_eventq(channel);
1356 if (rc)
1357 goto fail;
1358 }
9f2cb71c
BH		 1359 efx_start_eventq(channel);
1360 }
1361
1362 efx_mcdi_mode_event(efx);
261e4d96
JC		 1363
1364 return 0;
1365fail:
1366 end_channel = channel;
1367 efx_for_each_channel(channel, efx) {
1368 if (channel == end_channel)
1369 break;
1370 efx_stop_eventq(channel);
1371 if (!channel->type->keep_eventq)
1372 efx_fini_eventq(channel);
1373 }
1374
1375 return rc;
9f2cb71c
BH		 1376}
1377
d8291187 1378static void efx_soft_disable_interrupts(struct efx_nic *efx)
9f2cb71c
BH		 1379{
1380 struct efx_channel *channel;
1381
8b7325b4
BH		 1382 if (efx->state == STATE_DISABLED)
1383 return;
1384
9f2cb71c
BH		 1385 efx_mcdi_mode_poll(efx);
1386
d8291187
BH		 1387 efx->irq_soft_enabled = false;
1388 smp_wmb();
1389
1390 if (efx->legacy_irq)
9f2cb71c 1391 synchronize_irq(efx->legacy_irq);
9f2cb71c
BH		 1392
1393 efx_for_each_channel(channel, efx) {
1394 if (channel->irq)
1395 synchronize_irq(channel->irq);
1396
1397 efx_stop_eventq(channel);
d8291187 1398 if (!channel->type->keep_eventq)
7f967c01 1399 efx_fini_eventq(channel);
9f2cb71c 1400 }
cade715f
BH		 1401
1402 /* Flush the asynchronous MCDI request queue */
1403 efx_mcdi_flush_async(efx);
9f2cb71c
BH		 1404}
1405
261e4d96 1406static int efx_enable_interrupts(struct efx_nic *efx)
d8291187 1407{
261e4d96
JC		 1408 struct efx_channel *channel, *end_channel;
1409 int rc;
d8291187
BH		 1410
1411 BUG_ON(efx->state == STATE_DISABLED);
1412
1413 if (efx->eeh_disabled_legacy_irq) {
1414 enable_irq(efx->legacy_irq);
1415 efx->eeh_disabled_legacy_irq = false;
1416 }
1417
86094f7f 1418 efx->type->irq_enable_master(efx);
d8291187
BH		 1419
1420 efx_for_each_channel(channel, efx) {
261e4d96
JC		 1421 if (channel->type->keep_eventq) {
1422 rc = efx_init_eventq(channel);
1423 if (rc)
1424 goto fail;
1425 }
1426 }
1427
1428 rc = efx_soft_enable_interrupts(efx);
1429 if (rc)
1430 goto fail;
1431
1432 return 0;
1433
1434fail:
1435 end_channel = channel;
1436 efx_for_each_channel(channel, efx) {
1437 if (channel == end_channel)
1438 break;
d8291187 1439 if (channel->type->keep_eventq)
261e4d96 1440 efx_fini_eventq(channel);
d8291187
BH		 1441 }
1442
261e4d96
JC		 1443 efx->type->irq_disable_non_ev(efx);
1444
1445 return rc;
d8291187
BH		 1446}
1447
1448static void efx_disable_interrupts(struct efx_nic *efx)
1449{
1450 struct efx_channel *channel;
1451
1452 efx_soft_disable_interrupts(efx);
1453
1454 efx_for_each_channel(channel, efx) {
1455 if (channel->type->keep_eventq)
1456 efx_fini_eventq(channel);
1457 }
1458
86094f7f 1459 efx->type->irq_disable_non_ev(efx);
d8291187
BH		 1460}
1461
8ceee660
BH		 1462static void efx_remove_interrupts(struct efx_nic *efx)
1463{
1464 struct efx_channel *channel;
1465
1466 /* Remove MSI/MSI-X interrupts */
64ee3120 1467 efx_for_each_channel(channel, efx)
8ceee660
BH		 1468 channel->irq = 0;
1469 pci_disable_msi(efx->pci_dev);
1470 pci_disable_msix(efx->pci_dev);
1471
1472 /* Remove legacy interrupt */
1473 efx->legacy_irq = 0;
1474}
1475
8831da7b 1476static void efx_set_channels(struct efx_nic *efx)
8ceee660 1477{
602a5322
BH		 1478 struct efx_channel *channel;
1479 struct efx_tx_queue *tx_queue;
1480
97653431 1481 efx->tx_channel_offset =
a4900ac9 1482 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0;
602a5322 1483
79d68b37
SH		 1484 /* We need to mark which channels really have RX and TX
1485 * queues, and adjust the TX queue numbers if we have separate
602a5322
BH		 1486 * RX-only and TX-only channels.
1487 */
1488 efx_for_each_channel(channel, efx) {
79d68b37
SH		 1489 if (channel->channel < efx->n_rx_channels)
1490 channel->rx_queue.core_index = channel->channel;
1491 else
1492 channel->rx_queue.core_index = -1;
1493
602a5322
BH		 1494 efx_for_each_channel_tx_queue(tx_queue, channel)
1495 tx_queue->queue -= (efx->tx_channel_offset *
1496 EFX_TXQ_TYPES);
1497 }
8ceee660
BH		 1498}
1499
1500static int efx_probe_nic(struct efx_nic *efx)
1501{
765c9f46 1502 size_t i;
8ceee660
BH		 1503 int rc;
1504
62776d03 1505 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
8ceee660
BH		 1506
1507 /* Carry out hardware-type specific initialisation */
ef2b90ee 1508 rc = efx->type->probe(efx);
8ceee660
BH		 1509 if (rc)
1510 return rc;
1511
a4900ac9 1512 /* Determine the number of channels and queues by trying to hook
8ceee660 1513 * in MSI-X interrupts. */
64d8ad6d
BH		 1514 rc = efx_probe_interrupts(efx);
1515 if (rc)
1516 goto fail;
8ceee660 1517
28e47c49
BH		 1518 efx->type->dimension_resources(efx);
1519
5d3a6fca
BH		 1520 if (efx->n_channels > 1)
1521 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
765c9f46 1522 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
278bc429 1523 efx->rx_indir_table[i] =
cd2d5b52 1524 ethtool_rxfh_indir_default(i, efx->rss_spread);
5d3a6fca 1525
8831da7b 1526 efx_set_channels(efx);
c4f4adc7
BH		 1527 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1528 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
8ceee660
BH		 1529
1530 /* Initialise the interrupt moderation settings */
9e393b30
BH		 1531 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
1532 true);
8ceee660
BH		 1533
1534 return 0;
64d8ad6d
BH		 1535
1536fail:
1537 efx->type->remove(efx);
1538 return rc;
8ceee660
BH		 1539}
1540
1541static void efx_remove_nic(struct efx_nic *efx)
1542{
62776d03 1543 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
8ceee660
BH		 1544
1545 efx_remove_interrupts(efx);
ef2b90ee 1546 efx->type->remove(efx);
8ceee660
BH		 1547}
1548
add72477
BH		 1549static int efx_probe_filters(struct efx_nic *efx)
1550{
1551 int rc;
1552
1553 spin_lock_init(&efx->filter_lock);
1554
1555 rc = efx->type->filter_table_probe(efx);
1556 if (rc)
1557 return rc;
1558
1559#ifdef CONFIG_RFS_ACCEL
1560 if (efx->type->offload_features & NETIF_F_NTUPLE) {
1561 efx->rps_flow_id = kcalloc(efx->type->max_rx_ip_filters,
1562 sizeof(*efx->rps_flow_id),
1563 GFP_KERNEL);
1564 if (!efx->rps_flow_id) {
1565 efx->type->filter_table_remove(efx);
1566 return -ENOMEM;
1567 }
1568 }
1569#endif
1570
1571 return 0;
1572}
1573
1574static void efx_remove_filters(struct efx_nic *efx)
1575{
1576#ifdef CONFIG_RFS_ACCEL
1577 kfree(efx->rps_flow_id);
1578#endif
1579 efx->type->filter_table_remove(efx);
1580}
1581
1582static void efx_restore_filters(struct efx_nic *efx)
1583{
1584 efx->type->filter_table_restore(efx);
1585}
1586
8ceee660
BH		 1587/**************************************************************************
1588 *
1589 * NIC startup/shutdown
1590 *
1591 *************************************************************************/
1592
1593static int efx_probe_all(struct efx_nic *efx)
1594{
8ceee660
BH		 1595 int rc;
1596
8ceee660
BH		 1597 rc = efx_probe_nic(efx);
1598 if (rc) {
62776d03 1599 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
8ceee660
BH		 1600 goto fail1;
1601 }
1602
8ceee660
BH		 1603 rc = efx_probe_port(efx);
1604 if (rc) {
62776d03 1605 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
8ceee660
BH		 1606 goto fail2;
1607 }
1608
7e6d06f0
BH		 1609 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
1610 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
1611 rc = -EINVAL;
1612 goto fail3;
1613 }
ecc910f5 1614 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
8ceee660 1615
64eebcfd
BH		 1616 rc = efx_probe_filters(efx);
1617 if (rc) {
1618 netif_err(efx, probe, efx->net_dev,
1619 "failed to create filter tables\n");
7f967c01 1620 goto fail3;
64eebcfd
BH		 1621 }
1622
7f967c01
BH		 1623 rc = efx_probe_channels(efx);
1624 if (rc)
1625 goto fail4;
1626
8ceee660
BH		 1627 return 0;
1628
64eebcfd 1629 fail4:
7f967c01 1630 efx_remove_filters(efx);
8ceee660 1631 fail3:
8ceee660
BH		 1632 efx_remove_port(efx);
1633 fail2:
1634 efx_remove_nic(efx);
1635 fail1:
1636 return rc;
1637}
1638
8b7325b4
BH		 1639/* If the interface is supposed to be running but is not, start
1640 * the hardware and software data path, regular activity for the port
1641 * (MAC statistics, link polling, etc.) and schedule the port to be
1642 * reconfigured. Interrupts must already be enabled. This function
1643 * is safe to call multiple times, so long as the NIC is not disabled.
1644 * Requires the RTNL lock.
9f2cb71c 1645 */
8ceee660
BH		 1646static void efx_start_all(struct efx_nic *efx)
1647{
8ceee660 1648 EFX_ASSERT_RESET_SERIALISED(efx);
8b7325b4 1649 BUG_ON(efx->state == STATE_DISABLED);
8ceee660
BH		 1650
1651 /* Check that it is appropriate to restart the interface. All
1652 * of these flags are safe to read under just the rtnl lock */
8b7325b4 1653 if (efx->port_enabled || !netif_running(efx->net_dev))
8ceee660
BH		 1654 return;
1655
8ceee660 1656 efx_start_port(efx);
9f2cb71c 1657 efx_start_datapath(efx);
8880f4ec 1658
626950db
AR		 1659 /* Start the hardware monitor if there is one */
1660 if (efx->type->monitor != NULL)
8ceee660
BH		 1661 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1662 efx_monitor_interval);
626950db
AR		 1663
1664 /* If link state detection is normally event-driven, we have
1665 * to poll now because we could have missed a change
1666 */
1667 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
78c1f0a0
SH		 1668 mutex_lock(&efx->mac_lock);
1669 if (efx->phy_op->poll(efx))
1670 efx_link_status_changed(efx);
1671 mutex_unlock(&efx->mac_lock);
1672 }
55edc6e6 1673
ef2b90ee 1674 efx->type->start_stats(efx);
8ceee660
BH		 1675}
1676
1677/* Flush all delayed work. Should only be called when no more delayed work
1678 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1679 * since we're holding the rtnl_lock at this point. */
1680static void efx_flush_all(struct efx_nic *efx)
1681{
dd40781e 1682 /* Make sure the hardware monitor and event self-test are stopped */
8ceee660 1683 cancel_delayed_work_sync(&efx->monitor_work);
dd40781e 1684 efx_selftest_async_cancel(efx);
8ceee660 1685 /* Stop scheduled port reconfigurations */
766ca0fa 1686 cancel_work_sync(&efx->mac_work);
8ceee660
BH		 1687}
1688
8b7325b4
BH		 1689/* Quiesce the hardware and software data path, and regular activity
1690 * for the port without bringing the link down. Safe to call multiple
1691 * times with the NIC in almost any state, but interrupts should be
1692 * enabled. Requires the RTNL lock.
1693 */
8ceee660
BH		 1694static void efx_stop_all(struct efx_nic *efx)
1695{
8ceee660
BH		 1696 EFX_ASSERT_RESET_SERIALISED(efx);
1697
1698 /* port_enabled can be read safely under the rtnl lock */
1699 if (!efx->port_enabled)
1700 return;
1701
ef2b90ee 1702 efx->type->stop_stats(efx);
8ceee660
BH		 1703 efx_stop_port(efx);
1704
fdaa9aed 1705 /* Flush efx_mac_work(), refill_workqueue, monitor_work */
8ceee660
BH		 1706 efx_flush_all(efx);
1707
29c69a48
BH		 1708 /* Stop the kernel transmit interface. This is only valid if
1709 * the device is stopped or detached; otherwise the watchdog
1710 * may fire immediately.
1711 */
1712 WARN_ON(netif_running(efx->net_dev) &&
1713 netif_device_present(efx->net_dev));
9f2cb71c
BH		 1714 netif_tx_disable(efx->net_dev);
1715
1716 efx_stop_datapath(efx);
8ceee660
BH		 1717}
1718
1719static void efx_remove_all(struct efx_nic *efx)
1720{
4642610c 1721 efx_remove_channels(efx);
7f967c01 1722 efx_remove_filters(efx);
8ceee660
BH		 1723 efx_remove_port(efx);
1724 efx_remove_nic(efx);
1725}
1726
8ceee660
BH		 1727/**************************************************************************
1728 *
1729 * Interrupt moderation
1730 *
1731 **************************************************************************/
1732
cc180b69 1733static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns)
0d86ebd8 1734{
b548f976
BH		 1735 if (usecs == 0)
1736 return 0;
cc180b69 1737 if (usecs * 1000 < quantum_ns)
0d86ebd8 1738 return 1; /* never round down to 0 */
cc180b69 1739 return usecs * 1000 / quantum_ns;
0d86ebd8
BH		 1740}
1741
8ceee660 1742/* Set interrupt moderation parameters */
9e393b30
BH		 1743int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
1744 unsigned int rx_usecs, bool rx_adaptive,
1745 bool rx_may_override_tx)
8ceee660 1746{
f7d12cdc 1747 struct efx_channel *channel;
cc180b69
BH		 1748 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max *
1749 efx->timer_quantum_ns,
1750 1000);
1751 unsigned int tx_ticks;
1752 unsigned int rx_ticks;
8ceee660
BH		 1753
1754 EFX_ASSERT_RESET_SERIALISED(efx);
1755
cc180b69 1756 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max)
9e393b30
BH		 1757 return -EINVAL;
1758
cc180b69
BH		 1759 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns);
1760 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns);
1761
9e393b30
BH		 1762 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 &&
1763 !rx_may_override_tx) {
1764 netif_err(efx, drv, efx->net_dev, "Channels are shared. "
1765 "RX and TX IRQ moderation must be equal\n");
1766 return -EINVAL;
1767 }
1768
6fb70fd1 1769 efx->irq_rx_adaptive = rx_adaptive;
0d86ebd8 1770 efx->irq_rx_moderation = rx_ticks;
f7d12cdc 1771 efx_for_each_channel(channel, efx) {
525da907 1772 if (efx_channel_has_rx_queue(channel))
f7d12cdc 1773 channel->irq_moderation = rx_ticks;
525da907 1774 else if (efx_channel_has_tx_queues(channel))
f7d12cdc
BH		 1775 channel->irq_moderation = tx_ticks;
1776 }
9e393b30
BH		 1777
1778 return 0;
8ceee660
BH		 1779}
1780
a0c4faf5
BH		 1781void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
1782 unsigned int *rx_usecs, bool *rx_adaptive)
1783{
cc180b69
BH		 1784 /* We must round up when converting ticks to microseconds
1785 * because we round down when converting the other way.
1786 */
1787
a0c4faf5 1788 *rx_adaptive = efx->irq_rx_adaptive;
cc180b69
BH		 1789 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation *
1790 efx->timer_quantum_ns,
1791 1000);
a0c4faf5
BH		 1792
1793 /* If channels are shared between RX and TX, so is IRQ
1794 * moderation. Otherwise, IRQ moderation is the same for all
1795 * TX channels and is not adaptive.
1796 */
1797 if (efx->tx_channel_offset == 0)
1798 *tx_usecs = *rx_usecs;
1799 else
cc180b69 1800 *tx_usecs = DIV_ROUND_UP(
a0c4faf5 1801 efx->channel[efx->tx_channel_offset]->irq_moderation *
cc180b69
BH		 1802 efx->timer_quantum_ns,
1803 1000);
a0c4faf5
BH		 1804}
1805
8ceee660
BH		 1806/**************************************************************************
1807 *
1808 * Hardware monitor
1809 *
1810 **************************************************************************/
1811
e254c274 1812/* Run periodically off the general workqueue */
8ceee660
BH		 1813static void efx_monitor(struct work_struct *data)
1814{
1815 struct efx_nic *efx = container_of(data, struct efx_nic,
1816 monitor_work.work);
8ceee660 1817
62776d03
BH		 1818 netif_vdbg(efx, timer, efx->net_dev,
1819 "hardware monitor executing on CPU %d\n",
1820 raw_smp_processor_id());
ef2b90ee 1821 BUG_ON(efx->type->monitor == NULL);
8ceee660 1822
8ceee660
BH		 1823 /* If the mac_lock is already held then it is likely a port
1824 * reconfiguration is already in place, which will likely do
e254c274
BH		 1825 * most of the work of monitor() anyway. */
1826 if (mutex_trylock(&efx->mac_lock)) {
1827 if (efx->port_enabled)
1828 efx->type->monitor(efx);
1829 mutex_unlock(&efx->mac_lock);
1830 }
8ceee660 1831
8ceee660
BH		 1832 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1833 efx_monitor_interval);
1834}
1835
1836/**************************************************************************
1837 *
1838 * ioctls
1839 *
1840 *************************************************************************/
1841
1842/* Net device ioctl
1843 * Context: process, rtnl_lock() held.
1844 */
1845static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1846{
767e468c 1847 struct efx_nic *efx = netdev_priv(net_dev);
68e7f45e 1848 struct mii_ioctl_data *data = if_mii(ifr);
8ceee660 1849
7c236c43
SH		 1850 if (cmd == SIOCSHWTSTAMP)
1851 return efx_ptp_ioctl(efx, ifr, cmd);
1852
68e7f45e
BH		 1853 /* Convert phy_id from older PRTAD/DEVAD format */
1854 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1855 (data->phy_id & 0xfc00) == 0x0400)
1856 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1857
1858 return mdio_mii_ioctl(&efx->mdio, data, cmd);
8ceee660
BH		 1859}
1860
1861/**************************************************************************
1862 *
1863 * NAPI interface
1864 *
1865 **************************************************************************/
1866
7f967c01
BH		 1867static void efx_init_napi_channel(struct efx_channel *channel)
1868{
1869 struct efx_nic *efx = channel->efx;
1870
1871 channel->napi_dev = efx->net_dev;
1872 netif_napi_add(channel->napi_dev, &channel->napi_str,
1873 efx_poll, napi_weight);
1874}
1875
e8f14992 1876static void efx_init_napi(struct efx_nic *efx)
8ceee660
BH		 1877{
1878 struct efx_channel *channel;
8ceee660 1879
7f967c01
BH		 1880 efx_for_each_channel(channel, efx)
1881 efx_init_napi_channel(channel);
e8f14992
BH		 1882}
1883
1884static void efx_fini_napi_channel(struct efx_channel *channel)
1885{
1886 if (channel->napi_dev)
1887 netif_napi_del(&channel->napi_str);
1888 channel->napi_dev = NULL;
8ceee660
BH		 1889}
1890
1891static void efx_fini_napi(struct efx_nic *efx)
1892{
1893 struct efx_channel *channel;
1894
e8f14992
BH		 1895 efx_for_each_channel(channel, efx)
1896 efx_fini_napi_channel(channel);
8ceee660
BH		 1897}
1898
1899/**************************************************************************
1900 *
1901 * Kernel netpoll interface
1902 *
1903 *************************************************************************/
1904
1905#ifdef CONFIG_NET_POLL_CONTROLLER
1906
1907/* Although in the common case interrupts will be disabled, this is not
1908 * guaranteed. However, all our work happens inside the NAPI callback,
1909 * so no locking is required.
1910 */
1911static void efx_netpoll(struct net_device *net_dev)
1912{
767e468c 1913 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1914 struct efx_channel *channel;
1915
64ee3120 1916 efx_for_each_channel(channel, efx)
8ceee660
BH		 1917 efx_schedule_channel(channel);
1918}
1919
1920#endif
1921
1922/**************************************************************************
1923 *
1924 * Kernel net device interface
1925 *
1926 *************************************************************************/
1927
1928/* Context: process, rtnl_lock() held. */
1929static int efx_net_open(struct net_device *net_dev)
1930{
767e468c 1931 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4
BH		 1932 int rc;
1933
62776d03
BH		 1934 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
1935 raw_smp_processor_id());
8ceee660 1936
8b7325b4
BH		 1937 rc = efx_check_disabled(efx);
1938 if (rc)
1939 return rc;
f8b87c17
BH		 1940 if (efx->phy_mode & PHY_MODE_SPECIAL)
1941 return -EBUSY;
8880f4ec
BH		 1942 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
1943 return -EIO;
f8b87c17 1944
78c1f0a0
SH		 1945 /* Notify the kernel of the link state polled during driver load,
1946 * before the monitor starts running */
1947 efx_link_status_changed(efx);
1948
8ceee660 1949 efx_start_all(efx);
dd40781e 1950 efx_selftest_async_start(efx);
8ceee660
BH		 1951 return 0;
1952}
1953
1954/* Context: process, rtnl_lock() held.
1955 * Note that the kernel will ignore our return code; this method
1956 * should really be a void.
1957 */
1958static int efx_net_stop(struct net_device *net_dev)
1959{
767e468c 1960 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1961
62776d03
BH		 1962 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
1963 raw_smp_processor_id());
8ceee660 1964
8b7325b4
BH		 1965 /* Stop the device and flush all the channels */
1966 efx_stop_all(efx);
8ceee660
BH		 1967
1968 return 0;
1969}
1970
5b9e207c 1971/* Context: process, dev_base_lock or RTNL held, non-blocking. */
2aa9ef11
BH		 1972static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev,
1973 struct rtnl_link_stats64 *stats)
8ceee660 1974{
767e468c 1975 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1976
55edc6e6 1977 spin_lock_bh(&efx->stats_lock);
cd0ecc9a 1978 efx->type->update_stats(efx, NULL, stats);
1cb34522
BH		 1979 spin_unlock_bh(&efx->stats_lock);
1980
8ceee660
BH		 1981 return stats;
1982}
1983
1984/* Context: netif_tx_lock held, BHs disabled. */
1985static void efx_watchdog(struct net_device *net_dev)
1986{
767e468c 1987 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1988
62776d03
BH		 1989 netif_err(efx, tx_err, efx->net_dev,
1990 "TX stuck with port_enabled=%d: resetting channels\n",
1991 efx->port_enabled);
8ceee660 1992
739bb23d 1993 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
8ceee660
BH		 1994}
1995
1996
1997/* Context: process, rtnl_lock() held. */
1998static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
1999{
767e468c 2000 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4 2001 int rc;
8ceee660 2002
8b7325b4
BH		 2003 rc = efx_check_disabled(efx);
2004 if (rc)
2005 return rc;
8ceee660
BH		 2006 if (new_mtu > EFX_MAX_MTU)
2007 return -EINVAL;
2008
62776d03 2009 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
8ceee660 2010
29c69a48
BH		 2011 efx_device_detach_sync(efx);
2012 efx_stop_all(efx);
2013
d3245b28 2014 mutex_lock(&efx->mac_lock);
8ceee660 2015 net_dev->mtu = new_mtu;
710b208d 2016 efx->type->reconfigure_mac(efx);
d3245b28
BH		 2017 mutex_unlock(&efx->mac_lock);
2018
8ceee660 2019 efx_start_all(efx);
29c69a48 2020 netif_device_attach(efx->net_dev);
6c8eef4a 2021 return 0;
8ceee660
BH		 2022}
2023
2024static int efx_set_mac_address(struct net_device *net_dev, void *data)
2025{
767e468c 2026 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 2027 struct sockaddr *addr = data;
2028 char *new_addr = addr->sa_data;
2029
8ceee660 2030 if (!is_valid_ether_addr(new_addr)) {
62776d03
BH		 2031 netif_err(efx, drv, efx->net_dev,
2032 "invalid ethernet MAC address requested: %pM\n",
2033 new_addr);
504f9b5a 2034 return -EADDRNOTAVAIL;
8ceee660
BH		 2035 }
2036
2037 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
cd2d5b52 2038 efx_sriov_mac_address_changed(efx);
8ceee660
BH		 2039
2040 /* Reconfigure the MAC */
d3245b28 2041 mutex_lock(&efx->mac_lock);
710b208d 2042 efx->type->reconfigure_mac(efx);
d3245b28 2043 mutex_unlock(&efx->mac_lock);
8ceee660
BH		 2044
2045 return 0;
2046}
2047
a816f75a 2048/* Context: netif_addr_lock held, BHs disabled. */
0fca8c97 2049static void efx_set_rx_mode(struct net_device *net_dev)
8ceee660 2050{
767e468c 2051 struct efx_nic *efx = netdev_priv(net_dev);
a816f75a 2052
8be4f3e6
BH		 2053 if (efx->port_enabled)
2054 queue_work(efx->workqueue, &efx->mac_work);
2055 /* Otherwise efx_start_port() will do this */
8ceee660
BH		 2056}
2057
c8f44aff 2058static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
abfe9039
BH		 2059{
2060 struct efx_nic *efx = netdev_priv(net_dev);
2061
2062 /* If disabling RX n-tuple filtering, clear existing filters */
2063 if (net_dev->features & ~data & NETIF_F_NTUPLE)
2064 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
2065
2066 return 0;
2067}
2068
c3ecb9f3
SH		 2069static const struct net_device_ops efx_netdev_ops = {
2070 .ndo_open = efx_net_open,
2071 .ndo_stop = efx_net_stop,
4472702e 2072 .ndo_get_stats64 = efx_net_stats,
c3ecb9f3
SH		 2073 .ndo_tx_timeout = efx_watchdog,
2074 .ndo_start_xmit = efx_hard_start_xmit,
2075 .ndo_validate_addr = eth_validate_addr,
2076 .ndo_do_ioctl = efx_ioctl,
2077 .ndo_change_mtu = efx_change_mtu,
2078 .ndo_set_mac_address = efx_set_mac_address,
0fca8c97 2079 .ndo_set_rx_mode = efx_set_rx_mode,
abfe9039 2080 .ndo_set_features = efx_set_features,
cd2d5b52
BH		 2081#ifdef CONFIG_SFC_SRIOV
2082 .ndo_set_vf_mac = efx_sriov_set_vf_mac,
2083 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
2084 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
2085 .ndo_get_vf_config = efx_sriov_get_vf_config,
2086#endif
c3ecb9f3
SH		 2087#ifdef CONFIG_NET_POLL_CONTROLLER
2088 .ndo_poll_controller = efx_netpoll,
2089#endif
94b274bf 2090 .ndo_setup_tc = efx_setup_tc,
64d8ad6d
BH		 2091#ifdef CONFIG_RFS_ACCEL
2092 .ndo_rx_flow_steer = efx_filter_rfs,
2093#endif
c3ecb9f3
SH		 2094};
2095
7dde596e
BH		 2096static void efx_update_name(struct efx_nic *efx)
2097{
2098 strcpy(efx->name, efx->net_dev->name);
2099 efx_mtd_rename(efx);
2100 efx_set_channel_names(efx);
2101}
2102
8ceee660
BH		 2103static int efx_netdev_event(struct notifier_block *this,
2104 unsigned long event, void *ptr)
2105{
351638e7 2106 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr);
8ceee660 2107
7dde596e
BH		 2108 if (net_dev->netdev_ops == &efx_netdev_ops &&
2109 event == NETDEV_CHANGENAME)
2110 efx_update_name(netdev_priv(net_dev));
8ceee660
BH		 2111
2112 return NOTIFY_DONE;
2113}
2114
2115static struct notifier_block efx_netdev_notifier = {
2116 .notifier_call = efx_netdev_event,
2117};
2118
06d5e193
BH		 2119static ssize_t
2120show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
2121{
2122 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2123 return sprintf(buf, "%d\n", efx->phy_type);
2124}
776fbcc9 2125static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL);
06d5e193 2126
8ceee660
BH		 2127static int efx_register_netdev(struct efx_nic *efx)
2128{
2129 struct net_device *net_dev = efx->net_dev;
c04bfc6b 2130 struct efx_channel *channel;
8ceee660
BH		 2131 int rc;
2132
2133 net_dev->watchdog_timeo = 5 * HZ;
2134 net_dev->irq = efx->pci_dev->irq;
c3ecb9f3 2135 net_dev->netdev_ops = &efx_netdev_ops;
8ceee660 2136 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
7e6d06f0 2137 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
8ceee660 2138
7dde596e 2139 rtnl_lock();
aed0628d 2140
7153f623
BH		 2141 /* Enable resets to be scheduled and check whether any were
2142 * already requested. If so, the NIC is probably hosed so we
2143 * abort.
2144 */
2145 efx->state = STATE_READY;
2146 smp_mb(); /* ensure we change state before checking reset_pending */
2147 if (efx->reset_pending) {
2148 netif_err(efx, probe, efx->net_dev,
2149 "aborting probe due to scheduled reset\n");
2150 rc = -EIO;
2151 goto fail_locked;
2152 }
2153
aed0628d
BH		 2154 rc = dev_alloc_name(net_dev, net_dev->name);
2155 if (rc < 0)
2156 goto fail_locked;
7dde596e 2157 efx_update_name(efx);
aed0628d 2158
8f8b3d51
BH		 2159 /* Always start with carrier off; PHY events will detect the link */
2160 netif_carrier_off(net_dev);
2161
aed0628d
BH		 2162 rc = register_netdevice(net_dev);
2163 if (rc)
2164 goto fail_locked;
2165
c04bfc6b
BH		 2166 efx_for_each_channel(channel, efx) {
2167 struct efx_tx_queue *tx_queue;
60031fcc
BH		 2168 efx_for_each_channel_tx_queue(tx_queue, channel)
2169 efx_init_tx_queue_core_txq(tx_queue);
c04bfc6b
BH		 2170 }
2171
7dde596e 2172 rtnl_unlock();
8ceee660 2173
06d5e193
BH		 2174 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2175 if (rc) {
62776d03
BH		 2176 netif_err(efx, drv, efx->net_dev,
2177 "failed to init net dev attributes\n");
06d5e193
BH		 2178 goto fail_registered;
2179 }
2180
8ceee660 2181 return 0;
06d5e193 2182
7153f623
BH		 2183fail_registered:
2184 rtnl_lock();
2185 unregister_netdevice(net_dev);
aed0628d 2186fail_locked:
7153f623 2187 efx->state = STATE_UNINIT;
aed0628d 2188 rtnl_unlock();
62776d03 2189 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
aed0628d 2190 return rc;
8ceee660
BH		 2191}
2192
2193static void efx_unregister_netdev(struct efx_nic *efx)
2194{
8ceee660
BH		 2195 if (!efx->net_dev)
2196 return;
2197
767e468c 2198 BUG_ON(netdev_priv(efx->net_dev) != efx);
8ceee660 2199
73ba7b68
BH		 2200 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2201 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
7153f623
BH		 2202
2203 rtnl_lock();
2204 unregister_netdevice(efx->net_dev);
2205 efx->state = STATE_UNINIT;
2206 rtnl_unlock();
8ceee660
BH		 2207}
2208
2209/**************************************************************************
2210 *
2211 * Device reset and suspend
2212 *
2213 **************************************************************************/
2214
2467ca46
BH		 2215/* Tears down the entire software state and most of the hardware state
2216 * before reset. */
d3245b28 2217void efx_reset_down(struct efx_nic *efx, enum reset_type method)
8ceee660 2218{
8ceee660
BH		 2219 EFX_ASSERT_RESET_SERIALISED(efx);
2220
2467ca46 2221 efx_stop_all(efx);
d8291187 2222 efx_disable_interrupts(efx);
5642ceef
BH		 2223
2224 mutex_lock(&efx->mac_lock);
4b988280
SH		 2225 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
2226 efx->phy_op->fini(efx);
ef2b90ee 2227 efx->type->fini(efx);
8ceee660
BH		 2228}
2229
2467ca46
BH		 2230/* This function will always ensure that the locks acquired in
2231 * efx_reset_down() are released. A failure return code indicates
2232 * that we were unable to reinitialise the hardware, and the
2233 * driver should be disabled. If ok is false, then the rx and tx
2234 * engines are not restarted, pending a RESET_DISABLE. */
d3245b28 2235int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
8ceee660
BH		 2236{
2237 int rc;
2238
2467ca46 2239 EFX_ASSERT_RESET_SERIALISED(efx);
8ceee660 2240
ef2b90ee 2241 rc = efx->type->init(efx);
8ceee660 2242 if (rc) {
62776d03 2243 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
eb9f6744 2244 goto fail;
8ceee660
BH		 2245 }
2246
eb9f6744
BH		 2247 if (!ok)
2248 goto fail;
2249
4b988280 2250 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
eb9f6744
BH		 2251 rc = efx->phy_op->init(efx);
2252 if (rc)
2253 goto fail;
2254 if (efx->phy_op->reconfigure(efx))
62776d03
BH		 2255 netif_err(efx, drv, efx->net_dev,
2256 "could not restore PHY settings\n");
4b988280
SH		 2257 }
2258
261e4d96
JC		 2259 rc = efx_enable_interrupts(efx);
2260 if (rc)
2261 goto fail;
64eebcfd 2262 efx_restore_filters(efx);
cd2d5b52 2263 efx_sriov_reset(efx);
eb9f6744 2264
eb9f6744
BH		 2265 mutex_unlock(&efx->mac_lock);
2266
2267 efx_start_all(efx);
2268
2269 return 0;
2270
2271fail:
2272 efx->port_initialized = false;
2467ca46
BH		 2273
2274 mutex_unlock(&efx->mac_lock);
2275
8ceee660
BH		 2276 return rc;
2277}
2278
eb9f6744
BH		 2279/* Reset the NIC using the specified method. Note that the reset may
2280 * fail, in which case the card will be left in an unusable state.
8ceee660 2281 *
eb9f6744 2282 * Caller must hold the rtnl_lock.
8ceee660 2283 */
eb9f6744 2284int efx_reset(struct efx_nic *efx, enum reset_type method)
8ceee660 2285{
eb9f6744
BH		 2286 int rc, rc2;
2287 bool disabled;
8ceee660 2288
62776d03
BH		 2289 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2290 RESET_TYPE(method));
8ceee660 2291
c2f3b8e3 2292 efx_device_detach_sync(efx);
d3245b28 2293 efx_reset_down(efx, method);
8ceee660 2294
ef2b90ee 2295 rc = efx->type->reset(efx, method);
8ceee660 2296 if (rc) {
62776d03 2297 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
eb9f6744 2298 goto out;
8ceee660
BH		 2299 }
2300
a7d529ae
BH		 2301 /* Clear flags for the scopes we covered. We assume the NIC and
2302 * driver are now quiescent so that there is no race here.
2303 */
2304 efx->reset_pending &= -(1 << (method + 1));
8ceee660
BH		 2305
2306 /* Reinitialise bus-mastering, which may have been turned off before
2307 * the reset was scheduled. This is still appropriate, even in the
2308 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2309 * can respond to requests. */
2310 pci_set_master(efx->pci_dev);
2311
eb9f6744 2312out:
8ceee660 2313 /* Leave device stopped if necessary */
626950db
AR		 2314 disabled = rc ||
2315 method == RESET_TYPE_DISABLE ||
2316 method == RESET_TYPE_RECOVER_OR_DISABLE;
eb9f6744
BH		 2317 rc2 = efx_reset_up(efx, method, !disabled);
2318 if (rc2) {
2319 disabled = true;
2320 if (!rc)
2321 rc = rc2;
8ceee660
BH		 2322 }
2323
eb9f6744 2324 if (disabled) {
f49a4589 2325 dev_close(efx->net_dev);
62776d03 2326 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
f4bd954e 2327 efx->state = STATE_DISABLED;
f4bd954e 2328 } else {
62776d03 2329 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
e4abce85 2330 netif_device_attach(efx->net_dev);
f4bd954e 2331 }
8ceee660
BH		 2332 return rc;
2333}
2334
626950db
AR		 2335/* Try recovery mechanisms.
2336 * For now only EEH is supported.
2337 * Returns 0 if the recovery mechanisms are unsuccessful.
2338 * Returns a non-zero value otherwise.
2339 */
b28405b0 2340int efx_try_recovery(struct efx_nic *efx)
626950db
AR		 2341{
2342#ifdef CONFIG_EEH
2343 /* A PCI error can occur and not be seen by EEH because nothing
2344 * happens on the PCI bus. In this case the driver may fail and
2345 * schedule a 'recover or reset', leading to this recovery handler.
2346 * Manually call the eeh failure check function.
2347 */
2348 struct eeh_dev *eehdev =
2349 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
2350
2351 if (eeh_dev_check_failure(eehdev)) {
2352 /* The EEH mechanisms will handle the error and reset the
2353 * device if necessary.
2354 */
2355 return 1;
2356 }
2357#endif
2358 return 0;
2359}
2360
8ceee660
BH		 2361/* The worker thread exists so that code that cannot sleep can
2362 * schedule a reset for later.
2363 */
2364static void efx_reset_work(struct work_struct *data)
2365{
eb9f6744 2366 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
626950db
AR		 2367 unsigned long pending;
2368 enum reset_type method;
2369
2370 pending = ACCESS_ONCE(efx->reset_pending);
2371 method = fls(pending) - 1;
2372
2373 if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
2374 method == RESET_TYPE_RECOVER_OR_ALL) &&
2375 efx_try_recovery(efx))
2376 return;
8ceee660 2377
a7d529ae 2378 if (!pending)
319ba649
SH		 2379 return;
2380
eb9f6744 2381 rtnl_lock();
7153f623
BH		 2382
2383 /* We checked the state in efx_schedule_reset() but it may
2384 * have changed by now. Now that we have the RTNL lock,
2385 * it cannot change again.
2386 */
2387 if (efx->state == STATE_READY)
626950db 2388 (void)efx_reset(efx, method);
7153f623 2389
eb9f6744 2390 rtnl_unlock();
8ceee660
BH		 2391}
2392
2393void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2394{
2395 enum reset_type method;
2396
626950db
AR		 2397 if (efx->state == STATE_RECOVERY) {
2398 netif_dbg(efx, drv, efx->net_dev,
2399 "recovering: skip scheduling %s reset\n",
2400 RESET_TYPE(type));
2401 return;
2402 }
2403
8ceee660
BH		 2404 switch (type) {
2405 case RESET_TYPE_INVISIBLE:
2406 case RESET_TYPE_ALL:
626950db 2407 case RESET_TYPE_RECOVER_OR_ALL:
8ceee660
BH		 2408 case RESET_TYPE_WORLD:
2409 case RESET_TYPE_DISABLE:
626950db 2410 case RESET_TYPE_RECOVER_OR_DISABLE:
8ceee660 2411 method = type;
0e2a9c7c
BH		 2412 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2413 RESET_TYPE(method));
8ceee660 2414 break;
8ceee660 2415 default:
0e2a9c7c 2416 method = efx->type->map_reset_reason(type);
62776d03
BH		 2417 netif_dbg(efx, drv, efx->net_dev,
2418 "scheduling %s reset for %s\n",
2419 RESET_TYPE(method), RESET_TYPE(type));
0e2a9c7c
BH		 2420 break;
2421 }
8ceee660 2422
a7d529ae 2423 set_bit(method, &efx->reset_pending);
7153f623
BH		 2424 smp_mb(); /* ensure we change reset_pending before checking state */
2425
2426 /* If we're not READY then just leave the flags set as the cue
2427 * to abort probing or reschedule the reset later.
2428 */
2429 if (ACCESS_ONCE(efx->state) != STATE_READY)
2430 return;
8ceee660 2431
8880f4ec
BH		 2432 /* efx_process_channel() will no longer read events once a
2433 * reset is scheduled. So switch back to poll'd MCDI completions. */
2434 efx_mcdi_mode_poll(efx);
2435
1ab00629 2436 queue_work(reset_workqueue, &efx->reset_work);
8ceee660
BH		 2437}
2438
2439/**************************************************************************
2440 *
2441 * List of NICs we support
2442 *
2443 **************************************************************************/
2444
2445/* PCI device ID table */
a3aa1884 2446static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
937383a5
BH		 2447 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2448 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0),
daeda630 2449 .driver_data = (unsigned long) &falcon_a1_nic_type},
937383a5
BH		 2450 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2451 PCI_DEVICE_ID_SOLARFLARE_SFC4000B),
daeda630 2452 .driver_data = (unsigned long) &falcon_b0_nic_type},
547c474f 2453 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
8880f4ec 2454 .driver_data = (unsigned long) &siena_a0_nic_type},
547c474f 2455 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
8880f4ec 2456 .driver_data = (unsigned long) &siena_a0_nic_type},
8ceee660
BH		 2457 {0} /* end of list */
2458};
2459
2460/**************************************************************************
2461 *
3759433d 2462 * Dummy PHY/MAC operations
8ceee660 2463 *
01aad7b6 2464 * Can be used for some unimplemented operations
8ceee660
BH		 2465 * Needed so all function pointers are valid and do not have to be tested
2466 * before use
2467 *
2468 **************************************************************************/
2469int efx_port_dummy_op_int(struct efx_nic *efx)
2470{
2471 return 0;
2472}
2473void efx_port_dummy_op_void(struct efx_nic *efx) {}
d215697f 2474
2475static bool efx_port_dummy_op_poll(struct efx_nic *efx)
fdaa9aed
SH		 2476{
2477 return false;
2478}
8ceee660 2479
6c8c2513 2480static const struct efx_phy_operations efx_dummy_phy_operations = {
8ceee660 2481 .init = efx_port_dummy_op_int,
d3245b28 2482 .reconfigure = efx_port_dummy_op_int,
fdaa9aed 2483 .poll = efx_port_dummy_op_poll,
8ceee660 2484 .fini = efx_port_dummy_op_void,
8ceee660
BH		 2485};
2486
8ceee660
BH		 2487/**************************************************************************
2488 *
2489 * Data housekeeping
2490 *
2491 **************************************************************************/
2492
2493/* This zeroes out and then fills in the invariants in a struct
2494 * efx_nic (including all sub-structures).
2495 */
adeb15aa 2496static int efx_init_struct(struct efx_nic *efx,
8ceee660
BH		 2497 struct pci_dev *pci_dev, struct net_device *net_dev)
2498{
4642610c 2499 int i;
8ceee660
BH		 2500
2501 /* Initialise common structures */
8ceee660 2502 spin_lock_init(&efx->biu_lock);
76884835
BH		 2503#ifdef CONFIG_SFC_MTD
2504 INIT_LIST_HEAD(&efx->mtd_list);
2505#endif
8ceee660
BH		 2506 INIT_WORK(&efx->reset_work, efx_reset_work);
2507 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
dd40781e 2508 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
8ceee660 2509 efx->pci_dev = pci_dev;
62776d03 2510 efx->msg_enable = debug;
f16aeea0 2511 efx->state = STATE_UNINIT;
8ceee660 2512 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
8ceee660
BH		 2513
2514 efx->net_dev = net_dev;
43a3739d
JC		 2515 efx->rx_prefix_size = efx->type->rx_prefix_size;
2516 efx->rx_packet_hash_offset =
2517 efx->type->rx_hash_offset - efx->type->rx_prefix_size;
8ceee660
BH		 2518 spin_lock_init(&efx->stats_lock);
2519 mutex_init(&efx->mac_lock);
2520 efx->phy_op = &efx_dummy_phy_operations;
68e7f45e 2521 efx->mdio.dev = net_dev;
766ca0fa 2522 INIT_WORK(&efx->mac_work, efx_mac_work);
9f2cb71c 2523 init_waitqueue_head(&efx->flush_wq);
8ceee660
BH		 2524
2525 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
4642610c
BH		 2526 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2527 if (!efx->channel[i])
2528 goto fail;
d8291187
BH		 2529 efx->msi_context[i].efx = efx;
2530 efx->msi_context[i].index = i;
8ceee660
BH		 2531 }
2532
8ceee660
BH		 2533 /* Higher numbered interrupt modes are less capable! */
2534 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2535 interrupt_mode);
2536
6977dc63
BH		 2537 /* Would be good to use the net_dev name, but we're too early */
2538 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2539 pci_name(pci_dev));
2540 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1ab00629 2541 if (!efx->workqueue)
4642610c 2542 goto fail;
8d9853d9 2543
8ceee660 2544 return 0;
4642610c
BH		 2545
2546fail:
2547 efx_fini_struct(efx);
2548 return -ENOMEM;
8ceee660
BH		 2549}
2550
2551static void efx_fini_struct(struct efx_nic *efx)
2552{
8313aca3
BH		 2553 int i;
2554
2555 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2556 kfree(efx->channel[i]);
2557
8ceee660
BH		 2558 if (efx->workqueue) {
2559 destroy_workqueue(efx->workqueue);
2560 efx->workqueue = NULL;
2561 }
2562}
2563
2564/**************************************************************************
2565 *
2566 * PCI interface
2567 *
2568 **************************************************************************/
2569
2570/* Main body of final NIC shutdown code
2571 * This is called only at module unload (or hotplug removal).
2572 */
2573static void efx_pci_remove_main(struct efx_nic *efx)
2574{
7153f623
BH		 2575 /* Flush reset_work. It can no longer be scheduled since we
2576 * are not READY.
2577 */
2578 BUG_ON(efx->state == STATE_READY);
2579 cancel_work_sync(&efx->reset_work);
2580
d8291187 2581 efx_disable_interrupts(efx);
152b6a62 2582 efx_nic_fini_interrupt(efx);
8ceee660 2583 efx_fini_port(efx);
ef2b90ee 2584 efx->type->fini(efx);
8ceee660
BH		 2585 efx_fini_napi(efx);
2586 efx_remove_all(efx);
2587}
2588
2589/* Final NIC shutdown
2590 * This is called only at module unload (or hotplug removal).
2591 */
2592static void efx_pci_remove(struct pci_dev *pci_dev)
2593{
2594 struct efx_nic *efx;
2595
2596 efx = pci_get_drvdata(pci_dev);
2597 if (!efx)
2598 return;
2599
2600 /* Mark the NIC as fini, then stop the interface */
2601 rtnl_lock();
8ceee660 2602 dev_close(efx->net_dev);
d8291187 2603 efx_disable_interrupts(efx);
8ceee660
BH		 2604 rtnl_unlock();
2605
cd2d5b52 2606 efx_sriov_fini(efx);
8ceee660
BH		 2607 efx_unregister_netdev(efx);
2608
7dde596e
BH		 2609 efx_mtd_remove(efx);
2610
8ceee660
BH		 2611 efx_pci_remove_main(efx);
2612
8ceee660 2613 efx_fini_io(efx);
62776d03 2614 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
8ceee660 2615
8ceee660 2616 efx_fini_struct(efx);
3de4e301 2617 pci_set_drvdata(pci_dev, NULL);
8ceee660 2618 free_netdev(efx->net_dev);
626950db
AR		 2619
2620 pci_disable_pcie_error_reporting(pci_dev);
8ceee660
BH		 2621};
2622
460eeaa0
BH		 2623/* NIC VPD information
2624 * Called during probe to display the part number of the
2625 * installed NIC. VPD is potentially very large but this should
2626 * always appear within the first 512 bytes.
2627 */
2628#define SFC_VPD_LEN 512
2629static void efx_print_product_vpd(struct efx_nic *efx)
2630{
2631 struct pci_dev *dev = efx->pci_dev;
2632 char vpd_data[SFC_VPD_LEN];
2633 ssize_t vpd_size;
2634 int i, j;
2635
2636 /* Get the vpd data from the device */
2637 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
2638 if (vpd_size <= 0) {
2639 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
2640 return;
2641 }
2642
2643 /* Get the Read only section */
2644 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
2645 if (i < 0) {
2646 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
2647 return;
2648 }
2649
2650 j = pci_vpd_lrdt_size(&vpd_data[i]);
2651 i += PCI_VPD_LRDT_TAG_SIZE;
2652 if (i + j > vpd_size)
2653 j = vpd_size - i;
2654
2655 /* Get the Part number */
2656 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
2657 if (i < 0) {
2658 netif_err(efx, drv, efx->net_dev, "Part number not found\n");
2659 return;
2660 }
2661
2662 j = pci_vpd_info_field_size(&vpd_data[i]);
2663 i += PCI_VPD_INFO_FLD_HDR_SIZE;
2664 if (i + j > vpd_size) {
2665 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
2666 return;
2667 }
2668
2669 netif_info(efx, drv, efx->net_dev,
2670 "Part Number : %.*s\n", j, &vpd_data[i]);
2671}
2672
2673
8ceee660
BH		 2674/* Main body of NIC initialisation
2675 * This is called at module load (or hotplug insertion, theoretically).
2676 */
2677static int efx_pci_probe_main(struct efx_nic *efx)
2678{
2679 int rc;
2680
2681 /* Do start-of-day initialisation */
2682 rc = efx_probe_all(efx);
2683 if (rc)
2684 goto fail1;
2685
e8f14992 2686 efx_init_napi(efx);
8ceee660 2687
ef2b90ee 2688 rc = efx->type->init(efx);
8ceee660 2689 if (rc) {
62776d03
BH		 2690 netif_err(efx, probe, efx->net_dev,
2691 "failed to initialise NIC\n");
278c0621 2692 goto fail3;
8ceee660
BH		 2693 }
2694
2695 rc = efx_init_port(efx);
2696 if (rc) {
62776d03
BH		 2697 netif_err(efx, probe, efx->net_dev,
2698 "failed to initialise port\n");
278c0621 2699 goto fail4;
8ceee660
BH		 2700 }
2701
152b6a62 2702 rc = efx_nic_init_interrupt(efx);
8ceee660 2703 if (rc)
278c0621 2704 goto fail5;
261e4d96
JC		 2705 rc = efx_enable_interrupts(efx);
2706 if (rc)
2707 goto fail6;
8ceee660
BH		 2708
2709 return 0;
2710
261e4d96
JC		 2711 fail6:
2712 efx_nic_fini_interrupt(efx);
278c0621 2713 fail5:
8ceee660 2714 efx_fini_port(efx);
8ceee660 2715 fail4:
ef2b90ee 2716 efx->type->fini(efx);
8ceee660
BH		 2717 fail3:
2718 efx_fini_napi(efx);
8ceee660
BH		 2719 efx_remove_all(efx);
2720 fail1:
2721 return rc;
2722}
2723
2724/* NIC initialisation
2725 *
2726 * This is called at module load (or hotplug insertion,
73ba7b68 2727 * theoretically). It sets up PCI mappings, resets the NIC,
8ceee660
BH		 2728 * sets up and registers the network devices with the kernel and hooks
2729 * the interrupt service routine. It does not prepare the device for
2730 * transmission; this is left to the first time one of the network
2731 * interfaces is brought up (i.e. efx_net_open).
2732 */
87d1fc11 2733static int efx_pci_probe(struct pci_dev *pci_dev,
1dd06ae8 2734 const struct pci_device_id *entry)
8ceee660 2735{
8ceee660
BH		 2736 struct net_device *net_dev;
2737 struct efx_nic *efx;
fadac6aa 2738 int rc;
8ceee660
BH		 2739
2740 /* Allocate and initialise a struct net_device and struct efx_nic */
94b274bf
BH		 2741 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
2742 EFX_MAX_RX_QUEUES);
8ceee660
BH		 2743 if (!net_dev)
2744 return -ENOMEM;
adeb15aa
BH		 2745 efx = netdev_priv(net_dev);
2746 efx->type = (const struct efx_nic_type *) entry->driver_data;
2747 net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
97bc5415 2748 NETIF_F_HIGHDMA | NETIF_F_TSO |
abfe9039 2749 NETIF_F_RXCSUM);
adeb15aa 2750 if (efx->type->offload_features & NETIF_F_V6_CSUM)
738a8f4b 2751 net_dev->features |= NETIF_F_TSO6;
28506563
BH		 2752 /* Mask for features that also apply to VLAN devices */
2753 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
abfe9039
BH		 2754 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
2755 NETIF_F_RXCSUM);
2756 /* All offloads can be toggled */
2757 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA;
8ceee660 2758 pci_set_drvdata(pci_dev, efx);
62776d03 2759 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
adeb15aa 2760 rc = efx_init_struct(efx, pci_dev, net_dev);
8ceee660
BH		 2761 if (rc)
2762 goto fail1;
2763
62776d03 2764 netif_info(efx, probe, efx->net_dev,
ff79c8ac 2765 "Solarflare NIC detected\n");
8ceee660 2766
460eeaa0
BH		 2767 efx_print_product_vpd(efx);
2768
8ceee660
BH		 2769 /* Set up basic I/O (BAR mappings etc) */
2770 rc = efx_init_io(efx);
2771 if (rc)
2772 goto fail2;
2773
fadac6aa 2774 rc = efx_pci_probe_main(efx);
fadac6aa
BH		 2775 if (rc)
2776 goto fail3;
8ceee660 2777
8ceee660
BH		 2778 rc = efx_register_netdev(efx);
2779 if (rc)
fadac6aa 2780 goto fail4;
8ceee660 2781
cd2d5b52
BH		 2782 rc = efx_sriov_init(efx);
2783 if (rc)
2784 netif_err(efx, probe, efx->net_dev,
2785 "SR-IOV can't be enabled rc %d\n", rc);
2786
62776d03 2787 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
a5211bb5 2788
7c43161c 2789 /* Try to create MTDs, but allow this to fail */
a5211bb5 2790 rtnl_lock();
7c43161c 2791 rc = efx_mtd_probe(efx);
a5211bb5 2792 rtnl_unlock();
7c43161c
BH		 2793 if (rc)
2794 netif_warn(efx, probe, efx->net_dev,
2795 "failed to create MTDs (%d)\n", rc);
2796
626950db
AR		 2797 rc = pci_enable_pcie_error_reporting(pci_dev);
2798 if (rc && rc != -EINVAL)
2799 netif_warn(efx, probe, efx->net_dev,
2800 "pci_enable_pcie_error_reporting failed (%d)\n", rc);
2801
8ceee660
BH		 2802 return 0;
2803
8ceee660 2804 fail4:
fadac6aa 2805 efx_pci_remove_main(efx);
8ceee660
BH		 2806 fail3:
2807 efx_fini_io(efx);
2808 fail2:
2809 efx_fini_struct(efx);
2810 fail1:
3de4e301 2811 pci_set_drvdata(pci_dev, NULL);
5e2a911c 2812 WARN_ON(rc > 0);
62776d03 2813 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
8ceee660
BH		 2814 free_netdev(net_dev);
2815 return rc;
2816}
2817
89c758fa
BH		 2818static int efx_pm_freeze(struct device *dev)
2819{
2820 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2821
61da026d
BH		 2822 rtnl_lock();
2823
6032fb56
BH		 2824 if (efx->state != STATE_DISABLED) {
2825 efx->state = STATE_UNINIT;
89c758fa 2826
c2f3b8e3 2827 efx_device_detach_sync(efx);
89c758fa 2828
6032fb56 2829 efx_stop_all(efx);
d8291187 2830 efx_disable_interrupts(efx);
6032fb56 2831 }
89c758fa 2832
61da026d
BH		 2833 rtnl_unlock();
2834
89c758fa
BH		 2835 return 0;
2836}
2837
2838static int efx_pm_thaw(struct device *dev)
2839{
261e4d96 2840 int rc;
89c758fa
BH		 2841 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2842
61da026d
BH		 2843 rtnl_lock();
2844
6032fb56 2845 if (efx->state != STATE_DISABLED) {
261e4d96
JC		 2846 rc = efx_enable_interrupts(efx);
2847 if (rc)
2848 goto fail;
89c758fa 2849
6032fb56
BH		 2850 mutex_lock(&efx->mac_lock);
2851 efx->phy_op->reconfigure(efx);
2852 mutex_unlock(&efx->mac_lock);
89c758fa 2853
6032fb56 2854 efx_start_all(efx);
89c758fa 2855
6032fb56 2856 netif_device_attach(efx->net_dev);
89c758fa 2857
6032fb56 2858 efx->state = STATE_READY;
89c758fa 2859
6032fb56
BH		 2860 efx->type->resume_wol(efx);
2861 }
89c758fa 2862
61da026d
BH		 2863 rtnl_unlock();
2864
319ba649
SH		 2865 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
2866 queue_work(reset_workqueue, &efx->reset_work);
2867
89c758fa 2868 return 0;
261e4d96
JC		 2869
2870fail:
2871 rtnl_unlock();
2872
2873 return rc;
89c758fa
BH		 2874}
2875
2876static int efx_pm_poweroff(struct device *dev)
2877{
2878 struct pci_dev *pci_dev = to_pci_dev(dev);
2879 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2880
2881 efx->type->fini(efx);
2882
a7d529ae 2883 efx->reset_pending = 0;
89c758fa
BH		 2884
2885 pci_save_state(pci_dev);
2886 return pci_set_power_state(pci_dev, PCI_D3hot);
2887}
2888
2889/* Used for both resume and restore */
2890static int efx_pm_resume(struct device *dev)
2891{
2892 struct pci_dev *pci_dev = to_pci_dev(dev);
2893 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2894 int rc;
2895
2896 rc = pci_set_power_state(pci_dev, PCI_D0);
2897 if (rc)
2898 return rc;
2899 pci_restore_state(pci_dev);
2900 rc = pci_enable_device(pci_dev);
2901 if (rc)
2902 return rc;
2903 pci_set_master(efx->pci_dev);
2904 rc = efx->type->reset(efx, RESET_TYPE_ALL);
2905 if (rc)
2906 return rc;
2907 rc = efx->type->init(efx);
2908 if (rc)
2909 return rc;
261e4d96
JC		 2910 rc = efx_pm_thaw(dev);
2911 return rc;
89c758fa
BH		 2912}
2913
2914static int efx_pm_suspend(struct device *dev)
2915{
2916 int rc;
2917
2918 efx_pm_freeze(dev);
2919 rc = efx_pm_poweroff(dev);
2920 if (rc)
2921 efx_pm_resume(dev);
2922 return rc;
2923}
2924
18e83e4c 2925static const struct dev_pm_ops efx_pm_ops = {
89c758fa
BH		 2926 .suspend = efx_pm_suspend,
2927 .resume = efx_pm_resume,
2928 .freeze = efx_pm_freeze,
2929 .thaw = efx_pm_thaw,
2930 .poweroff = efx_pm_poweroff,
2931 .restore = efx_pm_resume,
2932};
2933
626950db
AR		 2934/* A PCI error affecting this device was detected.
2935 * At this point MMIO and DMA may be disabled.
2936 * Stop the software path and request a slot reset.
2937 */
debd0034 2938static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
2939 enum pci_channel_state state)
626950db
AR		 2940{
2941 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
2942 struct efx_nic *efx = pci_get_drvdata(pdev);
2943
2944 if (state == pci_channel_io_perm_failure)
2945 return PCI_ERS_RESULT_DISCONNECT;
2946
2947 rtnl_lock();
2948
2949 if (efx->state != STATE_DISABLED) {
2950 efx->state = STATE_RECOVERY;
2951 efx->reset_pending = 0;
2952
2953 efx_device_detach_sync(efx);
2954
2955 efx_stop_all(efx);
d8291187 2956 efx_disable_interrupts(efx);
626950db
AR		 2957
2958 status = PCI_ERS_RESULT_NEED_RESET;
2959 } else {
2960 /* If the interface is disabled we don't want to do anything
2961 * with it.
2962 */
2963 status = PCI_ERS_RESULT_RECOVERED;
2964 }
2965
2966 rtnl_unlock();
2967
2968 pci_disable_device(pdev);
2969
2970 return status;
2971}
2972
2973/* Fake a successfull reset, which will be performed later in efx_io_resume. */
debd0034 2974static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
626950db
AR		 2975{
2976 struct efx_nic *efx = pci_get_drvdata(pdev);
2977 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
2978 int rc;
2979
2980 if (pci_enable_device(pdev)) {
2981 netif_err(efx, hw, efx->net_dev,
2982 "Cannot re-enable PCI device after reset.\n");
2983 status = PCI_ERS_RESULT_DISCONNECT;
2984 }
2985
2986 rc = pci_cleanup_aer_uncorrect_error_status(pdev);
2987 if (rc) {
2988 netif_err(efx, hw, efx->net_dev,
2989 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc);
2990 /* Non-fatal error. Continue. */
2991 }
2992
2993 return status;
2994}
2995
2996/* Perform the actual reset and resume I/O operations. */
2997static void efx_io_resume(struct pci_dev *pdev)
2998{
2999 struct efx_nic *efx = pci_get_drvdata(pdev);
3000 int rc;
3001
3002 rtnl_lock();
3003
3004 if (efx->state == STATE_DISABLED)
3005 goto out;
3006
3007 rc = efx_reset(efx, RESET_TYPE_ALL);
3008 if (rc) {
3009 netif_err(efx, hw, efx->net_dev,
3010 "efx_reset failed after PCI error (%d)\n", rc);
3011 } else {
3012 efx->state = STATE_READY;
3013 netif_dbg(efx, hw, efx->net_dev,
3014 "Done resetting and resuming IO after PCI error.\n");
3015 }
3016
3017out:
3018 rtnl_unlock();
3019}
3020
3021/* For simplicity and reliability, we always require a slot reset and try to
3022 * reset the hardware when a pci error affecting the device is detected.
3023 * We leave both the link_reset and mmio_enabled callback unimplemented:
3024 * with our request for slot reset the mmio_enabled callback will never be
3025 * called, and the link_reset callback is not used by AER or EEH mechanisms.
3026 */
3027static struct pci_error_handlers efx_err_handlers = {
3028 .error_detected = efx_io_error_detected,
3029 .slot_reset = efx_io_slot_reset,
3030 .resume = efx_io_resume,
3031};
3032
8ceee660 3033static struct pci_driver efx_pci_driver = {
c5d5f5fd 3034 .name = KBUILD_MODNAME,
8ceee660
BH		 3035 .id_table = efx_pci_table,
3036 .probe = efx_pci_probe,
3037 .remove = efx_pci_remove,
89c758fa 3038 .driver.pm = &efx_pm_ops,
626950db 3039 .err_handler = &efx_err_handlers,
8ceee660
BH		 3040};
3041
3042/**************************************************************************
3043 *
3044 * Kernel module interface
3045 *
3046 *************************************************************************/
3047
3048module_param(interrupt_mode, uint, 0444);
3049MODULE_PARM_DESC(interrupt_mode,
3050 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
3051
3052static int __init efx_init_module(void)
3053{
3054 int rc;
3055
3056 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
3057
3058 rc = register_netdevice_notifier(&efx_netdev_notifier);
3059 if (rc)
3060 goto err_notifier;
3061
cd2d5b52
BH		 3062 rc = efx_init_sriov();
3063 if (rc)
3064 goto err_sriov;
3065
1ab00629
SH		 3066 reset_workqueue = create_singlethread_workqueue("sfc_reset");
3067 if (!reset_workqueue) {
3068 rc = -ENOMEM;
3069 goto err_reset;
3070 }
8ceee660
BH		 3071
3072 rc = pci_register_driver(&efx_pci_driver);
3073 if (rc < 0)
3074 goto err_pci;
3075
3076 return 0;
3077
3078 err_pci:
1ab00629
SH		 3079 destroy_workqueue(reset_workqueue);
3080 err_reset:
cd2d5b52
BH		 3081 efx_fini_sriov();
3082 err_sriov:
8ceee660
BH		 3083 unregister_netdevice_notifier(&efx_netdev_notifier);
3084 err_notifier:
3085 return rc;
3086}
3087
3088static void __exit efx_exit_module(void)
3089{
3090 printk(KERN_INFO "Solarflare NET driver unloading\n");
3091
3092 pci_unregister_driver(&efx_pci_driver);
1ab00629 3093 destroy_workqueue(reset_workqueue);
cd2d5b52 3094 efx_fini_sriov();
8ceee660
BH		 3095 unregister_netdevice_notifier(&efx_netdev_notifier);
3096
3097}
3098
3099module_init(efx_init_module);
3100module_exit(efx_exit_module);
3101
906bb26c
BH		 3102MODULE_AUTHOR("Solarflare Communications and "
3103 "Michael Brown <mbrown@fensystems.co.uk>");
8ceee660
BH		 3104MODULE_DESCRIPTION("Solarflare Communications network driver");
3105MODULE_LICENSE("GPL");
3106MODULE_DEVICE_TABLE(pci, efx_pci_table);
Linux kernel - Deliverables
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