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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
64d8ad6d | 24 | #include <linux/cpu_rmap.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
dd40781e | 28 | #include "selftest.h" |
8ceee660 | 29 | |
8880f4ec | 30 | #include "mcdi.h" |
fd371e32 | 31 | #include "workarounds.h" |
8880f4ec | 32 | |
c459302d BH |
33 | /************************************************************************** |
34 | * | |
35 | * Type name strings | |
36 | * | |
37 | ************************************************************************** | |
38 | */ | |
39 | ||
40 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
41 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 42 | const char *const efx_loopback_mode_names[] = { |
c459302d | 43 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 44 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
45 | [LOOPBACK_GMAC] = "GMAC", |
46 | [LOOPBACK_XGMII] = "XGMII", | |
47 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
48 | [LOOPBACK_XAUI] = "XAUI", |
49 | [LOOPBACK_GMII] = "GMII", | |
50 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
51 | [LOOPBACK_XGBR] = "XGBR", |
52 | [LOOPBACK_XFI] = "XFI", | |
53 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
54 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
55 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
56 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
57 | [LOOPBACK_GPHY] = "GPHY", |
58 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
59 | [LOOPBACK_PCS] = "PCS", |
60 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
61 | [LOOPBACK_XPORT] = "XPORT", |
62 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 63 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
64 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
65 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 66 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
67 | [LOOPBACK_XFI_WS] = "XFI_WS", |
68 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 69 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
70 | }; |
71 | ||
c459302d | 72 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 73 | const char *const efx_reset_type_names[] = { |
c459302d BH |
74 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
75 | [RESET_TYPE_ALL] = "ALL", | |
76 | [RESET_TYPE_WORLD] = "WORLD", | |
77 | [RESET_TYPE_DISABLE] = "DISABLE", | |
78 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
79 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
80 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
81 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
82 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
83 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 84 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
85 | }; |
86 | ||
8ceee660 BH |
87 | #define EFX_MAX_MTU (9 * 1024) |
88 | ||
1ab00629 SH |
89 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
90 | * queued onto this work queue. This is not a per-nic work queue, because | |
91 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
92 | */ | |
93 | static struct workqueue_struct *reset_workqueue; | |
94 | ||
8ceee660 BH |
95 | /************************************************************************** |
96 | * | |
97 | * Configurable values | |
98 | * | |
99 | *************************************************************************/ | |
100 | ||
8ceee660 BH |
101 | /* |
102 | * Use separate channels for TX and RX events | |
103 | * | |
28b581ab NT |
104 | * Set this to 1 to use separate channels for TX and RX. It allows us |
105 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 106 | * |
28b581ab | 107 | * This is only used in MSI-X interrupt mode |
8ceee660 | 108 | */ |
b9cc977d BH |
109 | static bool separate_tx_channels; |
110 | module_param(separate_tx_channels, bool, 0444); | |
28b581ab NT |
111 | MODULE_PARM_DESC(separate_tx_channels, |
112 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
113 | |
114 | /* This is the weight assigned to each of the (per-channel) virtual | |
115 | * NAPI devices. | |
116 | */ | |
117 | static int napi_weight = 64; | |
118 | ||
119 | /* This is the time (in jiffies) between invocations of the hardware | |
e254c274 BH |
120 | * monitor. On Falcon-based NICs, this will: |
121 | * - Check the on-board hardware monitor; | |
122 | * - Poll the link state and reconfigure the hardware as necessary. | |
8ceee660 | 123 | */ |
d215697f | 124 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 125 | |
8ceee660 BH |
126 | /* Initial interrupt moderation settings. They can be modified after |
127 | * module load with ethtool. | |
128 | * | |
129 | * The default for RX should strike a balance between increasing the | |
130 | * round-trip latency and reducing overhead. | |
131 | */ | |
132 | static unsigned int rx_irq_mod_usec = 60; | |
133 | ||
134 | /* Initial interrupt moderation settings. They can be modified after | |
135 | * module load with ethtool. | |
136 | * | |
137 | * This default is chosen to ensure that a 10G link does not go idle | |
138 | * while a TX queue is stopped after it has become full. A queue is | |
139 | * restarted when it drops below half full. The time this takes (assuming | |
140 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
141 | * 512 / 3 * 1.2 = 205 usec. | |
142 | */ | |
143 | static unsigned int tx_irq_mod_usec = 150; | |
144 | ||
145 | /* This is the first interrupt mode to try out of: | |
146 | * 0 => MSI-X | |
147 | * 1 => MSI | |
148 | * 2 => legacy | |
149 | */ | |
150 | static unsigned int interrupt_mode; | |
151 | ||
152 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
153 | * i.e. the number of CPUs among which we may distribute simultaneous | |
154 | * interrupt handling. | |
155 | * | |
156 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 157 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
158 | */ |
159 | static unsigned int rss_cpus; | |
160 | module_param(rss_cpus, uint, 0444); | |
161 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
162 | ||
b9cc977d BH |
163 | static bool phy_flash_cfg; |
164 | module_param(phy_flash_cfg, bool, 0644); | |
84ae48fe BH |
165 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); |
166 | ||
e7bed9c8 | 167 | static unsigned irq_adapt_low_thresh = 8000; |
6fb70fd1 BH |
168 | module_param(irq_adapt_low_thresh, uint, 0644); |
169 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
170 | "Threshold score for reducing IRQ moderation"); | |
171 | ||
e7bed9c8 | 172 | static unsigned irq_adapt_high_thresh = 16000; |
6fb70fd1 BH |
173 | module_param(irq_adapt_high_thresh, uint, 0644); |
174 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
175 | "Threshold score for increasing IRQ moderation"); | |
176 | ||
62776d03 BH |
177 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
178 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
179 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
180 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
181 | module_param(debug, uint, 0); | |
182 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
183 | ||
8ceee660 BH |
184 | /************************************************************************** |
185 | * | |
186 | * Utility functions and prototypes | |
187 | * | |
188 | *************************************************************************/ | |
4642610c | 189 | |
7f967c01 BH |
190 | static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq); |
191 | static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq); | |
192 | static void efx_remove_channel(struct efx_channel *channel); | |
4642610c | 193 | static void efx_remove_channels(struct efx_nic *efx); |
7f967c01 | 194 | static const struct efx_channel_type efx_default_channel_type; |
8ceee660 | 195 | static void efx_remove_port(struct efx_nic *efx); |
7f967c01 | 196 | static void efx_init_napi_channel(struct efx_channel *channel); |
8ceee660 | 197 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 198 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
199 | static void efx_fini_struct(struct efx_nic *efx); |
200 | static void efx_start_all(struct efx_nic *efx); | |
201 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
202 | |
203 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
204 | do { \ | |
f16aeea0 | 205 | if ((efx->state == STATE_READY) || \ |
332c1ce9 | 206 | (efx->state == STATE_DISABLED)) \ |
8ceee660 BH |
207 | ASSERT_RTNL(); \ |
208 | } while (0) | |
209 | ||
8b7325b4 BH |
210 | static int efx_check_disabled(struct efx_nic *efx) |
211 | { | |
212 | if (efx->state == STATE_DISABLED) { | |
213 | netif_err(efx, drv, efx->net_dev, | |
214 | "device is disabled due to earlier errors\n"); | |
215 | return -EIO; | |
216 | } | |
217 | return 0; | |
218 | } | |
219 | ||
8ceee660 BH |
220 | /************************************************************************** |
221 | * | |
222 | * Event queue processing | |
223 | * | |
224 | *************************************************************************/ | |
225 | ||
226 | /* Process channel's event queue | |
227 | * | |
228 | * This function is responsible for processing the event queue of a | |
229 | * single channel. The caller must guarantee that this function will | |
230 | * never be concurrently called more than once on the same channel, | |
231 | * though different channels may be being processed concurrently. | |
232 | */ | |
fa236e18 | 233 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 234 | { |
fa236e18 | 235 | int spent; |
8ceee660 | 236 | |
9f2cb71c | 237 | if (unlikely(!channel->enabled)) |
42cbe2d7 | 238 | return 0; |
8ceee660 | 239 | |
fa236e18 | 240 | spent = efx_nic_process_eventq(channel, budget); |
d9ab7007 BH |
241 | if (spent && efx_channel_has_rx_queue(channel)) { |
242 | struct efx_rx_queue *rx_queue = | |
243 | efx_channel_get_rx_queue(channel); | |
244 | ||
245 | /* Deliver last RX packet. */ | |
246 | if (channel->rx_pkt) { | |
247 | __efx_rx_packet(channel, channel->rx_pkt); | |
248 | channel->rx_pkt = NULL; | |
249 | } | |
9f2cb71c BH |
250 | if (rx_queue->enabled) { |
251 | efx_rx_strategy(channel); | |
252 | efx_fast_push_rx_descriptors(rx_queue); | |
253 | } | |
8ceee660 BH |
254 | } |
255 | ||
fa236e18 | 256 | return spent; |
8ceee660 BH |
257 | } |
258 | ||
259 | /* Mark channel as finished processing | |
260 | * | |
261 | * Note that since we will not receive further interrupts for this | |
262 | * channel before we finish processing and call the eventq_read_ack() | |
263 | * method, there is no need to use the interrupt hold-off timers. | |
264 | */ | |
265 | static inline void efx_channel_processed(struct efx_channel *channel) | |
266 | { | |
5b9e207c BH |
267 | /* The interrupt handler for this channel may set work_pending |
268 | * as soon as we acknowledge the events we've seen. Make sure | |
269 | * it's cleared before then. */ | |
dc8cfa55 | 270 | channel->work_pending = false; |
5b9e207c BH |
271 | smp_wmb(); |
272 | ||
152b6a62 | 273 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
274 | } |
275 | ||
276 | /* NAPI poll handler | |
277 | * | |
278 | * NAPI guarantees serialisation of polls of the same device, which | |
279 | * provides the guarantee required by efx_process_channel(). | |
280 | */ | |
281 | static int efx_poll(struct napi_struct *napi, int budget) | |
282 | { | |
283 | struct efx_channel *channel = | |
284 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 285 | struct efx_nic *efx = channel->efx; |
fa236e18 | 286 | int spent; |
8ceee660 | 287 | |
62776d03 BH |
288 | netif_vdbg(efx, intr, efx->net_dev, |
289 | "channel %d NAPI poll executing on CPU %d\n", | |
290 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 291 | |
fa236e18 | 292 | spent = efx_process_channel(channel, budget); |
8ceee660 | 293 | |
fa236e18 | 294 | if (spent < budget) { |
9d9a6973 | 295 | if (efx_channel_has_rx_queue(channel) && |
6fb70fd1 BH |
296 | efx->irq_rx_adaptive && |
297 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
298 | if (unlikely(channel->irq_mod_score < |
299 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
300 | if (channel->irq_moderation > 1) { |
301 | channel->irq_moderation -= 1; | |
ef2b90ee | 302 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 303 | } |
6fb70fd1 BH |
304 | } else if (unlikely(channel->irq_mod_score > |
305 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
306 | if (channel->irq_moderation < |
307 | efx->irq_rx_moderation) { | |
308 | channel->irq_moderation += 1; | |
ef2b90ee | 309 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 310 | } |
6fb70fd1 | 311 | } |
6fb70fd1 BH |
312 | channel->irq_count = 0; |
313 | channel->irq_mod_score = 0; | |
314 | } | |
315 | ||
64d8ad6d BH |
316 | efx_filter_rfs_expire(channel); |
317 | ||
8ceee660 | 318 | /* There is no race here; although napi_disable() will |
288379f0 | 319 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
320 | * since efx_channel_processed() will have no effect if |
321 | * interrupts have already been disabled. | |
322 | */ | |
288379f0 | 323 | napi_complete(napi); |
8ceee660 BH |
324 | efx_channel_processed(channel); |
325 | } | |
326 | ||
fa236e18 | 327 | return spent; |
8ceee660 BH |
328 | } |
329 | ||
330 | /* Process the eventq of the specified channel immediately on this CPU | |
331 | * | |
332 | * Disable hardware generated interrupts, wait for any existing | |
333 | * processing to finish, then directly poll (and ack ) the eventq. | |
334 | * Finally reenable NAPI and interrupts. | |
335 | * | |
d4fabcc8 BH |
336 | * This is for use only during a loopback self-test. It must not |
337 | * deliver any packets up the stack as this can result in deadlock. | |
8ceee660 BH |
338 | */ |
339 | void efx_process_channel_now(struct efx_channel *channel) | |
340 | { | |
341 | struct efx_nic *efx = channel->efx; | |
342 | ||
8313aca3 | 343 | BUG_ON(channel->channel >= efx->n_channels); |
8ceee660 | 344 | BUG_ON(!channel->enabled); |
d4fabcc8 | 345 | BUG_ON(!efx->loopback_selftest); |
8ceee660 BH |
346 | |
347 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 348 | efx_nic_disable_interrupts(efx); |
94dec6a2 | 349 | if (efx->legacy_irq) { |
8ceee660 | 350 | synchronize_irq(efx->legacy_irq); |
94dec6a2 BH |
351 | efx->legacy_irq_enabled = false; |
352 | } | |
64ee3120 | 353 | if (channel->irq) |
8ceee660 BH |
354 | synchronize_irq(channel->irq); |
355 | ||
356 | /* Wait for any NAPI processing to complete */ | |
357 | napi_disable(&channel->napi_str); | |
358 | ||
359 | /* Poll the channel */ | |
ecc910f5 | 360 | efx_process_channel(channel, channel->eventq_mask + 1); |
8ceee660 BH |
361 | |
362 | /* Ack the eventq. This may cause an interrupt to be generated | |
363 | * when they are reenabled */ | |
364 | efx_channel_processed(channel); | |
365 | ||
366 | napi_enable(&channel->napi_str); | |
94dec6a2 BH |
367 | if (efx->legacy_irq) |
368 | efx->legacy_irq_enabled = true; | |
152b6a62 | 369 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
370 | } |
371 | ||
372 | /* Create event queue | |
373 | * Event queue memory allocations are done only once. If the channel | |
374 | * is reset, the memory buffer will be reused; this guards against | |
375 | * errors during channel reset and also simplifies interrupt handling. | |
376 | */ | |
377 | static int efx_probe_eventq(struct efx_channel *channel) | |
378 | { | |
ecc910f5 SH |
379 | struct efx_nic *efx = channel->efx; |
380 | unsigned long entries; | |
381 | ||
86ee5302 | 382 | netif_dbg(efx, probe, efx->net_dev, |
62776d03 | 383 | "chan %d create event queue\n", channel->channel); |
8ceee660 | 384 | |
ecc910f5 SH |
385 | /* Build an event queue with room for one event per tx and rx buffer, |
386 | * plus some extra for link state events and MCDI completions. */ | |
387 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
388 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
389 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
390 | ||
152b6a62 | 391 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
392 | } |
393 | ||
394 | /* Prepare channel's event queue */ | |
bc3c90a2 | 395 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 396 | { |
62776d03 BH |
397 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
398 | "chan %d init event queue\n", channel->channel); | |
8ceee660 BH |
399 | |
400 | channel->eventq_read_ptr = 0; | |
401 | ||
152b6a62 | 402 | efx_nic_init_eventq(channel); |
8ceee660 BH |
403 | } |
404 | ||
9f2cb71c BH |
405 | /* Enable event queue processing and NAPI */ |
406 | static void efx_start_eventq(struct efx_channel *channel) | |
407 | { | |
408 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, | |
409 | "chan %d start event queue\n", channel->channel); | |
410 | ||
411 | /* The interrupt handler for this channel may set work_pending | |
412 | * as soon as we enable it. Make sure it's cleared before | |
413 | * then. Similarly, make sure it sees the enabled flag set. | |
414 | */ | |
415 | channel->work_pending = false; | |
416 | channel->enabled = true; | |
417 | smp_wmb(); | |
418 | ||
419 | napi_enable(&channel->napi_str); | |
420 | efx_nic_eventq_read_ack(channel); | |
421 | } | |
422 | ||
423 | /* Disable event queue processing and NAPI */ | |
424 | static void efx_stop_eventq(struct efx_channel *channel) | |
425 | { | |
426 | if (!channel->enabled) | |
427 | return; | |
428 | ||
429 | napi_disable(&channel->napi_str); | |
430 | channel->enabled = false; | |
431 | } | |
432 | ||
8ceee660 BH |
433 | static void efx_fini_eventq(struct efx_channel *channel) |
434 | { | |
62776d03 BH |
435 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
436 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 437 | |
152b6a62 | 438 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
439 | } |
440 | ||
441 | static void efx_remove_eventq(struct efx_channel *channel) | |
442 | { | |
62776d03 BH |
443 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
444 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 445 | |
152b6a62 | 446 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
447 | } |
448 | ||
449 | /************************************************************************** | |
450 | * | |
451 | * Channel handling | |
452 | * | |
453 | *************************************************************************/ | |
454 | ||
7f967c01 | 455 | /* Allocate and initialise a channel structure. */ |
4642610c BH |
456 | static struct efx_channel * |
457 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
458 | { | |
459 | struct efx_channel *channel; | |
460 | struct efx_rx_queue *rx_queue; | |
461 | struct efx_tx_queue *tx_queue; | |
462 | int j; | |
463 | ||
7f967c01 BH |
464 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); |
465 | if (!channel) | |
466 | return NULL; | |
4642610c | 467 | |
7f967c01 BH |
468 | channel->efx = efx; |
469 | channel->channel = i; | |
470 | channel->type = &efx_default_channel_type; | |
4642610c | 471 | |
7f967c01 BH |
472 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
473 | tx_queue = &channel->tx_queue[j]; | |
474 | tx_queue->efx = efx; | |
475 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
476 | tx_queue->channel = channel; | |
477 | } | |
4642610c | 478 | |
7f967c01 BH |
479 | rx_queue = &channel->rx_queue; |
480 | rx_queue->efx = efx; | |
481 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
482 | (unsigned long)rx_queue); | |
4642610c | 483 | |
7f967c01 BH |
484 | return channel; |
485 | } | |
486 | ||
487 | /* Allocate and initialise a channel structure, copying parameters | |
488 | * (but not resources) from an old channel structure. | |
489 | */ | |
490 | static struct efx_channel * | |
491 | efx_copy_channel(const struct efx_channel *old_channel) | |
492 | { | |
493 | struct efx_channel *channel; | |
494 | struct efx_rx_queue *rx_queue; | |
495 | struct efx_tx_queue *tx_queue; | |
496 | int j; | |
4642610c | 497 | |
7f967c01 BH |
498 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); |
499 | if (!channel) | |
500 | return NULL; | |
501 | ||
502 | *channel = *old_channel; | |
503 | ||
504 | channel->napi_dev = NULL; | |
505 | memset(&channel->eventq, 0, sizeof(channel->eventq)); | |
4642610c | 506 | |
7f967c01 BH |
507 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
508 | tx_queue = &channel->tx_queue[j]; | |
509 | if (tx_queue->channel) | |
4642610c | 510 | tx_queue->channel = channel; |
7f967c01 BH |
511 | tx_queue->buffer = NULL; |
512 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
4642610c BH |
513 | } |
514 | ||
4642610c | 515 | rx_queue = &channel->rx_queue; |
7f967c01 BH |
516 | rx_queue->buffer = NULL; |
517 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
4642610c BH |
518 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
519 | (unsigned long)rx_queue); | |
520 | ||
521 | return channel; | |
522 | } | |
523 | ||
8ceee660 BH |
524 | static int efx_probe_channel(struct efx_channel *channel) |
525 | { | |
526 | struct efx_tx_queue *tx_queue; | |
527 | struct efx_rx_queue *rx_queue; | |
528 | int rc; | |
529 | ||
62776d03 BH |
530 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
531 | "creating channel %d\n", channel->channel); | |
8ceee660 | 532 | |
7f967c01 BH |
533 | rc = channel->type->pre_probe(channel); |
534 | if (rc) | |
535 | goto fail; | |
536 | ||
8ceee660 BH |
537 | rc = efx_probe_eventq(channel); |
538 | if (rc) | |
7f967c01 | 539 | goto fail; |
8ceee660 BH |
540 | |
541 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
542 | rc = efx_probe_tx_queue(tx_queue); | |
543 | if (rc) | |
7f967c01 | 544 | goto fail; |
8ceee660 BH |
545 | } |
546 | ||
547 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
548 | rc = efx_probe_rx_queue(rx_queue); | |
549 | if (rc) | |
7f967c01 | 550 | goto fail; |
8ceee660 BH |
551 | } |
552 | ||
553 | channel->n_rx_frm_trunc = 0; | |
554 | ||
555 | return 0; | |
556 | ||
7f967c01 BH |
557 | fail: |
558 | efx_remove_channel(channel); | |
8ceee660 BH |
559 | return rc; |
560 | } | |
561 | ||
7f967c01 BH |
562 | static void |
563 | efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) | |
564 | { | |
565 | struct efx_nic *efx = channel->efx; | |
566 | const char *type; | |
567 | int number; | |
568 | ||
569 | number = channel->channel; | |
570 | if (efx->tx_channel_offset == 0) { | |
571 | type = ""; | |
572 | } else if (channel->channel < efx->tx_channel_offset) { | |
573 | type = "-rx"; | |
574 | } else { | |
575 | type = "-tx"; | |
576 | number -= efx->tx_channel_offset; | |
577 | } | |
578 | snprintf(buf, len, "%s%s-%d", efx->name, type, number); | |
579 | } | |
8ceee660 | 580 | |
56536e9c BH |
581 | static void efx_set_channel_names(struct efx_nic *efx) |
582 | { | |
583 | struct efx_channel *channel; | |
56536e9c | 584 | |
7f967c01 BH |
585 | efx_for_each_channel(channel, efx) |
586 | channel->type->get_name(channel, | |
587 | efx->channel_name[channel->channel], | |
588 | sizeof(efx->channel_name[0])); | |
56536e9c BH |
589 | } |
590 | ||
4642610c BH |
591 | static int efx_probe_channels(struct efx_nic *efx) |
592 | { | |
593 | struct efx_channel *channel; | |
594 | int rc; | |
595 | ||
596 | /* Restart special buffer allocation */ | |
597 | efx->next_buffer_table = 0; | |
598 | ||
c92aaff1 BH |
599 | /* Probe channels in reverse, so that any 'extra' channels |
600 | * use the start of the buffer table. This allows the traffic | |
601 | * channels to be resized without moving them or wasting the | |
602 | * entries before them. | |
603 | */ | |
604 | efx_for_each_channel_rev(channel, efx) { | |
4642610c BH |
605 | rc = efx_probe_channel(channel); |
606 | if (rc) { | |
607 | netif_err(efx, probe, efx->net_dev, | |
608 | "failed to create channel %d\n", | |
609 | channel->channel); | |
610 | goto fail; | |
611 | } | |
612 | } | |
613 | efx_set_channel_names(efx); | |
614 | ||
615 | return 0; | |
616 | ||
617 | fail: | |
618 | efx_remove_channels(efx); | |
619 | return rc; | |
620 | } | |
621 | ||
8ceee660 BH |
622 | /* Channels are shutdown and reinitialised whilst the NIC is running |
623 | * to propagate configuration changes (mtu, checksum offload), or | |
624 | * to clear hardware error conditions | |
625 | */ | |
9f2cb71c | 626 | static void efx_start_datapath(struct efx_nic *efx) |
8ceee660 BH |
627 | { |
628 | struct efx_tx_queue *tx_queue; | |
629 | struct efx_rx_queue *rx_queue; | |
630 | struct efx_channel *channel; | |
8ceee660 | 631 | |
f7f13b0b BH |
632 | /* Calculate the rx buffer allocation parameters required to |
633 | * support the current MTU, including padding for header | |
634 | * alignment and overruns. | |
635 | */ | |
636 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
637 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
39c9cf07 | 638 | efx->type->rx_buffer_hash_size + |
f7f13b0b | 639 | efx->type->rx_buffer_padding); |
62b330ba SH |
640 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
641 | sizeof(struct efx_rx_page_state)); | |
8ceee660 | 642 | |
14bf718f BH |
643 | /* We must keep at least one descriptor in a TX ring empty. |
644 | * We could avoid this when the queue size does not exactly | |
645 | * match the hardware ring size, but it's not that important. | |
646 | * Therefore we stop the queue when one more skb might fill | |
647 | * the ring completely. We wake it when half way back to | |
648 | * empty. | |
649 | */ | |
650 | efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); | |
651 | efx->txq_wake_thresh = efx->txq_stop_thresh / 2; | |
652 | ||
8ceee660 BH |
653 | /* Initialise the channels */ |
654 | efx_for_each_channel(channel, efx) { | |
bc3c90a2 BH |
655 | efx_for_each_channel_tx_queue(tx_queue, channel) |
656 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
657 | |
658 | /* The rx buffer allocation strategy is MTU dependent */ | |
659 | efx_rx_strategy(channel); | |
660 | ||
9f2cb71c | 661 | efx_for_each_channel_rx_queue(rx_queue, channel) { |
bc3c90a2 | 662 | efx_init_rx_queue(rx_queue); |
9f2cb71c BH |
663 | efx_nic_generate_fill_event(rx_queue); |
664 | } | |
8ceee660 BH |
665 | |
666 | WARN_ON(channel->rx_pkt != NULL); | |
667 | efx_rx_strategy(channel); | |
668 | } | |
8ceee660 | 669 | |
9f2cb71c BH |
670 | if (netif_device_present(efx->net_dev)) |
671 | netif_tx_wake_all_queues(efx->net_dev); | |
8ceee660 BH |
672 | } |
673 | ||
9f2cb71c | 674 | static void efx_stop_datapath(struct efx_nic *efx) |
8ceee660 BH |
675 | { |
676 | struct efx_channel *channel; | |
677 | struct efx_tx_queue *tx_queue; | |
678 | struct efx_rx_queue *rx_queue; | |
3dca9d2d | 679 | struct pci_dev *dev = efx->pci_dev; |
6bc5d3a9 | 680 | int rc; |
8ceee660 BH |
681 | |
682 | EFX_ASSERT_RESET_SERIALISED(efx); | |
683 | BUG_ON(efx->port_enabled); | |
684 | ||
3dca9d2d SH |
685 | /* Only perform flush if dma is enabled */ |
686 | if (dev->is_busmaster) { | |
687 | rc = efx_nic_flush_queues(efx); | |
688 | ||
689 | if (rc && EFX_WORKAROUND_7803(efx)) { | |
690 | /* Schedule a reset to recover from the flush failure. The | |
691 | * descriptor caches reference memory we're about to free, | |
692 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
693 | * the MACs because of the pending reset. */ | |
694 | netif_err(efx, drv, efx->net_dev, | |
695 | "Resetting to recover from flush failure\n"); | |
696 | efx_schedule_reset(efx, RESET_TYPE_ALL); | |
697 | } else if (rc) { | |
698 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); | |
699 | } else { | |
700 | netif_dbg(efx, drv, efx->net_dev, | |
701 | "successfully flushed all queues\n"); | |
702 | } | |
fd371e32 | 703 | } |
6bc5d3a9 | 704 | |
8ceee660 | 705 | efx_for_each_channel(channel, efx) { |
9f2cb71c BH |
706 | /* RX packet processing is pipelined, so wait for the |
707 | * NAPI handler to complete. At least event queue 0 | |
708 | * might be kept active by non-data events, so don't | |
709 | * use napi_synchronize() but actually disable NAPI | |
710 | * temporarily. | |
711 | */ | |
712 | if (efx_channel_has_rx_queue(channel)) { | |
713 | efx_stop_eventq(channel); | |
714 | efx_start_eventq(channel); | |
715 | } | |
8ceee660 BH |
716 | |
717 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
718 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 719 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 720 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
721 | } |
722 | } | |
723 | ||
724 | static void efx_remove_channel(struct efx_channel *channel) | |
725 | { | |
726 | struct efx_tx_queue *tx_queue; | |
727 | struct efx_rx_queue *rx_queue; | |
728 | ||
62776d03 BH |
729 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
730 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
731 | |
732 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
733 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 734 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
735 | efx_remove_tx_queue(tx_queue); |
736 | efx_remove_eventq(channel); | |
c31e5f9f | 737 | channel->type->post_remove(channel); |
8ceee660 BH |
738 | } |
739 | ||
4642610c BH |
740 | static void efx_remove_channels(struct efx_nic *efx) |
741 | { | |
742 | struct efx_channel *channel; | |
743 | ||
744 | efx_for_each_channel(channel, efx) | |
745 | efx_remove_channel(channel); | |
746 | } | |
747 | ||
748 | int | |
749 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
750 | { | |
751 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
752 | u32 old_rxq_entries, old_txq_entries; | |
7f967c01 | 753 | unsigned i, next_buffer_table = 0; |
8b7325b4 BH |
754 | int rc; |
755 | ||
756 | rc = efx_check_disabled(efx); | |
757 | if (rc) | |
758 | return rc; | |
7f967c01 BH |
759 | |
760 | /* Not all channels should be reallocated. We must avoid | |
761 | * reallocating their buffer table entries. | |
762 | */ | |
763 | efx_for_each_channel(channel, efx) { | |
764 | struct efx_rx_queue *rx_queue; | |
765 | struct efx_tx_queue *tx_queue; | |
766 | ||
767 | if (channel->type->copy) | |
768 | continue; | |
769 | next_buffer_table = max(next_buffer_table, | |
770 | channel->eventq.index + | |
771 | channel->eventq.entries); | |
772 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
773 | next_buffer_table = max(next_buffer_table, | |
774 | rx_queue->rxd.index + | |
775 | rx_queue->rxd.entries); | |
776 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
777 | next_buffer_table = max(next_buffer_table, | |
778 | tx_queue->txd.index + | |
779 | tx_queue->txd.entries); | |
780 | } | |
4642610c BH |
781 | |
782 | efx_stop_all(efx); | |
7f967c01 | 783 | efx_stop_interrupts(efx, true); |
4642610c | 784 | |
7f967c01 | 785 | /* Clone channels (where possible) */ |
4642610c BH |
786 | memset(other_channel, 0, sizeof(other_channel)); |
787 | for (i = 0; i < efx->n_channels; i++) { | |
7f967c01 BH |
788 | channel = efx->channel[i]; |
789 | if (channel->type->copy) | |
790 | channel = channel->type->copy(channel); | |
4642610c BH |
791 | if (!channel) { |
792 | rc = -ENOMEM; | |
793 | goto out; | |
794 | } | |
795 | other_channel[i] = channel; | |
796 | } | |
797 | ||
798 | /* Swap entry counts and channel pointers */ | |
799 | old_rxq_entries = efx->rxq_entries; | |
800 | old_txq_entries = efx->txq_entries; | |
801 | efx->rxq_entries = rxq_entries; | |
802 | efx->txq_entries = txq_entries; | |
803 | for (i = 0; i < efx->n_channels; i++) { | |
804 | channel = efx->channel[i]; | |
805 | efx->channel[i] = other_channel[i]; | |
806 | other_channel[i] = channel; | |
807 | } | |
808 | ||
7f967c01 BH |
809 | /* Restart buffer table allocation */ |
810 | efx->next_buffer_table = next_buffer_table; | |
e8f14992 | 811 | |
e8f14992 | 812 | for (i = 0; i < efx->n_channels; i++) { |
7f967c01 BH |
813 | channel = efx->channel[i]; |
814 | if (!channel->type->copy) | |
815 | continue; | |
816 | rc = efx_probe_channel(channel); | |
817 | if (rc) | |
818 | goto rollback; | |
819 | efx_init_napi_channel(efx->channel[i]); | |
e8f14992 | 820 | } |
7f967c01 | 821 | |
4642610c | 822 | out: |
7f967c01 BH |
823 | /* Destroy unused channel structures */ |
824 | for (i = 0; i < efx->n_channels; i++) { | |
825 | channel = other_channel[i]; | |
826 | if (channel && channel->type->copy) { | |
827 | efx_fini_napi_channel(channel); | |
828 | efx_remove_channel(channel); | |
829 | kfree(channel); | |
830 | } | |
831 | } | |
4642610c | 832 | |
7f967c01 | 833 | efx_start_interrupts(efx, true); |
4642610c BH |
834 | efx_start_all(efx); |
835 | return rc; | |
836 | ||
837 | rollback: | |
838 | /* Swap back */ | |
839 | efx->rxq_entries = old_rxq_entries; | |
840 | efx->txq_entries = old_txq_entries; | |
841 | for (i = 0; i < efx->n_channels; i++) { | |
842 | channel = efx->channel[i]; | |
843 | efx->channel[i] = other_channel[i]; | |
844 | other_channel[i] = channel; | |
845 | } | |
846 | goto out; | |
847 | } | |
848 | ||
90d683af | 849 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 850 | { |
90d683af | 851 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
852 | } |
853 | ||
7f967c01 BH |
854 | static const struct efx_channel_type efx_default_channel_type = { |
855 | .pre_probe = efx_channel_dummy_op_int, | |
c31e5f9f | 856 | .post_remove = efx_channel_dummy_op_void, |
7f967c01 BH |
857 | .get_name = efx_get_channel_name, |
858 | .copy = efx_copy_channel, | |
859 | .keep_eventq = false, | |
860 | }; | |
861 | ||
862 | int efx_channel_dummy_op_int(struct efx_channel *channel) | |
863 | { | |
864 | return 0; | |
865 | } | |
866 | ||
c31e5f9f SH |
867 | void efx_channel_dummy_op_void(struct efx_channel *channel) |
868 | { | |
869 | } | |
870 | ||
8ceee660 BH |
871 | /************************************************************************** |
872 | * | |
873 | * Port handling | |
874 | * | |
875 | **************************************************************************/ | |
876 | ||
877 | /* This ensures that the kernel is kept informed (via | |
878 | * netif_carrier_on/off) of the link status, and also maintains the | |
879 | * link status's stop on the port's TX queue. | |
880 | */ | |
fdaa9aed | 881 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 882 | { |
eb50c0d6 BH |
883 | struct efx_link_state *link_state = &efx->link_state; |
884 | ||
8ceee660 BH |
885 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
886 | * that no events are triggered between unregister_netdev() and the | |
887 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
888 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
889 | if (!netif_running(efx->net_dev)) | |
890 | return; | |
891 | ||
eb50c0d6 | 892 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
893 | efx->n_link_state_changes++; |
894 | ||
eb50c0d6 | 895 | if (link_state->up) |
8ceee660 BH |
896 | netif_carrier_on(efx->net_dev); |
897 | else | |
898 | netif_carrier_off(efx->net_dev); | |
899 | } | |
900 | ||
901 | /* Status message for kernel log */ | |
2aa9ef11 | 902 | if (link_state->up) |
62776d03 BH |
903 | netif_info(efx, link, efx->net_dev, |
904 | "link up at %uMbps %s-duplex (MTU %d)%s\n", | |
905 | link_state->speed, link_state->fd ? "full" : "half", | |
906 | efx->net_dev->mtu, | |
907 | (efx->promiscuous ? " [PROMISC]" : "")); | |
2aa9ef11 | 908 | else |
62776d03 | 909 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
910 | } |
911 | ||
d3245b28 BH |
912 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
913 | { | |
914 | efx->link_advertising = advertising; | |
915 | if (advertising) { | |
916 | if (advertising & ADVERTISED_Pause) | |
917 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
918 | else | |
919 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
920 | if (advertising & ADVERTISED_Asym_Pause) | |
921 | efx->wanted_fc ^= EFX_FC_TX; | |
922 | } | |
923 | } | |
924 | ||
b5626946 | 925 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
926 | { |
927 | efx->wanted_fc = wanted_fc; | |
928 | if (efx->link_advertising) { | |
929 | if (wanted_fc & EFX_FC_RX) | |
930 | efx->link_advertising |= (ADVERTISED_Pause | | |
931 | ADVERTISED_Asym_Pause); | |
932 | else | |
933 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
934 | ADVERTISED_Asym_Pause); | |
935 | if (wanted_fc & EFX_FC_TX) | |
936 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
937 | } | |
938 | } | |
939 | ||
115122af BH |
940 | static void efx_fini_port(struct efx_nic *efx); |
941 | ||
d3245b28 BH |
942 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
943 | * the MAC appropriately. All other PHY configuration changes are pushed | |
944 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
945 | * through efx_monitor(). | |
946 | * | |
947 | * Callers must hold the mac_lock | |
948 | */ | |
949 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 950 | { |
d3245b28 BH |
951 | enum efx_phy_mode phy_mode; |
952 | int rc; | |
8ceee660 | 953 | |
d3245b28 | 954 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 955 | |
0fca8c97 | 956 | /* Serialise the promiscuous flag with efx_set_rx_mode. */ |
73ba7b68 BH |
957 | netif_addr_lock_bh(efx->net_dev); |
958 | netif_addr_unlock_bh(efx->net_dev); | |
a816f75a | 959 | |
d3245b28 BH |
960 | /* Disable PHY transmit in mac level loopbacks */ |
961 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
962 | if (LOOPBACK_INTERNAL(efx)) |
963 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
964 | else | |
965 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 966 | |
d3245b28 | 967 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 968 | |
d3245b28 BH |
969 | if (rc) |
970 | efx->phy_mode = phy_mode; | |
177dfcd8 | 971 | |
d3245b28 | 972 | return rc; |
8ceee660 BH |
973 | } |
974 | ||
975 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
976 | * disabled. */ | |
d3245b28 | 977 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 978 | { |
d3245b28 BH |
979 | int rc; |
980 | ||
8ceee660 BH |
981 | EFX_ASSERT_RESET_SERIALISED(efx); |
982 | ||
983 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 984 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 985 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
986 | |
987 | return rc; | |
8ceee660 BH |
988 | } |
989 | ||
8be4f3e6 BH |
990 | /* Asynchronous work item for changing MAC promiscuity and multicast |
991 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
992 | * MAC directly. */ | |
766ca0fa BH |
993 | static void efx_mac_work(struct work_struct *data) |
994 | { | |
995 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
996 | ||
997 | mutex_lock(&efx->mac_lock); | |
30b81cda | 998 | if (efx->port_enabled) |
710b208d | 999 | efx->type->reconfigure_mac(efx); |
766ca0fa BH |
1000 | mutex_unlock(&efx->mac_lock); |
1001 | } | |
1002 | ||
8ceee660 BH |
1003 | static int efx_probe_port(struct efx_nic *efx) |
1004 | { | |
1005 | int rc; | |
1006 | ||
62776d03 | 1007 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 1008 | |
ff3b00a0 SH |
1009 | if (phy_flash_cfg) |
1010 | efx->phy_mode = PHY_MODE_SPECIAL; | |
1011 | ||
ef2b90ee BH |
1012 | /* Connect up MAC/PHY operations table */ |
1013 | rc = efx->type->probe_port(efx); | |
8ceee660 | 1014 | if (rc) |
e42de262 | 1015 | return rc; |
8ceee660 | 1016 | |
e332bcb3 BH |
1017 | /* Initialise MAC address to permanent address */ |
1018 | memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN); | |
8ceee660 BH |
1019 | |
1020 | return 0; | |
8ceee660 BH |
1021 | } |
1022 | ||
1023 | static int efx_init_port(struct efx_nic *efx) | |
1024 | { | |
1025 | int rc; | |
1026 | ||
62776d03 | 1027 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 1028 | |
1dfc5cea BH |
1029 | mutex_lock(&efx->mac_lock); |
1030 | ||
177dfcd8 | 1031 | rc = efx->phy_op->init(efx); |
8ceee660 | 1032 | if (rc) |
1dfc5cea | 1033 | goto fail1; |
8ceee660 | 1034 | |
dc8cfa55 | 1035 | efx->port_initialized = true; |
1dfc5cea | 1036 | |
d3245b28 BH |
1037 | /* Reconfigure the MAC before creating dma queues (required for |
1038 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
710b208d | 1039 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1040 | |
1041 | /* Ensure the PHY advertises the correct flow control settings */ | |
1042 | rc = efx->phy_op->reconfigure(efx); | |
1043 | if (rc) | |
1044 | goto fail2; | |
1045 | ||
1dfc5cea | 1046 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 1047 | return 0; |
177dfcd8 | 1048 | |
1dfc5cea | 1049 | fail2: |
177dfcd8 | 1050 | efx->phy_op->fini(efx); |
1dfc5cea BH |
1051 | fail1: |
1052 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 1053 | return rc; |
8ceee660 BH |
1054 | } |
1055 | ||
8ceee660 BH |
1056 | static void efx_start_port(struct efx_nic *efx) |
1057 | { | |
62776d03 | 1058 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
1059 | BUG_ON(efx->port_enabled); |
1060 | ||
1061 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1062 | efx->port_enabled = true; |
8be4f3e6 BH |
1063 | |
1064 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
1065 | * and then cancelled by efx_flush_all() */ | |
710b208d | 1066 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 1067 | |
8ceee660 BH |
1068 | mutex_unlock(&efx->mac_lock); |
1069 | } | |
1070 | ||
fdaa9aed | 1071 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
1072 | static void efx_stop_port(struct efx_nic *efx) |
1073 | { | |
62776d03 | 1074 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 BH |
1075 | |
1076 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1077 | efx->port_enabled = false; |
8ceee660 BH |
1078 | mutex_unlock(&efx->mac_lock); |
1079 | ||
1080 | /* Serialise against efx_set_multicast_list() */ | |
73ba7b68 BH |
1081 | netif_addr_lock_bh(efx->net_dev); |
1082 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
1083 | } |
1084 | ||
1085 | static void efx_fini_port(struct efx_nic *efx) | |
1086 | { | |
62776d03 | 1087 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1088 | |
1089 | if (!efx->port_initialized) | |
1090 | return; | |
1091 | ||
177dfcd8 | 1092 | efx->phy_op->fini(efx); |
dc8cfa55 | 1093 | efx->port_initialized = false; |
8ceee660 | 1094 | |
eb50c0d6 | 1095 | efx->link_state.up = false; |
8ceee660 BH |
1096 | efx_link_status_changed(efx); |
1097 | } | |
1098 | ||
1099 | static void efx_remove_port(struct efx_nic *efx) | |
1100 | { | |
62776d03 | 1101 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1102 | |
ef2b90ee | 1103 | efx->type->remove_port(efx); |
8ceee660 BH |
1104 | } |
1105 | ||
1106 | /************************************************************************** | |
1107 | * | |
1108 | * NIC handling | |
1109 | * | |
1110 | **************************************************************************/ | |
1111 | ||
1112 | /* This configures the PCI device to enable I/O and DMA. */ | |
1113 | static int efx_init_io(struct efx_nic *efx) | |
1114 | { | |
1115 | struct pci_dev *pci_dev = efx->pci_dev; | |
1116 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
1117 | int rc; | |
1118 | ||
62776d03 | 1119 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1120 | |
1121 | rc = pci_enable_device(pci_dev); | |
1122 | if (rc) { | |
62776d03 BH |
1123 | netif_err(efx, probe, efx->net_dev, |
1124 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1125 | goto fail1; |
1126 | } | |
1127 | ||
1128 | pci_set_master(pci_dev); | |
1129 | ||
1130 | /* Set the PCI DMA mask. Try all possibilities from our | |
1131 | * genuine mask down to 32 bits, because some architectures | |
1132 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1133 | * masks event though they reject 46 bit masks. | |
1134 | */ | |
1135 | while (dma_mask > 0x7fffffffUL) { | |
0e33d870 BH |
1136 | if (dma_supported(&pci_dev->dev, dma_mask)) { |
1137 | rc = dma_set_mask(&pci_dev->dev, dma_mask); | |
e9e01846 BH |
1138 | if (rc == 0) |
1139 | break; | |
1140 | } | |
8ceee660 BH |
1141 | dma_mask >>= 1; |
1142 | } | |
1143 | if (rc) { | |
62776d03 BH |
1144 | netif_err(efx, probe, efx->net_dev, |
1145 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1146 | goto fail2; |
1147 | } | |
62776d03 BH |
1148 | netif_dbg(efx, probe, efx->net_dev, |
1149 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
0e33d870 | 1150 | rc = dma_set_coherent_mask(&pci_dev->dev, dma_mask); |
8ceee660 | 1151 | if (rc) { |
0e33d870 BH |
1152 | /* dma_set_coherent_mask() is not *allowed* to |
1153 | * fail with a mask that dma_set_mask() accepted, | |
8ceee660 BH |
1154 | * but just in case... |
1155 | */ | |
62776d03 BH |
1156 | netif_err(efx, probe, efx->net_dev, |
1157 | "failed to set consistent DMA mask\n"); | |
8ceee660 BH |
1158 | goto fail2; |
1159 | } | |
1160 | ||
dc803df8 BH |
1161 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1162 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1163 | if (rc) { |
62776d03 BH |
1164 | netif_err(efx, probe, efx->net_dev, |
1165 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1166 | rc = -EIO; |
1167 | goto fail3; | |
1168 | } | |
86c432ca BH |
1169 | efx->membase = ioremap_nocache(efx->membase_phys, |
1170 | efx->type->mem_map_size); | |
8ceee660 | 1171 | if (!efx->membase) { |
62776d03 BH |
1172 | netif_err(efx, probe, efx->net_dev, |
1173 | "could not map memory BAR at %llx+%x\n", | |
1174 | (unsigned long long)efx->membase_phys, | |
1175 | efx->type->mem_map_size); | |
8ceee660 BH |
1176 | rc = -ENOMEM; |
1177 | goto fail4; | |
1178 | } | |
62776d03 BH |
1179 | netif_dbg(efx, probe, efx->net_dev, |
1180 | "memory BAR at %llx+%x (virtual %p)\n", | |
1181 | (unsigned long long)efx->membase_phys, | |
1182 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
1183 | |
1184 | return 0; | |
1185 | ||
1186 | fail4: | |
dc803df8 | 1187 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1188 | fail3: |
2c118e0f | 1189 | efx->membase_phys = 0; |
8ceee660 BH |
1190 | fail2: |
1191 | pci_disable_device(efx->pci_dev); | |
1192 | fail1: | |
1193 | return rc; | |
1194 | } | |
1195 | ||
1196 | static void efx_fini_io(struct efx_nic *efx) | |
1197 | { | |
62776d03 | 1198 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1199 | |
1200 | if (efx->membase) { | |
1201 | iounmap(efx->membase); | |
1202 | efx->membase = NULL; | |
1203 | } | |
1204 | ||
1205 | if (efx->membase_phys) { | |
dc803df8 | 1206 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1207 | efx->membase_phys = 0; |
8ceee660 BH |
1208 | } |
1209 | ||
1210 | pci_disable_device(efx->pci_dev); | |
1211 | } | |
1212 | ||
a9a52506 | 1213 | static unsigned int efx_wanted_parallelism(struct efx_nic *efx) |
46123d04 | 1214 | { |
cdb08f8f | 1215 | cpumask_var_t thread_mask; |
a16e5b24 | 1216 | unsigned int count; |
46123d04 | 1217 | int cpu; |
5b874e25 | 1218 | |
cd2d5b52 BH |
1219 | if (rss_cpus) { |
1220 | count = rss_cpus; | |
1221 | } else { | |
1222 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { | |
1223 | netif_warn(efx, probe, efx->net_dev, | |
1224 | "RSS disabled due to allocation failure\n"); | |
1225 | return 1; | |
1226 | } | |
46123d04 | 1227 | |
cd2d5b52 BH |
1228 | count = 0; |
1229 | for_each_online_cpu(cpu) { | |
1230 | if (!cpumask_test_cpu(cpu, thread_mask)) { | |
1231 | ++count; | |
1232 | cpumask_or(thread_mask, thread_mask, | |
1233 | topology_thread_cpumask(cpu)); | |
1234 | } | |
1235 | } | |
1236 | ||
1237 | free_cpumask_var(thread_mask); | |
2f8975fb RR |
1238 | } |
1239 | ||
cd2d5b52 BH |
1240 | /* If RSS is requested for the PF *and* VFs then we can't write RSS |
1241 | * table entries that are inaccessible to VFs | |
1242 | */ | |
1243 | if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 && | |
1244 | count > efx_vf_size(efx)) { | |
1245 | netif_warn(efx, probe, efx->net_dev, | |
1246 | "Reducing number of RSS channels from %u to %u for " | |
1247 | "VF support. Increase vf-msix-limit to use more " | |
1248 | "channels on the PF.\n", | |
1249 | count, efx_vf_size(efx)); | |
1250 | count = efx_vf_size(efx); | |
46123d04 BH |
1251 | } |
1252 | ||
1253 | return count; | |
1254 | } | |
1255 | ||
64d8ad6d BH |
1256 | static int |
1257 | efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries) | |
1258 | { | |
1259 | #ifdef CONFIG_RFS_ACCEL | |
a16e5b24 BH |
1260 | unsigned int i; |
1261 | int rc; | |
64d8ad6d BH |
1262 | |
1263 | efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels); | |
1264 | if (!efx->net_dev->rx_cpu_rmap) | |
1265 | return -ENOMEM; | |
1266 | for (i = 0; i < efx->n_rx_channels; i++) { | |
1267 | rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, | |
1268 | xentries[i].vector); | |
1269 | if (rc) { | |
1270 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
1271 | efx->net_dev->rx_cpu_rmap = NULL; | |
1272 | return rc; | |
1273 | } | |
1274 | } | |
1275 | #endif | |
1276 | return 0; | |
1277 | } | |
1278 | ||
46123d04 BH |
1279 | /* Probe the number and type of interrupts we are able to obtain, and |
1280 | * the resulting numbers of channels and RX queues. | |
1281 | */ | |
64d8ad6d | 1282 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1283 | { |
a16e5b24 BH |
1284 | unsigned int max_channels = |
1285 | min(efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
7f967c01 BH |
1286 | unsigned int extra_channels = 0; |
1287 | unsigned int i, j; | |
a16e5b24 | 1288 | int rc; |
8ceee660 | 1289 | |
7f967c01 BH |
1290 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) |
1291 | if (efx->extra_channel_type[i]) | |
1292 | ++extra_channels; | |
1293 | ||
8ceee660 | 1294 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { |
46123d04 | 1295 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a16e5b24 | 1296 | unsigned int n_channels; |
aa6ef27e | 1297 | |
a9a52506 | 1298 | n_channels = efx_wanted_parallelism(efx); |
a4900ac9 BH |
1299 | if (separate_tx_channels) |
1300 | n_channels *= 2; | |
7f967c01 | 1301 | n_channels += extra_channels; |
a4900ac9 | 1302 | n_channels = min(n_channels, max_channels); |
8ceee660 | 1303 | |
a4900ac9 | 1304 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1305 | xentries[i].entry = i; |
a4900ac9 | 1306 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1307 | if (rc > 0) { |
62776d03 BH |
1308 | netif_err(efx, drv, efx->net_dev, |
1309 | "WARNING: Insufficient MSI-X vectors" | |
a16e5b24 | 1310 | " available (%d < %u).\n", rc, n_channels); |
62776d03 BH |
1311 | netif_err(efx, drv, efx->net_dev, |
1312 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1313 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1314 | n_channels = rc; | |
8ceee660 | 1315 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1316 | n_channels); |
8ceee660 BH |
1317 | } |
1318 | ||
1319 | if (rc == 0) { | |
a4900ac9 | 1320 | efx->n_channels = n_channels; |
7f967c01 BH |
1321 | if (n_channels > extra_channels) |
1322 | n_channels -= extra_channels; | |
a4900ac9 | 1323 | if (separate_tx_channels) { |
7f967c01 BH |
1324 | efx->n_tx_channels = max(n_channels / 2, 1U); |
1325 | efx->n_rx_channels = max(n_channels - | |
1326 | efx->n_tx_channels, | |
1327 | 1U); | |
a4900ac9 | 1328 | } else { |
7f967c01 BH |
1329 | efx->n_tx_channels = n_channels; |
1330 | efx->n_rx_channels = n_channels; | |
a4900ac9 | 1331 | } |
64d8ad6d BH |
1332 | rc = efx_init_rx_cpu_rmap(efx, xentries); |
1333 | if (rc) { | |
1334 | pci_disable_msix(efx->pci_dev); | |
1335 | return rc; | |
1336 | } | |
7f967c01 | 1337 | for (i = 0; i < efx->n_channels; i++) |
f7d12cdc BH |
1338 | efx_get_channel(efx, i)->irq = |
1339 | xentries[i].vector; | |
8ceee660 BH |
1340 | } else { |
1341 | /* Fall back to single channel MSI */ | |
1342 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1343 | netif_err(efx, drv, efx->net_dev, |
1344 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1345 | } |
1346 | } | |
1347 | ||
1348 | /* Try single interrupt MSI */ | |
1349 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1350 | efx->n_channels = 1; |
a4900ac9 BH |
1351 | efx->n_rx_channels = 1; |
1352 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1353 | rc = pci_enable_msi(efx->pci_dev); |
1354 | if (rc == 0) { | |
f7d12cdc | 1355 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1356 | } else { |
62776d03 BH |
1357 | netif_err(efx, drv, efx->net_dev, |
1358 | "could not enable MSI\n"); | |
8ceee660 BH |
1359 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1360 | } | |
1361 | } | |
1362 | ||
1363 | /* Assume legacy interrupts */ | |
1364 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1365 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1366 | efx->n_rx_channels = 1; |
1367 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1368 | efx->legacy_irq = efx->pci_dev->irq; |
1369 | } | |
64d8ad6d | 1370 | |
7f967c01 BH |
1371 | /* Assign extra channels if possible */ |
1372 | j = efx->n_channels; | |
1373 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { | |
1374 | if (!efx->extra_channel_type[i]) | |
1375 | continue; | |
1376 | if (efx->interrupt_mode != EFX_INT_MODE_MSIX || | |
1377 | efx->n_channels <= extra_channels) { | |
1378 | efx->extra_channel_type[i]->handle_no_channel(efx); | |
1379 | } else { | |
1380 | --j; | |
1381 | efx_get_channel(efx, j)->type = | |
1382 | efx->extra_channel_type[i]; | |
1383 | } | |
1384 | } | |
1385 | ||
cd2d5b52 | 1386 | /* RSS might be usable on VFs even if it is disabled on the PF */ |
3132d282 | 1387 | efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ? |
cd2d5b52 BH |
1388 | efx->n_rx_channels : efx_vf_size(efx)); |
1389 | ||
64d8ad6d | 1390 | return 0; |
8ceee660 BH |
1391 | } |
1392 | ||
9f2cb71c | 1393 | /* Enable interrupts, then probe and start the event queues */ |
7f967c01 | 1394 | static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq) |
9f2cb71c BH |
1395 | { |
1396 | struct efx_channel *channel; | |
1397 | ||
8b7325b4 BH |
1398 | BUG_ON(efx->state == STATE_DISABLED); |
1399 | ||
9f2cb71c BH |
1400 | if (efx->legacy_irq) |
1401 | efx->legacy_irq_enabled = true; | |
1402 | efx_nic_enable_interrupts(efx); | |
1403 | ||
1404 | efx_for_each_channel(channel, efx) { | |
7f967c01 BH |
1405 | if (!channel->type->keep_eventq || !may_keep_eventq) |
1406 | efx_init_eventq(channel); | |
9f2cb71c BH |
1407 | efx_start_eventq(channel); |
1408 | } | |
1409 | ||
1410 | efx_mcdi_mode_event(efx); | |
1411 | } | |
1412 | ||
7f967c01 | 1413 | static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq) |
9f2cb71c BH |
1414 | { |
1415 | struct efx_channel *channel; | |
1416 | ||
8b7325b4 BH |
1417 | if (efx->state == STATE_DISABLED) |
1418 | return; | |
1419 | ||
9f2cb71c BH |
1420 | efx_mcdi_mode_poll(efx); |
1421 | ||
1422 | efx_nic_disable_interrupts(efx); | |
1423 | if (efx->legacy_irq) { | |
1424 | synchronize_irq(efx->legacy_irq); | |
1425 | efx->legacy_irq_enabled = false; | |
1426 | } | |
1427 | ||
1428 | efx_for_each_channel(channel, efx) { | |
1429 | if (channel->irq) | |
1430 | synchronize_irq(channel->irq); | |
1431 | ||
1432 | efx_stop_eventq(channel); | |
7f967c01 BH |
1433 | if (!channel->type->keep_eventq || !may_keep_eventq) |
1434 | efx_fini_eventq(channel); | |
9f2cb71c BH |
1435 | } |
1436 | } | |
1437 | ||
8ceee660 BH |
1438 | static void efx_remove_interrupts(struct efx_nic *efx) |
1439 | { | |
1440 | struct efx_channel *channel; | |
1441 | ||
1442 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1443 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1444 | channel->irq = 0; |
1445 | pci_disable_msi(efx->pci_dev); | |
1446 | pci_disable_msix(efx->pci_dev); | |
1447 | ||
1448 | /* Remove legacy interrupt */ | |
1449 | efx->legacy_irq = 0; | |
1450 | } | |
1451 | ||
8831da7b | 1452 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1453 | { |
602a5322 BH |
1454 | struct efx_channel *channel; |
1455 | struct efx_tx_queue *tx_queue; | |
1456 | ||
97653431 | 1457 | efx->tx_channel_offset = |
a4900ac9 | 1458 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 | 1459 | |
79d68b37 SH |
1460 | /* We need to mark which channels really have RX and TX |
1461 | * queues, and adjust the TX queue numbers if we have separate | |
602a5322 BH |
1462 | * RX-only and TX-only channels. |
1463 | */ | |
1464 | efx_for_each_channel(channel, efx) { | |
79d68b37 SH |
1465 | if (channel->channel < efx->n_rx_channels) |
1466 | channel->rx_queue.core_index = channel->channel; | |
1467 | else | |
1468 | channel->rx_queue.core_index = -1; | |
1469 | ||
602a5322 BH |
1470 | efx_for_each_channel_tx_queue(tx_queue, channel) |
1471 | tx_queue->queue -= (efx->tx_channel_offset * | |
1472 | EFX_TXQ_TYPES); | |
1473 | } | |
8ceee660 BH |
1474 | } |
1475 | ||
1476 | static int efx_probe_nic(struct efx_nic *efx) | |
1477 | { | |
765c9f46 | 1478 | size_t i; |
8ceee660 BH |
1479 | int rc; |
1480 | ||
62776d03 | 1481 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1482 | |
1483 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1484 | rc = efx->type->probe(efx); |
8ceee660 BH |
1485 | if (rc) |
1486 | return rc; | |
1487 | ||
a4900ac9 | 1488 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1489 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1490 | rc = efx_probe_interrupts(efx); |
1491 | if (rc) | |
1492 | goto fail; | |
8ceee660 | 1493 | |
28e47c49 BH |
1494 | efx->type->dimension_resources(efx); |
1495 | ||
5d3a6fca BH |
1496 | if (efx->n_channels > 1) |
1497 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 | 1498 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
278bc429 | 1499 | efx->rx_indir_table[i] = |
cd2d5b52 | 1500 | ethtool_rxfh_indir_default(i, efx->rss_spread); |
5d3a6fca | 1501 | |
8831da7b | 1502 | efx_set_channels(efx); |
c4f4adc7 BH |
1503 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1504 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1505 | |
1506 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1507 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1508 | true); | |
8ceee660 BH |
1509 | |
1510 | return 0; | |
64d8ad6d BH |
1511 | |
1512 | fail: | |
1513 | efx->type->remove(efx); | |
1514 | return rc; | |
8ceee660 BH |
1515 | } |
1516 | ||
1517 | static void efx_remove_nic(struct efx_nic *efx) | |
1518 | { | |
62776d03 | 1519 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1520 | |
1521 | efx_remove_interrupts(efx); | |
ef2b90ee | 1522 | efx->type->remove(efx); |
8ceee660 BH |
1523 | } |
1524 | ||
1525 | /************************************************************************** | |
1526 | * | |
1527 | * NIC startup/shutdown | |
1528 | * | |
1529 | *************************************************************************/ | |
1530 | ||
1531 | static int efx_probe_all(struct efx_nic *efx) | |
1532 | { | |
8ceee660 BH |
1533 | int rc; |
1534 | ||
8ceee660 BH |
1535 | rc = efx_probe_nic(efx); |
1536 | if (rc) { | |
62776d03 | 1537 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1538 | goto fail1; |
1539 | } | |
1540 | ||
8ceee660 BH |
1541 | rc = efx_probe_port(efx); |
1542 | if (rc) { | |
62776d03 | 1543 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1544 | goto fail2; |
1545 | } | |
1546 | ||
7e6d06f0 BH |
1547 | BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); |
1548 | if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { | |
1549 | rc = -EINVAL; | |
1550 | goto fail3; | |
1551 | } | |
ecc910f5 | 1552 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
8ceee660 | 1553 | |
64eebcfd BH |
1554 | rc = efx_probe_filters(efx); |
1555 | if (rc) { | |
1556 | netif_err(efx, probe, efx->net_dev, | |
1557 | "failed to create filter tables\n"); | |
7f967c01 | 1558 | goto fail3; |
64eebcfd BH |
1559 | } |
1560 | ||
7f967c01 BH |
1561 | rc = efx_probe_channels(efx); |
1562 | if (rc) | |
1563 | goto fail4; | |
1564 | ||
8ceee660 BH |
1565 | return 0; |
1566 | ||
64eebcfd | 1567 | fail4: |
7f967c01 | 1568 | efx_remove_filters(efx); |
8ceee660 | 1569 | fail3: |
8ceee660 BH |
1570 | efx_remove_port(efx); |
1571 | fail2: | |
1572 | efx_remove_nic(efx); | |
1573 | fail1: | |
1574 | return rc; | |
1575 | } | |
1576 | ||
8b7325b4 BH |
1577 | /* If the interface is supposed to be running but is not, start |
1578 | * the hardware and software data path, regular activity for the port | |
1579 | * (MAC statistics, link polling, etc.) and schedule the port to be | |
1580 | * reconfigured. Interrupts must already be enabled. This function | |
1581 | * is safe to call multiple times, so long as the NIC is not disabled. | |
1582 | * Requires the RTNL lock. | |
9f2cb71c | 1583 | */ |
8ceee660 BH |
1584 | static void efx_start_all(struct efx_nic *efx) |
1585 | { | |
8ceee660 | 1586 | EFX_ASSERT_RESET_SERIALISED(efx); |
8b7325b4 | 1587 | BUG_ON(efx->state == STATE_DISABLED); |
8ceee660 BH |
1588 | |
1589 | /* Check that it is appropriate to restart the interface. All | |
1590 | * of these flags are safe to read under just the rtnl lock */ | |
8b7325b4 | 1591 | if (efx->port_enabled || !netif_running(efx->net_dev)) |
8ceee660 BH |
1592 | return; |
1593 | ||
8ceee660 | 1594 | efx_start_port(efx); |
9f2cb71c | 1595 | efx_start_datapath(efx); |
8880f4ec | 1596 | |
78c1f0a0 SH |
1597 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1598 | * event driven), we have to poll the PHY because after an event queue | |
1599 | * flush, we could have a missed a link state change */ | |
1600 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1601 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1602 | efx_monitor_interval); | |
78c1f0a0 SH |
1603 | } else { |
1604 | mutex_lock(&efx->mac_lock); | |
1605 | if (efx->phy_op->poll(efx)) | |
1606 | efx_link_status_changed(efx); | |
1607 | mutex_unlock(&efx->mac_lock); | |
1608 | } | |
55edc6e6 | 1609 | |
ef2b90ee | 1610 | efx->type->start_stats(efx); |
8ceee660 BH |
1611 | } |
1612 | ||
1613 | /* Flush all delayed work. Should only be called when no more delayed work | |
1614 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1615 | * since we're holding the rtnl_lock at this point. */ | |
1616 | static void efx_flush_all(struct efx_nic *efx) | |
1617 | { | |
dd40781e | 1618 | /* Make sure the hardware monitor and event self-test are stopped */ |
8ceee660 | 1619 | cancel_delayed_work_sync(&efx->monitor_work); |
dd40781e | 1620 | efx_selftest_async_cancel(efx); |
8ceee660 | 1621 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1622 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1623 | } |
1624 | ||
8b7325b4 BH |
1625 | /* Quiesce the hardware and software data path, and regular activity |
1626 | * for the port without bringing the link down. Safe to call multiple | |
1627 | * times with the NIC in almost any state, but interrupts should be | |
1628 | * enabled. Requires the RTNL lock. | |
1629 | */ | |
8ceee660 BH |
1630 | static void efx_stop_all(struct efx_nic *efx) |
1631 | { | |
8ceee660 BH |
1632 | EFX_ASSERT_RESET_SERIALISED(efx); |
1633 | ||
1634 | /* port_enabled can be read safely under the rtnl lock */ | |
1635 | if (!efx->port_enabled) | |
1636 | return; | |
1637 | ||
ef2b90ee | 1638 | efx->type->stop_stats(efx); |
8ceee660 BH |
1639 | efx_stop_port(efx); |
1640 | ||
fdaa9aed | 1641 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1642 | efx_flush_all(efx); |
1643 | ||
8ceee660 BH |
1644 | /* Stop the kernel transmit interface late, so the watchdog |
1645 | * timer isn't ticking over the flush */ | |
9f2cb71c BH |
1646 | netif_tx_disable(efx->net_dev); |
1647 | ||
1648 | efx_stop_datapath(efx); | |
8ceee660 BH |
1649 | } |
1650 | ||
1651 | static void efx_remove_all(struct efx_nic *efx) | |
1652 | { | |
4642610c | 1653 | efx_remove_channels(efx); |
7f967c01 | 1654 | efx_remove_filters(efx); |
8ceee660 BH |
1655 | efx_remove_port(efx); |
1656 | efx_remove_nic(efx); | |
1657 | } | |
1658 | ||
8ceee660 BH |
1659 | /************************************************************************** |
1660 | * | |
1661 | * Interrupt moderation | |
1662 | * | |
1663 | **************************************************************************/ | |
1664 | ||
cc180b69 | 1665 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) |
0d86ebd8 | 1666 | { |
b548f976 BH |
1667 | if (usecs == 0) |
1668 | return 0; | |
cc180b69 | 1669 | if (usecs * 1000 < quantum_ns) |
0d86ebd8 | 1670 | return 1; /* never round down to 0 */ |
cc180b69 | 1671 | return usecs * 1000 / quantum_ns; |
0d86ebd8 BH |
1672 | } |
1673 | ||
8ceee660 | 1674 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1675 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1676 | unsigned int rx_usecs, bool rx_adaptive, | |
1677 | bool rx_may_override_tx) | |
8ceee660 | 1678 | { |
f7d12cdc | 1679 | struct efx_channel *channel; |
cc180b69 BH |
1680 | unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * |
1681 | efx->timer_quantum_ns, | |
1682 | 1000); | |
1683 | unsigned int tx_ticks; | |
1684 | unsigned int rx_ticks; | |
8ceee660 BH |
1685 | |
1686 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1687 | ||
cc180b69 | 1688 | if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) |
9e393b30 BH |
1689 | return -EINVAL; |
1690 | ||
cc180b69 BH |
1691 | tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); |
1692 | rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); | |
1693 | ||
9e393b30 BH |
1694 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && |
1695 | !rx_may_override_tx) { | |
1696 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1697 | "RX and TX IRQ moderation must be equal\n"); | |
1698 | return -EINVAL; | |
1699 | } | |
1700 | ||
6fb70fd1 | 1701 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1702 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1703 | efx_for_each_channel(channel, efx) { |
525da907 | 1704 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1705 | channel->irq_moderation = rx_ticks; |
525da907 | 1706 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1707 | channel->irq_moderation = tx_ticks; |
1708 | } | |
9e393b30 BH |
1709 | |
1710 | return 0; | |
8ceee660 BH |
1711 | } |
1712 | ||
a0c4faf5 BH |
1713 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1714 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1715 | { | |
cc180b69 BH |
1716 | /* We must round up when converting ticks to microseconds |
1717 | * because we round down when converting the other way. | |
1718 | */ | |
1719 | ||
a0c4faf5 | 1720 | *rx_adaptive = efx->irq_rx_adaptive; |
cc180b69 BH |
1721 | *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * |
1722 | efx->timer_quantum_ns, | |
1723 | 1000); | |
a0c4faf5 BH |
1724 | |
1725 | /* If channels are shared between RX and TX, so is IRQ | |
1726 | * moderation. Otherwise, IRQ moderation is the same for all | |
1727 | * TX channels and is not adaptive. | |
1728 | */ | |
1729 | if (efx->tx_channel_offset == 0) | |
1730 | *tx_usecs = *rx_usecs; | |
1731 | else | |
cc180b69 | 1732 | *tx_usecs = DIV_ROUND_UP( |
a0c4faf5 | 1733 | efx->channel[efx->tx_channel_offset]->irq_moderation * |
cc180b69 BH |
1734 | efx->timer_quantum_ns, |
1735 | 1000); | |
a0c4faf5 BH |
1736 | } |
1737 | ||
8ceee660 BH |
1738 | /************************************************************************** |
1739 | * | |
1740 | * Hardware monitor | |
1741 | * | |
1742 | **************************************************************************/ | |
1743 | ||
e254c274 | 1744 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1745 | static void efx_monitor(struct work_struct *data) |
1746 | { | |
1747 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1748 | monitor_work.work); | |
8ceee660 | 1749 | |
62776d03 BH |
1750 | netif_vdbg(efx, timer, efx->net_dev, |
1751 | "hardware monitor executing on CPU %d\n", | |
1752 | raw_smp_processor_id()); | |
ef2b90ee | 1753 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1754 | |
8ceee660 BH |
1755 | /* If the mac_lock is already held then it is likely a port |
1756 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1757 | * most of the work of monitor() anyway. */ |
1758 | if (mutex_trylock(&efx->mac_lock)) { | |
1759 | if (efx->port_enabled) | |
1760 | efx->type->monitor(efx); | |
1761 | mutex_unlock(&efx->mac_lock); | |
1762 | } | |
8ceee660 | 1763 | |
8ceee660 BH |
1764 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1765 | efx_monitor_interval); | |
1766 | } | |
1767 | ||
1768 | /************************************************************************** | |
1769 | * | |
1770 | * ioctls | |
1771 | * | |
1772 | *************************************************************************/ | |
1773 | ||
1774 | /* Net device ioctl | |
1775 | * Context: process, rtnl_lock() held. | |
1776 | */ | |
1777 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1778 | { | |
767e468c | 1779 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1780 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 | 1781 | |
7c236c43 SH |
1782 | if (cmd == SIOCSHWTSTAMP) |
1783 | return efx_ptp_ioctl(efx, ifr, cmd); | |
1784 | ||
68e7f45e BH |
1785 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1786 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1787 | (data->phy_id & 0xfc00) == 0x0400) | |
1788 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1789 | ||
1790 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1791 | } |
1792 | ||
1793 | /************************************************************************** | |
1794 | * | |
1795 | * NAPI interface | |
1796 | * | |
1797 | **************************************************************************/ | |
1798 | ||
7f967c01 BH |
1799 | static void efx_init_napi_channel(struct efx_channel *channel) |
1800 | { | |
1801 | struct efx_nic *efx = channel->efx; | |
1802 | ||
1803 | channel->napi_dev = efx->net_dev; | |
1804 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
1805 | efx_poll, napi_weight); | |
1806 | } | |
1807 | ||
e8f14992 | 1808 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1809 | { |
1810 | struct efx_channel *channel; | |
8ceee660 | 1811 | |
7f967c01 BH |
1812 | efx_for_each_channel(channel, efx) |
1813 | efx_init_napi_channel(channel); | |
e8f14992 BH |
1814 | } |
1815 | ||
1816 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1817 | { | |
1818 | if (channel->napi_dev) | |
1819 | netif_napi_del(&channel->napi_str); | |
1820 | channel->napi_dev = NULL; | |
8ceee660 BH |
1821 | } |
1822 | ||
1823 | static void efx_fini_napi(struct efx_nic *efx) | |
1824 | { | |
1825 | struct efx_channel *channel; | |
1826 | ||
e8f14992 BH |
1827 | efx_for_each_channel(channel, efx) |
1828 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
1829 | } |
1830 | ||
1831 | /************************************************************************** | |
1832 | * | |
1833 | * Kernel netpoll interface | |
1834 | * | |
1835 | *************************************************************************/ | |
1836 | ||
1837 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1838 | ||
1839 | /* Although in the common case interrupts will be disabled, this is not | |
1840 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1841 | * so no locking is required. | |
1842 | */ | |
1843 | static void efx_netpoll(struct net_device *net_dev) | |
1844 | { | |
767e468c | 1845 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1846 | struct efx_channel *channel; |
1847 | ||
64ee3120 | 1848 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1849 | efx_schedule_channel(channel); |
1850 | } | |
1851 | ||
1852 | #endif | |
1853 | ||
1854 | /************************************************************************** | |
1855 | * | |
1856 | * Kernel net device interface | |
1857 | * | |
1858 | *************************************************************************/ | |
1859 | ||
1860 | /* Context: process, rtnl_lock() held. */ | |
1861 | static int efx_net_open(struct net_device *net_dev) | |
1862 | { | |
767e468c | 1863 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 BH |
1864 | int rc; |
1865 | ||
62776d03 BH |
1866 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1867 | raw_smp_processor_id()); | |
8ceee660 | 1868 | |
8b7325b4 BH |
1869 | rc = efx_check_disabled(efx); |
1870 | if (rc) | |
1871 | return rc; | |
f8b87c17 BH |
1872 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1873 | return -EBUSY; | |
8880f4ec BH |
1874 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1875 | return -EIO; | |
f8b87c17 | 1876 | |
78c1f0a0 SH |
1877 | /* Notify the kernel of the link state polled during driver load, |
1878 | * before the monitor starts running */ | |
1879 | efx_link_status_changed(efx); | |
1880 | ||
8ceee660 | 1881 | efx_start_all(efx); |
dd40781e | 1882 | efx_selftest_async_start(efx); |
8ceee660 BH |
1883 | return 0; |
1884 | } | |
1885 | ||
1886 | /* Context: process, rtnl_lock() held. | |
1887 | * Note that the kernel will ignore our return code; this method | |
1888 | * should really be a void. | |
1889 | */ | |
1890 | static int efx_net_stop(struct net_device *net_dev) | |
1891 | { | |
767e468c | 1892 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1893 | |
62776d03 BH |
1894 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1895 | raw_smp_processor_id()); | |
8ceee660 | 1896 | |
8b7325b4 BH |
1897 | /* Stop the device and flush all the channels */ |
1898 | efx_stop_all(efx); | |
8ceee660 BH |
1899 | |
1900 | return 0; | |
1901 | } | |
1902 | ||
5b9e207c | 1903 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
2aa9ef11 BH |
1904 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, |
1905 | struct rtnl_link_stats64 *stats) | |
8ceee660 | 1906 | { |
767e468c | 1907 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1908 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
8ceee660 | 1909 | |
55edc6e6 | 1910 | spin_lock_bh(&efx->stats_lock); |
1cb34522 | 1911 | |
ef2b90ee | 1912 | efx->type->update_stats(efx); |
8ceee660 BH |
1913 | |
1914 | stats->rx_packets = mac_stats->rx_packets; | |
1915 | stats->tx_packets = mac_stats->tx_packets; | |
1916 | stats->rx_bytes = mac_stats->rx_bytes; | |
1917 | stats->tx_bytes = mac_stats->tx_bytes; | |
80485d34 | 1918 | stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; |
8ceee660 BH |
1919 | stats->multicast = mac_stats->rx_multicast; |
1920 | stats->collisions = mac_stats->tx_collision; | |
1921 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1922 | mac_stats->rx_length_error); | |
8ceee660 BH |
1923 | stats->rx_crc_errors = mac_stats->rx_bad; |
1924 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1925 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1926 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1927 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1928 | ||
1929 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1930 | stats->rx_crc_errors + |
1931 | stats->rx_frame_errors + | |
8ceee660 BH |
1932 | mac_stats->rx_symbol_error); |
1933 | stats->tx_errors = (stats->tx_window_errors + | |
1934 | mac_stats->tx_bad); | |
1935 | ||
1cb34522 BH |
1936 | spin_unlock_bh(&efx->stats_lock); |
1937 | ||
8ceee660 BH |
1938 | return stats; |
1939 | } | |
1940 | ||
1941 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1942 | static void efx_watchdog(struct net_device *net_dev) | |
1943 | { | |
767e468c | 1944 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1945 | |
62776d03 BH |
1946 | netif_err(efx, tx_err, efx->net_dev, |
1947 | "TX stuck with port_enabled=%d: resetting channels\n", | |
1948 | efx->port_enabled); | |
8ceee660 | 1949 | |
739bb23d | 1950 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1951 | } |
1952 | ||
1953 | ||
1954 | /* Context: process, rtnl_lock() held. */ | |
1955 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1956 | { | |
767e468c | 1957 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 | 1958 | int rc; |
8ceee660 | 1959 | |
8b7325b4 BH |
1960 | rc = efx_check_disabled(efx); |
1961 | if (rc) | |
1962 | return rc; | |
8ceee660 BH |
1963 | if (new_mtu > EFX_MAX_MTU) |
1964 | return -EINVAL; | |
1965 | ||
1966 | efx_stop_all(efx); | |
1967 | ||
62776d03 | 1968 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 | 1969 | |
d3245b28 | 1970 | mutex_lock(&efx->mac_lock); |
8ceee660 | 1971 | net_dev->mtu = new_mtu; |
710b208d | 1972 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1973 | mutex_unlock(&efx->mac_lock); |
1974 | ||
8ceee660 | 1975 | efx_start_all(efx); |
6c8eef4a | 1976 | return 0; |
8ceee660 BH |
1977 | } |
1978 | ||
1979 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1980 | { | |
767e468c | 1981 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1982 | struct sockaddr *addr = data; |
1983 | char *new_addr = addr->sa_data; | |
1984 | ||
8ceee660 | 1985 | if (!is_valid_ether_addr(new_addr)) { |
62776d03 BH |
1986 | netif_err(efx, drv, efx->net_dev, |
1987 | "invalid ethernet MAC address requested: %pM\n", | |
1988 | new_addr); | |
504f9b5a | 1989 | return -EADDRNOTAVAIL; |
8ceee660 BH |
1990 | } |
1991 | ||
1992 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
cd2d5b52 | 1993 | efx_sriov_mac_address_changed(efx); |
8ceee660 BH |
1994 | |
1995 | /* Reconfigure the MAC */ | |
d3245b28 | 1996 | mutex_lock(&efx->mac_lock); |
710b208d | 1997 | efx->type->reconfigure_mac(efx); |
d3245b28 | 1998 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
1999 | |
2000 | return 0; | |
2001 | } | |
2002 | ||
a816f75a | 2003 | /* Context: netif_addr_lock held, BHs disabled. */ |
0fca8c97 | 2004 | static void efx_set_rx_mode(struct net_device *net_dev) |
8ceee660 | 2005 | { |
767e468c | 2006 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 2007 | struct netdev_hw_addr *ha; |
8ceee660 | 2008 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
2009 | u32 crc; |
2010 | int bit; | |
8ceee660 | 2011 | |
8be4f3e6 | 2012 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
2013 | |
2014 | /* Build multicast hash table */ | |
8be4f3e6 | 2015 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
2016 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
2017 | } else { | |
2018 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
2019 | netdev_for_each_mc_addr(ha, net_dev) { |
2020 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 | 2021 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
32766ec8 | 2022 | __set_bit_le(bit, mc_hash); |
8ceee660 | 2023 | } |
8ceee660 | 2024 | |
8be4f3e6 BH |
2025 | /* Broadcast packets go through the multicast hash filter. |
2026 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
2027 | * so we always add bit 0xff to the mask. | |
2028 | */ | |
32766ec8 | 2029 | __set_bit_le(0xff, mc_hash); |
8be4f3e6 | 2030 | } |
a816f75a | 2031 | |
8be4f3e6 BH |
2032 | if (efx->port_enabled) |
2033 | queue_work(efx->workqueue, &efx->mac_work); | |
2034 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
2035 | } |
2036 | ||
c8f44aff | 2037 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
2038 | { |
2039 | struct efx_nic *efx = netdev_priv(net_dev); | |
2040 | ||
2041 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
2042 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
2043 | efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); | |
2044 | ||
2045 | return 0; | |
2046 | } | |
2047 | ||
c3ecb9f3 SH |
2048 | static const struct net_device_ops efx_netdev_ops = { |
2049 | .ndo_open = efx_net_open, | |
2050 | .ndo_stop = efx_net_stop, | |
4472702e | 2051 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
2052 | .ndo_tx_timeout = efx_watchdog, |
2053 | .ndo_start_xmit = efx_hard_start_xmit, | |
2054 | .ndo_validate_addr = eth_validate_addr, | |
2055 | .ndo_do_ioctl = efx_ioctl, | |
2056 | .ndo_change_mtu = efx_change_mtu, | |
2057 | .ndo_set_mac_address = efx_set_mac_address, | |
0fca8c97 | 2058 | .ndo_set_rx_mode = efx_set_rx_mode, |
abfe9039 | 2059 | .ndo_set_features = efx_set_features, |
cd2d5b52 BH |
2060 | #ifdef CONFIG_SFC_SRIOV |
2061 | .ndo_set_vf_mac = efx_sriov_set_vf_mac, | |
2062 | .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, | |
2063 | .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, | |
2064 | .ndo_get_vf_config = efx_sriov_get_vf_config, | |
2065 | #endif | |
c3ecb9f3 SH |
2066 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2067 | .ndo_poll_controller = efx_netpoll, | |
2068 | #endif | |
94b274bf | 2069 | .ndo_setup_tc = efx_setup_tc, |
64d8ad6d BH |
2070 | #ifdef CONFIG_RFS_ACCEL |
2071 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2072 | #endif | |
c3ecb9f3 SH |
2073 | }; |
2074 | ||
7dde596e BH |
2075 | static void efx_update_name(struct efx_nic *efx) |
2076 | { | |
2077 | strcpy(efx->name, efx->net_dev->name); | |
2078 | efx_mtd_rename(efx); | |
2079 | efx_set_channel_names(efx); | |
2080 | } | |
2081 | ||
8ceee660 BH |
2082 | static int efx_netdev_event(struct notifier_block *this, |
2083 | unsigned long event, void *ptr) | |
2084 | { | |
d3208b5e | 2085 | struct net_device *net_dev = ptr; |
8ceee660 | 2086 | |
7dde596e BH |
2087 | if (net_dev->netdev_ops == &efx_netdev_ops && |
2088 | event == NETDEV_CHANGENAME) | |
2089 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
2090 | |
2091 | return NOTIFY_DONE; | |
2092 | } | |
2093 | ||
2094 | static struct notifier_block efx_netdev_notifier = { | |
2095 | .notifier_call = efx_netdev_event, | |
2096 | }; | |
2097 | ||
06d5e193 BH |
2098 | static ssize_t |
2099 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
2100 | { | |
2101 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2102 | return sprintf(buf, "%d\n", efx->phy_type); | |
2103 | } | |
2104 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
2105 | ||
8ceee660 BH |
2106 | static int efx_register_netdev(struct efx_nic *efx) |
2107 | { | |
2108 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 2109 | struct efx_channel *channel; |
8ceee660 BH |
2110 | int rc; |
2111 | ||
2112 | net_dev->watchdog_timeo = 5 * HZ; | |
2113 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 2114 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 | 2115 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
7e6d06f0 | 2116 | net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; |
8ceee660 | 2117 | |
7dde596e | 2118 | rtnl_lock(); |
aed0628d | 2119 | |
7153f623 BH |
2120 | /* Enable resets to be scheduled and check whether any were |
2121 | * already requested. If so, the NIC is probably hosed so we | |
2122 | * abort. | |
2123 | */ | |
2124 | efx->state = STATE_READY; | |
2125 | smp_mb(); /* ensure we change state before checking reset_pending */ | |
2126 | if (efx->reset_pending) { | |
2127 | netif_err(efx, probe, efx->net_dev, | |
2128 | "aborting probe due to scheduled reset\n"); | |
2129 | rc = -EIO; | |
2130 | goto fail_locked; | |
2131 | } | |
2132 | ||
aed0628d BH |
2133 | rc = dev_alloc_name(net_dev, net_dev->name); |
2134 | if (rc < 0) | |
2135 | goto fail_locked; | |
7dde596e | 2136 | efx_update_name(efx); |
aed0628d | 2137 | |
8f8b3d51 BH |
2138 | /* Always start with carrier off; PHY events will detect the link */ |
2139 | netif_carrier_off(net_dev); | |
2140 | ||
aed0628d BH |
2141 | rc = register_netdevice(net_dev); |
2142 | if (rc) | |
2143 | goto fail_locked; | |
2144 | ||
c04bfc6b BH |
2145 | efx_for_each_channel(channel, efx) { |
2146 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
2147 | efx_for_each_channel_tx_queue(tx_queue, channel) |
2148 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
2149 | } |
2150 | ||
7dde596e | 2151 | rtnl_unlock(); |
8ceee660 | 2152 | |
06d5e193 BH |
2153 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
2154 | if (rc) { | |
62776d03 BH |
2155 | netif_err(efx, drv, efx->net_dev, |
2156 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
2157 | goto fail_registered; |
2158 | } | |
2159 | ||
8ceee660 | 2160 | return 0; |
06d5e193 | 2161 | |
7153f623 BH |
2162 | fail_registered: |
2163 | rtnl_lock(); | |
2164 | unregister_netdevice(net_dev); | |
aed0628d | 2165 | fail_locked: |
7153f623 | 2166 | efx->state = STATE_UNINIT; |
aed0628d | 2167 | rtnl_unlock(); |
62776d03 | 2168 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d | 2169 | return rc; |
8ceee660 BH |
2170 | } |
2171 | ||
2172 | static void efx_unregister_netdev(struct efx_nic *efx) | |
2173 | { | |
f7d12cdc | 2174 | struct efx_channel *channel; |
8ceee660 BH |
2175 | struct efx_tx_queue *tx_queue; |
2176 | ||
2177 | if (!efx->net_dev) | |
2178 | return; | |
2179 | ||
767e468c | 2180 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
2181 | |
2182 | /* Free up any skbs still remaining. This has to happen before | |
2183 | * we try to unregister the netdev as running their destructors | |
2184 | * may be needed to get the device ref. count to 0. */ | |
f7d12cdc BH |
2185 | efx_for_each_channel(channel, efx) { |
2186 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
2187 | efx_release_tx_buffers(tx_queue); | |
2188 | } | |
8ceee660 | 2189 | |
73ba7b68 BH |
2190 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
2191 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
7153f623 BH |
2192 | |
2193 | rtnl_lock(); | |
2194 | unregister_netdevice(efx->net_dev); | |
2195 | efx->state = STATE_UNINIT; | |
2196 | rtnl_unlock(); | |
8ceee660 BH |
2197 | } |
2198 | ||
2199 | /************************************************************************** | |
2200 | * | |
2201 | * Device reset and suspend | |
2202 | * | |
2203 | **************************************************************************/ | |
2204 | ||
2467ca46 BH |
2205 | /* Tears down the entire software state and most of the hardware state |
2206 | * before reset. */ | |
d3245b28 | 2207 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2208 | { |
8ceee660 BH |
2209 | EFX_ASSERT_RESET_SERIALISED(efx); |
2210 | ||
2467ca46 | 2211 | efx_stop_all(efx); |
7f967c01 | 2212 | efx_stop_interrupts(efx, false); |
5642ceef BH |
2213 | |
2214 | mutex_lock(&efx->mac_lock); | |
4b988280 SH |
2215 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2216 | efx->phy_op->fini(efx); | |
ef2b90ee | 2217 | efx->type->fini(efx); |
8ceee660 BH |
2218 | } |
2219 | ||
2467ca46 BH |
2220 | /* This function will always ensure that the locks acquired in |
2221 | * efx_reset_down() are released. A failure return code indicates | |
2222 | * that we were unable to reinitialise the hardware, and the | |
2223 | * driver should be disabled. If ok is false, then the rx and tx | |
2224 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2225 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2226 | { |
2227 | int rc; | |
2228 | ||
2467ca46 | 2229 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2230 | |
ef2b90ee | 2231 | rc = efx->type->init(efx); |
8ceee660 | 2232 | if (rc) { |
62776d03 | 2233 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2234 | goto fail; |
8ceee660 BH |
2235 | } |
2236 | ||
eb9f6744 BH |
2237 | if (!ok) |
2238 | goto fail; | |
2239 | ||
4b988280 | 2240 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2241 | rc = efx->phy_op->init(efx); |
2242 | if (rc) | |
2243 | goto fail; | |
2244 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2245 | netif_err(efx, drv, efx->net_dev, |
2246 | "could not restore PHY settings\n"); | |
4b988280 SH |
2247 | } |
2248 | ||
710b208d | 2249 | efx->type->reconfigure_mac(efx); |
8ceee660 | 2250 | |
7f967c01 | 2251 | efx_start_interrupts(efx, false); |
64eebcfd | 2252 | efx_restore_filters(efx); |
cd2d5b52 | 2253 | efx_sriov_reset(efx); |
eb9f6744 | 2254 | |
eb9f6744 BH |
2255 | mutex_unlock(&efx->mac_lock); |
2256 | ||
2257 | efx_start_all(efx); | |
2258 | ||
2259 | return 0; | |
2260 | ||
2261 | fail: | |
2262 | efx->port_initialized = false; | |
2467ca46 BH |
2263 | |
2264 | mutex_unlock(&efx->mac_lock); | |
2265 | ||
8ceee660 BH |
2266 | return rc; |
2267 | } | |
2268 | ||
eb9f6744 BH |
2269 | /* Reset the NIC using the specified method. Note that the reset may |
2270 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2271 | * |
eb9f6744 | 2272 | * Caller must hold the rtnl_lock. |
8ceee660 | 2273 | */ |
eb9f6744 | 2274 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2275 | { |
eb9f6744 BH |
2276 | int rc, rc2; |
2277 | bool disabled; | |
8ceee660 | 2278 | |
62776d03 BH |
2279 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2280 | RESET_TYPE(method)); | |
8ceee660 | 2281 | |
c2f3b8e3 | 2282 | efx_device_detach_sync(efx); |
d3245b28 | 2283 | efx_reset_down(efx, method); |
8ceee660 | 2284 | |
ef2b90ee | 2285 | rc = efx->type->reset(efx, method); |
8ceee660 | 2286 | if (rc) { |
62776d03 | 2287 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2288 | goto out; |
8ceee660 BH |
2289 | } |
2290 | ||
a7d529ae BH |
2291 | /* Clear flags for the scopes we covered. We assume the NIC and |
2292 | * driver are now quiescent so that there is no race here. | |
2293 | */ | |
2294 | efx->reset_pending &= -(1 << (method + 1)); | |
8ceee660 BH |
2295 | |
2296 | /* Reinitialise bus-mastering, which may have been turned off before | |
2297 | * the reset was scheduled. This is still appropriate, even in the | |
2298 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2299 | * can respond to requests. */ | |
2300 | pci_set_master(efx->pci_dev); | |
2301 | ||
eb9f6744 | 2302 | out: |
8ceee660 | 2303 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
2304 | disabled = rc || method == RESET_TYPE_DISABLE; |
2305 | rc2 = efx_reset_up(efx, method, !disabled); | |
2306 | if (rc2) { | |
2307 | disabled = true; | |
2308 | if (!rc) | |
2309 | rc = rc2; | |
8ceee660 BH |
2310 | } |
2311 | ||
eb9f6744 | 2312 | if (disabled) { |
f49a4589 | 2313 | dev_close(efx->net_dev); |
62776d03 | 2314 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2315 | efx->state = STATE_DISABLED; |
f4bd954e | 2316 | } else { |
62776d03 | 2317 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2318 | netif_device_attach(efx->net_dev); |
f4bd954e | 2319 | } |
8ceee660 BH |
2320 | return rc; |
2321 | } | |
2322 | ||
2323 | /* The worker thread exists so that code that cannot sleep can | |
2324 | * schedule a reset for later. | |
2325 | */ | |
2326 | static void efx_reset_work(struct work_struct *data) | |
2327 | { | |
eb9f6744 | 2328 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
a7d529ae | 2329 | unsigned long pending = ACCESS_ONCE(efx->reset_pending); |
8ceee660 | 2330 | |
a7d529ae | 2331 | if (!pending) |
319ba649 SH |
2332 | return; |
2333 | ||
eb9f6744 | 2334 | rtnl_lock(); |
7153f623 BH |
2335 | |
2336 | /* We checked the state in efx_schedule_reset() but it may | |
2337 | * have changed by now. Now that we have the RTNL lock, | |
2338 | * it cannot change again. | |
2339 | */ | |
2340 | if (efx->state == STATE_READY) | |
2341 | (void)efx_reset(efx, fls(pending) - 1); | |
2342 | ||
eb9f6744 | 2343 | rtnl_unlock(); |
8ceee660 BH |
2344 | } |
2345 | ||
2346 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2347 | { | |
2348 | enum reset_type method; | |
2349 | ||
8ceee660 BH |
2350 | switch (type) { |
2351 | case RESET_TYPE_INVISIBLE: | |
2352 | case RESET_TYPE_ALL: | |
2353 | case RESET_TYPE_WORLD: | |
2354 | case RESET_TYPE_DISABLE: | |
2355 | method = type; | |
0e2a9c7c BH |
2356 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2357 | RESET_TYPE(method)); | |
8ceee660 | 2358 | break; |
8ceee660 | 2359 | default: |
0e2a9c7c | 2360 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2361 | netif_dbg(efx, drv, efx->net_dev, |
2362 | "scheduling %s reset for %s\n", | |
2363 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2364 | break; |
2365 | } | |
8ceee660 | 2366 | |
a7d529ae | 2367 | set_bit(method, &efx->reset_pending); |
7153f623 BH |
2368 | smp_mb(); /* ensure we change reset_pending before checking state */ |
2369 | ||
2370 | /* If we're not READY then just leave the flags set as the cue | |
2371 | * to abort probing or reschedule the reset later. | |
2372 | */ | |
2373 | if (ACCESS_ONCE(efx->state) != STATE_READY) | |
2374 | return; | |
8ceee660 | 2375 | |
8880f4ec BH |
2376 | /* efx_process_channel() will no longer read events once a |
2377 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2378 | efx_mcdi_mode_poll(efx); | |
2379 | ||
1ab00629 | 2380 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2381 | } |
2382 | ||
2383 | /************************************************************************** | |
2384 | * | |
2385 | * List of NICs we support | |
2386 | * | |
2387 | **************************************************************************/ | |
2388 | ||
2389 | /* PCI device ID table */ | |
a3aa1884 | 2390 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
937383a5 BH |
2391 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2392 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2393 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2394 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2395 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2396 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2397 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2398 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2399 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2400 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8ceee660 BH |
2401 | {0} /* end of list */ |
2402 | }; | |
2403 | ||
2404 | /************************************************************************** | |
2405 | * | |
3759433d | 2406 | * Dummy PHY/MAC operations |
8ceee660 | 2407 | * |
01aad7b6 | 2408 | * Can be used for some unimplemented operations |
8ceee660 BH |
2409 | * Needed so all function pointers are valid and do not have to be tested |
2410 | * before use | |
2411 | * | |
2412 | **************************************************************************/ | |
2413 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2414 | { | |
2415 | return 0; | |
2416 | } | |
2417 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2418 | |
2419 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2420 | { |
2421 | return false; | |
2422 | } | |
8ceee660 | 2423 | |
6c8c2513 | 2424 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2425 | .init = efx_port_dummy_op_int, |
d3245b28 | 2426 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2427 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2428 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2429 | }; |
2430 | ||
8ceee660 BH |
2431 | /************************************************************************** |
2432 | * | |
2433 | * Data housekeeping | |
2434 | * | |
2435 | **************************************************************************/ | |
2436 | ||
2437 | /* This zeroes out and then fills in the invariants in a struct | |
2438 | * efx_nic (including all sub-structures). | |
2439 | */ | |
adeb15aa | 2440 | static int efx_init_struct(struct efx_nic *efx, |
8ceee660 BH |
2441 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2442 | { | |
4642610c | 2443 | int i; |
8ceee660 BH |
2444 | |
2445 | /* Initialise common structures */ | |
8ceee660 | 2446 | spin_lock_init(&efx->biu_lock); |
76884835 BH |
2447 | #ifdef CONFIG_SFC_MTD |
2448 | INIT_LIST_HEAD(&efx->mtd_list); | |
2449 | #endif | |
8ceee660 BH |
2450 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2451 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
dd40781e | 2452 | INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); |
8ceee660 | 2453 | efx->pci_dev = pci_dev; |
62776d03 | 2454 | efx->msg_enable = debug; |
f16aeea0 | 2455 | efx->state = STATE_UNINIT; |
8ceee660 | 2456 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2457 | |
2458 | efx->net_dev = net_dev; | |
8ceee660 BH |
2459 | spin_lock_init(&efx->stats_lock); |
2460 | mutex_init(&efx->mac_lock); | |
2461 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2462 | efx->mdio.dev = net_dev; |
766ca0fa | 2463 | INIT_WORK(&efx->mac_work, efx_mac_work); |
9f2cb71c | 2464 | init_waitqueue_head(&efx->flush_wq); |
8ceee660 BH |
2465 | |
2466 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2467 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2468 | if (!efx->channel[i]) | |
2469 | goto fail; | |
8ceee660 BH |
2470 | } |
2471 | ||
8ceee660 BH |
2472 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2473 | ||
2474 | /* Higher numbered interrupt modes are less capable! */ | |
2475 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2476 | interrupt_mode); | |
2477 | ||
6977dc63 BH |
2478 | /* Would be good to use the net_dev name, but we're too early */ |
2479 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2480 | pci_name(pci_dev)); | |
2481 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2482 | if (!efx->workqueue) |
4642610c | 2483 | goto fail; |
8d9853d9 | 2484 | |
8ceee660 | 2485 | return 0; |
4642610c BH |
2486 | |
2487 | fail: | |
2488 | efx_fini_struct(efx); | |
2489 | return -ENOMEM; | |
8ceee660 BH |
2490 | } |
2491 | ||
2492 | static void efx_fini_struct(struct efx_nic *efx) | |
2493 | { | |
8313aca3 BH |
2494 | int i; |
2495 | ||
2496 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2497 | kfree(efx->channel[i]); | |
2498 | ||
8ceee660 BH |
2499 | if (efx->workqueue) { |
2500 | destroy_workqueue(efx->workqueue); | |
2501 | efx->workqueue = NULL; | |
2502 | } | |
2503 | } | |
2504 | ||
2505 | /************************************************************************** | |
2506 | * | |
2507 | * PCI interface | |
2508 | * | |
2509 | **************************************************************************/ | |
2510 | ||
2511 | /* Main body of final NIC shutdown code | |
2512 | * This is called only at module unload (or hotplug removal). | |
2513 | */ | |
2514 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2515 | { | |
7153f623 BH |
2516 | /* Flush reset_work. It can no longer be scheduled since we |
2517 | * are not READY. | |
2518 | */ | |
2519 | BUG_ON(efx->state == STATE_READY); | |
2520 | cancel_work_sync(&efx->reset_work); | |
2521 | ||
64d8ad6d BH |
2522 | #ifdef CONFIG_RFS_ACCEL |
2523 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
2524 | efx->net_dev->rx_cpu_rmap = NULL; | |
2525 | #endif | |
7f967c01 | 2526 | efx_stop_interrupts(efx, false); |
152b6a62 | 2527 | efx_nic_fini_interrupt(efx); |
8ceee660 | 2528 | efx_fini_port(efx); |
ef2b90ee | 2529 | efx->type->fini(efx); |
8ceee660 BH |
2530 | efx_fini_napi(efx); |
2531 | efx_remove_all(efx); | |
2532 | } | |
2533 | ||
2534 | /* Final NIC shutdown | |
2535 | * This is called only at module unload (or hotplug removal). | |
2536 | */ | |
2537 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2538 | { | |
2539 | struct efx_nic *efx; | |
2540 | ||
2541 | efx = pci_get_drvdata(pci_dev); | |
2542 | if (!efx) | |
2543 | return; | |
2544 | ||
2545 | /* Mark the NIC as fini, then stop the interface */ | |
2546 | rtnl_lock(); | |
8ceee660 | 2547 | dev_close(efx->net_dev); |
5642ceef | 2548 | efx_stop_interrupts(efx, false); |
8ceee660 BH |
2549 | rtnl_unlock(); |
2550 | ||
cd2d5b52 | 2551 | efx_sriov_fini(efx); |
8ceee660 BH |
2552 | efx_unregister_netdev(efx); |
2553 | ||
7dde596e BH |
2554 | efx_mtd_remove(efx); |
2555 | ||
8ceee660 BH |
2556 | efx_pci_remove_main(efx); |
2557 | ||
8ceee660 | 2558 | efx_fini_io(efx); |
62776d03 | 2559 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 | 2560 | |
8ceee660 | 2561 | efx_fini_struct(efx); |
3de4e301 | 2562 | pci_set_drvdata(pci_dev, NULL); |
8ceee660 BH |
2563 | free_netdev(efx->net_dev); |
2564 | }; | |
2565 | ||
460eeaa0 BH |
2566 | /* NIC VPD information |
2567 | * Called during probe to display the part number of the | |
2568 | * installed NIC. VPD is potentially very large but this should | |
2569 | * always appear within the first 512 bytes. | |
2570 | */ | |
2571 | #define SFC_VPD_LEN 512 | |
2572 | static void efx_print_product_vpd(struct efx_nic *efx) | |
2573 | { | |
2574 | struct pci_dev *dev = efx->pci_dev; | |
2575 | char vpd_data[SFC_VPD_LEN]; | |
2576 | ssize_t vpd_size; | |
2577 | int i, j; | |
2578 | ||
2579 | /* Get the vpd data from the device */ | |
2580 | vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); | |
2581 | if (vpd_size <= 0) { | |
2582 | netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); | |
2583 | return; | |
2584 | } | |
2585 | ||
2586 | /* Get the Read only section */ | |
2587 | i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); | |
2588 | if (i < 0) { | |
2589 | netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); | |
2590 | return; | |
2591 | } | |
2592 | ||
2593 | j = pci_vpd_lrdt_size(&vpd_data[i]); | |
2594 | i += PCI_VPD_LRDT_TAG_SIZE; | |
2595 | if (i + j > vpd_size) | |
2596 | j = vpd_size - i; | |
2597 | ||
2598 | /* Get the Part number */ | |
2599 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); | |
2600 | if (i < 0) { | |
2601 | netif_err(efx, drv, efx->net_dev, "Part number not found\n"); | |
2602 | return; | |
2603 | } | |
2604 | ||
2605 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
2606 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
2607 | if (i + j > vpd_size) { | |
2608 | netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); | |
2609 | return; | |
2610 | } | |
2611 | ||
2612 | netif_info(efx, drv, efx->net_dev, | |
2613 | "Part Number : %.*s\n", j, &vpd_data[i]); | |
2614 | } | |
2615 | ||
2616 | ||
8ceee660 BH |
2617 | /* Main body of NIC initialisation |
2618 | * This is called at module load (or hotplug insertion, theoretically). | |
2619 | */ | |
2620 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2621 | { | |
2622 | int rc; | |
2623 | ||
2624 | /* Do start-of-day initialisation */ | |
2625 | rc = efx_probe_all(efx); | |
2626 | if (rc) | |
2627 | goto fail1; | |
2628 | ||
e8f14992 | 2629 | efx_init_napi(efx); |
8ceee660 | 2630 | |
ef2b90ee | 2631 | rc = efx->type->init(efx); |
8ceee660 | 2632 | if (rc) { |
62776d03 BH |
2633 | netif_err(efx, probe, efx->net_dev, |
2634 | "failed to initialise NIC\n"); | |
278c0621 | 2635 | goto fail3; |
8ceee660 BH |
2636 | } |
2637 | ||
2638 | rc = efx_init_port(efx); | |
2639 | if (rc) { | |
62776d03 BH |
2640 | netif_err(efx, probe, efx->net_dev, |
2641 | "failed to initialise port\n"); | |
278c0621 | 2642 | goto fail4; |
8ceee660 BH |
2643 | } |
2644 | ||
152b6a62 | 2645 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2646 | if (rc) |
278c0621 | 2647 | goto fail5; |
7f967c01 | 2648 | efx_start_interrupts(efx, false); |
8ceee660 BH |
2649 | |
2650 | return 0; | |
2651 | ||
278c0621 | 2652 | fail5: |
8ceee660 | 2653 | efx_fini_port(efx); |
8ceee660 | 2654 | fail4: |
ef2b90ee | 2655 | efx->type->fini(efx); |
8ceee660 BH |
2656 | fail3: |
2657 | efx_fini_napi(efx); | |
8ceee660 BH |
2658 | efx_remove_all(efx); |
2659 | fail1: | |
2660 | return rc; | |
2661 | } | |
2662 | ||
2663 | /* NIC initialisation | |
2664 | * | |
2665 | * This is called at module load (or hotplug insertion, | |
73ba7b68 | 2666 | * theoretically). It sets up PCI mappings, resets the NIC, |
8ceee660 BH |
2667 | * sets up and registers the network devices with the kernel and hooks |
2668 | * the interrupt service routine. It does not prepare the device for | |
2669 | * transmission; this is left to the first time one of the network | |
2670 | * interfaces is brought up (i.e. efx_net_open). | |
2671 | */ | |
87d1fc11 | 2672 | static int efx_pci_probe(struct pci_dev *pci_dev, |
8ceee660 BH |
2673 | const struct pci_device_id *entry) |
2674 | { | |
8ceee660 BH |
2675 | struct net_device *net_dev; |
2676 | struct efx_nic *efx; | |
fadac6aa | 2677 | int rc; |
8ceee660 BH |
2678 | |
2679 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2680 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2681 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2682 | if (!net_dev) |
2683 | return -ENOMEM; | |
adeb15aa BH |
2684 | efx = netdev_priv(net_dev); |
2685 | efx->type = (const struct efx_nic_type *) entry->driver_data; | |
2686 | net_dev->features |= (efx->type->offload_features | NETIF_F_SG | | |
97bc5415 | 2687 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 2688 | NETIF_F_RXCSUM); |
adeb15aa | 2689 | if (efx->type->offload_features & NETIF_F_V6_CSUM) |
738a8f4b | 2690 | net_dev->features |= NETIF_F_TSO6; |
28506563 BH |
2691 | /* Mask for features that also apply to VLAN devices */ |
2692 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
2693 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
2694 | NETIF_F_RXCSUM); | |
2695 | /* All offloads can be toggled */ | |
2696 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
8ceee660 | 2697 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2698 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
adeb15aa | 2699 | rc = efx_init_struct(efx, pci_dev, net_dev); |
8ceee660 BH |
2700 | if (rc) |
2701 | goto fail1; | |
2702 | ||
62776d03 | 2703 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 2704 | "Solarflare NIC detected\n"); |
8ceee660 | 2705 | |
460eeaa0 BH |
2706 | efx_print_product_vpd(efx); |
2707 | ||
8ceee660 BH |
2708 | /* Set up basic I/O (BAR mappings etc) */ |
2709 | rc = efx_init_io(efx); | |
2710 | if (rc) | |
2711 | goto fail2; | |
2712 | ||
fadac6aa | 2713 | rc = efx_pci_probe_main(efx); |
fadac6aa BH |
2714 | if (rc) |
2715 | goto fail3; | |
8ceee660 | 2716 | |
8ceee660 BH |
2717 | rc = efx_register_netdev(efx); |
2718 | if (rc) | |
fadac6aa | 2719 | goto fail4; |
8ceee660 | 2720 | |
cd2d5b52 BH |
2721 | rc = efx_sriov_init(efx); |
2722 | if (rc) | |
2723 | netif_err(efx, probe, efx->net_dev, | |
2724 | "SR-IOV can't be enabled rc %d\n", rc); | |
2725 | ||
62776d03 | 2726 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 | 2727 | |
7c43161c | 2728 | /* Try to create MTDs, but allow this to fail */ |
a5211bb5 | 2729 | rtnl_lock(); |
7c43161c | 2730 | rc = efx_mtd_probe(efx); |
a5211bb5 | 2731 | rtnl_unlock(); |
7c43161c BH |
2732 | if (rc) |
2733 | netif_warn(efx, probe, efx->net_dev, | |
2734 | "failed to create MTDs (%d)\n", rc); | |
2735 | ||
8ceee660 BH |
2736 | return 0; |
2737 | ||
8ceee660 | 2738 | fail4: |
fadac6aa | 2739 | efx_pci_remove_main(efx); |
8ceee660 BH |
2740 | fail3: |
2741 | efx_fini_io(efx); | |
2742 | fail2: | |
2743 | efx_fini_struct(efx); | |
2744 | fail1: | |
3de4e301 | 2745 | pci_set_drvdata(pci_dev, NULL); |
5e2a911c | 2746 | WARN_ON(rc > 0); |
62776d03 | 2747 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2748 | free_netdev(net_dev); |
2749 | return rc; | |
2750 | } | |
2751 | ||
89c758fa BH |
2752 | static int efx_pm_freeze(struct device *dev) |
2753 | { | |
2754 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2755 | ||
61da026d BH |
2756 | rtnl_lock(); |
2757 | ||
6032fb56 BH |
2758 | if (efx->state != STATE_DISABLED) { |
2759 | efx->state = STATE_UNINIT; | |
89c758fa | 2760 | |
c2f3b8e3 | 2761 | efx_device_detach_sync(efx); |
89c758fa | 2762 | |
6032fb56 BH |
2763 | efx_stop_all(efx); |
2764 | efx_stop_interrupts(efx, false); | |
2765 | } | |
89c758fa | 2766 | |
61da026d BH |
2767 | rtnl_unlock(); |
2768 | ||
89c758fa BH |
2769 | return 0; |
2770 | } | |
2771 | ||
2772 | static int efx_pm_thaw(struct device *dev) | |
2773 | { | |
2774 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2775 | ||
61da026d BH |
2776 | rtnl_lock(); |
2777 | ||
6032fb56 BH |
2778 | if (efx->state != STATE_DISABLED) { |
2779 | efx_start_interrupts(efx, false); | |
89c758fa | 2780 | |
6032fb56 BH |
2781 | mutex_lock(&efx->mac_lock); |
2782 | efx->phy_op->reconfigure(efx); | |
2783 | mutex_unlock(&efx->mac_lock); | |
89c758fa | 2784 | |
6032fb56 | 2785 | efx_start_all(efx); |
89c758fa | 2786 | |
6032fb56 | 2787 | netif_device_attach(efx->net_dev); |
89c758fa | 2788 | |
6032fb56 | 2789 | efx->state = STATE_READY; |
89c758fa | 2790 | |
6032fb56 BH |
2791 | efx->type->resume_wol(efx); |
2792 | } | |
89c758fa | 2793 | |
61da026d BH |
2794 | rtnl_unlock(); |
2795 | ||
319ba649 SH |
2796 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2797 | queue_work(reset_workqueue, &efx->reset_work); | |
2798 | ||
89c758fa BH |
2799 | return 0; |
2800 | } | |
2801 | ||
2802 | static int efx_pm_poweroff(struct device *dev) | |
2803 | { | |
2804 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2805 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2806 | ||
2807 | efx->type->fini(efx); | |
2808 | ||
a7d529ae | 2809 | efx->reset_pending = 0; |
89c758fa BH |
2810 | |
2811 | pci_save_state(pci_dev); | |
2812 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2813 | } | |
2814 | ||
2815 | /* Used for both resume and restore */ | |
2816 | static int efx_pm_resume(struct device *dev) | |
2817 | { | |
2818 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2819 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2820 | int rc; | |
2821 | ||
2822 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2823 | if (rc) | |
2824 | return rc; | |
2825 | pci_restore_state(pci_dev); | |
2826 | rc = pci_enable_device(pci_dev); | |
2827 | if (rc) | |
2828 | return rc; | |
2829 | pci_set_master(efx->pci_dev); | |
2830 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2831 | if (rc) | |
2832 | return rc; | |
2833 | rc = efx->type->init(efx); | |
2834 | if (rc) | |
2835 | return rc; | |
2836 | efx_pm_thaw(dev); | |
2837 | return 0; | |
2838 | } | |
2839 | ||
2840 | static int efx_pm_suspend(struct device *dev) | |
2841 | { | |
2842 | int rc; | |
2843 | ||
2844 | efx_pm_freeze(dev); | |
2845 | rc = efx_pm_poweroff(dev); | |
2846 | if (rc) | |
2847 | efx_pm_resume(dev); | |
2848 | return rc; | |
2849 | } | |
2850 | ||
18e83e4c | 2851 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
2852 | .suspend = efx_pm_suspend, |
2853 | .resume = efx_pm_resume, | |
2854 | .freeze = efx_pm_freeze, | |
2855 | .thaw = efx_pm_thaw, | |
2856 | .poweroff = efx_pm_poweroff, | |
2857 | .restore = efx_pm_resume, | |
2858 | }; | |
2859 | ||
8ceee660 | 2860 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 2861 | .name = KBUILD_MODNAME, |
8ceee660 BH |
2862 | .id_table = efx_pci_table, |
2863 | .probe = efx_pci_probe, | |
2864 | .remove = efx_pci_remove, | |
89c758fa | 2865 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2866 | }; |
2867 | ||
2868 | /************************************************************************** | |
2869 | * | |
2870 | * Kernel module interface | |
2871 | * | |
2872 | *************************************************************************/ | |
2873 | ||
2874 | module_param(interrupt_mode, uint, 0444); | |
2875 | MODULE_PARM_DESC(interrupt_mode, | |
2876 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2877 | ||
2878 | static int __init efx_init_module(void) | |
2879 | { | |
2880 | int rc; | |
2881 | ||
2882 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2883 | ||
2884 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2885 | if (rc) | |
2886 | goto err_notifier; | |
2887 | ||
cd2d5b52 BH |
2888 | rc = efx_init_sriov(); |
2889 | if (rc) | |
2890 | goto err_sriov; | |
2891 | ||
1ab00629 SH |
2892 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2893 | if (!reset_workqueue) { | |
2894 | rc = -ENOMEM; | |
2895 | goto err_reset; | |
2896 | } | |
8ceee660 BH |
2897 | |
2898 | rc = pci_register_driver(&efx_pci_driver); | |
2899 | if (rc < 0) | |
2900 | goto err_pci; | |
2901 | ||
2902 | return 0; | |
2903 | ||
2904 | err_pci: | |
1ab00629 SH |
2905 | destroy_workqueue(reset_workqueue); |
2906 | err_reset: | |
cd2d5b52 BH |
2907 | efx_fini_sriov(); |
2908 | err_sriov: | |
8ceee660 BH |
2909 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2910 | err_notifier: | |
2911 | return rc; | |
2912 | } | |
2913 | ||
2914 | static void __exit efx_exit_module(void) | |
2915 | { | |
2916 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2917 | ||
2918 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2919 | destroy_workqueue(reset_workqueue); |
cd2d5b52 | 2920 | efx_fini_sriov(); |
8ceee660 BH |
2921 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2922 | ||
2923 | } | |
2924 | ||
2925 | module_init(efx_init_module); | |
2926 | module_exit(efx_exit_module); | |
2927 | ||
906bb26c BH |
2928 | MODULE_AUTHOR("Solarflare Communications and " |
2929 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2930 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2931 | MODULE_LICENSE("GPL"); | |
2932 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |