sfc: Disable RSS when using SR-IOV and only 1 RX queue on the PF
[deliverable/linux.git] / drivers / net / ethernet / sfc / efx.c
CommitLineData
8ceee660
BH
1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
0a6f40c6 4 * Copyright 2005-2011 Solarflare Communications Inc.
8ceee660
BH
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
20#include <linux/crc32.h>
21#include <linux/ethtool.h>
aa6ef27e 22#include <linux/topology.h>
5a0e3ad6 23#include <linux/gfp.h>
64d8ad6d 24#include <linux/cpu_rmap.h>
8ceee660 25#include "net_driver.h"
8ceee660 26#include "efx.h"
744093c9 27#include "nic.h"
dd40781e 28#include "selftest.h"
8ceee660 29
8880f4ec 30#include "mcdi.h"
fd371e32 31#include "workarounds.h"
8880f4ec 32
c459302d
BH
33/**************************************************************************
34 *
35 * Type name strings
36 *
37 **************************************************************************
38 */
39
40/* Loopback mode names (see LOOPBACK_MODE()) */
41const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
18e83e4c 42const char *const efx_loopback_mode_names[] = {
c459302d 43 [LOOPBACK_NONE] = "NONE",
e58f69f4 44 [LOOPBACK_DATA] = "DATAPATH",
c459302d
BH
45 [LOOPBACK_GMAC] = "GMAC",
46 [LOOPBACK_XGMII] = "XGMII",
47 [LOOPBACK_XGXS] = "XGXS",
9c636baf
BH
48 [LOOPBACK_XAUI] = "XAUI",
49 [LOOPBACK_GMII] = "GMII",
50 [LOOPBACK_SGMII] = "SGMII",
e58f69f4
BH
51 [LOOPBACK_XGBR] = "XGBR",
52 [LOOPBACK_XFI] = "XFI",
53 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
54 [LOOPBACK_GMII_FAR] = "GMII_FAR",
55 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
56 [LOOPBACK_XFI_FAR] = "XFI_FAR",
c459302d
BH
57 [LOOPBACK_GPHY] = "GPHY",
58 [LOOPBACK_PHYXS] = "PHYXS",
9c636baf
BH
59 [LOOPBACK_PCS] = "PCS",
60 [LOOPBACK_PMAPMD] = "PMA/PMD",
e58f69f4
BH
61 [LOOPBACK_XPORT] = "XPORT",
62 [LOOPBACK_XGMII_WS] = "XGMII_WS",
9c636baf 63 [LOOPBACK_XAUI_WS] = "XAUI_WS",
e58f69f4
BH
64 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
65 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
9c636baf 66 [LOOPBACK_GMII_WS] = "GMII_WS",
e58f69f4
BH
67 [LOOPBACK_XFI_WS] = "XFI_WS",
68 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
9c636baf 69 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
c459302d
BH
70};
71
c459302d 72const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
18e83e4c 73const char *const efx_reset_type_names[] = {
c459302d
BH
74 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
75 [RESET_TYPE_ALL] = "ALL",
76 [RESET_TYPE_WORLD] = "WORLD",
77 [RESET_TYPE_DISABLE] = "DISABLE",
78 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
79 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
80 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
81 [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH",
82 [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH",
83 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
8880f4ec 84 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
c459302d
BH
85};
86
8ceee660
BH
87#define EFX_MAX_MTU (9 * 1024)
88
1ab00629
SH
89/* Reset workqueue. If any NIC has a hardware failure then a reset will be
90 * queued onto this work queue. This is not a per-nic work queue, because
91 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
92 */
93static struct workqueue_struct *reset_workqueue;
94
8ceee660
BH
95/**************************************************************************
96 *
97 * Configurable values
98 *
99 *************************************************************************/
100
8ceee660
BH
101/*
102 * Use separate channels for TX and RX events
103 *
28b581ab
NT
104 * Set this to 1 to use separate channels for TX and RX. It allows us
105 * to control interrupt affinity separately for TX and RX.
8ceee660 106 *
28b581ab 107 * This is only used in MSI-X interrupt mode
8ceee660 108 */
b9cc977d
BH
109static bool separate_tx_channels;
110module_param(separate_tx_channels, bool, 0444);
28b581ab
NT
111MODULE_PARM_DESC(separate_tx_channels,
112 "Use separate channels for TX and RX");
8ceee660
BH
113
114/* This is the weight assigned to each of the (per-channel) virtual
115 * NAPI devices.
116 */
117static int napi_weight = 64;
118
119/* This is the time (in jiffies) between invocations of the hardware
e254c274
BH
120 * monitor. On Falcon-based NICs, this will:
121 * - Check the on-board hardware monitor;
122 * - Poll the link state and reconfigure the hardware as necessary.
8ceee660 123 */
d215697f 124static unsigned int efx_monitor_interval = 1 * HZ;
8ceee660 125
8ceee660
BH
126/* Initial interrupt moderation settings. They can be modified after
127 * module load with ethtool.
128 *
129 * The default for RX should strike a balance between increasing the
130 * round-trip latency and reducing overhead.
131 */
132static unsigned int rx_irq_mod_usec = 60;
133
134/* Initial interrupt moderation settings. They can be modified after
135 * module load with ethtool.
136 *
137 * This default is chosen to ensure that a 10G link does not go idle
138 * while a TX queue is stopped after it has become full. A queue is
139 * restarted when it drops below half full. The time this takes (assuming
140 * worst case 3 descriptors per packet and 1024 descriptors) is
141 * 512 / 3 * 1.2 = 205 usec.
142 */
143static unsigned int tx_irq_mod_usec = 150;
144
145/* This is the first interrupt mode to try out of:
146 * 0 => MSI-X
147 * 1 => MSI
148 * 2 => legacy
149 */
150static unsigned int interrupt_mode;
151
152/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
153 * i.e. the number of CPUs among which we may distribute simultaneous
154 * interrupt handling.
155 *
156 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
cdb08f8f 157 * The default (0) means to assign an interrupt to each core.
8ceee660
BH
158 */
159static unsigned int rss_cpus;
160module_param(rss_cpus, uint, 0444);
161MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
162
b9cc977d
BH
163static bool phy_flash_cfg;
164module_param(phy_flash_cfg, bool, 0644);
84ae48fe
BH
165MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
166
e7bed9c8 167static unsigned irq_adapt_low_thresh = 8000;
6fb70fd1
BH
168module_param(irq_adapt_low_thresh, uint, 0644);
169MODULE_PARM_DESC(irq_adapt_low_thresh,
170 "Threshold score for reducing IRQ moderation");
171
e7bed9c8 172static unsigned irq_adapt_high_thresh = 16000;
6fb70fd1
BH
173module_param(irq_adapt_high_thresh, uint, 0644);
174MODULE_PARM_DESC(irq_adapt_high_thresh,
175 "Threshold score for increasing IRQ moderation");
176
62776d03
BH
177static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
178 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
179 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
180 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
181module_param(debug, uint, 0);
182MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
183
8ceee660
BH
184/**************************************************************************
185 *
186 * Utility functions and prototypes
187 *
188 *************************************************************************/
4642610c 189
7f967c01
BH
190static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq);
191static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq);
192static void efx_remove_channel(struct efx_channel *channel);
4642610c 193static void efx_remove_channels(struct efx_nic *efx);
7f967c01 194static const struct efx_channel_type efx_default_channel_type;
8ceee660 195static void efx_remove_port(struct efx_nic *efx);
7f967c01 196static void efx_init_napi_channel(struct efx_channel *channel);
8ceee660 197static void efx_fini_napi(struct efx_nic *efx);
e8f14992 198static void efx_fini_napi_channel(struct efx_channel *channel);
4642610c
BH
199static void efx_fini_struct(struct efx_nic *efx);
200static void efx_start_all(struct efx_nic *efx);
201static void efx_stop_all(struct efx_nic *efx);
8ceee660
BH
202
203#define EFX_ASSERT_RESET_SERIALISED(efx) \
204 do { \
f16aeea0 205 if ((efx->state == STATE_READY) || \
332c1ce9 206 (efx->state == STATE_DISABLED)) \
8ceee660
BH
207 ASSERT_RTNL(); \
208 } while (0)
209
8b7325b4
BH
210static int efx_check_disabled(struct efx_nic *efx)
211{
212 if (efx->state == STATE_DISABLED) {
213 netif_err(efx, drv, efx->net_dev,
214 "device is disabled due to earlier errors\n");
215 return -EIO;
216 }
217 return 0;
218}
219
8ceee660
BH
220/**************************************************************************
221 *
222 * Event queue processing
223 *
224 *************************************************************************/
225
226/* Process channel's event queue
227 *
228 * This function is responsible for processing the event queue of a
229 * single channel. The caller must guarantee that this function will
230 * never be concurrently called more than once on the same channel,
231 * though different channels may be being processed concurrently.
232 */
fa236e18 233static int efx_process_channel(struct efx_channel *channel, int budget)
8ceee660 234{
fa236e18 235 int spent;
8ceee660 236
9f2cb71c 237 if (unlikely(!channel->enabled))
42cbe2d7 238 return 0;
8ceee660 239
fa236e18 240 spent = efx_nic_process_eventq(channel, budget);
d9ab7007
BH
241 if (spent && efx_channel_has_rx_queue(channel)) {
242 struct efx_rx_queue *rx_queue =
243 efx_channel_get_rx_queue(channel);
244
245 /* Deliver last RX packet. */
246 if (channel->rx_pkt) {
247 __efx_rx_packet(channel, channel->rx_pkt);
248 channel->rx_pkt = NULL;
249 }
97d48a10 250 if (rx_queue->enabled)
9f2cb71c 251 efx_fast_push_rx_descriptors(rx_queue);
8ceee660
BH
252 }
253
fa236e18 254 return spent;
8ceee660
BH
255}
256
257/* Mark channel as finished processing
258 *
259 * Note that since we will not receive further interrupts for this
260 * channel before we finish processing and call the eventq_read_ack()
261 * method, there is no need to use the interrupt hold-off timers.
262 */
263static inline void efx_channel_processed(struct efx_channel *channel)
264{
5b9e207c
BH
265 /* The interrupt handler for this channel may set work_pending
266 * as soon as we acknowledge the events we've seen. Make sure
267 * it's cleared before then. */
dc8cfa55 268 channel->work_pending = false;
5b9e207c
BH
269 smp_wmb();
270
152b6a62 271 efx_nic_eventq_read_ack(channel);
8ceee660
BH
272}
273
274/* NAPI poll handler
275 *
276 * NAPI guarantees serialisation of polls of the same device, which
277 * provides the guarantee required by efx_process_channel().
278 */
279static int efx_poll(struct napi_struct *napi, int budget)
280{
281 struct efx_channel *channel =
282 container_of(napi, struct efx_channel, napi_str);
62776d03 283 struct efx_nic *efx = channel->efx;
fa236e18 284 int spent;
8ceee660 285
62776d03
BH
286 netif_vdbg(efx, intr, efx->net_dev,
287 "channel %d NAPI poll executing on CPU %d\n",
288 channel->channel, raw_smp_processor_id());
8ceee660 289
fa236e18 290 spent = efx_process_channel(channel, budget);
8ceee660 291
fa236e18 292 if (spent < budget) {
9d9a6973 293 if (efx_channel_has_rx_queue(channel) &&
6fb70fd1
BH
294 efx->irq_rx_adaptive &&
295 unlikely(++channel->irq_count == 1000)) {
6fb70fd1
BH
296 if (unlikely(channel->irq_mod_score <
297 irq_adapt_low_thresh)) {
0d86ebd8
BH
298 if (channel->irq_moderation > 1) {
299 channel->irq_moderation -= 1;
ef2b90ee 300 efx->type->push_irq_moderation(channel);
0d86ebd8 301 }
6fb70fd1
BH
302 } else if (unlikely(channel->irq_mod_score >
303 irq_adapt_high_thresh)) {
0d86ebd8
BH
304 if (channel->irq_moderation <
305 efx->irq_rx_moderation) {
306 channel->irq_moderation += 1;
ef2b90ee 307 efx->type->push_irq_moderation(channel);
0d86ebd8 308 }
6fb70fd1 309 }
6fb70fd1
BH
310 channel->irq_count = 0;
311 channel->irq_mod_score = 0;
312 }
313
64d8ad6d
BH
314 efx_filter_rfs_expire(channel);
315
8ceee660 316 /* There is no race here; although napi_disable() will
288379f0 317 * only wait for napi_complete(), this isn't a problem
8ceee660
BH
318 * since efx_channel_processed() will have no effect if
319 * interrupts have already been disabled.
320 */
288379f0 321 napi_complete(napi);
8ceee660
BH
322 efx_channel_processed(channel);
323 }
324
fa236e18 325 return spent;
8ceee660
BH
326}
327
328/* Process the eventq of the specified channel immediately on this CPU
329 *
330 * Disable hardware generated interrupts, wait for any existing
331 * processing to finish, then directly poll (and ack ) the eventq.
332 * Finally reenable NAPI and interrupts.
333 *
d4fabcc8
BH
334 * This is for use only during a loopback self-test. It must not
335 * deliver any packets up the stack as this can result in deadlock.
8ceee660
BH
336 */
337void efx_process_channel_now(struct efx_channel *channel)
338{
339 struct efx_nic *efx = channel->efx;
340
8313aca3 341 BUG_ON(channel->channel >= efx->n_channels);
8ceee660 342 BUG_ON(!channel->enabled);
d4fabcc8 343 BUG_ON(!efx->loopback_selftest);
8ceee660
BH
344
345 /* Disable interrupts and wait for ISRs to complete */
152b6a62 346 efx_nic_disable_interrupts(efx);
94dec6a2 347 if (efx->legacy_irq) {
8ceee660 348 synchronize_irq(efx->legacy_irq);
94dec6a2
BH
349 efx->legacy_irq_enabled = false;
350 }
64ee3120 351 if (channel->irq)
8ceee660
BH
352 synchronize_irq(channel->irq);
353
354 /* Wait for any NAPI processing to complete */
355 napi_disable(&channel->napi_str);
356
357 /* Poll the channel */
ecc910f5 358 efx_process_channel(channel, channel->eventq_mask + 1);
8ceee660
BH
359
360 /* Ack the eventq. This may cause an interrupt to be generated
361 * when they are reenabled */
362 efx_channel_processed(channel);
363
364 napi_enable(&channel->napi_str);
94dec6a2
BH
365 if (efx->legacy_irq)
366 efx->legacy_irq_enabled = true;
152b6a62 367 efx_nic_enable_interrupts(efx);
8ceee660
BH
368}
369
370/* Create event queue
371 * Event queue memory allocations are done only once. If the channel
372 * is reset, the memory buffer will be reused; this guards against
373 * errors during channel reset and also simplifies interrupt handling.
374 */
375static int efx_probe_eventq(struct efx_channel *channel)
376{
ecc910f5
SH
377 struct efx_nic *efx = channel->efx;
378 unsigned long entries;
379
86ee5302 380 netif_dbg(efx, probe, efx->net_dev,
62776d03 381 "chan %d create event queue\n", channel->channel);
8ceee660 382
ecc910f5
SH
383 /* Build an event queue with room for one event per tx and rx buffer,
384 * plus some extra for link state events and MCDI completions. */
385 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
386 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
387 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
388
152b6a62 389 return efx_nic_probe_eventq(channel);
8ceee660
BH
390}
391
392/* Prepare channel's event queue */
bc3c90a2 393static void efx_init_eventq(struct efx_channel *channel)
8ceee660 394{
62776d03
BH
395 netif_dbg(channel->efx, drv, channel->efx->net_dev,
396 "chan %d init event queue\n", channel->channel);
8ceee660
BH
397
398 channel->eventq_read_ptr = 0;
399
152b6a62 400 efx_nic_init_eventq(channel);
8ceee660
BH
401}
402
9f2cb71c
BH
403/* Enable event queue processing and NAPI */
404static void efx_start_eventq(struct efx_channel *channel)
405{
406 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
407 "chan %d start event queue\n", channel->channel);
408
409 /* The interrupt handler for this channel may set work_pending
410 * as soon as we enable it. Make sure it's cleared before
411 * then. Similarly, make sure it sees the enabled flag set.
412 */
413 channel->work_pending = false;
414 channel->enabled = true;
415 smp_wmb();
416
417 napi_enable(&channel->napi_str);
418 efx_nic_eventq_read_ack(channel);
419}
420
421/* Disable event queue processing and NAPI */
422static void efx_stop_eventq(struct efx_channel *channel)
423{
424 if (!channel->enabled)
425 return;
426
427 napi_disable(&channel->napi_str);
428 channel->enabled = false;
429}
430
8ceee660
BH
431static void efx_fini_eventq(struct efx_channel *channel)
432{
62776d03
BH
433 netif_dbg(channel->efx, drv, channel->efx->net_dev,
434 "chan %d fini event queue\n", channel->channel);
8ceee660 435
152b6a62 436 efx_nic_fini_eventq(channel);
8ceee660
BH
437}
438
439static void efx_remove_eventq(struct efx_channel *channel)
440{
62776d03
BH
441 netif_dbg(channel->efx, drv, channel->efx->net_dev,
442 "chan %d remove event queue\n", channel->channel);
8ceee660 443
152b6a62 444 efx_nic_remove_eventq(channel);
8ceee660
BH
445}
446
447/**************************************************************************
448 *
449 * Channel handling
450 *
451 *************************************************************************/
452
7f967c01 453/* Allocate and initialise a channel structure. */
4642610c
BH
454static struct efx_channel *
455efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
456{
457 struct efx_channel *channel;
458 struct efx_rx_queue *rx_queue;
459 struct efx_tx_queue *tx_queue;
460 int j;
461
7f967c01
BH
462 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
463 if (!channel)
464 return NULL;
4642610c 465
7f967c01
BH
466 channel->efx = efx;
467 channel->channel = i;
468 channel->type = &efx_default_channel_type;
4642610c 469
7f967c01
BH
470 for (j = 0; j < EFX_TXQ_TYPES; j++) {
471 tx_queue = &channel->tx_queue[j];
472 tx_queue->efx = efx;
473 tx_queue->queue = i * EFX_TXQ_TYPES + j;
474 tx_queue->channel = channel;
475 }
4642610c 476
7f967c01
BH
477 rx_queue = &channel->rx_queue;
478 rx_queue->efx = efx;
479 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
480 (unsigned long)rx_queue);
4642610c 481
7f967c01
BH
482 return channel;
483}
484
485/* Allocate and initialise a channel structure, copying parameters
486 * (but not resources) from an old channel structure.
487 */
488static struct efx_channel *
489efx_copy_channel(const struct efx_channel *old_channel)
490{
491 struct efx_channel *channel;
492 struct efx_rx_queue *rx_queue;
493 struct efx_tx_queue *tx_queue;
494 int j;
4642610c 495
7f967c01
BH
496 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
497 if (!channel)
498 return NULL;
499
500 *channel = *old_channel;
501
502 channel->napi_dev = NULL;
503 memset(&channel->eventq, 0, sizeof(channel->eventq));
4642610c 504
7f967c01
BH
505 for (j = 0; j < EFX_TXQ_TYPES; j++) {
506 tx_queue = &channel->tx_queue[j];
507 if (tx_queue->channel)
4642610c 508 tx_queue->channel = channel;
7f967c01
BH
509 tx_queue->buffer = NULL;
510 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
4642610c
BH
511 }
512
4642610c 513 rx_queue = &channel->rx_queue;
7f967c01
BH
514 rx_queue->buffer = NULL;
515 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
4642610c
BH
516 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
517 (unsigned long)rx_queue);
518
519 return channel;
520}
521
8ceee660
BH
522static int efx_probe_channel(struct efx_channel *channel)
523{
524 struct efx_tx_queue *tx_queue;
525 struct efx_rx_queue *rx_queue;
526 int rc;
527
62776d03
BH
528 netif_dbg(channel->efx, probe, channel->efx->net_dev,
529 "creating channel %d\n", channel->channel);
8ceee660 530
7f967c01
BH
531 rc = channel->type->pre_probe(channel);
532 if (rc)
533 goto fail;
534
8ceee660
BH
535 rc = efx_probe_eventq(channel);
536 if (rc)
7f967c01 537 goto fail;
8ceee660
BH
538
539 efx_for_each_channel_tx_queue(tx_queue, channel) {
540 rc = efx_probe_tx_queue(tx_queue);
541 if (rc)
7f967c01 542 goto fail;
8ceee660
BH
543 }
544
545 efx_for_each_channel_rx_queue(rx_queue, channel) {
546 rc = efx_probe_rx_queue(rx_queue);
547 if (rc)
7f967c01 548 goto fail;
8ceee660
BH
549 }
550
551 channel->n_rx_frm_trunc = 0;
552
553 return 0;
554
7f967c01
BH
555fail:
556 efx_remove_channel(channel);
8ceee660
BH
557 return rc;
558}
559
7f967c01
BH
560static void
561efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
562{
563 struct efx_nic *efx = channel->efx;
564 const char *type;
565 int number;
566
567 number = channel->channel;
568 if (efx->tx_channel_offset == 0) {
569 type = "";
570 } else if (channel->channel < efx->tx_channel_offset) {
571 type = "-rx";
572 } else {
573 type = "-tx";
574 number -= efx->tx_channel_offset;
575 }
576 snprintf(buf, len, "%s%s-%d", efx->name, type, number);
577}
8ceee660 578
56536e9c
BH
579static void efx_set_channel_names(struct efx_nic *efx)
580{
581 struct efx_channel *channel;
56536e9c 582
7f967c01
BH
583 efx_for_each_channel(channel, efx)
584 channel->type->get_name(channel,
585 efx->channel_name[channel->channel],
586 sizeof(efx->channel_name[0]));
56536e9c
BH
587}
588
4642610c
BH
589static int efx_probe_channels(struct efx_nic *efx)
590{
591 struct efx_channel *channel;
592 int rc;
593
594 /* Restart special buffer allocation */
595 efx->next_buffer_table = 0;
596
c92aaff1
BH
597 /* Probe channels in reverse, so that any 'extra' channels
598 * use the start of the buffer table. This allows the traffic
599 * channels to be resized without moving them or wasting the
600 * entries before them.
601 */
602 efx_for_each_channel_rev(channel, efx) {
4642610c
BH
603 rc = efx_probe_channel(channel);
604 if (rc) {
605 netif_err(efx, probe, efx->net_dev,
606 "failed to create channel %d\n",
607 channel->channel);
608 goto fail;
609 }
610 }
611 efx_set_channel_names(efx);
612
613 return 0;
614
615fail:
616 efx_remove_channels(efx);
617 return rc;
618}
619
8ceee660
BH
620/* Channels are shutdown and reinitialised whilst the NIC is running
621 * to propagate configuration changes (mtu, checksum offload), or
622 * to clear hardware error conditions
623 */
9f2cb71c 624static void efx_start_datapath(struct efx_nic *efx)
8ceee660
BH
625{
626 struct efx_tx_queue *tx_queue;
627 struct efx_rx_queue *rx_queue;
628 struct efx_channel *channel;
8ceee660 629
f7f13b0b
BH
630 /* Calculate the rx buffer allocation parameters required to
631 * support the current MTU, including padding for header
632 * alignment and overruns.
633 */
634 efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) +
635 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
39c9cf07 636 efx->type->rx_buffer_hash_size +
f7f13b0b 637 efx->type->rx_buffer_padding);
62b330ba
SH
638 efx->rx_buffer_order = get_order(efx->rx_buffer_len +
639 sizeof(struct efx_rx_page_state));
8ceee660 640
14bf718f
BH
641 /* We must keep at least one descriptor in a TX ring empty.
642 * We could avoid this when the queue size does not exactly
643 * match the hardware ring size, but it's not that important.
644 * Therefore we stop the queue when one more skb might fill
645 * the ring completely. We wake it when half way back to
646 * empty.
647 */
648 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
649 efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
650
8ceee660
BH
651 /* Initialise the channels */
652 efx_for_each_channel(channel, efx) {
bc3c90a2
BH
653 efx_for_each_channel_tx_queue(tx_queue, channel)
654 efx_init_tx_queue(tx_queue);
8ceee660 655
9f2cb71c 656 efx_for_each_channel_rx_queue(rx_queue, channel) {
bc3c90a2 657 efx_init_rx_queue(rx_queue);
9f2cb71c
BH
658 efx_nic_generate_fill_event(rx_queue);
659 }
8ceee660
BH
660
661 WARN_ON(channel->rx_pkt != NULL);
8ceee660 662 }
8ceee660 663
9f2cb71c
BH
664 if (netif_device_present(efx->net_dev))
665 netif_tx_wake_all_queues(efx->net_dev);
8ceee660
BH
666}
667
9f2cb71c 668static void efx_stop_datapath(struct efx_nic *efx)
8ceee660
BH
669{
670 struct efx_channel *channel;
671 struct efx_tx_queue *tx_queue;
672 struct efx_rx_queue *rx_queue;
3dca9d2d 673 struct pci_dev *dev = efx->pci_dev;
6bc5d3a9 674 int rc;
8ceee660
BH
675
676 EFX_ASSERT_RESET_SERIALISED(efx);
677 BUG_ON(efx->port_enabled);
678
3dca9d2d
SH
679 /* Only perform flush if dma is enabled */
680 if (dev->is_busmaster) {
681 rc = efx_nic_flush_queues(efx);
682
683 if (rc && EFX_WORKAROUND_7803(efx)) {
684 /* Schedule a reset to recover from the flush failure. The
685 * descriptor caches reference memory we're about to free,
686 * but falcon_reconfigure_mac_wrapper() won't reconnect
687 * the MACs because of the pending reset. */
688 netif_err(efx, drv, efx->net_dev,
689 "Resetting to recover from flush failure\n");
690 efx_schedule_reset(efx, RESET_TYPE_ALL);
691 } else if (rc) {
692 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
693 } else {
694 netif_dbg(efx, drv, efx->net_dev,
695 "successfully flushed all queues\n");
696 }
fd371e32 697 }
6bc5d3a9 698
8ceee660 699 efx_for_each_channel(channel, efx) {
9f2cb71c
BH
700 /* RX packet processing is pipelined, so wait for the
701 * NAPI handler to complete. At least event queue 0
702 * might be kept active by non-data events, so don't
703 * use napi_synchronize() but actually disable NAPI
704 * temporarily.
705 */
706 if (efx_channel_has_rx_queue(channel)) {
707 efx_stop_eventq(channel);
708 efx_start_eventq(channel);
709 }
8ceee660
BH
710
711 efx_for_each_channel_rx_queue(rx_queue, channel)
712 efx_fini_rx_queue(rx_queue);
94b274bf 713 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660 714 efx_fini_tx_queue(tx_queue);
8ceee660
BH
715 }
716}
717
718static void efx_remove_channel(struct efx_channel *channel)
719{
720 struct efx_tx_queue *tx_queue;
721 struct efx_rx_queue *rx_queue;
722
62776d03
BH
723 netif_dbg(channel->efx, drv, channel->efx->net_dev,
724 "destroy chan %d\n", channel->channel);
8ceee660
BH
725
726 efx_for_each_channel_rx_queue(rx_queue, channel)
727 efx_remove_rx_queue(rx_queue);
94b274bf 728 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660
BH
729 efx_remove_tx_queue(tx_queue);
730 efx_remove_eventq(channel);
c31e5f9f 731 channel->type->post_remove(channel);
8ceee660
BH
732}
733
4642610c
BH
734static void efx_remove_channels(struct efx_nic *efx)
735{
736 struct efx_channel *channel;
737
738 efx_for_each_channel(channel, efx)
739 efx_remove_channel(channel);
740}
741
742int
743efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
744{
745 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
746 u32 old_rxq_entries, old_txq_entries;
7f967c01 747 unsigned i, next_buffer_table = 0;
8b7325b4
BH
748 int rc;
749
750 rc = efx_check_disabled(efx);
751 if (rc)
752 return rc;
7f967c01
BH
753
754 /* Not all channels should be reallocated. We must avoid
755 * reallocating their buffer table entries.
756 */
757 efx_for_each_channel(channel, efx) {
758 struct efx_rx_queue *rx_queue;
759 struct efx_tx_queue *tx_queue;
760
761 if (channel->type->copy)
762 continue;
763 next_buffer_table = max(next_buffer_table,
764 channel->eventq.index +
765 channel->eventq.entries);
766 efx_for_each_channel_rx_queue(rx_queue, channel)
767 next_buffer_table = max(next_buffer_table,
768 rx_queue->rxd.index +
769 rx_queue->rxd.entries);
770 efx_for_each_channel_tx_queue(tx_queue, channel)
771 next_buffer_table = max(next_buffer_table,
772 tx_queue->txd.index +
773 tx_queue->txd.entries);
774 }
4642610c 775
29c69a48 776 efx_device_detach_sync(efx);
4642610c 777 efx_stop_all(efx);
7f967c01 778 efx_stop_interrupts(efx, true);
4642610c 779
7f967c01 780 /* Clone channels (where possible) */
4642610c
BH
781 memset(other_channel, 0, sizeof(other_channel));
782 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH
783 channel = efx->channel[i];
784 if (channel->type->copy)
785 channel = channel->type->copy(channel);
4642610c
BH
786 if (!channel) {
787 rc = -ENOMEM;
788 goto out;
789 }
790 other_channel[i] = channel;
791 }
792
793 /* Swap entry counts and channel pointers */
794 old_rxq_entries = efx->rxq_entries;
795 old_txq_entries = efx->txq_entries;
796 efx->rxq_entries = rxq_entries;
797 efx->txq_entries = txq_entries;
798 for (i = 0; i < efx->n_channels; i++) {
799 channel = efx->channel[i];
800 efx->channel[i] = other_channel[i];
801 other_channel[i] = channel;
802 }
803
7f967c01
BH
804 /* Restart buffer table allocation */
805 efx->next_buffer_table = next_buffer_table;
e8f14992 806
e8f14992 807 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH
808 channel = efx->channel[i];
809 if (!channel->type->copy)
810 continue;
811 rc = efx_probe_channel(channel);
812 if (rc)
813 goto rollback;
814 efx_init_napi_channel(efx->channel[i]);
e8f14992 815 }
7f967c01 816
4642610c 817out:
7f967c01
BH
818 /* Destroy unused channel structures */
819 for (i = 0; i < efx->n_channels; i++) {
820 channel = other_channel[i];
821 if (channel && channel->type->copy) {
822 efx_fini_napi_channel(channel);
823 efx_remove_channel(channel);
824 kfree(channel);
825 }
826 }
4642610c 827
7f967c01 828 efx_start_interrupts(efx, true);
4642610c 829 efx_start_all(efx);
29c69a48 830 netif_device_attach(efx->net_dev);
4642610c
BH
831 return rc;
832
833rollback:
834 /* Swap back */
835 efx->rxq_entries = old_rxq_entries;
836 efx->txq_entries = old_txq_entries;
837 for (i = 0; i < efx->n_channels; i++) {
838 channel = efx->channel[i];
839 efx->channel[i] = other_channel[i];
840 other_channel[i] = channel;
841 }
842 goto out;
843}
844
90d683af 845void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
8ceee660 846{
90d683af 847 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
8ceee660
BH
848}
849
7f967c01
BH
850static const struct efx_channel_type efx_default_channel_type = {
851 .pre_probe = efx_channel_dummy_op_int,
c31e5f9f 852 .post_remove = efx_channel_dummy_op_void,
7f967c01
BH
853 .get_name = efx_get_channel_name,
854 .copy = efx_copy_channel,
855 .keep_eventq = false,
856};
857
858int efx_channel_dummy_op_int(struct efx_channel *channel)
859{
860 return 0;
861}
862
c31e5f9f
SH
863void efx_channel_dummy_op_void(struct efx_channel *channel)
864{
865}
866
8ceee660
BH
867/**************************************************************************
868 *
869 * Port handling
870 *
871 **************************************************************************/
872
873/* This ensures that the kernel is kept informed (via
874 * netif_carrier_on/off) of the link status, and also maintains the
875 * link status's stop on the port's TX queue.
876 */
fdaa9aed 877void efx_link_status_changed(struct efx_nic *efx)
8ceee660 878{
eb50c0d6
BH
879 struct efx_link_state *link_state = &efx->link_state;
880
8ceee660
BH
881 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
882 * that no events are triggered between unregister_netdev() and the
883 * driver unloading. A more general condition is that NETDEV_CHANGE
884 * can only be generated between NETDEV_UP and NETDEV_DOWN */
885 if (!netif_running(efx->net_dev))
886 return;
887
eb50c0d6 888 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
8ceee660
BH
889 efx->n_link_state_changes++;
890
eb50c0d6 891 if (link_state->up)
8ceee660
BH
892 netif_carrier_on(efx->net_dev);
893 else
894 netif_carrier_off(efx->net_dev);
895 }
896
897 /* Status message for kernel log */
2aa9ef11 898 if (link_state->up)
62776d03
BH
899 netif_info(efx, link, efx->net_dev,
900 "link up at %uMbps %s-duplex (MTU %d)%s\n",
901 link_state->speed, link_state->fd ? "full" : "half",
902 efx->net_dev->mtu,
903 (efx->promiscuous ? " [PROMISC]" : ""));
2aa9ef11 904 else
62776d03 905 netif_info(efx, link, efx->net_dev, "link down\n");
8ceee660
BH
906}
907
d3245b28
BH
908void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
909{
910 efx->link_advertising = advertising;
911 if (advertising) {
912 if (advertising & ADVERTISED_Pause)
913 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
914 else
915 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
916 if (advertising & ADVERTISED_Asym_Pause)
917 efx->wanted_fc ^= EFX_FC_TX;
918 }
919}
920
b5626946 921void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
d3245b28
BH
922{
923 efx->wanted_fc = wanted_fc;
924 if (efx->link_advertising) {
925 if (wanted_fc & EFX_FC_RX)
926 efx->link_advertising |= (ADVERTISED_Pause |
927 ADVERTISED_Asym_Pause);
928 else
929 efx->link_advertising &= ~(ADVERTISED_Pause |
930 ADVERTISED_Asym_Pause);
931 if (wanted_fc & EFX_FC_TX)
932 efx->link_advertising ^= ADVERTISED_Asym_Pause;
933 }
934}
935
115122af
BH
936static void efx_fini_port(struct efx_nic *efx);
937
d3245b28
BH
938/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
939 * the MAC appropriately. All other PHY configuration changes are pushed
940 * through phy_op->set_settings(), and pushed asynchronously to the MAC
941 * through efx_monitor().
942 *
943 * Callers must hold the mac_lock
944 */
945int __efx_reconfigure_port(struct efx_nic *efx)
8ceee660 946{
d3245b28
BH
947 enum efx_phy_mode phy_mode;
948 int rc;
8ceee660 949
d3245b28 950 WARN_ON(!mutex_is_locked(&efx->mac_lock));
8ceee660 951
0fca8c97 952 /* Serialise the promiscuous flag with efx_set_rx_mode. */
73ba7b68
BH
953 netif_addr_lock_bh(efx->net_dev);
954 netif_addr_unlock_bh(efx->net_dev);
a816f75a 955
d3245b28
BH
956 /* Disable PHY transmit in mac level loopbacks */
957 phy_mode = efx->phy_mode;
177dfcd8
BH
958 if (LOOPBACK_INTERNAL(efx))
959 efx->phy_mode |= PHY_MODE_TX_DISABLED;
960 else
961 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
177dfcd8 962
d3245b28 963 rc = efx->type->reconfigure_port(efx);
8ceee660 964
d3245b28
BH
965 if (rc)
966 efx->phy_mode = phy_mode;
177dfcd8 967
d3245b28 968 return rc;
8ceee660
BH
969}
970
971/* Reinitialise the MAC to pick up new PHY settings, even if the port is
972 * disabled. */
d3245b28 973int efx_reconfigure_port(struct efx_nic *efx)
8ceee660 974{
d3245b28
BH
975 int rc;
976
8ceee660
BH
977 EFX_ASSERT_RESET_SERIALISED(efx);
978
979 mutex_lock(&efx->mac_lock);
d3245b28 980 rc = __efx_reconfigure_port(efx);
8ceee660 981 mutex_unlock(&efx->mac_lock);
d3245b28
BH
982
983 return rc;
8ceee660
BH
984}
985
8be4f3e6
BH
986/* Asynchronous work item for changing MAC promiscuity and multicast
987 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
988 * MAC directly. */
766ca0fa
BH
989static void efx_mac_work(struct work_struct *data)
990{
991 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
992
993 mutex_lock(&efx->mac_lock);
30b81cda 994 if (efx->port_enabled)
710b208d 995 efx->type->reconfigure_mac(efx);
766ca0fa
BH
996 mutex_unlock(&efx->mac_lock);
997}
998
8ceee660
BH
999static int efx_probe_port(struct efx_nic *efx)
1000{
1001 int rc;
1002
62776d03 1003 netif_dbg(efx, probe, efx->net_dev, "create port\n");
8ceee660 1004
ff3b00a0
SH
1005 if (phy_flash_cfg)
1006 efx->phy_mode = PHY_MODE_SPECIAL;
1007
ef2b90ee
BH
1008 /* Connect up MAC/PHY operations table */
1009 rc = efx->type->probe_port(efx);
8ceee660 1010 if (rc)
e42de262 1011 return rc;
8ceee660 1012
e332bcb3
BH
1013 /* Initialise MAC address to permanent address */
1014 memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN);
8ceee660
BH
1015
1016 return 0;
8ceee660
BH
1017}
1018
1019static int efx_init_port(struct efx_nic *efx)
1020{
1021 int rc;
1022
62776d03 1023 netif_dbg(efx, drv, efx->net_dev, "init port\n");
8ceee660 1024
1dfc5cea
BH
1025 mutex_lock(&efx->mac_lock);
1026
177dfcd8 1027 rc = efx->phy_op->init(efx);
8ceee660 1028 if (rc)
1dfc5cea 1029 goto fail1;
8ceee660 1030
dc8cfa55 1031 efx->port_initialized = true;
1dfc5cea 1032
d3245b28
BH
1033 /* Reconfigure the MAC before creating dma queues (required for
1034 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
710b208d 1035 efx->type->reconfigure_mac(efx);
d3245b28
BH
1036
1037 /* Ensure the PHY advertises the correct flow control settings */
1038 rc = efx->phy_op->reconfigure(efx);
1039 if (rc)
1040 goto fail2;
1041
1dfc5cea 1042 mutex_unlock(&efx->mac_lock);
8ceee660 1043 return 0;
177dfcd8 1044
1dfc5cea 1045fail2:
177dfcd8 1046 efx->phy_op->fini(efx);
1dfc5cea
BH
1047fail1:
1048 mutex_unlock(&efx->mac_lock);
177dfcd8 1049 return rc;
8ceee660
BH
1050}
1051
8ceee660
BH
1052static void efx_start_port(struct efx_nic *efx)
1053{
62776d03 1054 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
8ceee660
BH
1055 BUG_ON(efx->port_enabled);
1056
1057 mutex_lock(&efx->mac_lock);
dc8cfa55 1058 efx->port_enabled = true;
8be4f3e6
BH
1059
1060 /* efx_mac_work() might have been scheduled after efx_stop_port(),
1061 * and then cancelled by efx_flush_all() */
710b208d 1062 efx->type->reconfigure_mac(efx);
8be4f3e6 1063
8ceee660
BH
1064 mutex_unlock(&efx->mac_lock);
1065}
1066
fdaa9aed 1067/* Prevent efx_mac_work() and efx_monitor() from working */
8ceee660
BH
1068static void efx_stop_port(struct efx_nic *efx)
1069{
62776d03 1070 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
8ceee660
BH
1071
1072 mutex_lock(&efx->mac_lock);
dc8cfa55 1073 efx->port_enabled = false;
8ceee660
BH
1074 mutex_unlock(&efx->mac_lock);
1075
1076 /* Serialise against efx_set_multicast_list() */
73ba7b68
BH
1077 netif_addr_lock_bh(efx->net_dev);
1078 netif_addr_unlock_bh(efx->net_dev);
8ceee660
BH
1079}
1080
1081static void efx_fini_port(struct efx_nic *efx)
1082{
62776d03 1083 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
8ceee660
BH
1084
1085 if (!efx->port_initialized)
1086 return;
1087
177dfcd8 1088 efx->phy_op->fini(efx);
dc8cfa55 1089 efx->port_initialized = false;
8ceee660 1090
eb50c0d6 1091 efx->link_state.up = false;
8ceee660
BH
1092 efx_link_status_changed(efx);
1093}
1094
1095static void efx_remove_port(struct efx_nic *efx)
1096{
62776d03 1097 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
8ceee660 1098
ef2b90ee 1099 efx->type->remove_port(efx);
8ceee660
BH
1100}
1101
1102/**************************************************************************
1103 *
1104 * NIC handling
1105 *
1106 **************************************************************************/
1107
1108/* This configures the PCI device to enable I/O and DMA. */
1109static int efx_init_io(struct efx_nic *efx)
1110{
1111 struct pci_dev *pci_dev = efx->pci_dev;
1112 dma_addr_t dma_mask = efx->type->max_dma_mask;
1113 int rc;
1114
62776d03 1115 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
8ceee660
BH
1116
1117 rc = pci_enable_device(pci_dev);
1118 if (rc) {
62776d03
BH
1119 netif_err(efx, probe, efx->net_dev,
1120 "failed to enable PCI device\n");
8ceee660
BH
1121 goto fail1;
1122 }
1123
1124 pci_set_master(pci_dev);
1125
1126 /* Set the PCI DMA mask. Try all possibilities from our
1127 * genuine mask down to 32 bits, because some architectures
1128 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1129 * masks event though they reject 46 bit masks.
1130 */
1131 while (dma_mask > 0x7fffffffUL) {
0e33d870
BH
1132 if (dma_supported(&pci_dev->dev, dma_mask)) {
1133 rc = dma_set_mask(&pci_dev->dev, dma_mask);
e9e01846
BH
1134 if (rc == 0)
1135 break;
1136 }
8ceee660
BH
1137 dma_mask >>= 1;
1138 }
1139 if (rc) {
62776d03
BH
1140 netif_err(efx, probe, efx->net_dev,
1141 "could not find a suitable DMA mask\n");
8ceee660
BH
1142 goto fail2;
1143 }
62776d03
BH
1144 netif_dbg(efx, probe, efx->net_dev,
1145 "using DMA mask %llx\n", (unsigned long long) dma_mask);
0e33d870 1146 rc = dma_set_coherent_mask(&pci_dev->dev, dma_mask);
8ceee660 1147 if (rc) {
0e33d870
BH
1148 /* dma_set_coherent_mask() is not *allowed* to
1149 * fail with a mask that dma_set_mask() accepted,
8ceee660
BH
1150 * but just in case...
1151 */
62776d03
BH
1152 netif_err(efx, probe, efx->net_dev,
1153 "failed to set consistent DMA mask\n");
8ceee660
BH
1154 goto fail2;
1155 }
1156
dc803df8
BH
1157 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
1158 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
8ceee660 1159 if (rc) {
62776d03
BH
1160 netif_err(efx, probe, efx->net_dev,
1161 "request for memory BAR failed\n");
8ceee660
BH
1162 rc = -EIO;
1163 goto fail3;
1164 }
86c432ca
BH
1165 efx->membase = ioremap_nocache(efx->membase_phys,
1166 efx->type->mem_map_size);
8ceee660 1167 if (!efx->membase) {
62776d03
BH
1168 netif_err(efx, probe, efx->net_dev,
1169 "could not map memory BAR at %llx+%x\n",
1170 (unsigned long long)efx->membase_phys,
1171 efx->type->mem_map_size);
8ceee660
BH
1172 rc = -ENOMEM;
1173 goto fail4;
1174 }
62776d03
BH
1175 netif_dbg(efx, probe, efx->net_dev,
1176 "memory BAR at %llx+%x (virtual %p)\n",
1177 (unsigned long long)efx->membase_phys,
1178 efx->type->mem_map_size, efx->membase);
8ceee660
BH
1179
1180 return 0;
1181
1182 fail4:
dc803df8 1183 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
8ceee660 1184 fail3:
2c118e0f 1185 efx->membase_phys = 0;
8ceee660
BH
1186 fail2:
1187 pci_disable_device(efx->pci_dev);
1188 fail1:
1189 return rc;
1190}
1191
1192static void efx_fini_io(struct efx_nic *efx)
1193{
62776d03 1194 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
8ceee660
BH
1195
1196 if (efx->membase) {
1197 iounmap(efx->membase);
1198 efx->membase = NULL;
1199 }
1200
1201 if (efx->membase_phys) {
dc803df8 1202 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
2c118e0f 1203 efx->membase_phys = 0;
8ceee660
BH
1204 }
1205
1206 pci_disable_device(efx->pci_dev);
1207}
1208
a9a52506 1209static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
46123d04 1210{
cdb08f8f 1211 cpumask_var_t thread_mask;
a16e5b24 1212 unsigned int count;
46123d04 1213 int cpu;
5b874e25 1214
cd2d5b52
BH
1215 if (rss_cpus) {
1216 count = rss_cpus;
1217 } else {
1218 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
1219 netif_warn(efx, probe, efx->net_dev,
1220 "RSS disabled due to allocation failure\n");
1221 return 1;
1222 }
46123d04 1223
cd2d5b52
BH
1224 count = 0;
1225 for_each_online_cpu(cpu) {
1226 if (!cpumask_test_cpu(cpu, thread_mask)) {
1227 ++count;
1228 cpumask_or(thread_mask, thread_mask,
1229 topology_thread_cpumask(cpu));
1230 }
1231 }
1232
1233 free_cpumask_var(thread_mask);
2f8975fb
RR
1234 }
1235
cd2d5b52
BH
1236 /* If RSS is requested for the PF *and* VFs then we can't write RSS
1237 * table entries that are inaccessible to VFs
1238 */
1239 if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
1240 count > efx_vf_size(efx)) {
1241 netif_warn(efx, probe, efx->net_dev,
1242 "Reducing number of RSS channels from %u to %u for "
1243 "VF support. Increase vf-msix-limit to use more "
1244 "channels on the PF.\n",
1245 count, efx_vf_size(efx));
1246 count = efx_vf_size(efx);
46123d04
BH
1247 }
1248
1249 return count;
1250}
1251
64d8ad6d
BH
1252static int
1253efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries)
1254{
1255#ifdef CONFIG_RFS_ACCEL
a16e5b24
BH
1256 unsigned int i;
1257 int rc;
64d8ad6d
BH
1258
1259 efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels);
1260 if (!efx->net_dev->rx_cpu_rmap)
1261 return -ENOMEM;
1262 for (i = 0; i < efx->n_rx_channels; i++) {
1263 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
1264 xentries[i].vector);
1265 if (rc) {
1266 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
1267 efx->net_dev->rx_cpu_rmap = NULL;
1268 return rc;
1269 }
1270 }
1271#endif
1272 return 0;
1273}
1274
46123d04
BH
1275/* Probe the number and type of interrupts we are able to obtain, and
1276 * the resulting numbers of channels and RX queues.
1277 */
64d8ad6d 1278static int efx_probe_interrupts(struct efx_nic *efx)
8ceee660 1279{
a16e5b24
BH
1280 unsigned int max_channels =
1281 min(efx->type->phys_addr_channels, EFX_MAX_CHANNELS);
7f967c01
BH
1282 unsigned int extra_channels = 0;
1283 unsigned int i, j;
a16e5b24 1284 int rc;
8ceee660 1285
7f967c01
BH
1286 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
1287 if (efx->extra_channel_type[i])
1288 ++extra_channels;
1289
8ceee660 1290 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
46123d04 1291 struct msix_entry xentries[EFX_MAX_CHANNELS];
a16e5b24 1292 unsigned int n_channels;
aa6ef27e 1293
a9a52506 1294 n_channels = efx_wanted_parallelism(efx);
a4900ac9
BH
1295 if (separate_tx_channels)
1296 n_channels *= 2;
7f967c01 1297 n_channels += extra_channels;
a4900ac9 1298 n_channels = min(n_channels, max_channels);
8ceee660 1299
a4900ac9 1300 for (i = 0; i < n_channels; i++)
8ceee660 1301 xentries[i].entry = i;
a4900ac9 1302 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels);
8ceee660 1303 if (rc > 0) {
62776d03
BH
1304 netif_err(efx, drv, efx->net_dev,
1305 "WARNING: Insufficient MSI-X vectors"
a16e5b24 1306 " available (%d < %u).\n", rc, n_channels);
62776d03
BH
1307 netif_err(efx, drv, efx->net_dev,
1308 "WARNING: Performance may be reduced.\n");
a4900ac9
BH
1309 EFX_BUG_ON_PARANOID(rc >= n_channels);
1310 n_channels = rc;
8ceee660 1311 rc = pci_enable_msix(efx->pci_dev, xentries,
a4900ac9 1312 n_channels);
8ceee660
BH
1313 }
1314
1315 if (rc == 0) {
a4900ac9 1316 efx->n_channels = n_channels;
7f967c01
BH
1317 if (n_channels > extra_channels)
1318 n_channels -= extra_channels;
a4900ac9 1319 if (separate_tx_channels) {
7f967c01
BH
1320 efx->n_tx_channels = max(n_channels / 2, 1U);
1321 efx->n_rx_channels = max(n_channels -
1322 efx->n_tx_channels,
1323 1U);
a4900ac9 1324 } else {
7f967c01
BH
1325 efx->n_tx_channels = n_channels;
1326 efx->n_rx_channels = n_channels;
a4900ac9 1327 }
64d8ad6d
BH
1328 rc = efx_init_rx_cpu_rmap(efx, xentries);
1329 if (rc) {
1330 pci_disable_msix(efx->pci_dev);
1331 return rc;
1332 }
7f967c01 1333 for (i = 0; i < efx->n_channels; i++)
f7d12cdc
BH
1334 efx_get_channel(efx, i)->irq =
1335 xentries[i].vector;
8ceee660
BH
1336 } else {
1337 /* Fall back to single channel MSI */
1338 efx->interrupt_mode = EFX_INT_MODE_MSI;
62776d03
BH
1339 netif_err(efx, drv, efx->net_dev,
1340 "could not enable MSI-X\n");
8ceee660
BH
1341 }
1342 }
1343
1344 /* Try single interrupt MSI */
1345 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
28b581ab 1346 efx->n_channels = 1;
a4900ac9
BH
1347 efx->n_rx_channels = 1;
1348 efx->n_tx_channels = 1;
8ceee660
BH
1349 rc = pci_enable_msi(efx->pci_dev);
1350 if (rc == 0) {
f7d12cdc 1351 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
8ceee660 1352 } else {
62776d03
BH
1353 netif_err(efx, drv, efx->net_dev,
1354 "could not enable MSI\n");
8ceee660
BH
1355 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1356 }
1357 }
1358
1359 /* Assume legacy interrupts */
1360 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
28b581ab 1361 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
a4900ac9
BH
1362 efx->n_rx_channels = 1;
1363 efx->n_tx_channels = 1;
8ceee660
BH
1364 efx->legacy_irq = efx->pci_dev->irq;
1365 }
64d8ad6d 1366
7f967c01
BH
1367 /* Assign extra channels if possible */
1368 j = efx->n_channels;
1369 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
1370 if (!efx->extra_channel_type[i])
1371 continue;
1372 if (efx->interrupt_mode != EFX_INT_MODE_MSIX ||
1373 efx->n_channels <= extra_channels) {
1374 efx->extra_channel_type[i]->handle_no_channel(efx);
1375 } else {
1376 --j;
1377 efx_get_channel(efx, j)->type =
1378 efx->extra_channel_type[i];
1379 }
1380 }
1381
cd2d5b52 1382 /* RSS might be usable on VFs even if it is disabled on the PF */
3132d282 1383 efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ?
cd2d5b52
BH
1384 efx->n_rx_channels : efx_vf_size(efx));
1385
64d8ad6d 1386 return 0;
8ceee660
BH
1387}
1388
9f2cb71c 1389/* Enable interrupts, then probe and start the event queues */
7f967c01 1390static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq)
9f2cb71c
BH
1391{
1392 struct efx_channel *channel;
1393
8b7325b4
BH
1394 BUG_ON(efx->state == STATE_DISABLED);
1395
9f2cb71c
BH
1396 if (efx->legacy_irq)
1397 efx->legacy_irq_enabled = true;
1398 efx_nic_enable_interrupts(efx);
1399
1400 efx_for_each_channel(channel, efx) {
7f967c01
BH
1401 if (!channel->type->keep_eventq || !may_keep_eventq)
1402 efx_init_eventq(channel);
9f2cb71c
BH
1403 efx_start_eventq(channel);
1404 }
1405
1406 efx_mcdi_mode_event(efx);
1407}
1408
7f967c01 1409static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq)
9f2cb71c
BH
1410{
1411 struct efx_channel *channel;
1412
8b7325b4
BH
1413 if (efx->state == STATE_DISABLED)
1414 return;
1415
9f2cb71c
BH
1416 efx_mcdi_mode_poll(efx);
1417
1418 efx_nic_disable_interrupts(efx);
1419 if (efx->legacy_irq) {
1420 synchronize_irq(efx->legacy_irq);
1421 efx->legacy_irq_enabled = false;
1422 }
1423
1424 efx_for_each_channel(channel, efx) {
1425 if (channel->irq)
1426 synchronize_irq(channel->irq);
1427
1428 efx_stop_eventq(channel);
7f967c01
BH
1429 if (!channel->type->keep_eventq || !may_keep_eventq)
1430 efx_fini_eventq(channel);
9f2cb71c
BH
1431 }
1432}
1433
8ceee660
BH
1434static void efx_remove_interrupts(struct efx_nic *efx)
1435{
1436 struct efx_channel *channel;
1437
1438 /* Remove MSI/MSI-X interrupts */
64ee3120 1439 efx_for_each_channel(channel, efx)
8ceee660
BH
1440 channel->irq = 0;
1441 pci_disable_msi(efx->pci_dev);
1442 pci_disable_msix(efx->pci_dev);
1443
1444 /* Remove legacy interrupt */
1445 efx->legacy_irq = 0;
1446}
1447
8831da7b 1448static void efx_set_channels(struct efx_nic *efx)
8ceee660 1449{
602a5322
BH
1450 struct efx_channel *channel;
1451 struct efx_tx_queue *tx_queue;
1452
97653431 1453 efx->tx_channel_offset =
a4900ac9 1454 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0;
602a5322 1455
79d68b37
SH
1456 /* We need to mark which channels really have RX and TX
1457 * queues, and adjust the TX queue numbers if we have separate
602a5322
BH
1458 * RX-only and TX-only channels.
1459 */
1460 efx_for_each_channel(channel, efx) {
79d68b37
SH
1461 if (channel->channel < efx->n_rx_channels)
1462 channel->rx_queue.core_index = channel->channel;
1463 else
1464 channel->rx_queue.core_index = -1;
1465
602a5322
BH
1466 efx_for_each_channel_tx_queue(tx_queue, channel)
1467 tx_queue->queue -= (efx->tx_channel_offset *
1468 EFX_TXQ_TYPES);
1469 }
8ceee660
BH
1470}
1471
1472static int efx_probe_nic(struct efx_nic *efx)
1473{
765c9f46 1474 size_t i;
8ceee660
BH
1475 int rc;
1476
62776d03 1477 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
8ceee660
BH
1478
1479 /* Carry out hardware-type specific initialisation */
ef2b90ee 1480 rc = efx->type->probe(efx);
8ceee660
BH
1481 if (rc)
1482 return rc;
1483
a4900ac9 1484 /* Determine the number of channels and queues by trying to hook
8ceee660 1485 * in MSI-X interrupts. */
64d8ad6d
BH
1486 rc = efx_probe_interrupts(efx);
1487 if (rc)
1488 goto fail;
8ceee660 1489
28e47c49
BH
1490 efx->type->dimension_resources(efx);
1491
5d3a6fca
BH
1492 if (efx->n_channels > 1)
1493 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
765c9f46 1494 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
278bc429 1495 efx->rx_indir_table[i] =
cd2d5b52 1496 ethtool_rxfh_indir_default(i, efx->rss_spread);
5d3a6fca 1497
8831da7b 1498 efx_set_channels(efx);
c4f4adc7
BH
1499 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1500 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
8ceee660
BH
1501
1502 /* Initialise the interrupt moderation settings */
9e393b30
BH
1503 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
1504 true);
8ceee660
BH
1505
1506 return 0;
64d8ad6d
BH
1507
1508fail:
1509 efx->type->remove(efx);
1510 return rc;
8ceee660
BH
1511}
1512
1513static void efx_remove_nic(struct efx_nic *efx)
1514{
62776d03 1515 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
8ceee660
BH
1516
1517 efx_remove_interrupts(efx);
ef2b90ee 1518 efx->type->remove(efx);
8ceee660
BH
1519}
1520
1521/**************************************************************************
1522 *
1523 * NIC startup/shutdown
1524 *
1525 *************************************************************************/
1526
1527static int efx_probe_all(struct efx_nic *efx)
1528{
8ceee660
BH
1529 int rc;
1530
8ceee660
BH
1531 rc = efx_probe_nic(efx);
1532 if (rc) {
62776d03 1533 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
8ceee660
BH
1534 goto fail1;
1535 }
1536
8ceee660
BH
1537 rc = efx_probe_port(efx);
1538 if (rc) {
62776d03 1539 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
8ceee660
BH
1540 goto fail2;
1541 }
1542
7e6d06f0
BH
1543 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
1544 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
1545 rc = -EINVAL;
1546 goto fail3;
1547 }
ecc910f5 1548 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
8ceee660 1549
64eebcfd
BH
1550 rc = efx_probe_filters(efx);
1551 if (rc) {
1552 netif_err(efx, probe, efx->net_dev,
1553 "failed to create filter tables\n");
7f967c01 1554 goto fail3;
64eebcfd
BH
1555 }
1556
7f967c01
BH
1557 rc = efx_probe_channels(efx);
1558 if (rc)
1559 goto fail4;
1560
8ceee660
BH
1561 return 0;
1562
64eebcfd 1563 fail4:
7f967c01 1564 efx_remove_filters(efx);
8ceee660 1565 fail3:
8ceee660
BH
1566 efx_remove_port(efx);
1567 fail2:
1568 efx_remove_nic(efx);
1569 fail1:
1570 return rc;
1571}
1572
8b7325b4
BH
1573/* If the interface is supposed to be running but is not, start
1574 * the hardware and software data path, regular activity for the port
1575 * (MAC statistics, link polling, etc.) and schedule the port to be
1576 * reconfigured. Interrupts must already be enabled. This function
1577 * is safe to call multiple times, so long as the NIC is not disabled.
1578 * Requires the RTNL lock.
9f2cb71c 1579 */
8ceee660
BH
1580static void efx_start_all(struct efx_nic *efx)
1581{
8ceee660 1582 EFX_ASSERT_RESET_SERIALISED(efx);
8b7325b4 1583 BUG_ON(efx->state == STATE_DISABLED);
8ceee660
BH
1584
1585 /* Check that it is appropriate to restart the interface. All
1586 * of these flags are safe to read under just the rtnl lock */
8b7325b4 1587 if (efx->port_enabled || !netif_running(efx->net_dev))
8ceee660
BH
1588 return;
1589
8ceee660 1590 efx_start_port(efx);
9f2cb71c 1591 efx_start_datapath(efx);
8880f4ec 1592
78c1f0a0
SH
1593 /* Start the hardware monitor if there is one. Otherwise (we're link
1594 * event driven), we have to poll the PHY because after an event queue
1595 * flush, we could have a missed a link state change */
1596 if (efx->type->monitor != NULL) {
8ceee660
BH
1597 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1598 efx_monitor_interval);
78c1f0a0
SH
1599 } else {
1600 mutex_lock(&efx->mac_lock);
1601 if (efx->phy_op->poll(efx))
1602 efx_link_status_changed(efx);
1603 mutex_unlock(&efx->mac_lock);
1604 }
55edc6e6 1605
ef2b90ee 1606 efx->type->start_stats(efx);
8ceee660
BH
1607}
1608
1609/* Flush all delayed work. Should only be called when no more delayed work
1610 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1611 * since we're holding the rtnl_lock at this point. */
1612static void efx_flush_all(struct efx_nic *efx)
1613{
dd40781e 1614 /* Make sure the hardware monitor and event self-test are stopped */
8ceee660 1615 cancel_delayed_work_sync(&efx->monitor_work);
dd40781e 1616 efx_selftest_async_cancel(efx);
8ceee660 1617 /* Stop scheduled port reconfigurations */
766ca0fa 1618 cancel_work_sync(&efx->mac_work);
8ceee660
BH
1619}
1620
8b7325b4
BH
1621/* Quiesce the hardware and software data path, and regular activity
1622 * for the port without bringing the link down. Safe to call multiple
1623 * times with the NIC in almost any state, but interrupts should be
1624 * enabled. Requires the RTNL lock.
1625 */
8ceee660
BH
1626static void efx_stop_all(struct efx_nic *efx)
1627{
8ceee660
BH
1628 EFX_ASSERT_RESET_SERIALISED(efx);
1629
1630 /* port_enabled can be read safely under the rtnl lock */
1631 if (!efx->port_enabled)
1632 return;
1633
ef2b90ee 1634 efx->type->stop_stats(efx);
8ceee660
BH
1635 efx_stop_port(efx);
1636
fdaa9aed 1637 /* Flush efx_mac_work(), refill_workqueue, monitor_work */
8ceee660
BH
1638 efx_flush_all(efx);
1639
29c69a48
BH
1640 /* Stop the kernel transmit interface. This is only valid if
1641 * the device is stopped or detached; otherwise the watchdog
1642 * may fire immediately.
1643 */
1644 WARN_ON(netif_running(efx->net_dev) &&
1645 netif_device_present(efx->net_dev));
9f2cb71c
BH
1646 netif_tx_disable(efx->net_dev);
1647
1648 efx_stop_datapath(efx);
8ceee660
BH
1649}
1650
1651static void efx_remove_all(struct efx_nic *efx)
1652{
4642610c 1653 efx_remove_channels(efx);
7f967c01 1654 efx_remove_filters(efx);
8ceee660
BH
1655 efx_remove_port(efx);
1656 efx_remove_nic(efx);
1657}
1658
8ceee660
BH
1659/**************************************************************************
1660 *
1661 * Interrupt moderation
1662 *
1663 **************************************************************************/
1664
cc180b69 1665static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns)
0d86ebd8 1666{
b548f976
BH
1667 if (usecs == 0)
1668 return 0;
cc180b69 1669 if (usecs * 1000 < quantum_ns)
0d86ebd8 1670 return 1; /* never round down to 0 */
cc180b69 1671 return usecs * 1000 / quantum_ns;
0d86ebd8
BH
1672}
1673
8ceee660 1674/* Set interrupt moderation parameters */
9e393b30
BH
1675int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
1676 unsigned int rx_usecs, bool rx_adaptive,
1677 bool rx_may_override_tx)
8ceee660 1678{
f7d12cdc 1679 struct efx_channel *channel;
cc180b69
BH
1680 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max *
1681 efx->timer_quantum_ns,
1682 1000);
1683 unsigned int tx_ticks;
1684 unsigned int rx_ticks;
8ceee660
BH
1685
1686 EFX_ASSERT_RESET_SERIALISED(efx);
1687
cc180b69 1688 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max)
9e393b30
BH
1689 return -EINVAL;
1690
cc180b69
BH
1691 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns);
1692 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns);
1693
9e393b30
BH
1694 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 &&
1695 !rx_may_override_tx) {
1696 netif_err(efx, drv, efx->net_dev, "Channels are shared. "
1697 "RX and TX IRQ moderation must be equal\n");
1698 return -EINVAL;
1699 }
1700
6fb70fd1 1701 efx->irq_rx_adaptive = rx_adaptive;
0d86ebd8 1702 efx->irq_rx_moderation = rx_ticks;
f7d12cdc 1703 efx_for_each_channel(channel, efx) {
525da907 1704 if (efx_channel_has_rx_queue(channel))
f7d12cdc 1705 channel->irq_moderation = rx_ticks;
525da907 1706 else if (efx_channel_has_tx_queues(channel))
f7d12cdc
BH
1707 channel->irq_moderation = tx_ticks;
1708 }
9e393b30
BH
1709
1710 return 0;
8ceee660
BH
1711}
1712
a0c4faf5
BH
1713void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
1714 unsigned int *rx_usecs, bool *rx_adaptive)
1715{
cc180b69
BH
1716 /* We must round up when converting ticks to microseconds
1717 * because we round down when converting the other way.
1718 */
1719
a0c4faf5 1720 *rx_adaptive = efx->irq_rx_adaptive;
cc180b69
BH
1721 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation *
1722 efx->timer_quantum_ns,
1723 1000);
a0c4faf5
BH
1724
1725 /* If channels are shared between RX and TX, so is IRQ
1726 * moderation. Otherwise, IRQ moderation is the same for all
1727 * TX channels and is not adaptive.
1728 */
1729 if (efx->tx_channel_offset == 0)
1730 *tx_usecs = *rx_usecs;
1731 else
cc180b69 1732 *tx_usecs = DIV_ROUND_UP(
a0c4faf5 1733 efx->channel[efx->tx_channel_offset]->irq_moderation *
cc180b69
BH
1734 efx->timer_quantum_ns,
1735 1000);
a0c4faf5
BH
1736}
1737
8ceee660
BH
1738/**************************************************************************
1739 *
1740 * Hardware monitor
1741 *
1742 **************************************************************************/
1743
e254c274 1744/* Run periodically off the general workqueue */
8ceee660
BH
1745static void efx_monitor(struct work_struct *data)
1746{
1747 struct efx_nic *efx = container_of(data, struct efx_nic,
1748 monitor_work.work);
8ceee660 1749
62776d03
BH
1750 netif_vdbg(efx, timer, efx->net_dev,
1751 "hardware monitor executing on CPU %d\n",
1752 raw_smp_processor_id());
ef2b90ee 1753 BUG_ON(efx->type->monitor == NULL);
8ceee660 1754
8ceee660
BH
1755 /* If the mac_lock is already held then it is likely a port
1756 * reconfiguration is already in place, which will likely do
e254c274
BH
1757 * most of the work of monitor() anyway. */
1758 if (mutex_trylock(&efx->mac_lock)) {
1759 if (efx->port_enabled)
1760 efx->type->monitor(efx);
1761 mutex_unlock(&efx->mac_lock);
1762 }
8ceee660 1763
8ceee660
BH
1764 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1765 efx_monitor_interval);
1766}
1767
1768/**************************************************************************
1769 *
1770 * ioctls
1771 *
1772 *************************************************************************/
1773
1774/* Net device ioctl
1775 * Context: process, rtnl_lock() held.
1776 */
1777static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1778{
767e468c 1779 struct efx_nic *efx = netdev_priv(net_dev);
68e7f45e 1780 struct mii_ioctl_data *data = if_mii(ifr);
8ceee660 1781
7c236c43
SH
1782 if (cmd == SIOCSHWTSTAMP)
1783 return efx_ptp_ioctl(efx, ifr, cmd);
1784
68e7f45e
BH
1785 /* Convert phy_id from older PRTAD/DEVAD format */
1786 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1787 (data->phy_id & 0xfc00) == 0x0400)
1788 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1789
1790 return mdio_mii_ioctl(&efx->mdio, data, cmd);
8ceee660
BH
1791}
1792
1793/**************************************************************************
1794 *
1795 * NAPI interface
1796 *
1797 **************************************************************************/
1798
7f967c01
BH
1799static void efx_init_napi_channel(struct efx_channel *channel)
1800{
1801 struct efx_nic *efx = channel->efx;
1802
1803 channel->napi_dev = efx->net_dev;
1804 netif_napi_add(channel->napi_dev, &channel->napi_str,
1805 efx_poll, napi_weight);
1806}
1807
e8f14992 1808static void efx_init_napi(struct efx_nic *efx)
8ceee660
BH
1809{
1810 struct efx_channel *channel;
8ceee660 1811
7f967c01
BH
1812 efx_for_each_channel(channel, efx)
1813 efx_init_napi_channel(channel);
e8f14992
BH
1814}
1815
1816static void efx_fini_napi_channel(struct efx_channel *channel)
1817{
1818 if (channel->napi_dev)
1819 netif_napi_del(&channel->napi_str);
1820 channel->napi_dev = NULL;
8ceee660
BH
1821}
1822
1823static void efx_fini_napi(struct efx_nic *efx)
1824{
1825 struct efx_channel *channel;
1826
e8f14992
BH
1827 efx_for_each_channel(channel, efx)
1828 efx_fini_napi_channel(channel);
8ceee660
BH
1829}
1830
1831/**************************************************************************
1832 *
1833 * Kernel netpoll interface
1834 *
1835 *************************************************************************/
1836
1837#ifdef CONFIG_NET_POLL_CONTROLLER
1838
1839/* Although in the common case interrupts will be disabled, this is not
1840 * guaranteed. However, all our work happens inside the NAPI callback,
1841 * so no locking is required.
1842 */
1843static void efx_netpoll(struct net_device *net_dev)
1844{
767e468c 1845 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH
1846 struct efx_channel *channel;
1847
64ee3120 1848 efx_for_each_channel(channel, efx)
8ceee660
BH
1849 efx_schedule_channel(channel);
1850}
1851
1852#endif
1853
1854/**************************************************************************
1855 *
1856 * Kernel net device interface
1857 *
1858 *************************************************************************/
1859
1860/* Context: process, rtnl_lock() held. */
1861static int efx_net_open(struct net_device *net_dev)
1862{
767e468c 1863 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4
BH
1864 int rc;
1865
62776d03
BH
1866 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
1867 raw_smp_processor_id());
8ceee660 1868
8b7325b4
BH
1869 rc = efx_check_disabled(efx);
1870 if (rc)
1871 return rc;
f8b87c17
BH
1872 if (efx->phy_mode & PHY_MODE_SPECIAL)
1873 return -EBUSY;
8880f4ec
BH
1874 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
1875 return -EIO;
f8b87c17 1876
78c1f0a0
SH
1877 /* Notify the kernel of the link state polled during driver load,
1878 * before the monitor starts running */
1879 efx_link_status_changed(efx);
1880
8ceee660 1881 efx_start_all(efx);
dd40781e 1882 efx_selftest_async_start(efx);
8ceee660
BH
1883 return 0;
1884}
1885
1886/* Context: process, rtnl_lock() held.
1887 * Note that the kernel will ignore our return code; this method
1888 * should really be a void.
1889 */
1890static int efx_net_stop(struct net_device *net_dev)
1891{
767e468c 1892 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1893
62776d03
BH
1894 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
1895 raw_smp_processor_id());
8ceee660 1896
8b7325b4
BH
1897 /* Stop the device and flush all the channels */
1898 efx_stop_all(efx);
8ceee660
BH
1899
1900 return 0;
1901}
1902
5b9e207c 1903/* Context: process, dev_base_lock or RTNL held, non-blocking. */
2aa9ef11
BH
1904static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev,
1905 struct rtnl_link_stats64 *stats)
8ceee660 1906{
767e468c 1907 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1908 struct efx_mac_stats *mac_stats = &efx->mac_stats;
8ceee660 1909
55edc6e6 1910 spin_lock_bh(&efx->stats_lock);
1cb34522 1911
ef2b90ee 1912 efx->type->update_stats(efx);
8ceee660
BH
1913
1914 stats->rx_packets = mac_stats->rx_packets;
1915 stats->tx_packets = mac_stats->tx_packets;
1916 stats->rx_bytes = mac_stats->rx_bytes;
1917 stats->tx_bytes = mac_stats->tx_bytes;
80485d34 1918 stats->rx_dropped = efx->n_rx_nodesc_drop_cnt;
8ceee660
BH
1919 stats->multicast = mac_stats->rx_multicast;
1920 stats->collisions = mac_stats->tx_collision;
1921 stats->rx_length_errors = (mac_stats->rx_gtjumbo +
1922 mac_stats->rx_length_error);
8ceee660
BH
1923 stats->rx_crc_errors = mac_stats->rx_bad;
1924 stats->rx_frame_errors = mac_stats->rx_align_error;
1925 stats->rx_fifo_errors = mac_stats->rx_overflow;
1926 stats->rx_missed_errors = mac_stats->rx_missed;
1927 stats->tx_window_errors = mac_stats->tx_late_collision;
1928
1929 stats->rx_errors = (stats->rx_length_errors +
8ceee660
BH
1930 stats->rx_crc_errors +
1931 stats->rx_frame_errors +
8ceee660
BH
1932 mac_stats->rx_symbol_error);
1933 stats->tx_errors = (stats->tx_window_errors +
1934 mac_stats->tx_bad);
1935
1cb34522
BH
1936 spin_unlock_bh(&efx->stats_lock);
1937
8ceee660
BH
1938 return stats;
1939}
1940
1941/* Context: netif_tx_lock held, BHs disabled. */
1942static void efx_watchdog(struct net_device *net_dev)
1943{
767e468c 1944 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1945
62776d03
BH
1946 netif_err(efx, tx_err, efx->net_dev,
1947 "TX stuck with port_enabled=%d: resetting channels\n",
1948 efx->port_enabled);
8ceee660 1949
739bb23d 1950 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
8ceee660
BH
1951}
1952
1953
1954/* Context: process, rtnl_lock() held. */
1955static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
1956{
767e468c 1957 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4 1958 int rc;
8ceee660 1959
8b7325b4
BH
1960 rc = efx_check_disabled(efx);
1961 if (rc)
1962 return rc;
8ceee660
BH
1963 if (new_mtu > EFX_MAX_MTU)
1964 return -EINVAL;
1965
62776d03 1966 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
8ceee660 1967
29c69a48
BH
1968 efx_device_detach_sync(efx);
1969 efx_stop_all(efx);
1970
d3245b28 1971 mutex_lock(&efx->mac_lock);
8ceee660 1972 net_dev->mtu = new_mtu;
710b208d 1973 efx->type->reconfigure_mac(efx);
d3245b28
BH
1974 mutex_unlock(&efx->mac_lock);
1975
8ceee660 1976 efx_start_all(efx);
29c69a48 1977 netif_device_attach(efx->net_dev);
6c8eef4a 1978 return 0;
8ceee660
BH
1979}
1980
1981static int efx_set_mac_address(struct net_device *net_dev, void *data)
1982{
767e468c 1983 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH
1984 struct sockaddr *addr = data;
1985 char *new_addr = addr->sa_data;
1986
8ceee660 1987 if (!is_valid_ether_addr(new_addr)) {
62776d03
BH
1988 netif_err(efx, drv, efx->net_dev,
1989 "invalid ethernet MAC address requested: %pM\n",
1990 new_addr);
504f9b5a 1991 return -EADDRNOTAVAIL;
8ceee660
BH
1992 }
1993
1994 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
cd2d5b52 1995 efx_sriov_mac_address_changed(efx);
8ceee660
BH
1996
1997 /* Reconfigure the MAC */
d3245b28 1998 mutex_lock(&efx->mac_lock);
710b208d 1999 efx->type->reconfigure_mac(efx);
d3245b28 2000 mutex_unlock(&efx->mac_lock);
8ceee660
BH
2001
2002 return 0;
2003}
2004
a816f75a 2005/* Context: netif_addr_lock held, BHs disabled. */
0fca8c97 2006static void efx_set_rx_mode(struct net_device *net_dev)
8ceee660 2007{
767e468c 2008 struct efx_nic *efx = netdev_priv(net_dev);
22bedad3 2009 struct netdev_hw_addr *ha;
8ceee660 2010 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
8ceee660
BH
2011 u32 crc;
2012 int bit;
8ceee660 2013
8be4f3e6 2014 efx->promiscuous = !!(net_dev->flags & IFF_PROMISC);
8ceee660
BH
2015
2016 /* Build multicast hash table */
8be4f3e6 2017 if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) {
8ceee660
BH
2018 memset(mc_hash, 0xff, sizeof(*mc_hash));
2019 } else {
2020 memset(mc_hash, 0x00, sizeof(*mc_hash));
22bedad3
JP
2021 netdev_for_each_mc_addr(ha, net_dev) {
2022 crc = ether_crc_le(ETH_ALEN, ha->addr);
8ceee660 2023 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
32766ec8 2024 __set_bit_le(bit, mc_hash);
8ceee660 2025 }
8ceee660 2026
8be4f3e6
BH
2027 /* Broadcast packets go through the multicast hash filter.
2028 * ether_crc_le() of the broadcast address is 0xbe2612ff
2029 * so we always add bit 0xff to the mask.
2030 */
32766ec8 2031 __set_bit_le(0xff, mc_hash);
8be4f3e6 2032 }
a816f75a 2033
8be4f3e6
BH
2034 if (efx->port_enabled)
2035 queue_work(efx->workqueue, &efx->mac_work);
2036 /* Otherwise efx_start_port() will do this */
8ceee660
BH
2037}
2038
c8f44aff 2039static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
abfe9039
BH
2040{
2041 struct efx_nic *efx = netdev_priv(net_dev);
2042
2043 /* If disabling RX n-tuple filtering, clear existing filters */
2044 if (net_dev->features & ~data & NETIF_F_NTUPLE)
2045 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
2046
2047 return 0;
2048}
2049
c3ecb9f3
SH
2050static const struct net_device_ops efx_netdev_ops = {
2051 .ndo_open = efx_net_open,
2052 .ndo_stop = efx_net_stop,
4472702e 2053 .ndo_get_stats64 = efx_net_stats,
c3ecb9f3
SH
2054 .ndo_tx_timeout = efx_watchdog,
2055 .ndo_start_xmit = efx_hard_start_xmit,
2056 .ndo_validate_addr = eth_validate_addr,
2057 .ndo_do_ioctl = efx_ioctl,
2058 .ndo_change_mtu = efx_change_mtu,
2059 .ndo_set_mac_address = efx_set_mac_address,
0fca8c97 2060 .ndo_set_rx_mode = efx_set_rx_mode,
abfe9039 2061 .ndo_set_features = efx_set_features,
cd2d5b52
BH
2062#ifdef CONFIG_SFC_SRIOV
2063 .ndo_set_vf_mac = efx_sriov_set_vf_mac,
2064 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
2065 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
2066 .ndo_get_vf_config = efx_sriov_get_vf_config,
2067#endif
c3ecb9f3
SH
2068#ifdef CONFIG_NET_POLL_CONTROLLER
2069 .ndo_poll_controller = efx_netpoll,
2070#endif
94b274bf 2071 .ndo_setup_tc = efx_setup_tc,
64d8ad6d
BH
2072#ifdef CONFIG_RFS_ACCEL
2073 .ndo_rx_flow_steer = efx_filter_rfs,
2074#endif
c3ecb9f3
SH
2075};
2076
7dde596e
BH
2077static void efx_update_name(struct efx_nic *efx)
2078{
2079 strcpy(efx->name, efx->net_dev->name);
2080 efx_mtd_rename(efx);
2081 efx_set_channel_names(efx);
2082}
2083
8ceee660
BH
2084static int efx_netdev_event(struct notifier_block *this,
2085 unsigned long event, void *ptr)
2086{
d3208b5e 2087 struct net_device *net_dev = ptr;
8ceee660 2088
7dde596e
BH
2089 if (net_dev->netdev_ops == &efx_netdev_ops &&
2090 event == NETDEV_CHANGENAME)
2091 efx_update_name(netdev_priv(net_dev));
8ceee660
BH
2092
2093 return NOTIFY_DONE;
2094}
2095
2096static struct notifier_block efx_netdev_notifier = {
2097 .notifier_call = efx_netdev_event,
2098};
2099
06d5e193
BH
2100static ssize_t
2101show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
2102{
2103 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2104 return sprintf(buf, "%d\n", efx->phy_type);
2105}
2106static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL);
2107
8ceee660
BH
2108static int efx_register_netdev(struct efx_nic *efx)
2109{
2110 struct net_device *net_dev = efx->net_dev;
c04bfc6b 2111 struct efx_channel *channel;
8ceee660
BH
2112 int rc;
2113
2114 net_dev->watchdog_timeo = 5 * HZ;
2115 net_dev->irq = efx->pci_dev->irq;
c3ecb9f3 2116 net_dev->netdev_ops = &efx_netdev_ops;
8ceee660 2117 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
7e6d06f0 2118 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
8ceee660 2119
7dde596e 2120 rtnl_lock();
aed0628d 2121
7153f623
BH
2122 /* Enable resets to be scheduled and check whether any were
2123 * already requested. If so, the NIC is probably hosed so we
2124 * abort.
2125 */
2126 efx->state = STATE_READY;
2127 smp_mb(); /* ensure we change state before checking reset_pending */
2128 if (efx->reset_pending) {
2129 netif_err(efx, probe, efx->net_dev,
2130 "aborting probe due to scheduled reset\n");
2131 rc = -EIO;
2132 goto fail_locked;
2133 }
2134
aed0628d
BH
2135 rc = dev_alloc_name(net_dev, net_dev->name);
2136 if (rc < 0)
2137 goto fail_locked;
7dde596e 2138 efx_update_name(efx);
aed0628d 2139
8f8b3d51
BH
2140 /* Always start with carrier off; PHY events will detect the link */
2141 netif_carrier_off(net_dev);
2142
aed0628d
BH
2143 rc = register_netdevice(net_dev);
2144 if (rc)
2145 goto fail_locked;
2146
c04bfc6b
BH
2147 efx_for_each_channel(channel, efx) {
2148 struct efx_tx_queue *tx_queue;
60031fcc
BH
2149 efx_for_each_channel_tx_queue(tx_queue, channel)
2150 efx_init_tx_queue_core_txq(tx_queue);
c04bfc6b
BH
2151 }
2152
7dde596e 2153 rtnl_unlock();
8ceee660 2154
06d5e193
BH
2155 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2156 if (rc) {
62776d03
BH
2157 netif_err(efx, drv, efx->net_dev,
2158 "failed to init net dev attributes\n");
06d5e193
BH
2159 goto fail_registered;
2160 }
2161
8ceee660 2162 return 0;
06d5e193 2163
7153f623
BH
2164fail_registered:
2165 rtnl_lock();
2166 unregister_netdevice(net_dev);
aed0628d 2167fail_locked:
7153f623 2168 efx->state = STATE_UNINIT;
aed0628d 2169 rtnl_unlock();
62776d03 2170 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
aed0628d 2171 return rc;
8ceee660
BH
2172}
2173
2174static void efx_unregister_netdev(struct efx_nic *efx)
2175{
f7d12cdc 2176 struct efx_channel *channel;
8ceee660
BH
2177 struct efx_tx_queue *tx_queue;
2178
2179 if (!efx->net_dev)
2180 return;
2181
767e468c 2182 BUG_ON(netdev_priv(efx->net_dev) != efx);
8ceee660
BH
2183
2184 /* Free up any skbs still remaining. This has to happen before
2185 * we try to unregister the netdev as running their destructors
2186 * may be needed to get the device ref. count to 0. */
f7d12cdc
BH
2187 efx_for_each_channel(channel, efx) {
2188 efx_for_each_channel_tx_queue(tx_queue, channel)
2189 efx_release_tx_buffers(tx_queue);
2190 }
8ceee660 2191
73ba7b68
BH
2192 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2193 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
7153f623
BH
2194
2195 rtnl_lock();
2196 unregister_netdevice(efx->net_dev);
2197 efx->state = STATE_UNINIT;
2198 rtnl_unlock();
8ceee660
BH
2199}
2200
2201/**************************************************************************
2202 *
2203 * Device reset and suspend
2204 *
2205 **************************************************************************/
2206
2467ca46
BH
2207/* Tears down the entire software state and most of the hardware state
2208 * before reset. */
d3245b28 2209void efx_reset_down(struct efx_nic *efx, enum reset_type method)
8ceee660 2210{
8ceee660
BH
2211 EFX_ASSERT_RESET_SERIALISED(efx);
2212
2467ca46 2213 efx_stop_all(efx);
7f967c01 2214 efx_stop_interrupts(efx, false);
5642ceef
BH
2215
2216 mutex_lock(&efx->mac_lock);
4b988280
SH
2217 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
2218 efx->phy_op->fini(efx);
ef2b90ee 2219 efx->type->fini(efx);
8ceee660
BH
2220}
2221
2467ca46
BH
2222/* This function will always ensure that the locks acquired in
2223 * efx_reset_down() are released. A failure return code indicates
2224 * that we were unable to reinitialise the hardware, and the
2225 * driver should be disabled. If ok is false, then the rx and tx
2226 * engines are not restarted, pending a RESET_DISABLE. */
d3245b28 2227int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
8ceee660
BH
2228{
2229 int rc;
2230
2467ca46 2231 EFX_ASSERT_RESET_SERIALISED(efx);
8ceee660 2232
ef2b90ee 2233 rc = efx->type->init(efx);
8ceee660 2234 if (rc) {
62776d03 2235 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
eb9f6744 2236 goto fail;
8ceee660
BH
2237 }
2238
eb9f6744
BH
2239 if (!ok)
2240 goto fail;
2241
4b988280 2242 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
eb9f6744
BH
2243 rc = efx->phy_op->init(efx);
2244 if (rc)
2245 goto fail;
2246 if (efx->phy_op->reconfigure(efx))
62776d03
BH
2247 netif_err(efx, drv, efx->net_dev,
2248 "could not restore PHY settings\n");
4b988280
SH
2249 }
2250
710b208d 2251 efx->type->reconfigure_mac(efx);
8ceee660 2252
7f967c01 2253 efx_start_interrupts(efx, false);
64eebcfd 2254 efx_restore_filters(efx);
cd2d5b52 2255 efx_sriov_reset(efx);
eb9f6744 2256
eb9f6744
BH
2257 mutex_unlock(&efx->mac_lock);
2258
2259 efx_start_all(efx);
2260
2261 return 0;
2262
2263fail:
2264 efx->port_initialized = false;
2467ca46
BH
2265
2266 mutex_unlock(&efx->mac_lock);
2267
8ceee660
BH
2268 return rc;
2269}
2270
eb9f6744
BH
2271/* Reset the NIC using the specified method. Note that the reset may
2272 * fail, in which case the card will be left in an unusable state.
8ceee660 2273 *
eb9f6744 2274 * Caller must hold the rtnl_lock.
8ceee660 2275 */
eb9f6744 2276int efx_reset(struct efx_nic *efx, enum reset_type method)
8ceee660 2277{
eb9f6744
BH
2278 int rc, rc2;
2279 bool disabled;
8ceee660 2280
62776d03
BH
2281 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2282 RESET_TYPE(method));
8ceee660 2283
c2f3b8e3 2284 efx_device_detach_sync(efx);
d3245b28 2285 efx_reset_down(efx, method);
8ceee660 2286
ef2b90ee 2287 rc = efx->type->reset(efx, method);
8ceee660 2288 if (rc) {
62776d03 2289 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
eb9f6744 2290 goto out;
8ceee660
BH
2291 }
2292
a7d529ae
BH
2293 /* Clear flags for the scopes we covered. We assume the NIC and
2294 * driver are now quiescent so that there is no race here.
2295 */
2296 efx->reset_pending &= -(1 << (method + 1));
8ceee660
BH
2297
2298 /* Reinitialise bus-mastering, which may have been turned off before
2299 * the reset was scheduled. This is still appropriate, even in the
2300 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2301 * can respond to requests. */
2302 pci_set_master(efx->pci_dev);
2303
eb9f6744 2304out:
8ceee660 2305 /* Leave device stopped if necessary */
eb9f6744
BH
2306 disabled = rc || method == RESET_TYPE_DISABLE;
2307 rc2 = efx_reset_up(efx, method, !disabled);
2308 if (rc2) {
2309 disabled = true;
2310 if (!rc)
2311 rc = rc2;
8ceee660
BH
2312 }
2313
eb9f6744 2314 if (disabled) {
f49a4589 2315 dev_close(efx->net_dev);
62776d03 2316 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
f4bd954e 2317 efx->state = STATE_DISABLED;
f4bd954e 2318 } else {
62776d03 2319 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
e4abce85 2320 netif_device_attach(efx->net_dev);
f4bd954e 2321 }
8ceee660
BH
2322 return rc;
2323}
2324
2325/* The worker thread exists so that code that cannot sleep can
2326 * schedule a reset for later.
2327 */
2328static void efx_reset_work(struct work_struct *data)
2329{
eb9f6744 2330 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
a7d529ae 2331 unsigned long pending = ACCESS_ONCE(efx->reset_pending);
8ceee660 2332
a7d529ae 2333 if (!pending)
319ba649
SH
2334 return;
2335
eb9f6744 2336 rtnl_lock();
7153f623
BH
2337
2338 /* We checked the state in efx_schedule_reset() but it may
2339 * have changed by now. Now that we have the RTNL lock,
2340 * it cannot change again.
2341 */
2342 if (efx->state == STATE_READY)
2343 (void)efx_reset(efx, fls(pending) - 1);
2344
eb9f6744 2345 rtnl_unlock();
8ceee660
BH
2346}
2347
2348void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2349{
2350 enum reset_type method;
2351
8ceee660
BH
2352 switch (type) {
2353 case RESET_TYPE_INVISIBLE:
2354 case RESET_TYPE_ALL:
2355 case RESET_TYPE_WORLD:
2356 case RESET_TYPE_DISABLE:
2357 method = type;
0e2a9c7c
BH
2358 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2359 RESET_TYPE(method));
8ceee660 2360 break;
8ceee660 2361 default:
0e2a9c7c 2362 method = efx->type->map_reset_reason(type);
62776d03
BH
2363 netif_dbg(efx, drv, efx->net_dev,
2364 "scheduling %s reset for %s\n",
2365 RESET_TYPE(method), RESET_TYPE(type));
0e2a9c7c
BH
2366 break;
2367 }
8ceee660 2368
a7d529ae 2369 set_bit(method, &efx->reset_pending);
7153f623
BH
2370 smp_mb(); /* ensure we change reset_pending before checking state */
2371
2372 /* If we're not READY then just leave the flags set as the cue
2373 * to abort probing or reschedule the reset later.
2374 */
2375 if (ACCESS_ONCE(efx->state) != STATE_READY)
2376 return;
8ceee660 2377
8880f4ec
BH
2378 /* efx_process_channel() will no longer read events once a
2379 * reset is scheduled. So switch back to poll'd MCDI completions. */
2380 efx_mcdi_mode_poll(efx);
2381
1ab00629 2382 queue_work(reset_workqueue, &efx->reset_work);
8ceee660
BH
2383}
2384
2385/**************************************************************************
2386 *
2387 * List of NICs we support
2388 *
2389 **************************************************************************/
2390
2391/* PCI device ID table */
a3aa1884 2392static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
937383a5
BH
2393 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2394 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0),
daeda630 2395 .driver_data = (unsigned long) &falcon_a1_nic_type},
937383a5
BH
2396 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2397 PCI_DEVICE_ID_SOLARFLARE_SFC4000B),
daeda630 2398 .driver_data = (unsigned long) &falcon_b0_nic_type},
547c474f 2399 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
8880f4ec 2400 .driver_data = (unsigned long) &siena_a0_nic_type},
547c474f 2401 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
8880f4ec 2402 .driver_data = (unsigned long) &siena_a0_nic_type},
8ceee660
BH
2403 {0} /* end of list */
2404};
2405
2406/**************************************************************************
2407 *
3759433d 2408 * Dummy PHY/MAC operations
8ceee660 2409 *
01aad7b6 2410 * Can be used for some unimplemented operations
8ceee660
BH
2411 * Needed so all function pointers are valid and do not have to be tested
2412 * before use
2413 *
2414 **************************************************************************/
2415int efx_port_dummy_op_int(struct efx_nic *efx)
2416{
2417 return 0;
2418}
2419void efx_port_dummy_op_void(struct efx_nic *efx) {}
d215697f 2420
2421static bool efx_port_dummy_op_poll(struct efx_nic *efx)
fdaa9aed
SH
2422{
2423 return false;
2424}
8ceee660 2425
6c8c2513 2426static const struct efx_phy_operations efx_dummy_phy_operations = {
8ceee660 2427 .init = efx_port_dummy_op_int,
d3245b28 2428 .reconfigure = efx_port_dummy_op_int,
fdaa9aed 2429 .poll = efx_port_dummy_op_poll,
8ceee660 2430 .fini = efx_port_dummy_op_void,
8ceee660
BH
2431};
2432
8ceee660
BH
2433/**************************************************************************
2434 *
2435 * Data housekeeping
2436 *
2437 **************************************************************************/
2438
2439/* This zeroes out and then fills in the invariants in a struct
2440 * efx_nic (including all sub-structures).
2441 */
adeb15aa 2442static int efx_init_struct(struct efx_nic *efx,
8ceee660
BH
2443 struct pci_dev *pci_dev, struct net_device *net_dev)
2444{
4642610c 2445 int i;
8ceee660
BH
2446
2447 /* Initialise common structures */
8ceee660 2448 spin_lock_init(&efx->biu_lock);
76884835
BH
2449#ifdef CONFIG_SFC_MTD
2450 INIT_LIST_HEAD(&efx->mtd_list);
2451#endif
8ceee660
BH
2452 INIT_WORK(&efx->reset_work, efx_reset_work);
2453 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
dd40781e 2454 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
8ceee660 2455 efx->pci_dev = pci_dev;
62776d03 2456 efx->msg_enable = debug;
f16aeea0 2457 efx->state = STATE_UNINIT;
8ceee660 2458 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
8ceee660
BH
2459
2460 efx->net_dev = net_dev;
8ceee660
BH
2461 spin_lock_init(&efx->stats_lock);
2462 mutex_init(&efx->mac_lock);
2463 efx->phy_op = &efx_dummy_phy_operations;
68e7f45e 2464 efx->mdio.dev = net_dev;
766ca0fa 2465 INIT_WORK(&efx->mac_work, efx_mac_work);
9f2cb71c 2466 init_waitqueue_head(&efx->flush_wq);
8ceee660
BH
2467
2468 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
4642610c
BH
2469 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2470 if (!efx->channel[i])
2471 goto fail;
8ceee660
BH
2472 }
2473
8ceee660
BH
2474 EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS);
2475
2476 /* Higher numbered interrupt modes are less capable! */
2477 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2478 interrupt_mode);
2479
6977dc63
BH
2480 /* Would be good to use the net_dev name, but we're too early */
2481 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2482 pci_name(pci_dev));
2483 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1ab00629 2484 if (!efx->workqueue)
4642610c 2485 goto fail;
8d9853d9 2486
8ceee660 2487 return 0;
4642610c
BH
2488
2489fail:
2490 efx_fini_struct(efx);
2491 return -ENOMEM;
8ceee660
BH
2492}
2493
2494static void efx_fini_struct(struct efx_nic *efx)
2495{
8313aca3
BH
2496 int i;
2497
2498 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2499 kfree(efx->channel[i]);
2500
8ceee660
BH
2501 if (efx->workqueue) {
2502 destroy_workqueue(efx->workqueue);
2503 efx->workqueue = NULL;
2504 }
2505}
2506
2507/**************************************************************************
2508 *
2509 * PCI interface
2510 *
2511 **************************************************************************/
2512
2513/* Main body of final NIC shutdown code
2514 * This is called only at module unload (or hotplug removal).
2515 */
2516static void efx_pci_remove_main(struct efx_nic *efx)
2517{
7153f623
BH
2518 /* Flush reset_work. It can no longer be scheduled since we
2519 * are not READY.
2520 */
2521 BUG_ON(efx->state == STATE_READY);
2522 cancel_work_sync(&efx->reset_work);
2523
64d8ad6d
BH
2524#ifdef CONFIG_RFS_ACCEL
2525 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
2526 efx->net_dev->rx_cpu_rmap = NULL;
2527#endif
7f967c01 2528 efx_stop_interrupts(efx, false);
152b6a62 2529 efx_nic_fini_interrupt(efx);
8ceee660 2530 efx_fini_port(efx);
ef2b90ee 2531 efx->type->fini(efx);
8ceee660
BH
2532 efx_fini_napi(efx);
2533 efx_remove_all(efx);
2534}
2535
2536/* Final NIC shutdown
2537 * This is called only at module unload (or hotplug removal).
2538 */
2539static void efx_pci_remove(struct pci_dev *pci_dev)
2540{
2541 struct efx_nic *efx;
2542
2543 efx = pci_get_drvdata(pci_dev);
2544 if (!efx)
2545 return;
2546
2547 /* Mark the NIC as fini, then stop the interface */
2548 rtnl_lock();
8ceee660 2549 dev_close(efx->net_dev);
5642ceef 2550 efx_stop_interrupts(efx, false);
8ceee660
BH
2551 rtnl_unlock();
2552
cd2d5b52 2553 efx_sriov_fini(efx);
8ceee660
BH
2554 efx_unregister_netdev(efx);
2555
7dde596e
BH
2556 efx_mtd_remove(efx);
2557
8ceee660
BH
2558 efx_pci_remove_main(efx);
2559
8ceee660 2560 efx_fini_io(efx);
62776d03 2561 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
8ceee660 2562
8ceee660 2563 efx_fini_struct(efx);
3de4e301 2564 pci_set_drvdata(pci_dev, NULL);
8ceee660
BH
2565 free_netdev(efx->net_dev);
2566};
2567
460eeaa0
BH
2568/* NIC VPD information
2569 * Called during probe to display the part number of the
2570 * installed NIC. VPD is potentially very large but this should
2571 * always appear within the first 512 bytes.
2572 */
2573#define SFC_VPD_LEN 512
2574static void efx_print_product_vpd(struct efx_nic *efx)
2575{
2576 struct pci_dev *dev = efx->pci_dev;
2577 char vpd_data[SFC_VPD_LEN];
2578 ssize_t vpd_size;
2579 int i, j;
2580
2581 /* Get the vpd data from the device */
2582 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
2583 if (vpd_size <= 0) {
2584 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
2585 return;
2586 }
2587
2588 /* Get the Read only section */
2589 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
2590 if (i < 0) {
2591 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
2592 return;
2593 }
2594
2595 j = pci_vpd_lrdt_size(&vpd_data[i]);
2596 i += PCI_VPD_LRDT_TAG_SIZE;
2597 if (i + j > vpd_size)
2598 j = vpd_size - i;
2599
2600 /* Get the Part number */
2601 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
2602 if (i < 0) {
2603 netif_err(efx, drv, efx->net_dev, "Part number not found\n");
2604 return;
2605 }
2606
2607 j = pci_vpd_info_field_size(&vpd_data[i]);
2608 i += PCI_VPD_INFO_FLD_HDR_SIZE;
2609 if (i + j > vpd_size) {
2610 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
2611 return;
2612 }
2613
2614 netif_info(efx, drv, efx->net_dev,
2615 "Part Number : %.*s\n", j, &vpd_data[i]);
2616}
2617
2618
8ceee660
BH
2619/* Main body of NIC initialisation
2620 * This is called at module load (or hotplug insertion, theoretically).
2621 */
2622static int efx_pci_probe_main(struct efx_nic *efx)
2623{
2624 int rc;
2625
2626 /* Do start-of-day initialisation */
2627 rc = efx_probe_all(efx);
2628 if (rc)
2629 goto fail1;
2630
e8f14992 2631 efx_init_napi(efx);
8ceee660 2632
ef2b90ee 2633 rc = efx->type->init(efx);
8ceee660 2634 if (rc) {
62776d03
BH
2635 netif_err(efx, probe, efx->net_dev,
2636 "failed to initialise NIC\n");
278c0621 2637 goto fail3;
8ceee660
BH
2638 }
2639
2640 rc = efx_init_port(efx);
2641 if (rc) {
62776d03
BH
2642 netif_err(efx, probe, efx->net_dev,
2643 "failed to initialise port\n");
278c0621 2644 goto fail4;
8ceee660
BH
2645 }
2646
152b6a62 2647 rc = efx_nic_init_interrupt(efx);
8ceee660 2648 if (rc)
278c0621 2649 goto fail5;
7f967c01 2650 efx_start_interrupts(efx, false);
8ceee660
BH
2651
2652 return 0;
2653
278c0621 2654 fail5:
8ceee660 2655 efx_fini_port(efx);
8ceee660 2656 fail4:
ef2b90ee 2657 efx->type->fini(efx);
8ceee660
BH
2658 fail3:
2659 efx_fini_napi(efx);
8ceee660
BH
2660 efx_remove_all(efx);
2661 fail1:
2662 return rc;
2663}
2664
2665/* NIC initialisation
2666 *
2667 * This is called at module load (or hotplug insertion,
73ba7b68 2668 * theoretically). It sets up PCI mappings, resets the NIC,
8ceee660
BH
2669 * sets up and registers the network devices with the kernel and hooks
2670 * the interrupt service routine. It does not prepare the device for
2671 * transmission; this is left to the first time one of the network
2672 * interfaces is brought up (i.e. efx_net_open).
2673 */
87d1fc11 2674static int efx_pci_probe(struct pci_dev *pci_dev,
1dd06ae8 2675 const struct pci_device_id *entry)
8ceee660 2676{
8ceee660
BH
2677 struct net_device *net_dev;
2678 struct efx_nic *efx;
fadac6aa 2679 int rc;
8ceee660
BH
2680
2681 /* Allocate and initialise a struct net_device and struct efx_nic */
94b274bf
BH
2682 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
2683 EFX_MAX_RX_QUEUES);
8ceee660
BH
2684 if (!net_dev)
2685 return -ENOMEM;
adeb15aa
BH
2686 efx = netdev_priv(net_dev);
2687 efx->type = (const struct efx_nic_type *) entry->driver_data;
2688 net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
97bc5415 2689 NETIF_F_HIGHDMA | NETIF_F_TSO |
abfe9039 2690 NETIF_F_RXCSUM);
adeb15aa 2691 if (efx->type->offload_features & NETIF_F_V6_CSUM)
738a8f4b 2692 net_dev->features |= NETIF_F_TSO6;
28506563
BH
2693 /* Mask for features that also apply to VLAN devices */
2694 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
abfe9039
BH
2695 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
2696 NETIF_F_RXCSUM);
2697 /* All offloads can be toggled */
2698 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA;
8ceee660 2699 pci_set_drvdata(pci_dev, efx);
62776d03 2700 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
adeb15aa 2701 rc = efx_init_struct(efx, pci_dev, net_dev);
8ceee660
BH
2702 if (rc)
2703 goto fail1;
2704
62776d03 2705 netif_info(efx, probe, efx->net_dev,
ff79c8ac 2706 "Solarflare NIC detected\n");
8ceee660 2707
460eeaa0
BH
2708 efx_print_product_vpd(efx);
2709
8ceee660
BH
2710 /* Set up basic I/O (BAR mappings etc) */
2711 rc = efx_init_io(efx);
2712 if (rc)
2713 goto fail2;
2714
fadac6aa 2715 rc = efx_pci_probe_main(efx);
fadac6aa
BH
2716 if (rc)
2717 goto fail3;
8ceee660 2718
8ceee660
BH
2719 rc = efx_register_netdev(efx);
2720 if (rc)
fadac6aa 2721 goto fail4;
8ceee660 2722
cd2d5b52
BH
2723 rc = efx_sriov_init(efx);
2724 if (rc)
2725 netif_err(efx, probe, efx->net_dev,
2726 "SR-IOV can't be enabled rc %d\n", rc);
2727
62776d03 2728 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
a5211bb5 2729
7c43161c 2730 /* Try to create MTDs, but allow this to fail */
a5211bb5 2731 rtnl_lock();
7c43161c 2732 rc = efx_mtd_probe(efx);
a5211bb5 2733 rtnl_unlock();
7c43161c
BH
2734 if (rc)
2735 netif_warn(efx, probe, efx->net_dev,
2736 "failed to create MTDs (%d)\n", rc);
2737
8ceee660
BH
2738 return 0;
2739
8ceee660 2740 fail4:
fadac6aa 2741 efx_pci_remove_main(efx);
8ceee660
BH
2742 fail3:
2743 efx_fini_io(efx);
2744 fail2:
2745 efx_fini_struct(efx);
2746 fail1:
3de4e301 2747 pci_set_drvdata(pci_dev, NULL);
5e2a911c 2748 WARN_ON(rc > 0);
62776d03 2749 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
8ceee660
BH
2750 free_netdev(net_dev);
2751 return rc;
2752}
2753
89c758fa
BH
2754static int efx_pm_freeze(struct device *dev)
2755{
2756 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2757
61da026d
BH
2758 rtnl_lock();
2759
6032fb56
BH
2760 if (efx->state != STATE_DISABLED) {
2761 efx->state = STATE_UNINIT;
89c758fa 2762
c2f3b8e3 2763 efx_device_detach_sync(efx);
89c758fa 2764
6032fb56
BH
2765 efx_stop_all(efx);
2766 efx_stop_interrupts(efx, false);
2767 }
89c758fa 2768
61da026d
BH
2769 rtnl_unlock();
2770
89c758fa
BH
2771 return 0;
2772}
2773
2774static int efx_pm_thaw(struct device *dev)
2775{
2776 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2777
61da026d
BH
2778 rtnl_lock();
2779
6032fb56
BH
2780 if (efx->state != STATE_DISABLED) {
2781 efx_start_interrupts(efx, false);
89c758fa 2782
6032fb56
BH
2783 mutex_lock(&efx->mac_lock);
2784 efx->phy_op->reconfigure(efx);
2785 mutex_unlock(&efx->mac_lock);
89c758fa 2786
6032fb56 2787 efx_start_all(efx);
89c758fa 2788
6032fb56 2789 netif_device_attach(efx->net_dev);
89c758fa 2790
6032fb56 2791 efx->state = STATE_READY;
89c758fa 2792
6032fb56
BH
2793 efx->type->resume_wol(efx);
2794 }
89c758fa 2795
61da026d
BH
2796 rtnl_unlock();
2797
319ba649
SH
2798 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
2799 queue_work(reset_workqueue, &efx->reset_work);
2800
89c758fa
BH
2801 return 0;
2802}
2803
2804static int efx_pm_poweroff(struct device *dev)
2805{
2806 struct pci_dev *pci_dev = to_pci_dev(dev);
2807 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2808
2809 efx->type->fini(efx);
2810
a7d529ae 2811 efx->reset_pending = 0;
89c758fa
BH
2812
2813 pci_save_state(pci_dev);
2814 return pci_set_power_state(pci_dev, PCI_D3hot);
2815}
2816
2817/* Used for both resume and restore */
2818static int efx_pm_resume(struct device *dev)
2819{
2820 struct pci_dev *pci_dev = to_pci_dev(dev);
2821 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2822 int rc;
2823
2824 rc = pci_set_power_state(pci_dev, PCI_D0);
2825 if (rc)
2826 return rc;
2827 pci_restore_state(pci_dev);
2828 rc = pci_enable_device(pci_dev);
2829 if (rc)
2830 return rc;
2831 pci_set_master(efx->pci_dev);
2832 rc = efx->type->reset(efx, RESET_TYPE_ALL);
2833 if (rc)
2834 return rc;
2835 rc = efx->type->init(efx);
2836 if (rc)
2837 return rc;
2838 efx_pm_thaw(dev);
2839 return 0;
2840}
2841
2842static int efx_pm_suspend(struct device *dev)
2843{
2844 int rc;
2845
2846 efx_pm_freeze(dev);
2847 rc = efx_pm_poweroff(dev);
2848 if (rc)
2849 efx_pm_resume(dev);
2850 return rc;
2851}
2852
18e83e4c 2853static const struct dev_pm_ops efx_pm_ops = {
89c758fa
BH
2854 .suspend = efx_pm_suspend,
2855 .resume = efx_pm_resume,
2856 .freeze = efx_pm_freeze,
2857 .thaw = efx_pm_thaw,
2858 .poweroff = efx_pm_poweroff,
2859 .restore = efx_pm_resume,
2860};
2861
8ceee660 2862static struct pci_driver efx_pci_driver = {
c5d5f5fd 2863 .name = KBUILD_MODNAME,
8ceee660
BH
2864 .id_table = efx_pci_table,
2865 .probe = efx_pci_probe,
2866 .remove = efx_pci_remove,
89c758fa 2867 .driver.pm = &efx_pm_ops,
8ceee660
BH
2868};
2869
2870/**************************************************************************
2871 *
2872 * Kernel module interface
2873 *
2874 *************************************************************************/
2875
2876module_param(interrupt_mode, uint, 0444);
2877MODULE_PARM_DESC(interrupt_mode,
2878 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
2879
2880static int __init efx_init_module(void)
2881{
2882 int rc;
2883
2884 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
2885
2886 rc = register_netdevice_notifier(&efx_netdev_notifier);
2887 if (rc)
2888 goto err_notifier;
2889
cd2d5b52
BH
2890 rc = efx_init_sriov();
2891 if (rc)
2892 goto err_sriov;
2893
1ab00629
SH
2894 reset_workqueue = create_singlethread_workqueue("sfc_reset");
2895 if (!reset_workqueue) {
2896 rc = -ENOMEM;
2897 goto err_reset;
2898 }
8ceee660
BH
2899
2900 rc = pci_register_driver(&efx_pci_driver);
2901 if (rc < 0)
2902 goto err_pci;
2903
2904 return 0;
2905
2906 err_pci:
1ab00629
SH
2907 destroy_workqueue(reset_workqueue);
2908 err_reset:
cd2d5b52
BH
2909 efx_fini_sriov();
2910 err_sriov:
8ceee660
BH
2911 unregister_netdevice_notifier(&efx_netdev_notifier);
2912 err_notifier:
2913 return rc;
2914}
2915
2916static void __exit efx_exit_module(void)
2917{
2918 printk(KERN_INFO "Solarflare NET driver unloading\n");
2919
2920 pci_unregister_driver(&efx_pci_driver);
1ab00629 2921 destroy_workqueue(reset_workqueue);
cd2d5b52 2922 efx_fini_sriov();
8ceee660
BH
2923 unregister_netdevice_notifier(&efx_netdev_notifier);
2924
2925}
2926
2927module_init(efx_init_module);
2928module_exit(efx_exit_module);
2929
906bb26c
BH
2930MODULE_AUTHOR("Solarflare Communications and "
2931 "Michael Brown <mbrown@fensystems.co.uk>");
8ceee660
BH
2932MODULE_DESCRIPTION("Solarflare Communications network driver");
2933MODULE_LICENSE("GPL");
2934MODULE_DEVICE_TABLE(pci, efx_pci_table);
This page took 0.777303 seconds and 5 git commands to generate.