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sfc: Update product naming
[deliverable/linux.git] / drivers / net / ethernet / sfc / efx.c
CommitLineData
8ceee660 1/****************************************************************************
f7a6d2c4 2 * Driver for Solarflare network controllers and boards
8ceee660 3 * Copyright 2005-2006 Fen Systems Ltd.
f7a6d2c4 4 * Copyright 2005-2013 Solarflare Communications Inc.
8ceee660
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
8ceee660 20#include <linux/ethtool.h>
aa6ef27e 21#include <linux/topology.h>
5a0e3ad6 22#include <linux/gfp.h>
626950db 23#include <linux/aer.h>
b28405b0 24#include <linux/interrupt.h>
8ceee660 25#include "net_driver.h"
8ceee660 26#include "efx.h"
744093c9 27#include "nic.h"
dd40781e 28#include "selftest.h"
8ceee660 29
8880f4ec 30#include "mcdi.h"
fd371e32 31#include "workarounds.h"
8880f4ec 32
c459302d
BH		 33/**************************************************************************
34 *
35 * Type name strings
36 *
37 **************************************************************************
38 */
39
40/* Loopback mode names (see LOOPBACK_MODE()) */
41const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
18e83e4c 42const char *const efx_loopback_mode_names[] = {
c459302d 43 [LOOPBACK_NONE] = "NONE",
e58f69f4 44 [LOOPBACK_DATA] = "DATAPATH",
c459302d
BH		 45 [LOOPBACK_GMAC] = "GMAC",
46 [LOOPBACK_XGMII] = "XGMII",
47 [LOOPBACK_XGXS] = "XGXS",
9c636baf
BH		 48 [LOOPBACK_XAUI] = "XAUI",
49 [LOOPBACK_GMII] = "GMII",
50 [LOOPBACK_SGMII] = "SGMII",
e58f69f4
BH		 51 [LOOPBACK_XGBR] = "XGBR",
52 [LOOPBACK_XFI] = "XFI",
53 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
54 [LOOPBACK_GMII_FAR] = "GMII_FAR",
55 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
56 [LOOPBACK_XFI_FAR] = "XFI_FAR",
c459302d
BH		 57 [LOOPBACK_GPHY] = "GPHY",
58 [LOOPBACK_PHYXS] = "PHYXS",
9c636baf
BH		 59 [LOOPBACK_PCS] = "PCS",
60 [LOOPBACK_PMAPMD] = "PMA/PMD",
e58f69f4
BH		 61 [LOOPBACK_XPORT] = "XPORT",
62 [LOOPBACK_XGMII_WS] = "XGMII_WS",
9c636baf 63 [LOOPBACK_XAUI_WS] = "XAUI_WS",
e58f69f4
BH		 64 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
65 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
9c636baf 66 [LOOPBACK_GMII_WS] = "GMII_WS",
e58f69f4
BH		 67 [LOOPBACK_XFI_WS] = "XFI_WS",
68 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
9c636baf 69 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
c459302d
BH		 70};
71
c459302d 72const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
18e83e4c 73const char *const efx_reset_type_names[] = {
626950db
AR		 74 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
75 [RESET_TYPE_ALL] = "ALL",
76 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
77 [RESET_TYPE_WORLD] = "WORLD",
78 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
79 [RESET_TYPE_DISABLE] = "DISABLE",
80 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
81 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
82 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
3de82b91 83 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR",
626950db
AR		 84 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
85 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
74cd60a4 86 [RESET_TYPE_MC_BIST] = "MC_BIST",
c459302d
BH		 87};
88
1ab00629
SH		 89/* Reset workqueue. If any NIC has a hardware failure then a reset will be
90 * queued onto this work queue. This is not a per-nic work queue, because
91 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
92 */
93static struct workqueue_struct *reset_workqueue;
94
74cd60a4
JC		 95/* How often and how many times to poll for a reset while waiting for a
96 * BIST that another function started to complete.
97 */
98#define BIST_WAIT_DELAY_MS 100
99#define BIST_WAIT_DELAY_COUNT 100
100
8ceee660
BH		 101/**************************************************************************
102 *
103 * Configurable values
104 *
105 *************************************************************************/
106
8ceee660
BH		 107/*
108 * Use separate channels for TX and RX events
109 *
28b581ab
NT		 110 * Set this to 1 to use separate channels for TX and RX. It allows us
111 * to control interrupt affinity separately for TX and RX.
8ceee660 112 *
28b581ab 113 * This is only used in MSI-X interrupt mode
8ceee660 114 */
b9cc977d
BH		 115static bool separate_tx_channels;
116module_param(separate_tx_channels, bool, 0444);
28b581ab
NT		 117MODULE_PARM_DESC(separate_tx_channels,
118 "Use separate channels for TX and RX");
8ceee660
BH		 119
120/* This is the weight assigned to each of the (per-channel) virtual
121 * NAPI devices.
122 */
123static int napi_weight = 64;
124
125/* This is the time (in jiffies) between invocations of the hardware
626950db
AR		 126 * monitor.
127 * On Falcon-based NICs, this will:
e254c274
BH		 128 * - Check the on-board hardware monitor;
129 * - Poll the link state and reconfigure the hardware as necessary.
626950db
AR		 130 * On Siena-based NICs for power systems with EEH support, this will give EEH a
131 * chance to start.
8ceee660 132 */
d215697f 133static unsigned int efx_monitor_interval = 1 * HZ;
8ceee660 134
8ceee660
BH		 135/* Initial interrupt moderation settings. They can be modified after
136 * module load with ethtool.
137 *
138 * The default for RX should strike a balance between increasing the
139 * round-trip latency and reducing overhead.
140 */
141static unsigned int rx_irq_mod_usec = 60;
142
143/* Initial interrupt moderation settings. They can be modified after
144 * module load with ethtool.
145 *
146 * This default is chosen to ensure that a 10G link does not go idle
147 * while a TX queue is stopped after it has become full. A queue is
148 * restarted when it drops below half full. The time this takes (assuming
149 * worst case 3 descriptors per packet and 1024 descriptors) is
150 * 512 / 3 * 1.2 = 205 usec.
151 */
152static unsigned int tx_irq_mod_usec = 150;
153
154/* This is the first interrupt mode to try out of:
155 * 0 => MSI-X
156 * 1 => MSI
157 * 2 => legacy
158 */
159static unsigned int interrupt_mode;
160
161/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
162 * i.e. the number of CPUs among which we may distribute simultaneous
163 * interrupt handling.
164 *
165 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
cdb08f8f 166 * The default (0) means to assign an interrupt to each core.
8ceee660
BH		 167 */
168static unsigned int rss_cpus;
169module_param(rss_cpus, uint, 0444);
170MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
171
b9cc977d
BH		 172static bool phy_flash_cfg;
173module_param(phy_flash_cfg, bool, 0644);
84ae48fe
BH		 174MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
175
e7bed9c8 176static unsigned irq_adapt_low_thresh = 8000;
6fb70fd1
BH		 177module_param(irq_adapt_low_thresh, uint, 0644);
178MODULE_PARM_DESC(irq_adapt_low_thresh,
179 "Threshold score for reducing IRQ moderation");
180
e7bed9c8 181static unsigned irq_adapt_high_thresh = 16000;
6fb70fd1
BH		 182module_param(irq_adapt_high_thresh, uint, 0644);
183MODULE_PARM_DESC(irq_adapt_high_thresh,
184 "Threshold score for increasing IRQ moderation");
185
62776d03
BH		 186static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
187 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
188 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
189 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
190module_param(debug, uint, 0);
191MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
192
8ceee660
BH		 193/**************************************************************************
194 *
195 * Utility functions and prototypes
196 *
197 *************************************************************************/
4642610c 198
261e4d96 199static int efx_soft_enable_interrupts(struct efx_nic *efx);
d8291187 200static void efx_soft_disable_interrupts(struct efx_nic *efx);
7f967c01 201static void efx_remove_channel(struct efx_channel *channel);
4642610c 202static void efx_remove_channels(struct efx_nic *efx);
7f967c01 203static const struct efx_channel_type efx_default_channel_type;
8ceee660 204static void efx_remove_port(struct efx_nic *efx);
7f967c01 205static void efx_init_napi_channel(struct efx_channel *channel);
8ceee660 206static void efx_fini_napi(struct efx_nic *efx);
e8f14992 207static void efx_fini_napi_channel(struct efx_channel *channel);
4642610c
BH		 208static void efx_fini_struct(struct efx_nic *efx);
209static void efx_start_all(struct efx_nic *efx);
210static void efx_stop_all(struct efx_nic *efx);
8ceee660
BH		 211
212#define EFX_ASSERT_RESET_SERIALISED(efx) \
213 do { \
f16aeea0 214 if ((efx->state == STATE_READY) || \
626950db 215 (efx->state == STATE_RECOVERY) || \
332c1ce9 216 (efx->state == STATE_DISABLED)) \
8ceee660
BH		 217 ASSERT_RTNL(); \
218 } while (0)
219
8b7325b4
BH		 220static int efx_check_disabled(struct efx_nic *efx)
221{
626950db 222 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) {
8b7325b4
BH		 223 netif_err(efx, drv, efx->net_dev,
224 "device is disabled due to earlier errors\n");
225 return -EIO;
226 }
227 return 0;
228}
229
8ceee660
BH		 230/**************************************************************************
231 *
232 * Event queue processing
233 *
234 *************************************************************************/
235
236/* Process channel's event queue
237 *
238 * This function is responsible for processing the event queue of a
239 * single channel. The caller must guarantee that this function will
240 * never be concurrently called more than once on the same channel,
241 * though different channels may be being processed concurrently.
242 */
fa236e18 243static int efx_process_channel(struct efx_channel *channel, int budget)
8ceee660 244{
fa236e18 245 int spent;
8ceee660 246
9f2cb71c 247 if (unlikely(!channel->enabled))
42cbe2d7 248 return 0;
8ceee660 249
fa236e18 250 spent = efx_nic_process_eventq(channel, budget);
d9ab7007
BH		 251 if (spent && efx_channel_has_rx_queue(channel)) {
252 struct efx_rx_queue *rx_queue =
253 efx_channel_get_rx_queue(channel);
254
ff734ef4 255 efx_rx_flush_packet(channel);
cce28794 256 efx_fast_push_rx_descriptors(rx_queue, true);
8ceee660
BH		 257 }
258
fa236e18 259 return spent;
8ceee660
BH		 260}
261
8ceee660
BH		 262/* NAPI poll handler
263 *
264 * NAPI guarantees serialisation of polls of the same device, which
265 * provides the guarantee required by efx_process_channel().
266 */
267static int efx_poll(struct napi_struct *napi, int budget)
268{
269 struct efx_channel *channel =
270 container_of(napi, struct efx_channel, napi_str);
62776d03 271 struct efx_nic *efx = channel->efx;
fa236e18 272 int spent;
8ceee660 273
62776d03
BH		 274 netif_vdbg(efx, intr, efx->net_dev,
275 "channel %d NAPI poll executing on CPU %d\n",
276 channel->channel, raw_smp_processor_id());
8ceee660 277
fa236e18 278 spent = efx_process_channel(channel, budget);
8ceee660 279
fa236e18 280 if (spent < budget) {
9d9a6973 281 if (efx_channel_has_rx_queue(channel) &&
6fb70fd1
BH		 282 efx->irq_rx_adaptive &&
283 unlikely(++channel->irq_count == 1000)) {
6fb70fd1
BH		 284 if (unlikely(channel->irq_mod_score <
285 irq_adapt_low_thresh)) {
0d86ebd8
BH		 286 if (channel->irq_moderation > 1) {
287 channel->irq_moderation -= 1;
ef2b90ee 288 efx->type->push_irq_moderation(channel);
0d86ebd8 289 }
6fb70fd1
BH		 290 } else if (unlikely(channel->irq_mod_score >
291 irq_adapt_high_thresh)) {
0d86ebd8
BH		 292 if (channel->irq_moderation <
293 efx->irq_rx_moderation) {
294 channel->irq_moderation += 1;
ef2b90ee 295 efx->type->push_irq_moderation(channel);
0d86ebd8 296 }
6fb70fd1 297 }
6fb70fd1
BH		 298 channel->irq_count = 0;
299 channel->irq_mod_score = 0;
300 }
301
64d8ad6d
BH		 302 efx_filter_rfs_expire(channel);
303
8ceee660 304 /* There is no race here; although napi_disable() will
288379f0 305 * only wait for napi_complete(), this isn't a problem
514bedbc 306 * since efx_nic_eventq_read_ack() will have no effect if
8ceee660
BH		 307 * interrupts have already been disabled.
308 */
288379f0 309 napi_complete(napi);
514bedbc 310 efx_nic_eventq_read_ack(channel);
8ceee660
BH		 311 }
312
fa236e18 313 return spent;
8ceee660
BH		 314}
315
8ceee660
BH		 316/* Create event queue
317 * Event queue memory allocations are done only once. If the channel
318 * is reset, the memory buffer will be reused; this guards against
319 * errors during channel reset and also simplifies interrupt handling.
320 */
321static int efx_probe_eventq(struct efx_channel *channel)
322{
ecc910f5
SH		 323 struct efx_nic *efx = channel->efx;
324 unsigned long entries;
325
86ee5302 326 netif_dbg(efx, probe, efx->net_dev,
62776d03 327 "chan %d create event queue\n", channel->channel);
8ceee660 328
ecc910f5
SH		 329 /* Build an event queue with room for one event per tx and rx buffer,
330 * plus some extra for link state events and MCDI completions. */
331 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
332 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
333 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
334
152b6a62 335 return efx_nic_probe_eventq(channel);
8ceee660
BH		 336}
337
338/* Prepare channel's event queue */
261e4d96 339static int efx_init_eventq(struct efx_channel *channel)
8ceee660 340{
15acb1ce 341 struct efx_nic *efx = channel->efx;
261e4d96
JC		 342 int rc;
343
344 EFX_WARN_ON_PARANOID(channel->eventq_init);
345
15acb1ce 346 netif_dbg(efx, drv, efx->net_dev,
62776d03 347 "chan %d init event queue\n", channel->channel);
8ceee660 348
261e4d96
JC		 349 rc = efx_nic_init_eventq(channel);
350 if (rc == 0) {
15acb1ce 351 efx->type->push_irq_moderation(channel);
261e4d96
JC		 352 channel->eventq_read_ptr = 0;
353 channel->eventq_init = true;
354 }
355 return rc;
8ceee660
BH		 356}
357
9f2cb71c
BH		 358/* Enable event queue processing and NAPI */
359static void efx_start_eventq(struct efx_channel *channel)
360{
361 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
362 "chan %d start event queue\n", channel->channel);
363
514bedbc 364 /* Make sure the NAPI handler sees the enabled flag set */
9f2cb71c
BH		 365 channel->enabled = true;
366 smp_wmb();
367
368 napi_enable(&channel->napi_str);
369 efx_nic_eventq_read_ack(channel);
370}
371
372/* Disable event queue processing and NAPI */
373static void efx_stop_eventq(struct efx_channel *channel)
374{
375 if (!channel->enabled)
376 return;
377
378 napi_disable(&channel->napi_str);
379 channel->enabled = false;
380}
381
8ceee660
BH		 382static void efx_fini_eventq(struct efx_channel *channel)
383{
be3fc09c
BH		 384 if (!channel->eventq_init)
385 return;
386
62776d03
BH		 387 netif_dbg(channel->efx, drv, channel->efx->net_dev,
388 "chan %d fini event queue\n", channel->channel);
8ceee660 389
152b6a62 390 efx_nic_fini_eventq(channel);
be3fc09c 391 channel->eventq_init = false;
8ceee660
BH		 392}
393
394static void efx_remove_eventq(struct efx_channel *channel)
395{
62776d03
BH		 396 netif_dbg(channel->efx, drv, channel->efx->net_dev,
397 "chan %d remove event queue\n", channel->channel);
8ceee660 398
152b6a62 399 efx_nic_remove_eventq(channel);
8ceee660
BH		 400}
401
402/**************************************************************************
403 *
404 * Channel handling
405 *
406 *************************************************************************/
407
7f967c01 408/* Allocate and initialise a channel structure. */
4642610c
BH		 409static struct efx_channel *
410efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
411{
412 struct efx_channel *channel;
413 struct efx_rx_queue *rx_queue;
414 struct efx_tx_queue *tx_queue;
415 int j;
416
7f967c01
BH		 417 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
418 if (!channel)
419 return NULL;
4642610c 420
7f967c01
BH		 421 channel->efx = efx;
422 channel->channel = i;
423 channel->type = &efx_default_channel_type;
4642610c 424
7f967c01
BH		 425 for (j = 0; j < EFX_TXQ_TYPES; j++) {
426 tx_queue = &channel->tx_queue[j];
427 tx_queue->efx = efx;
428 tx_queue->queue = i * EFX_TXQ_TYPES + j;
429 tx_queue->channel = channel;
430 }
4642610c 431
7f967c01
BH		 432 rx_queue = &channel->rx_queue;
433 rx_queue->efx = efx;
434 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
435 (unsigned long)rx_queue);
4642610c 436
7f967c01
BH		 437 return channel;
438}
439
440/* Allocate and initialise a channel structure, copying parameters
441 * (but not resources) from an old channel structure.
442 */
443static struct efx_channel *
444efx_copy_channel(const struct efx_channel *old_channel)
445{
446 struct efx_channel *channel;
447 struct efx_rx_queue *rx_queue;
448 struct efx_tx_queue *tx_queue;
449 int j;
4642610c 450
7f967c01
BH		 451 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
452 if (!channel)
453 return NULL;
454
455 *channel = *old_channel;
456
457 channel->napi_dev = NULL;
458 memset(&channel->eventq, 0, sizeof(channel->eventq));
4642610c 459
7f967c01
BH		 460 for (j = 0; j < EFX_TXQ_TYPES; j++) {
461 tx_queue = &channel->tx_queue[j];
462 if (tx_queue->channel)
4642610c 463 tx_queue->channel = channel;
7f967c01
BH		 464 tx_queue->buffer = NULL;
465 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
4642610c
BH		 466 }
467
4642610c 468 rx_queue = &channel->rx_queue;
7f967c01
BH		 469 rx_queue->buffer = NULL;
470 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
4642610c
BH		 471 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
472 (unsigned long)rx_queue);
473
474 return channel;
475}
476
8ceee660
BH		 477static int efx_probe_channel(struct efx_channel *channel)
478{
479 struct efx_tx_queue *tx_queue;
480 struct efx_rx_queue *rx_queue;
481 int rc;
482
62776d03
BH		 483 netif_dbg(channel->efx, probe, channel->efx->net_dev,
484 "creating channel %d\n", channel->channel);
8ceee660 485
7f967c01
BH		 486 rc = channel->type->pre_probe(channel);
487 if (rc)
488 goto fail;
489
8ceee660
BH		 490 rc = efx_probe_eventq(channel);
491 if (rc)
7f967c01 492 goto fail;
8ceee660
BH		 493
494 efx_for_each_channel_tx_queue(tx_queue, channel) {
495 rc = efx_probe_tx_queue(tx_queue);
496 if (rc)
7f967c01 497 goto fail;
8ceee660
BH		 498 }
499
500 efx_for_each_channel_rx_queue(rx_queue, channel) {
501 rc = efx_probe_rx_queue(rx_queue);
502 if (rc)
7f967c01 503 goto fail;
8ceee660
BH		 504 }
505
8ceee660
BH		 506 return 0;
507
7f967c01
BH		 508fail:
509 efx_remove_channel(channel);
8ceee660
BH		 510 return rc;
511}
512
7f967c01
BH		 513static void
514efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
515{
516 struct efx_nic *efx = channel->efx;
517 const char *type;
518 int number;
519
520 number = channel->channel;
521 if (efx->tx_channel_offset == 0) {
522 type = "";
523 } else if (channel->channel < efx->tx_channel_offset) {
524 type = "-rx";
525 } else {
526 type = "-tx";
527 number -= efx->tx_channel_offset;
528 }
529 snprintf(buf, len, "%s%s-%d", efx->name, type, number);
530}
8ceee660 531
56536e9c
BH		 532static void efx_set_channel_names(struct efx_nic *efx)
533{
534 struct efx_channel *channel;
56536e9c 535
7f967c01
BH		 536 efx_for_each_channel(channel, efx)
537 channel->type->get_name(channel,
d8291187
BH		 538 efx->msi_context[channel->channel].name,
539 sizeof(efx->msi_context[0].name));
56536e9c
BH		 540}
541
4642610c
BH		 542static int efx_probe_channels(struct efx_nic *efx)
543{
544 struct efx_channel *channel;
545 int rc;
546
547 /* Restart special buffer allocation */
548 efx->next_buffer_table = 0;
549
c92aaff1
BH		 550 /* Probe channels in reverse, so that any 'extra' channels
551 * use the start of the buffer table. This allows the traffic
552 * channels to be resized without moving them or wasting the
553 * entries before them.
554 */
555 efx_for_each_channel_rev(channel, efx) {
4642610c
BH		 556 rc = efx_probe_channel(channel);
557 if (rc) {
558 netif_err(efx, probe, efx->net_dev,
559 "failed to create channel %d\n",
560 channel->channel);
561 goto fail;
562 }
563 }
564 efx_set_channel_names(efx);
565
566 return 0;
567
568fail:
569 efx_remove_channels(efx);
570 return rc;
571}
572
8ceee660
BH		 573/* Channels are shutdown and reinitialised whilst the NIC is running
574 * to propagate configuration changes (mtu, checksum offload), or
575 * to clear hardware error conditions
576 */
9f2cb71c 577static void efx_start_datapath(struct efx_nic *efx)
8ceee660 578{
85740cdf 579 bool old_rx_scatter = efx->rx_scatter;
8ceee660
BH		 580 struct efx_tx_queue *tx_queue;
581 struct efx_rx_queue *rx_queue;
582 struct efx_channel *channel;
85740cdf 583 size_t rx_buf_len;
8ceee660 584
f7f13b0b
BH		 585 /* Calculate the rx buffer allocation parameters required to
586 * support the current MTU, including padding for header
587 * alignment and overruns.
588 */
43a3739d 589 efx->rx_dma_len = (efx->rx_prefix_size +
272baeeb
BH		 590 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
591 efx->type->rx_buffer_padding);
85740cdf 592 rx_buf_len = (sizeof(struct efx_rx_page_state) +
2ec03014 593 efx->rx_ip_align + efx->rx_dma_len);
85740cdf 594 if (rx_buf_len <= PAGE_SIZE) {
e8c68c0a 595 efx->rx_scatter = efx->type->always_rx_scatter;
85740cdf 596 efx->rx_buffer_order = 0;
85740cdf 597 } else if (efx->type->can_rx_scatter) {
950c54df 598 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
85740cdf 599 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
950c54df
BH		 600 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
601 EFX_RX_BUF_ALIGNMENT) >
602 PAGE_SIZE);
85740cdf
BH		 603 efx->rx_scatter = true;
604 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
605 efx->rx_buffer_order = 0;
85740cdf
BH		 606 } else {
607 efx->rx_scatter = false;
608 efx->rx_buffer_order = get_order(rx_buf_len);
85740cdf
BH		 609 }
610
1648a23f
DP		 611 efx_rx_config_page_split(efx);
612 if (efx->rx_buffer_order)
613 netif_dbg(efx, drv, efx->net_dev,
614 "RX buf len=%u; page order=%u batch=%u\n",
615 efx->rx_dma_len, efx->rx_buffer_order,
616 efx->rx_pages_per_batch);
617 else
618 netif_dbg(efx, drv, efx->net_dev,
619 "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
620 efx->rx_dma_len, efx->rx_page_buf_step,
621 efx->rx_bufs_per_page, efx->rx_pages_per_batch);
2768935a 622
e8c68c0a 623 /* RX filters may also have scatter-enabled flags */
85740cdf 624 if (efx->rx_scatter != old_rx_scatter)
add72477 625 efx->type->filter_update_rx_scatter(efx);
8ceee660 626
14bf718f
BH		 627 /* We must keep at least one descriptor in a TX ring empty.
628 * We could avoid this when the queue size does not exactly
629 * match the hardware ring size, but it's not that important.
630 * Therefore we stop the queue when one more skb might fill
631 * the ring completely. We wake it when half way back to
632 * empty.
633 */
634 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
635 efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
636
8ceee660
BH		 637 /* Initialise the channels */
638 efx_for_each_channel(channel, efx) {
3881d8ab 639 efx_for_each_channel_tx_queue(tx_queue, channel) {
bc3c90a2 640 efx_init_tx_queue(tx_queue);
3881d8ab
AR		 641 atomic_inc(&efx->active_queues);
642 }
8ceee660 643
9f2cb71c 644 efx_for_each_channel_rx_queue(rx_queue, channel) {
bc3c90a2 645 efx_init_rx_queue(rx_queue);
3881d8ab 646 atomic_inc(&efx->active_queues);
cce28794
JC		 647 efx_stop_eventq(channel);
648 efx_fast_push_rx_descriptors(rx_queue, false);
649 efx_start_eventq(channel);
9f2cb71c 650 }
8ceee660 651
85740cdf 652 WARN_ON(channel->rx_pkt_n_frags);
8ceee660 653 }
8ceee660 654
2ea4dc28
AR		 655 efx_ptp_start_datapath(efx);
656
9f2cb71c
BH		 657 if (netif_device_present(efx->net_dev))
658 netif_tx_wake_all_queues(efx->net_dev);
8ceee660
BH		 659}
660
9f2cb71c 661static void efx_stop_datapath(struct efx_nic *efx)
8ceee660
BH		 662{
663 struct efx_channel *channel;
664 struct efx_tx_queue *tx_queue;
665 struct efx_rx_queue *rx_queue;
6bc5d3a9 666 int rc;
8ceee660
BH		 667
668 EFX_ASSERT_RESET_SERIALISED(efx);
669 BUG_ON(efx->port_enabled);
670
2ea4dc28
AR		 671 efx_ptp_stop_datapath(efx);
672
d8aec745
BH		 673 /* Stop RX refill */
674 efx_for_each_channel(channel, efx) {
675 efx_for_each_channel_rx_queue(rx_queue, channel)
676 rx_queue->refill_enabled = false;
677 }
678
8ceee660 679 efx_for_each_channel(channel, efx) {
9f2cb71c
BH		 680 /* RX packet processing is pipelined, so wait for the
681 * NAPI handler to complete. At least event queue 0
682 * might be kept active by non-data events, so don't
683 * use napi_synchronize() but actually disable NAPI
684 * temporarily.
685 */
686 if (efx_channel_has_rx_queue(channel)) {
687 efx_stop_eventq(channel);
688 efx_start_eventq(channel);
689 }
e42c3d85 690 }
8ceee660 691
e42c3d85
BH		 692 rc = efx->type->fini_dmaq(efx);
693 if (rc && EFX_WORKAROUND_7803(efx)) {
694 /* Schedule a reset to recover from the flush failure. The
695 * descriptor caches reference memory we're about to free,
696 * but falcon_reconfigure_mac_wrapper() won't reconnect
697 * the MACs because of the pending reset.
698 */
699 netif_err(efx, drv, efx->net_dev,
700 "Resetting to recover from flush failure\n");
701 efx_schedule_reset(efx, RESET_TYPE_ALL);
702 } else if (rc) {
703 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
704 } else {
705 netif_dbg(efx, drv, efx->net_dev,
706 "successfully flushed all queues\n");
707 }
708
709 efx_for_each_channel(channel, efx) {
8ceee660
BH		 710 efx_for_each_channel_rx_queue(rx_queue, channel)
711 efx_fini_rx_queue(rx_queue);
94b274bf 712 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660 713 efx_fini_tx_queue(tx_queue);
8ceee660
BH		 714 }
715}
716
717static void efx_remove_channel(struct efx_channel *channel)
718{
719 struct efx_tx_queue *tx_queue;
720 struct efx_rx_queue *rx_queue;
721
62776d03
BH		 722 netif_dbg(channel->efx, drv, channel->efx->net_dev,
723 "destroy chan %d\n", channel->channel);
8ceee660
BH		 724
725 efx_for_each_channel_rx_queue(rx_queue, channel)
726 efx_remove_rx_queue(rx_queue);
94b274bf 727 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660
BH		 728 efx_remove_tx_queue(tx_queue);
729 efx_remove_eventq(channel);
c31e5f9f 730 channel->type->post_remove(channel);
8ceee660
BH		 731}
732
4642610c
BH		 733static void efx_remove_channels(struct efx_nic *efx)
734{
735 struct efx_channel *channel;
736
737 efx_for_each_channel(channel, efx)
738 efx_remove_channel(channel);
739}
740
741int
742efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
743{
744 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
745 u32 old_rxq_entries, old_txq_entries;
7f967c01 746 unsigned i, next_buffer_table = 0;
261e4d96 747 int rc, rc2;
8b7325b4
BH		 748
749 rc = efx_check_disabled(efx);
750 if (rc)
751 return rc;
7f967c01
BH		 752
753 /* Not all channels should be reallocated. We must avoid
754 * reallocating their buffer table entries.
755 */
756 efx_for_each_channel(channel, efx) {
757 struct efx_rx_queue *rx_queue;
758 struct efx_tx_queue *tx_queue;
759
760 if (channel->type->copy)
761 continue;
762 next_buffer_table = max(next_buffer_table,
763 channel->eventq.index +
764 channel->eventq.entries);
765 efx_for_each_channel_rx_queue(rx_queue, channel)
766 next_buffer_table = max(next_buffer_table,
767 rx_queue->rxd.index +
768 rx_queue->rxd.entries);
769 efx_for_each_channel_tx_queue(tx_queue, channel)
770 next_buffer_table = max(next_buffer_table,
771 tx_queue->txd.index +
772 tx_queue->txd.entries);
773 }
4642610c 774
29c69a48 775 efx_device_detach_sync(efx);
4642610c 776 efx_stop_all(efx);
d8291187 777 efx_soft_disable_interrupts(efx);
4642610c 778
7f967c01 779 /* Clone channels (where possible) */
4642610c
BH		 780 memset(other_channel, 0, sizeof(other_channel));
781 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 782 channel = efx->channel[i];
783 if (channel->type->copy)
784 channel = channel->type->copy(channel);
4642610c
BH		 785 if (!channel) {
786 rc = -ENOMEM;
787 goto out;
788 }
789 other_channel[i] = channel;
790 }
791
792 /* Swap entry counts and channel pointers */
793 old_rxq_entries = efx->rxq_entries;
794 old_txq_entries = efx->txq_entries;
795 efx->rxq_entries = rxq_entries;
796 efx->txq_entries = txq_entries;
797 for (i = 0; i < efx->n_channels; i++) {
798 channel = efx->channel[i];
799 efx->channel[i] = other_channel[i];
800 other_channel[i] = channel;
801 }
802
7f967c01
BH		 803 /* Restart buffer table allocation */
804 efx->next_buffer_table = next_buffer_table;
e8f14992 805
e8f14992 806 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 807 channel = efx->channel[i];
808 if (!channel->type->copy)
809 continue;
810 rc = efx_probe_channel(channel);
811 if (rc)
812 goto rollback;
813 efx_init_napi_channel(efx->channel[i]);
e8f14992 814 }
7f967c01 815
4642610c 816out:
7f967c01
BH		 817 /* Destroy unused channel structures */
818 for (i = 0; i < efx->n_channels; i++) {
819 channel = other_channel[i];
820 if (channel && channel->type->copy) {
821 efx_fini_napi_channel(channel);
822 efx_remove_channel(channel);
823 kfree(channel);
824 }
825 }
4642610c 826
261e4d96
JC		 827 rc2 = efx_soft_enable_interrupts(efx);
828 if (rc2) {
829 rc = rc ? rc : rc2;
830 netif_err(efx, drv, efx->net_dev,
831 "unable to restart interrupts on channel reallocation\n");
832 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
833 } else {
834 efx_start_all(efx);
835 netif_device_attach(efx->net_dev);
836 }
4642610c
BH		 837 return rc;
838
839rollback:
840 /* Swap back */
841 efx->rxq_entries = old_rxq_entries;
842 efx->txq_entries = old_txq_entries;
843 for (i = 0; i < efx->n_channels; i++) {
844 channel = efx->channel[i];
845 efx->channel[i] = other_channel[i];
846 other_channel[i] = channel;
847 }
848 goto out;
849}
850
90d683af 851void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
8ceee660 852{
90d683af 853 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
8ceee660
BH		 854}
855
7f967c01
BH		 856static const struct efx_channel_type efx_default_channel_type = {
857 .pre_probe = efx_channel_dummy_op_int,
c31e5f9f 858 .post_remove = efx_channel_dummy_op_void,
7f967c01
BH		 859 .get_name = efx_get_channel_name,
860 .copy = efx_copy_channel,
861 .keep_eventq = false,
862};
863
864int efx_channel_dummy_op_int(struct efx_channel *channel)
865{
866 return 0;
867}
868
c31e5f9f
SH		 869void efx_channel_dummy_op_void(struct efx_channel *channel)
870{
871}
872
8ceee660
BH		 873/**************************************************************************
874 *
875 * Port handling
876 *
877 **************************************************************************/
878
879/* This ensures that the kernel is kept informed (via
880 * netif_carrier_on/off) of the link status, and also maintains the
881 * link status's stop on the port's TX queue.
882 */
fdaa9aed 883void efx_link_status_changed(struct efx_nic *efx)
8ceee660 884{
eb50c0d6
BH		 885 struct efx_link_state *link_state = &efx->link_state;
886
8ceee660
BH		 887 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
888 * that no events are triggered between unregister_netdev() and the
889 * driver unloading. A more general condition is that NETDEV_CHANGE
890 * can only be generated between NETDEV_UP and NETDEV_DOWN */
891 if (!netif_running(efx->net_dev))
892 return;
893
eb50c0d6 894 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
8ceee660
BH		 895 efx->n_link_state_changes++;
896
eb50c0d6 897 if (link_state->up)
8ceee660
BH		 898 netif_carrier_on(efx->net_dev);
899 else
900 netif_carrier_off(efx->net_dev);
901 }
902
903 /* Status message for kernel log */
2aa9ef11 904 if (link_state->up)
62776d03 905 netif_info(efx, link, efx->net_dev,
964e6135 906 "link up at %uMbps %s-duplex (MTU %d)\n",
62776d03 907 link_state->speed, link_state->fd ? "full" : "half",
964e6135 908 efx->net_dev->mtu);
2aa9ef11 909 else
62776d03 910 netif_info(efx, link, efx->net_dev, "link down\n");
8ceee660
BH		 911}
912
d3245b28
BH		 913void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
914{
915 efx->link_advertising = advertising;
916 if (advertising) {
917 if (advertising & ADVERTISED_Pause)
918 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
919 else
920 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
921 if (advertising & ADVERTISED_Asym_Pause)
922 efx->wanted_fc ^= EFX_FC_TX;
923 }
924}
925
b5626946 926void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
d3245b28
BH		 927{
928 efx->wanted_fc = wanted_fc;
929 if (efx->link_advertising) {
930 if (wanted_fc & EFX_FC_RX)
931 efx->link_advertising |= (ADVERTISED_Pause |
932 ADVERTISED_Asym_Pause);
933 else
934 efx->link_advertising &= ~(ADVERTISED_Pause |
935 ADVERTISED_Asym_Pause);
936 if (wanted_fc & EFX_FC_TX)
937 efx->link_advertising ^= ADVERTISED_Asym_Pause;
938 }
939}
940
115122af
BH		 941static void efx_fini_port(struct efx_nic *efx);
942
d3245b28
BH		 943/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
944 * the MAC appropriately. All other PHY configuration changes are pushed
945 * through phy_op->set_settings(), and pushed asynchronously to the MAC
946 * through efx_monitor().
947 *
948 * Callers must hold the mac_lock
949 */
950int __efx_reconfigure_port(struct efx_nic *efx)
8ceee660 951{
d3245b28
BH		 952 enum efx_phy_mode phy_mode;
953 int rc;
8ceee660 954
d3245b28 955 WARN_ON(!mutex_is_locked(&efx->mac_lock));
8ceee660 956
d3245b28
BH		 957 /* Disable PHY transmit in mac level loopbacks */
958 phy_mode = efx->phy_mode;
177dfcd8
BH		 959 if (LOOPBACK_INTERNAL(efx))
960 efx->phy_mode |= PHY_MODE_TX_DISABLED;
961 else
962 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
177dfcd8 963
d3245b28 964 rc = efx->type->reconfigure_port(efx);
8ceee660 965
d3245b28
BH		 966 if (rc)
967 efx->phy_mode = phy_mode;
177dfcd8 968
d3245b28 969 return rc;
8ceee660
BH		 970}
971
972/* Reinitialise the MAC to pick up new PHY settings, even if the port is
973 * disabled. */
d3245b28 974int efx_reconfigure_port(struct efx_nic *efx)
8ceee660 975{
d3245b28
BH		 976 int rc;
977
8ceee660
BH		 978 EFX_ASSERT_RESET_SERIALISED(efx);
979
980 mutex_lock(&efx->mac_lock);
d3245b28 981 rc = __efx_reconfigure_port(efx);
8ceee660 982 mutex_unlock(&efx->mac_lock);
d3245b28
BH		 983
984 return rc;
8ceee660
BH		 985}
986
8be4f3e6
BH		 987/* Asynchronous work item for changing MAC promiscuity and multicast
988 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
989 * MAC directly. */
766ca0fa
BH		 990static void efx_mac_work(struct work_struct *data)
991{
992 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
993
994 mutex_lock(&efx->mac_lock);
30b81cda 995 if (efx->port_enabled)
710b208d 996 efx->type->reconfigure_mac(efx);
766ca0fa
BH		 997 mutex_unlock(&efx->mac_lock);
998}
999
8ceee660
BH		 1000static int efx_probe_port(struct efx_nic *efx)
1001{
1002 int rc;
1003
62776d03 1004 netif_dbg(efx, probe, efx->net_dev, "create port\n");
8ceee660 1005
ff3b00a0
SH		 1006 if (phy_flash_cfg)
1007 efx->phy_mode = PHY_MODE_SPECIAL;
1008
ef2b90ee
BH		 1009 /* Connect up MAC/PHY operations table */
1010 rc = efx->type->probe_port(efx);
8ceee660 1011 if (rc)
e42de262 1012 return rc;
8ceee660 1013
e332bcb3
BH		 1014 /* Initialise MAC address to permanent address */
1015 memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN);
8ceee660
BH		 1016
1017 return 0;
8ceee660
BH		 1018}
1019
1020static int efx_init_port(struct efx_nic *efx)
1021{
1022 int rc;
1023
62776d03 1024 netif_dbg(efx, drv, efx->net_dev, "init port\n");
8ceee660 1025
1dfc5cea
BH		 1026 mutex_lock(&efx->mac_lock);
1027
177dfcd8 1028 rc = efx->phy_op->init(efx);
8ceee660 1029 if (rc)
1dfc5cea 1030 goto fail1;
8ceee660 1031
dc8cfa55 1032 efx->port_initialized = true;
1dfc5cea 1033
d3245b28
BH		 1034 /* Reconfigure the MAC before creating dma queues (required for
1035 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
710b208d 1036 efx->type->reconfigure_mac(efx);
d3245b28
BH		 1037
1038 /* Ensure the PHY advertises the correct flow control settings */
1039 rc = efx->phy_op->reconfigure(efx);
1040 if (rc)
1041 goto fail2;
1042
1dfc5cea 1043 mutex_unlock(&efx->mac_lock);
8ceee660 1044 return 0;
177dfcd8 1045
1dfc5cea 1046fail2:
177dfcd8 1047 efx->phy_op->fini(efx);
1dfc5cea
BH		 1048fail1:
1049 mutex_unlock(&efx->mac_lock);
177dfcd8 1050 return rc;
8ceee660
BH		 1051}
1052
8ceee660
BH		 1053static void efx_start_port(struct efx_nic *efx)
1054{
62776d03 1055 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
8ceee660
BH		 1056 BUG_ON(efx->port_enabled);
1057
1058 mutex_lock(&efx->mac_lock);
dc8cfa55 1059 efx->port_enabled = true;
8be4f3e6 1060
d615c039 1061 /* Ensure MAC ingress/egress is enabled */
710b208d 1062 efx->type->reconfigure_mac(efx);
8be4f3e6 1063
8ceee660
BH		 1064 mutex_unlock(&efx->mac_lock);
1065}
1066
d615c039
BH		 1067/* Cancel work for MAC reconfiguration, periodic hardware monitoring
1068 * and the async self-test, wait for them to finish and prevent them
1069 * being scheduled again. This doesn't cover online resets, which
1070 * should only be cancelled when removing the device.
1071 */
8ceee660
BH		 1072static void efx_stop_port(struct efx_nic *efx)
1073{
62776d03 1074 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
8ceee660 1075
d615c039
BH		 1076 EFX_ASSERT_RESET_SERIALISED(efx);
1077
8ceee660 1078 mutex_lock(&efx->mac_lock);
dc8cfa55 1079 efx->port_enabled = false;
8ceee660
BH		 1080 mutex_unlock(&efx->mac_lock);
1081
1082 /* Serialise against efx_set_multicast_list() */
73ba7b68
BH		 1083 netif_addr_lock_bh(efx->net_dev);
1084 netif_addr_unlock_bh(efx->net_dev);
d615c039
BH		 1085
1086 cancel_delayed_work_sync(&efx->monitor_work);
1087 efx_selftest_async_cancel(efx);
1088 cancel_work_sync(&efx->mac_work);
8ceee660
BH		 1089}
1090
1091static void efx_fini_port(struct efx_nic *efx)
1092{
62776d03 1093 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
8ceee660
BH		 1094
1095 if (!efx->port_initialized)
1096 return;
1097
177dfcd8 1098 efx->phy_op->fini(efx);
dc8cfa55 1099 efx->port_initialized = false;
8ceee660 1100
eb50c0d6 1101 efx->link_state.up = false;
8ceee660
BH		 1102 efx_link_status_changed(efx);
1103}
1104
1105static void efx_remove_port(struct efx_nic *efx)
1106{
62776d03 1107 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
8ceee660 1108
ef2b90ee 1109 efx->type->remove_port(efx);
8ceee660
BH		 1110}
1111
1112/**************************************************************************
1113 *
1114 * NIC handling
1115 *
1116 **************************************************************************/
1117
0bcf4a64
BH		 1118static LIST_HEAD(efx_primary_list);
1119static LIST_HEAD(efx_unassociated_list);
1120
1121static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right)
1122{
1123 return left->type == right->type &&
1124 left->vpd_sn && right->vpd_sn &&
1125 !strcmp(left->vpd_sn, right->vpd_sn);
1126}
1127
1128static void efx_associate(struct efx_nic *efx)
1129{
1130 struct efx_nic *other, *next;
1131
1132 if (efx->primary == efx) {
1133 /* Adding primary function; look for secondaries */
1134
1135 netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n");
1136 list_add_tail(&efx->node, &efx_primary_list);
1137
1138 list_for_each_entry_safe(other, next, &efx_unassociated_list,
1139 node) {
1140 if (efx_same_controller(efx, other)) {
1141 list_del(&other->node);
1142 netif_dbg(other, probe, other->net_dev,
1143 "moving to secondary list of %s %s\n",
1144 pci_name(efx->pci_dev),
1145 efx->net_dev->name);
1146 list_add_tail(&other->node,
1147 &efx->secondary_list);
1148 other->primary = efx;
1149 }
1150 }
1151 } else {
1152 /* Adding secondary function; look for primary */
1153
1154 list_for_each_entry(other, &efx_primary_list, node) {
1155 if (efx_same_controller(efx, other)) {
1156 netif_dbg(efx, probe, efx->net_dev,
1157 "adding to secondary list of %s %s\n",
1158 pci_name(other->pci_dev),
1159 other->net_dev->name);
1160 list_add_tail(&efx->node,
1161 &other->secondary_list);
1162 efx->primary = other;
1163 return;
1164 }
1165 }
1166
1167 netif_dbg(efx, probe, efx->net_dev,
1168 "adding to unassociated list\n");
1169 list_add_tail(&efx->node, &efx_unassociated_list);
1170 }
1171}
1172
1173static void efx_dissociate(struct efx_nic *efx)
1174{
1175 struct efx_nic *other, *next;
1176
1177 list_del(&efx->node);
1178 efx->primary = NULL;
1179
1180 list_for_each_entry_safe(other, next, &efx->secondary_list, node) {
1181 list_del(&other->node);
1182 netif_dbg(other, probe, other->net_dev,
1183 "moving to unassociated list\n");
1184 list_add_tail(&other->node, &efx_unassociated_list);
1185 other->primary = NULL;
1186 }
1187}
1188
8ceee660
BH		 1189/* This configures the PCI device to enable I/O and DMA. */
1190static int efx_init_io(struct efx_nic *efx)
1191{
1192 struct pci_dev *pci_dev = efx->pci_dev;
1193 dma_addr_t dma_mask = efx->type->max_dma_mask;
b105798f 1194 unsigned int mem_map_size = efx->type->mem_map_size(efx);
8ceee660
BH		 1195 int rc;
1196
62776d03 1197 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
8ceee660
BH		 1198
1199 rc = pci_enable_device(pci_dev);
1200 if (rc) {
62776d03
BH		 1201 netif_err(efx, probe, efx->net_dev,
1202 "failed to enable PCI device\n");
8ceee660
BH		 1203 goto fail1;
1204 }
1205
1206 pci_set_master(pci_dev);
1207
1208 /* Set the PCI DMA mask. Try all possibilities from our
1209 * genuine mask down to 32 bits, because some architectures
1210 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1211 * masks event though they reject 46 bit masks.
1212 */
1213 while (dma_mask > 0x7fffffffUL) {
0e33d870 1214 if (dma_supported(&pci_dev->dev, dma_mask)) {
9663deda 1215 rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask);
e9e01846
BH		 1216 if (rc == 0)
1217 break;
1218 }
8ceee660
BH		 1219 dma_mask >>= 1;
1220 }
1221 if (rc) {
62776d03
BH		 1222 netif_err(efx, probe, efx->net_dev,
1223 "could not find a suitable DMA mask\n");
8ceee660
BH		 1224 goto fail2;
1225 }
62776d03
BH		 1226 netif_dbg(efx, probe, efx->net_dev,
1227 "using DMA mask %llx\n", (unsigned long long) dma_mask);
8ceee660 1228
dc803df8
BH		 1229 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
1230 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
8ceee660 1231 if (rc) {
62776d03
BH		 1232 netif_err(efx, probe, efx->net_dev,
1233 "request for memory BAR failed\n");
8ceee660
BH		 1234 rc = -EIO;
1235 goto fail3;
1236 }
b105798f 1237 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size);
8ceee660 1238 if (!efx->membase) {
62776d03
BH		 1239 netif_err(efx, probe, efx->net_dev,
1240 "could not map memory BAR at %llx+%x\n",
b105798f 1241 (unsigned long long)efx->membase_phys, mem_map_size);
8ceee660
BH		 1242 rc = -ENOMEM;
1243 goto fail4;
1244 }
62776d03
BH		 1245 netif_dbg(efx, probe, efx->net_dev,
1246 "memory BAR at %llx+%x (virtual %p)\n",
b105798f
BH		 1247 (unsigned long long)efx->membase_phys, mem_map_size,
1248 efx->membase);
8ceee660
BH		 1249
1250 return 0;
1251
1252 fail4:
dc803df8 1253 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
8ceee660 1254 fail3:
2c118e0f 1255 efx->membase_phys = 0;
8ceee660
BH		 1256 fail2:
1257 pci_disable_device(efx->pci_dev);
1258 fail1:
1259 return rc;
1260}
1261
1262static void efx_fini_io(struct efx_nic *efx)
1263{
62776d03 1264 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
8ceee660
BH		 1265
1266 if (efx->membase) {
1267 iounmap(efx->membase);
1268 efx->membase = NULL;
1269 }
1270
1271 if (efx->membase_phys) {
dc803df8 1272 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
2c118e0f 1273 efx->membase_phys = 0;
8ceee660
BH		 1274 }
1275
1276 pci_disable_device(efx->pci_dev);
1277}
1278
a9a52506 1279static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
46123d04 1280{
cdb08f8f 1281 cpumask_var_t thread_mask;
a16e5b24 1282 unsigned int count;
46123d04 1283 int cpu;
5b874e25 1284
cd2d5b52
BH		 1285 if (rss_cpus) {
1286 count = rss_cpus;
1287 } else {
1288 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
1289 netif_warn(efx, probe, efx->net_dev,
1290 "RSS disabled due to allocation failure\n");
1291 return 1;
1292 }
46123d04 1293
cd2d5b52
BH		 1294 count = 0;
1295 for_each_online_cpu(cpu) {
1296 if (!cpumask_test_cpu(cpu, thread_mask)) {
1297 ++count;
1298 cpumask_or(thread_mask, thread_mask,
1299 topology_thread_cpumask(cpu));
1300 }
1301 }
1302
1303 free_cpumask_var(thread_mask);
2f8975fb
RR		 1304 }
1305
cd2d5b52
BH		 1306 /* If RSS is requested for the PF *and* VFs then we can't write RSS
1307 * table entries that are inaccessible to VFs
1308 */
1309 if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
1310 count > efx_vf_size(efx)) {
1311 netif_warn(efx, probe, efx->net_dev,
1312 "Reducing number of RSS channels from %u to %u for "
1313 "VF support. Increase vf-msix-limit to use more "
1314 "channels on the PF.\n",
1315 count, efx_vf_size(efx));
1316 count = efx_vf_size(efx);
46123d04
BH		 1317 }
1318
1319 return count;
1320}
1321
1322/* Probe the number and type of interrupts we are able to obtain, and
1323 * the resulting numbers of channels and RX queues.
1324 */
64d8ad6d 1325static int efx_probe_interrupts(struct efx_nic *efx)
8ceee660 1326{
7f967c01
BH		 1327 unsigned int extra_channels = 0;
1328 unsigned int i, j;
a16e5b24 1329 int rc;
8ceee660 1330
7f967c01
BH		 1331 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
1332 if (efx->extra_channel_type[i])
1333 ++extra_channels;
1334
8ceee660 1335 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
46123d04 1336 struct msix_entry xentries[EFX_MAX_CHANNELS];
a16e5b24 1337 unsigned int n_channels;
aa6ef27e 1338
a9a52506 1339 n_channels = efx_wanted_parallelism(efx);
a4900ac9
BH		 1340 if (separate_tx_channels)
1341 n_channels *= 2;
7f967c01 1342 n_channels += extra_channels;
b105798f 1343 n_channels = min(n_channels, efx->max_channels);
8ceee660 1344
a4900ac9 1345 for (i = 0; i < n_channels; i++)
8ceee660 1346 xentries[i].entry = i;
a4900ac9 1347 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels);
8ceee660 1348 if (rc > 0) {
62776d03
BH		 1349 netif_err(efx, drv, efx->net_dev,
1350 "WARNING: Insufficient MSI-X vectors"
a16e5b24 1351 " available (%d < %u).\n", rc, n_channels);
62776d03
BH		 1352 netif_err(efx, drv, efx->net_dev,
1353 "WARNING: Performance may be reduced.\n");
a4900ac9
BH		 1354 EFX_BUG_ON_PARANOID(rc >= n_channels);
1355 n_channels = rc;
8ceee660 1356 rc = pci_enable_msix(efx->pci_dev, xentries,
a4900ac9 1357 n_channels);
8ceee660
BH		 1358 }
1359
1360 if (rc == 0) {
a4900ac9 1361 efx->n_channels = n_channels;
7f967c01
BH		 1362 if (n_channels > extra_channels)
1363 n_channels -= extra_channels;
a4900ac9 1364 if (separate_tx_channels) {
7f967c01
BH		 1365 efx->n_tx_channels = max(n_channels / 2, 1U);
1366 efx->n_rx_channels = max(n_channels -
1367 efx->n_tx_channels,
1368 1U);
a4900ac9 1369 } else {
7f967c01
BH		 1370 efx->n_tx_channels = n_channels;
1371 efx->n_rx_channels = n_channels;
a4900ac9 1372 }
7f967c01 1373 for (i = 0; i < efx->n_channels; i++)
f7d12cdc
BH		 1374 efx_get_channel(efx, i)->irq =
1375 xentries[i].vector;
8ceee660
BH		 1376 } else {
1377 /* Fall back to single channel MSI */
1378 efx->interrupt_mode = EFX_INT_MODE_MSI;
62776d03
BH		 1379 netif_err(efx, drv, efx->net_dev,
1380 "could not enable MSI-X\n");
8ceee660
BH		 1381 }
1382 }
1383
1384 /* Try single interrupt MSI */
1385 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
28b581ab 1386 efx->n_channels = 1;
a4900ac9
BH		 1387 efx->n_rx_channels = 1;
1388 efx->n_tx_channels = 1;
8ceee660
BH		 1389 rc = pci_enable_msi(efx->pci_dev);
1390 if (rc == 0) {
f7d12cdc 1391 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
8ceee660 1392 } else {
62776d03
BH		 1393 netif_err(efx, drv, efx->net_dev,
1394 "could not enable MSI\n");
8ceee660
BH		 1395 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1396 }
1397 }
1398
1399 /* Assume legacy interrupts */
1400 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
28b581ab 1401 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
a4900ac9
BH		 1402 efx->n_rx_channels = 1;
1403 efx->n_tx_channels = 1;
8ceee660
BH		 1404 efx->legacy_irq = efx->pci_dev->irq;
1405 }
64d8ad6d 1406
7f967c01
BH		 1407 /* Assign extra channels if possible */
1408 j = efx->n_channels;
1409 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
1410 if (!efx->extra_channel_type[i])
1411 continue;
1412 if (efx->interrupt_mode != EFX_INT_MODE_MSIX ||
1413 efx->n_channels <= extra_channels) {
1414 efx->extra_channel_type[i]->handle_no_channel(efx);
1415 } else {
1416 --j;
1417 efx_get_channel(efx, j)->type =
1418 efx->extra_channel_type[i];
1419 }
1420 }
1421
cd2d5b52 1422 /* RSS might be usable on VFs even if it is disabled on the PF */
3132d282 1423 efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ?
cd2d5b52
BH		 1424 efx->n_rx_channels : efx_vf_size(efx));
1425
64d8ad6d 1426 return 0;
8ceee660
BH		 1427}
1428
261e4d96 1429static int efx_soft_enable_interrupts(struct efx_nic *efx)
9f2cb71c 1430{
261e4d96
JC		 1431 struct efx_channel *channel, *end_channel;
1432 int rc;
9f2cb71c 1433
8b7325b4
BH		 1434 BUG_ON(efx->state == STATE_DISABLED);
1435
d8291187
BH		 1436 efx->irq_soft_enabled = true;
1437 smp_wmb();
9f2cb71c
BH		 1438
1439 efx_for_each_channel(channel, efx) {
261e4d96
JC		 1440 if (!channel->type->keep_eventq) {
1441 rc = efx_init_eventq(channel);
1442 if (rc)
1443 goto fail;
1444 }
9f2cb71c
BH		 1445 efx_start_eventq(channel);
1446 }
1447
1448 efx_mcdi_mode_event(efx);
261e4d96
JC		 1449
1450 return 0;
1451fail:
1452 end_channel = channel;
1453 efx_for_each_channel(channel, efx) {
1454 if (channel == end_channel)
1455 break;
1456 efx_stop_eventq(channel);
1457 if (!channel->type->keep_eventq)
1458 efx_fini_eventq(channel);
1459 }
1460
1461 return rc;
9f2cb71c
BH		 1462}
1463
d8291187 1464static void efx_soft_disable_interrupts(struct efx_nic *efx)
9f2cb71c
BH		 1465{
1466 struct efx_channel *channel;
1467
8b7325b4
BH		 1468 if (efx->state == STATE_DISABLED)
1469 return;
1470
9f2cb71c
BH		 1471 efx_mcdi_mode_poll(efx);
1472
d8291187
BH		 1473 efx->irq_soft_enabled = false;
1474 smp_wmb();
1475
1476 if (efx->legacy_irq)
9f2cb71c 1477 synchronize_irq(efx->legacy_irq);
9f2cb71c
BH		 1478
1479 efx_for_each_channel(channel, efx) {
1480 if (channel->irq)
1481 synchronize_irq(channel->irq);
1482
1483 efx_stop_eventq(channel);
d8291187 1484 if (!channel->type->keep_eventq)
7f967c01 1485 efx_fini_eventq(channel);
9f2cb71c 1486 }
cade715f
BH		 1487
1488 /* Flush the asynchronous MCDI request queue */
1489 efx_mcdi_flush_async(efx);
9f2cb71c
BH		 1490}
1491
261e4d96 1492static int efx_enable_interrupts(struct efx_nic *efx)
d8291187 1493{
261e4d96
JC		 1494 struct efx_channel *channel, *end_channel;
1495 int rc;
d8291187
BH		 1496
1497 BUG_ON(efx->state == STATE_DISABLED);
1498
1499 if (efx->eeh_disabled_legacy_irq) {
1500 enable_irq(efx->legacy_irq);
1501 efx->eeh_disabled_legacy_irq = false;
1502 }
1503
86094f7f 1504 efx->type->irq_enable_master(efx);
d8291187
BH		 1505
1506 efx_for_each_channel(channel, efx) {
261e4d96
JC		 1507 if (channel->type->keep_eventq) {
1508 rc = efx_init_eventq(channel);
1509 if (rc)
1510 goto fail;
1511 }
1512 }
1513
1514 rc = efx_soft_enable_interrupts(efx);
1515 if (rc)
1516 goto fail;
1517
1518 return 0;
1519
1520fail:
1521 end_channel = channel;
1522 efx_for_each_channel(channel, efx) {
1523 if (channel == end_channel)
1524 break;
d8291187 1525 if (channel->type->keep_eventq)
261e4d96 1526 efx_fini_eventq(channel);
d8291187
BH		 1527 }
1528
261e4d96
JC		 1529 efx->type->irq_disable_non_ev(efx);
1530
1531 return rc;
d8291187
BH		 1532}
1533
1534static void efx_disable_interrupts(struct efx_nic *efx)
1535{
1536 struct efx_channel *channel;
1537
1538 efx_soft_disable_interrupts(efx);
1539
1540 efx_for_each_channel(channel, efx) {
1541 if (channel->type->keep_eventq)
1542 efx_fini_eventq(channel);
1543 }
1544
86094f7f 1545 efx->type->irq_disable_non_ev(efx);
d8291187
BH		 1546}
1547
8ceee660
BH		 1548static void efx_remove_interrupts(struct efx_nic *efx)
1549{
1550 struct efx_channel *channel;
1551
1552 /* Remove MSI/MSI-X interrupts */
64ee3120 1553 efx_for_each_channel(channel, efx)
8ceee660
BH		 1554 channel->irq = 0;
1555 pci_disable_msi(efx->pci_dev);
1556 pci_disable_msix(efx->pci_dev);
1557
1558 /* Remove legacy interrupt */
1559 efx->legacy_irq = 0;
1560}
1561
8831da7b 1562static void efx_set_channels(struct efx_nic *efx)
8ceee660 1563{
602a5322
BH		 1564 struct efx_channel *channel;
1565 struct efx_tx_queue *tx_queue;
1566
97653431 1567 efx->tx_channel_offset =
a4900ac9 1568 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0;
602a5322 1569
79d68b37
SH		 1570 /* We need to mark which channels really have RX and TX
1571 * queues, and adjust the TX queue numbers if we have separate
602a5322
BH		 1572 * RX-only and TX-only channels.
1573 */
1574 efx_for_each_channel(channel, efx) {
79d68b37
SH		 1575 if (channel->channel < efx->n_rx_channels)
1576 channel->rx_queue.core_index = channel->channel;
1577 else
1578 channel->rx_queue.core_index = -1;
1579
602a5322
BH		 1580 efx_for_each_channel_tx_queue(tx_queue, channel)
1581 tx_queue->queue -= (efx->tx_channel_offset *
1582 EFX_TXQ_TYPES);
1583 }
8ceee660
BH		 1584}
1585
1586static int efx_probe_nic(struct efx_nic *efx)
1587{
765c9f46 1588 size_t i;
8ceee660
BH		 1589 int rc;
1590
62776d03 1591 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
8ceee660
BH		 1592
1593 /* Carry out hardware-type specific initialisation */
ef2b90ee 1594 rc = efx->type->probe(efx);
8ceee660
BH		 1595 if (rc)
1596 return rc;
1597
a4900ac9 1598 /* Determine the number of channels and queues by trying to hook
8ceee660 1599 * in MSI-X interrupts. */
64d8ad6d
BH		 1600 rc = efx_probe_interrupts(efx);
1601 if (rc)
c15eed22 1602 goto fail1;
8ceee660 1603
c15eed22
BH		 1604 rc = efx->type->dimension_resources(efx);
1605 if (rc)
1606 goto fail2;
28e47c49 1607
5d3a6fca
BH		 1608 if (efx->n_channels > 1)
1609 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
765c9f46 1610 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
278bc429 1611 efx->rx_indir_table[i] =
cd2d5b52 1612 ethtool_rxfh_indir_default(i, efx->rss_spread);
5d3a6fca 1613
8831da7b 1614 efx_set_channels(efx);
c4f4adc7
BH		 1615 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1616 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
8ceee660
BH		 1617
1618 /* Initialise the interrupt moderation settings */
9e393b30
BH		 1619 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
1620 true);
8ceee660
BH		 1621
1622 return 0;
64d8ad6d 1623
c15eed22
BH		 1624fail2:
1625 efx_remove_interrupts(efx);
1626fail1:
64d8ad6d
BH		 1627 efx->type->remove(efx);
1628 return rc;
8ceee660
BH		 1629}
1630
1631static void efx_remove_nic(struct efx_nic *efx)
1632{
62776d03 1633 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
8ceee660
BH		 1634
1635 efx_remove_interrupts(efx);
ef2b90ee 1636 efx->type->remove(efx);
8ceee660
BH		 1637}
1638
add72477
BH		 1639static int efx_probe_filters(struct efx_nic *efx)
1640{
1641 int rc;
1642
1643 spin_lock_init(&efx->filter_lock);
1644
1645 rc = efx->type->filter_table_probe(efx);
1646 if (rc)
1647 return rc;
1648
1649#ifdef CONFIG_RFS_ACCEL
1650 if (efx->type->offload_features & NETIF_F_NTUPLE) {
1651 efx->rps_flow_id = kcalloc(efx->type->max_rx_ip_filters,
1652 sizeof(*efx->rps_flow_id),
1653 GFP_KERNEL);
1654 if (!efx->rps_flow_id) {
1655 efx->type->filter_table_remove(efx);
1656 return -ENOMEM;
1657 }
1658 }
1659#endif
1660
1661 return 0;
1662}
1663
1664static void efx_remove_filters(struct efx_nic *efx)
1665{
1666#ifdef CONFIG_RFS_ACCEL
1667 kfree(efx->rps_flow_id);
1668#endif
1669 efx->type->filter_table_remove(efx);
1670}
1671
1672static void efx_restore_filters(struct efx_nic *efx)
1673{
1674 efx->type->filter_table_restore(efx);
1675}
1676
8ceee660
BH		 1677/**************************************************************************
1678 *
1679 * NIC startup/shutdown
1680 *
1681 *************************************************************************/
1682
1683static int efx_probe_all(struct efx_nic *efx)
1684{
8ceee660
BH		 1685 int rc;
1686
8ceee660
BH		 1687 rc = efx_probe_nic(efx);
1688 if (rc) {
62776d03 1689 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
8ceee660
BH		 1690 goto fail1;
1691 }
1692
8ceee660
BH		 1693 rc = efx_probe_port(efx);
1694 if (rc) {
62776d03 1695 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
8ceee660
BH		 1696 goto fail2;
1697 }
1698
7e6d06f0
BH		 1699 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
1700 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
1701 rc = -EINVAL;
1702 goto fail3;
1703 }
ecc910f5 1704 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
8ceee660 1705
64eebcfd
BH		 1706 rc = efx_probe_filters(efx);
1707 if (rc) {
1708 netif_err(efx, probe, efx->net_dev,
1709 "failed to create filter tables\n");
7f967c01 1710 goto fail3;
64eebcfd
BH		 1711 }
1712
7f967c01
BH		 1713 rc = efx_probe_channels(efx);
1714 if (rc)
1715 goto fail4;
1716
8ceee660
BH		 1717 return 0;
1718
64eebcfd 1719 fail4:
7f967c01 1720 efx_remove_filters(efx);
8ceee660 1721 fail3:
8ceee660
BH		 1722 efx_remove_port(efx);
1723 fail2:
1724 efx_remove_nic(efx);
1725 fail1:
1726 return rc;
1727}
1728
8b7325b4
BH		 1729/* If the interface is supposed to be running but is not, start
1730 * the hardware and software data path, regular activity for the port
1731 * (MAC statistics, link polling, etc.) and schedule the port to be
1732 * reconfigured. Interrupts must already be enabled. This function
1733 * is safe to call multiple times, so long as the NIC is not disabled.
1734 * Requires the RTNL lock.
9f2cb71c 1735 */
8ceee660
BH		 1736static void efx_start_all(struct efx_nic *efx)
1737{
8ceee660 1738 EFX_ASSERT_RESET_SERIALISED(efx);
8b7325b4 1739 BUG_ON(efx->state == STATE_DISABLED);
8ceee660
BH		 1740
1741 /* Check that it is appropriate to restart the interface. All
1742 * of these flags are safe to read under just the rtnl lock */
8b7325b4 1743 if (efx->port_enabled || !netif_running(efx->net_dev))
8ceee660
BH		 1744 return;
1745
8ceee660 1746 efx_start_port(efx);
9f2cb71c 1747 efx_start_datapath(efx);
8880f4ec 1748
626950db
AR		 1749 /* Start the hardware monitor if there is one */
1750 if (efx->type->monitor != NULL)
8ceee660
BH		 1751 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1752 efx_monitor_interval);
626950db
AR		 1753
1754 /* If link state detection is normally event-driven, we have
1755 * to poll now because we could have missed a change
1756 */
1757 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
78c1f0a0
SH		 1758 mutex_lock(&efx->mac_lock);
1759 if (efx->phy_op->poll(efx))
1760 efx_link_status_changed(efx);
1761 mutex_unlock(&efx->mac_lock);
1762 }
55edc6e6 1763
ef2b90ee 1764 efx->type->start_stats(efx);
f8f3b5ae
JC		 1765 efx->type->pull_stats(efx);
1766 spin_lock_bh(&efx->stats_lock);
1767 efx->type->update_stats(efx, NULL, NULL);
1768 spin_unlock_bh(&efx->stats_lock);
8ceee660
BH		 1769}
1770
8b7325b4
BH		 1771/* Quiesce the hardware and software data path, and regular activity
1772 * for the port without bringing the link down. Safe to call multiple
1773 * times with the NIC in almost any state, but interrupts should be
1774 * enabled. Requires the RTNL lock.
1775 */
8ceee660
BH		 1776static void efx_stop_all(struct efx_nic *efx)
1777{
8ceee660
BH		 1778 EFX_ASSERT_RESET_SERIALISED(efx);
1779
1780 /* port_enabled can be read safely under the rtnl lock */
1781 if (!efx->port_enabled)
1782 return;
1783
f8f3b5ae
JC		 1784 /* update stats before we go down so we can accurately count
1785 * rx_nodesc_drops
1786 */
1787 efx->type->pull_stats(efx);
1788 spin_lock_bh(&efx->stats_lock);
1789 efx->type->update_stats(efx, NULL, NULL);
1790 spin_unlock_bh(&efx->stats_lock);
ef2b90ee 1791 efx->type->stop_stats(efx);
8ceee660
BH		 1792 efx_stop_port(efx);
1793
29c69a48
BH		 1794 /* Stop the kernel transmit interface. This is only valid if
1795 * the device is stopped or detached; otherwise the watchdog
1796 * may fire immediately.
1797 */
1798 WARN_ON(netif_running(efx->net_dev) &&
1799 netif_device_present(efx->net_dev));
9f2cb71c
BH		 1800 netif_tx_disable(efx->net_dev);
1801
1802 efx_stop_datapath(efx);
8ceee660
BH		 1803}
1804
1805static void efx_remove_all(struct efx_nic *efx)
1806{
4642610c 1807 efx_remove_channels(efx);
7f967c01 1808 efx_remove_filters(efx);
8ceee660
BH		 1809 efx_remove_port(efx);
1810 efx_remove_nic(efx);
1811}
1812
8ceee660
BH		 1813/**************************************************************************
1814 *
1815 * Interrupt moderation
1816 *
1817 **************************************************************************/
1818
cc180b69 1819static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns)
0d86ebd8 1820{
b548f976
BH		 1821 if (usecs == 0)
1822 return 0;
cc180b69 1823 if (usecs * 1000 < quantum_ns)
0d86ebd8 1824 return 1; /* never round down to 0 */
cc180b69 1825 return usecs * 1000 / quantum_ns;
0d86ebd8
BH		 1826}
1827
8ceee660 1828/* Set interrupt moderation parameters */
9e393b30
BH		 1829int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
1830 unsigned int rx_usecs, bool rx_adaptive,
1831 bool rx_may_override_tx)
8ceee660 1832{
f7d12cdc 1833 struct efx_channel *channel;
cc180b69
BH		 1834 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max *
1835 efx->timer_quantum_ns,
1836 1000);
1837 unsigned int tx_ticks;
1838 unsigned int rx_ticks;
8ceee660
BH		 1839
1840 EFX_ASSERT_RESET_SERIALISED(efx);
1841
cc180b69 1842 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max)
9e393b30
BH		 1843 return -EINVAL;
1844
cc180b69
BH		 1845 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns);
1846 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns);
1847
9e393b30
BH		 1848 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 &&
1849 !rx_may_override_tx) {
1850 netif_err(efx, drv, efx->net_dev, "Channels are shared. "
1851 "RX and TX IRQ moderation must be equal\n");
1852 return -EINVAL;
1853 }
1854
6fb70fd1 1855 efx->irq_rx_adaptive = rx_adaptive;
0d86ebd8 1856 efx->irq_rx_moderation = rx_ticks;
f7d12cdc 1857 efx_for_each_channel(channel, efx) {
525da907 1858 if (efx_channel_has_rx_queue(channel))
f7d12cdc 1859 channel->irq_moderation = rx_ticks;
525da907 1860 else if (efx_channel_has_tx_queues(channel))
f7d12cdc
BH		 1861 channel->irq_moderation = tx_ticks;
1862 }
9e393b30
BH		 1863
1864 return 0;
8ceee660
BH		 1865}
1866
a0c4faf5
BH		 1867void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
1868 unsigned int *rx_usecs, bool *rx_adaptive)
1869{
cc180b69
BH		 1870 /* We must round up when converting ticks to microseconds
1871 * because we round down when converting the other way.
1872 */
1873
a0c4faf5 1874 *rx_adaptive = efx->irq_rx_adaptive;
cc180b69
BH		 1875 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation *
1876 efx->timer_quantum_ns,
1877 1000);
a0c4faf5
BH		 1878
1879 /* If channels are shared between RX and TX, so is IRQ
1880 * moderation. Otherwise, IRQ moderation is the same for all
1881 * TX channels and is not adaptive.
1882 */
1883 if (efx->tx_channel_offset == 0)
1884 *tx_usecs = *rx_usecs;
1885 else
cc180b69 1886 *tx_usecs = DIV_ROUND_UP(
a0c4faf5 1887 efx->channel[efx->tx_channel_offset]->irq_moderation *
cc180b69
BH		 1888 efx->timer_quantum_ns,
1889 1000);
a0c4faf5
BH		 1890}
1891
8ceee660
BH		 1892/**************************************************************************
1893 *
1894 * Hardware monitor
1895 *
1896 **************************************************************************/
1897
e254c274 1898/* Run periodically off the general workqueue */
8ceee660
BH		 1899static void efx_monitor(struct work_struct *data)
1900{
1901 struct efx_nic *efx = container_of(data, struct efx_nic,
1902 monitor_work.work);
8ceee660 1903
62776d03
BH		 1904 netif_vdbg(efx, timer, efx->net_dev,
1905 "hardware monitor executing on CPU %d\n",
1906 raw_smp_processor_id());
ef2b90ee 1907 BUG_ON(efx->type->monitor == NULL);
8ceee660 1908
8ceee660
BH		 1909 /* If the mac_lock is already held then it is likely a port
1910 * reconfiguration is already in place, which will likely do
e254c274
BH		 1911 * most of the work of monitor() anyway. */
1912 if (mutex_trylock(&efx->mac_lock)) {
1913 if (efx->port_enabled)
1914 efx->type->monitor(efx);
1915 mutex_unlock(&efx->mac_lock);
1916 }
8ceee660 1917
8ceee660
BH		 1918 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1919 efx_monitor_interval);
1920}
1921
1922/**************************************************************************
1923 *
1924 * ioctls
1925 *
1926 *************************************************************************/
1927
1928/* Net device ioctl
1929 * Context: process, rtnl_lock() held.
1930 */
1931static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1932{
767e468c 1933 struct efx_nic *efx = netdev_priv(net_dev);
68e7f45e 1934 struct mii_ioctl_data *data = if_mii(ifr);
8ceee660 1935
7c236c43 1936 if (cmd == SIOCSHWTSTAMP)
433dc9b3
BH		 1937 return efx_ptp_set_ts_config(efx, ifr);
1938 if (cmd == SIOCGHWTSTAMP)
1939 return efx_ptp_get_ts_config(efx, ifr);
7c236c43 1940
68e7f45e
BH		 1941 /* Convert phy_id from older PRTAD/DEVAD format */
1942 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1943 (data->phy_id & 0xfc00) == 0x0400)
1944 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1945
1946 return mdio_mii_ioctl(&efx->mdio, data, cmd);
8ceee660
BH		 1947}
1948
1949/**************************************************************************
1950 *
1951 * NAPI interface
1952 *
1953 **************************************************************************/
1954
7f967c01
BH		 1955static void efx_init_napi_channel(struct efx_channel *channel)
1956{
1957 struct efx_nic *efx = channel->efx;
1958
1959 channel->napi_dev = efx->net_dev;
1960 netif_napi_add(channel->napi_dev, &channel->napi_str,
1961 efx_poll, napi_weight);
1962}
1963
e8f14992 1964static void efx_init_napi(struct efx_nic *efx)
8ceee660
BH		 1965{
1966 struct efx_channel *channel;
8ceee660 1967
7f967c01
BH		 1968 efx_for_each_channel(channel, efx)
1969 efx_init_napi_channel(channel);
e8f14992
BH		 1970}
1971
1972static void efx_fini_napi_channel(struct efx_channel *channel)
1973{
1974 if (channel->napi_dev)
1975 netif_napi_del(&channel->napi_str);
1976 channel->napi_dev = NULL;
8ceee660
BH		 1977}
1978
1979static void efx_fini_napi(struct efx_nic *efx)
1980{
1981 struct efx_channel *channel;
1982
e8f14992
BH		 1983 efx_for_each_channel(channel, efx)
1984 efx_fini_napi_channel(channel);
8ceee660
BH		 1985}
1986
1987/**************************************************************************
1988 *
1989 * Kernel netpoll interface
1990 *
1991 *************************************************************************/
1992
1993#ifdef CONFIG_NET_POLL_CONTROLLER
1994
1995/* Although in the common case interrupts will be disabled, this is not
1996 * guaranteed. However, all our work happens inside the NAPI callback,
1997 * so no locking is required.
1998 */
1999static void efx_netpoll(struct net_device *net_dev)
2000{
767e468c 2001 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 2002 struct efx_channel *channel;
2003
64ee3120 2004 efx_for_each_channel(channel, efx)
8ceee660
BH		 2005 efx_schedule_channel(channel);
2006}
2007
2008#endif
2009
2010/**************************************************************************
2011 *
2012 * Kernel net device interface
2013 *
2014 *************************************************************************/
2015
2016/* Context: process, rtnl_lock() held. */
2017static int efx_net_open(struct net_device *net_dev)
2018{
767e468c 2019 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4
BH		 2020 int rc;
2021
62776d03
BH		 2022 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
2023 raw_smp_processor_id());
8ceee660 2024
8b7325b4
BH		 2025 rc = efx_check_disabled(efx);
2026 if (rc)
2027 return rc;
f8b87c17
BH		 2028 if (efx->phy_mode & PHY_MODE_SPECIAL)
2029 return -EBUSY;
8880f4ec
BH		 2030 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
2031 return -EIO;
f8b87c17 2032
78c1f0a0
SH		 2033 /* Notify the kernel of the link state polled during driver load,
2034 * before the monitor starts running */
2035 efx_link_status_changed(efx);
2036
8ceee660 2037 efx_start_all(efx);
dd40781e 2038 efx_selftest_async_start(efx);
8ceee660
BH		 2039 return 0;
2040}
2041
2042/* Context: process, rtnl_lock() held.
2043 * Note that the kernel will ignore our return code; this method
2044 * should really be a void.
2045 */
2046static int efx_net_stop(struct net_device *net_dev)
2047{
767e468c 2048 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2049
62776d03
BH		 2050 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
2051 raw_smp_processor_id());
8ceee660 2052
8b7325b4
BH		 2053 /* Stop the device and flush all the channels */
2054 efx_stop_all(efx);
8ceee660
BH		 2055
2056 return 0;
2057}
2058
5b9e207c 2059/* Context: process, dev_base_lock or RTNL held, non-blocking. */
2aa9ef11
BH		 2060static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev,
2061 struct rtnl_link_stats64 *stats)
8ceee660 2062{
767e468c 2063 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2064
55edc6e6 2065 spin_lock_bh(&efx->stats_lock);
cd0ecc9a 2066 efx->type->update_stats(efx, NULL, stats);
1cb34522
BH		 2067 spin_unlock_bh(&efx->stats_lock);
2068
8ceee660
BH		 2069 return stats;
2070}
2071
2072/* Context: netif_tx_lock held, BHs disabled. */
2073static void efx_watchdog(struct net_device *net_dev)
2074{
767e468c 2075 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2076
62776d03
BH		 2077 netif_err(efx, tx_err, efx->net_dev,
2078 "TX stuck with port_enabled=%d: resetting channels\n",
2079 efx->port_enabled);
8ceee660 2080
739bb23d 2081 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
8ceee660
BH		 2082}
2083
2084
2085/* Context: process, rtnl_lock() held. */
2086static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
2087{
767e468c 2088 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4 2089 int rc;
8ceee660 2090
8b7325b4
BH		 2091 rc = efx_check_disabled(efx);
2092 if (rc)
2093 return rc;
8ceee660
BH		 2094 if (new_mtu > EFX_MAX_MTU)
2095 return -EINVAL;
2096
62776d03 2097 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
8ceee660 2098
29c69a48
BH		 2099 efx_device_detach_sync(efx);
2100 efx_stop_all(efx);
2101
d3245b28 2102 mutex_lock(&efx->mac_lock);
8ceee660 2103 net_dev->mtu = new_mtu;
710b208d 2104 efx->type->reconfigure_mac(efx);
d3245b28
BH		 2105 mutex_unlock(&efx->mac_lock);
2106
8ceee660 2107 efx_start_all(efx);
29c69a48 2108 netif_device_attach(efx->net_dev);
6c8eef4a 2109 return 0;
8ceee660
BH		 2110}
2111
2112static int efx_set_mac_address(struct net_device *net_dev, void *data)
2113{
767e468c 2114 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2115 struct sockaddr *addr = data;
e0b3ae30 2116 u8 *new_addr = addr->sa_data;
8ceee660 2117
8ceee660 2118 if (!is_valid_ether_addr(new_addr)) {
62776d03
BH		 2119 netif_err(efx, drv, efx->net_dev,
2120 "invalid ethernet MAC address requested: %pM\n",
2121 new_addr);
504f9b5a 2122 return -EADDRNOTAVAIL;
8ceee660
BH		 2123 }
2124
2125 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
cd2d5b52 2126 efx_sriov_mac_address_changed(efx);
8ceee660
BH		 2127
2128 /* Reconfigure the MAC */
d3245b28 2129 mutex_lock(&efx->mac_lock);
710b208d 2130 efx->type->reconfigure_mac(efx);
d3245b28 2131 mutex_unlock(&efx->mac_lock);
8ceee660
BH		 2132
2133 return 0;
2134}
2135
a816f75a 2136/* Context: netif_addr_lock held, BHs disabled. */
0fca8c97 2137static void efx_set_rx_mode(struct net_device *net_dev)
8ceee660 2138{
767e468c 2139 struct efx_nic *efx = netdev_priv(net_dev);
a816f75a 2140
8be4f3e6
BH		 2141 if (efx->port_enabled)
2142 queue_work(efx->workqueue, &efx->mac_work);
2143 /* Otherwise efx_start_port() will do this */
8ceee660
BH		 2144}
2145
c8f44aff 2146static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
abfe9039
BH		 2147{
2148 struct efx_nic *efx = netdev_priv(net_dev);
2149
2150 /* If disabling RX n-tuple filtering, clear existing filters */
2151 if (net_dev->features & ~data & NETIF_F_NTUPLE)
fbd79120 2152 return efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
abfe9039
BH		 2153
2154 return 0;
2155}
2156
8127d661 2157static const struct net_device_ops efx_farch_netdev_ops = {
c3ecb9f3
SH		 2158 .ndo_open = efx_net_open,
2159 .ndo_stop = efx_net_stop,
4472702e 2160 .ndo_get_stats64 = efx_net_stats,
c3ecb9f3
SH		 2161 .ndo_tx_timeout = efx_watchdog,
2162 .ndo_start_xmit = efx_hard_start_xmit,
2163 .ndo_validate_addr = eth_validate_addr,
2164 .ndo_do_ioctl = efx_ioctl,
2165 .ndo_change_mtu = efx_change_mtu,
2166 .ndo_set_mac_address = efx_set_mac_address,
0fca8c97 2167 .ndo_set_rx_mode = efx_set_rx_mode,
abfe9039 2168 .ndo_set_features = efx_set_features,
cd2d5b52
BH		 2169#ifdef CONFIG_SFC_SRIOV
2170 .ndo_set_vf_mac = efx_sriov_set_vf_mac,
2171 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
2172 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
2173 .ndo_get_vf_config = efx_sriov_get_vf_config,
2174#endif
c3ecb9f3
SH		 2175#ifdef CONFIG_NET_POLL_CONTROLLER
2176 .ndo_poll_controller = efx_netpoll,
2177#endif
94b274bf 2178 .ndo_setup_tc = efx_setup_tc,
64d8ad6d
BH		 2179#ifdef CONFIG_RFS_ACCEL
2180 .ndo_rx_flow_steer = efx_filter_rfs,
2181#endif
c3ecb9f3
SH		 2182};
2183
8127d661
BH		 2184static const struct net_device_ops efx_ef10_netdev_ops = {
2185 .ndo_open = efx_net_open,
2186 .ndo_stop = efx_net_stop,
2187 .ndo_get_stats64 = efx_net_stats,
2188 .ndo_tx_timeout = efx_watchdog,
2189 .ndo_start_xmit = efx_hard_start_xmit,
2190 .ndo_validate_addr = eth_validate_addr,
2191 .ndo_do_ioctl = efx_ioctl,
2192 .ndo_change_mtu = efx_change_mtu,
2193 .ndo_set_mac_address = efx_set_mac_address,
2194 .ndo_set_rx_mode = efx_set_rx_mode,
2195 .ndo_set_features = efx_set_features,
2196#ifdef CONFIG_NET_POLL_CONTROLLER
2197 .ndo_poll_controller = efx_netpoll,
2198#endif
2199#ifdef CONFIG_RFS_ACCEL
2200 .ndo_rx_flow_steer = efx_filter_rfs,
2201#endif
2202};
2203
7dde596e
BH		 2204static void efx_update_name(struct efx_nic *efx)
2205{
2206 strcpy(efx->name, efx->net_dev->name);
2207 efx_mtd_rename(efx);
2208 efx_set_channel_names(efx);
2209}
2210
8ceee660
BH		 2211static int efx_netdev_event(struct notifier_block *this,
2212 unsigned long event, void *ptr)
2213{
351638e7 2214 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr);
8ceee660 2215
8127d661
BH		 2216 if ((net_dev->netdev_ops == &efx_farch_netdev_ops ||
2217 net_dev->netdev_ops == &efx_ef10_netdev_ops) &&
7dde596e
BH		 2218 event == NETDEV_CHANGENAME)
2219 efx_update_name(netdev_priv(net_dev));
8ceee660
BH		 2220
2221 return NOTIFY_DONE;
2222}
2223
2224static struct notifier_block efx_netdev_notifier = {
2225 .notifier_call = efx_netdev_event,
2226};
2227
06d5e193
BH		 2228static ssize_t
2229show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
2230{
2231 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2232 return sprintf(buf, "%d\n", efx->phy_type);
2233}
776fbcc9 2234static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL);
06d5e193 2235
8ceee660
BH		 2236static int efx_register_netdev(struct efx_nic *efx)
2237{
2238 struct net_device *net_dev = efx->net_dev;
c04bfc6b 2239 struct efx_channel *channel;
8ceee660
BH		 2240 int rc;
2241
2242 net_dev->watchdog_timeo = 5 * HZ;
2243 net_dev->irq = efx->pci_dev->irq;
8127d661
BH		 2244 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) {
2245 net_dev->netdev_ops = &efx_ef10_netdev_ops;
2246 net_dev->priv_flags |= IFF_UNICAST_FLT;
2247 } else {
2248 net_dev->netdev_ops = &efx_farch_netdev_ops;
2249 }
8ceee660 2250 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
7e6d06f0 2251 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
8ceee660 2252
7dde596e 2253 rtnl_lock();
aed0628d 2254
7153f623
BH		 2255 /* Enable resets to be scheduled and check whether any were
2256 * already requested. If so, the NIC is probably hosed so we
2257 * abort.
2258 */
2259 efx->state = STATE_READY;
2260 smp_mb(); /* ensure we change state before checking reset_pending */
2261 if (efx->reset_pending) {
2262 netif_err(efx, probe, efx->net_dev,
2263 "aborting probe due to scheduled reset\n");
2264 rc = -EIO;
2265 goto fail_locked;
2266 }
2267
aed0628d
BH		 2268 rc = dev_alloc_name(net_dev, net_dev->name);
2269 if (rc < 0)
2270 goto fail_locked;
7dde596e 2271 efx_update_name(efx);
aed0628d 2272
8f8b3d51
BH		 2273 /* Always start with carrier off; PHY events will detect the link */
2274 netif_carrier_off(net_dev);
2275
aed0628d
BH		 2276 rc = register_netdevice(net_dev);
2277 if (rc)
2278 goto fail_locked;
2279
c04bfc6b
BH		 2280 efx_for_each_channel(channel, efx) {
2281 struct efx_tx_queue *tx_queue;
60031fcc
BH		 2282 efx_for_each_channel_tx_queue(tx_queue, channel)
2283 efx_init_tx_queue_core_txq(tx_queue);
c04bfc6b
BH		 2284 }
2285
0bcf4a64
BH		 2286 efx_associate(efx);
2287
7dde596e 2288 rtnl_unlock();
8ceee660 2289
06d5e193
BH		 2290 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2291 if (rc) {
62776d03
BH		 2292 netif_err(efx, drv, efx->net_dev,
2293 "failed to init net dev attributes\n");
06d5e193
BH		 2294 goto fail_registered;
2295 }
2296
8ceee660 2297 return 0;
06d5e193 2298
7153f623
BH		 2299fail_registered:
2300 rtnl_lock();
0bcf4a64 2301 efx_dissociate(efx);
7153f623 2302 unregister_netdevice(net_dev);
aed0628d 2303fail_locked:
7153f623 2304 efx->state = STATE_UNINIT;
aed0628d 2305 rtnl_unlock();
62776d03 2306 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
aed0628d 2307 return rc;
8ceee660
BH		 2308}
2309
2310static void efx_unregister_netdev(struct efx_nic *efx)
2311{
8ceee660
BH		 2312 if (!efx->net_dev)
2313 return;
2314
767e468c 2315 BUG_ON(netdev_priv(efx->net_dev) != efx);
8ceee660 2316
73ba7b68
BH		 2317 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2318 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
7153f623
BH		 2319
2320 rtnl_lock();
2321 unregister_netdevice(efx->net_dev);
2322 efx->state = STATE_UNINIT;
2323 rtnl_unlock();
8ceee660
BH		 2324}
2325
2326/**************************************************************************
2327 *
2328 * Device reset and suspend
2329 *
2330 **************************************************************************/
2331
2467ca46
BH		 2332/* Tears down the entire software state and most of the hardware state
2333 * before reset. */
d3245b28 2334void efx_reset_down(struct efx_nic *efx, enum reset_type method)
8ceee660 2335{
8ceee660
BH		 2336 EFX_ASSERT_RESET_SERIALISED(efx);
2337
2467ca46 2338 efx_stop_all(efx);
d8291187 2339 efx_disable_interrupts(efx);
5642ceef
BH		 2340
2341 mutex_lock(&efx->mac_lock);
4b988280
SH		 2342 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
2343 efx->phy_op->fini(efx);
ef2b90ee 2344 efx->type->fini(efx);
8ceee660
BH		 2345}
2346
2467ca46
BH		 2347/* This function will always ensure that the locks acquired in
2348 * efx_reset_down() are released. A failure return code indicates
2349 * that we were unable to reinitialise the hardware, and the
2350 * driver should be disabled. If ok is false, then the rx and tx
2351 * engines are not restarted, pending a RESET_DISABLE. */
d3245b28 2352int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
8ceee660
BH		 2353{
2354 int rc;
2355
2467ca46 2356 EFX_ASSERT_RESET_SERIALISED(efx);
8ceee660 2357
ef2b90ee 2358 rc = efx->type->init(efx);
8ceee660 2359 if (rc) {
62776d03 2360 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
eb9f6744 2361 goto fail;
8ceee660
BH		 2362 }
2363
eb9f6744
BH		 2364 if (!ok)
2365 goto fail;
2366
4b988280 2367 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
eb9f6744
BH		 2368 rc = efx->phy_op->init(efx);
2369 if (rc)
2370 goto fail;
2371 if (efx->phy_op->reconfigure(efx))
62776d03
BH		 2372 netif_err(efx, drv, efx->net_dev,
2373 "could not restore PHY settings\n");
4b988280
SH		 2374 }
2375
261e4d96
JC		 2376 rc = efx_enable_interrupts(efx);
2377 if (rc)
2378 goto fail;
64eebcfd 2379 efx_restore_filters(efx);
cd2d5b52 2380 efx_sriov_reset(efx);
eb9f6744 2381
eb9f6744
BH		 2382 mutex_unlock(&efx->mac_lock);
2383
2384 efx_start_all(efx);
2385
2386 return 0;
2387
2388fail:
2389 efx->port_initialized = false;
2467ca46
BH		 2390
2391 mutex_unlock(&efx->mac_lock);
2392
8ceee660
BH		 2393 return rc;
2394}
2395
eb9f6744
BH		 2396/* Reset the NIC using the specified method. Note that the reset may
2397 * fail, in which case the card will be left in an unusable state.
8ceee660 2398 *
eb9f6744 2399 * Caller must hold the rtnl_lock.
8ceee660 2400 */
eb9f6744 2401int efx_reset(struct efx_nic *efx, enum reset_type method)
8ceee660 2402{
eb9f6744
BH		 2403 int rc, rc2;
2404 bool disabled;
8ceee660 2405
62776d03
BH		 2406 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2407 RESET_TYPE(method));
8ceee660 2408
c2f3b8e3 2409 efx_device_detach_sync(efx);
d3245b28 2410 efx_reset_down(efx, method);
8ceee660 2411
ef2b90ee 2412 rc = efx->type->reset(efx, method);
8ceee660 2413 if (rc) {
62776d03 2414 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
eb9f6744 2415 goto out;
8ceee660
BH		 2416 }
2417
a7d529ae
BH		 2418 /* Clear flags for the scopes we covered. We assume the NIC and
2419 * driver are now quiescent so that there is no race here.
2420 */
2421 efx->reset_pending &= -(1 << (method + 1));
8ceee660
BH		 2422
2423 /* Reinitialise bus-mastering, which may have been turned off before
2424 * the reset was scheduled. This is still appropriate, even in the
2425 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2426 * can respond to requests. */
2427 pci_set_master(efx->pci_dev);
2428
eb9f6744 2429out:
8ceee660 2430 /* Leave device stopped if necessary */
626950db
AR		 2431 disabled = rc ||
2432 method == RESET_TYPE_DISABLE ||
2433 method == RESET_TYPE_RECOVER_OR_DISABLE;
eb9f6744
BH		 2434 rc2 = efx_reset_up(efx, method, !disabled);
2435 if (rc2) {
2436 disabled = true;
2437 if (!rc)
2438 rc = rc2;
8ceee660
BH		 2439 }
2440
eb9f6744 2441 if (disabled) {
f49a4589 2442 dev_close(efx->net_dev);
62776d03 2443 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
f4bd954e 2444 efx->state = STATE_DISABLED;
f4bd954e 2445 } else {
62776d03 2446 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
e4abce85 2447 netif_device_attach(efx->net_dev);
f4bd954e 2448 }
8ceee660
BH		 2449 return rc;
2450}
2451
626950db
AR		 2452/* Try recovery mechanisms.
2453 * For now only EEH is supported.
2454 * Returns 0 if the recovery mechanisms are unsuccessful.
2455 * Returns a non-zero value otherwise.
2456 */
b28405b0 2457int efx_try_recovery(struct efx_nic *efx)
626950db
AR		 2458{
2459#ifdef CONFIG_EEH
2460 /* A PCI error can occur and not be seen by EEH because nothing
2461 * happens on the PCI bus. In this case the driver may fail and
2462 * schedule a 'recover or reset', leading to this recovery handler.
2463 * Manually call the eeh failure check function.
2464 */
2465 struct eeh_dev *eehdev =
2466 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
2467
2468 if (eeh_dev_check_failure(eehdev)) {
2469 /* The EEH mechanisms will handle the error and reset the
2470 * device if necessary.
2471 */
2472 return 1;
2473 }
2474#endif
2475 return 0;
2476}
2477
74cd60a4
JC		 2478static void efx_wait_for_bist_end(struct efx_nic *efx)
2479{
2480 int i;
2481
2482 for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) {
2483 if (efx_mcdi_poll_reboot(efx))
2484 goto out;
2485 msleep(BIST_WAIT_DELAY_MS);
2486 }
2487
2488 netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n");
2489out:
2490 /* Either way unset the BIST flag. If we found no reboot we probably
2491 * won't recover, but we should try.
2492 */
2493 efx->mc_bist_for_other_fn = false;
2494}
2495
8ceee660
BH		 2496/* The worker thread exists so that code that cannot sleep can
2497 * schedule a reset for later.
2498 */
2499static void efx_reset_work(struct work_struct *data)
2500{
eb9f6744 2501 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
626950db
AR		 2502 unsigned long pending;
2503 enum reset_type method;
2504
2505 pending = ACCESS_ONCE(efx->reset_pending);
2506 method = fls(pending) - 1;
2507
74cd60a4
JC		 2508 if (method == RESET_TYPE_MC_BIST)
2509 efx_wait_for_bist_end(efx);
2510
626950db
AR		 2511 if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
2512 method == RESET_TYPE_RECOVER_OR_ALL) &&
2513 efx_try_recovery(efx))
2514 return;
8ceee660 2515
a7d529ae 2516 if (!pending)
319ba649
SH		 2517 return;
2518
eb9f6744 2519 rtnl_lock();
7153f623
BH		 2520
2521 /* We checked the state in efx_schedule_reset() but it may
2522 * have changed by now. Now that we have the RTNL lock,
2523 * it cannot change again.
2524 */
2525 if (efx->state == STATE_READY)
626950db 2526 (void)efx_reset(efx, method);
7153f623 2527
eb9f6744 2528 rtnl_unlock();
8ceee660
BH		 2529}
2530
2531void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2532{
2533 enum reset_type method;
2534
626950db
AR		 2535 if (efx->state == STATE_RECOVERY) {
2536 netif_dbg(efx, drv, efx->net_dev,
2537 "recovering: skip scheduling %s reset\n",
2538 RESET_TYPE(type));
2539 return;
2540 }
2541
8ceee660
BH		 2542 switch (type) {
2543 case RESET_TYPE_INVISIBLE:
2544 case RESET_TYPE_ALL:
626950db 2545 case RESET_TYPE_RECOVER_OR_ALL:
8ceee660
BH		 2546 case RESET_TYPE_WORLD:
2547 case RESET_TYPE_DISABLE:
626950db 2548 case RESET_TYPE_RECOVER_OR_DISABLE:
74cd60a4 2549 case RESET_TYPE_MC_BIST:
8ceee660 2550 method = type;
0e2a9c7c
BH		 2551 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2552 RESET_TYPE(method));
8ceee660 2553 break;
8ceee660 2554 default:
0e2a9c7c 2555 method = efx->type->map_reset_reason(type);
62776d03
BH		 2556 netif_dbg(efx, drv, efx->net_dev,
2557 "scheduling %s reset for %s\n",
2558 RESET_TYPE(method), RESET_TYPE(type));
0e2a9c7c
BH		 2559 break;
2560 }
8ceee660 2561
a7d529ae 2562 set_bit(method, &efx->reset_pending);
7153f623
BH		 2563 smp_mb(); /* ensure we change reset_pending before checking state */
2564
2565 /* If we're not READY then just leave the flags set as the cue
2566 * to abort probing or reschedule the reset later.
2567 */
2568 if (ACCESS_ONCE(efx->state) != STATE_READY)
2569 return;
8ceee660 2570
8880f4ec
BH		 2571 /* efx_process_channel() will no longer read events once a
2572 * reset is scheduled. So switch back to poll'd MCDI completions. */
2573 efx_mcdi_mode_poll(efx);
2574
1ab00629 2575 queue_work(reset_workqueue, &efx->reset_work);
8ceee660
BH		 2576}
2577
2578/**************************************************************************
2579 *
2580 * List of NICs we support
2581 *
2582 **************************************************************************/
2583
2584/* PCI device ID table */
a3aa1884 2585static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
937383a5
BH		 2586 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2587 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0),
daeda630 2588 .driver_data = (unsigned long) &falcon_a1_nic_type},
937383a5
BH		 2589 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2590 PCI_DEVICE_ID_SOLARFLARE_SFC4000B),
daeda630 2591 .driver_data = (unsigned long) &falcon_b0_nic_type},
547c474f 2592 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
8880f4ec 2593 .driver_data = (unsigned long) &siena_a0_nic_type},
547c474f 2594 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
8880f4ec 2595 .driver_data = (unsigned long) &siena_a0_nic_type},
8127d661
BH		 2596 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */
2597 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
8ceee660
BH		 2598 {0} /* end of list */
2599};
2600
2601/**************************************************************************
2602 *
3759433d 2603 * Dummy PHY/MAC operations
8ceee660 2604 *
01aad7b6 2605 * Can be used for some unimplemented operations
8ceee660
BH		 2606 * Needed so all function pointers are valid and do not have to be tested
2607 * before use
2608 *
2609 **************************************************************************/
2610int efx_port_dummy_op_int(struct efx_nic *efx)
2611{
2612 return 0;
2613}
2614void efx_port_dummy_op_void(struct efx_nic *efx) {}
d215697f 2615
2616static bool efx_port_dummy_op_poll(struct efx_nic *efx)
fdaa9aed
SH		 2617{
2618 return false;
2619}
8ceee660 2620
6c8c2513 2621static const struct efx_phy_operations efx_dummy_phy_operations = {
8ceee660 2622 .init = efx_port_dummy_op_int,
d3245b28 2623 .reconfigure = efx_port_dummy_op_int,
fdaa9aed 2624 .poll = efx_port_dummy_op_poll,
8ceee660 2625 .fini = efx_port_dummy_op_void,
8ceee660
BH		 2626};
2627
8ceee660
BH		 2628/**************************************************************************
2629 *
2630 * Data housekeeping
2631 *
2632 **************************************************************************/
2633
2634/* This zeroes out and then fills in the invariants in a struct
2635 * efx_nic (including all sub-structures).
2636 */
adeb15aa 2637static int efx_init_struct(struct efx_nic *efx,
8ceee660
BH		 2638 struct pci_dev *pci_dev, struct net_device *net_dev)
2639{
4642610c 2640 int i;
8ceee660
BH		 2641
2642 /* Initialise common structures */
0bcf4a64
BH		 2643 INIT_LIST_HEAD(&efx->node);
2644 INIT_LIST_HEAD(&efx->secondary_list);
8ceee660 2645 spin_lock_init(&efx->biu_lock);
76884835
BH		 2646#ifdef CONFIG_SFC_MTD
2647 INIT_LIST_HEAD(&efx->mtd_list);
2648#endif
8ceee660
BH		 2649 INIT_WORK(&efx->reset_work, efx_reset_work);
2650 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
dd40781e 2651 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
8ceee660 2652 efx->pci_dev = pci_dev;
62776d03 2653 efx->msg_enable = debug;
f16aeea0 2654 efx->state = STATE_UNINIT;
8ceee660 2655 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
8ceee660
BH		 2656
2657 efx->net_dev = net_dev;
43a3739d 2658 efx->rx_prefix_size = efx->type->rx_prefix_size;
2ec03014
AR		 2659 efx->rx_ip_align =
2660 NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0;
43a3739d
JC		 2661 efx->rx_packet_hash_offset =
2662 efx->type->rx_hash_offset - efx->type->rx_prefix_size;
bd9a265d
JC		 2663 efx->rx_packet_ts_offset =
2664 efx->type->rx_ts_offset - efx->type->rx_prefix_size;
8ceee660
BH		 2665 spin_lock_init(&efx->stats_lock);
2666 mutex_init(&efx->mac_lock);
2667 efx->phy_op = &efx_dummy_phy_operations;
68e7f45e 2668 efx->mdio.dev = net_dev;
766ca0fa 2669 INIT_WORK(&efx->mac_work, efx_mac_work);
9f2cb71c 2670 init_waitqueue_head(&efx->flush_wq);
8ceee660
BH		 2671
2672 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
4642610c
BH		 2673 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2674 if (!efx->channel[i])
2675 goto fail;
d8291187
BH		 2676 efx->msi_context[i].efx = efx;
2677 efx->msi_context[i].index = i;
8ceee660
BH		 2678 }
2679
8ceee660
BH		 2680 /* Higher numbered interrupt modes are less capable! */
2681 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2682 interrupt_mode);
2683
6977dc63
BH		 2684 /* Would be good to use the net_dev name, but we're too early */
2685 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2686 pci_name(pci_dev));
2687 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1ab00629 2688 if (!efx->workqueue)
4642610c 2689 goto fail;
8d9853d9 2690
8ceee660 2691 return 0;
4642610c
BH		 2692
2693fail:
2694 efx_fini_struct(efx);
2695 return -ENOMEM;
8ceee660
BH		 2696}
2697
2698static void efx_fini_struct(struct efx_nic *efx)
2699{
8313aca3
BH		 2700 int i;
2701
2702 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2703 kfree(efx->channel[i]);
2704
ef215e64
BH		 2705 kfree(efx->vpd_sn);
2706
8ceee660
BH		 2707 if (efx->workqueue) {
2708 destroy_workqueue(efx->workqueue);
2709 efx->workqueue = NULL;
2710 }
2711}
2712
2713/**************************************************************************
2714 *
2715 * PCI interface
2716 *
2717 **************************************************************************/
2718
2719/* Main body of final NIC shutdown code
2720 * This is called only at module unload (or hotplug removal).
2721 */
2722static void efx_pci_remove_main(struct efx_nic *efx)
2723{
7153f623
BH		 2724 /* Flush reset_work. It can no longer be scheduled since we
2725 * are not READY.
2726 */
2727 BUG_ON(efx->state == STATE_READY);
2728 cancel_work_sync(&efx->reset_work);
2729
d8291187 2730 efx_disable_interrupts(efx);
152b6a62 2731 efx_nic_fini_interrupt(efx);
8ceee660 2732 efx_fini_port(efx);
ef2b90ee 2733 efx->type->fini(efx);
8ceee660
BH		 2734 efx_fini_napi(efx);
2735 efx_remove_all(efx);
2736}
2737
2738/* Final NIC shutdown
2739 * This is called only at module unload (or hotplug removal).
2740 */
2741static void efx_pci_remove(struct pci_dev *pci_dev)
2742{
2743 struct efx_nic *efx;
2744
2745 efx = pci_get_drvdata(pci_dev);
2746 if (!efx)
2747 return;
2748
2749 /* Mark the NIC as fini, then stop the interface */
2750 rtnl_lock();
0bcf4a64 2751 efx_dissociate(efx);
8ceee660 2752 dev_close(efx->net_dev);
d8291187 2753 efx_disable_interrupts(efx);
8ceee660
BH		 2754 rtnl_unlock();
2755
cd2d5b52 2756 efx_sriov_fini(efx);
8ceee660
BH		 2757 efx_unregister_netdev(efx);
2758
7dde596e
BH		 2759 efx_mtd_remove(efx);
2760
8ceee660
BH		 2761 efx_pci_remove_main(efx);
2762
8ceee660 2763 efx_fini_io(efx);
62776d03 2764 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
8ceee660 2765
8ceee660
BH		 2766 efx_fini_struct(efx);
2767 free_netdev(efx->net_dev);
626950db
AR		 2768
2769 pci_disable_pcie_error_reporting(pci_dev);
8ceee660
BH		 2770};
2771
460eeaa0
BH		 2772/* NIC VPD information
2773 * Called during probe to display the part number of the
2774 * installed NIC. VPD is potentially very large but this should
2775 * always appear within the first 512 bytes.
2776 */
2777#define SFC_VPD_LEN 512
ef215e64 2778static void efx_probe_vpd_strings(struct efx_nic *efx)
460eeaa0
BH		 2779{
2780 struct pci_dev *dev = efx->pci_dev;
2781 char vpd_data[SFC_VPD_LEN];
2782 ssize_t vpd_size;
ef215e64 2783 int ro_start, ro_size, i, j;
460eeaa0
BH		 2784
2785 /* Get the vpd data from the device */
2786 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
2787 if (vpd_size <= 0) {
2788 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
2789 return;
2790 }
2791
2792 /* Get the Read only section */
ef215e64
BH		 2793 ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
2794 if (ro_start < 0) {
460eeaa0
BH		 2795 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
2796 return;
2797 }
2798
ef215e64
BH		 2799 ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]);
2800 j = ro_size;
2801 i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
460eeaa0
BH		 2802 if (i + j > vpd_size)
2803 j = vpd_size - i;
2804
2805 /* Get the Part number */
2806 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
2807 if (i < 0) {
2808 netif_err(efx, drv, efx->net_dev, "Part number not found\n");
2809 return;
2810 }
2811
2812 j = pci_vpd_info_field_size(&vpd_data[i]);
2813 i += PCI_VPD_INFO_FLD_HDR_SIZE;
2814 if (i + j > vpd_size) {
2815 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
2816 return;
2817 }
2818
2819 netif_info(efx, drv, efx->net_dev,
2820 "Part Number : %.*s\n", j, &vpd_data[i]);
ef215e64
BH		 2821
2822 i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
2823 j = ro_size;
2824 i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN");
2825 if (i < 0) {
2826 netif_err(efx, drv, efx->net_dev, "Serial number not found\n");
2827 return;
2828 }
2829
2830 j = pci_vpd_info_field_size(&vpd_data[i]);
2831 i += PCI_VPD_INFO_FLD_HDR_SIZE;
2832 if (i + j > vpd_size) {
2833 netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n");
2834 return;
2835 }
2836
2837 efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL);
2838 if (!efx->vpd_sn)
2839 return;
2840
2841 snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]);
460eeaa0
BH		 2842}
2843
2844
8ceee660
BH		 2845/* Main body of NIC initialisation
2846 * This is called at module load (or hotplug insertion, theoretically).
2847 */
2848static int efx_pci_probe_main(struct efx_nic *efx)
2849{
2850 int rc;
2851
2852 /* Do start-of-day initialisation */
2853 rc = efx_probe_all(efx);
2854 if (rc)
2855 goto fail1;
2856
e8f14992 2857 efx_init_napi(efx);
8ceee660 2858
ef2b90ee 2859 rc = efx->type->init(efx);
8ceee660 2860 if (rc) {
62776d03
BH		 2861 netif_err(efx, probe, efx->net_dev,
2862 "failed to initialise NIC\n");
278c0621 2863 goto fail3;
8ceee660
BH		 2864 }
2865
2866 rc = efx_init_port(efx);
2867 if (rc) {
62776d03
BH		 2868 netif_err(efx, probe, efx->net_dev,
2869 "failed to initialise port\n");
278c0621 2870 goto fail4;
8ceee660
BH		 2871 }
2872
152b6a62 2873 rc = efx_nic_init_interrupt(efx);
8ceee660 2874 if (rc)
278c0621 2875 goto fail5;
261e4d96
JC		 2876 rc = efx_enable_interrupts(efx);
2877 if (rc)
2878 goto fail6;
8ceee660
BH		 2879
2880 return 0;
2881
261e4d96
JC		 2882 fail6:
2883 efx_nic_fini_interrupt(efx);
278c0621 2884 fail5:
8ceee660 2885 efx_fini_port(efx);
8ceee660 2886 fail4:
ef2b90ee 2887 efx->type->fini(efx);
8ceee660
BH		 2888 fail3:
2889 efx_fini_napi(efx);
8ceee660
BH		 2890 efx_remove_all(efx);
2891 fail1:
2892 return rc;
2893}
2894
2895/* NIC initialisation
2896 *
2897 * This is called at module load (or hotplug insertion,
73ba7b68 2898 * theoretically). It sets up PCI mappings, resets the NIC,
8ceee660
BH		 2899 * sets up and registers the network devices with the kernel and hooks
2900 * the interrupt service routine. It does not prepare the device for
2901 * transmission; this is left to the first time one of the network
2902 * interfaces is brought up (i.e. efx_net_open).
2903 */
87d1fc11 2904static int efx_pci_probe(struct pci_dev *pci_dev,
1dd06ae8 2905 const struct pci_device_id *entry)
8ceee660 2906{
8ceee660
BH		 2907 struct net_device *net_dev;
2908 struct efx_nic *efx;
fadac6aa 2909 int rc;
8ceee660
BH		 2910
2911 /* Allocate and initialise a struct net_device and struct efx_nic */
94b274bf
BH		 2912 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
2913 EFX_MAX_RX_QUEUES);
8ceee660
BH		 2914 if (!net_dev)
2915 return -ENOMEM;
adeb15aa
BH		 2916 efx = netdev_priv(net_dev);
2917 efx->type = (const struct efx_nic_type *) entry->driver_data;
2918 net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
97bc5415 2919 NETIF_F_HIGHDMA | NETIF_F_TSO |
abfe9039 2920 NETIF_F_RXCSUM);
adeb15aa 2921 if (efx->type->offload_features & NETIF_F_V6_CSUM)
738a8f4b 2922 net_dev->features |= NETIF_F_TSO6;
28506563
BH		 2923 /* Mask for features that also apply to VLAN devices */
2924 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
abfe9039
BH		 2925 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
2926 NETIF_F_RXCSUM);
2927 /* All offloads can be toggled */
2928 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA;
8ceee660 2929 pci_set_drvdata(pci_dev, efx);
62776d03 2930 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
adeb15aa 2931 rc = efx_init_struct(efx, pci_dev, net_dev);
8ceee660
BH		 2932 if (rc)
2933 goto fail1;
2934
62776d03 2935 netif_info(efx, probe, efx->net_dev,
ff79c8ac 2936 "Solarflare NIC detected\n");
8ceee660 2937
ef215e64 2938 efx_probe_vpd_strings(efx);
460eeaa0 2939
8ceee660
BH		 2940 /* Set up basic I/O (BAR mappings etc) */
2941 rc = efx_init_io(efx);
2942 if (rc)
2943 goto fail2;
2944
fadac6aa 2945 rc = efx_pci_probe_main(efx);
fadac6aa
BH		 2946 if (rc)
2947 goto fail3;
8ceee660 2948
8ceee660
BH		 2949 rc = efx_register_netdev(efx);
2950 if (rc)
fadac6aa 2951 goto fail4;
8ceee660 2952
cd2d5b52
BH		 2953 rc = efx_sriov_init(efx);
2954 if (rc)
2955 netif_err(efx, probe, efx->net_dev,
2956 "SR-IOV can't be enabled rc %d\n", rc);
2957
62776d03 2958 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
a5211bb5 2959
7c43161c 2960 /* Try to create MTDs, but allow this to fail */
a5211bb5 2961 rtnl_lock();
7c43161c 2962 rc = efx_mtd_probe(efx);
a5211bb5 2963 rtnl_unlock();
7c43161c
BH		 2964 if (rc)
2965 netif_warn(efx, probe, efx->net_dev,
2966 "failed to create MTDs (%d)\n", rc);
2967
626950db
AR		 2968 rc = pci_enable_pcie_error_reporting(pci_dev);
2969 if (rc && rc != -EINVAL)
2970 netif_warn(efx, probe, efx->net_dev,
2971 "pci_enable_pcie_error_reporting failed (%d)\n", rc);
2972
8ceee660
BH		 2973 return 0;
2974
8ceee660 2975 fail4:
fadac6aa 2976 efx_pci_remove_main(efx);
8ceee660
BH		 2977 fail3:
2978 efx_fini_io(efx);
2979 fail2:
2980 efx_fini_struct(efx);
2981 fail1:
5e2a911c 2982 WARN_ON(rc > 0);
62776d03 2983 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
8ceee660
BH		 2984 free_netdev(net_dev);
2985 return rc;
2986}
2987
89c758fa
BH		 2988static int efx_pm_freeze(struct device *dev)
2989{
2990 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2991
61da026d
BH		 2992 rtnl_lock();
2993
6032fb56
BH		 2994 if (efx->state != STATE_DISABLED) {
2995 efx->state = STATE_UNINIT;
89c758fa 2996
c2f3b8e3 2997 efx_device_detach_sync(efx);
89c758fa 2998
6032fb56 2999 efx_stop_all(efx);
d8291187 3000 efx_disable_interrupts(efx);
6032fb56 3001 }
89c758fa 3002
61da026d
BH		 3003 rtnl_unlock();
3004
89c758fa
BH		 3005 return 0;
3006}
3007
3008static int efx_pm_thaw(struct device *dev)
3009{
261e4d96 3010 int rc;
89c758fa
BH		 3011 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
3012
61da026d
BH		 3013 rtnl_lock();
3014
6032fb56 3015 if (efx->state != STATE_DISABLED) {
261e4d96
JC		 3016 rc = efx_enable_interrupts(efx);
3017 if (rc)
3018 goto fail;
89c758fa 3019
6032fb56
BH		 3020 mutex_lock(&efx->mac_lock);
3021 efx->phy_op->reconfigure(efx);
3022 mutex_unlock(&efx->mac_lock);
89c758fa 3023
6032fb56 3024 efx_start_all(efx);
89c758fa 3025
6032fb56 3026 netif_device_attach(efx->net_dev);
89c758fa 3027
6032fb56 3028 efx->state = STATE_READY;
89c758fa 3029
6032fb56
BH		 3030 efx->type->resume_wol(efx);
3031 }
89c758fa 3032
61da026d
BH		 3033 rtnl_unlock();
3034
319ba649
SH		 3035 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
3036 queue_work(reset_workqueue, &efx->reset_work);
3037
89c758fa 3038 return 0;
261e4d96
JC		 3039
3040fail:
3041 rtnl_unlock();
3042
3043 return rc;
89c758fa
BH		 3044}
3045
3046static int efx_pm_poweroff(struct device *dev)
3047{
3048 struct pci_dev *pci_dev = to_pci_dev(dev);
3049 struct efx_nic *efx = pci_get_drvdata(pci_dev);
3050
3051 efx->type->fini(efx);
3052
a7d529ae 3053 efx->reset_pending = 0;
89c758fa
BH		 3054
3055 pci_save_state(pci_dev);
3056 return pci_set_power_state(pci_dev, PCI_D3hot);
3057}
3058
3059/* Used for both resume and restore */
3060static int efx_pm_resume(struct device *dev)
3061{
3062 struct pci_dev *pci_dev = to_pci_dev(dev);
3063 struct efx_nic *efx = pci_get_drvdata(pci_dev);
3064 int rc;
3065
3066 rc = pci_set_power_state(pci_dev, PCI_D0);
3067 if (rc)
3068 return rc;
3069 pci_restore_state(pci_dev);
3070 rc = pci_enable_device(pci_dev);
3071 if (rc)
3072 return rc;
3073 pci_set_master(efx->pci_dev);
3074 rc = efx->type->reset(efx, RESET_TYPE_ALL);
3075 if (rc)
3076 return rc;
3077 rc = efx->type->init(efx);
3078 if (rc)
3079 return rc;
261e4d96
JC		 3080 rc = efx_pm_thaw(dev);
3081 return rc;
89c758fa
BH		 3082}
3083
3084static int efx_pm_suspend(struct device *dev)
3085{
3086 int rc;
3087
3088 efx_pm_freeze(dev);
3089 rc = efx_pm_poweroff(dev);
3090 if (rc)
3091 efx_pm_resume(dev);
3092 return rc;
3093}
3094
18e83e4c 3095static const struct dev_pm_ops efx_pm_ops = {
89c758fa
BH		 3096 .suspend = efx_pm_suspend,
3097 .resume = efx_pm_resume,
3098 .freeze = efx_pm_freeze,
3099 .thaw = efx_pm_thaw,
3100 .poweroff = efx_pm_poweroff,
3101 .restore = efx_pm_resume,
3102};
3103
626950db
AR		 3104/* A PCI error affecting this device was detected.
3105 * At this point MMIO and DMA may be disabled.
3106 * Stop the software path and request a slot reset.
3107 */
debd0034 3108static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
3109 enum pci_channel_state state)
626950db
AR		 3110{
3111 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
3112 struct efx_nic *efx = pci_get_drvdata(pdev);
3113
3114 if (state == pci_channel_io_perm_failure)
3115 return PCI_ERS_RESULT_DISCONNECT;
3116
3117 rtnl_lock();
3118
3119 if (efx->state != STATE_DISABLED) {
3120 efx->state = STATE_RECOVERY;
3121 efx->reset_pending = 0;
3122
3123 efx_device_detach_sync(efx);
3124
3125 efx_stop_all(efx);
d8291187 3126 efx_disable_interrupts(efx);
626950db
AR		 3127
3128 status = PCI_ERS_RESULT_NEED_RESET;
3129 } else {
3130 /* If the interface is disabled we don't want to do anything
3131 * with it.
3132 */
3133 status = PCI_ERS_RESULT_RECOVERED;
3134 }
3135
3136 rtnl_unlock();
3137
3138 pci_disable_device(pdev);
3139
3140 return status;
3141}
3142
3143/* Fake a successfull reset, which will be performed later in efx_io_resume. */
debd0034 3144static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
626950db
AR		 3145{
3146 struct efx_nic *efx = pci_get_drvdata(pdev);
3147 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
3148 int rc;
3149
3150 if (pci_enable_device(pdev)) {
3151 netif_err(efx, hw, efx->net_dev,
3152 "Cannot re-enable PCI device after reset.\n");
3153 status = PCI_ERS_RESULT_DISCONNECT;
3154 }
3155
3156 rc = pci_cleanup_aer_uncorrect_error_status(pdev);
3157 if (rc) {
3158 netif_err(efx, hw, efx->net_dev,
3159 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc);
3160 /* Non-fatal error. Continue. */
3161 }
3162
3163 return status;
3164}
3165
3166/* Perform the actual reset and resume I/O operations. */
3167static void efx_io_resume(struct pci_dev *pdev)
3168{
3169 struct efx_nic *efx = pci_get_drvdata(pdev);
3170 int rc;
3171
3172 rtnl_lock();
3173
3174 if (efx->state == STATE_DISABLED)
3175 goto out;
3176
3177 rc = efx_reset(efx, RESET_TYPE_ALL);
3178 if (rc) {
3179 netif_err(efx, hw, efx->net_dev,
3180 "efx_reset failed after PCI error (%d)\n", rc);
3181 } else {
3182 efx->state = STATE_READY;
3183 netif_dbg(efx, hw, efx->net_dev,
3184 "Done resetting and resuming IO after PCI error.\n");
3185 }
3186
3187out:
3188 rtnl_unlock();
3189}
3190
3191/* For simplicity and reliability, we always require a slot reset and try to
3192 * reset the hardware when a pci error affecting the device is detected.
3193 * We leave both the link_reset and mmio_enabled callback unimplemented:
3194 * with our request for slot reset the mmio_enabled callback will never be
3195 * called, and the link_reset callback is not used by AER or EEH mechanisms.
3196 */
3197static struct pci_error_handlers efx_err_handlers = {
3198 .error_detected = efx_io_error_detected,
3199 .slot_reset = efx_io_slot_reset,
3200 .resume = efx_io_resume,
3201};
3202
8ceee660 3203static struct pci_driver efx_pci_driver = {
c5d5f5fd 3204 .name = KBUILD_MODNAME,
8ceee660
BH		 3205 .id_table = efx_pci_table,
3206 .probe = efx_pci_probe,
3207 .remove = efx_pci_remove,
89c758fa 3208 .driver.pm = &efx_pm_ops,
626950db 3209 .err_handler = &efx_err_handlers,
8ceee660
BH		 3210};
3211
3212/**************************************************************************
3213 *
3214 * Kernel module interface
3215 *
3216 *************************************************************************/
3217
3218module_param(interrupt_mode, uint, 0444);
3219MODULE_PARM_DESC(interrupt_mode,
3220 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
3221
3222static int __init efx_init_module(void)
3223{
3224 int rc;
3225
3226 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
3227
3228 rc = register_netdevice_notifier(&efx_netdev_notifier);
3229 if (rc)
3230 goto err_notifier;
3231
cd2d5b52
BH		 3232 rc = efx_init_sriov();
3233 if (rc)
3234 goto err_sriov;
3235
1ab00629
SH		 3236 reset_workqueue = create_singlethread_workqueue("sfc_reset");
3237 if (!reset_workqueue) {
3238 rc = -ENOMEM;
3239 goto err_reset;
3240 }
8ceee660
BH		 3241
3242 rc = pci_register_driver(&efx_pci_driver);
3243 if (rc < 0)
3244 goto err_pci;
3245
3246 return 0;
3247
3248 err_pci:
1ab00629
SH		 3249 destroy_workqueue(reset_workqueue);
3250 err_reset:
cd2d5b52
BH		 3251 efx_fini_sriov();
3252 err_sriov:
8ceee660
BH		 3253 unregister_netdevice_notifier(&efx_netdev_notifier);
3254 err_notifier:
3255 return rc;
3256}
3257
3258static void __exit efx_exit_module(void)
3259{
3260 printk(KERN_INFO "Solarflare NET driver unloading\n");
3261
3262 pci_unregister_driver(&efx_pci_driver);
1ab00629 3263 destroy_workqueue(reset_workqueue);
cd2d5b52 3264 efx_fini_sriov();
8ceee660
BH		 3265 unregister_netdevice_notifier(&efx_netdev_notifier);
3266
3267}
3268
3269module_init(efx_init_module);
3270module_exit(efx_exit_module);
3271
906bb26c
BH		 3272MODULE_AUTHOR("Solarflare Communications and "
3273 "Michael Brown <mbrown@fensystems.co.uk>");
6a350fdb 3274MODULE_DESCRIPTION("Solarflare network driver");
8ceee660
BH		 3275MODULE_LICENSE("GPL");
3276MODULE_DEVICE_TABLE(pci, efx_pci_table);
Linux kernel - Deliverables
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