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sfc: Document conditions for multicast replication vs filter replacement
[deliverable/linux.git] / drivers / net / ethernet / sfc / efx.c
CommitLineData
8ceee660
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
0a6f40c6 4 * Copyright 2005-2011 Solarflare Communications Inc.
8ceee660
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
8ceee660 20#include <linux/ethtool.h>
aa6ef27e 21#include <linux/topology.h>
5a0e3ad6 22#include <linux/gfp.h>
626950db 23#include <linux/aer.h>
b28405b0 24#include <linux/interrupt.h>
8ceee660 25#include "net_driver.h"
8ceee660 26#include "efx.h"
744093c9 27#include "nic.h"
dd40781e 28#include "selftest.h"
8ceee660 29
8880f4ec 30#include "mcdi.h"
fd371e32 31#include "workarounds.h"
8880f4ec 32
c459302d
BH		 33/**************************************************************************
34 *
35 * Type name strings
36 *
37 **************************************************************************
38 */
39
40/* Loopback mode names (see LOOPBACK_MODE()) */
41const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
18e83e4c 42const char *const efx_loopback_mode_names[] = {
c459302d 43 [LOOPBACK_NONE] = "NONE",
e58f69f4 44 [LOOPBACK_DATA] = "DATAPATH",
c459302d
BH		 45 [LOOPBACK_GMAC] = "GMAC",
46 [LOOPBACK_XGMII] = "XGMII",
47 [LOOPBACK_XGXS] = "XGXS",
9c636baf
BH		 48 [LOOPBACK_XAUI] = "XAUI",
49 [LOOPBACK_GMII] = "GMII",
50 [LOOPBACK_SGMII] = "SGMII",
e58f69f4
BH		 51 [LOOPBACK_XGBR] = "XGBR",
52 [LOOPBACK_XFI] = "XFI",
53 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
54 [LOOPBACK_GMII_FAR] = "GMII_FAR",
55 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
56 [LOOPBACK_XFI_FAR] = "XFI_FAR",
c459302d
BH		 57 [LOOPBACK_GPHY] = "GPHY",
58 [LOOPBACK_PHYXS] = "PHYXS",
9c636baf
BH		 59 [LOOPBACK_PCS] = "PCS",
60 [LOOPBACK_PMAPMD] = "PMA/PMD",
e58f69f4
BH		 61 [LOOPBACK_XPORT] = "XPORT",
62 [LOOPBACK_XGMII_WS] = "XGMII_WS",
9c636baf 63 [LOOPBACK_XAUI_WS] = "XAUI_WS",
e58f69f4
BH		 64 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
65 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
9c636baf 66 [LOOPBACK_GMII_WS] = "GMII_WS",
e58f69f4
BH		 67 [LOOPBACK_XFI_WS] = "XFI_WS",
68 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
9c636baf 69 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
c459302d
BH		 70};
71
c459302d 72const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
18e83e4c 73const char *const efx_reset_type_names[] = {
626950db
AR		 74 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
75 [RESET_TYPE_ALL] = "ALL",
76 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
77 [RESET_TYPE_WORLD] = "WORLD",
78 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
79 [RESET_TYPE_DISABLE] = "DISABLE",
80 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
81 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
82 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
3de82b91 83 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR",
626950db
AR		 84 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
85 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
c459302d
BH		 86};
87
1ab00629
SH		 88/* Reset workqueue. If any NIC has a hardware failure then a reset will be
89 * queued onto this work queue. This is not a per-nic work queue, because
90 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
91 */
92static struct workqueue_struct *reset_workqueue;
93
8ceee660
BH		 94/**************************************************************************
95 *
96 * Configurable values
97 *
98 *************************************************************************/
99
8ceee660
BH		 100/*
101 * Use separate channels for TX and RX events
102 *
28b581ab
NT		 103 * Set this to 1 to use separate channels for TX and RX. It allows us
104 * to control interrupt affinity separately for TX and RX.
8ceee660 105 *
28b581ab 106 * This is only used in MSI-X interrupt mode
8ceee660 107 */
b9cc977d
BH		 108static bool separate_tx_channels;
109module_param(separate_tx_channels, bool, 0444);
28b581ab
NT		 110MODULE_PARM_DESC(separate_tx_channels,
111 "Use separate channels for TX and RX");
8ceee660
BH		 112
113/* This is the weight assigned to each of the (per-channel) virtual
114 * NAPI devices.
115 */
116static int napi_weight = 64;
117
118/* This is the time (in jiffies) between invocations of the hardware
626950db
AR		 119 * monitor.
120 * On Falcon-based NICs, this will:
e254c274
BH		 121 * - Check the on-board hardware monitor;
122 * - Poll the link state and reconfigure the hardware as necessary.
626950db
AR		 123 * On Siena-based NICs for power systems with EEH support, this will give EEH a
124 * chance to start.
8ceee660 125 */
d215697f 126static unsigned int efx_monitor_interval = 1 * HZ;
8ceee660 127
8ceee660
BH		 128/* Initial interrupt moderation settings. They can be modified after
129 * module load with ethtool.
130 *
131 * The default for RX should strike a balance between increasing the
132 * round-trip latency and reducing overhead.
133 */
134static unsigned int rx_irq_mod_usec = 60;
135
136/* Initial interrupt moderation settings. They can be modified after
137 * module load with ethtool.
138 *
139 * This default is chosen to ensure that a 10G link does not go idle
140 * while a TX queue is stopped after it has become full. A queue is
141 * restarted when it drops below half full. The time this takes (assuming
142 * worst case 3 descriptors per packet and 1024 descriptors) is
143 * 512 / 3 * 1.2 = 205 usec.
144 */
145static unsigned int tx_irq_mod_usec = 150;
146
147/* This is the first interrupt mode to try out of:
148 * 0 => MSI-X
149 * 1 => MSI
150 * 2 => legacy
151 */
152static unsigned int interrupt_mode;
153
154/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
155 * i.e. the number of CPUs among which we may distribute simultaneous
156 * interrupt handling.
157 *
158 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
cdb08f8f 159 * The default (0) means to assign an interrupt to each core.
8ceee660
BH		 160 */
161static unsigned int rss_cpus;
162module_param(rss_cpus, uint, 0444);
163MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
164
b9cc977d
BH		 165static bool phy_flash_cfg;
166module_param(phy_flash_cfg, bool, 0644);
84ae48fe
BH		 167MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
168
e7bed9c8 169static unsigned irq_adapt_low_thresh = 8000;
6fb70fd1
BH		 170module_param(irq_adapt_low_thresh, uint, 0644);
171MODULE_PARM_DESC(irq_adapt_low_thresh,
172 "Threshold score for reducing IRQ moderation");
173
e7bed9c8 174static unsigned irq_adapt_high_thresh = 16000;
6fb70fd1
BH		 175module_param(irq_adapt_high_thresh, uint, 0644);
176MODULE_PARM_DESC(irq_adapt_high_thresh,
177 "Threshold score for increasing IRQ moderation");
178
62776d03
BH		 179static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
180 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
181 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
182 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
183module_param(debug, uint, 0);
184MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
185
8ceee660
BH		 186/**************************************************************************
187 *
188 * Utility functions and prototypes
189 *
190 *************************************************************************/
4642610c 191
d8291187
BH		 192static void efx_soft_enable_interrupts(struct efx_nic *efx);
193static void efx_soft_disable_interrupts(struct efx_nic *efx);
7f967c01 194static void efx_remove_channel(struct efx_channel *channel);
4642610c 195static void efx_remove_channels(struct efx_nic *efx);
7f967c01 196static const struct efx_channel_type efx_default_channel_type;
8ceee660 197static void efx_remove_port(struct efx_nic *efx);
7f967c01 198static void efx_init_napi_channel(struct efx_channel *channel);
8ceee660 199static void efx_fini_napi(struct efx_nic *efx);
e8f14992 200static void efx_fini_napi_channel(struct efx_channel *channel);
4642610c
BH		 201static void efx_fini_struct(struct efx_nic *efx);
202static void efx_start_all(struct efx_nic *efx);
203static void efx_stop_all(struct efx_nic *efx);
8ceee660
BH		 204
205#define EFX_ASSERT_RESET_SERIALISED(efx) \
206 do { \
f16aeea0 207 if ((efx->state == STATE_READY) || \
626950db 208 (efx->state == STATE_RECOVERY) || \
332c1ce9 209 (efx->state == STATE_DISABLED)) \
8ceee660
BH		 210 ASSERT_RTNL(); \
211 } while (0)
212
8b7325b4
BH		 213static int efx_check_disabled(struct efx_nic *efx)
214{
626950db 215 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) {
8b7325b4
BH		 216 netif_err(efx, drv, efx->net_dev,
217 "device is disabled due to earlier errors\n");
218 return -EIO;
219 }
220 return 0;
221}
222
8ceee660
BH		 223/**************************************************************************
224 *
225 * Event queue processing
226 *
227 *************************************************************************/
228
229/* Process channel's event queue
230 *
231 * This function is responsible for processing the event queue of a
232 * single channel. The caller must guarantee that this function will
233 * never be concurrently called more than once on the same channel,
234 * though different channels may be being processed concurrently.
235 */
fa236e18 236static int efx_process_channel(struct efx_channel *channel, int budget)
8ceee660 237{
fa236e18 238 int spent;
8ceee660 239
9f2cb71c 240 if (unlikely(!channel->enabled))
42cbe2d7 241 return 0;
8ceee660 242
fa236e18 243 spent = efx_nic_process_eventq(channel, budget);
d9ab7007
BH		 244 if (spent && efx_channel_has_rx_queue(channel)) {
245 struct efx_rx_queue *rx_queue =
246 efx_channel_get_rx_queue(channel);
247
ff734ef4 248 efx_rx_flush_packet(channel);
d8aec745 249 efx_fast_push_rx_descriptors(rx_queue);
8ceee660
BH		 250 }
251
fa236e18 252 return spent;
8ceee660
BH		 253}
254
8ceee660
BH		 255/* NAPI poll handler
256 *
257 * NAPI guarantees serialisation of polls of the same device, which
258 * provides the guarantee required by efx_process_channel().
259 */
260static int efx_poll(struct napi_struct *napi, int budget)
261{
262 struct efx_channel *channel =
263 container_of(napi, struct efx_channel, napi_str);
62776d03 264 struct efx_nic *efx = channel->efx;
fa236e18 265 int spent;
8ceee660 266
62776d03
BH		 267 netif_vdbg(efx, intr, efx->net_dev,
268 "channel %d NAPI poll executing on CPU %d\n",
269 channel->channel, raw_smp_processor_id());
8ceee660 270
fa236e18 271 spent = efx_process_channel(channel, budget);
8ceee660 272
fa236e18 273 if (spent < budget) {
9d9a6973 274 if (efx_channel_has_rx_queue(channel) &&
6fb70fd1
BH		 275 efx->irq_rx_adaptive &&
276 unlikely(++channel->irq_count == 1000)) {
6fb70fd1
BH		 277 if (unlikely(channel->irq_mod_score <
278 irq_adapt_low_thresh)) {
0d86ebd8
BH		 279 if (channel->irq_moderation > 1) {
280 channel->irq_moderation -= 1;
ef2b90ee 281 efx->type->push_irq_moderation(channel);
0d86ebd8 282 }
6fb70fd1
BH		 283 } else if (unlikely(channel->irq_mod_score >
284 irq_adapt_high_thresh)) {
0d86ebd8
BH		 285 if (channel->irq_moderation <
286 efx->irq_rx_moderation) {
287 channel->irq_moderation += 1;
ef2b90ee 288 efx->type->push_irq_moderation(channel);
0d86ebd8 289 }
6fb70fd1 290 }
6fb70fd1
BH		 291 channel->irq_count = 0;
292 channel->irq_mod_score = 0;
293 }
294
64d8ad6d
BH		 295 efx_filter_rfs_expire(channel);
296
8ceee660 297 /* There is no race here; although napi_disable() will
288379f0 298 * only wait for napi_complete(), this isn't a problem
514bedbc 299 * since efx_nic_eventq_read_ack() will have no effect if
8ceee660
BH		 300 * interrupts have already been disabled.
301 */
288379f0 302 napi_complete(napi);
514bedbc 303 efx_nic_eventq_read_ack(channel);
8ceee660
BH		 304 }
305
fa236e18 306 return spent;
8ceee660
BH		 307}
308
8ceee660
BH		 309/* Create event queue
310 * Event queue memory allocations are done only once. If the channel
311 * is reset, the memory buffer will be reused; this guards against
312 * errors during channel reset and also simplifies interrupt handling.
313 */
314static int efx_probe_eventq(struct efx_channel *channel)
315{
ecc910f5
SH		 316 struct efx_nic *efx = channel->efx;
317 unsigned long entries;
318
86ee5302 319 netif_dbg(efx, probe, efx->net_dev,
62776d03 320 "chan %d create event queue\n", channel->channel);
8ceee660 321
ecc910f5
SH		 322 /* Build an event queue with room for one event per tx and rx buffer,
323 * plus some extra for link state events and MCDI completions. */
324 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
325 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
326 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
327
152b6a62 328 return efx_nic_probe_eventq(channel);
8ceee660
BH		 329}
330
331/* Prepare channel's event queue */
bc3c90a2 332static void efx_init_eventq(struct efx_channel *channel)
8ceee660 333{
62776d03
BH		 334 netif_dbg(channel->efx, drv, channel->efx->net_dev,
335 "chan %d init event queue\n", channel->channel);
8ceee660
BH		 336
337 channel->eventq_read_ptr = 0;
338
152b6a62 339 efx_nic_init_eventq(channel);
be3fc09c 340 channel->eventq_init = true;
8ceee660
BH		 341}
342
9f2cb71c
BH		 343/* Enable event queue processing and NAPI */
344static void efx_start_eventq(struct efx_channel *channel)
345{
346 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
347 "chan %d start event queue\n", channel->channel);
348
514bedbc 349 /* Make sure the NAPI handler sees the enabled flag set */
9f2cb71c
BH		 350 channel->enabled = true;
351 smp_wmb();
352
353 napi_enable(&channel->napi_str);
354 efx_nic_eventq_read_ack(channel);
355}
356
357/* Disable event queue processing and NAPI */
358static void efx_stop_eventq(struct efx_channel *channel)
359{
360 if (!channel->enabled)
361 return;
362
363 napi_disable(&channel->napi_str);
364 channel->enabled = false;
365}
366
8ceee660
BH		 367static void efx_fini_eventq(struct efx_channel *channel)
368{
be3fc09c
BH		 369 if (!channel->eventq_init)
370 return;
371
62776d03
BH		 372 netif_dbg(channel->efx, drv, channel->efx->net_dev,
373 "chan %d fini event queue\n", channel->channel);
8ceee660 374
152b6a62 375 efx_nic_fini_eventq(channel);
be3fc09c 376 channel->eventq_init = false;
8ceee660
BH		 377}
378
379static void efx_remove_eventq(struct efx_channel *channel)
380{
62776d03
BH		 381 netif_dbg(channel->efx, drv, channel->efx->net_dev,
382 "chan %d remove event queue\n", channel->channel);
8ceee660 383
152b6a62 384 efx_nic_remove_eventq(channel);
8ceee660
BH		 385}
386
387/**************************************************************************
388 *
389 * Channel handling
390 *
391 *************************************************************************/
392
7f967c01 393/* Allocate and initialise a channel structure. */
4642610c
BH		 394static struct efx_channel *
395efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
396{
397 struct efx_channel *channel;
398 struct efx_rx_queue *rx_queue;
399 struct efx_tx_queue *tx_queue;
400 int j;
401
7f967c01
BH		 402 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
403 if (!channel)
404 return NULL;
4642610c 405
7f967c01
BH		 406 channel->efx = efx;
407 channel->channel = i;
408 channel->type = &efx_default_channel_type;
4642610c 409
7f967c01
BH		 410 for (j = 0; j < EFX_TXQ_TYPES; j++) {
411 tx_queue = &channel->tx_queue[j];
412 tx_queue->efx = efx;
413 tx_queue->queue = i * EFX_TXQ_TYPES + j;
414 tx_queue->channel = channel;
415 }
4642610c 416
7f967c01
BH		 417 rx_queue = &channel->rx_queue;
418 rx_queue->efx = efx;
419 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
420 (unsigned long)rx_queue);
4642610c 421
7f967c01
BH		 422 return channel;
423}
424
425/* Allocate and initialise a channel structure, copying parameters
426 * (but not resources) from an old channel structure.
427 */
428static struct efx_channel *
429efx_copy_channel(const struct efx_channel *old_channel)
430{
431 struct efx_channel *channel;
432 struct efx_rx_queue *rx_queue;
433 struct efx_tx_queue *tx_queue;
434 int j;
4642610c 435
7f967c01
BH		 436 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
437 if (!channel)
438 return NULL;
439
440 *channel = *old_channel;
441
442 channel->napi_dev = NULL;
443 memset(&channel->eventq, 0, sizeof(channel->eventq));
4642610c 444
7f967c01
BH		 445 for (j = 0; j < EFX_TXQ_TYPES; j++) {
446 tx_queue = &channel->tx_queue[j];
447 if (tx_queue->channel)
4642610c 448 tx_queue->channel = channel;
7f967c01
BH		 449 tx_queue->buffer = NULL;
450 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
4642610c
BH		 451 }
452
4642610c 453 rx_queue = &channel->rx_queue;
7f967c01
BH		 454 rx_queue->buffer = NULL;
455 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
4642610c
BH		 456 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
457 (unsigned long)rx_queue);
458
459 return channel;
460}
461
8ceee660
BH		 462static int efx_probe_channel(struct efx_channel *channel)
463{
464 struct efx_tx_queue *tx_queue;
465 struct efx_rx_queue *rx_queue;
466 int rc;
467
62776d03
BH		 468 netif_dbg(channel->efx, probe, channel->efx->net_dev,
469 "creating channel %d\n", channel->channel);
8ceee660 470
7f967c01
BH		 471 rc = channel->type->pre_probe(channel);
472 if (rc)
473 goto fail;
474
8ceee660
BH		 475 rc = efx_probe_eventq(channel);
476 if (rc)
7f967c01 477 goto fail;
8ceee660
BH		 478
479 efx_for_each_channel_tx_queue(tx_queue, channel) {
480 rc = efx_probe_tx_queue(tx_queue);
481 if (rc)
7f967c01 482 goto fail;
8ceee660
BH		 483 }
484
485 efx_for_each_channel_rx_queue(rx_queue, channel) {
486 rc = efx_probe_rx_queue(rx_queue);
487 if (rc)
7f967c01 488 goto fail;
8ceee660
BH		 489 }
490
491 channel->n_rx_frm_trunc = 0;
492
493 return 0;
494
7f967c01
BH		 495fail:
496 efx_remove_channel(channel);
8ceee660
BH		 497 return rc;
498}
499
7f967c01
BH		 500static void
501efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
502{
503 struct efx_nic *efx = channel->efx;
504 const char *type;
505 int number;
506
507 number = channel->channel;
508 if (efx->tx_channel_offset == 0) {
509 type = "";
510 } else if (channel->channel < efx->tx_channel_offset) {
511 type = "-rx";
512 } else {
513 type = "-tx";
514 number -= efx->tx_channel_offset;
515 }
516 snprintf(buf, len, "%s%s-%d", efx->name, type, number);
517}
8ceee660 518
56536e9c
BH		 519static void efx_set_channel_names(struct efx_nic *efx)
520{
521 struct efx_channel *channel;
56536e9c 522
7f967c01
BH		 523 efx_for_each_channel(channel, efx)
524 channel->type->get_name(channel,
d8291187
BH		 525 efx->msi_context[channel->channel].name,
526 sizeof(efx->msi_context[0].name));
56536e9c
BH		 527}
528
4642610c
BH		 529static int efx_probe_channels(struct efx_nic *efx)
530{
531 struct efx_channel *channel;
532 int rc;
533
534 /* Restart special buffer allocation */
535 efx->next_buffer_table = 0;
536
c92aaff1
BH		 537 /* Probe channels in reverse, so that any 'extra' channels
538 * use the start of the buffer table. This allows the traffic
539 * channels to be resized without moving them or wasting the
540 * entries before them.
541 */
542 efx_for_each_channel_rev(channel, efx) {
4642610c
BH		 543 rc = efx_probe_channel(channel);
544 if (rc) {
545 netif_err(efx, probe, efx->net_dev,
546 "failed to create channel %d\n",
547 channel->channel);
548 goto fail;
549 }
550 }
551 efx_set_channel_names(efx);
552
553 return 0;
554
555fail:
556 efx_remove_channels(efx);
557 return rc;
558}
559
8ceee660
BH		 560/* Channels are shutdown and reinitialised whilst the NIC is running
561 * to propagate configuration changes (mtu, checksum offload), or
562 * to clear hardware error conditions
563 */
9f2cb71c 564static void efx_start_datapath(struct efx_nic *efx)
8ceee660 565{
85740cdf 566 bool old_rx_scatter = efx->rx_scatter;
8ceee660
BH		 567 struct efx_tx_queue *tx_queue;
568 struct efx_rx_queue *rx_queue;
569 struct efx_channel *channel;
85740cdf 570 size_t rx_buf_len;
8ceee660 571
f7f13b0b
BH		 572 /* Calculate the rx buffer allocation parameters required to
573 * support the current MTU, including padding for header
574 * alignment and overruns.
575 */
43a3739d 576 efx->rx_dma_len = (efx->rx_prefix_size +
272baeeb
BH		 577 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
578 efx->type->rx_buffer_padding);
85740cdf 579 rx_buf_len = (sizeof(struct efx_rx_page_state) +
c14ff2ea 580 NET_IP_ALIGN + efx->rx_dma_len);
85740cdf
BH		 581 if (rx_buf_len <= PAGE_SIZE) {
582 efx->rx_scatter = false;
583 efx->rx_buffer_order = 0;
85740cdf 584 } else if (efx->type->can_rx_scatter) {
950c54df 585 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
85740cdf 586 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
950c54df
BH		 587 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
588 EFX_RX_BUF_ALIGNMENT) >
589 PAGE_SIZE);
85740cdf
BH		 590 efx->rx_scatter = true;
591 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
592 efx->rx_buffer_order = 0;
85740cdf
BH		 593 } else {
594 efx->rx_scatter = false;
595 efx->rx_buffer_order = get_order(rx_buf_len);
85740cdf
BH		 596 }
597
1648a23f
DP		 598 efx_rx_config_page_split(efx);
599 if (efx->rx_buffer_order)
600 netif_dbg(efx, drv, efx->net_dev,
601 "RX buf len=%u; page order=%u batch=%u\n",
602 efx->rx_dma_len, efx->rx_buffer_order,
603 efx->rx_pages_per_batch);
604 else
605 netif_dbg(efx, drv, efx->net_dev,
606 "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
607 efx->rx_dma_len, efx->rx_page_buf_step,
608 efx->rx_bufs_per_page, efx->rx_pages_per_batch);
2768935a 609
85740cdf
BH		 610 /* RX filters also have scatter-enabled flags */
611 if (efx->rx_scatter != old_rx_scatter)
add72477 612 efx->type->filter_update_rx_scatter(efx);
8ceee660 613
14bf718f
BH		 614 /* We must keep at least one descriptor in a TX ring empty.
615 * We could avoid this when the queue size does not exactly
616 * match the hardware ring size, but it's not that important.
617 * Therefore we stop the queue when one more skb might fill
618 * the ring completely. We wake it when half way back to
619 * empty.
620 */
621 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
622 efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
623
8ceee660
BH		 624 /* Initialise the channels */
625 efx_for_each_channel(channel, efx) {
bc3c90a2
BH		 626 efx_for_each_channel_tx_queue(tx_queue, channel)
627 efx_init_tx_queue(tx_queue);
8ceee660 628
9f2cb71c 629 efx_for_each_channel_rx_queue(rx_queue, channel) {
bc3c90a2 630 efx_init_rx_queue(rx_queue);
9f2cb71c
BH		 631 efx_nic_generate_fill_event(rx_queue);
632 }
8ceee660 633
85740cdf 634 WARN_ON(channel->rx_pkt_n_frags);
8ceee660 635 }
8ceee660 636
9f2cb71c
BH		 637 if (netif_device_present(efx->net_dev))
638 netif_tx_wake_all_queues(efx->net_dev);
8ceee660
BH		 639}
640
9f2cb71c 641static void efx_stop_datapath(struct efx_nic *efx)
8ceee660
BH		 642{
643 struct efx_channel *channel;
644 struct efx_tx_queue *tx_queue;
645 struct efx_rx_queue *rx_queue;
6bc5d3a9 646 int rc;
8ceee660
BH		 647
648 EFX_ASSERT_RESET_SERIALISED(efx);
649 BUG_ON(efx->port_enabled);
650
d8aec745
BH		 651 /* Stop RX refill */
652 efx_for_each_channel(channel, efx) {
653 efx_for_each_channel_rx_queue(rx_queue, channel)
654 rx_queue->refill_enabled = false;
655 }
656
8ceee660 657 efx_for_each_channel(channel, efx) {
9f2cb71c
BH		 658 /* RX packet processing is pipelined, so wait for the
659 * NAPI handler to complete. At least event queue 0
660 * might be kept active by non-data events, so don't
661 * use napi_synchronize() but actually disable NAPI
662 * temporarily.
663 */
664 if (efx_channel_has_rx_queue(channel)) {
665 efx_stop_eventq(channel);
666 efx_start_eventq(channel);
667 }
e42c3d85 668 }
8ceee660 669
e42c3d85
BH		 670 rc = efx->type->fini_dmaq(efx);
671 if (rc && EFX_WORKAROUND_7803(efx)) {
672 /* Schedule a reset to recover from the flush failure. The
673 * descriptor caches reference memory we're about to free,
674 * but falcon_reconfigure_mac_wrapper() won't reconnect
675 * the MACs because of the pending reset.
676 */
677 netif_err(efx, drv, efx->net_dev,
678 "Resetting to recover from flush failure\n");
679 efx_schedule_reset(efx, RESET_TYPE_ALL);
680 } else if (rc) {
681 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
682 } else {
683 netif_dbg(efx, drv, efx->net_dev,
684 "successfully flushed all queues\n");
685 }
686
687 efx_for_each_channel(channel, efx) {
8ceee660
BH		 688 efx_for_each_channel_rx_queue(rx_queue, channel)
689 efx_fini_rx_queue(rx_queue);
94b274bf 690 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660 691 efx_fini_tx_queue(tx_queue);
8ceee660
BH		 692 }
693}
694
695static void efx_remove_channel(struct efx_channel *channel)
696{
697 struct efx_tx_queue *tx_queue;
698 struct efx_rx_queue *rx_queue;
699
62776d03
BH		 700 netif_dbg(channel->efx, drv, channel->efx->net_dev,
701 "destroy chan %d\n", channel->channel);
8ceee660
BH		 702
703 efx_for_each_channel_rx_queue(rx_queue, channel)
704 efx_remove_rx_queue(rx_queue);
94b274bf 705 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660
BH		 706 efx_remove_tx_queue(tx_queue);
707 efx_remove_eventq(channel);
c31e5f9f 708 channel->type->post_remove(channel);
8ceee660
BH		 709}
710
4642610c
BH		 711static void efx_remove_channels(struct efx_nic *efx)
712{
713 struct efx_channel *channel;
714
715 efx_for_each_channel(channel, efx)
716 efx_remove_channel(channel);
717}
718
719int
720efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
721{
722 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
723 u32 old_rxq_entries, old_txq_entries;
7f967c01 724 unsigned i, next_buffer_table = 0;
8b7325b4
BH		 725 int rc;
726
727 rc = efx_check_disabled(efx);
728 if (rc)
729 return rc;
7f967c01
BH		 730
731 /* Not all channels should be reallocated. We must avoid
732 * reallocating their buffer table entries.
733 */
734 efx_for_each_channel(channel, efx) {
735 struct efx_rx_queue *rx_queue;
736 struct efx_tx_queue *tx_queue;
737
738 if (channel->type->copy)
739 continue;
740 next_buffer_table = max(next_buffer_table,
741 channel->eventq.index +
742 channel->eventq.entries);
743 efx_for_each_channel_rx_queue(rx_queue, channel)
744 next_buffer_table = max(next_buffer_table,
745 rx_queue->rxd.index +
746 rx_queue->rxd.entries);
747 efx_for_each_channel_tx_queue(tx_queue, channel)
748 next_buffer_table = max(next_buffer_table,
749 tx_queue->txd.index +
750 tx_queue->txd.entries);
751 }
4642610c 752
29c69a48 753 efx_device_detach_sync(efx);
4642610c 754 efx_stop_all(efx);
d8291187 755 efx_soft_disable_interrupts(efx);
4642610c 756
7f967c01 757 /* Clone channels (where possible) */
4642610c
BH		 758 memset(other_channel, 0, sizeof(other_channel));
759 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 760 channel = efx->channel[i];
761 if (channel->type->copy)
762 channel = channel->type->copy(channel);
4642610c
BH		 763 if (!channel) {
764 rc = -ENOMEM;
765 goto out;
766 }
767 other_channel[i] = channel;
768 }
769
770 /* Swap entry counts and channel pointers */
771 old_rxq_entries = efx->rxq_entries;
772 old_txq_entries = efx->txq_entries;
773 efx->rxq_entries = rxq_entries;
774 efx->txq_entries = txq_entries;
775 for (i = 0; i < efx->n_channels; i++) {
776 channel = efx->channel[i];
777 efx->channel[i] = other_channel[i];
778 other_channel[i] = channel;
779 }
780
7f967c01
BH		 781 /* Restart buffer table allocation */
782 efx->next_buffer_table = next_buffer_table;
e8f14992 783
e8f14992 784 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 785 channel = efx->channel[i];
786 if (!channel->type->copy)
787 continue;
788 rc = efx_probe_channel(channel);
789 if (rc)
790 goto rollback;
791 efx_init_napi_channel(efx->channel[i]);
e8f14992 792 }
7f967c01 793
4642610c 794out:
7f967c01
BH		 795 /* Destroy unused channel structures */
796 for (i = 0; i < efx->n_channels; i++) {
797 channel = other_channel[i];
798 if (channel && channel->type->copy) {
799 efx_fini_napi_channel(channel);
800 efx_remove_channel(channel);
801 kfree(channel);
802 }
803 }
4642610c 804
d8291187 805 efx_soft_enable_interrupts(efx);
4642610c 806 efx_start_all(efx);
29c69a48 807 netif_device_attach(efx->net_dev);
4642610c
BH		 808 return rc;
809
810rollback:
811 /* Swap back */
812 efx->rxq_entries = old_rxq_entries;
813 efx->txq_entries = old_txq_entries;
814 for (i = 0; i < efx->n_channels; i++) {
815 channel = efx->channel[i];
816 efx->channel[i] = other_channel[i];
817 other_channel[i] = channel;
818 }
819 goto out;
820}
821
90d683af 822void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
8ceee660 823{
90d683af 824 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
8ceee660
BH		 825}
826
7f967c01
BH		 827static const struct efx_channel_type efx_default_channel_type = {
828 .pre_probe = efx_channel_dummy_op_int,
c31e5f9f 829 .post_remove = efx_channel_dummy_op_void,
7f967c01
BH		 830 .get_name = efx_get_channel_name,
831 .copy = efx_copy_channel,
832 .keep_eventq = false,
833};
834
835int efx_channel_dummy_op_int(struct efx_channel *channel)
836{
837 return 0;
838}
839
c31e5f9f
SH		 840void efx_channel_dummy_op_void(struct efx_channel *channel)
841{
842}
843
8ceee660
BH		 844/**************************************************************************
845 *
846 * Port handling
847 *
848 **************************************************************************/
849
850/* This ensures that the kernel is kept informed (via
851 * netif_carrier_on/off) of the link status, and also maintains the
852 * link status's stop on the port's TX queue.
853 */
fdaa9aed 854void efx_link_status_changed(struct efx_nic *efx)
8ceee660 855{
eb50c0d6
BH		 856 struct efx_link_state *link_state = &efx->link_state;
857
8ceee660
BH		 858 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
859 * that no events are triggered between unregister_netdev() and the
860 * driver unloading. A more general condition is that NETDEV_CHANGE
861 * can only be generated between NETDEV_UP and NETDEV_DOWN */
862 if (!netif_running(efx->net_dev))
863 return;
864
eb50c0d6 865 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
8ceee660
BH		 866 efx->n_link_state_changes++;
867
eb50c0d6 868 if (link_state->up)
8ceee660
BH		 869 netif_carrier_on(efx->net_dev);
870 else
871 netif_carrier_off(efx->net_dev);
872 }
873
874 /* Status message for kernel log */
2aa9ef11 875 if (link_state->up)
62776d03 876 netif_info(efx, link, efx->net_dev,
964e6135 877 "link up at %uMbps %s-duplex (MTU %d)\n",
62776d03 878 link_state->speed, link_state->fd ? "full" : "half",
964e6135 879 efx->net_dev->mtu);
2aa9ef11 880 else
62776d03 881 netif_info(efx, link, efx->net_dev, "link down\n");
8ceee660
BH		 882}
883
d3245b28
BH		 884void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
885{
886 efx->link_advertising = advertising;
887 if (advertising) {
888 if (advertising & ADVERTISED_Pause)
889 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
890 else
891 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
892 if (advertising & ADVERTISED_Asym_Pause)
893 efx->wanted_fc ^= EFX_FC_TX;
894 }
895}
896
b5626946 897void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
d3245b28
BH		 898{
899 efx->wanted_fc = wanted_fc;
900 if (efx->link_advertising) {
901 if (wanted_fc & EFX_FC_RX)
902 efx->link_advertising |= (ADVERTISED_Pause |
903 ADVERTISED_Asym_Pause);
904 else
905 efx->link_advertising &= ~(ADVERTISED_Pause |
906 ADVERTISED_Asym_Pause);
907 if (wanted_fc & EFX_FC_TX)
908 efx->link_advertising ^= ADVERTISED_Asym_Pause;
909 }
910}
911
115122af
BH		 912static void efx_fini_port(struct efx_nic *efx);
913
d3245b28
BH		 914/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
915 * the MAC appropriately. All other PHY configuration changes are pushed
916 * through phy_op->set_settings(), and pushed asynchronously to the MAC
917 * through efx_monitor().
918 *
919 * Callers must hold the mac_lock
920 */
921int __efx_reconfigure_port(struct efx_nic *efx)
8ceee660 922{
d3245b28
BH		 923 enum efx_phy_mode phy_mode;
924 int rc;
8ceee660 925
d3245b28 926 WARN_ON(!mutex_is_locked(&efx->mac_lock));
8ceee660 927
d3245b28
BH		 928 /* Disable PHY transmit in mac level loopbacks */
929 phy_mode = efx->phy_mode;
177dfcd8
BH		 930 if (LOOPBACK_INTERNAL(efx))
931 efx->phy_mode |= PHY_MODE_TX_DISABLED;
932 else
933 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
177dfcd8 934
d3245b28 935 rc = efx->type->reconfigure_port(efx);
8ceee660 936
d3245b28
BH		 937 if (rc)
938 efx->phy_mode = phy_mode;
177dfcd8 939
d3245b28 940 return rc;
8ceee660
BH		 941}
942
943/* Reinitialise the MAC to pick up new PHY settings, even if the port is
944 * disabled. */
d3245b28 945int efx_reconfigure_port(struct efx_nic *efx)
8ceee660 946{
d3245b28
BH		 947 int rc;
948
8ceee660
BH		 949 EFX_ASSERT_RESET_SERIALISED(efx);
950
951 mutex_lock(&efx->mac_lock);
d3245b28 952 rc = __efx_reconfigure_port(efx);
8ceee660 953 mutex_unlock(&efx->mac_lock);
d3245b28
BH		 954
955 return rc;
8ceee660
BH		 956}
957
8be4f3e6
BH		 958/* Asynchronous work item for changing MAC promiscuity and multicast
959 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
960 * MAC directly. */
766ca0fa
BH		 961static void efx_mac_work(struct work_struct *data)
962{
963 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
964
965 mutex_lock(&efx->mac_lock);
30b81cda 966 if (efx->port_enabled)
710b208d 967 efx->type->reconfigure_mac(efx);
766ca0fa
BH		 968 mutex_unlock(&efx->mac_lock);
969}
970
8ceee660
BH		 971static int efx_probe_port(struct efx_nic *efx)
972{
973 int rc;
974
62776d03 975 netif_dbg(efx, probe, efx->net_dev, "create port\n");
8ceee660 976
ff3b00a0
SH		 977 if (phy_flash_cfg)
978 efx->phy_mode = PHY_MODE_SPECIAL;
979
ef2b90ee
BH		 980 /* Connect up MAC/PHY operations table */
981 rc = efx->type->probe_port(efx);
8ceee660 982 if (rc)
e42de262 983 return rc;
8ceee660 984
e332bcb3
BH		 985 /* Initialise MAC address to permanent address */
986 memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN);
8ceee660
BH		 987
988 return 0;
8ceee660
BH		 989}
990
991static int efx_init_port(struct efx_nic *efx)
992{
993 int rc;
994
62776d03 995 netif_dbg(efx, drv, efx->net_dev, "init port\n");
8ceee660 996
1dfc5cea
BH		 997 mutex_lock(&efx->mac_lock);
998
177dfcd8 999 rc = efx->phy_op->init(efx);
8ceee660 1000 if (rc)
1dfc5cea 1001 goto fail1;
8ceee660 1002
dc8cfa55 1003 efx->port_initialized = true;
1dfc5cea 1004
d3245b28
BH		 1005 /* Reconfigure the MAC before creating dma queues (required for
1006 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
710b208d 1007 efx->type->reconfigure_mac(efx);
d3245b28
BH		 1008
1009 /* Ensure the PHY advertises the correct flow control settings */
1010 rc = efx->phy_op->reconfigure(efx);
1011 if (rc)
1012 goto fail2;
1013
1dfc5cea 1014 mutex_unlock(&efx->mac_lock);
8ceee660 1015 return 0;
177dfcd8 1016
1dfc5cea 1017fail2:
177dfcd8 1018 efx->phy_op->fini(efx);
1dfc5cea
BH		 1019fail1:
1020 mutex_unlock(&efx->mac_lock);
177dfcd8 1021 return rc;
8ceee660
BH		 1022}
1023
8ceee660
BH		 1024static void efx_start_port(struct efx_nic *efx)
1025{
62776d03 1026 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
8ceee660
BH		 1027 BUG_ON(efx->port_enabled);
1028
1029 mutex_lock(&efx->mac_lock);
dc8cfa55 1030 efx->port_enabled = true;
8be4f3e6
BH		 1031
1032 /* efx_mac_work() might have been scheduled after efx_stop_port(),
1033 * and then cancelled by efx_flush_all() */
710b208d 1034 efx->type->reconfigure_mac(efx);
8be4f3e6 1035
8ceee660
BH		 1036 mutex_unlock(&efx->mac_lock);
1037}
1038
fdaa9aed 1039/* Prevent efx_mac_work() and efx_monitor() from working */
8ceee660
BH		 1040static void efx_stop_port(struct efx_nic *efx)
1041{
62776d03 1042 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
8ceee660
BH		 1043
1044 mutex_lock(&efx->mac_lock);
dc8cfa55 1045 efx->port_enabled = false;
8ceee660
BH		 1046 mutex_unlock(&efx->mac_lock);
1047
1048 /* Serialise against efx_set_multicast_list() */
73ba7b68
BH		 1049 netif_addr_lock_bh(efx->net_dev);
1050 netif_addr_unlock_bh(efx->net_dev);
8ceee660
BH		 1051}
1052
1053static void efx_fini_port(struct efx_nic *efx)
1054{
62776d03 1055 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
8ceee660
BH		 1056
1057 if (!efx->port_initialized)
1058 return;
1059
177dfcd8 1060 efx->phy_op->fini(efx);
dc8cfa55 1061 efx->port_initialized = false;
8ceee660 1062
eb50c0d6 1063 efx->link_state.up = false;
8ceee660
BH		 1064 efx_link_status_changed(efx);
1065}
1066
1067static void efx_remove_port(struct efx_nic *efx)
1068{
62776d03 1069 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
8ceee660 1070
ef2b90ee 1071 efx->type->remove_port(efx);
8ceee660
BH		 1072}
1073
1074/**************************************************************************
1075 *
1076 * NIC handling
1077 *
1078 **************************************************************************/
1079
1080/* This configures the PCI device to enable I/O and DMA. */
1081static int efx_init_io(struct efx_nic *efx)
1082{
1083 struct pci_dev *pci_dev = efx->pci_dev;
1084 dma_addr_t dma_mask = efx->type->max_dma_mask;
b105798f 1085 unsigned int mem_map_size = efx->type->mem_map_size(efx);
8ceee660
BH		 1086 int rc;
1087
62776d03 1088 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
8ceee660
BH		 1089
1090 rc = pci_enable_device(pci_dev);
1091 if (rc) {
62776d03
BH		 1092 netif_err(efx, probe, efx->net_dev,
1093 "failed to enable PCI device\n");
8ceee660
BH		 1094 goto fail1;
1095 }
1096
1097 pci_set_master(pci_dev);
1098
1099 /* Set the PCI DMA mask. Try all possibilities from our
1100 * genuine mask down to 32 bits, because some architectures
1101 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1102 * masks event though they reject 46 bit masks.
1103 */
1104 while (dma_mask > 0x7fffffffUL) {
0e33d870
BH		 1105 if (dma_supported(&pci_dev->dev, dma_mask)) {
1106 rc = dma_set_mask(&pci_dev->dev, dma_mask);
e9e01846
BH		 1107 if (rc == 0)
1108 break;
1109 }
8ceee660
BH		 1110 dma_mask >>= 1;
1111 }
1112 if (rc) {
62776d03
BH		 1113 netif_err(efx, probe, efx->net_dev,
1114 "could not find a suitable DMA mask\n");
8ceee660
BH		 1115 goto fail2;
1116 }
62776d03
BH		 1117 netif_dbg(efx, probe, efx->net_dev,
1118 "using DMA mask %llx\n", (unsigned long long) dma_mask);
0e33d870 1119 rc = dma_set_coherent_mask(&pci_dev->dev, dma_mask);
8ceee660 1120 if (rc) {
0e33d870
BH		 1121 /* dma_set_coherent_mask() is not *allowed* to
1122 * fail with a mask that dma_set_mask() accepted,
8ceee660
BH		 1123 * but just in case...
1124 */
62776d03
BH		 1125 netif_err(efx, probe, efx->net_dev,
1126 "failed to set consistent DMA mask\n");
8ceee660
BH		 1127 goto fail2;
1128 }
1129
dc803df8
BH		 1130 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
1131 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
8ceee660 1132 if (rc) {
62776d03
BH		 1133 netif_err(efx, probe, efx->net_dev,
1134 "request for memory BAR failed\n");
8ceee660
BH		 1135 rc = -EIO;
1136 goto fail3;
1137 }
b105798f 1138 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size);
8ceee660 1139 if (!efx->membase) {
62776d03
BH		 1140 netif_err(efx, probe, efx->net_dev,
1141 "could not map memory BAR at %llx+%x\n",
b105798f 1142 (unsigned long long)efx->membase_phys, mem_map_size);
8ceee660
BH		 1143 rc = -ENOMEM;
1144 goto fail4;
1145 }
62776d03
BH		 1146 netif_dbg(efx, probe, efx->net_dev,
1147 "memory BAR at %llx+%x (virtual %p)\n",
b105798f
BH		 1148 (unsigned long long)efx->membase_phys, mem_map_size,
1149 efx->membase);
8ceee660
BH		 1150
1151 return 0;
1152
1153 fail4:
dc803df8 1154 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
8ceee660 1155 fail3:
2c118e0f 1156 efx->membase_phys = 0;
8ceee660
BH		 1157 fail2:
1158 pci_disable_device(efx->pci_dev);
1159 fail1:
1160 return rc;
1161}
1162
1163static void efx_fini_io(struct efx_nic *efx)
1164{
62776d03 1165 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
8ceee660
BH		 1166
1167 if (efx->membase) {
1168 iounmap(efx->membase);
1169 efx->membase = NULL;
1170 }
1171
1172 if (efx->membase_phys) {
dc803df8 1173 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
2c118e0f 1174 efx->membase_phys = 0;
8ceee660
BH		 1175 }
1176
1177 pci_disable_device(efx->pci_dev);
1178}
1179
a9a52506 1180static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
46123d04 1181{
cdb08f8f 1182 cpumask_var_t thread_mask;
a16e5b24 1183 unsigned int count;
46123d04 1184 int cpu;
5b874e25 1185
cd2d5b52
BH		 1186 if (rss_cpus) {
1187 count = rss_cpus;
1188 } else {
1189 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
1190 netif_warn(efx, probe, efx->net_dev,
1191 "RSS disabled due to allocation failure\n");
1192 return 1;
1193 }
46123d04 1194
cd2d5b52
BH		 1195 count = 0;
1196 for_each_online_cpu(cpu) {
1197 if (!cpumask_test_cpu(cpu, thread_mask)) {
1198 ++count;
1199 cpumask_or(thread_mask, thread_mask,
1200 topology_thread_cpumask(cpu));
1201 }
1202 }
1203
1204 free_cpumask_var(thread_mask);
2f8975fb
RR		 1205 }
1206
cd2d5b52
BH		 1207 /* If RSS is requested for the PF *and* VFs then we can't write RSS
1208 * table entries that are inaccessible to VFs
1209 */
1210 if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
1211 count > efx_vf_size(efx)) {
1212 netif_warn(efx, probe, efx->net_dev,
1213 "Reducing number of RSS channels from %u to %u for "
1214 "VF support. Increase vf-msix-limit to use more "
1215 "channels on the PF.\n",
1216 count, efx_vf_size(efx));
1217 count = efx_vf_size(efx);
46123d04
BH		 1218 }
1219
1220 return count;
1221}
1222
1223/* Probe the number and type of interrupts we are able to obtain, and
1224 * the resulting numbers of channels and RX queues.
1225 */
64d8ad6d 1226static int efx_probe_interrupts(struct efx_nic *efx)
8ceee660 1227{
7f967c01
BH		 1228 unsigned int extra_channels = 0;
1229 unsigned int i, j;
a16e5b24 1230 int rc;
8ceee660 1231
7f967c01
BH		 1232 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
1233 if (efx->extra_channel_type[i])
1234 ++extra_channels;
1235
8ceee660 1236 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
46123d04 1237 struct msix_entry xentries[EFX_MAX_CHANNELS];
a16e5b24 1238 unsigned int n_channels;
aa6ef27e 1239
a9a52506 1240 n_channels = efx_wanted_parallelism(efx);
a4900ac9
BH		 1241 if (separate_tx_channels)
1242 n_channels *= 2;
7f967c01 1243 n_channels += extra_channels;
b105798f 1244 n_channels = min(n_channels, efx->max_channels);
8ceee660 1245
a4900ac9 1246 for (i = 0; i < n_channels; i++)
8ceee660 1247 xentries[i].entry = i;
a4900ac9 1248 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels);
8ceee660 1249 if (rc > 0) {
62776d03
BH		 1250 netif_err(efx, drv, efx->net_dev,
1251 "WARNING: Insufficient MSI-X vectors"
a16e5b24 1252 " available (%d < %u).\n", rc, n_channels);
62776d03
BH		 1253 netif_err(efx, drv, efx->net_dev,
1254 "WARNING: Performance may be reduced.\n");
a4900ac9
BH		 1255 EFX_BUG_ON_PARANOID(rc >= n_channels);
1256 n_channels = rc;
8ceee660 1257 rc = pci_enable_msix(efx->pci_dev, xentries,
a4900ac9 1258 n_channels);
8ceee660
BH		 1259 }
1260
1261 if (rc == 0) {
a4900ac9 1262 efx->n_channels = n_channels;
7f967c01
BH		 1263 if (n_channels > extra_channels)
1264 n_channels -= extra_channels;
a4900ac9 1265 if (separate_tx_channels) {
7f967c01
BH		 1266 efx->n_tx_channels = max(n_channels / 2, 1U);
1267 efx->n_rx_channels = max(n_channels -
1268 efx->n_tx_channels,
1269 1U);
a4900ac9 1270 } else {
7f967c01
BH		 1271 efx->n_tx_channels = n_channels;
1272 efx->n_rx_channels = n_channels;
a4900ac9 1273 }
7f967c01 1274 for (i = 0; i < efx->n_channels; i++)
f7d12cdc
BH		 1275 efx_get_channel(efx, i)->irq =
1276 xentries[i].vector;
8ceee660
BH		 1277 } else {
1278 /* Fall back to single channel MSI */
1279 efx->interrupt_mode = EFX_INT_MODE_MSI;
62776d03
BH		 1280 netif_err(efx, drv, efx->net_dev,
1281 "could not enable MSI-X\n");
8ceee660
BH		 1282 }
1283 }
1284
1285 /* Try single interrupt MSI */
1286 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
28b581ab 1287 efx->n_channels = 1;
a4900ac9
BH		 1288 efx->n_rx_channels = 1;
1289 efx->n_tx_channels = 1;
8ceee660
BH		 1290 rc = pci_enable_msi(efx->pci_dev);
1291 if (rc == 0) {
f7d12cdc 1292 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
8ceee660 1293 } else {
62776d03
BH		 1294 netif_err(efx, drv, efx->net_dev,
1295 "could not enable MSI\n");
8ceee660
BH		 1296 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1297 }
1298 }
1299
1300 /* Assume legacy interrupts */
1301 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
28b581ab 1302 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
a4900ac9
BH		 1303 efx->n_rx_channels = 1;
1304 efx->n_tx_channels = 1;
8ceee660
BH		 1305 efx->legacy_irq = efx->pci_dev->irq;
1306 }
64d8ad6d 1307
7f967c01
BH		 1308 /* Assign extra channels if possible */
1309 j = efx->n_channels;
1310 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
1311 if (!efx->extra_channel_type[i])
1312 continue;
1313 if (efx->interrupt_mode != EFX_INT_MODE_MSIX ||
1314 efx->n_channels <= extra_channels) {
1315 efx->extra_channel_type[i]->handle_no_channel(efx);
1316 } else {
1317 --j;
1318 efx_get_channel(efx, j)->type =
1319 efx->extra_channel_type[i];
1320 }
1321 }
1322
cd2d5b52 1323 /* RSS might be usable on VFs even if it is disabled on the PF */
3132d282 1324 efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ?
cd2d5b52
BH		 1325 efx->n_rx_channels : efx_vf_size(efx));
1326
64d8ad6d 1327 return 0;
8ceee660
BH		 1328}
1329
d8291187 1330static void efx_soft_enable_interrupts(struct efx_nic *efx)
9f2cb71c
BH		 1331{
1332 struct efx_channel *channel;
1333
8b7325b4
BH		 1334 BUG_ON(efx->state == STATE_DISABLED);
1335
d8291187
BH		 1336 efx->irq_soft_enabled = true;
1337 smp_wmb();
9f2cb71c
BH		 1338
1339 efx_for_each_channel(channel, efx) {
d8291187 1340 if (!channel->type->keep_eventq)
7f967c01 1341 efx_init_eventq(channel);
9f2cb71c
BH		 1342 efx_start_eventq(channel);
1343 }
1344
1345 efx_mcdi_mode_event(efx);
1346}
1347
d8291187 1348static void efx_soft_disable_interrupts(struct efx_nic *efx)
9f2cb71c
BH		 1349{
1350 struct efx_channel *channel;
1351
8b7325b4
BH		 1352 if (efx->state == STATE_DISABLED)
1353 return;
1354
9f2cb71c
BH		 1355 efx_mcdi_mode_poll(efx);
1356
d8291187
BH		 1357 efx->irq_soft_enabled = false;
1358 smp_wmb();
1359
1360 if (efx->legacy_irq)
9f2cb71c 1361 synchronize_irq(efx->legacy_irq);
9f2cb71c
BH		 1362
1363 efx_for_each_channel(channel, efx) {
1364 if (channel->irq)
1365 synchronize_irq(channel->irq);
1366
1367 efx_stop_eventq(channel);
d8291187 1368 if (!channel->type->keep_eventq)
7f967c01 1369 efx_fini_eventq(channel);
9f2cb71c 1370 }
cade715f
BH		 1371
1372 /* Flush the asynchronous MCDI request queue */
1373 efx_mcdi_flush_async(efx);
9f2cb71c
BH		 1374}
1375
d8291187
BH		 1376static void efx_enable_interrupts(struct efx_nic *efx)
1377{
1378 struct efx_channel *channel;
1379
1380 BUG_ON(efx->state == STATE_DISABLED);
1381
1382 if (efx->eeh_disabled_legacy_irq) {
1383 enable_irq(efx->legacy_irq);
1384 efx->eeh_disabled_legacy_irq = false;
1385 }
1386
86094f7f 1387 efx->type->irq_enable_master(efx);
d8291187
BH		 1388
1389 efx_for_each_channel(channel, efx) {
1390 if (channel->type->keep_eventq)
1391 efx_init_eventq(channel);
1392 }
1393
1394 efx_soft_enable_interrupts(efx);
1395}
1396
1397static void efx_disable_interrupts(struct efx_nic *efx)
1398{
1399 struct efx_channel *channel;
1400
1401 efx_soft_disable_interrupts(efx);
1402
1403 efx_for_each_channel(channel, efx) {
1404 if (channel->type->keep_eventq)
1405 efx_fini_eventq(channel);
1406 }
1407
86094f7f 1408 efx->type->irq_disable_non_ev(efx);
d8291187
BH		 1409}
1410
8ceee660
BH		 1411static void efx_remove_interrupts(struct efx_nic *efx)
1412{
1413 struct efx_channel *channel;
1414
1415 /* Remove MSI/MSI-X interrupts */
64ee3120 1416 efx_for_each_channel(channel, efx)
8ceee660
BH		 1417 channel->irq = 0;
1418 pci_disable_msi(efx->pci_dev);
1419 pci_disable_msix(efx->pci_dev);
1420
1421 /* Remove legacy interrupt */
1422 efx->legacy_irq = 0;
1423}
1424
8831da7b 1425static void efx_set_channels(struct efx_nic *efx)
8ceee660 1426{
602a5322
BH		 1427 struct efx_channel *channel;
1428 struct efx_tx_queue *tx_queue;
1429
97653431 1430 efx->tx_channel_offset =
a4900ac9 1431 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0;
602a5322 1432
79d68b37
SH		 1433 /* We need to mark which channels really have RX and TX
1434 * queues, and adjust the TX queue numbers if we have separate
602a5322
BH		 1435 * RX-only and TX-only channels.
1436 */
1437 efx_for_each_channel(channel, efx) {
79d68b37
SH		 1438 if (channel->channel < efx->n_rx_channels)
1439 channel->rx_queue.core_index = channel->channel;
1440 else
1441 channel->rx_queue.core_index = -1;
1442
602a5322
BH		 1443 efx_for_each_channel_tx_queue(tx_queue, channel)
1444 tx_queue->queue -= (efx->tx_channel_offset *
1445 EFX_TXQ_TYPES);
1446 }
8ceee660
BH		 1447}
1448
1449static int efx_probe_nic(struct efx_nic *efx)
1450{
765c9f46 1451 size_t i;
8ceee660
BH		 1452 int rc;
1453
62776d03 1454 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
8ceee660
BH		 1455
1456 /* Carry out hardware-type specific initialisation */
ef2b90ee 1457 rc = efx->type->probe(efx);
8ceee660
BH		 1458 if (rc)
1459 return rc;
1460
a4900ac9 1461 /* Determine the number of channels and queues by trying to hook
8ceee660 1462 * in MSI-X interrupts. */
64d8ad6d
BH		 1463 rc = efx_probe_interrupts(efx);
1464 if (rc)
1465 goto fail;
8ceee660 1466
28e47c49
BH		 1467 efx->type->dimension_resources(efx);
1468
5d3a6fca
BH		 1469 if (efx->n_channels > 1)
1470 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
765c9f46 1471 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
278bc429 1472 efx->rx_indir_table[i] =
cd2d5b52 1473 ethtool_rxfh_indir_default(i, efx->rss_spread);
5d3a6fca 1474
8831da7b 1475 efx_set_channels(efx);
c4f4adc7
BH		 1476 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1477 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
8ceee660
BH		 1478
1479 /* Initialise the interrupt moderation settings */
9e393b30
BH		 1480 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
1481 true);
8ceee660
BH		 1482
1483 return 0;
64d8ad6d
BH		 1484
1485fail:
1486 efx->type->remove(efx);
1487 return rc;
8ceee660
BH		 1488}
1489
1490static void efx_remove_nic(struct efx_nic *efx)
1491{
62776d03 1492 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
8ceee660
BH		 1493
1494 efx_remove_interrupts(efx);
ef2b90ee 1495 efx->type->remove(efx);
8ceee660
BH		 1496}
1497
add72477
BH		 1498static int efx_probe_filters(struct efx_nic *efx)
1499{
1500 int rc;
1501
1502 spin_lock_init(&efx->filter_lock);
1503
1504 rc = efx->type->filter_table_probe(efx);
1505 if (rc)
1506 return rc;
1507
1508#ifdef CONFIG_RFS_ACCEL
1509 if (efx->type->offload_features & NETIF_F_NTUPLE) {
1510 efx->rps_flow_id = kcalloc(efx->type->max_rx_ip_filters,
1511 sizeof(*efx->rps_flow_id),
1512 GFP_KERNEL);
1513 if (!efx->rps_flow_id) {
1514 efx->type->filter_table_remove(efx);
1515 return -ENOMEM;
1516 }
1517 }
1518#endif
1519
1520 return 0;
1521}
1522
1523static void efx_remove_filters(struct efx_nic *efx)
1524{
1525#ifdef CONFIG_RFS_ACCEL
1526 kfree(efx->rps_flow_id);
1527#endif
1528 efx->type->filter_table_remove(efx);
1529}
1530
1531static void efx_restore_filters(struct efx_nic *efx)
1532{
1533 efx->type->filter_table_restore(efx);
1534}
1535
8ceee660
BH		 1536/**************************************************************************
1537 *
1538 * NIC startup/shutdown
1539 *
1540 *************************************************************************/
1541
1542static int efx_probe_all(struct efx_nic *efx)
1543{
8ceee660
BH		 1544 int rc;
1545
8ceee660
BH		 1546 rc = efx_probe_nic(efx);
1547 if (rc) {
62776d03 1548 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
8ceee660
BH		 1549 goto fail1;
1550 }
1551
8ceee660
BH		 1552 rc = efx_probe_port(efx);
1553 if (rc) {
62776d03 1554 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
8ceee660
BH		 1555 goto fail2;
1556 }
1557
7e6d06f0
BH		 1558 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
1559 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
1560 rc = -EINVAL;
1561 goto fail3;
1562 }
ecc910f5 1563 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
8ceee660 1564
64eebcfd
BH		 1565 rc = efx_probe_filters(efx);
1566 if (rc) {
1567 netif_err(efx, probe, efx->net_dev,
1568 "failed to create filter tables\n");
7f967c01 1569 goto fail3;
64eebcfd
BH		 1570 }
1571
7f967c01
BH		 1572 rc = efx_probe_channels(efx);
1573 if (rc)
1574 goto fail4;
1575
8ceee660
BH		 1576 return 0;
1577
64eebcfd 1578 fail4:
7f967c01 1579 efx_remove_filters(efx);
8ceee660 1580 fail3:
8ceee660
BH		 1581 efx_remove_port(efx);
1582 fail2:
1583 efx_remove_nic(efx);
1584 fail1:
1585 return rc;
1586}
1587
8b7325b4
BH		 1588/* If the interface is supposed to be running but is not, start
1589 * the hardware and software data path, regular activity for the port
1590 * (MAC statistics, link polling, etc.) and schedule the port to be
1591 * reconfigured. Interrupts must already be enabled. This function
1592 * is safe to call multiple times, so long as the NIC is not disabled.
1593 * Requires the RTNL lock.
9f2cb71c 1594 */
8ceee660
BH		 1595static void efx_start_all(struct efx_nic *efx)
1596{
8ceee660 1597 EFX_ASSERT_RESET_SERIALISED(efx);
8b7325b4 1598 BUG_ON(efx->state == STATE_DISABLED);
8ceee660
BH		 1599
1600 /* Check that it is appropriate to restart the interface. All
1601 * of these flags are safe to read under just the rtnl lock */
8b7325b4 1602 if (efx->port_enabled || !netif_running(efx->net_dev))
8ceee660
BH		 1603 return;
1604
8ceee660 1605 efx_start_port(efx);
9f2cb71c 1606 efx_start_datapath(efx);
8880f4ec 1607
626950db
AR		 1608 /* Start the hardware monitor if there is one */
1609 if (efx->type->monitor != NULL)
8ceee660
BH		 1610 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1611 efx_monitor_interval);
626950db
AR		 1612
1613 /* If link state detection is normally event-driven, we have
1614 * to poll now because we could have missed a change
1615 */
1616 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
78c1f0a0
SH		 1617 mutex_lock(&efx->mac_lock);
1618 if (efx->phy_op->poll(efx))
1619 efx_link_status_changed(efx);
1620 mutex_unlock(&efx->mac_lock);
1621 }
55edc6e6 1622
ef2b90ee 1623 efx->type->start_stats(efx);
8ceee660
BH		 1624}
1625
1626/* Flush all delayed work. Should only be called when no more delayed work
1627 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1628 * since we're holding the rtnl_lock at this point. */
1629static void efx_flush_all(struct efx_nic *efx)
1630{
dd40781e 1631 /* Make sure the hardware monitor and event self-test are stopped */
8ceee660 1632 cancel_delayed_work_sync(&efx->monitor_work);
dd40781e 1633 efx_selftest_async_cancel(efx);
8ceee660 1634 /* Stop scheduled port reconfigurations */
766ca0fa 1635 cancel_work_sync(&efx->mac_work);
8ceee660
BH		 1636}
1637
8b7325b4
BH		 1638/* Quiesce the hardware and software data path, and regular activity
1639 * for the port without bringing the link down. Safe to call multiple
1640 * times with the NIC in almost any state, but interrupts should be
1641 * enabled. Requires the RTNL lock.
1642 */
8ceee660
BH		 1643static void efx_stop_all(struct efx_nic *efx)
1644{
8ceee660
BH		 1645 EFX_ASSERT_RESET_SERIALISED(efx);
1646
1647 /* port_enabled can be read safely under the rtnl lock */
1648 if (!efx->port_enabled)
1649 return;
1650
ef2b90ee 1651 efx->type->stop_stats(efx);
8ceee660
BH		 1652 efx_stop_port(efx);
1653
fdaa9aed 1654 /* Flush efx_mac_work(), refill_workqueue, monitor_work */
8ceee660
BH		 1655 efx_flush_all(efx);
1656
29c69a48
BH		 1657 /* Stop the kernel transmit interface. This is only valid if
1658 * the device is stopped or detached; otherwise the watchdog
1659 * may fire immediately.
1660 */
1661 WARN_ON(netif_running(efx->net_dev) &&
1662 netif_device_present(efx->net_dev));
9f2cb71c
BH		 1663 netif_tx_disable(efx->net_dev);
1664
1665 efx_stop_datapath(efx);
8ceee660
BH		 1666}
1667
1668static void efx_remove_all(struct efx_nic *efx)
1669{
4642610c 1670 efx_remove_channels(efx);
7f967c01 1671 efx_remove_filters(efx);
8ceee660
BH		 1672 efx_remove_port(efx);
1673 efx_remove_nic(efx);
1674}
1675
8ceee660
BH		 1676/**************************************************************************
1677 *
1678 * Interrupt moderation
1679 *
1680 **************************************************************************/
1681
cc180b69 1682static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns)
0d86ebd8 1683{
b548f976
BH		 1684 if (usecs == 0)
1685 return 0;
cc180b69 1686 if (usecs * 1000 < quantum_ns)
0d86ebd8 1687 return 1; /* never round down to 0 */
cc180b69 1688 return usecs * 1000 / quantum_ns;
0d86ebd8
BH		 1689}
1690
8ceee660 1691/* Set interrupt moderation parameters */
9e393b30
BH		 1692int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
1693 unsigned int rx_usecs, bool rx_adaptive,
1694 bool rx_may_override_tx)
8ceee660 1695{
f7d12cdc 1696 struct efx_channel *channel;
cc180b69
BH		 1697 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max *
1698 efx->timer_quantum_ns,
1699 1000);
1700 unsigned int tx_ticks;
1701 unsigned int rx_ticks;
8ceee660
BH		 1702
1703 EFX_ASSERT_RESET_SERIALISED(efx);
1704
cc180b69 1705 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max)
9e393b30
BH		 1706 return -EINVAL;
1707
cc180b69
BH		 1708 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns);
1709 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns);
1710
9e393b30
BH		 1711 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 &&
1712 !rx_may_override_tx) {
1713 netif_err(efx, drv, efx->net_dev, "Channels are shared. "
1714 "RX and TX IRQ moderation must be equal\n");
1715 return -EINVAL;
1716 }
1717
6fb70fd1 1718 efx->irq_rx_adaptive = rx_adaptive;
0d86ebd8 1719 efx->irq_rx_moderation = rx_ticks;
f7d12cdc 1720 efx_for_each_channel(channel, efx) {
525da907 1721 if (efx_channel_has_rx_queue(channel))
f7d12cdc 1722 channel->irq_moderation = rx_ticks;
525da907 1723 else if (efx_channel_has_tx_queues(channel))
f7d12cdc
BH		 1724 channel->irq_moderation = tx_ticks;
1725 }
9e393b30
BH		 1726
1727 return 0;
8ceee660
BH		 1728}
1729
a0c4faf5
BH		 1730void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
1731 unsigned int *rx_usecs, bool *rx_adaptive)
1732{
cc180b69
BH		 1733 /* We must round up when converting ticks to microseconds
1734 * because we round down when converting the other way.
1735 */
1736
a0c4faf5 1737 *rx_adaptive = efx->irq_rx_adaptive;
cc180b69
BH		 1738 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation *
1739 efx->timer_quantum_ns,
1740 1000);
a0c4faf5
BH		 1741
1742 /* If channels are shared between RX and TX, so is IRQ
1743 * moderation. Otherwise, IRQ moderation is the same for all
1744 * TX channels and is not adaptive.
1745 */
1746 if (efx->tx_channel_offset == 0)
1747 *tx_usecs = *rx_usecs;
1748 else
cc180b69 1749 *tx_usecs = DIV_ROUND_UP(
a0c4faf5 1750 efx->channel[efx->tx_channel_offset]->irq_moderation *
cc180b69
BH		 1751 efx->timer_quantum_ns,
1752 1000);
a0c4faf5
BH		 1753}
1754
8ceee660
BH		 1755/**************************************************************************
1756 *
1757 * Hardware monitor
1758 *
1759 **************************************************************************/
1760
e254c274 1761/* Run periodically off the general workqueue */
8ceee660
BH		 1762static void efx_monitor(struct work_struct *data)
1763{
1764 struct efx_nic *efx = container_of(data, struct efx_nic,
1765 monitor_work.work);
8ceee660 1766
62776d03
BH		 1767 netif_vdbg(efx, timer, efx->net_dev,
1768 "hardware monitor executing on CPU %d\n",
1769 raw_smp_processor_id());
ef2b90ee 1770 BUG_ON(efx->type->monitor == NULL);
8ceee660 1771
8ceee660
BH		 1772 /* If the mac_lock is already held then it is likely a port
1773 * reconfiguration is already in place, which will likely do
e254c274
BH		 1774 * most of the work of monitor() anyway. */
1775 if (mutex_trylock(&efx->mac_lock)) {
1776 if (efx->port_enabled)
1777 efx->type->monitor(efx);
1778 mutex_unlock(&efx->mac_lock);
1779 }
8ceee660 1780
8ceee660
BH		 1781 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1782 efx_monitor_interval);
1783}
1784
1785/**************************************************************************
1786 *
1787 * ioctls
1788 *
1789 *************************************************************************/
1790
1791/* Net device ioctl
1792 * Context: process, rtnl_lock() held.
1793 */
1794static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1795{
767e468c 1796 struct efx_nic *efx = netdev_priv(net_dev);
68e7f45e 1797 struct mii_ioctl_data *data = if_mii(ifr);
8ceee660 1798
7c236c43
SH		 1799 if (cmd == SIOCSHWTSTAMP)
1800 return efx_ptp_ioctl(efx, ifr, cmd);
1801
68e7f45e
BH		 1802 /* Convert phy_id from older PRTAD/DEVAD format */
1803 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1804 (data->phy_id & 0xfc00) == 0x0400)
1805 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1806
1807 return mdio_mii_ioctl(&efx->mdio, data, cmd);
8ceee660
BH		 1808}
1809
1810/**************************************************************************
1811 *
1812 * NAPI interface
1813 *
1814 **************************************************************************/
1815
7f967c01
BH		 1816static void efx_init_napi_channel(struct efx_channel *channel)
1817{
1818 struct efx_nic *efx = channel->efx;
1819
1820 channel->napi_dev = efx->net_dev;
1821 netif_napi_add(channel->napi_dev, &channel->napi_str,
1822 efx_poll, napi_weight);
1823}
1824
e8f14992 1825static void efx_init_napi(struct efx_nic *efx)
8ceee660
BH		 1826{
1827 struct efx_channel *channel;
8ceee660 1828
7f967c01
BH		 1829 efx_for_each_channel(channel, efx)
1830 efx_init_napi_channel(channel);
e8f14992
BH		 1831}
1832
1833static void efx_fini_napi_channel(struct efx_channel *channel)
1834{
1835 if (channel->napi_dev)
1836 netif_napi_del(&channel->napi_str);
1837 channel->napi_dev = NULL;
8ceee660
BH		 1838}
1839
1840static void efx_fini_napi(struct efx_nic *efx)
1841{
1842 struct efx_channel *channel;
1843
e8f14992
BH		 1844 efx_for_each_channel(channel, efx)
1845 efx_fini_napi_channel(channel);
8ceee660
BH		 1846}
1847
1848/**************************************************************************
1849 *
1850 * Kernel netpoll interface
1851 *
1852 *************************************************************************/
1853
1854#ifdef CONFIG_NET_POLL_CONTROLLER
1855
1856/* Although in the common case interrupts will be disabled, this is not
1857 * guaranteed. However, all our work happens inside the NAPI callback,
1858 * so no locking is required.
1859 */
1860static void efx_netpoll(struct net_device *net_dev)
1861{
767e468c 1862 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1863 struct efx_channel *channel;
1864
64ee3120 1865 efx_for_each_channel(channel, efx)
8ceee660
BH		 1866 efx_schedule_channel(channel);
1867}
1868
1869#endif
1870
1871/**************************************************************************
1872 *
1873 * Kernel net device interface
1874 *
1875 *************************************************************************/
1876
1877/* Context: process, rtnl_lock() held. */
1878static int efx_net_open(struct net_device *net_dev)
1879{
767e468c 1880 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4
BH		 1881 int rc;
1882
62776d03
BH		 1883 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
1884 raw_smp_processor_id());
8ceee660 1885
8b7325b4
BH		 1886 rc = efx_check_disabled(efx);
1887 if (rc)
1888 return rc;
f8b87c17
BH		 1889 if (efx->phy_mode & PHY_MODE_SPECIAL)
1890 return -EBUSY;
8880f4ec
BH		 1891 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
1892 return -EIO;
f8b87c17 1893
78c1f0a0
SH		 1894 /* Notify the kernel of the link state polled during driver load,
1895 * before the monitor starts running */
1896 efx_link_status_changed(efx);
1897
8ceee660 1898 efx_start_all(efx);
dd40781e 1899 efx_selftest_async_start(efx);
8ceee660
BH		 1900 return 0;
1901}
1902
1903/* Context: process, rtnl_lock() held.
1904 * Note that the kernel will ignore our return code; this method
1905 * should really be a void.
1906 */
1907static int efx_net_stop(struct net_device *net_dev)
1908{
767e468c 1909 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1910
62776d03
BH		 1911 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
1912 raw_smp_processor_id());
8ceee660 1913
8b7325b4
BH		 1914 /* Stop the device and flush all the channels */
1915 efx_stop_all(efx);
8ceee660
BH		 1916
1917 return 0;
1918}
1919
5b9e207c 1920/* Context: process, dev_base_lock or RTNL held, non-blocking. */
2aa9ef11
BH		 1921static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev,
1922 struct rtnl_link_stats64 *stats)
8ceee660 1923{
767e468c 1924 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1925
55edc6e6 1926 spin_lock_bh(&efx->stats_lock);
cd0ecc9a 1927 efx->type->update_stats(efx, NULL, stats);
1cb34522
BH		 1928 spin_unlock_bh(&efx->stats_lock);
1929
8ceee660
BH		 1930 return stats;
1931}
1932
1933/* Context: netif_tx_lock held, BHs disabled. */
1934static void efx_watchdog(struct net_device *net_dev)
1935{
767e468c 1936 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1937
62776d03
BH		 1938 netif_err(efx, tx_err, efx->net_dev,
1939 "TX stuck with port_enabled=%d: resetting channels\n",
1940 efx->port_enabled);
8ceee660 1941
739bb23d 1942 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
8ceee660
BH		 1943}
1944
1945
1946/* Context: process, rtnl_lock() held. */
1947static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
1948{
767e468c 1949 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4 1950 int rc;
8ceee660 1951
8b7325b4
BH		 1952 rc = efx_check_disabled(efx);
1953 if (rc)
1954 return rc;
8ceee660
BH		 1955 if (new_mtu > EFX_MAX_MTU)
1956 return -EINVAL;
1957
62776d03 1958 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
8ceee660 1959
29c69a48
BH		 1960 efx_device_detach_sync(efx);
1961 efx_stop_all(efx);
1962
d3245b28 1963 mutex_lock(&efx->mac_lock);
8ceee660 1964 net_dev->mtu = new_mtu;
710b208d 1965 efx->type->reconfigure_mac(efx);
d3245b28
BH		 1966 mutex_unlock(&efx->mac_lock);
1967
8ceee660 1968 efx_start_all(efx);
29c69a48 1969 netif_device_attach(efx->net_dev);
6c8eef4a 1970 return 0;
8ceee660
BH		 1971}
1972
1973static int efx_set_mac_address(struct net_device *net_dev, void *data)
1974{
767e468c 1975 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1976 struct sockaddr *addr = data;
1977 char *new_addr = addr->sa_data;
1978
8ceee660 1979 if (!is_valid_ether_addr(new_addr)) {
62776d03
BH		 1980 netif_err(efx, drv, efx->net_dev,
1981 "invalid ethernet MAC address requested: %pM\n",
1982 new_addr);
504f9b5a 1983 return -EADDRNOTAVAIL;
8ceee660
BH		 1984 }
1985
1986 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
cd2d5b52 1987 efx_sriov_mac_address_changed(efx);
8ceee660
BH		 1988
1989 /* Reconfigure the MAC */
d3245b28 1990 mutex_lock(&efx->mac_lock);
710b208d 1991 efx->type->reconfigure_mac(efx);
d3245b28 1992 mutex_unlock(&efx->mac_lock);
8ceee660
BH		 1993
1994 return 0;
1995}
1996
a816f75a 1997/* Context: netif_addr_lock held, BHs disabled. */
0fca8c97 1998static void efx_set_rx_mode(struct net_device *net_dev)
8ceee660 1999{
767e468c 2000 struct efx_nic *efx = netdev_priv(net_dev);
a816f75a 2001
8be4f3e6
BH		 2002 if (efx->port_enabled)
2003 queue_work(efx->workqueue, &efx->mac_work);
2004 /* Otherwise efx_start_port() will do this */
8ceee660
BH		 2005}
2006
c8f44aff 2007static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
abfe9039
BH		 2008{
2009 struct efx_nic *efx = netdev_priv(net_dev);
2010
2011 /* If disabling RX n-tuple filtering, clear existing filters */
2012 if (net_dev->features & ~data & NETIF_F_NTUPLE)
2013 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
2014
2015 return 0;
2016}
2017
c3ecb9f3
SH		 2018static const struct net_device_ops efx_netdev_ops = {
2019 .ndo_open = efx_net_open,
2020 .ndo_stop = efx_net_stop,
4472702e 2021 .ndo_get_stats64 = efx_net_stats,
c3ecb9f3
SH		 2022 .ndo_tx_timeout = efx_watchdog,
2023 .ndo_start_xmit = efx_hard_start_xmit,
2024 .ndo_validate_addr = eth_validate_addr,
2025 .ndo_do_ioctl = efx_ioctl,
2026 .ndo_change_mtu = efx_change_mtu,
2027 .ndo_set_mac_address = efx_set_mac_address,
0fca8c97 2028 .ndo_set_rx_mode = efx_set_rx_mode,
abfe9039 2029 .ndo_set_features = efx_set_features,
cd2d5b52
BH		 2030#ifdef CONFIG_SFC_SRIOV
2031 .ndo_set_vf_mac = efx_sriov_set_vf_mac,
2032 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
2033 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
2034 .ndo_get_vf_config = efx_sriov_get_vf_config,
2035#endif
c3ecb9f3
SH		 2036#ifdef CONFIG_NET_POLL_CONTROLLER
2037 .ndo_poll_controller = efx_netpoll,
2038#endif
94b274bf 2039 .ndo_setup_tc = efx_setup_tc,
64d8ad6d
BH		 2040#ifdef CONFIG_RFS_ACCEL
2041 .ndo_rx_flow_steer = efx_filter_rfs,
2042#endif
c3ecb9f3
SH		 2043};
2044
7dde596e
BH		 2045static void efx_update_name(struct efx_nic *efx)
2046{
2047 strcpy(efx->name, efx->net_dev->name);
2048 efx_mtd_rename(efx);
2049 efx_set_channel_names(efx);
2050}
2051
8ceee660
BH		 2052static int efx_netdev_event(struct notifier_block *this,
2053 unsigned long event, void *ptr)
2054{
351638e7 2055 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr);
8ceee660 2056
7dde596e
BH		 2057 if (net_dev->netdev_ops == &efx_netdev_ops &&
2058 event == NETDEV_CHANGENAME)
2059 efx_update_name(netdev_priv(net_dev));
8ceee660
BH		 2060
2061 return NOTIFY_DONE;
2062}
2063
2064static struct notifier_block efx_netdev_notifier = {
2065 .notifier_call = efx_netdev_event,
2066};
2067
06d5e193
BH		 2068static ssize_t
2069show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
2070{
2071 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2072 return sprintf(buf, "%d\n", efx->phy_type);
2073}
776fbcc9 2074static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL);
06d5e193 2075
8ceee660
BH		 2076static int efx_register_netdev(struct efx_nic *efx)
2077{
2078 struct net_device *net_dev = efx->net_dev;
c04bfc6b 2079 struct efx_channel *channel;
8ceee660
BH		 2080 int rc;
2081
2082 net_dev->watchdog_timeo = 5 * HZ;
2083 net_dev->irq = efx->pci_dev->irq;
c3ecb9f3 2084 net_dev->netdev_ops = &efx_netdev_ops;
8ceee660 2085 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
7e6d06f0 2086 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
8ceee660 2087
7dde596e 2088 rtnl_lock();
aed0628d 2089
7153f623
BH		 2090 /* Enable resets to be scheduled and check whether any were
2091 * already requested. If so, the NIC is probably hosed so we
2092 * abort.
2093 */
2094 efx->state = STATE_READY;
2095 smp_mb(); /* ensure we change state before checking reset_pending */
2096 if (efx->reset_pending) {
2097 netif_err(efx, probe, efx->net_dev,
2098 "aborting probe due to scheduled reset\n");
2099 rc = -EIO;
2100 goto fail_locked;
2101 }
2102
aed0628d
BH		 2103 rc = dev_alloc_name(net_dev, net_dev->name);
2104 if (rc < 0)
2105 goto fail_locked;
7dde596e 2106 efx_update_name(efx);
aed0628d 2107
8f8b3d51
BH		 2108 /* Always start with carrier off; PHY events will detect the link */
2109 netif_carrier_off(net_dev);
2110
aed0628d
BH		 2111 rc = register_netdevice(net_dev);
2112 if (rc)
2113 goto fail_locked;
2114
c04bfc6b
BH		 2115 efx_for_each_channel(channel, efx) {
2116 struct efx_tx_queue *tx_queue;
60031fcc
BH		 2117 efx_for_each_channel_tx_queue(tx_queue, channel)
2118 efx_init_tx_queue_core_txq(tx_queue);
c04bfc6b
BH		 2119 }
2120
7dde596e 2121 rtnl_unlock();
8ceee660 2122
06d5e193
BH		 2123 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2124 if (rc) {
62776d03
BH		 2125 netif_err(efx, drv, efx->net_dev,
2126 "failed to init net dev attributes\n");
06d5e193
BH		 2127 goto fail_registered;
2128 }
2129
8ceee660 2130 return 0;
06d5e193 2131
7153f623
BH		 2132fail_registered:
2133 rtnl_lock();
2134 unregister_netdevice(net_dev);
aed0628d 2135fail_locked:
7153f623 2136 efx->state = STATE_UNINIT;
aed0628d 2137 rtnl_unlock();
62776d03 2138 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
aed0628d 2139 return rc;
8ceee660
BH		 2140}
2141
2142static void efx_unregister_netdev(struct efx_nic *efx)
2143{
8ceee660
BH		 2144 if (!efx->net_dev)
2145 return;
2146
767e468c 2147 BUG_ON(netdev_priv(efx->net_dev) != efx);
8ceee660 2148
73ba7b68
BH		 2149 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2150 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
7153f623
BH		 2151
2152 rtnl_lock();
2153 unregister_netdevice(efx->net_dev);
2154 efx->state = STATE_UNINIT;
2155 rtnl_unlock();
8ceee660
BH		 2156}
2157
2158/**************************************************************************
2159 *
2160 * Device reset and suspend
2161 *
2162 **************************************************************************/
2163
2467ca46
BH		 2164/* Tears down the entire software state and most of the hardware state
2165 * before reset. */
d3245b28 2166void efx_reset_down(struct efx_nic *efx, enum reset_type method)
8ceee660 2167{
8ceee660
BH		 2168 EFX_ASSERT_RESET_SERIALISED(efx);
2169
2467ca46 2170 efx_stop_all(efx);
d8291187 2171 efx_disable_interrupts(efx);
5642ceef
BH		 2172
2173 mutex_lock(&efx->mac_lock);
4b988280
SH		 2174 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
2175 efx->phy_op->fini(efx);
ef2b90ee 2176 efx->type->fini(efx);
8ceee660
BH		 2177}
2178
2467ca46
BH		 2179/* This function will always ensure that the locks acquired in
2180 * efx_reset_down() are released. A failure return code indicates
2181 * that we were unable to reinitialise the hardware, and the
2182 * driver should be disabled. If ok is false, then the rx and tx
2183 * engines are not restarted, pending a RESET_DISABLE. */
d3245b28 2184int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
8ceee660
BH		 2185{
2186 int rc;
2187
2467ca46 2188 EFX_ASSERT_RESET_SERIALISED(efx);
8ceee660 2189
ef2b90ee 2190 rc = efx->type->init(efx);
8ceee660 2191 if (rc) {
62776d03 2192 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
eb9f6744 2193 goto fail;
8ceee660
BH		 2194 }
2195
eb9f6744
BH		 2196 if (!ok)
2197 goto fail;
2198
4b988280 2199 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
eb9f6744
BH		 2200 rc = efx->phy_op->init(efx);
2201 if (rc)
2202 goto fail;
2203 if (efx->phy_op->reconfigure(efx))
62776d03
BH		 2204 netif_err(efx, drv, efx->net_dev,
2205 "could not restore PHY settings\n");
4b988280
SH		 2206 }
2207
d8291187 2208 efx_enable_interrupts(efx);
64eebcfd 2209 efx_restore_filters(efx);
cd2d5b52 2210 efx_sriov_reset(efx);
eb9f6744 2211
eb9f6744
BH		 2212 mutex_unlock(&efx->mac_lock);
2213
2214 efx_start_all(efx);
2215
2216 return 0;
2217
2218fail:
2219 efx->port_initialized = false;
2467ca46
BH		 2220
2221 mutex_unlock(&efx->mac_lock);
2222
8ceee660
BH		 2223 return rc;
2224}
2225
eb9f6744
BH		 2226/* Reset the NIC using the specified method. Note that the reset may
2227 * fail, in which case the card will be left in an unusable state.
8ceee660 2228 *
eb9f6744 2229 * Caller must hold the rtnl_lock.
8ceee660 2230 */
eb9f6744 2231int efx_reset(struct efx_nic *efx, enum reset_type method)
8ceee660 2232{
eb9f6744
BH		 2233 int rc, rc2;
2234 bool disabled;
8ceee660 2235
62776d03
BH		 2236 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2237 RESET_TYPE(method));
8ceee660 2238
c2f3b8e3 2239 efx_device_detach_sync(efx);
d3245b28 2240 efx_reset_down(efx, method);
8ceee660 2241
ef2b90ee 2242 rc = efx->type->reset(efx, method);
8ceee660 2243 if (rc) {
62776d03 2244 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
eb9f6744 2245 goto out;
8ceee660
BH		 2246 }
2247
a7d529ae
BH		 2248 /* Clear flags for the scopes we covered. We assume the NIC and
2249 * driver are now quiescent so that there is no race here.
2250 */
2251 efx->reset_pending &= -(1 << (method + 1));
8ceee660
BH		 2252
2253 /* Reinitialise bus-mastering, which may have been turned off before
2254 * the reset was scheduled. This is still appropriate, even in the
2255 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2256 * can respond to requests. */
2257 pci_set_master(efx->pci_dev);
2258
eb9f6744 2259out:
8ceee660 2260 /* Leave device stopped if necessary */
626950db
AR		 2261 disabled = rc ||
2262 method == RESET_TYPE_DISABLE ||
2263 method == RESET_TYPE_RECOVER_OR_DISABLE;
eb9f6744
BH		 2264 rc2 = efx_reset_up(efx, method, !disabled);
2265 if (rc2) {
2266 disabled = true;
2267 if (!rc)
2268 rc = rc2;
8ceee660
BH		 2269 }
2270
eb9f6744 2271 if (disabled) {
f49a4589 2272 dev_close(efx->net_dev);
62776d03 2273 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
f4bd954e 2274 efx->state = STATE_DISABLED;
f4bd954e 2275 } else {
62776d03 2276 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
e4abce85 2277 netif_device_attach(efx->net_dev);
f4bd954e 2278 }
8ceee660
BH		 2279 return rc;
2280}
2281
626950db
AR		 2282/* Try recovery mechanisms.
2283 * For now only EEH is supported.
2284 * Returns 0 if the recovery mechanisms are unsuccessful.
2285 * Returns a non-zero value otherwise.
2286 */
b28405b0 2287int efx_try_recovery(struct efx_nic *efx)
626950db
AR		 2288{
2289#ifdef CONFIG_EEH
2290 /* A PCI error can occur and not be seen by EEH because nothing
2291 * happens on the PCI bus. In this case the driver may fail and
2292 * schedule a 'recover or reset', leading to this recovery handler.
2293 * Manually call the eeh failure check function.
2294 */
2295 struct eeh_dev *eehdev =
2296 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
2297
2298 if (eeh_dev_check_failure(eehdev)) {
2299 /* The EEH mechanisms will handle the error and reset the
2300 * device if necessary.
2301 */
2302 return 1;
2303 }
2304#endif
2305 return 0;
2306}
2307
8ceee660
BH		 2308/* The worker thread exists so that code that cannot sleep can
2309 * schedule a reset for later.
2310 */
2311static void efx_reset_work(struct work_struct *data)
2312{
eb9f6744 2313 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
626950db
AR		 2314 unsigned long pending;
2315 enum reset_type method;
2316
2317 pending = ACCESS_ONCE(efx->reset_pending);
2318 method = fls(pending) - 1;
2319
2320 if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
2321 method == RESET_TYPE_RECOVER_OR_ALL) &&
2322 efx_try_recovery(efx))
2323 return;
8ceee660 2324
a7d529ae 2325 if (!pending)
319ba649
SH		 2326 return;
2327
eb9f6744 2328 rtnl_lock();
7153f623
BH		 2329
2330 /* We checked the state in efx_schedule_reset() but it may
2331 * have changed by now. Now that we have the RTNL lock,
2332 * it cannot change again.
2333 */
2334 if (efx->state == STATE_READY)
626950db 2335 (void)efx_reset(efx, method);
7153f623 2336
eb9f6744 2337 rtnl_unlock();
8ceee660
BH		 2338}
2339
2340void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2341{
2342 enum reset_type method;
2343
626950db
AR		 2344 if (efx->state == STATE_RECOVERY) {
2345 netif_dbg(efx, drv, efx->net_dev,
2346 "recovering: skip scheduling %s reset\n",
2347 RESET_TYPE(type));
2348 return;
2349 }
2350
8ceee660
BH		 2351 switch (type) {
2352 case RESET_TYPE_INVISIBLE:
2353 case RESET_TYPE_ALL:
626950db 2354 case RESET_TYPE_RECOVER_OR_ALL:
8ceee660
BH		 2355 case RESET_TYPE_WORLD:
2356 case RESET_TYPE_DISABLE:
626950db 2357 case RESET_TYPE_RECOVER_OR_DISABLE:
8ceee660 2358 method = type;
0e2a9c7c
BH		 2359 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2360 RESET_TYPE(method));
8ceee660 2361 break;
8ceee660 2362 default:
0e2a9c7c 2363 method = efx->type->map_reset_reason(type);
62776d03
BH		 2364 netif_dbg(efx, drv, efx->net_dev,
2365 "scheduling %s reset for %s\n",
2366 RESET_TYPE(method), RESET_TYPE(type));
0e2a9c7c
BH		 2367 break;
2368 }
8ceee660 2369
a7d529ae 2370 set_bit(method, &efx->reset_pending);
7153f623
BH		 2371 smp_mb(); /* ensure we change reset_pending before checking state */
2372
2373 /* If we're not READY then just leave the flags set as the cue
2374 * to abort probing or reschedule the reset later.
2375 */
2376 if (ACCESS_ONCE(efx->state) != STATE_READY)
2377 return;
8ceee660 2378
8880f4ec
BH		 2379 /* efx_process_channel() will no longer read events once a
2380 * reset is scheduled. So switch back to poll'd MCDI completions. */
2381 efx_mcdi_mode_poll(efx);
2382
1ab00629 2383 queue_work(reset_workqueue, &efx->reset_work);
8ceee660
BH		 2384}
2385
2386/**************************************************************************
2387 *
2388 * List of NICs we support
2389 *
2390 **************************************************************************/
2391
2392/* PCI device ID table */
a3aa1884 2393static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
937383a5
BH		 2394 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2395 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0),
daeda630 2396 .driver_data = (unsigned long) &falcon_a1_nic_type},
937383a5
BH		 2397 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2398 PCI_DEVICE_ID_SOLARFLARE_SFC4000B),
daeda630 2399 .driver_data = (unsigned long) &falcon_b0_nic_type},
547c474f 2400 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
8880f4ec 2401 .driver_data = (unsigned long) &siena_a0_nic_type},
547c474f 2402 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
8880f4ec 2403 .driver_data = (unsigned long) &siena_a0_nic_type},
8ceee660
BH		 2404 {0} /* end of list */
2405};
2406
2407/**************************************************************************
2408 *
3759433d 2409 * Dummy PHY/MAC operations
8ceee660 2410 *
01aad7b6 2411 * Can be used for some unimplemented operations
8ceee660
BH		 2412 * Needed so all function pointers are valid and do not have to be tested
2413 * before use
2414 *
2415 **************************************************************************/
2416int efx_port_dummy_op_int(struct efx_nic *efx)
2417{
2418 return 0;
2419}
2420void efx_port_dummy_op_void(struct efx_nic *efx) {}
d215697f 2421
2422static bool efx_port_dummy_op_poll(struct efx_nic *efx)
fdaa9aed
SH		 2423{
2424 return false;
2425}
8ceee660 2426
6c8c2513 2427static const struct efx_phy_operations efx_dummy_phy_operations = {
8ceee660 2428 .init = efx_port_dummy_op_int,
d3245b28 2429 .reconfigure = efx_port_dummy_op_int,
fdaa9aed 2430 .poll = efx_port_dummy_op_poll,
8ceee660 2431 .fini = efx_port_dummy_op_void,
8ceee660
BH		 2432};
2433
8ceee660
BH		 2434/**************************************************************************
2435 *
2436 * Data housekeeping
2437 *
2438 **************************************************************************/
2439
2440/* This zeroes out and then fills in the invariants in a struct
2441 * efx_nic (including all sub-structures).
2442 */
adeb15aa 2443static int efx_init_struct(struct efx_nic *efx,
8ceee660
BH		 2444 struct pci_dev *pci_dev, struct net_device *net_dev)
2445{
4642610c 2446 int i;
8ceee660
BH		 2447
2448 /* Initialise common structures */
8ceee660 2449 spin_lock_init(&efx->biu_lock);
76884835
BH		 2450#ifdef CONFIG_SFC_MTD
2451 INIT_LIST_HEAD(&efx->mtd_list);
2452#endif
8ceee660
BH		 2453 INIT_WORK(&efx->reset_work, efx_reset_work);
2454 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
dd40781e 2455 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
8ceee660 2456 efx->pci_dev = pci_dev;
62776d03 2457 efx->msg_enable = debug;
f16aeea0 2458 efx->state = STATE_UNINIT;
8ceee660 2459 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
8ceee660
BH		 2460
2461 efx->net_dev = net_dev;
43a3739d
JC		 2462 efx->rx_prefix_size = efx->type->rx_prefix_size;
2463 efx->rx_packet_hash_offset =
2464 efx->type->rx_hash_offset - efx->type->rx_prefix_size;
8ceee660
BH		 2465 spin_lock_init(&efx->stats_lock);
2466 mutex_init(&efx->mac_lock);
2467 efx->phy_op = &efx_dummy_phy_operations;
68e7f45e 2468 efx->mdio.dev = net_dev;
766ca0fa 2469 INIT_WORK(&efx->mac_work, efx_mac_work);
9f2cb71c 2470 init_waitqueue_head(&efx->flush_wq);
8ceee660
BH		 2471
2472 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
4642610c
BH		 2473 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2474 if (!efx->channel[i])
2475 goto fail;
d8291187
BH		 2476 efx->msi_context[i].efx = efx;
2477 efx->msi_context[i].index = i;
8ceee660
BH		 2478 }
2479
8ceee660
BH		 2480 /* Higher numbered interrupt modes are less capable! */
2481 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2482 interrupt_mode);
2483
6977dc63
BH		 2484 /* Would be good to use the net_dev name, but we're too early */
2485 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2486 pci_name(pci_dev));
2487 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1ab00629 2488 if (!efx->workqueue)
4642610c 2489 goto fail;
8d9853d9 2490
8ceee660 2491 return 0;
4642610c
BH		 2492
2493fail:
2494 efx_fini_struct(efx);
2495 return -ENOMEM;
8ceee660
BH		 2496}
2497
2498static void efx_fini_struct(struct efx_nic *efx)
2499{
8313aca3
BH		 2500 int i;
2501
2502 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2503 kfree(efx->channel[i]);
2504
8ceee660
BH		 2505 if (efx->workqueue) {
2506 destroy_workqueue(efx->workqueue);
2507 efx->workqueue = NULL;
2508 }
2509}
2510
2511/**************************************************************************
2512 *
2513 * PCI interface
2514 *
2515 **************************************************************************/
2516
2517/* Main body of final NIC shutdown code
2518 * This is called only at module unload (or hotplug removal).
2519 */
2520static void efx_pci_remove_main(struct efx_nic *efx)
2521{
7153f623
BH		 2522 /* Flush reset_work. It can no longer be scheduled since we
2523 * are not READY.
2524 */
2525 BUG_ON(efx->state == STATE_READY);
2526 cancel_work_sync(&efx->reset_work);
2527
d8291187 2528 efx_disable_interrupts(efx);
152b6a62 2529 efx_nic_fini_interrupt(efx);
8ceee660 2530 efx_fini_port(efx);
ef2b90ee 2531 efx->type->fini(efx);
8ceee660
BH		 2532 efx_fini_napi(efx);
2533 efx_remove_all(efx);
2534}
2535
2536/* Final NIC shutdown
2537 * This is called only at module unload (or hotplug removal).
2538 */
2539static void efx_pci_remove(struct pci_dev *pci_dev)
2540{
2541 struct efx_nic *efx;
2542
2543 efx = pci_get_drvdata(pci_dev);
2544 if (!efx)
2545 return;
2546
2547 /* Mark the NIC as fini, then stop the interface */
2548 rtnl_lock();
8ceee660 2549 dev_close(efx->net_dev);
d8291187 2550 efx_disable_interrupts(efx);
8ceee660
BH		 2551 rtnl_unlock();
2552
cd2d5b52 2553 efx_sriov_fini(efx);
8ceee660
BH		 2554 efx_unregister_netdev(efx);
2555
7dde596e
BH		 2556 efx_mtd_remove(efx);
2557
8ceee660
BH		 2558 efx_pci_remove_main(efx);
2559
8ceee660 2560 efx_fini_io(efx);
62776d03 2561 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
8ceee660 2562
8ceee660 2563 efx_fini_struct(efx);
3de4e301 2564 pci_set_drvdata(pci_dev, NULL);
8ceee660 2565 free_netdev(efx->net_dev);
626950db
AR		 2566
2567 pci_disable_pcie_error_reporting(pci_dev);
8ceee660
BH		 2568};
2569
460eeaa0
BH		 2570/* NIC VPD information
2571 * Called during probe to display the part number of the
2572 * installed NIC. VPD is potentially very large but this should
2573 * always appear within the first 512 bytes.
2574 */
2575#define SFC_VPD_LEN 512
2576static void efx_print_product_vpd(struct efx_nic *efx)
2577{
2578 struct pci_dev *dev = efx->pci_dev;
2579 char vpd_data[SFC_VPD_LEN];
2580 ssize_t vpd_size;
2581 int i, j;
2582
2583 /* Get the vpd data from the device */
2584 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
2585 if (vpd_size <= 0) {
2586 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
2587 return;
2588 }
2589
2590 /* Get the Read only section */
2591 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
2592 if (i < 0) {
2593 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
2594 return;
2595 }
2596
2597 j = pci_vpd_lrdt_size(&vpd_data[i]);
2598 i += PCI_VPD_LRDT_TAG_SIZE;
2599 if (i + j > vpd_size)
2600 j = vpd_size - i;
2601
2602 /* Get the Part number */
2603 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
2604 if (i < 0) {
2605 netif_err(efx, drv, efx->net_dev, "Part number not found\n");
2606 return;
2607 }
2608
2609 j = pci_vpd_info_field_size(&vpd_data[i]);
2610 i += PCI_VPD_INFO_FLD_HDR_SIZE;
2611 if (i + j > vpd_size) {
2612 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
2613 return;
2614 }
2615
2616 netif_info(efx, drv, efx->net_dev,
2617 "Part Number : %.*s\n", j, &vpd_data[i]);
2618}
2619
2620
8ceee660
BH		 2621/* Main body of NIC initialisation
2622 * This is called at module load (or hotplug insertion, theoretically).
2623 */
2624static int efx_pci_probe_main(struct efx_nic *efx)
2625{
2626 int rc;
2627
2628 /* Do start-of-day initialisation */
2629 rc = efx_probe_all(efx);
2630 if (rc)
2631 goto fail1;
2632
e8f14992 2633 efx_init_napi(efx);
8ceee660 2634
ef2b90ee 2635 rc = efx->type->init(efx);
8ceee660 2636 if (rc) {
62776d03
BH		 2637 netif_err(efx, probe, efx->net_dev,
2638 "failed to initialise NIC\n");
278c0621 2639 goto fail3;
8ceee660
BH		 2640 }
2641
2642 rc = efx_init_port(efx);
2643 if (rc) {
62776d03
BH		 2644 netif_err(efx, probe, efx->net_dev,
2645 "failed to initialise port\n");
278c0621 2646 goto fail4;
8ceee660
BH		 2647 }
2648
152b6a62 2649 rc = efx_nic_init_interrupt(efx);
8ceee660 2650 if (rc)
278c0621 2651 goto fail5;
d8291187 2652 efx_enable_interrupts(efx);
8ceee660
BH		 2653
2654 return 0;
2655
278c0621 2656 fail5:
8ceee660 2657 efx_fini_port(efx);
8ceee660 2658 fail4:
ef2b90ee 2659 efx->type->fini(efx);
8ceee660
BH		 2660 fail3:
2661 efx_fini_napi(efx);
8ceee660
BH		 2662 efx_remove_all(efx);
2663 fail1:
2664 return rc;
2665}
2666
2667/* NIC initialisation
2668 *
2669 * This is called at module load (or hotplug insertion,
73ba7b68 2670 * theoretically). It sets up PCI mappings, resets the NIC,
8ceee660
BH		 2671 * sets up and registers the network devices with the kernel and hooks
2672 * the interrupt service routine. It does not prepare the device for
2673 * transmission; this is left to the first time one of the network
2674 * interfaces is brought up (i.e. efx_net_open).
2675 */
87d1fc11 2676static int efx_pci_probe(struct pci_dev *pci_dev,
1dd06ae8 2677 const struct pci_device_id *entry)
8ceee660 2678{
8ceee660
BH		 2679 struct net_device *net_dev;
2680 struct efx_nic *efx;
fadac6aa 2681 int rc;
8ceee660
BH		 2682
2683 /* Allocate and initialise a struct net_device and struct efx_nic */
94b274bf
BH		 2684 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
2685 EFX_MAX_RX_QUEUES);
8ceee660
BH		 2686 if (!net_dev)
2687 return -ENOMEM;
adeb15aa
BH		 2688 efx = netdev_priv(net_dev);
2689 efx->type = (const struct efx_nic_type *) entry->driver_data;
2690 net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
97bc5415 2691 NETIF_F_HIGHDMA | NETIF_F_TSO |
abfe9039 2692 NETIF_F_RXCSUM);
adeb15aa 2693 if (efx->type->offload_features & NETIF_F_V6_CSUM)
738a8f4b 2694 net_dev->features |= NETIF_F_TSO6;
28506563
BH		 2695 /* Mask for features that also apply to VLAN devices */
2696 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
abfe9039
BH		 2697 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
2698 NETIF_F_RXCSUM);
2699 /* All offloads can be toggled */
2700 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA;
8ceee660 2701 pci_set_drvdata(pci_dev, efx);
62776d03 2702 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
adeb15aa 2703 rc = efx_init_struct(efx, pci_dev, net_dev);
8ceee660
BH		 2704 if (rc)
2705 goto fail1;
2706
62776d03 2707 netif_info(efx, probe, efx->net_dev,
ff79c8ac 2708 "Solarflare NIC detected\n");
8ceee660 2709
460eeaa0
BH		 2710 efx_print_product_vpd(efx);
2711
8ceee660
BH		 2712 /* Set up basic I/O (BAR mappings etc) */
2713 rc = efx_init_io(efx);
2714 if (rc)
2715 goto fail2;
2716
fadac6aa 2717 rc = efx_pci_probe_main(efx);
fadac6aa
BH		 2718 if (rc)
2719 goto fail3;
8ceee660 2720
8ceee660
BH		 2721 rc = efx_register_netdev(efx);
2722 if (rc)
fadac6aa 2723 goto fail4;
8ceee660 2724
cd2d5b52
BH		 2725 rc = efx_sriov_init(efx);
2726 if (rc)
2727 netif_err(efx, probe, efx->net_dev,
2728 "SR-IOV can't be enabled rc %d\n", rc);
2729
62776d03 2730 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
a5211bb5 2731
7c43161c 2732 /* Try to create MTDs, but allow this to fail */
a5211bb5 2733 rtnl_lock();
7c43161c 2734 rc = efx_mtd_probe(efx);
a5211bb5 2735 rtnl_unlock();
7c43161c
BH		 2736 if (rc)
2737 netif_warn(efx, probe, efx->net_dev,
2738 "failed to create MTDs (%d)\n", rc);
2739
626950db
AR		 2740 rc = pci_enable_pcie_error_reporting(pci_dev);
2741 if (rc && rc != -EINVAL)
2742 netif_warn(efx, probe, efx->net_dev,
2743 "pci_enable_pcie_error_reporting failed (%d)\n", rc);
2744
8ceee660
BH		 2745 return 0;
2746
8ceee660 2747 fail4:
fadac6aa 2748 efx_pci_remove_main(efx);
8ceee660
BH		 2749 fail3:
2750 efx_fini_io(efx);
2751 fail2:
2752 efx_fini_struct(efx);
2753 fail1:
3de4e301 2754 pci_set_drvdata(pci_dev, NULL);
5e2a911c 2755 WARN_ON(rc > 0);
62776d03 2756 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
8ceee660
BH		 2757 free_netdev(net_dev);
2758 return rc;
2759}
2760
89c758fa
BH		 2761static int efx_pm_freeze(struct device *dev)
2762{
2763 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2764
61da026d
BH		 2765 rtnl_lock();
2766
6032fb56
BH		 2767 if (efx->state != STATE_DISABLED) {
2768 efx->state = STATE_UNINIT;
89c758fa 2769
c2f3b8e3 2770 efx_device_detach_sync(efx);
89c758fa 2771
6032fb56 2772 efx_stop_all(efx);
d8291187 2773 efx_disable_interrupts(efx);
6032fb56 2774 }
89c758fa 2775
61da026d
BH		 2776 rtnl_unlock();
2777
89c758fa
BH		 2778 return 0;
2779}
2780
2781static int efx_pm_thaw(struct device *dev)
2782{
2783 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2784
61da026d
BH		 2785 rtnl_lock();
2786
6032fb56 2787 if (efx->state != STATE_DISABLED) {
d8291187 2788 efx_enable_interrupts(efx);
89c758fa 2789
6032fb56
BH		 2790 mutex_lock(&efx->mac_lock);
2791 efx->phy_op->reconfigure(efx);
2792 mutex_unlock(&efx->mac_lock);
89c758fa 2793
6032fb56 2794 efx_start_all(efx);
89c758fa 2795
6032fb56 2796 netif_device_attach(efx->net_dev);
89c758fa 2797
6032fb56 2798 efx->state = STATE_READY;
89c758fa 2799
6032fb56
BH		 2800 efx->type->resume_wol(efx);
2801 }
89c758fa 2802
61da026d
BH		 2803 rtnl_unlock();
2804
319ba649
SH		 2805 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
2806 queue_work(reset_workqueue, &efx->reset_work);
2807
89c758fa
BH		 2808 return 0;
2809}
2810
2811static int efx_pm_poweroff(struct device *dev)
2812{
2813 struct pci_dev *pci_dev = to_pci_dev(dev);
2814 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2815
2816 efx->type->fini(efx);
2817
a7d529ae 2818 efx->reset_pending = 0;
89c758fa
BH		 2819
2820 pci_save_state(pci_dev);
2821 return pci_set_power_state(pci_dev, PCI_D3hot);
2822}
2823
2824/* Used for both resume and restore */
2825static int efx_pm_resume(struct device *dev)
2826{
2827 struct pci_dev *pci_dev = to_pci_dev(dev);
2828 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2829 int rc;
2830
2831 rc = pci_set_power_state(pci_dev, PCI_D0);
2832 if (rc)
2833 return rc;
2834 pci_restore_state(pci_dev);
2835 rc = pci_enable_device(pci_dev);
2836 if (rc)
2837 return rc;
2838 pci_set_master(efx->pci_dev);
2839 rc = efx->type->reset(efx, RESET_TYPE_ALL);
2840 if (rc)
2841 return rc;
2842 rc = efx->type->init(efx);
2843 if (rc)
2844 return rc;
2845 efx_pm_thaw(dev);
2846 return 0;
2847}
2848
2849static int efx_pm_suspend(struct device *dev)
2850{
2851 int rc;
2852
2853 efx_pm_freeze(dev);
2854 rc = efx_pm_poweroff(dev);
2855 if (rc)
2856 efx_pm_resume(dev);
2857 return rc;
2858}
2859
18e83e4c 2860static const struct dev_pm_ops efx_pm_ops = {
89c758fa
BH		 2861 .suspend = efx_pm_suspend,
2862 .resume = efx_pm_resume,
2863 .freeze = efx_pm_freeze,
2864 .thaw = efx_pm_thaw,
2865 .poweroff = efx_pm_poweroff,
2866 .restore = efx_pm_resume,
2867};
2868
626950db
AR		 2869/* A PCI error affecting this device was detected.
2870 * At this point MMIO and DMA may be disabled.
2871 * Stop the software path and request a slot reset.
2872 */
debd0034 2873static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
2874 enum pci_channel_state state)
626950db
AR		 2875{
2876 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
2877 struct efx_nic *efx = pci_get_drvdata(pdev);
2878
2879 if (state == pci_channel_io_perm_failure)
2880 return PCI_ERS_RESULT_DISCONNECT;
2881
2882 rtnl_lock();
2883
2884 if (efx->state != STATE_DISABLED) {
2885 efx->state = STATE_RECOVERY;
2886 efx->reset_pending = 0;
2887
2888 efx_device_detach_sync(efx);
2889
2890 efx_stop_all(efx);
d8291187 2891 efx_disable_interrupts(efx);
626950db
AR		 2892
2893 status = PCI_ERS_RESULT_NEED_RESET;
2894 } else {
2895 /* If the interface is disabled we don't want to do anything
2896 * with it.
2897 */
2898 status = PCI_ERS_RESULT_RECOVERED;
2899 }
2900
2901 rtnl_unlock();
2902
2903 pci_disable_device(pdev);
2904
2905 return status;
2906}
2907
2908/* Fake a successfull reset, which will be performed later in efx_io_resume. */
debd0034 2909static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
626950db
AR		 2910{
2911 struct efx_nic *efx = pci_get_drvdata(pdev);
2912 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
2913 int rc;
2914
2915 if (pci_enable_device(pdev)) {
2916 netif_err(efx, hw, efx->net_dev,
2917 "Cannot re-enable PCI device after reset.\n");
2918 status = PCI_ERS_RESULT_DISCONNECT;
2919 }
2920
2921 rc = pci_cleanup_aer_uncorrect_error_status(pdev);
2922 if (rc) {
2923 netif_err(efx, hw, efx->net_dev,
2924 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc);
2925 /* Non-fatal error. Continue. */
2926 }
2927
2928 return status;
2929}
2930
2931/* Perform the actual reset and resume I/O operations. */
2932static void efx_io_resume(struct pci_dev *pdev)
2933{
2934 struct efx_nic *efx = pci_get_drvdata(pdev);
2935 int rc;
2936
2937 rtnl_lock();
2938
2939 if (efx->state == STATE_DISABLED)
2940 goto out;
2941
2942 rc = efx_reset(efx, RESET_TYPE_ALL);
2943 if (rc) {
2944 netif_err(efx, hw, efx->net_dev,
2945 "efx_reset failed after PCI error (%d)\n", rc);
2946 } else {
2947 efx->state = STATE_READY;
2948 netif_dbg(efx, hw, efx->net_dev,
2949 "Done resetting and resuming IO after PCI error.\n");
2950 }
2951
2952out:
2953 rtnl_unlock();
2954}
2955
2956/* For simplicity and reliability, we always require a slot reset and try to
2957 * reset the hardware when a pci error affecting the device is detected.
2958 * We leave both the link_reset and mmio_enabled callback unimplemented:
2959 * with our request for slot reset the mmio_enabled callback will never be
2960 * called, and the link_reset callback is not used by AER or EEH mechanisms.
2961 */
2962static struct pci_error_handlers efx_err_handlers = {
2963 .error_detected = efx_io_error_detected,
2964 .slot_reset = efx_io_slot_reset,
2965 .resume = efx_io_resume,
2966};
2967
8ceee660 2968static struct pci_driver efx_pci_driver = {
c5d5f5fd 2969 .name = KBUILD_MODNAME,
8ceee660
BH		 2970 .id_table = efx_pci_table,
2971 .probe = efx_pci_probe,
2972 .remove = efx_pci_remove,
89c758fa 2973 .driver.pm = &efx_pm_ops,
626950db 2974 .err_handler = &efx_err_handlers,
8ceee660
BH		 2975};
2976
2977/**************************************************************************
2978 *
2979 * Kernel module interface
2980 *
2981 *************************************************************************/
2982
2983module_param(interrupt_mode, uint, 0444);
2984MODULE_PARM_DESC(interrupt_mode,
2985 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
2986
2987static int __init efx_init_module(void)
2988{
2989 int rc;
2990
2991 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
2992
2993 rc = register_netdevice_notifier(&efx_netdev_notifier);
2994 if (rc)
2995 goto err_notifier;
2996
cd2d5b52
BH		 2997 rc = efx_init_sriov();
2998 if (rc)
2999 goto err_sriov;
3000
1ab00629
SH		 3001 reset_workqueue = create_singlethread_workqueue("sfc_reset");
3002 if (!reset_workqueue) {
3003 rc = -ENOMEM;
3004 goto err_reset;
3005 }
8ceee660
BH		 3006
3007 rc = pci_register_driver(&efx_pci_driver);
3008 if (rc < 0)
3009 goto err_pci;
3010
3011 return 0;
3012
3013 err_pci:
1ab00629
SH		 3014 destroy_workqueue(reset_workqueue);
3015 err_reset:
cd2d5b52
BH		 3016 efx_fini_sriov();
3017 err_sriov:
8ceee660
BH		 3018 unregister_netdevice_notifier(&efx_netdev_notifier);
3019 err_notifier:
3020 return rc;
3021}
3022
3023static void __exit efx_exit_module(void)
3024{
3025 printk(KERN_INFO "Solarflare NET driver unloading\n");
3026
3027 pci_unregister_driver(&efx_pci_driver);
1ab00629 3028 destroy_workqueue(reset_workqueue);
cd2d5b52 3029 efx_fini_sriov();
8ceee660
BH		 3030 unregister_netdevice_notifier(&efx_netdev_notifier);
3031
3032}
3033
3034module_init(efx_init_module);
3035module_exit(efx_exit_module);
3036
906bb26c
BH		 3037MODULE_AUTHOR("Solarflare Communications and "
3038 "Michael Brown <mbrown@fensystems.co.uk>");
8ceee660
BH		 3039MODULE_DESCRIPTION("Solarflare Communications network driver");
3040MODULE_LICENSE("GPL");
3041MODULE_DEVICE_TABLE(pci, efx_pci_table);
Linux kernel - Deliverables
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