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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2005-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
8ceee660 | 20 | #include <linux/ethtool.h> |
aa6ef27e | 21 | #include <linux/topology.h> |
5a0e3ad6 | 22 | #include <linux/gfp.h> |
626950db | 23 | #include <linux/aer.h> |
b28405b0 | 24 | #include <linux/interrupt.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
dd40781e | 28 | #include "selftest.h" |
8ceee660 | 29 | |
8880f4ec | 30 | #include "mcdi.h" |
fd371e32 | 31 | #include "workarounds.h" |
8880f4ec | 32 | |
c459302d BH |
33 | /************************************************************************** |
34 | * | |
35 | * Type name strings | |
36 | * | |
37 | ************************************************************************** | |
38 | */ | |
39 | ||
40 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
41 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 42 | const char *const efx_loopback_mode_names[] = { |
c459302d | 43 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 44 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
45 | [LOOPBACK_GMAC] = "GMAC", |
46 | [LOOPBACK_XGMII] = "XGMII", | |
47 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
48 | [LOOPBACK_XAUI] = "XAUI", |
49 | [LOOPBACK_GMII] = "GMII", | |
50 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
51 | [LOOPBACK_XGBR] = "XGBR", |
52 | [LOOPBACK_XFI] = "XFI", | |
53 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
54 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
55 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
56 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
57 | [LOOPBACK_GPHY] = "GPHY", |
58 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
59 | [LOOPBACK_PCS] = "PCS", |
60 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
61 | [LOOPBACK_XPORT] = "XPORT", |
62 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 63 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
64 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
65 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 66 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
67 | [LOOPBACK_XFI_WS] = "XFI_WS", |
68 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 69 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
70 | }; |
71 | ||
c459302d | 72 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 73 | const char *const efx_reset_type_names[] = { |
626950db AR |
74 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
75 | [RESET_TYPE_ALL] = "ALL", | |
76 | [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL", | |
77 | [RESET_TYPE_WORLD] = "WORLD", | |
78 | [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE", | |
79 | [RESET_TYPE_DISABLE] = "DISABLE", | |
80 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
81 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
82 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
3de82b91 | 83 | [RESET_TYPE_DMA_ERROR] = "DMA_ERROR", |
626950db AR |
84 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", |
85 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", | |
74cd60a4 | 86 | [RESET_TYPE_MC_BIST] = "MC_BIST", |
c459302d BH |
87 | }; |
88 | ||
1ab00629 SH |
89 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
90 | * queued onto this work queue. This is not a per-nic work queue, because | |
91 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
92 | */ | |
93 | static struct workqueue_struct *reset_workqueue; | |
94 | ||
74cd60a4 JC |
95 | /* How often and how many times to poll for a reset while waiting for a |
96 | * BIST that another function started to complete. | |
97 | */ | |
98 | #define BIST_WAIT_DELAY_MS 100 | |
99 | #define BIST_WAIT_DELAY_COUNT 100 | |
100 | ||
8ceee660 BH |
101 | /************************************************************************** |
102 | * | |
103 | * Configurable values | |
104 | * | |
105 | *************************************************************************/ | |
106 | ||
8ceee660 BH |
107 | /* |
108 | * Use separate channels for TX and RX events | |
109 | * | |
28b581ab NT |
110 | * Set this to 1 to use separate channels for TX and RX. It allows us |
111 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 112 | * |
28b581ab | 113 | * This is only used in MSI-X interrupt mode |
8ceee660 | 114 | */ |
b9cc977d BH |
115 | static bool separate_tx_channels; |
116 | module_param(separate_tx_channels, bool, 0444); | |
28b581ab NT |
117 | MODULE_PARM_DESC(separate_tx_channels, |
118 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
119 | |
120 | /* This is the weight assigned to each of the (per-channel) virtual | |
121 | * NAPI devices. | |
122 | */ | |
123 | static int napi_weight = 64; | |
124 | ||
125 | /* This is the time (in jiffies) between invocations of the hardware | |
626950db AR |
126 | * monitor. |
127 | * On Falcon-based NICs, this will: | |
e254c274 BH |
128 | * - Check the on-board hardware monitor; |
129 | * - Poll the link state and reconfigure the hardware as necessary. | |
626950db AR |
130 | * On Siena-based NICs for power systems with EEH support, this will give EEH a |
131 | * chance to start. | |
8ceee660 | 132 | */ |
d215697f | 133 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 134 | |
8ceee660 BH |
135 | /* Initial interrupt moderation settings. They can be modified after |
136 | * module load with ethtool. | |
137 | * | |
138 | * The default for RX should strike a balance between increasing the | |
139 | * round-trip latency and reducing overhead. | |
140 | */ | |
141 | static unsigned int rx_irq_mod_usec = 60; | |
142 | ||
143 | /* Initial interrupt moderation settings. They can be modified after | |
144 | * module load with ethtool. | |
145 | * | |
146 | * This default is chosen to ensure that a 10G link does not go idle | |
147 | * while a TX queue is stopped after it has become full. A queue is | |
148 | * restarted when it drops below half full. The time this takes (assuming | |
149 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
150 | * 512 / 3 * 1.2 = 205 usec. | |
151 | */ | |
152 | static unsigned int tx_irq_mod_usec = 150; | |
153 | ||
154 | /* This is the first interrupt mode to try out of: | |
155 | * 0 => MSI-X | |
156 | * 1 => MSI | |
157 | * 2 => legacy | |
158 | */ | |
159 | static unsigned int interrupt_mode; | |
160 | ||
161 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
162 | * i.e. the number of CPUs among which we may distribute simultaneous | |
163 | * interrupt handling. | |
164 | * | |
165 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 166 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
167 | */ |
168 | static unsigned int rss_cpus; | |
169 | module_param(rss_cpus, uint, 0444); | |
170 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
171 | ||
b9cc977d BH |
172 | static bool phy_flash_cfg; |
173 | module_param(phy_flash_cfg, bool, 0644); | |
84ae48fe BH |
174 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); |
175 | ||
e7bed9c8 | 176 | static unsigned irq_adapt_low_thresh = 8000; |
6fb70fd1 BH |
177 | module_param(irq_adapt_low_thresh, uint, 0644); |
178 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
179 | "Threshold score for reducing IRQ moderation"); | |
180 | ||
e7bed9c8 | 181 | static unsigned irq_adapt_high_thresh = 16000; |
6fb70fd1 BH |
182 | module_param(irq_adapt_high_thresh, uint, 0644); |
183 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
184 | "Threshold score for increasing IRQ moderation"); | |
185 | ||
62776d03 BH |
186 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
187 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
188 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
189 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
190 | module_param(debug, uint, 0); | |
191 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
192 | ||
8ceee660 BH |
193 | /************************************************************************** |
194 | * | |
195 | * Utility functions and prototypes | |
196 | * | |
197 | *************************************************************************/ | |
4642610c | 198 | |
261e4d96 | 199 | static int efx_soft_enable_interrupts(struct efx_nic *efx); |
d8291187 | 200 | static void efx_soft_disable_interrupts(struct efx_nic *efx); |
7f967c01 | 201 | static void efx_remove_channel(struct efx_channel *channel); |
4642610c | 202 | static void efx_remove_channels(struct efx_nic *efx); |
7f967c01 | 203 | static const struct efx_channel_type efx_default_channel_type; |
8ceee660 | 204 | static void efx_remove_port(struct efx_nic *efx); |
7f967c01 | 205 | static void efx_init_napi_channel(struct efx_channel *channel); |
8ceee660 | 206 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 207 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
208 | static void efx_fini_struct(struct efx_nic *efx); |
209 | static void efx_start_all(struct efx_nic *efx); | |
210 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
211 | |
212 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
213 | do { \ | |
f16aeea0 | 214 | if ((efx->state == STATE_READY) || \ |
626950db | 215 | (efx->state == STATE_RECOVERY) || \ |
332c1ce9 | 216 | (efx->state == STATE_DISABLED)) \ |
8ceee660 BH |
217 | ASSERT_RTNL(); \ |
218 | } while (0) | |
219 | ||
8b7325b4 BH |
220 | static int efx_check_disabled(struct efx_nic *efx) |
221 | { | |
626950db | 222 | if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) { |
8b7325b4 BH |
223 | netif_err(efx, drv, efx->net_dev, |
224 | "device is disabled due to earlier errors\n"); | |
225 | return -EIO; | |
226 | } | |
227 | return 0; | |
228 | } | |
229 | ||
8ceee660 BH |
230 | /************************************************************************** |
231 | * | |
232 | * Event queue processing | |
233 | * | |
234 | *************************************************************************/ | |
235 | ||
236 | /* Process channel's event queue | |
237 | * | |
238 | * This function is responsible for processing the event queue of a | |
239 | * single channel. The caller must guarantee that this function will | |
240 | * never be concurrently called more than once on the same channel, | |
241 | * though different channels may be being processed concurrently. | |
242 | */ | |
fa236e18 | 243 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 244 | { |
fa236e18 | 245 | int spent; |
8ceee660 | 246 | |
9f2cb71c | 247 | if (unlikely(!channel->enabled)) |
42cbe2d7 | 248 | return 0; |
8ceee660 | 249 | |
fa236e18 | 250 | spent = efx_nic_process_eventq(channel, budget); |
d9ab7007 BH |
251 | if (spent && efx_channel_has_rx_queue(channel)) { |
252 | struct efx_rx_queue *rx_queue = | |
253 | efx_channel_get_rx_queue(channel); | |
254 | ||
ff734ef4 | 255 | efx_rx_flush_packet(channel); |
cce28794 | 256 | efx_fast_push_rx_descriptors(rx_queue, true); |
8ceee660 BH |
257 | } |
258 | ||
fa236e18 | 259 | return spent; |
8ceee660 BH |
260 | } |
261 | ||
8ceee660 BH |
262 | /* NAPI poll handler |
263 | * | |
264 | * NAPI guarantees serialisation of polls of the same device, which | |
265 | * provides the guarantee required by efx_process_channel(). | |
266 | */ | |
267 | static int efx_poll(struct napi_struct *napi, int budget) | |
268 | { | |
269 | struct efx_channel *channel = | |
270 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 271 | struct efx_nic *efx = channel->efx; |
fa236e18 | 272 | int spent; |
8ceee660 | 273 | |
62776d03 BH |
274 | netif_vdbg(efx, intr, efx->net_dev, |
275 | "channel %d NAPI poll executing on CPU %d\n", | |
276 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 277 | |
fa236e18 | 278 | spent = efx_process_channel(channel, budget); |
8ceee660 | 279 | |
fa236e18 | 280 | if (spent < budget) { |
9d9a6973 | 281 | if (efx_channel_has_rx_queue(channel) && |
6fb70fd1 BH |
282 | efx->irq_rx_adaptive && |
283 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
284 | if (unlikely(channel->irq_mod_score < |
285 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
286 | if (channel->irq_moderation > 1) { |
287 | channel->irq_moderation -= 1; | |
ef2b90ee | 288 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 289 | } |
6fb70fd1 BH |
290 | } else if (unlikely(channel->irq_mod_score > |
291 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
292 | if (channel->irq_moderation < |
293 | efx->irq_rx_moderation) { | |
294 | channel->irq_moderation += 1; | |
ef2b90ee | 295 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 296 | } |
6fb70fd1 | 297 | } |
6fb70fd1 BH |
298 | channel->irq_count = 0; |
299 | channel->irq_mod_score = 0; | |
300 | } | |
301 | ||
64d8ad6d BH |
302 | efx_filter_rfs_expire(channel); |
303 | ||
8ceee660 | 304 | /* There is no race here; although napi_disable() will |
288379f0 | 305 | * only wait for napi_complete(), this isn't a problem |
514bedbc | 306 | * since efx_nic_eventq_read_ack() will have no effect if |
8ceee660 BH |
307 | * interrupts have already been disabled. |
308 | */ | |
288379f0 | 309 | napi_complete(napi); |
514bedbc | 310 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
311 | } |
312 | ||
fa236e18 | 313 | return spent; |
8ceee660 BH |
314 | } |
315 | ||
8ceee660 BH |
316 | /* Create event queue |
317 | * Event queue memory allocations are done only once. If the channel | |
318 | * is reset, the memory buffer will be reused; this guards against | |
319 | * errors during channel reset and also simplifies interrupt handling. | |
320 | */ | |
321 | static int efx_probe_eventq(struct efx_channel *channel) | |
322 | { | |
ecc910f5 SH |
323 | struct efx_nic *efx = channel->efx; |
324 | unsigned long entries; | |
325 | ||
86ee5302 | 326 | netif_dbg(efx, probe, efx->net_dev, |
62776d03 | 327 | "chan %d create event queue\n", channel->channel); |
8ceee660 | 328 | |
ecc910f5 SH |
329 | /* Build an event queue with room for one event per tx and rx buffer, |
330 | * plus some extra for link state events and MCDI completions. */ | |
331 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
332 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
333 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
334 | ||
152b6a62 | 335 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
336 | } |
337 | ||
338 | /* Prepare channel's event queue */ | |
261e4d96 | 339 | static int efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 340 | { |
15acb1ce | 341 | struct efx_nic *efx = channel->efx; |
261e4d96 JC |
342 | int rc; |
343 | ||
344 | EFX_WARN_ON_PARANOID(channel->eventq_init); | |
345 | ||
15acb1ce | 346 | netif_dbg(efx, drv, efx->net_dev, |
62776d03 | 347 | "chan %d init event queue\n", channel->channel); |
8ceee660 | 348 | |
261e4d96 JC |
349 | rc = efx_nic_init_eventq(channel); |
350 | if (rc == 0) { | |
15acb1ce | 351 | efx->type->push_irq_moderation(channel); |
261e4d96 JC |
352 | channel->eventq_read_ptr = 0; |
353 | channel->eventq_init = true; | |
354 | } | |
355 | return rc; | |
8ceee660 BH |
356 | } |
357 | ||
9f2cb71c BH |
358 | /* Enable event queue processing and NAPI */ |
359 | static void efx_start_eventq(struct efx_channel *channel) | |
360 | { | |
361 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, | |
362 | "chan %d start event queue\n", channel->channel); | |
363 | ||
514bedbc | 364 | /* Make sure the NAPI handler sees the enabled flag set */ |
9f2cb71c BH |
365 | channel->enabled = true; |
366 | smp_wmb(); | |
367 | ||
368 | napi_enable(&channel->napi_str); | |
369 | efx_nic_eventq_read_ack(channel); | |
370 | } | |
371 | ||
372 | /* Disable event queue processing and NAPI */ | |
373 | static void efx_stop_eventq(struct efx_channel *channel) | |
374 | { | |
375 | if (!channel->enabled) | |
376 | return; | |
377 | ||
378 | napi_disable(&channel->napi_str); | |
379 | channel->enabled = false; | |
380 | } | |
381 | ||
8ceee660 BH |
382 | static void efx_fini_eventq(struct efx_channel *channel) |
383 | { | |
be3fc09c BH |
384 | if (!channel->eventq_init) |
385 | return; | |
386 | ||
62776d03 BH |
387 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
388 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 389 | |
152b6a62 | 390 | efx_nic_fini_eventq(channel); |
be3fc09c | 391 | channel->eventq_init = false; |
8ceee660 BH |
392 | } |
393 | ||
394 | static void efx_remove_eventq(struct efx_channel *channel) | |
395 | { | |
62776d03 BH |
396 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
397 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 398 | |
152b6a62 | 399 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
400 | } |
401 | ||
402 | /************************************************************************** | |
403 | * | |
404 | * Channel handling | |
405 | * | |
406 | *************************************************************************/ | |
407 | ||
7f967c01 | 408 | /* Allocate and initialise a channel structure. */ |
4642610c BH |
409 | static struct efx_channel * |
410 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
411 | { | |
412 | struct efx_channel *channel; | |
413 | struct efx_rx_queue *rx_queue; | |
414 | struct efx_tx_queue *tx_queue; | |
415 | int j; | |
416 | ||
7f967c01 BH |
417 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); |
418 | if (!channel) | |
419 | return NULL; | |
4642610c | 420 | |
7f967c01 BH |
421 | channel->efx = efx; |
422 | channel->channel = i; | |
423 | channel->type = &efx_default_channel_type; | |
4642610c | 424 | |
7f967c01 BH |
425 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
426 | tx_queue = &channel->tx_queue[j]; | |
427 | tx_queue->efx = efx; | |
428 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
429 | tx_queue->channel = channel; | |
430 | } | |
4642610c | 431 | |
7f967c01 BH |
432 | rx_queue = &channel->rx_queue; |
433 | rx_queue->efx = efx; | |
434 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
435 | (unsigned long)rx_queue); | |
4642610c | 436 | |
7f967c01 BH |
437 | return channel; |
438 | } | |
439 | ||
440 | /* Allocate and initialise a channel structure, copying parameters | |
441 | * (but not resources) from an old channel structure. | |
442 | */ | |
443 | static struct efx_channel * | |
444 | efx_copy_channel(const struct efx_channel *old_channel) | |
445 | { | |
446 | struct efx_channel *channel; | |
447 | struct efx_rx_queue *rx_queue; | |
448 | struct efx_tx_queue *tx_queue; | |
449 | int j; | |
4642610c | 450 | |
7f967c01 BH |
451 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); |
452 | if (!channel) | |
453 | return NULL; | |
454 | ||
455 | *channel = *old_channel; | |
456 | ||
457 | channel->napi_dev = NULL; | |
458 | memset(&channel->eventq, 0, sizeof(channel->eventq)); | |
4642610c | 459 | |
7f967c01 BH |
460 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
461 | tx_queue = &channel->tx_queue[j]; | |
462 | if (tx_queue->channel) | |
4642610c | 463 | tx_queue->channel = channel; |
7f967c01 BH |
464 | tx_queue->buffer = NULL; |
465 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
4642610c BH |
466 | } |
467 | ||
4642610c | 468 | rx_queue = &channel->rx_queue; |
7f967c01 BH |
469 | rx_queue->buffer = NULL; |
470 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
4642610c BH |
471 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
472 | (unsigned long)rx_queue); | |
473 | ||
474 | return channel; | |
475 | } | |
476 | ||
8ceee660 BH |
477 | static int efx_probe_channel(struct efx_channel *channel) |
478 | { | |
479 | struct efx_tx_queue *tx_queue; | |
480 | struct efx_rx_queue *rx_queue; | |
481 | int rc; | |
482 | ||
62776d03 BH |
483 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
484 | "creating channel %d\n", channel->channel); | |
8ceee660 | 485 | |
7f967c01 BH |
486 | rc = channel->type->pre_probe(channel); |
487 | if (rc) | |
488 | goto fail; | |
489 | ||
8ceee660 BH |
490 | rc = efx_probe_eventq(channel); |
491 | if (rc) | |
7f967c01 | 492 | goto fail; |
8ceee660 BH |
493 | |
494 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
495 | rc = efx_probe_tx_queue(tx_queue); | |
496 | if (rc) | |
7f967c01 | 497 | goto fail; |
8ceee660 BH |
498 | } |
499 | ||
500 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
501 | rc = efx_probe_rx_queue(rx_queue); | |
502 | if (rc) | |
7f967c01 | 503 | goto fail; |
8ceee660 BH |
504 | } |
505 | ||
506 | channel->n_rx_frm_trunc = 0; | |
507 | ||
508 | return 0; | |
509 | ||
7f967c01 BH |
510 | fail: |
511 | efx_remove_channel(channel); | |
8ceee660 BH |
512 | return rc; |
513 | } | |
514 | ||
7f967c01 BH |
515 | static void |
516 | efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) | |
517 | { | |
518 | struct efx_nic *efx = channel->efx; | |
519 | const char *type; | |
520 | int number; | |
521 | ||
522 | number = channel->channel; | |
523 | if (efx->tx_channel_offset == 0) { | |
524 | type = ""; | |
525 | } else if (channel->channel < efx->tx_channel_offset) { | |
526 | type = "-rx"; | |
527 | } else { | |
528 | type = "-tx"; | |
529 | number -= efx->tx_channel_offset; | |
530 | } | |
531 | snprintf(buf, len, "%s%s-%d", efx->name, type, number); | |
532 | } | |
8ceee660 | 533 | |
56536e9c BH |
534 | static void efx_set_channel_names(struct efx_nic *efx) |
535 | { | |
536 | struct efx_channel *channel; | |
56536e9c | 537 | |
7f967c01 BH |
538 | efx_for_each_channel(channel, efx) |
539 | channel->type->get_name(channel, | |
d8291187 BH |
540 | efx->msi_context[channel->channel].name, |
541 | sizeof(efx->msi_context[0].name)); | |
56536e9c BH |
542 | } |
543 | ||
4642610c BH |
544 | static int efx_probe_channels(struct efx_nic *efx) |
545 | { | |
546 | struct efx_channel *channel; | |
547 | int rc; | |
548 | ||
549 | /* Restart special buffer allocation */ | |
550 | efx->next_buffer_table = 0; | |
551 | ||
c92aaff1 BH |
552 | /* Probe channels in reverse, so that any 'extra' channels |
553 | * use the start of the buffer table. This allows the traffic | |
554 | * channels to be resized without moving them or wasting the | |
555 | * entries before them. | |
556 | */ | |
557 | efx_for_each_channel_rev(channel, efx) { | |
4642610c BH |
558 | rc = efx_probe_channel(channel); |
559 | if (rc) { | |
560 | netif_err(efx, probe, efx->net_dev, | |
561 | "failed to create channel %d\n", | |
562 | channel->channel); | |
563 | goto fail; | |
564 | } | |
565 | } | |
566 | efx_set_channel_names(efx); | |
567 | ||
568 | return 0; | |
569 | ||
570 | fail: | |
571 | efx_remove_channels(efx); | |
572 | return rc; | |
573 | } | |
574 | ||
8ceee660 BH |
575 | /* Channels are shutdown and reinitialised whilst the NIC is running |
576 | * to propagate configuration changes (mtu, checksum offload), or | |
577 | * to clear hardware error conditions | |
578 | */ | |
9f2cb71c | 579 | static void efx_start_datapath(struct efx_nic *efx) |
8ceee660 | 580 | { |
85740cdf | 581 | bool old_rx_scatter = efx->rx_scatter; |
8ceee660 BH |
582 | struct efx_tx_queue *tx_queue; |
583 | struct efx_rx_queue *rx_queue; | |
584 | struct efx_channel *channel; | |
85740cdf | 585 | size_t rx_buf_len; |
8ceee660 | 586 | |
f7f13b0b BH |
587 | /* Calculate the rx buffer allocation parameters required to |
588 | * support the current MTU, including padding for header | |
589 | * alignment and overruns. | |
590 | */ | |
43a3739d | 591 | efx->rx_dma_len = (efx->rx_prefix_size + |
272baeeb BH |
592 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + |
593 | efx->type->rx_buffer_padding); | |
85740cdf | 594 | rx_buf_len = (sizeof(struct efx_rx_page_state) + |
2ec03014 | 595 | efx->rx_ip_align + efx->rx_dma_len); |
85740cdf | 596 | if (rx_buf_len <= PAGE_SIZE) { |
e8c68c0a | 597 | efx->rx_scatter = efx->type->always_rx_scatter; |
85740cdf | 598 | efx->rx_buffer_order = 0; |
85740cdf | 599 | } else if (efx->type->can_rx_scatter) { |
950c54df | 600 | BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES); |
85740cdf | 601 | BUILD_BUG_ON(sizeof(struct efx_rx_page_state) + |
950c54df BH |
602 | 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE, |
603 | EFX_RX_BUF_ALIGNMENT) > | |
604 | PAGE_SIZE); | |
85740cdf BH |
605 | efx->rx_scatter = true; |
606 | efx->rx_dma_len = EFX_RX_USR_BUF_SIZE; | |
607 | efx->rx_buffer_order = 0; | |
85740cdf BH |
608 | } else { |
609 | efx->rx_scatter = false; | |
610 | efx->rx_buffer_order = get_order(rx_buf_len); | |
85740cdf BH |
611 | } |
612 | ||
1648a23f DP |
613 | efx_rx_config_page_split(efx); |
614 | if (efx->rx_buffer_order) | |
615 | netif_dbg(efx, drv, efx->net_dev, | |
616 | "RX buf len=%u; page order=%u batch=%u\n", | |
617 | efx->rx_dma_len, efx->rx_buffer_order, | |
618 | efx->rx_pages_per_batch); | |
619 | else | |
620 | netif_dbg(efx, drv, efx->net_dev, | |
621 | "RX buf len=%u step=%u bpp=%u; page batch=%u\n", | |
622 | efx->rx_dma_len, efx->rx_page_buf_step, | |
623 | efx->rx_bufs_per_page, efx->rx_pages_per_batch); | |
2768935a | 624 | |
e8c68c0a | 625 | /* RX filters may also have scatter-enabled flags */ |
85740cdf | 626 | if (efx->rx_scatter != old_rx_scatter) |
add72477 | 627 | efx->type->filter_update_rx_scatter(efx); |
8ceee660 | 628 | |
14bf718f BH |
629 | /* We must keep at least one descriptor in a TX ring empty. |
630 | * We could avoid this when the queue size does not exactly | |
631 | * match the hardware ring size, but it's not that important. | |
632 | * Therefore we stop the queue when one more skb might fill | |
633 | * the ring completely. We wake it when half way back to | |
634 | * empty. | |
635 | */ | |
636 | efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); | |
637 | efx->txq_wake_thresh = efx->txq_stop_thresh / 2; | |
638 | ||
8ceee660 BH |
639 | /* Initialise the channels */ |
640 | efx_for_each_channel(channel, efx) { | |
3881d8ab | 641 | efx_for_each_channel_tx_queue(tx_queue, channel) { |
bc3c90a2 | 642 | efx_init_tx_queue(tx_queue); |
3881d8ab AR |
643 | atomic_inc(&efx->active_queues); |
644 | } | |
8ceee660 | 645 | |
9f2cb71c | 646 | efx_for_each_channel_rx_queue(rx_queue, channel) { |
bc3c90a2 | 647 | efx_init_rx_queue(rx_queue); |
3881d8ab | 648 | atomic_inc(&efx->active_queues); |
cce28794 JC |
649 | efx_stop_eventq(channel); |
650 | efx_fast_push_rx_descriptors(rx_queue, false); | |
651 | efx_start_eventq(channel); | |
9f2cb71c | 652 | } |
8ceee660 | 653 | |
85740cdf | 654 | WARN_ON(channel->rx_pkt_n_frags); |
8ceee660 | 655 | } |
8ceee660 | 656 | |
2ea4dc28 AR |
657 | efx_ptp_start_datapath(efx); |
658 | ||
9f2cb71c BH |
659 | if (netif_device_present(efx->net_dev)) |
660 | netif_tx_wake_all_queues(efx->net_dev); | |
8ceee660 BH |
661 | } |
662 | ||
9f2cb71c | 663 | static void efx_stop_datapath(struct efx_nic *efx) |
8ceee660 BH |
664 | { |
665 | struct efx_channel *channel; | |
666 | struct efx_tx_queue *tx_queue; | |
667 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 668 | int rc; |
8ceee660 BH |
669 | |
670 | EFX_ASSERT_RESET_SERIALISED(efx); | |
671 | BUG_ON(efx->port_enabled); | |
672 | ||
2ea4dc28 AR |
673 | efx_ptp_stop_datapath(efx); |
674 | ||
d8aec745 BH |
675 | /* Stop RX refill */ |
676 | efx_for_each_channel(channel, efx) { | |
677 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
678 | rx_queue->refill_enabled = false; | |
679 | } | |
680 | ||
8ceee660 | 681 | efx_for_each_channel(channel, efx) { |
9f2cb71c BH |
682 | /* RX packet processing is pipelined, so wait for the |
683 | * NAPI handler to complete. At least event queue 0 | |
684 | * might be kept active by non-data events, so don't | |
685 | * use napi_synchronize() but actually disable NAPI | |
686 | * temporarily. | |
687 | */ | |
688 | if (efx_channel_has_rx_queue(channel)) { | |
689 | efx_stop_eventq(channel); | |
690 | efx_start_eventq(channel); | |
691 | } | |
e42c3d85 | 692 | } |
8ceee660 | 693 | |
e42c3d85 BH |
694 | rc = efx->type->fini_dmaq(efx); |
695 | if (rc && EFX_WORKAROUND_7803(efx)) { | |
696 | /* Schedule a reset to recover from the flush failure. The | |
697 | * descriptor caches reference memory we're about to free, | |
698 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
699 | * the MACs because of the pending reset. | |
700 | */ | |
701 | netif_err(efx, drv, efx->net_dev, | |
702 | "Resetting to recover from flush failure\n"); | |
703 | efx_schedule_reset(efx, RESET_TYPE_ALL); | |
704 | } else if (rc) { | |
705 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); | |
706 | } else { | |
707 | netif_dbg(efx, drv, efx->net_dev, | |
708 | "successfully flushed all queues\n"); | |
709 | } | |
710 | ||
711 | efx_for_each_channel(channel, efx) { | |
8ceee660 BH |
712 | efx_for_each_channel_rx_queue(rx_queue, channel) |
713 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 714 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 715 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
716 | } |
717 | } | |
718 | ||
719 | static void efx_remove_channel(struct efx_channel *channel) | |
720 | { | |
721 | struct efx_tx_queue *tx_queue; | |
722 | struct efx_rx_queue *rx_queue; | |
723 | ||
62776d03 BH |
724 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
725 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
726 | |
727 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
728 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 729 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
730 | efx_remove_tx_queue(tx_queue); |
731 | efx_remove_eventq(channel); | |
c31e5f9f | 732 | channel->type->post_remove(channel); |
8ceee660 BH |
733 | } |
734 | ||
4642610c BH |
735 | static void efx_remove_channels(struct efx_nic *efx) |
736 | { | |
737 | struct efx_channel *channel; | |
738 | ||
739 | efx_for_each_channel(channel, efx) | |
740 | efx_remove_channel(channel); | |
741 | } | |
742 | ||
743 | int | |
744 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
745 | { | |
746 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
747 | u32 old_rxq_entries, old_txq_entries; | |
7f967c01 | 748 | unsigned i, next_buffer_table = 0; |
261e4d96 | 749 | int rc, rc2; |
8b7325b4 BH |
750 | |
751 | rc = efx_check_disabled(efx); | |
752 | if (rc) | |
753 | return rc; | |
7f967c01 BH |
754 | |
755 | /* Not all channels should be reallocated. We must avoid | |
756 | * reallocating their buffer table entries. | |
757 | */ | |
758 | efx_for_each_channel(channel, efx) { | |
759 | struct efx_rx_queue *rx_queue; | |
760 | struct efx_tx_queue *tx_queue; | |
761 | ||
762 | if (channel->type->copy) | |
763 | continue; | |
764 | next_buffer_table = max(next_buffer_table, | |
765 | channel->eventq.index + | |
766 | channel->eventq.entries); | |
767 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
768 | next_buffer_table = max(next_buffer_table, | |
769 | rx_queue->rxd.index + | |
770 | rx_queue->rxd.entries); | |
771 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
772 | next_buffer_table = max(next_buffer_table, | |
773 | tx_queue->txd.index + | |
774 | tx_queue->txd.entries); | |
775 | } | |
4642610c | 776 | |
29c69a48 | 777 | efx_device_detach_sync(efx); |
4642610c | 778 | efx_stop_all(efx); |
d8291187 | 779 | efx_soft_disable_interrupts(efx); |
4642610c | 780 | |
7f967c01 | 781 | /* Clone channels (where possible) */ |
4642610c BH |
782 | memset(other_channel, 0, sizeof(other_channel)); |
783 | for (i = 0; i < efx->n_channels; i++) { | |
7f967c01 BH |
784 | channel = efx->channel[i]; |
785 | if (channel->type->copy) | |
786 | channel = channel->type->copy(channel); | |
4642610c BH |
787 | if (!channel) { |
788 | rc = -ENOMEM; | |
789 | goto out; | |
790 | } | |
791 | other_channel[i] = channel; | |
792 | } | |
793 | ||
794 | /* Swap entry counts and channel pointers */ | |
795 | old_rxq_entries = efx->rxq_entries; | |
796 | old_txq_entries = efx->txq_entries; | |
797 | efx->rxq_entries = rxq_entries; | |
798 | efx->txq_entries = txq_entries; | |
799 | for (i = 0; i < efx->n_channels; i++) { | |
800 | channel = efx->channel[i]; | |
801 | efx->channel[i] = other_channel[i]; | |
802 | other_channel[i] = channel; | |
803 | } | |
804 | ||
7f967c01 BH |
805 | /* Restart buffer table allocation */ |
806 | efx->next_buffer_table = next_buffer_table; | |
e8f14992 | 807 | |
e8f14992 | 808 | for (i = 0; i < efx->n_channels; i++) { |
7f967c01 BH |
809 | channel = efx->channel[i]; |
810 | if (!channel->type->copy) | |
811 | continue; | |
812 | rc = efx_probe_channel(channel); | |
813 | if (rc) | |
814 | goto rollback; | |
815 | efx_init_napi_channel(efx->channel[i]); | |
e8f14992 | 816 | } |
7f967c01 | 817 | |
4642610c | 818 | out: |
7f967c01 BH |
819 | /* Destroy unused channel structures */ |
820 | for (i = 0; i < efx->n_channels; i++) { | |
821 | channel = other_channel[i]; | |
822 | if (channel && channel->type->copy) { | |
823 | efx_fini_napi_channel(channel); | |
824 | efx_remove_channel(channel); | |
825 | kfree(channel); | |
826 | } | |
827 | } | |
4642610c | 828 | |
261e4d96 JC |
829 | rc2 = efx_soft_enable_interrupts(efx); |
830 | if (rc2) { | |
831 | rc = rc ? rc : rc2; | |
832 | netif_err(efx, drv, efx->net_dev, | |
833 | "unable to restart interrupts on channel reallocation\n"); | |
834 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
835 | } else { | |
836 | efx_start_all(efx); | |
837 | netif_device_attach(efx->net_dev); | |
838 | } | |
4642610c BH |
839 | return rc; |
840 | ||
841 | rollback: | |
842 | /* Swap back */ | |
843 | efx->rxq_entries = old_rxq_entries; | |
844 | efx->txq_entries = old_txq_entries; | |
845 | for (i = 0; i < efx->n_channels; i++) { | |
846 | channel = efx->channel[i]; | |
847 | efx->channel[i] = other_channel[i]; | |
848 | other_channel[i] = channel; | |
849 | } | |
850 | goto out; | |
851 | } | |
852 | ||
90d683af | 853 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 854 | { |
90d683af | 855 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
856 | } |
857 | ||
7f967c01 BH |
858 | static const struct efx_channel_type efx_default_channel_type = { |
859 | .pre_probe = efx_channel_dummy_op_int, | |
c31e5f9f | 860 | .post_remove = efx_channel_dummy_op_void, |
7f967c01 BH |
861 | .get_name = efx_get_channel_name, |
862 | .copy = efx_copy_channel, | |
863 | .keep_eventq = false, | |
864 | }; | |
865 | ||
866 | int efx_channel_dummy_op_int(struct efx_channel *channel) | |
867 | { | |
868 | return 0; | |
869 | } | |
870 | ||
c31e5f9f SH |
871 | void efx_channel_dummy_op_void(struct efx_channel *channel) |
872 | { | |
873 | } | |
874 | ||
8ceee660 BH |
875 | /************************************************************************** |
876 | * | |
877 | * Port handling | |
878 | * | |
879 | **************************************************************************/ | |
880 | ||
881 | /* This ensures that the kernel is kept informed (via | |
882 | * netif_carrier_on/off) of the link status, and also maintains the | |
883 | * link status's stop on the port's TX queue. | |
884 | */ | |
fdaa9aed | 885 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 886 | { |
eb50c0d6 BH |
887 | struct efx_link_state *link_state = &efx->link_state; |
888 | ||
8ceee660 BH |
889 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
890 | * that no events are triggered between unregister_netdev() and the | |
891 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
892 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
893 | if (!netif_running(efx->net_dev)) | |
894 | return; | |
895 | ||
eb50c0d6 | 896 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
897 | efx->n_link_state_changes++; |
898 | ||
eb50c0d6 | 899 | if (link_state->up) |
8ceee660 BH |
900 | netif_carrier_on(efx->net_dev); |
901 | else | |
902 | netif_carrier_off(efx->net_dev); | |
903 | } | |
904 | ||
905 | /* Status message for kernel log */ | |
2aa9ef11 | 906 | if (link_state->up) |
62776d03 | 907 | netif_info(efx, link, efx->net_dev, |
964e6135 | 908 | "link up at %uMbps %s-duplex (MTU %d)\n", |
62776d03 | 909 | link_state->speed, link_state->fd ? "full" : "half", |
964e6135 | 910 | efx->net_dev->mtu); |
2aa9ef11 | 911 | else |
62776d03 | 912 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
913 | } |
914 | ||
d3245b28 BH |
915 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
916 | { | |
917 | efx->link_advertising = advertising; | |
918 | if (advertising) { | |
919 | if (advertising & ADVERTISED_Pause) | |
920 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
921 | else | |
922 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
923 | if (advertising & ADVERTISED_Asym_Pause) | |
924 | efx->wanted_fc ^= EFX_FC_TX; | |
925 | } | |
926 | } | |
927 | ||
b5626946 | 928 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
929 | { |
930 | efx->wanted_fc = wanted_fc; | |
931 | if (efx->link_advertising) { | |
932 | if (wanted_fc & EFX_FC_RX) | |
933 | efx->link_advertising |= (ADVERTISED_Pause | | |
934 | ADVERTISED_Asym_Pause); | |
935 | else | |
936 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
937 | ADVERTISED_Asym_Pause); | |
938 | if (wanted_fc & EFX_FC_TX) | |
939 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
940 | } | |
941 | } | |
942 | ||
115122af BH |
943 | static void efx_fini_port(struct efx_nic *efx); |
944 | ||
d3245b28 BH |
945 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
946 | * the MAC appropriately. All other PHY configuration changes are pushed | |
947 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
948 | * through efx_monitor(). | |
949 | * | |
950 | * Callers must hold the mac_lock | |
951 | */ | |
952 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 953 | { |
d3245b28 BH |
954 | enum efx_phy_mode phy_mode; |
955 | int rc; | |
8ceee660 | 956 | |
d3245b28 | 957 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 958 | |
d3245b28 BH |
959 | /* Disable PHY transmit in mac level loopbacks */ |
960 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
961 | if (LOOPBACK_INTERNAL(efx)) |
962 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
963 | else | |
964 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 965 | |
d3245b28 | 966 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 967 | |
d3245b28 BH |
968 | if (rc) |
969 | efx->phy_mode = phy_mode; | |
177dfcd8 | 970 | |
d3245b28 | 971 | return rc; |
8ceee660 BH |
972 | } |
973 | ||
974 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
975 | * disabled. */ | |
d3245b28 | 976 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 977 | { |
d3245b28 BH |
978 | int rc; |
979 | ||
8ceee660 BH |
980 | EFX_ASSERT_RESET_SERIALISED(efx); |
981 | ||
982 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 983 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 984 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
985 | |
986 | return rc; | |
8ceee660 BH |
987 | } |
988 | ||
8be4f3e6 BH |
989 | /* Asynchronous work item for changing MAC promiscuity and multicast |
990 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
991 | * MAC directly. */ | |
766ca0fa BH |
992 | static void efx_mac_work(struct work_struct *data) |
993 | { | |
994 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
995 | ||
996 | mutex_lock(&efx->mac_lock); | |
30b81cda | 997 | if (efx->port_enabled) |
710b208d | 998 | efx->type->reconfigure_mac(efx); |
766ca0fa BH |
999 | mutex_unlock(&efx->mac_lock); |
1000 | } | |
1001 | ||
8ceee660 BH |
1002 | static int efx_probe_port(struct efx_nic *efx) |
1003 | { | |
1004 | int rc; | |
1005 | ||
62776d03 | 1006 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 1007 | |
ff3b00a0 SH |
1008 | if (phy_flash_cfg) |
1009 | efx->phy_mode = PHY_MODE_SPECIAL; | |
1010 | ||
ef2b90ee BH |
1011 | /* Connect up MAC/PHY operations table */ |
1012 | rc = efx->type->probe_port(efx); | |
8ceee660 | 1013 | if (rc) |
e42de262 | 1014 | return rc; |
8ceee660 | 1015 | |
e332bcb3 BH |
1016 | /* Initialise MAC address to permanent address */ |
1017 | memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN); | |
8ceee660 BH |
1018 | |
1019 | return 0; | |
8ceee660 BH |
1020 | } |
1021 | ||
1022 | static int efx_init_port(struct efx_nic *efx) | |
1023 | { | |
1024 | int rc; | |
1025 | ||
62776d03 | 1026 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 1027 | |
1dfc5cea BH |
1028 | mutex_lock(&efx->mac_lock); |
1029 | ||
177dfcd8 | 1030 | rc = efx->phy_op->init(efx); |
8ceee660 | 1031 | if (rc) |
1dfc5cea | 1032 | goto fail1; |
8ceee660 | 1033 | |
dc8cfa55 | 1034 | efx->port_initialized = true; |
1dfc5cea | 1035 | |
d3245b28 BH |
1036 | /* Reconfigure the MAC before creating dma queues (required for |
1037 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
710b208d | 1038 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1039 | |
1040 | /* Ensure the PHY advertises the correct flow control settings */ | |
1041 | rc = efx->phy_op->reconfigure(efx); | |
1042 | if (rc) | |
1043 | goto fail2; | |
1044 | ||
1dfc5cea | 1045 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 1046 | return 0; |
177dfcd8 | 1047 | |
1dfc5cea | 1048 | fail2: |
177dfcd8 | 1049 | efx->phy_op->fini(efx); |
1dfc5cea BH |
1050 | fail1: |
1051 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 1052 | return rc; |
8ceee660 BH |
1053 | } |
1054 | ||
8ceee660 BH |
1055 | static void efx_start_port(struct efx_nic *efx) |
1056 | { | |
62776d03 | 1057 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
1058 | BUG_ON(efx->port_enabled); |
1059 | ||
1060 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1061 | efx->port_enabled = true; |
8be4f3e6 | 1062 | |
d615c039 | 1063 | /* Ensure MAC ingress/egress is enabled */ |
710b208d | 1064 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 1065 | |
8ceee660 BH |
1066 | mutex_unlock(&efx->mac_lock); |
1067 | } | |
1068 | ||
d615c039 BH |
1069 | /* Cancel work for MAC reconfiguration, periodic hardware monitoring |
1070 | * and the async self-test, wait for them to finish and prevent them | |
1071 | * being scheduled again. This doesn't cover online resets, which | |
1072 | * should only be cancelled when removing the device. | |
1073 | */ | |
8ceee660 BH |
1074 | static void efx_stop_port(struct efx_nic *efx) |
1075 | { | |
62776d03 | 1076 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 | 1077 | |
d615c039 BH |
1078 | EFX_ASSERT_RESET_SERIALISED(efx); |
1079 | ||
8ceee660 | 1080 | mutex_lock(&efx->mac_lock); |
dc8cfa55 | 1081 | efx->port_enabled = false; |
8ceee660 BH |
1082 | mutex_unlock(&efx->mac_lock); |
1083 | ||
1084 | /* Serialise against efx_set_multicast_list() */ | |
73ba7b68 BH |
1085 | netif_addr_lock_bh(efx->net_dev); |
1086 | netif_addr_unlock_bh(efx->net_dev); | |
d615c039 BH |
1087 | |
1088 | cancel_delayed_work_sync(&efx->monitor_work); | |
1089 | efx_selftest_async_cancel(efx); | |
1090 | cancel_work_sync(&efx->mac_work); | |
8ceee660 BH |
1091 | } |
1092 | ||
1093 | static void efx_fini_port(struct efx_nic *efx) | |
1094 | { | |
62776d03 | 1095 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1096 | |
1097 | if (!efx->port_initialized) | |
1098 | return; | |
1099 | ||
177dfcd8 | 1100 | efx->phy_op->fini(efx); |
dc8cfa55 | 1101 | efx->port_initialized = false; |
8ceee660 | 1102 | |
eb50c0d6 | 1103 | efx->link_state.up = false; |
8ceee660 BH |
1104 | efx_link_status_changed(efx); |
1105 | } | |
1106 | ||
1107 | static void efx_remove_port(struct efx_nic *efx) | |
1108 | { | |
62776d03 | 1109 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1110 | |
ef2b90ee | 1111 | efx->type->remove_port(efx); |
8ceee660 BH |
1112 | } |
1113 | ||
1114 | /************************************************************************** | |
1115 | * | |
1116 | * NIC handling | |
1117 | * | |
1118 | **************************************************************************/ | |
1119 | ||
1120 | /* This configures the PCI device to enable I/O and DMA. */ | |
1121 | static int efx_init_io(struct efx_nic *efx) | |
1122 | { | |
1123 | struct pci_dev *pci_dev = efx->pci_dev; | |
1124 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
b105798f | 1125 | unsigned int mem_map_size = efx->type->mem_map_size(efx); |
8ceee660 BH |
1126 | int rc; |
1127 | ||
62776d03 | 1128 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1129 | |
1130 | rc = pci_enable_device(pci_dev); | |
1131 | if (rc) { | |
62776d03 BH |
1132 | netif_err(efx, probe, efx->net_dev, |
1133 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1134 | goto fail1; |
1135 | } | |
1136 | ||
1137 | pci_set_master(pci_dev); | |
1138 | ||
1139 | /* Set the PCI DMA mask. Try all possibilities from our | |
1140 | * genuine mask down to 32 bits, because some architectures | |
1141 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1142 | * masks event though they reject 46 bit masks. | |
1143 | */ | |
1144 | while (dma_mask > 0x7fffffffUL) { | |
0e33d870 | 1145 | if (dma_supported(&pci_dev->dev, dma_mask)) { |
9663deda | 1146 | rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask); |
e9e01846 BH |
1147 | if (rc == 0) |
1148 | break; | |
1149 | } | |
8ceee660 BH |
1150 | dma_mask >>= 1; |
1151 | } | |
1152 | if (rc) { | |
62776d03 BH |
1153 | netif_err(efx, probe, efx->net_dev, |
1154 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1155 | goto fail2; |
1156 | } | |
62776d03 BH |
1157 | netif_dbg(efx, probe, efx->net_dev, |
1158 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 | 1159 | |
dc803df8 BH |
1160 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1161 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1162 | if (rc) { |
62776d03 BH |
1163 | netif_err(efx, probe, efx->net_dev, |
1164 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1165 | rc = -EIO; |
1166 | goto fail3; | |
1167 | } | |
b105798f | 1168 | efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size); |
8ceee660 | 1169 | if (!efx->membase) { |
62776d03 BH |
1170 | netif_err(efx, probe, efx->net_dev, |
1171 | "could not map memory BAR at %llx+%x\n", | |
b105798f | 1172 | (unsigned long long)efx->membase_phys, mem_map_size); |
8ceee660 BH |
1173 | rc = -ENOMEM; |
1174 | goto fail4; | |
1175 | } | |
62776d03 BH |
1176 | netif_dbg(efx, probe, efx->net_dev, |
1177 | "memory BAR at %llx+%x (virtual %p)\n", | |
b105798f BH |
1178 | (unsigned long long)efx->membase_phys, mem_map_size, |
1179 | efx->membase); | |
8ceee660 BH |
1180 | |
1181 | return 0; | |
1182 | ||
1183 | fail4: | |
dc803df8 | 1184 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1185 | fail3: |
2c118e0f | 1186 | efx->membase_phys = 0; |
8ceee660 BH |
1187 | fail2: |
1188 | pci_disable_device(efx->pci_dev); | |
1189 | fail1: | |
1190 | return rc; | |
1191 | } | |
1192 | ||
1193 | static void efx_fini_io(struct efx_nic *efx) | |
1194 | { | |
62776d03 | 1195 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1196 | |
1197 | if (efx->membase) { | |
1198 | iounmap(efx->membase); | |
1199 | efx->membase = NULL; | |
1200 | } | |
1201 | ||
1202 | if (efx->membase_phys) { | |
dc803df8 | 1203 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1204 | efx->membase_phys = 0; |
8ceee660 BH |
1205 | } |
1206 | ||
1207 | pci_disable_device(efx->pci_dev); | |
1208 | } | |
1209 | ||
a9a52506 | 1210 | static unsigned int efx_wanted_parallelism(struct efx_nic *efx) |
46123d04 | 1211 | { |
cdb08f8f | 1212 | cpumask_var_t thread_mask; |
a16e5b24 | 1213 | unsigned int count; |
46123d04 | 1214 | int cpu; |
5b874e25 | 1215 | |
cd2d5b52 BH |
1216 | if (rss_cpus) { |
1217 | count = rss_cpus; | |
1218 | } else { | |
1219 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { | |
1220 | netif_warn(efx, probe, efx->net_dev, | |
1221 | "RSS disabled due to allocation failure\n"); | |
1222 | return 1; | |
1223 | } | |
46123d04 | 1224 | |
cd2d5b52 BH |
1225 | count = 0; |
1226 | for_each_online_cpu(cpu) { | |
1227 | if (!cpumask_test_cpu(cpu, thread_mask)) { | |
1228 | ++count; | |
1229 | cpumask_or(thread_mask, thread_mask, | |
1230 | topology_thread_cpumask(cpu)); | |
1231 | } | |
1232 | } | |
1233 | ||
1234 | free_cpumask_var(thread_mask); | |
2f8975fb RR |
1235 | } |
1236 | ||
cd2d5b52 BH |
1237 | /* If RSS is requested for the PF *and* VFs then we can't write RSS |
1238 | * table entries that are inaccessible to VFs | |
1239 | */ | |
1240 | if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 && | |
1241 | count > efx_vf_size(efx)) { | |
1242 | netif_warn(efx, probe, efx->net_dev, | |
1243 | "Reducing number of RSS channels from %u to %u for " | |
1244 | "VF support. Increase vf-msix-limit to use more " | |
1245 | "channels on the PF.\n", | |
1246 | count, efx_vf_size(efx)); | |
1247 | count = efx_vf_size(efx); | |
46123d04 BH |
1248 | } |
1249 | ||
1250 | return count; | |
1251 | } | |
1252 | ||
1253 | /* Probe the number and type of interrupts we are able to obtain, and | |
1254 | * the resulting numbers of channels and RX queues. | |
1255 | */ | |
64d8ad6d | 1256 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1257 | { |
7f967c01 BH |
1258 | unsigned int extra_channels = 0; |
1259 | unsigned int i, j; | |
a16e5b24 | 1260 | int rc; |
8ceee660 | 1261 | |
7f967c01 BH |
1262 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) |
1263 | if (efx->extra_channel_type[i]) | |
1264 | ++extra_channels; | |
1265 | ||
8ceee660 | 1266 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { |
46123d04 | 1267 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a16e5b24 | 1268 | unsigned int n_channels; |
aa6ef27e | 1269 | |
a9a52506 | 1270 | n_channels = efx_wanted_parallelism(efx); |
a4900ac9 BH |
1271 | if (separate_tx_channels) |
1272 | n_channels *= 2; | |
7f967c01 | 1273 | n_channels += extra_channels; |
b105798f | 1274 | n_channels = min(n_channels, efx->max_channels); |
8ceee660 | 1275 | |
a4900ac9 | 1276 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1277 | xentries[i].entry = i; |
a4900ac9 | 1278 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1279 | if (rc > 0) { |
62776d03 BH |
1280 | netif_err(efx, drv, efx->net_dev, |
1281 | "WARNING: Insufficient MSI-X vectors" | |
a16e5b24 | 1282 | " available (%d < %u).\n", rc, n_channels); |
62776d03 BH |
1283 | netif_err(efx, drv, efx->net_dev, |
1284 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1285 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1286 | n_channels = rc; | |
8ceee660 | 1287 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1288 | n_channels); |
8ceee660 BH |
1289 | } |
1290 | ||
1291 | if (rc == 0) { | |
a4900ac9 | 1292 | efx->n_channels = n_channels; |
7f967c01 BH |
1293 | if (n_channels > extra_channels) |
1294 | n_channels -= extra_channels; | |
a4900ac9 | 1295 | if (separate_tx_channels) { |
7f967c01 BH |
1296 | efx->n_tx_channels = max(n_channels / 2, 1U); |
1297 | efx->n_rx_channels = max(n_channels - | |
1298 | efx->n_tx_channels, | |
1299 | 1U); | |
a4900ac9 | 1300 | } else { |
7f967c01 BH |
1301 | efx->n_tx_channels = n_channels; |
1302 | efx->n_rx_channels = n_channels; | |
a4900ac9 | 1303 | } |
7f967c01 | 1304 | for (i = 0; i < efx->n_channels; i++) |
f7d12cdc BH |
1305 | efx_get_channel(efx, i)->irq = |
1306 | xentries[i].vector; | |
8ceee660 BH |
1307 | } else { |
1308 | /* Fall back to single channel MSI */ | |
1309 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1310 | netif_err(efx, drv, efx->net_dev, |
1311 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1312 | } |
1313 | } | |
1314 | ||
1315 | /* Try single interrupt MSI */ | |
1316 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1317 | efx->n_channels = 1; |
a4900ac9 BH |
1318 | efx->n_rx_channels = 1; |
1319 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1320 | rc = pci_enable_msi(efx->pci_dev); |
1321 | if (rc == 0) { | |
f7d12cdc | 1322 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1323 | } else { |
62776d03 BH |
1324 | netif_err(efx, drv, efx->net_dev, |
1325 | "could not enable MSI\n"); | |
8ceee660 BH |
1326 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1327 | } | |
1328 | } | |
1329 | ||
1330 | /* Assume legacy interrupts */ | |
1331 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1332 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1333 | efx->n_rx_channels = 1; |
1334 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1335 | efx->legacy_irq = efx->pci_dev->irq; |
1336 | } | |
64d8ad6d | 1337 | |
7f967c01 BH |
1338 | /* Assign extra channels if possible */ |
1339 | j = efx->n_channels; | |
1340 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { | |
1341 | if (!efx->extra_channel_type[i]) | |
1342 | continue; | |
1343 | if (efx->interrupt_mode != EFX_INT_MODE_MSIX || | |
1344 | efx->n_channels <= extra_channels) { | |
1345 | efx->extra_channel_type[i]->handle_no_channel(efx); | |
1346 | } else { | |
1347 | --j; | |
1348 | efx_get_channel(efx, j)->type = | |
1349 | efx->extra_channel_type[i]; | |
1350 | } | |
1351 | } | |
1352 | ||
cd2d5b52 | 1353 | /* RSS might be usable on VFs even if it is disabled on the PF */ |
3132d282 | 1354 | efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ? |
cd2d5b52 BH |
1355 | efx->n_rx_channels : efx_vf_size(efx)); |
1356 | ||
64d8ad6d | 1357 | return 0; |
8ceee660 BH |
1358 | } |
1359 | ||
261e4d96 | 1360 | static int efx_soft_enable_interrupts(struct efx_nic *efx) |
9f2cb71c | 1361 | { |
261e4d96 JC |
1362 | struct efx_channel *channel, *end_channel; |
1363 | int rc; | |
9f2cb71c | 1364 | |
8b7325b4 BH |
1365 | BUG_ON(efx->state == STATE_DISABLED); |
1366 | ||
d8291187 BH |
1367 | efx->irq_soft_enabled = true; |
1368 | smp_wmb(); | |
9f2cb71c BH |
1369 | |
1370 | efx_for_each_channel(channel, efx) { | |
261e4d96 JC |
1371 | if (!channel->type->keep_eventq) { |
1372 | rc = efx_init_eventq(channel); | |
1373 | if (rc) | |
1374 | goto fail; | |
1375 | } | |
9f2cb71c BH |
1376 | efx_start_eventq(channel); |
1377 | } | |
1378 | ||
1379 | efx_mcdi_mode_event(efx); | |
261e4d96 JC |
1380 | |
1381 | return 0; | |
1382 | fail: | |
1383 | end_channel = channel; | |
1384 | efx_for_each_channel(channel, efx) { | |
1385 | if (channel == end_channel) | |
1386 | break; | |
1387 | efx_stop_eventq(channel); | |
1388 | if (!channel->type->keep_eventq) | |
1389 | efx_fini_eventq(channel); | |
1390 | } | |
1391 | ||
1392 | return rc; | |
9f2cb71c BH |
1393 | } |
1394 | ||
d8291187 | 1395 | static void efx_soft_disable_interrupts(struct efx_nic *efx) |
9f2cb71c BH |
1396 | { |
1397 | struct efx_channel *channel; | |
1398 | ||
8b7325b4 BH |
1399 | if (efx->state == STATE_DISABLED) |
1400 | return; | |
1401 | ||
9f2cb71c BH |
1402 | efx_mcdi_mode_poll(efx); |
1403 | ||
d8291187 BH |
1404 | efx->irq_soft_enabled = false; |
1405 | smp_wmb(); | |
1406 | ||
1407 | if (efx->legacy_irq) | |
9f2cb71c | 1408 | synchronize_irq(efx->legacy_irq); |
9f2cb71c BH |
1409 | |
1410 | efx_for_each_channel(channel, efx) { | |
1411 | if (channel->irq) | |
1412 | synchronize_irq(channel->irq); | |
1413 | ||
1414 | efx_stop_eventq(channel); | |
d8291187 | 1415 | if (!channel->type->keep_eventq) |
7f967c01 | 1416 | efx_fini_eventq(channel); |
9f2cb71c | 1417 | } |
cade715f BH |
1418 | |
1419 | /* Flush the asynchronous MCDI request queue */ | |
1420 | efx_mcdi_flush_async(efx); | |
9f2cb71c BH |
1421 | } |
1422 | ||
261e4d96 | 1423 | static int efx_enable_interrupts(struct efx_nic *efx) |
d8291187 | 1424 | { |
261e4d96 JC |
1425 | struct efx_channel *channel, *end_channel; |
1426 | int rc; | |
d8291187 BH |
1427 | |
1428 | BUG_ON(efx->state == STATE_DISABLED); | |
1429 | ||
1430 | if (efx->eeh_disabled_legacy_irq) { | |
1431 | enable_irq(efx->legacy_irq); | |
1432 | efx->eeh_disabled_legacy_irq = false; | |
1433 | } | |
1434 | ||
86094f7f | 1435 | efx->type->irq_enable_master(efx); |
d8291187 BH |
1436 | |
1437 | efx_for_each_channel(channel, efx) { | |
261e4d96 JC |
1438 | if (channel->type->keep_eventq) { |
1439 | rc = efx_init_eventq(channel); | |
1440 | if (rc) | |
1441 | goto fail; | |
1442 | } | |
1443 | } | |
1444 | ||
1445 | rc = efx_soft_enable_interrupts(efx); | |
1446 | if (rc) | |
1447 | goto fail; | |
1448 | ||
1449 | return 0; | |
1450 | ||
1451 | fail: | |
1452 | end_channel = channel; | |
1453 | efx_for_each_channel(channel, efx) { | |
1454 | if (channel == end_channel) | |
1455 | break; | |
d8291187 | 1456 | if (channel->type->keep_eventq) |
261e4d96 | 1457 | efx_fini_eventq(channel); |
d8291187 BH |
1458 | } |
1459 | ||
261e4d96 JC |
1460 | efx->type->irq_disable_non_ev(efx); |
1461 | ||
1462 | return rc; | |
d8291187 BH |
1463 | } |
1464 | ||
1465 | static void efx_disable_interrupts(struct efx_nic *efx) | |
1466 | { | |
1467 | struct efx_channel *channel; | |
1468 | ||
1469 | efx_soft_disable_interrupts(efx); | |
1470 | ||
1471 | efx_for_each_channel(channel, efx) { | |
1472 | if (channel->type->keep_eventq) | |
1473 | efx_fini_eventq(channel); | |
1474 | } | |
1475 | ||
86094f7f | 1476 | efx->type->irq_disable_non_ev(efx); |
d8291187 BH |
1477 | } |
1478 | ||
8ceee660 BH |
1479 | static void efx_remove_interrupts(struct efx_nic *efx) |
1480 | { | |
1481 | struct efx_channel *channel; | |
1482 | ||
1483 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1484 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1485 | channel->irq = 0; |
1486 | pci_disable_msi(efx->pci_dev); | |
1487 | pci_disable_msix(efx->pci_dev); | |
1488 | ||
1489 | /* Remove legacy interrupt */ | |
1490 | efx->legacy_irq = 0; | |
1491 | } | |
1492 | ||
8831da7b | 1493 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1494 | { |
602a5322 BH |
1495 | struct efx_channel *channel; |
1496 | struct efx_tx_queue *tx_queue; | |
1497 | ||
97653431 | 1498 | efx->tx_channel_offset = |
a4900ac9 | 1499 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 | 1500 | |
79d68b37 SH |
1501 | /* We need to mark which channels really have RX and TX |
1502 | * queues, and adjust the TX queue numbers if we have separate | |
602a5322 BH |
1503 | * RX-only and TX-only channels. |
1504 | */ | |
1505 | efx_for_each_channel(channel, efx) { | |
79d68b37 SH |
1506 | if (channel->channel < efx->n_rx_channels) |
1507 | channel->rx_queue.core_index = channel->channel; | |
1508 | else | |
1509 | channel->rx_queue.core_index = -1; | |
1510 | ||
602a5322 BH |
1511 | efx_for_each_channel_tx_queue(tx_queue, channel) |
1512 | tx_queue->queue -= (efx->tx_channel_offset * | |
1513 | EFX_TXQ_TYPES); | |
1514 | } | |
8ceee660 BH |
1515 | } |
1516 | ||
1517 | static int efx_probe_nic(struct efx_nic *efx) | |
1518 | { | |
765c9f46 | 1519 | size_t i; |
8ceee660 BH |
1520 | int rc; |
1521 | ||
62776d03 | 1522 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1523 | |
1524 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1525 | rc = efx->type->probe(efx); |
8ceee660 BH |
1526 | if (rc) |
1527 | return rc; | |
1528 | ||
a4900ac9 | 1529 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1530 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1531 | rc = efx_probe_interrupts(efx); |
1532 | if (rc) | |
c15eed22 | 1533 | goto fail1; |
8ceee660 | 1534 | |
c15eed22 BH |
1535 | rc = efx->type->dimension_resources(efx); |
1536 | if (rc) | |
1537 | goto fail2; | |
28e47c49 | 1538 | |
5d3a6fca BH |
1539 | if (efx->n_channels > 1) |
1540 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 | 1541 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
278bc429 | 1542 | efx->rx_indir_table[i] = |
cd2d5b52 | 1543 | ethtool_rxfh_indir_default(i, efx->rss_spread); |
5d3a6fca | 1544 | |
8831da7b | 1545 | efx_set_channels(efx); |
c4f4adc7 BH |
1546 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1547 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1548 | |
1549 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1550 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1551 | true); | |
8ceee660 BH |
1552 | |
1553 | return 0; | |
64d8ad6d | 1554 | |
c15eed22 BH |
1555 | fail2: |
1556 | efx_remove_interrupts(efx); | |
1557 | fail1: | |
64d8ad6d BH |
1558 | efx->type->remove(efx); |
1559 | return rc; | |
8ceee660 BH |
1560 | } |
1561 | ||
1562 | static void efx_remove_nic(struct efx_nic *efx) | |
1563 | { | |
62776d03 | 1564 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1565 | |
1566 | efx_remove_interrupts(efx); | |
ef2b90ee | 1567 | efx->type->remove(efx); |
8ceee660 BH |
1568 | } |
1569 | ||
add72477 BH |
1570 | static int efx_probe_filters(struct efx_nic *efx) |
1571 | { | |
1572 | int rc; | |
1573 | ||
1574 | spin_lock_init(&efx->filter_lock); | |
1575 | ||
1576 | rc = efx->type->filter_table_probe(efx); | |
1577 | if (rc) | |
1578 | return rc; | |
1579 | ||
1580 | #ifdef CONFIG_RFS_ACCEL | |
1581 | if (efx->type->offload_features & NETIF_F_NTUPLE) { | |
1582 | efx->rps_flow_id = kcalloc(efx->type->max_rx_ip_filters, | |
1583 | sizeof(*efx->rps_flow_id), | |
1584 | GFP_KERNEL); | |
1585 | if (!efx->rps_flow_id) { | |
1586 | efx->type->filter_table_remove(efx); | |
1587 | return -ENOMEM; | |
1588 | } | |
1589 | } | |
1590 | #endif | |
1591 | ||
1592 | return 0; | |
1593 | } | |
1594 | ||
1595 | static void efx_remove_filters(struct efx_nic *efx) | |
1596 | { | |
1597 | #ifdef CONFIG_RFS_ACCEL | |
1598 | kfree(efx->rps_flow_id); | |
1599 | #endif | |
1600 | efx->type->filter_table_remove(efx); | |
1601 | } | |
1602 | ||
1603 | static void efx_restore_filters(struct efx_nic *efx) | |
1604 | { | |
1605 | efx->type->filter_table_restore(efx); | |
1606 | } | |
1607 | ||
8ceee660 BH |
1608 | /************************************************************************** |
1609 | * | |
1610 | * NIC startup/shutdown | |
1611 | * | |
1612 | *************************************************************************/ | |
1613 | ||
1614 | static int efx_probe_all(struct efx_nic *efx) | |
1615 | { | |
8ceee660 BH |
1616 | int rc; |
1617 | ||
8ceee660 BH |
1618 | rc = efx_probe_nic(efx); |
1619 | if (rc) { | |
62776d03 | 1620 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1621 | goto fail1; |
1622 | } | |
1623 | ||
8ceee660 BH |
1624 | rc = efx_probe_port(efx); |
1625 | if (rc) { | |
62776d03 | 1626 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1627 | goto fail2; |
1628 | } | |
1629 | ||
7e6d06f0 BH |
1630 | BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); |
1631 | if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { | |
1632 | rc = -EINVAL; | |
1633 | goto fail3; | |
1634 | } | |
ecc910f5 | 1635 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
8ceee660 | 1636 | |
64eebcfd BH |
1637 | rc = efx_probe_filters(efx); |
1638 | if (rc) { | |
1639 | netif_err(efx, probe, efx->net_dev, | |
1640 | "failed to create filter tables\n"); | |
7f967c01 | 1641 | goto fail3; |
64eebcfd BH |
1642 | } |
1643 | ||
7f967c01 BH |
1644 | rc = efx_probe_channels(efx); |
1645 | if (rc) | |
1646 | goto fail4; | |
1647 | ||
8ceee660 BH |
1648 | return 0; |
1649 | ||
64eebcfd | 1650 | fail4: |
7f967c01 | 1651 | efx_remove_filters(efx); |
8ceee660 | 1652 | fail3: |
8ceee660 BH |
1653 | efx_remove_port(efx); |
1654 | fail2: | |
1655 | efx_remove_nic(efx); | |
1656 | fail1: | |
1657 | return rc; | |
1658 | } | |
1659 | ||
8b7325b4 BH |
1660 | /* If the interface is supposed to be running but is not, start |
1661 | * the hardware and software data path, regular activity for the port | |
1662 | * (MAC statistics, link polling, etc.) and schedule the port to be | |
1663 | * reconfigured. Interrupts must already be enabled. This function | |
1664 | * is safe to call multiple times, so long as the NIC is not disabled. | |
1665 | * Requires the RTNL lock. | |
9f2cb71c | 1666 | */ |
8ceee660 BH |
1667 | static void efx_start_all(struct efx_nic *efx) |
1668 | { | |
8ceee660 | 1669 | EFX_ASSERT_RESET_SERIALISED(efx); |
8b7325b4 | 1670 | BUG_ON(efx->state == STATE_DISABLED); |
8ceee660 BH |
1671 | |
1672 | /* Check that it is appropriate to restart the interface. All | |
1673 | * of these flags are safe to read under just the rtnl lock */ | |
8b7325b4 | 1674 | if (efx->port_enabled || !netif_running(efx->net_dev)) |
8ceee660 BH |
1675 | return; |
1676 | ||
8ceee660 | 1677 | efx_start_port(efx); |
9f2cb71c | 1678 | efx_start_datapath(efx); |
8880f4ec | 1679 | |
626950db AR |
1680 | /* Start the hardware monitor if there is one */ |
1681 | if (efx->type->monitor != NULL) | |
8ceee660 BH |
1682 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1683 | efx_monitor_interval); | |
626950db AR |
1684 | |
1685 | /* If link state detection is normally event-driven, we have | |
1686 | * to poll now because we could have missed a change | |
1687 | */ | |
1688 | if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) { | |
78c1f0a0 SH |
1689 | mutex_lock(&efx->mac_lock); |
1690 | if (efx->phy_op->poll(efx)) | |
1691 | efx_link_status_changed(efx); | |
1692 | mutex_unlock(&efx->mac_lock); | |
1693 | } | |
55edc6e6 | 1694 | |
ef2b90ee | 1695 | efx->type->start_stats(efx); |
f8f3b5ae JC |
1696 | efx->type->pull_stats(efx); |
1697 | spin_lock_bh(&efx->stats_lock); | |
1698 | efx->type->update_stats(efx, NULL, NULL); | |
1699 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
1700 | } |
1701 | ||
8b7325b4 BH |
1702 | /* Quiesce the hardware and software data path, and regular activity |
1703 | * for the port without bringing the link down. Safe to call multiple | |
1704 | * times with the NIC in almost any state, but interrupts should be | |
1705 | * enabled. Requires the RTNL lock. | |
1706 | */ | |
8ceee660 BH |
1707 | static void efx_stop_all(struct efx_nic *efx) |
1708 | { | |
8ceee660 BH |
1709 | EFX_ASSERT_RESET_SERIALISED(efx); |
1710 | ||
1711 | /* port_enabled can be read safely under the rtnl lock */ | |
1712 | if (!efx->port_enabled) | |
1713 | return; | |
1714 | ||
f8f3b5ae JC |
1715 | /* update stats before we go down so we can accurately count |
1716 | * rx_nodesc_drops | |
1717 | */ | |
1718 | efx->type->pull_stats(efx); | |
1719 | spin_lock_bh(&efx->stats_lock); | |
1720 | efx->type->update_stats(efx, NULL, NULL); | |
1721 | spin_unlock_bh(&efx->stats_lock); | |
ef2b90ee | 1722 | efx->type->stop_stats(efx); |
8ceee660 BH |
1723 | efx_stop_port(efx); |
1724 | ||
29c69a48 BH |
1725 | /* Stop the kernel transmit interface. This is only valid if |
1726 | * the device is stopped or detached; otherwise the watchdog | |
1727 | * may fire immediately. | |
1728 | */ | |
1729 | WARN_ON(netif_running(efx->net_dev) && | |
1730 | netif_device_present(efx->net_dev)); | |
9f2cb71c BH |
1731 | netif_tx_disable(efx->net_dev); |
1732 | ||
1733 | efx_stop_datapath(efx); | |
8ceee660 BH |
1734 | } |
1735 | ||
1736 | static void efx_remove_all(struct efx_nic *efx) | |
1737 | { | |
4642610c | 1738 | efx_remove_channels(efx); |
7f967c01 | 1739 | efx_remove_filters(efx); |
8ceee660 BH |
1740 | efx_remove_port(efx); |
1741 | efx_remove_nic(efx); | |
1742 | } | |
1743 | ||
8ceee660 BH |
1744 | /************************************************************************** |
1745 | * | |
1746 | * Interrupt moderation | |
1747 | * | |
1748 | **************************************************************************/ | |
1749 | ||
cc180b69 | 1750 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) |
0d86ebd8 | 1751 | { |
b548f976 BH |
1752 | if (usecs == 0) |
1753 | return 0; | |
cc180b69 | 1754 | if (usecs * 1000 < quantum_ns) |
0d86ebd8 | 1755 | return 1; /* never round down to 0 */ |
cc180b69 | 1756 | return usecs * 1000 / quantum_ns; |
0d86ebd8 BH |
1757 | } |
1758 | ||
8ceee660 | 1759 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1760 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1761 | unsigned int rx_usecs, bool rx_adaptive, | |
1762 | bool rx_may_override_tx) | |
8ceee660 | 1763 | { |
f7d12cdc | 1764 | struct efx_channel *channel; |
cc180b69 BH |
1765 | unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * |
1766 | efx->timer_quantum_ns, | |
1767 | 1000); | |
1768 | unsigned int tx_ticks; | |
1769 | unsigned int rx_ticks; | |
8ceee660 BH |
1770 | |
1771 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1772 | ||
cc180b69 | 1773 | if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) |
9e393b30 BH |
1774 | return -EINVAL; |
1775 | ||
cc180b69 BH |
1776 | tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); |
1777 | rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); | |
1778 | ||
9e393b30 BH |
1779 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && |
1780 | !rx_may_override_tx) { | |
1781 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1782 | "RX and TX IRQ moderation must be equal\n"); | |
1783 | return -EINVAL; | |
1784 | } | |
1785 | ||
6fb70fd1 | 1786 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1787 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1788 | efx_for_each_channel(channel, efx) { |
525da907 | 1789 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1790 | channel->irq_moderation = rx_ticks; |
525da907 | 1791 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1792 | channel->irq_moderation = tx_ticks; |
1793 | } | |
9e393b30 BH |
1794 | |
1795 | return 0; | |
8ceee660 BH |
1796 | } |
1797 | ||
a0c4faf5 BH |
1798 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1799 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1800 | { | |
cc180b69 BH |
1801 | /* We must round up when converting ticks to microseconds |
1802 | * because we round down when converting the other way. | |
1803 | */ | |
1804 | ||
a0c4faf5 | 1805 | *rx_adaptive = efx->irq_rx_adaptive; |
cc180b69 BH |
1806 | *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * |
1807 | efx->timer_quantum_ns, | |
1808 | 1000); | |
a0c4faf5 BH |
1809 | |
1810 | /* If channels are shared between RX and TX, so is IRQ | |
1811 | * moderation. Otherwise, IRQ moderation is the same for all | |
1812 | * TX channels and is not adaptive. | |
1813 | */ | |
1814 | if (efx->tx_channel_offset == 0) | |
1815 | *tx_usecs = *rx_usecs; | |
1816 | else | |
cc180b69 | 1817 | *tx_usecs = DIV_ROUND_UP( |
a0c4faf5 | 1818 | efx->channel[efx->tx_channel_offset]->irq_moderation * |
cc180b69 BH |
1819 | efx->timer_quantum_ns, |
1820 | 1000); | |
a0c4faf5 BH |
1821 | } |
1822 | ||
8ceee660 BH |
1823 | /************************************************************************** |
1824 | * | |
1825 | * Hardware monitor | |
1826 | * | |
1827 | **************************************************************************/ | |
1828 | ||
e254c274 | 1829 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1830 | static void efx_monitor(struct work_struct *data) |
1831 | { | |
1832 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1833 | monitor_work.work); | |
8ceee660 | 1834 | |
62776d03 BH |
1835 | netif_vdbg(efx, timer, efx->net_dev, |
1836 | "hardware monitor executing on CPU %d\n", | |
1837 | raw_smp_processor_id()); | |
ef2b90ee | 1838 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1839 | |
8ceee660 BH |
1840 | /* If the mac_lock is already held then it is likely a port |
1841 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1842 | * most of the work of monitor() anyway. */ |
1843 | if (mutex_trylock(&efx->mac_lock)) { | |
1844 | if (efx->port_enabled) | |
1845 | efx->type->monitor(efx); | |
1846 | mutex_unlock(&efx->mac_lock); | |
1847 | } | |
8ceee660 | 1848 | |
8ceee660 BH |
1849 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1850 | efx_monitor_interval); | |
1851 | } | |
1852 | ||
1853 | /************************************************************************** | |
1854 | * | |
1855 | * ioctls | |
1856 | * | |
1857 | *************************************************************************/ | |
1858 | ||
1859 | /* Net device ioctl | |
1860 | * Context: process, rtnl_lock() held. | |
1861 | */ | |
1862 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1863 | { | |
767e468c | 1864 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1865 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 | 1866 | |
7c236c43 | 1867 | if (cmd == SIOCSHWTSTAMP) |
433dc9b3 BH |
1868 | return efx_ptp_set_ts_config(efx, ifr); |
1869 | if (cmd == SIOCGHWTSTAMP) | |
1870 | return efx_ptp_get_ts_config(efx, ifr); | |
7c236c43 | 1871 | |
68e7f45e BH |
1872 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1873 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1874 | (data->phy_id & 0xfc00) == 0x0400) | |
1875 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1876 | ||
1877 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1878 | } |
1879 | ||
1880 | /************************************************************************** | |
1881 | * | |
1882 | * NAPI interface | |
1883 | * | |
1884 | **************************************************************************/ | |
1885 | ||
7f967c01 BH |
1886 | static void efx_init_napi_channel(struct efx_channel *channel) |
1887 | { | |
1888 | struct efx_nic *efx = channel->efx; | |
1889 | ||
1890 | channel->napi_dev = efx->net_dev; | |
1891 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
1892 | efx_poll, napi_weight); | |
1893 | } | |
1894 | ||
e8f14992 | 1895 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1896 | { |
1897 | struct efx_channel *channel; | |
8ceee660 | 1898 | |
7f967c01 BH |
1899 | efx_for_each_channel(channel, efx) |
1900 | efx_init_napi_channel(channel); | |
e8f14992 BH |
1901 | } |
1902 | ||
1903 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1904 | { | |
1905 | if (channel->napi_dev) | |
1906 | netif_napi_del(&channel->napi_str); | |
1907 | channel->napi_dev = NULL; | |
8ceee660 BH |
1908 | } |
1909 | ||
1910 | static void efx_fini_napi(struct efx_nic *efx) | |
1911 | { | |
1912 | struct efx_channel *channel; | |
1913 | ||
e8f14992 BH |
1914 | efx_for_each_channel(channel, efx) |
1915 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
1916 | } |
1917 | ||
1918 | /************************************************************************** | |
1919 | * | |
1920 | * Kernel netpoll interface | |
1921 | * | |
1922 | *************************************************************************/ | |
1923 | ||
1924 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1925 | ||
1926 | /* Although in the common case interrupts will be disabled, this is not | |
1927 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1928 | * so no locking is required. | |
1929 | */ | |
1930 | static void efx_netpoll(struct net_device *net_dev) | |
1931 | { | |
767e468c | 1932 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1933 | struct efx_channel *channel; |
1934 | ||
64ee3120 | 1935 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1936 | efx_schedule_channel(channel); |
1937 | } | |
1938 | ||
1939 | #endif | |
1940 | ||
1941 | /************************************************************************** | |
1942 | * | |
1943 | * Kernel net device interface | |
1944 | * | |
1945 | *************************************************************************/ | |
1946 | ||
1947 | /* Context: process, rtnl_lock() held. */ | |
1948 | static int efx_net_open(struct net_device *net_dev) | |
1949 | { | |
767e468c | 1950 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 BH |
1951 | int rc; |
1952 | ||
62776d03 BH |
1953 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1954 | raw_smp_processor_id()); | |
8ceee660 | 1955 | |
8b7325b4 BH |
1956 | rc = efx_check_disabled(efx); |
1957 | if (rc) | |
1958 | return rc; | |
f8b87c17 BH |
1959 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1960 | return -EBUSY; | |
8880f4ec BH |
1961 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1962 | return -EIO; | |
f8b87c17 | 1963 | |
78c1f0a0 SH |
1964 | /* Notify the kernel of the link state polled during driver load, |
1965 | * before the monitor starts running */ | |
1966 | efx_link_status_changed(efx); | |
1967 | ||
8ceee660 | 1968 | efx_start_all(efx); |
dd40781e | 1969 | efx_selftest_async_start(efx); |
8ceee660 BH |
1970 | return 0; |
1971 | } | |
1972 | ||
1973 | /* Context: process, rtnl_lock() held. | |
1974 | * Note that the kernel will ignore our return code; this method | |
1975 | * should really be a void. | |
1976 | */ | |
1977 | static int efx_net_stop(struct net_device *net_dev) | |
1978 | { | |
767e468c | 1979 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1980 | |
62776d03 BH |
1981 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1982 | raw_smp_processor_id()); | |
8ceee660 | 1983 | |
8b7325b4 BH |
1984 | /* Stop the device and flush all the channels */ |
1985 | efx_stop_all(efx); | |
8ceee660 BH |
1986 | |
1987 | return 0; | |
1988 | } | |
1989 | ||
5b9e207c | 1990 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
2aa9ef11 BH |
1991 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, |
1992 | struct rtnl_link_stats64 *stats) | |
8ceee660 | 1993 | { |
767e468c | 1994 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1995 | |
55edc6e6 | 1996 | spin_lock_bh(&efx->stats_lock); |
cd0ecc9a | 1997 | efx->type->update_stats(efx, NULL, stats); |
1cb34522 BH |
1998 | spin_unlock_bh(&efx->stats_lock); |
1999 | ||
8ceee660 BH |
2000 | return stats; |
2001 | } | |
2002 | ||
2003 | /* Context: netif_tx_lock held, BHs disabled. */ | |
2004 | static void efx_watchdog(struct net_device *net_dev) | |
2005 | { | |
767e468c | 2006 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2007 | |
62776d03 BH |
2008 | netif_err(efx, tx_err, efx->net_dev, |
2009 | "TX stuck with port_enabled=%d: resetting channels\n", | |
2010 | efx->port_enabled); | |
8ceee660 | 2011 | |
739bb23d | 2012 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
2013 | } |
2014 | ||
2015 | ||
2016 | /* Context: process, rtnl_lock() held. */ | |
2017 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
2018 | { | |
767e468c | 2019 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 | 2020 | int rc; |
8ceee660 | 2021 | |
8b7325b4 BH |
2022 | rc = efx_check_disabled(efx); |
2023 | if (rc) | |
2024 | return rc; | |
8ceee660 BH |
2025 | if (new_mtu > EFX_MAX_MTU) |
2026 | return -EINVAL; | |
2027 | ||
62776d03 | 2028 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 | 2029 | |
29c69a48 BH |
2030 | efx_device_detach_sync(efx); |
2031 | efx_stop_all(efx); | |
2032 | ||
d3245b28 | 2033 | mutex_lock(&efx->mac_lock); |
8ceee660 | 2034 | net_dev->mtu = new_mtu; |
710b208d | 2035 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
2036 | mutex_unlock(&efx->mac_lock); |
2037 | ||
8ceee660 | 2038 | efx_start_all(efx); |
29c69a48 | 2039 | netif_device_attach(efx->net_dev); |
6c8eef4a | 2040 | return 0; |
8ceee660 BH |
2041 | } |
2042 | ||
2043 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
2044 | { | |
767e468c | 2045 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
2046 | struct sockaddr *addr = data; |
2047 | char *new_addr = addr->sa_data; | |
2048 | ||
8ceee660 | 2049 | if (!is_valid_ether_addr(new_addr)) { |
62776d03 BH |
2050 | netif_err(efx, drv, efx->net_dev, |
2051 | "invalid ethernet MAC address requested: %pM\n", | |
2052 | new_addr); | |
504f9b5a | 2053 | return -EADDRNOTAVAIL; |
8ceee660 BH |
2054 | } |
2055 | ||
2056 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
cd2d5b52 | 2057 | efx_sriov_mac_address_changed(efx); |
8ceee660 BH |
2058 | |
2059 | /* Reconfigure the MAC */ | |
d3245b28 | 2060 | mutex_lock(&efx->mac_lock); |
710b208d | 2061 | efx->type->reconfigure_mac(efx); |
d3245b28 | 2062 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
2063 | |
2064 | return 0; | |
2065 | } | |
2066 | ||
a816f75a | 2067 | /* Context: netif_addr_lock held, BHs disabled. */ |
0fca8c97 | 2068 | static void efx_set_rx_mode(struct net_device *net_dev) |
8ceee660 | 2069 | { |
767e468c | 2070 | struct efx_nic *efx = netdev_priv(net_dev); |
a816f75a | 2071 | |
8be4f3e6 BH |
2072 | if (efx->port_enabled) |
2073 | queue_work(efx->workqueue, &efx->mac_work); | |
2074 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
2075 | } |
2076 | ||
c8f44aff | 2077 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
2078 | { |
2079 | struct efx_nic *efx = netdev_priv(net_dev); | |
2080 | ||
2081 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
2082 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
2083 | efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); | |
2084 | ||
2085 | return 0; | |
2086 | } | |
2087 | ||
8127d661 | 2088 | static const struct net_device_ops efx_farch_netdev_ops = { |
c3ecb9f3 SH |
2089 | .ndo_open = efx_net_open, |
2090 | .ndo_stop = efx_net_stop, | |
4472702e | 2091 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
2092 | .ndo_tx_timeout = efx_watchdog, |
2093 | .ndo_start_xmit = efx_hard_start_xmit, | |
2094 | .ndo_validate_addr = eth_validate_addr, | |
2095 | .ndo_do_ioctl = efx_ioctl, | |
2096 | .ndo_change_mtu = efx_change_mtu, | |
2097 | .ndo_set_mac_address = efx_set_mac_address, | |
0fca8c97 | 2098 | .ndo_set_rx_mode = efx_set_rx_mode, |
abfe9039 | 2099 | .ndo_set_features = efx_set_features, |
cd2d5b52 BH |
2100 | #ifdef CONFIG_SFC_SRIOV |
2101 | .ndo_set_vf_mac = efx_sriov_set_vf_mac, | |
2102 | .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, | |
2103 | .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, | |
2104 | .ndo_get_vf_config = efx_sriov_get_vf_config, | |
2105 | #endif | |
c3ecb9f3 SH |
2106 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2107 | .ndo_poll_controller = efx_netpoll, | |
2108 | #endif | |
94b274bf | 2109 | .ndo_setup_tc = efx_setup_tc, |
64d8ad6d BH |
2110 | #ifdef CONFIG_RFS_ACCEL |
2111 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2112 | #endif | |
c3ecb9f3 SH |
2113 | }; |
2114 | ||
8127d661 BH |
2115 | static const struct net_device_ops efx_ef10_netdev_ops = { |
2116 | .ndo_open = efx_net_open, | |
2117 | .ndo_stop = efx_net_stop, | |
2118 | .ndo_get_stats64 = efx_net_stats, | |
2119 | .ndo_tx_timeout = efx_watchdog, | |
2120 | .ndo_start_xmit = efx_hard_start_xmit, | |
2121 | .ndo_validate_addr = eth_validate_addr, | |
2122 | .ndo_do_ioctl = efx_ioctl, | |
2123 | .ndo_change_mtu = efx_change_mtu, | |
2124 | .ndo_set_mac_address = efx_set_mac_address, | |
2125 | .ndo_set_rx_mode = efx_set_rx_mode, | |
2126 | .ndo_set_features = efx_set_features, | |
2127 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2128 | .ndo_poll_controller = efx_netpoll, | |
2129 | #endif | |
2130 | #ifdef CONFIG_RFS_ACCEL | |
2131 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2132 | #endif | |
2133 | }; | |
2134 | ||
7dde596e BH |
2135 | static void efx_update_name(struct efx_nic *efx) |
2136 | { | |
2137 | strcpy(efx->name, efx->net_dev->name); | |
2138 | efx_mtd_rename(efx); | |
2139 | efx_set_channel_names(efx); | |
2140 | } | |
2141 | ||
8ceee660 BH |
2142 | static int efx_netdev_event(struct notifier_block *this, |
2143 | unsigned long event, void *ptr) | |
2144 | { | |
351638e7 | 2145 | struct net_device *net_dev = netdev_notifier_info_to_dev(ptr); |
8ceee660 | 2146 | |
8127d661 BH |
2147 | if ((net_dev->netdev_ops == &efx_farch_netdev_ops || |
2148 | net_dev->netdev_ops == &efx_ef10_netdev_ops) && | |
7dde596e BH |
2149 | event == NETDEV_CHANGENAME) |
2150 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
2151 | |
2152 | return NOTIFY_DONE; | |
2153 | } | |
2154 | ||
2155 | static struct notifier_block efx_netdev_notifier = { | |
2156 | .notifier_call = efx_netdev_event, | |
2157 | }; | |
2158 | ||
06d5e193 BH |
2159 | static ssize_t |
2160 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
2161 | { | |
2162 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2163 | return sprintf(buf, "%d\n", efx->phy_type); | |
2164 | } | |
776fbcc9 | 2165 | static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL); |
06d5e193 | 2166 | |
8ceee660 BH |
2167 | static int efx_register_netdev(struct efx_nic *efx) |
2168 | { | |
2169 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 2170 | struct efx_channel *channel; |
8ceee660 BH |
2171 | int rc; |
2172 | ||
2173 | net_dev->watchdog_timeo = 5 * HZ; | |
2174 | net_dev->irq = efx->pci_dev->irq; | |
8127d661 BH |
2175 | if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) { |
2176 | net_dev->netdev_ops = &efx_ef10_netdev_ops; | |
2177 | net_dev->priv_flags |= IFF_UNICAST_FLT; | |
2178 | } else { | |
2179 | net_dev->netdev_ops = &efx_farch_netdev_ops; | |
2180 | } | |
8ceee660 | 2181 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
7e6d06f0 | 2182 | net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; |
8ceee660 | 2183 | |
7dde596e | 2184 | rtnl_lock(); |
aed0628d | 2185 | |
7153f623 BH |
2186 | /* Enable resets to be scheduled and check whether any were |
2187 | * already requested. If so, the NIC is probably hosed so we | |
2188 | * abort. | |
2189 | */ | |
2190 | efx->state = STATE_READY; | |
2191 | smp_mb(); /* ensure we change state before checking reset_pending */ | |
2192 | if (efx->reset_pending) { | |
2193 | netif_err(efx, probe, efx->net_dev, | |
2194 | "aborting probe due to scheduled reset\n"); | |
2195 | rc = -EIO; | |
2196 | goto fail_locked; | |
2197 | } | |
2198 | ||
aed0628d BH |
2199 | rc = dev_alloc_name(net_dev, net_dev->name); |
2200 | if (rc < 0) | |
2201 | goto fail_locked; | |
7dde596e | 2202 | efx_update_name(efx); |
aed0628d | 2203 | |
8f8b3d51 BH |
2204 | /* Always start with carrier off; PHY events will detect the link */ |
2205 | netif_carrier_off(net_dev); | |
2206 | ||
aed0628d BH |
2207 | rc = register_netdevice(net_dev); |
2208 | if (rc) | |
2209 | goto fail_locked; | |
2210 | ||
c04bfc6b BH |
2211 | efx_for_each_channel(channel, efx) { |
2212 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
2213 | efx_for_each_channel_tx_queue(tx_queue, channel) |
2214 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
2215 | } |
2216 | ||
7dde596e | 2217 | rtnl_unlock(); |
8ceee660 | 2218 | |
06d5e193 BH |
2219 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
2220 | if (rc) { | |
62776d03 BH |
2221 | netif_err(efx, drv, efx->net_dev, |
2222 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
2223 | goto fail_registered; |
2224 | } | |
2225 | ||
8ceee660 | 2226 | return 0; |
06d5e193 | 2227 | |
7153f623 BH |
2228 | fail_registered: |
2229 | rtnl_lock(); | |
2230 | unregister_netdevice(net_dev); | |
aed0628d | 2231 | fail_locked: |
7153f623 | 2232 | efx->state = STATE_UNINIT; |
aed0628d | 2233 | rtnl_unlock(); |
62776d03 | 2234 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d | 2235 | return rc; |
8ceee660 BH |
2236 | } |
2237 | ||
2238 | static void efx_unregister_netdev(struct efx_nic *efx) | |
2239 | { | |
8ceee660 BH |
2240 | if (!efx->net_dev) |
2241 | return; | |
2242 | ||
767e468c | 2243 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 | 2244 | |
73ba7b68 BH |
2245 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
2246 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
7153f623 BH |
2247 | |
2248 | rtnl_lock(); | |
2249 | unregister_netdevice(efx->net_dev); | |
2250 | efx->state = STATE_UNINIT; | |
2251 | rtnl_unlock(); | |
8ceee660 BH |
2252 | } |
2253 | ||
2254 | /************************************************************************** | |
2255 | * | |
2256 | * Device reset and suspend | |
2257 | * | |
2258 | **************************************************************************/ | |
2259 | ||
2467ca46 BH |
2260 | /* Tears down the entire software state and most of the hardware state |
2261 | * before reset. */ | |
d3245b28 | 2262 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2263 | { |
8ceee660 BH |
2264 | EFX_ASSERT_RESET_SERIALISED(efx); |
2265 | ||
2467ca46 | 2266 | efx_stop_all(efx); |
d8291187 | 2267 | efx_disable_interrupts(efx); |
5642ceef BH |
2268 | |
2269 | mutex_lock(&efx->mac_lock); | |
4b988280 SH |
2270 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2271 | efx->phy_op->fini(efx); | |
ef2b90ee | 2272 | efx->type->fini(efx); |
8ceee660 BH |
2273 | } |
2274 | ||
2467ca46 BH |
2275 | /* This function will always ensure that the locks acquired in |
2276 | * efx_reset_down() are released. A failure return code indicates | |
2277 | * that we were unable to reinitialise the hardware, and the | |
2278 | * driver should be disabled. If ok is false, then the rx and tx | |
2279 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2280 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2281 | { |
2282 | int rc; | |
2283 | ||
2467ca46 | 2284 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2285 | |
ef2b90ee | 2286 | rc = efx->type->init(efx); |
8ceee660 | 2287 | if (rc) { |
62776d03 | 2288 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2289 | goto fail; |
8ceee660 BH |
2290 | } |
2291 | ||
eb9f6744 BH |
2292 | if (!ok) |
2293 | goto fail; | |
2294 | ||
4b988280 | 2295 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2296 | rc = efx->phy_op->init(efx); |
2297 | if (rc) | |
2298 | goto fail; | |
2299 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2300 | netif_err(efx, drv, efx->net_dev, |
2301 | "could not restore PHY settings\n"); | |
4b988280 SH |
2302 | } |
2303 | ||
261e4d96 JC |
2304 | rc = efx_enable_interrupts(efx); |
2305 | if (rc) | |
2306 | goto fail; | |
64eebcfd | 2307 | efx_restore_filters(efx); |
cd2d5b52 | 2308 | efx_sriov_reset(efx); |
eb9f6744 | 2309 | |
eb9f6744 BH |
2310 | mutex_unlock(&efx->mac_lock); |
2311 | ||
2312 | efx_start_all(efx); | |
2313 | ||
2314 | return 0; | |
2315 | ||
2316 | fail: | |
2317 | efx->port_initialized = false; | |
2467ca46 BH |
2318 | |
2319 | mutex_unlock(&efx->mac_lock); | |
2320 | ||
8ceee660 BH |
2321 | return rc; |
2322 | } | |
2323 | ||
eb9f6744 BH |
2324 | /* Reset the NIC using the specified method. Note that the reset may |
2325 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2326 | * |
eb9f6744 | 2327 | * Caller must hold the rtnl_lock. |
8ceee660 | 2328 | */ |
eb9f6744 | 2329 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2330 | { |
eb9f6744 BH |
2331 | int rc, rc2; |
2332 | bool disabled; | |
8ceee660 | 2333 | |
62776d03 BH |
2334 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2335 | RESET_TYPE(method)); | |
8ceee660 | 2336 | |
c2f3b8e3 | 2337 | efx_device_detach_sync(efx); |
d3245b28 | 2338 | efx_reset_down(efx, method); |
8ceee660 | 2339 | |
ef2b90ee | 2340 | rc = efx->type->reset(efx, method); |
8ceee660 | 2341 | if (rc) { |
62776d03 | 2342 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2343 | goto out; |
8ceee660 BH |
2344 | } |
2345 | ||
a7d529ae BH |
2346 | /* Clear flags for the scopes we covered. We assume the NIC and |
2347 | * driver are now quiescent so that there is no race here. | |
2348 | */ | |
2349 | efx->reset_pending &= -(1 << (method + 1)); | |
8ceee660 BH |
2350 | |
2351 | /* Reinitialise bus-mastering, which may have been turned off before | |
2352 | * the reset was scheduled. This is still appropriate, even in the | |
2353 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2354 | * can respond to requests. */ | |
2355 | pci_set_master(efx->pci_dev); | |
2356 | ||
eb9f6744 | 2357 | out: |
8ceee660 | 2358 | /* Leave device stopped if necessary */ |
626950db AR |
2359 | disabled = rc || |
2360 | method == RESET_TYPE_DISABLE || | |
2361 | method == RESET_TYPE_RECOVER_OR_DISABLE; | |
eb9f6744 BH |
2362 | rc2 = efx_reset_up(efx, method, !disabled); |
2363 | if (rc2) { | |
2364 | disabled = true; | |
2365 | if (!rc) | |
2366 | rc = rc2; | |
8ceee660 BH |
2367 | } |
2368 | ||
eb9f6744 | 2369 | if (disabled) { |
f49a4589 | 2370 | dev_close(efx->net_dev); |
62776d03 | 2371 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2372 | efx->state = STATE_DISABLED; |
f4bd954e | 2373 | } else { |
62776d03 | 2374 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2375 | netif_device_attach(efx->net_dev); |
f4bd954e | 2376 | } |
8ceee660 BH |
2377 | return rc; |
2378 | } | |
2379 | ||
626950db AR |
2380 | /* Try recovery mechanisms. |
2381 | * For now only EEH is supported. | |
2382 | * Returns 0 if the recovery mechanisms are unsuccessful. | |
2383 | * Returns a non-zero value otherwise. | |
2384 | */ | |
b28405b0 | 2385 | int efx_try_recovery(struct efx_nic *efx) |
626950db AR |
2386 | { |
2387 | #ifdef CONFIG_EEH | |
2388 | /* A PCI error can occur and not be seen by EEH because nothing | |
2389 | * happens on the PCI bus. In this case the driver may fail and | |
2390 | * schedule a 'recover or reset', leading to this recovery handler. | |
2391 | * Manually call the eeh failure check function. | |
2392 | */ | |
2393 | struct eeh_dev *eehdev = | |
2394 | of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev)); | |
2395 | ||
2396 | if (eeh_dev_check_failure(eehdev)) { | |
2397 | /* The EEH mechanisms will handle the error and reset the | |
2398 | * device if necessary. | |
2399 | */ | |
2400 | return 1; | |
2401 | } | |
2402 | #endif | |
2403 | return 0; | |
2404 | } | |
2405 | ||
74cd60a4 JC |
2406 | static void efx_wait_for_bist_end(struct efx_nic *efx) |
2407 | { | |
2408 | int i; | |
2409 | ||
2410 | for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) { | |
2411 | if (efx_mcdi_poll_reboot(efx)) | |
2412 | goto out; | |
2413 | msleep(BIST_WAIT_DELAY_MS); | |
2414 | } | |
2415 | ||
2416 | netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n"); | |
2417 | out: | |
2418 | /* Either way unset the BIST flag. If we found no reboot we probably | |
2419 | * won't recover, but we should try. | |
2420 | */ | |
2421 | efx->mc_bist_for_other_fn = false; | |
2422 | } | |
2423 | ||
8ceee660 BH |
2424 | /* The worker thread exists so that code that cannot sleep can |
2425 | * schedule a reset for later. | |
2426 | */ | |
2427 | static void efx_reset_work(struct work_struct *data) | |
2428 | { | |
eb9f6744 | 2429 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
626950db AR |
2430 | unsigned long pending; |
2431 | enum reset_type method; | |
2432 | ||
2433 | pending = ACCESS_ONCE(efx->reset_pending); | |
2434 | method = fls(pending) - 1; | |
2435 | ||
74cd60a4 JC |
2436 | if (method == RESET_TYPE_MC_BIST) |
2437 | efx_wait_for_bist_end(efx); | |
2438 | ||
626950db AR |
2439 | if ((method == RESET_TYPE_RECOVER_OR_DISABLE || |
2440 | method == RESET_TYPE_RECOVER_OR_ALL) && | |
2441 | efx_try_recovery(efx)) | |
2442 | return; | |
8ceee660 | 2443 | |
a7d529ae | 2444 | if (!pending) |
319ba649 SH |
2445 | return; |
2446 | ||
eb9f6744 | 2447 | rtnl_lock(); |
7153f623 BH |
2448 | |
2449 | /* We checked the state in efx_schedule_reset() but it may | |
2450 | * have changed by now. Now that we have the RTNL lock, | |
2451 | * it cannot change again. | |
2452 | */ | |
2453 | if (efx->state == STATE_READY) | |
626950db | 2454 | (void)efx_reset(efx, method); |
7153f623 | 2455 | |
eb9f6744 | 2456 | rtnl_unlock(); |
8ceee660 BH |
2457 | } |
2458 | ||
2459 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2460 | { | |
2461 | enum reset_type method; | |
2462 | ||
626950db AR |
2463 | if (efx->state == STATE_RECOVERY) { |
2464 | netif_dbg(efx, drv, efx->net_dev, | |
2465 | "recovering: skip scheduling %s reset\n", | |
2466 | RESET_TYPE(type)); | |
2467 | return; | |
2468 | } | |
2469 | ||
8ceee660 BH |
2470 | switch (type) { |
2471 | case RESET_TYPE_INVISIBLE: | |
2472 | case RESET_TYPE_ALL: | |
626950db | 2473 | case RESET_TYPE_RECOVER_OR_ALL: |
8ceee660 BH |
2474 | case RESET_TYPE_WORLD: |
2475 | case RESET_TYPE_DISABLE: | |
626950db | 2476 | case RESET_TYPE_RECOVER_OR_DISABLE: |
74cd60a4 | 2477 | case RESET_TYPE_MC_BIST: |
8ceee660 | 2478 | method = type; |
0e2a9c7c BH |
2479 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2480 | RESET_TYPE(method)); | |
8ceee660 | 2481 | break; |
8ceee660 | 2482 | default: |
0e2a9c7c | 2483 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2484 | netif_dbg(efx, drv, efx->net_dev, |
2485 | "scheduling %s reset for %s\n", | |
2486 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2487 | break; |
2488 | } | |
8ceee660 | 2489 | |
a7d529ae | 2490 | set_bit(method, &efx->reset_pending); |
7153f623 BH |
2491 | smp_mb(); /* ensure we change reset_pending before checking state */ |
2492 | ||
2493 | /* If we're not READY then just leave the flags set as the cue | |
2494 | * to abort probing or reschedule the reset later. | |
2495 | */ | |
2496 | if (ACCESS_ONCE(efx->state) != STATE_READY) | |
2497 | return; | |
8ceee660 | 2498 | |
8880f4ec BH |
2499 | /* efx_process_channel() will no longer read events once a |
2500 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2501 | efx_mcdi_mode_poll(efx); | |
2502 | ||
1ab00629 | 2503 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2504 | } |
2505 | ||
2506 | /************************************************************************** | |
2507 | * | |
2508 | * List of NICs we support | |
2509 | * | |
2510 | **************************************************************************/ | |
2511 | ||
2512 | /* PCI device ID table */ | |
a3aa1884 | 2513 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
937383a5 BH |
2514 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2515 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2516 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2517 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2518 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2519 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2520 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2521 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2522 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2523 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8127d661 BH |
2524 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */ |
2525 | .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, | |
8ceee660 BH |
2526 | {0} /* end of list */ |
2527 | }; | |
2528 | ||
2529 | /************************************************************************** | |
2530 | * | |
3759433d | 2531 | * Dummy PHY/MAC operations |
8ceee660 | 2532 | * |
01aad7b6 | 2533 | * Can be used for some unimplemented operations |
8ceee660 BH |
2534 | * Needed so all function pointers are valid and do not have to be tested |
2535 | * before use | |
2536 | * | |
2537 | **************************************************************************/ | |
2538 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2539 | { | |
2540 | return 0; | |
2541 | } | |
2542 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2543 | |
2544 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2545 | { |
2546 | return false; | |
2547 | } | |
8ceee660 | 2548 | |
6c8c2513 | 2549 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2550 | .init = efx_port_dummy_op_int, |
d3245b28 | 2551 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2552 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2553 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2554 | }; |
2555 | ||
8ceee660 BH |
2556 | /************************************************************************** |
2557 | * | |
2558 | * Data housekeeping | |
2559 | * | |
2560 | **************************************************************************/ | |
2561 | ||
2562 | /* This zeroes out and then fills in the invariants in a struct | |
2563 | * efx_nic (including all sub-structures). | |
2564 | */ | |
adeb15aa | 2565 | static int efx_init_struct(struct efx_nic *efx, |
8ceee660 BH |
2566 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2567 | { | |
4642610c | 2568 | int i; |
8ceee660 BH |
2569 | |
2570 | /* Initialise common structures */ | |
8ceee660 | 2571 | spin_lock_init(&efx->biu_lock); |
76884835 BH |
2572 | #ifdef CONFIG_SFC_MTD |
2573 | INIT_LIST_HEAD(&efx->mtd_list); | |
2574 | #endif | |
8ceee660 BH |
2575 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2576 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
dd40781e | 2577 | INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); |
8ceee660 | 2578 | efx->pci_dev = pci_dev; |
62776d03 | 2579 | efx->msg_enable = debug; |
f16aeea0 | 2580 | efx->state = STATE_UNINIT; |
8ceee660 | 2581 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2582 | |
2583 | efx->net_dev = net_dev; | |
43a3739d | 2584 | efx->rx_prefix_size = efx->type->rx_prefix_size; |
2ec03014 AR |
2585 | efx->rx_ip_align = |
2586 | NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0; | |
43a3739d JC |
2587 | efx->rx_packet_hash_offset = |
2588 | efx->type->rx_hash_offset - efx->type->rx_prefix_size; | |
bd9a265d JC |
2589 | efx->rx_packet_ts_offset = |
2590 | efx->type->rx_ts_offset - efx->type->rx_prefix_size; | |
8ceee660 BH |
2591 | spin_lock_init(&efx->stats_lock); |
2592 | mutex_init(&efx->mac_lock); | |
2593 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2594 | efx->mdio.dev = net_dev; |
766ca0fa | 2595 | INIT_WORK(&efx->mac_work, efx_mac_work); |
9f2cb71c | 2596 | init_waitqueue_head(&efx->flush_wq); |
8ceee660 BH |
2597 | |
2598 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2599 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2600 | if (!efx->channel[i]) | |
2601 | goto fail; | |
d8291187 BH |
2602 | efx->msi_context[i].efx = efx; |
2603 | efx->msi_context[i].index = i; | |
8ceee660 BH |
2604 | } |
2605 | ||
8ceee660 BH |
2606 | /* Higher numbered interrupt modes are less capable! */ |
2607 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2608 | interrupt_mode); | |
2609 | ||
6977dc63 BH |
2610 | /* Would be good to use the net_dev name, but we're too early */ |
2611 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2612 | pci_name(pci_dev)); | |
2613 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2614 | if (!efx->workqueue) |
4642610c | 2615 | goto fail; |
8d9853d9 | 2616 | |
8ceee660 | 2617 | return 0; |
4642610c BH |
2618 | |
2619 | fail: | |
2620 | efx_fini_struct(efx); | |
2621 | return -ENOMEM; | |
8ceee660 BH |
2622 | } |
2623 | ||
2624 | static void efx_fini_struct(struct efx_nic *efx) | |
2625 | { | |
8313aca3 BH |
2626 | int i; |
2627 | ||
2628 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2629 | kfree(efx->channel[i]); | |
2630 | ||
ef215e64 BH |
2631 | kfree(efx->vpd_sn); |
2632 | ||
8ceee660 BH |
2633 | if (efx->workqueue) { |
2634 | destroy_workqueue(efx->workqueue); | |
2635 | efx->workqueue = NULL; | |
2636 | } | |
2637 | } | |
2638 | ||
2639 | /************************************************************************** | |
2640 | * | |
2641 | * PCI interface | |
2642 | * | |
2643 | **************************************************************************/ | |
2644 | ||
2645 | /* Main body of final NIC shutdown code | |
2646 | * This is called only at module unload (or hotplug removal). | |
2647 | */ | |
2648 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2649 | { | |
7153f623 BH |
2650 | /* Flush reset_work. It can no longer be scheduled since we |
2651 | * are not READY. | |
2652 | */ | |
2653 | BUG_ON(efx->state == STATE_READY); | |
2654 | cancel_work_sync(&efx->reset_work); | |
2655 | ||
d8291187 | 2656 | efx_disable_interrupts(efx); |
152b6a62 | 2657 | efx_nic_fini_interrupt(efx); |
8ceee660 | 2658 | efx_fini_port(efx); |
ef2b90ee | 2659 | efx->type->fini(efx); |
8ceee660 BH |
2660 | efx_fini_napi(efx); |
2661 | efx_remove_all(efx); | |
2662 | } | |
2663 | ||
2664 | /* Final NIC shutdown | |
2665 | * This is called only at module unload (or hotplug removal). | |
2666 | */ | |
2667 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2668 | { | |
2669 | struct efx_nic *efx; | |
2670 | ||
2671 | efx = pci_get_drvdata(pci_dev); | |
2672 | if (!efx) | |
2673 | return; | |
2674 | ||
2675 | /* Mark the NIC as fini, then stop the interface */ | |
2676 | rtnl_lock(); | |
8ceee660 | 2677 | dev_close(efx->net_dev); |
d8291187 | 2678 | efx_disable_interrupts(efx); |
8ceee660 BH |
2679 | rtnl_unlock(); |
2680 | ||
cd2d5b52 | 2681 | efx_sriov_fini(efx); |
8ceee660 BH |
2682 | efx_unregister_netdev(efx); |
2683 | ||
7dde596e BH |
2684 | efx_mtd_remove(efx); |
2685 | ||
8ceee660 BH |
2686 | efx_pci_remove_main(efx); |
2687 | ||
8ceee660 | 2688 | efx_fini_io(efx); |
62776d03 | 2689 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 | 2690 | |
8ceee660 | 2691 | efx_fini_struct(efx); |
3de4e301 | 2692 | pci_set_drvdata(pci_dev, NULL); |
8ceee660 | 2693 | free_netdev(efx->net_dev); |
626950db AR |
2694 | |
2695 | pci_disable_pcie_error_reporting(pci_dev); | |
8ceee660 BH |
2696 | }; |
2697 | ||
460eeaa0 BH |
2698 | /* NIC VPD information |
2699 | * Called during probe to display the part number of the | |
2700 | * installed NIC. VPD is potentially very large but this should | |
2701 | * always appear within the first 512 bytes. | |
2702 | */ | |
2703 | #define SFC_VPD_LEN 512 | |
ef215e64 | 2704 | static void efx_probe_vpd_strings(struct efx_nic *efx) |
460eeaa0 BH |
2705 | { |
2706 | struct pci_dev *dev = efx->pci_dev; | |
2707 | char vpd_data[SFC_VPD_LEN]; | |
2708 | ssize_t vpd_size; | |
ef215e64 | 2709 | int ro_start, ro_size, i, j; |
460eeaa0 BH |
2710 | |
2711 | /* Get the vpd data from the device */ | |
2712 | vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); | |
2713 | if (vpd_size <= 0) { | |
2714 | netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); | |
2715 | return; | |
2716 | } | |
2717 | ||
2718 | /* Get the Read only section */ | |
ef215e64 BH |
2719 | ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); |
2720 | if (ro_start < 0) { | |
460eeaa0 BH |
2721 | netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); |
2722 | return; | |
2723 | } | |
2724 | ||
ef215e64 BH |
2725 | ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]); |
2726 | j = ro_size; | |
2727 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
460eeaa0 BH |
2728 | if (i + j > vpd_size) |
2729 | j = vpd_size - i; | |
2730 | ||
2731 | /* Get the Part number */ | |
2732 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); | |
2733 | if (i < 0) { | |
2734 | netif_err(efx, drv, efx->net_dev, "Part number not found\n"); | |
2735 | return; | |
2736 | } | |
2737 | ||
2738 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
2739 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
2740 | if (i + j > vpd_size) { | |
2741 | netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); | |
2742 | return; | |
2743 | } | |
2744 | ||
2745 | netif_info(efx, drv, efx->net_dev, | |
2746 | "Part Number : %.*s\n", j, &vpd_data[i]); | |
ef215e64 BH |
2747 | |
2748 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
2749 | j = ro_size; | |
2750 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN"); | |
2751 | if (i < 0) { | |
2752 | netif_err(efx, drv, efx->net_dev, "Serial number not found\n"); | |
2753 | return; | |
2754 | } | |
2755 | ||
2756 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
2757 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
2758 | if (i + j > vpd_size) { | |
2759 | netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n"); | |
2760 | return; | |
2761 | } | |
2762 | ||
2763 | efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL); | |
2764 | if (!efx->vpd_sn) | |
2765 | return; | |
2766 | ||
2767 | snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]); | |
460eeaa0 BH |
2768 | } |
2769 | ||
2770 | ||
8ceee660 BH |
2771 | /* Main body of NIC initialisation |
2772 | * This is called at module load (or hotplug insertion, theoretically). | |
2773 | */ | |
2774 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2775 | { | |
2776 | int rc; | |
2777 | ||
2778 | /* Do start-of-day initialisation */ | |
2779 | rc = efx_probe_all(efx); | |
2780 | if (rc) | |
2781 | goto fail1; | |
2782 | ||
e8f14992 | 2783 | efx_init_napi(efx); |
8ceee660 | 2784 | |
ef2b90ee | 2785 | rc = efx->type->init(efx); |
8ceee660 | 2786 | if (rc) { |
62776d03 BH |
2787 | netif_err(efx, probe, efx->net_dev, |
2788 | "failed to initialise NIC\n"); | |
278c0621 | 2789 | goto fail3; |
8ceee660 BH |
2790 | } |
2791 | ||
2792 | rc = efx_init_port(efx); | |
2793 | if (rc) { | |
62776d03 BH |
2794 | netif_err(efx, probe, efx->net_dev, |
2795 | "failed to initialise port\n"); | |
278c0621 | 2796 | goto fail4; |
8ceee660 BH |
2797 | } |
2798 | ||
152b6a62 | 2799 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2800 | if (rc) |
278c0621 | 2801 | goto fail5; |
261e4d96 JC |
2802 | rc = efx_enable_interrupts(efx); |
2803 | if (rc) | |
2804 | goto fail6; | |
8ceee660 BH |
2805 | |
2806 | return 0; | |
2807 | ||
261e4d96 JC |
2808 | fail6: |
2809 | efx_nic_fini_interrupt(efx); | |
278c0621 | 2810 | fail5: |
8ceee660 | 2811 | efx_fini_port(efx); |
8ceee660 | 2812 | fail4: |
ef2b90ee | 2813 | efx->type->fini(efx); |
8ceee660 BH |
2814 | fail3: |
2815 | efx_fini_napi(efx); | |
8ceee660 BH |
2816 | efx_remove_all(efx); |
2817 | fail1: | |
2818 | return rc; | |
2819 | } | |
2820 | ||
2821 | /* NIC initialisation | |
2822 | * | |
2823 | * This is called at module load (or hotplug insertion, | |
73ba7b68 | 2824 | * theoretically). It sets up PCI mappings, resets the NIC, |
8ceee660 BH |
2825 | * sets up and registers the network devices with the kernel and hooks |
2826 | * the interrupt service routine. It does not prepare the device for | |
2827 | * transmission; this is left to the first time one of the network | |
2828 | * interfaces is brought up (i.e. efx_net_open). | |
2829 | */ | |
87d1fc11 | 2830 | static int efx_pci_probe(struct pci_dev *pci_dev, |
1dd06ae8 | 2831 | const struct pci_device_id *entry) |
8ceee660 | 2832 | { |
8ceee660 BH |
2833 | struct net_device *net_dev; |
2834 | struct efx_nic *efx; | |
fadac6aa | 2835 | int rc; |
8ceee660 BH |
2836 | |
2837 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2838 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2839 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2840 | if (!net_dev) |
2841 | return -ENOMEM; | |
adeb15aa BH |
2842 | efx = netdev_priv(net_dev); |
2843 | efx->type = (const struct efx_nic_type *) entry->driver_data; | |
2844 | net_dev->features |= (efx->type->offload_features | NETIF_F_SG | | |
97bc5415 | 2845 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 2846 | NETIF_F_RXCSUM); |
adeb15aa | 2847 | if (efx->type->offload_features & NETIF_F_V6_CSUM) |
738a8f4b | 2848 | net_dev->features |= NETIF_F_TSO6; |
28506563 BH |
2849 | /* Mask for features that also apply to VLAN devices */ |
2850 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
2851 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
2852 | NETIF_F_RXCSUM); | |
2853 | /* All offloads can be toggled */ | |
2854 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
8ceee660 | 2855 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2856 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
adeb15aa | 2857 | rc = efx_init_struct(efx, pci_dev, net_dev); |
8ceee660 BH |
2858 | if (rc) |
2859 | goto fail1; | |
2860 | ||
62776d03 | 2861 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 2862 | "Solarflare NIC detected\n"); |
8ceee660 | 2863 | |
ef215e64 | 2864 | efx_probe_vpd_strings(efx); |
460eeaa0 | 2865 | |
8ceee660 BH |
2866 | /* Set up basic I/O (BAR mappings etc) */ |
2867 | rc = efx_init_io(efx); | |
2868 | if (rc) | |
2869 | goto fail2; | |
2870 | ||
fadac6aa | 2871 | rc = efx_pci_probe_main(efx); |
fadac6aa BH |
2872 | if (rc) |
2873 | goto fail3; | |
8ceee660 | 2874 | |
8ceee660 BH |
2875 | rc = efx_register_netdev(efx); |
2876 | if (rc) | |
fadac6aa | 2877 | goto fail4; |
8ceee660 | 2878 | |
cd2d5b52 BH |
2879 | rc = efx_sriov_init(efx); |
2880 | if (rc) | |
2881 | netif_err(efx, probe, efx->net_dev, | |
2882 | "SR-IOV can't be enabled rc %d\n", rc); | |
2883 | ||
62776d03 | 2884 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 | 2885 | |
7c43161c | 2886 | /* Try to create MTDs, but allow this to fail */ |
a5211bb5 | 2887 | rtnl_lock(); |
7c43161c | 2888 | rc = efx_mtd_probe(efx); |
a5211bb5 | 2889 | rtnl_unlock(); |
7c43161c BH |
2890 | if (rc) |
2891 | netif_warn(efx, probe, efx->net_dev, | |
2892 | "failed to create MTDs (%d)\n", rc); | |
2893 | ||
626950db AR |
2894 | rc = pci_enable_pcie_error_reporting(pci_dev); |
2895 | if (rc && rc != -EINVAL) | |
2896 | netif_warn(efx, probe, efx->net_dev, | |
2897 | "pci_enable_pcie_error_reporting failed (%d)\n", rc); | |
2898 | ||
8ceee660 BH |
2899 | return 0; |
2900 | ||
8ceee660 | 2901 | fail4: |
fadac6aa | 2902 | efx_pci_remove_main(efx); |
8ceee660 BH |
2903 | fail3: |
2904 | efx_fini_io(efx); | |
2905 | fail2: | |
2906 | efx_fini_struct(efx); | |
2907 | fail1: | |
3de4e301 | 2908 | pci_set_drvdata(pci_dev, NULL); |
5e2a911c | 2909 | WARN_ON(rc > 0); |
62776d03 | 2910 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2911 | free_netdev(net_dev); |
2912 | return rc; | |
2913 | } | |
2914 | ||
89c758fa BH |
2915 | static int efx_pm_freeze(struct device *dev) |
2916 | { | |
2917 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2918 | ||
61da026d BH |
2919 | rtnl_lock(); |
2920 | ||
6032fb56 BH |
2921 | if (efx->state != STATE_DISABLED) { |
2922 | efx->state = STATE_UNINIT; | |
89c758fa | 2923 | |
c2f3b8e3 | 2924 | efx_device_detach_sync(efx); |
89c758fa | 2925 | |
6032fb56 | 2926 | efx_stop_all(efx); |
d8291187 | 2927 | efx_disable_interrupts(efx); |
6032fb56 | 2928 | } |
89c758fa | 2929 | |
61da026d BH |
2930 | rtnl_unlock(); |
2931 | ||
89c758fa BH |
2932 | return 0; |
2933 | } | |
2934 | ||
2935 | static int efx_pm_thaw(struct device *dev) | |
2936 | { | |
261e4d96 | 2937 | int rc; |
89c758fa BH |
2938 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); |
2939 | ||
61da026d BH |
2940 | rtnl_lock(); |
2941 | ||
6032fb56 | 2942 | if (efx->state != STATE_DISABLED) { |
261e4d96 JC |
2943 | rc = efx_enable_interrupts(efx); |
2944 | if (rc) | |
2945 | goto fail; | |
89c758fa | 2946 | |
6032fb56 BH |
2947 | mutex_lock(&efx->mac_lock); |
2948 | efx->phy_op->reconfigure(efx); | |
2949 | mutex_unlock(&efx->mac_lock); | |
89c758fa | 2950 | |
6032fb56 | 2951 | efx_start_all(efx); |
89c758fa | 2952 | |
6032fb56 | 2953 | netif_device_attach(efx->net_dev); |
89c758fa | 2954 | |
6032fb56 | 2955 | efx->state = STATE_READY; |
89c758fa | 2956 | |
6032fb56 BH |
2957 | efx->type->resume_wol(efx); |
2958 | } | |
89c758fa | 2959 | |
61da026d BH |
2960 | rtnl_unlock(); |
2961 | ||
319ba649 SH |
2962 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2963 | queue_work(reset_workqueue, &efx->reset_work); | |
2964 | ||
89c758fa | 2965 | return 0; |
261e4d96 JC |
2966 | |
2967 | fail: | |
2968 | rtnl_unlock(); | |
2969 | ||
2970 | return rc; | |
89c758fa BH |
2971 | } |
2972 | ||
2973 | static int efx_pm_poweroff(struct device *dev) | |
2974 | { | |
2975 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2976 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2977 | ||
2978 | efx->type->fini(efx); | |
2979 | ||
a7d529ae | 2980 | efx->reset_pending = 0; |
89c758fa BH |
2981 | |
2982 | pci_save_state(pci_dev); | |
2983 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2984 | } | |
2985 | ||
2986 | /* Used for both resume and restore */ | |
2987 | static int efx_pm_resume(struct device *dev) | |
2988 | { | |
2989 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2990 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2991 | int rc; | |
2992 | ||
2993 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2994 | if (rc) | |
2995 | return rc; | |
2996 | pci_restore_state(pci_dev); | |
2997 | rc = pci_enable_device(pci_dev); | |
2998 | if (rc) | |
2999 | return rc; | |
3000 | pci_set_master(efx->pci_dev); | |
3001 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
3002 | if (rc) | |
3003 | return rc; | |
3004 | rc = efx->type->init(efx); | |
3005 | if (rc) | |
3006 | return rc; | |
261e4d96 JC |
3007 | rc = efx_pm_thaw(dev); |
3008 | return rc; | |
89c758fa BH |
3009 | } |
3010 | ||
3011 | static int efx_pm_suspend(struct device *dev) | |
3012 | { | |
3013 | int rc; | |
3014 | ||
3015 | efx_pm_freeze(dev); | |
3016 | rc = efx_pm_poweroff(dev); | |
3017 | if (rc) | |
3018 | efx_pm_resume(dev); | |
3019 | return rc; | |
3020 | } | |
3021 | ||
18e83e4c | 3022 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
3023 | .suspend = efx_pm_suspend, |
3024 | .resume = efx_pm_resume, | |
3025 | .freeze = efx_pm_freeze, | |
3026 | .thaw = efx_pm_thaw, | |
3027 | .poweroff = efx_pm_poweroff, | |
3028 | .restore = efx_pm_resume, | |
3029 | }; | |
3030 | ||
626950db AR |
3031 | /* A PCI error affecting this device was detected. |
3032 | * At this point MMIO and DMA may be disabled. | |
3033 | * Stop the software path and request a slot reset. | |
3034 | */ | |
debd0034 | 3035 | static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev, |
3036 | enum pci_channel_state state) | |
626950db AR |
3037 | { |
3038 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; | |
3039 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3040 | ||
3041 | if (state == pci_channel_io_perm_failure) | |
3042 | return PCI_ERS_RESULT_DISCONNECT; | |
3043 | ||
3044 | rtnl_lock(); | |
3045 | ||
3046 | if (efx->state != STATE_DISABLED) { | |
3047 | efx->state = STATE_RECOVERY; | |
3048 | efx->reset_pending = 0; | |
3049 | ||
3050 | efx_device_detach_sync(efx); | |
3051 | ||
3052 | efx_stop_all(efx); | |
d8291187 | 3053 | efx_disable_interrupts(efx); |
626950db AR |
3054 | |
3055 | status = PCI_ERS_RESULT_NEED_RESET; | |
3056 | } else { | |
3057 | /* If the interface is disabled we don't want to do anything | |
3058 | * with it. | |
3059 | */ | |
3060 | status = PCI_ERS_RESULT_RECOVERED; | |
3061 | } | |
3062 | ||
3063 | rtnl_unlock(); | |
3064 | ||
3065 | pci_disable_device(pdev); | |
3066 | ||
3067 | return status; | |
3068 | } | |
3069 | ||
3070 | /* Fake a successfull reset, which will be performed later in efx_io_resume. */ | |
debd0034 | 3071 | static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev) |
626950db AR |
3072 | { |
3073 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3074 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; | |
3075 | int rc; | |
3076 | ||
3077 | if (pci_enable_device(pdev)) { | |
3078 | netif_err(efx, hw, efx->net_dev, | |
3079 | "Cannot re-enable PCI device after reset.\n"); | |
3080 | status = PCI_ERS_RESULT_DISCONNECT; | |
3081 | } | |
3082 | ||
3083 | rc = pci_cleanup_aer_uncorrect_error_status(pdev); | |
3084 | if (rc) { | |
3085 | netif_err(efx, hw, efx->net_dev, | |
3086 | "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc); | |
3087 | /* Non-fatal error. Continue. */ | |
3088 | } | |
3089 | ||
3090 | return status; | |
3091 | } | |
3092 | ||
3093 | /* Perform the actual reset and resume I/O operations. */ | |
3094 | static void efx_io_resume(struct pci_dev *pdev) | |
3095 | { | |
3096 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3097 | int rc; | |
3098 | ||
3099 | rtnl_lock(); | |
3100 | ||
3101 | if (efx->state == STATE_DISABLED) | |
3102 | goto out; | |
3103 | ||
3104 | rc = efx_reset(efx, RESET_TYPE_ALL); | |
3105 | if (rc) { | |
3106 | netif_err(efx, hw, efx->net_dev, | |
3107 | "efx_reset failed after PCI error (%d)\n", rc); | |
3108 | } else { | |
3109 | efx->state = STATE_READY; | |
3110 | netif_dbg(efx, hw, efx->net_dev, | |
3111 | "Done resetting and resuming IO after PCI error.\n"); | |
3112 | } | |
3113 | ||
3114 | out: | |
3115 | rtnl_unlock(); | |
3116 | } | |
3117 | ||
3118 | /* For simplicity and reliability, we always require a slot reset and try to | |
3119 | * reset the hardware when a pci error affecting the device is detected. | |
3120 | * We leave both the link_reset and mmio_enabled callback unimplemented: | |
3121 | * with our request for slot reset the mmio_enabled callback will never be | |
3122 | * called, and the link_reset callback is not used by AER or EEH mechanisms. | |
3123 | */ | |
3124 | static struct pci_error_handlers efx_err_handlers = { | |
3125 | .error_detected = efx_io_error_detected, | |
3126 | .slot_reset = efx_io_slot_reset, | |
3127 | .resume = efx_io_resume, | |
3128 | }; | |
3129 | ||
8ceee660 | 3130 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 3131 | .name = KBUILD_MODNAME, |
8ceee660 BH |
3132 | .id_table = efx_pci_table, |
3133 | .probe = efx_pci_probe, | |
3134 | .remove = efx_pci_remove, | |
89c758fa | 3135 | .driver.pm = &efx_pm_ops, |
626950db | 3136 | .err_handler = &efx_err_handlers, |
8ceee660 BH |
3137 | }; |
3138 | ||
3139 | /************************************************************************** | |
3140 | * | |
3141 | * Kernel module interface | |
3142 | * | |
3143 | *************************************************************************/ | |
3144 | ||
3145 | module_param(interrupt_mode, uint, 0444); | |
3146 | MODULE_PARM_DESC(interrupt_mode, | |
3147 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
3148 | ||
3149 | static int __init efx_init_module(void) | |
3150 | { | |
3151 | int rc; | |
3152 | ||
3153 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
3154 | ||
3155 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
3156 | if (rc) | |
3157 | goto err_notifier; | |
3158 | ||
cd2d5b52 BH |
3159 | rc = efx_init_sriov(); |
3160 | if (rc) | |
3161 | goto err_sriov; | |
3162 | ||
1ab00629 SH |
3163 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
3164 | if (!reset_workqueue) { | |
3165 | rc = -ENOMEM; | |
3166 | goto err_reset; | |
3167 | } | |
8ceee660 BH |
3168 | |
3169 | rc = pci_register_driver(&efx_pci_driver); | |
3170 | if (rc < 0) | |
3171 | goto err_pci; | |
3172 | ||
3173 | return 0; | |
3174 | ||
3175 | err_pci: | |
1ab00629 SH |
3176 | destroy_workqueue(reset_workqueue); |
3177 | err_reset: | |
cd2d5b52 BH |
3178 | efx_fini_sriov(); |
3179 | err_sriov: | |
8ceee660 BH |
3180 | unregister_netdevice_notifier(&efx_netdev_notifier); |
3181 | err_notifier: | |
3182 | return rc; | |
3183 | } | |
3184 | ||
3185 | static void __exit efx_exit_module(void) | |
3186 | { | |
3187 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
3188 | ||
3189 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 3190 | destroy_workqueue(reset_workqueue); |
cd2d5b52 | 3191 | efx_fini_sriov(); |
8ceee660 BH |
3192 | unregister_netdevice_notifier(&efx_netdev_notifier); |
3193 | ||
3194 | } | |
3195 | ||
3196 | module_init(efx_init_module); | |
3197 | module_exit(efx_exit_module); | |
3198 | ||
906bb26c BH |
3199 | MODULE_AUTHOR("Solarflare Communications and " |
3200 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
3201 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
3202 | MODULE_LICENSE("GPL"); | |
3203 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |