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1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2006-2010 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #ifndef EFX_EFX_H | |
12 | #define EFX_EFX_H | |
13 | ||
14 | #include "net_driver.h" | |
64eebcfd | 15 | #include "filter.h" |
8ceee660 | 16 | |
dc803df8 BH |
17 | /* Solarstorm controllers use BAR 0 for I/O space and BAR 2(&3) for memory */ |
18 | #define EFX_MEM_BAR 2 | |
19 | ||
8ceee660 | 20 | /* TX */ |
f5e7adc3 BH |
21 | extern int efx_probe_tx_queue(struct efx_tx_queue *tx_queue); |
22 | extern void efx_remove_tx_queue(struct efx_tx_queue *tx_queue); | |
23 | extern void efx_init_tx_queue(struct efx_tx_queue *tx_queue); | |
60031fcc | 24 | extern void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue); |
f5e7adc3 BH |
25 | extern void efx_fini_tx_queue(struct efx_tx_queue *tx_queue); |
26 | extern void efx_release_tx_buffers(struct efx_tx_queue *tx_queue); | |
27 | extern netdev_tx_t | |
28 | efx_hard_start_xmit(struct sk_buff *skb, struct net_device *net_dev); | |
29 | extern netdev_tx_t | |
30 | efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb); | |
59cf09cc | 31 | extern void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index); |
94b274bf | 32 | extern int efx_setup_tc(struct net_device *net_dev, u8 num_tc); |
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33 | |
34 | /* RX */ | |
f5e7adc3 BH |
35 | extern int efx_probe_rx_queue(struct efx_rx_queue *rx_queue); |
36 | extern void efx_remove_rx_queue(struct efx_rx_queue *rx_queue); | |
37 | extern void efx_init_rx_queue(struct efx_rx_queue *rx_queue); | |
38 | extern void efx_fini_rx_queue(struct efx_rx_queue *rx_queue); | |
39 | extern void efx_rx_strategy(struct efx_channel *channel); | |
40 | extern void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue); | |
90d683af | 41 | extern void efx_rx_slow_fill(unsigned long context); |
f5e7adc3 BH |
42 | extern void __efx_rx_packet(struct efx_channel *channel, |
43 | struct efx_rx_buffer *rx_buf, bool checksummed); | |
8ceee660 | 44 | extern void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index, |
dc8cfa55 | 45 | unsigned int len, bool checksummed, bool discard); |
90d683af | 46 | extern void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue); |
ecc910f5 SH |
47 | |
48 | #define EFX_MAX_DMAQ_SIZE 4096UL | |
49 | #define EFX_DEFAULT_DMAQ_SIZE 1024UL | |
50 | #define EFX_MIN_DMAQ_SIZE 512UL | |
51 | ||
52 | #define EFX_MAX_EVQ_SIZE 16384UL | |
53 | #define EFX_MIN_EVQ_SIZE 512UL | |
8ceee660 | 54 | |
4642610c BH |
55 | /* The smallest [rt]xq_entries that the driver supports. Callers of |
56 | * efx_wake_queue() assume that they can subsequently send at least one | |
57 | * skb. Falcon/A1 may require up to three descriptors per skb_frag. */ | |
58 | #define EFX_MIN_RING_SIZE (roundup_pow_of_two(2 * 3 * MAX_SKB_FRAGS)) | |
59 | ||
64eebcfd BH |
60 | /* Filters */ |
61 | extern int efx_probe_filters(struct efx_nic *efx); | |
62 | extern void efx_restore_filters(struct efx_nic *efx); | |
63 | extern void efx_remove_filters(struct efx_nic *efx); | |
3532650f | 64 | extern s32 efx_filter_insert_filter(struct efx_nic *efx, |
64eebcfd BH |
65 | struct efx_filter_spec *spec, |
66 | bool replace); | |
1a6281ac BH |
67 | extern int efx_filter_remove_id_safe(struct efx_nic *efx, |
68 | enum efx_filter_priority priority, | |
69 | u32 filter_id); | |
70 | extern int efx_filter_get_filter_safe(struct efx_nic *efx, | |
71 | enum efx_filter_priority priority, | |
72 | u32 filter_id, struct efx_filter_spec *); | |
8891681a BH |
73 | extern void efx_filter_clear_rx(struct efx_nic *efx, |
74 | enum efx_filter_priority priority); | |
1a6281ac BH |
75 | extern u32 efx_filter_count_rx_used(struct efx_nic *efx, |
76 | enum efx_filter_priority priority); | |
77 | extern u32 efx_filter_get_rx_id_limit(struct efx_nic *efx); | |
78 | extern s32 efx_filter_get_rx_ids(struct efx_nic *efx, | |
79 | enum efx_filter_priority priority, | |
80 | u32 *buf, u32 size); | |
64d8ad6d BH |
81 | #ifdef CONFIG_RFS_ACCEL |
82 | extern int efx_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb, | |
83 | u16 rxq_index, u32 flow_id); | |
84 | extern bool __efx_filter_rfs_expire(struct efx_nic *efx, unsigned quota); | |
85 | static inline void efx_filter_rfs_expire(struct efx_channel *channel) | |
86 | { | |
87 | if (channel->rfs_filters_added >= 60 && | |
88 | __efx_filter_rfs_expire(channel->efx, 100)) | |
89 | channel->rfs_filters_added -= 60; | |
90 | } | |
91 | #define efx_filter_rfs_enabled() 1 | |
92 | #else | |
93 | static inline void efx_filter_rfs_expire(struct efx_channel *channel) {} | |
94 | #define efx_filter_rfs_enabled() 0 | |
95 | #endif | |
64eebcfd | 96 | |
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97 | /* Channels */ |
98 | extern void efx_process_channel_now(struct efx_channel *channel); | |
4642610c BH |
99 | extern int |
100 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries); | |
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101 | |
102 | /* Ports */ | |
d3245b28 BH |
103 | extern int efx_reconfigure_port(struct efx_nic *efx); |
104 | extern int __efx_reconfigure_port(struct efx_nic *efx); | |
8c8661e4 | 105 | |
f5e7adc3 | 106 | /* Ethtool support */ |
f5e7adc3 BH |
107 | extern const struct ethtool_ops efx_ethtool_ops; |
108 | ||
8c8661e4 | 109 | /* Reset handling */ |
eb9f6744 | 110 | extern int efx_reset(struct efx_nic *efx, enum reset_type method); |
d3245b28 BH |
111 | extern void efx_reset_down(struct efx_nic *efx, enum reset_type method); |
112 | extern int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok); | |
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113 | |
114 | /* Global */ | |
115 | extern void efx_schedule_reset(struct efx_nic *efx, enum reset_type type); | |
9e393b30 BH |
116 | extern int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
117 | unsigned int rx_usecs, bool rx_adaptive, | |
118 | bool rx_may_override_tx); | |
a0c4faf5 BH |
119 | extern void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
120 | unsigned int *rx_usecs, bool *rx_adaptive); | |
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121 | |
122 | /* Dummy PHY ops for PHY drivers */ | |
123 | extern int efx_port_dummy_op_int(struct efx_nic *efx); | |
124 | extern void efx_port_dummy_op_void(struct efx_nic *efx); | |
d215697f | 125 | |
8ceee660 | 126 | |
f4150724 BH |
127 | /* MTD */ |
128 | #ifdef CONFIG_SFC_MTD | |
129 | extern int efx_mtd_probe(struct efx_nic *efx); | |
130 | extern void efx_mtd_rename(struct efx_nic *efx); | |
131 | extern void efx_mtd_remove(struct efx_nic *efx); | |
132 | #else | |
133 | static inline int efx_mtd_probe(struct efx_nic *efx) { return 0; } | |
134 | static inline void efx_mtd_rename(struct efx_nic *efx) {} | |
135 | static inline void efx_mtd_remove(struct efx_nic *efx) {} | |
136 | #endif | |
8ceee660 | 137 | |
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138 | static inline void efx_schedule_channel(struct efx_channel *channel) |
139 | { | |
62776d03 BH |
140 | netif_vdbg(channel->efx, intr, channel->efx->net_dev, |
141 | "channel %d scheduling NAPI poll on CPU%d\n", | |
142 | channel->channel, raw_smp_processor_id()); | |
dc8cfa55 | 143 | channel->work_pending = true; |
8ceee660 | 144 | |
288379f0 | 145 | napi_schedule(&channel->napi_str); |
8ceee660 BH |
146 | } |
147 | ||
fdaa9aed | 148 | extern void efx_link_status_changed(struct efx_nic *efx); |
d3245b28 | 149 | extern void efx_link_set_advertising(struct efx_nic *efx, u32); |
b5626946 | 150 | extern void efx_link_set_wanted_fc(struct efx_nic *efx, u8); |
fdaa9aed | 151 | |
8ceee660 | 152 | #endif /* EFX_EFX_H */ |