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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2006-2010 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/seq_file.h> | |
37b5a603 | 16 | #include <linux/i2c.h> |
f31a45d2 | 17 | #include <linux/mii.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
8ceee660 BH |
19 | #include "net_driver.h" |
20 | #include "bitfield.h" | |
21 | #include "efx.h" | |
8ceee660 | 22 | #include "spi.h" |
744093c9 | 23 | #include "nic.h" |
3e6c4538 | 24 | #include "regs.h" |
12d00cad | 25 | #include "io.h" |
8ceee660 | 26 | #include "phy.h" |
8ceee660 BH |
27 | #include "workarounds.h" |
28 | ||
8986352a | 29 | /* Hardware control for SFC4000 (aka Falcon). */ |
8ceee660 | 30 | |
2f7f5730 BH |
31 | static const unsigned int |
32 | /* "Large" EEPROM device: Atmel AT25640 or similar | |
33 | * 8 KB, 16-bit address, 32 B write block */ | |
34 | large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN) | |
35 | | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
36 | | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)), | |
37 | /* Default flash device: Atmel AT25F1024 | |
38 | * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */ | |
39 | default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN) | |
40 | | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
41 | | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN) | |
42 | | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) | |
43 | | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); | |
44 | ||
8ceee660 BH |
45 | /************************************************************************** |
46 | * | |
47 | * I2C bus - this is a bit-bashing interface using GPIO pins | |
48 | * Note that it uses the output enables to tristate the outputs | |
49 | * SDA is the data pin and SCL is the clock | |
50 | * | |
51 | ************************************************************************** | |
52 | */ | |
37b5a603 | 53 | static void falcon_setsda(void *data, int state) |
8ceee660 | 54 | { |
37b5a603 | 55 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
56 | efx_oword_t reg; |
57 | ||
12d00cad | 58 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 59 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); |
12d00cad | 60 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
8ceee660 BH |
61 | } |
62 | ||
37b5a603 | 63 | static void falcon_setscl(void *data, int state) |
8ceee660 | 64 | { |
37b5a603 | 65 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
66 | efx_oword_t reg; |
67 | ||
12d00cad | 68 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 69 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); |
12d00cad | 70 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
37b5a603 BH |
71 | } |
72 | ||
8e730c15 BH |
73 | static int falcon_getsda(void *data) |
74 | { | |
75 | struct efx_nic *efx = (struct efx_nic *)data; | |
76 | efx_oword_t reg; | |
8ceee660 | 77 | |
8e730c15 BH |
78 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
79 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); | |
80 | } | |
8ceee660 | 81 | |
8e730c15 BH |
82 | static int falcon_getscl(void *data) |
83 | { | |
84 | struct efx_nic *efx = (struct efx_nic *)data; | |
85 | efx_oword_t reg; | |
8ceee660 | 86 | |
8e730c15 BH |
87 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
88 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); | |
8ceee660 BH |
89 | } |
90 | ||
18e83e4c | 91 | static const struct i2c_algo_bit_data falcon_i2c_bit_operations = { |
8e730c15 BH |
92 | .setsda = falcon_setsda, |
93 | .setscl = falcon_setscl, | |
94 | .getsda = falcon_getsda, | |
95 | .getscl = falcon_getscl, | |
96 | .udelay = 5, | |
97 | /* Wait up to 50 ms for slave to let us pull SCL high */ | |
98 | .timeout = DIV_ROUND_UP(HZ, 20), | |
99 | }; | |
100 | ||
ef2b90ee | 101 | static void falcon_push_irq_moderation(struct efx_channel *channel) |
8ceee660 BH |
102 | { |
103 | efx_dword_t timer_cmd; | |
104 | struct efx_nic *efx = channel->efx; | |
105 | ||
9e393b30 BH |
106 | BUILD_BUG_ON(EFX_IRQ_MOD_MAX > (1 << FRF_AB_TC_TIMER_VAL_WIDTH)); |
107 | ||
8ceee660 BH |
108 | /* Set timer register */ |
109 | if (channel->irq_moderation) { | |
8ceee660 | 110 | EFX_POPULATE_DWORD_2(timer_cmd, |
3e6c4538 BH |
111 | FRF_AB_TC_TIMER_MODE, |
112 | FFE_BB_TIMER_MODE_INT_HLDOFF, | |
113 | FRF_AB_TC_TIMER_VAL, | |
0d86ebd8 | 114 | channel->irq_moderation - 1); |
8ceee660 BH |
115 | } else { |
116 | EFX_POPULATE_DWORD_2(timer_cmd, | |
3e6c4538 BH |
117 | FRF_AB_TC_TIMER_MODE, |
118 | FFE_BB_TIMER_MODE_DIS, | |
119 | FRF_AB_TC_TIMER_VAL, 0); | |
8ceee660 | 120 | } |
3e6c4538 | 121 | BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); |
12d00cad BH |
122 | efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, |
123 | channel->channel); | |
127e6e10 BH |
124 | } |
125 | ||
d3245b28 BH |
126 | static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx); |
127 | ||
127e6e10 BH |
128 | static void falcon_prepare_flush(struct efx_nic *efx) |
129 | { | |
130 | falcon_deconfigure_mac_wrapper(efx); | |
131 | ||
132 | /* Wait for the tx and rx fifo's to get to the next packet boundary | |
133 | * (~1ms without back-pressure), then to drain the remainder of the | |
134 | * fifo's at data path speeds (negligible), with a healthy margin. */ | |
135 | msleep(10); | |
6bc5d3a9 BH |
136 | } |
137 | ||
8ceee660 BH |
138 | /* Acknowledge a legacy interrupt from Falcon |
139 | * | |
140 | * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. | |
141 | * | |
142 | * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the | |
143 | * BIU. Interrupt acknowledge is read sensitive so must write instead | |
144 | * (then read to ensure the BIU collector is flushed) | |
145 | * | |
146 | * NB most hardware supports MSI interrupts | |
147 | */ | |
152b6a62 | 148 | inline void falcon_irq_ack_a1(struct efx_nic *efx) |
8ceee660 BH |
149 | { |
150 | efx_dword_t reg; | |
151 | ||
3e6c4538 | 152 | EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); |
12d00cad BH |
153 | efx_writed(efx, ®, FR_AA_INT_ACK_KER); |
154 | efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS); | |
8ceee660 BH |
155 | } |
156 | ||
8ceee660 | 157 | |
152b6a62 | 158 | irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) |
8ceee660 | 159 | { |
d3208b5e BH |
160 | struct efx_nic *efx = dev_id; |
161 | efx_oword_t *int_ker = efx->irq_status.addr; | |
8ceee660 BH |
162 | int syserr; |
163 | int queues; | |
164 | ||
165 | /* Check to see if this is our interrupt. If it isn't, we | |
166 | * exit without having touched the hardware. | |
167 | */ | |
168 | if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) { | |
62776d03 BH |
169 | netif_vdbg(efx, intr, efx->net_dev, |
170 | "IRQ %d on CPU %d not for me\n", irq, | |
171 | raw_smp_processor_id()); | |
8ceee660 BH |
172 | return IRQ_NONE; |
173 | } | |
174 | efx->last_irq_cpu = raw_smp_processor_id(); | |
62776d03 BH |
175 | netif_vdbg(efx, intr, efx->net_dev, |
176 | "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
177 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
8ceee660 | 178 | |
8ceee660 BH |
179 | /* Determine interrupting queues, clear interrupt status |
180 | * register and acknowledge the device interrupt. | |
181 | */ | |
674979d3 BH |
182 | BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS); |
183 | queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q); | |
63695459 SH |
184 | |
185 | /* Check to see if we have a serious error condition */ | |
186 | if (queues & (1U << efx->fatal_irq_level)) { | |
187 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); | |
188 | if (unlikely(syserr)) | |
189 | return efx_nic_fatal_interrupt(efx); | |
190 | } | |
191 | ||
8ceee660 BH |
192 | EFX_ZERO_OWORD(*int_ker); |
193 | wmb(); /* Ensure the vector is cleared before interrupt ack */ | |
194 | falcon_irq_ack_a1(efx); | |
195 | ||
8313aca3 BH |
196 | if (queues & 1) |
197 | efx_schedule_channel(efx_get_channel(efx, 0)); | |
198 | if (queues & 2) | |
199 | efx_schedule_channel(efx_get_channel(efx, 1)); | |
8ceee660 BH |
200 | return IRQ_HANDLED; |
201 | } | |
8ceee660 BH |
202 | /************************************************************************** |
203 | * | |
204 | * EEPROM/flash | |
205 | * | |
206 | ************************************************************************** | |
207 | */ | |
208 | ||
23d30f02 | 209 | #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t) |
8ceee660 | 210 | |
be4ea89c BH |
211 | static int falcon_spi_poll(struct efx_nic *efx) |
212 | { | |
213 | efx_oword_t reg; | |
12d00cad | 214 | efx_reado(efx, ®, FR_AB_EE_SPI_HCMD); |
3e6c4538 | 215 | return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; |
be4ea89c BH |
216 | } |
217 | ||
8ceee660 BH |
218 | /* Wait for SPI command completion */ |
219 | static int falcon_spi_wait(struct efx_nic *efx) | |
220 | { | |
be4ea89c BH |
221 | /* Most commands will finish quickly, so we start polling at |
222 | * very short intervals. Sometimes the command may have to | |
223 | * wait for VPD or expansion ROM access outside of our | |
224 | * control, so we allow up to 100 ms. */ | |
225 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10); | |
226 | int i; | |
227 | ||
228 | for (i = 0; i < 10; i++) { | |
229 | if (!falcon_spi_poll(efx)) | |
230 | return 0; | |
231 | udelay(10); | |
232 | } | |
8ceee660 | 233 | |
4a5b504d | 234 | for (;;) { |
be4ea89c | 235 | if (!falcon_spi_poll(efx)) |
8ceee660 | 236 | return 0; |
4a5b504d | 237 | if (time_after_eq(jiffies, timeout)) { |
62776d03 BH |
238 | netif_err(efx, hw, efx->net_dev, |
239 | "timed out waiting for SPI\n"); | |
4a5b504d BH |
240 | return -ETIMEDOUT; |
241 | } | |
be4ea89c | 242 | schedule_timeout_uninterruptible(1); |
4a5b504d | 243 | } |
8ceee660 BH |
244 | } |
245 | ||
76884835 | 246 | int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi, |
f4150724 | 247 | unsigned int command, int address, |
23d30f02 | 248 | const void *in, void *out, size_t len) |
8ceee660 | 249 | { |
4a5b504d BH |
250 | bool addressed = (address >= 0); |
251 | bool reading = (out != NULL); | |
8ceee660 BH |
252 | efx_oword_t reg; |
253 | int rc; | |
254 | ||
4a5b504d BH |
255 | /* Input validation */ |
256 | if (len > FALCON_SPI_MAX_LEN) | |
257 | return -EINVAL; | |
8ceee660 | 258 | |
be4ea89c BH |
259 | /* Check that previous command is not still running */ |
260 | rc = falcon_spi_poll(efx); | |
8ceee660 BH |
261 | if (rc) |
262 | return rc; | |
263 | ||
4a5b504d BH |
264 | /* Program address register, if we have an address */ |
265 | if (addressed) { | |
3e6c4538 | 266 | EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); |
12d00cad | 267 | efx_writeo(efx, ®, FR_AB_EE_SPI_HADR); |
4a5b504d BH |
268 | } |
269 | ||
270 | /* Program data register, if we have data */ | |
271 | if (in != NULL) { | |
272 | memcpy(®, in, len); | |
12d00cad | 273 | efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d | 274 | } |
8ceee660 | 275 | |
4a5b504d | 276 | /* Issue read/write command */ |
8ceee660 | 277 | EFX_POPULATE_OWORD_7(reg, |
3e6c4538 BH |
278 | FRF_AB_EE_SPI_HCMD_CMD_EN, 1, |
279 | FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id, | |
280 | FRF_AB_EE_SPI_HCMD_DABCNT, len, | |
281 | FRF_AB_EE_SPI_HCMD_READ, reading, | |
282 | FRF_AB_EE_SPI_HCMD_DUBCNT, 0, | |
283 | FRF_AB_EE_SPI_HCMD_ADBCNT, | |
4a5b504d | 284 | (addressed ? spi->addr_len : 0), |
3e6c4538 | 285 | FRF_AB_EE_SPI_HCMD_ENC, command); |
12d00cad | 286 | efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD); |
8ceee660 | 287 | |
4a5b504d | 288 | /* Wait for read/write to complete */ |
8ceee660 BH |
289 | rc = falcon_spi_wait(efx); |
290 | if (rc) | |
291 | return rc; | |
292 | ||
293 | /* Read data */ | |
4a5b504d | 294 | if (out != NULL) { |
12d00cad | 295 | efx_reado(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d BH |
296 | memcpy(out, ®, len); |
297 | } | |
298 | ||
8ceee660 BH |
299 | return 0; |
300 | } | |
301 | ||
23d30f02 BH |
302 | static size_t |
303 | falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start) | |
4a5b504d BH |
304 | { |
305 | return min(FALCON_SPI_MAX_LEN, | |
306 | (spi->block_size - (start & (spi->block_size - 1)))); | |
307 | } | |
308 | ||
309 | static inline u8 | |
310 | efx_spi_munge_command(const struct efx_spi_device *spi, | |
311 | const u8 command, const unsigned int address) | |
312 | { | |
313 | return command | (((address >> 8) & spi->munge_address) << 3); | |
314 | } | |
315 | ||
be4ea89c | 316 | /* Wait up to 10 ms for buffered write completion */ |
76884835 BH |
317 | int |
318 | falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi) | |
4a5b504d | 319 | { |
be4ea89c | 320 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100); |
4a5b504d | 321 | u8 status; |
be4ea89c | 322 | int rc; |
4a5b504d | 323 | |
be4ea89c | 324 | for (;;) { |
76884835 | 325 | rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL, |
4a5b504d BH |
326 | &status, sizeof(status)); |
327 | if (rc) | |
328 | return rc; | |
329 | if (!(status & SPI_STATUS_NRDY)) | |
330 | return 0; | |
be4ea89c | 331 | if (time_after_eq(jiffies, timeout)) { |
62776d03 BH |
332 | netif_err(efx, hw, efx->net_dev, |
333 | "SPI write timeout on device %d" | |
334 | " last status=0x%02x\n", | |
335 | spi->device_id, status); | |
be4ea89c BH |
336 | return -ETIMEDOUT; |
337 | } | |
338 | schedule_timeout_uninterruptible(1); | |
4a5b504d | 339 | } |
4a5b504d BH |
340 | } |
341 | ||
76884835 BH |
342 | int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi, |
343 | loff_t start, size_t len, size_t *retlen, u8 *buffer) | |
4a5b504d | 344 | { |
23d30f02 BH |
345 | size_t block_len, pos = 0; |
346 | unsigned int command; | |
4a5b504d BH |
347 | int rc = 0; |
348 | ||
349 | while (pos < len) { | |
23d30f02 | 350 | block_len = min(len - pos, FALCON_SPI_MAX_LEN); |
4a5b504d BH |
351 | |
352 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
76884835 | 353 | rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL, |
4a5b504d BH |
354 | buffer + pos, block_len); |
355 | if (rc) | |
356 | break; | |
357 | pos += block_len; | |
358 | ||
359 | /* Avoid locking up the system */ | |
360 | cond_resched(); | |
361 | if (signal_pending(current)) { | |
362 | rc = -EINTR; | |
363 | break; | |
364 | } | |
365 | } | |
366 | ||
367 | if (retlen) | |
368 | *retlen = pos; | |
369 | return rc; | |
370 | } | |
371 | ||
76884835 BH |
372 | int |
373 | falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi, | |
374 | loff_t start, size_t len, size_t *retlen, const u8 *buffer) | |
4a5b504d BH |
375 | { |
376 | u8 verify_buffer[FALCON_SPI_MAX_LEN]; | |
23d30f02 BH |
377 | size_t block_len, pos = 0; |
378 | unsigned int command; | |
4a5b504d BH |
379 | int rc = 0; |
380 | ||
381 | while (pos < len) { | |
76884835 | 382 | rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0); |
4a5b504d BH |
383 | if (rc) |
384 | break; | |
385 | ||
23d30f02 | 386 | block_len = min(len - pos, |
4a5b504d BH |
387 | falcon_spi_write_limit(spi, start + pos)); |
388 | command = efx_spi_munge_command(spi, SPI_WRITE, start + pos); | |
76884835 | 389 | rc = falcon_spi_cmd(efx, spi, command, start + pos, |
4a5b504d BH |
390 | buffer + pos, NULL, block_len); |
391 | if (rc) | |
392 | break; | |
393 | ||
76884835 | 394 | rc = falcon_spi_wait_write(efx, spi); |
4a5b504d BH |
395 | if (rc) |
396 | break; | |
397 | ||
398 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
76884835 | 399 | rc = falcon_spi_cmd(efx, spi, command, start + pos, |
4a5b504d BH |
400 | NULL, verify_buffer, block_len); |
401 | if (memcmp(verify_buffer, buffer + pos, block_len)) { | |
402 | rc = -EIO; | |
403 | break; | |
404 | } | |
405 | ||
406 | pos += block_len; | |
407 | ||
408 | /* Avoid locking up the system */ | |
409 | cond_resched(); | |
410 | if (signal_pending(current)) { | |
411 | rc = -EINTR; | |
412 | break; | |
413 | } | |
414 | } | |
415 | ||
416 | if (retlen) | |
417 | *retlen = pos; | |
418 | return rc; | |
419 | } | |
420 | ||
8ceee660 BH |
421 | /************************************************************************** |
422 | * | |
423 | * MAC wrapper | |
424 | * | |
425 | ************************************************************************** | |
426 | */ | |
177dfcd8 | 427 | |
ef2b90ee BH |
428 | static void falcon_push_multicast_hash(struct efx_nic *efx) |
429 | { | |
430 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
431 | ||
432 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
433 | ||
434 | efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0); | |
435 | efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1); | |
436 | } | |
437 | ||
d3245b28 | 438 | static void falcon_reset_macs(struct efx_nic *efx) |
8ceee660 | 439 | { |
d3245b28 BH |
440 | struct falcon_nic_data *nic_data = efx->nic_data; |
441 | efx_oword_t reg, mac_ctrl; | |
8ceee660 BH |
442 | int count; |
443 | ||
daeda630 | 444 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { |
177dfcd8 BH |
445 | /* It's not safe to use GLB_CTL_REG to reset the |
446 | * macs, so instead use the internal MAC resets | |
447 | */ | |
8fbca791 BH |
448 | EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); |
449 | efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); | |
450 | ||
451 | for (count = 0; count < 10000; count++) { | |
452 | efx_reado(efx, ®, FR_AB_XM_GLB_CFG); | |
453 | if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == | |
454 | 0) | |
455 | return; | |
456 | udelay(10); | |
177dfcd8 | 457 | } |
8fbca791 BH |
458 | |
459 | netif_err(efx, hw, efx->net_dev, | |
460 | "timed out waiting for XMAC core reset\n"); | |
177dfcd8 | 461 | } |
8ceee660 | 462 | |
d3245b28 BH |
463 | /* Mac stats will fail whist the TX fifo is draining */ |
464 | WARN_ON(nic_data->stats_disable_count == 0); | |
8ceee660 | 465 | |
d3245b28 BH |
466 | efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL); |
467 | EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1); | |
468 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); | |
8ceee660 | 469 | |
12d00cad | 470 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
471 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); |
472 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); | |
473 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); | |
12d00cad | 474 | efx_writeo(efx, ®, FR_AB_GLB_CTL); |
8ceee660 BH |
475 | |
476 | count = 0; | |
477 | while (1) { | |
12d00cad | 478 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
479 | if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && |
480 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && | |
481 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) { | |
62776d03 BH |
482 | netif_dbg(efx, hw, efx->net_dev, |
483 | "Completed MAC reset after %d loops\n", | |
484 | count); | |
8ceee660 BH |
485 | break; |
486 | } | |
487 | if (count > 20) { | |
62776d03 | 488 | netif_err(efx, hw, efx->net_dev, "MAC reset failed\n"); |
8ceee660 BH |
489 | break; |
490 | } | |
491 | count++; | |
492 | udelay(10); | |
493 | } | |
494 | ||
d3245b28 BH |
495 | /* Ensure the correct MAC is selected before statistics |
496 | * are re-enabled by the caller */ | |
497 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); | |
b7b40eeb | 498 | |
b7b40eeb | 499 | falcon_setup_xaui(efx); |
177dfcd8 BH |
500 | } |
501 | ||
502 | void falcon_drain_tx_fifo(struct efx_nic *efx) | |
503 | { | |
504 | efx_oword_t reg; | |
505 | ||
daeda630 | 506 | if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) || |
177dfcd8 BH |
507 | (efx->loopback_mode != LOOPBACK_NONE)) |
508 | return; | |
509 | ||
12d00cad | 510 | efx_reado(efx, ®, FR_AB_MAC_CTRL); |
177dfcd8 | 511 | /* There is no point in draining more than once */ |
3e6c4538 | 512 | if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) |
177dfcd8 BH |
513 | return; |
514 | ||
515 | falcon_reset_macs(efx); | |
8ceee660 BH |
516 | } |
517 | ||
d3245b28 | 518 | static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx) |
8ceee660 | 519 | { |
177dfcd8 | 520 | efx_oword_t reg; |
8ceee660 | 521 | |
daeda630 | 522 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) |
8ceee660 BH |
523 | return; |
524 | ||
525 | /* Isolate the MAC -> RX */ | |
12d00cad | 526 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
3e6c4538 | 527 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); |
12d00cad | 528 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 | 529 | |
d3245b28 BH |
530 | /* Isolate TX -> MAC */ |
531 | falcon_drain_tx_fifo(efx); | |
8ceee660 BH |
532 | } |
533 | ||
534 | void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) | |
535 | { | |
eb50c0d6 | 536 | struct efx_link_state *link_state = &efx->link_state; |
8ceee660 | 537 | efx_oword_t reg; |
fd371e32 SH |
538 | int link_speed, isolate; |
539 | ||
a7d529ae | 540 | isolate = !!ACCESS_ONCE(efx->reset_pending); |
8ceee660 | 541 | |
eb50c0d6 | 542 | switch (link_state->speed) { |
f31a45d2 BH |
543 | case 10000: link_speed = 3; break; |
544 | case 1000: link_speed = 2; break; | |
545 | case 100: link_speed = 1; break; | |
546 | default: link_speed = 0; break; | |
547 | } | |
8ceee660 BH |
548 | /* MAC_LINK_STATUS controls MAC backpressure but doesn't work |
549 | * as advertised. Disable to ensure packets are not | |
550 | * indefinitely held and TX queue can be flushed at any point | |
551 | * while the link is down. */ | |
552 | EFX_POPULATE_OWORD_5(reg, | |
3e6c4538 BH |
553 | FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */, |
554 | FRF_AB_MAC_BCAD_ACPT, 1, | |
555 | FRF_AB_MAC_UC_PROM, efx->promiscuous, | |
556 | FRF_AB_MAC_LINK_STATUS, 1, /* always set */ | |
557 | FRF_AB_MAC_SPEED, link_speed); | |
8ceee660 BH |
558 | /* On B0, MAC backpressure can be disabled and packets get |
559 | * discarded. */ | |
daeda630 | 560 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
3e6c4538 | 561 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, |
fd371e32 | 562 | !link_state->up || isolate); |
8ceee660 BH |
563 | } |
564 | ||
12d00cad | 565 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); |
8ceee660 BH |
566 | |
567 | /* Restore the multicast hash registers. */ | |
8be4f3e6 | 568 | falcon_push_multicast_hash(efx); |
8ceee660 | 569 | |
12d00cad | 570 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
4b0d29dc BH |
571 | /* Enable XOFF signal from RX FIFO (we enabled it during NIC |
572 | * initialisation but it may read back as 0) */ | |
573 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); | |
8ceee660 | 574 | /* Unisolate the MAC -> RX */ |
daeda630 | 575 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
fd371e32 | 576 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate); |
12d00cad | 577 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 BH |
578 | } |
579 | ||
55edc6e6 | 580 | static void falcon_stats_request(struct efx_nic *efx) |
8ceee660 | 581 | { |
55edc6e6 | 582 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 583 | efx_oword_t reg; |
8ceee660 | 584 | |
55edc6e6 BH |
585 | WARN_ON(nic_data->stats_pending); |
586 | WARN_ON(nic_data->stats_disable_count); | |
8ceee660 | 587 | |
55edc6e6 BH |
588 | if (nic_data->stats_dma_done == NULL) |
589 | return; /* no mac selected */ | |
8ceee660 | 590 | |
55edc6e6 BH |
591 | *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE; |
592 | nic_data->stats_pending = true; | |
8ceee660 BH |
593 | wmb(); /* ensure done flag is clear */ |
594 | ||
595 | /* Initiate DMA transfer of stats */ | |
596 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
597 | FRF_AB_MAC_STAT_DMA_CMD, 1, |
598 | FRF_AB_MAC_STAT_DMA_ADR, | |
8ceee660 | 599 | efx->stats_buffer.dma_addr); |
12d00cad | 600 | efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA); |
8ceee660 | 601 | |
55edc6e6 BH |
602 | mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2)); |
603 | } | |
604 | ||
605 | static void falcon_stats_complete(struct efx_nic *efx) | |
606 | { | |
607 | struct falcon_nic_data *nic_data = efx->nic_data; | |
608 | ||
609 | if (!nic_data->stats_pending) | |
610 | return; | |
611 | ||
3db1cd5c | 612 | nic_data->stats_pending = false; |
55edc6e6 BH |
613 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) { |
614 | rmb(); /* read the done flag before the stats */ | |
710b208d | 615 | falcon_update_stats_xmac(efx); |
55edc6e6 | 616 | } else { |
62776d03 BH |
617 | netif_err(efx, hw, efx->net_dev, |
618 | "timed out waiting for statistics\n"); | |
8ceee660 | 619 | } |
55edc6e6 | 620 | } |
8ceee660 | 621 | |
55edc6e6 BH |
622 | static void falcon_stats_timer_func(unsigned long context) |
623 | { | |
624 | struct efx_nic *efx = (struct efx_nic *)context; | |
625 | struct falcon_nic_data *nic_data = efx->nic_data; | |
626 | ||
627 | spin_lock(&efx->stats_lock); | |
628 | ||
629 | falcon_stats_complete(efx); | |
630 | if (nic_data->stats_disable_count == 0) | |
631 | falcon_stats_request(efx); | |
632 | ||
633 | spin_unlock(&efx->stats_lock); | |
8ceee660 BH |
634 | } |
635 | ||
fdaa9aed SH |
636 | static bool falcon_loopback_link_poll(struct efx_nic *efx) |
637 | { | |
638 | struct efx_link_state old_state = efx->link_state; | |
639 | ||
640 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
641 | WARN_ON(!LOOPBACK_INTERNAL(efx)); | |
642 | ||
643 | efx->link_state.fd = true; | |
644 | efx->link_state.fc = efx->wanted_fc; | |
645 | efx->link_state.up = true; | |
8fbca791 | 646 | efx->link_state.speed = 10000; |
fdaa9aed SH |
647 | |
648 | return !efx_link_state_equal(&efx->link_state, &old_state); | |
649 | } | |
650 | ||
d3245b28 BH |
651 | static int falcon_reconfigure_port(struct efx_nic *efx) |
652 | { | |
653 | int rc; | |
654 | ||
655 | WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0); | |
656 | ||
657 | /* Poll the PHY link state *before* reconfiguring it. This means we | |
658 | * will pick up the correct speed (in loopback) to select the correct | |
659 | * MAC. | |
660 | */ | |
661 | if (LOOPBACK_INTERNAL(efx)) | |
662 | falcon_loopback_link_poll(efx); | |
663 | else | |
664 | efx->phy_op->poll(efx); | |
665 | ||
666 | falcon_stop_nic_stats(efx); | |
667 | falcon_deconfigure_mac_wrapper(efx); | |
668 | ||
8fbca791 | 669 | falcon_reset_macs(efx); |
d3245b28 BH |
670 | |
671 | efx->phy_op->reconfigure(efx); | |
710b208d | 672 | rc = falcon_reconfigure_xmac(efx); |
d3245b28 BH |
673 | BUG_ON(rc); |
674 | ||
675 | falcon_start_nic_stats(efx); | |
676 | ||
677 | /* Synchronise efx->link_state with the kernel */ | |
678 | efx_link_status_changed(efx); | |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
8ceee660 BH |
683 | /************************************************************************** |
684 | * | |
685 | * PHY access via GMII | |
686 | * | |
687 | ************************************************************************** | |
688 | */ | |
689 | ||
8ceee660 BH |
690 | /* Wait for GMII access to complete */ |
691 | static int falcon_gmii_wait(struct efx_nic *efx) | |
692 | { | |
80cb9a0f | 693 | efx_oword_t md_stat; |
8ceee660 BH |
694 | int count; |
695 | ||
25985edc | 696 | /* wait up to 50ms - taken max from datasheet */ |
177dfcd8 | 697 | for (count = 0; count < 5000; count++) { |
80cb9a0f BH |
698 | efx_reado(efx, &md_stat, FR_AB_MD_STAT); |
699 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) { | |
700 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 || | |
701 | EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) { | |
62776d03 BH |
702 | netif_err(efx, hw, efx->net_dev, |
703 | "error from GMII access " | |
704 | EFX_OWORD_FMT"\n", | |
705 | EFX_OWORD_VAL(md_stat)); | |
8ceee660 BH |
706 | return -EIO; |
707 | } | |
708 | return 0; | |
709 | } | |
710 | udelay(10); | |
711 | } | |
62776d03 | 712 | netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n"); |
8ceee660 BH |
713 | return -ETIMEDOUT; |
714 | } | |
715 | ||
68e7f45e BH |
716 | /* Write an MDIO register of a PHY connected to Falcon. */ |
717 | static int falcon_mdio_write(struct net_device *net_dev, | |
718 | int prtad, int devad, u16 addr, u16 value) | |
8ceee660 | 719 | { |
767e468c | 720 | struct efx_nic *efx = netdev_priv(net_dev); |
4833f02a | 721 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 722 | efx_oword_t reg; |
68e7f45e | 723 | int rc; |
8ceee660 | 724 | |
62776d03 BH |
725 | netif_vdbg(efx, hw, efx->net_dev, |
726 | "writing MDIO %d register %d.%d with 0x%04x\n", | |
68e7f45e | 727 | prtad, devad, addr, value); |
8ceee660 | 728 | |
4833f02a | 729 | mutex_lock(&nic_data->mdio_lock); |
8ceee660 | 730 | |
68e7f45e BH |
731 | /* Check MDIO not currently being accessed */ |
732 | rc = falcon_gmii_wait(efx); | |
733 | if (rc) | |
8ceee660 BH |
734 | goto out; |
735 | ||
736 | /* Write the address/ID register */ | |
3e6c4538 | 737 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 738 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 739 | |
3e6c4538 BH |
740 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
741 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 742 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
743 | |
744 | /* Write data */ | |
3e6c4538 | 745 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); |
12d00cad | 746 | efx_writeo(efx, ®, FR_AB_MD_TXD); |
8ceee660 BH |
747 | |
748 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
749 | FRF_AB_MD_WRC, 1, |
750 | FRF_AB_MD_GC, 0); | |
12d00cad | 751 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
752 | |
753 | /* Wait for data to be written */ | |
68e7f45e BH |
754 | rc = falcon_gmii_wait(efx); |
755 | if (rc) { | |
8ceee660 BH |
756 | /* Abort the write operation */ |
757 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
758 | FRF_AB_MD_WRC, 0, |
759 | FRF_AB_MD_GC, 1); | |
12d00cad | 760 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
761 | udelay(10); |
762 | } | |
763 | ||
ab867461 | 764 | out: |
4833f02a | 765 | mutex_unlock(&nic_data->mdio_lock); |
68e7f45e | 766 | return rc; |
8ceee660 BH |
767 | } |
768 | ||
68e7f45e BH |
769 | /* Read an MDIO register of a PHY connected to Falcon. */ |
770 | static int falcon_mdio_read(struct net_device *net_dev, | |
771 | int prtad, int devad, u16 addr) | |
8ceee660 | 772 | { |
767e468c | 773 | struct efx_nic *efx = netdev_priv(net_dev); |
4833f02a | 774 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 775 | efx_oword_t reg; |
68e7f45e | 776 | int rc; |
8ceee660 | 777 | |
4833f02a | 778 | mutex_lock(&nic_data->mdio_lock); |
8ceee660 | 779 | |
68e7f45e BH |
780 | /* Check MDIO not currently being accessed */ |
781 | rc = falcon_gmii_wait(efx); | |
782 | if (rc) | |
8ceee660 BH |
783 | goto out; |
784 | ||
3e6c4538 | 785 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 786 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 787 | |
3e6c4538 BH |
788 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
789 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 790 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
791 | |
792 | /* Request data to be read */ | |
3e6c4538 | 793 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); |
12d00cad | 794 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
795 | |
796 | /* Wait for data to become available */ | |
68e7f45e BH |
797 | rc = falcon_gmii_wait(efx); |
798 | if (rc == 0) { | |
12d00cad | 799 | efx_reado(efx, ®, FR_AB_MD_RXD); |
3e6c4538 | 800 | rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD); |
62776d03 BH |
801 | netif_vdbg(efx, hw, efx->net_dev, |
802 | "read from MDIO %d register %d.%d, got %04x\n", | |
803 | prtad, devad, addr, rc); | |
8ceee660 BH |
804 | } else { |
805 | /* Abort the read operation */ | |
806 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
807 | FRF_AB_MD_RIC, 0, |
808 | FRF_AB_MD_GC, 1); | |
12d00cad | 809 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 | 810 | |
62776d03 BH |
811 | netif_dbg(efx, hw, efx->net_dev, |
812 | "read from MDIO %d register %d.%d, got error %d\n", | |
813 | prtad, devad, addr, rc); | |
8ceee660 BH |
814 | } |
815 | ||
ab867461 | 816 | out: |
4833f02a | 817 | mutex_unlock(&nic_data->mdio_lock); |
68e7f45e | 818 | return rc; |
8ceee660 BH |
819 | } |
820 | ||
8ceee660 | 821 | /* This call is responsible for hooking in the MAC and PHY operations */ |
ef2b90ee | 822 | static int falcon_probe_port(struct efx_nic *efx) |
8ceee660 | 823 | { |
8fbca791 | 824 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 BH |
825 | int rc; |
826 | ||
96c45726 BH |
827 | switch (efx->phy_type) { |
828 | case PHY_TYPE_SFX7101: | |
829 | efx->phy_op = &falcon_sfx7101_phy_ops; | |
830 | break; | |
96c45726 BH |
831 | case PHY_TYPE_QT2022C2: |
832 | case PHY_TYPE_QT2025C: | |
b37b62fe | 833 | efx->phy_op = &falcon_qt202x_phy_ops; |
96c45726 | 834 | break; |
7e51b439 BH |
835 | case PHY_TYPE_TXC43128: |
836 | efx->phy_op = &falcon_txc_phy_ops; | |
837 | break; | |
96c45726 | 838 | default: |
62776d03 BH |
839 | netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n", |
840 | efx->phy_type); | |
96c45726 BH |
841 | return -ENODEV; |
842 | } | |
843 | ||
c1c4f453 | 844 | /* Fill out MDIO structure and loopback modes */ |
4833f02a | 845 | mutex_init(&nic_data->mdio_lock); |
68e7f45e BH |
846 | efx->mdio.mdio_read = falcon_mdio_read; |
847 | efx->mdio.mdio_write = falcon_mdio_write; | |
c1c4f453 BH |
848 | rc = efx->phy_op->probe(efx); |
849 | if (rc != 0) | |
850 | return rc; | |
8ceee660 | 851 | |
b895d73e SH |
852 | /* Initial assumption */ |
853 | efx->link_state.speed = 10000; | |
854 | efx->link_state.fd = true; | |
855 | ||
8ceee660 | 856 | /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ |
daeda630 | 857 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
04cc8cac | 858 | efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; |
8ceee660 | 859 | else |
04cc8cac | 860 | efx->wanted_fc = EFX_FC_RX; |
7a6b8f6f SH |
861 | if (efx->mdio.mmds & MDIO_DEVS_AN) |
862 | efx->wanted_fc |= EFX_FC_AUTO; | |
8ceee660 BH |
863 | |
864 | /* Allocate buffer for stats */ | |
152b6a62 BH |
865 | rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer, |
866 | FALCON_MAC_STATS_SIZE); | |
8ceee660 BH |
867 | if (rc) |
868 | return rc; | |
62776d03 BH |
869 | netif_dbg(efx, probe, efx->net_dev, |
870 | "stats buffer at %llx (virt %p phys %llx)\n", | |
871 | (u64)efx->stats_buffer.dma_addr, | |
872 | efx->stats_buffer.addr, | |
873 | (u64)virt_to_phys(efx->stats_buffer.addr)); | |
8fbca791 | 874 | nic_data->stats_dma_done = efx->stats_buffer.addr + XgDmaDone_offset; |
8ceee660 BH |
875 | |
876 | return 0; | |
877 | } | |
878 | ||
ef2b90ee | 879 | static void falcon_remove_port(struct efx_nic *efx) |
8ceee660 | 880 | { |
ff3b00a0 | 881 | efx->phy_op->remove(efx); |
152b6a62 | 882 | efx_nic_free_buffer(efx, &efx->stats_buffer); |
8ceee660 BH |
883 | } |
884 | ||
40641ed9 BH |
885 | /* Global events are basically PHY events */ |
886 | static bool | |
887 | falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event) | |
888 | { | |
889 | struct efx_nic *efx = channel->efx; | |
cef68bde | 890 | struct falcon_nic_data *nic_data = efx->nic_data; |
40641ed9 BH |
891 | |
892 | if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) || | |
893 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) || | |
894 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) | |
895 | /* Ignored */ | |
896 | return true; | |
897 | ||
898 | if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) && | |
899 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) { | |
cef68bde | 900 | nic_data->xmac_poll_required = true; |
40641ed9 BH |
901 | return true; |
902 | } | |
903 | ||
904 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ? | |
905 | EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) : | |
906 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) { | |
907 | netif_err(efx, rx_err, efx->net_dev, | |
908 | "channel %d seen global RX_RESET event. Resetting.\n", | |
909 | channel->channel); | |
910 | ||
911 | atomic_inc(&efx->rx_reset); | |
912 | efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ? | |
913 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | |
914 | return true; | |
915 | } | |
916 | ||
917 | return false; | |
918 | } | |
919 | ||
8c8661e4 BH |
920 | /************************************************************************** |
921 | * | |
922 | * Falcon test code | |
923 | * | |
924 | **************************************************************************/ | |
925 | ||
0aa3fbaa BH |
926 | static int |
927 | falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out) | |
8c8661e4 | 928 | { |
4de92180 | 929 | struct falcon_nic_data *nic_data = efx->nic_data; |
8c8661e4 BH |
930 | struct falcon_nvconfig *nvconfig; |
931 | struct efx_spi_device *spi; | |
932 | void *region; | |
933 | int rc, magic_num, struct_ver; | |
934 | __le16 *word, *limit; | |
935 | u32 csum; | |
936 | ||
4de92180 BH |
937 | if (efx_spi_present(&nic_data->spi_flash)) |
938 | spi = &nic_data->spi_flash; | |
939 | else if (efx_spi_present(&nic_data->spi_eeprom)) | |
940 | spi = &nic_data->spi_eeprom; | |
941 | else | |
2f7f5730 BH |
942 | return -EINVAL; |
943 | ||
0a95f563 | 944 | region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); |
8c8661e4 BH |
945 | if (!region) |
946 | return -ENOMEM; | |
3e6c4538 | 947 | nvconfig = region + FALCON_NVCONFIG_OFFSET; |
8c8661e4 | 948 | |
4de92180 | 949 | mutex_lock(&nic_data->spi_lock); |
76884835 | 950 | rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region); |
4de92180 | 951 | mutex_unlock(&nic_data->spi_lock); |
8c8661e4 | 952 | if (rc) { |
62776d03 | 953 | netif_err(efx, hw, efx->net_dev, "Failed to read %s\n", |
4de92180 BH |
954 | efx_spi_present(&nic_data->spi_flash) ? |
955 | "flash" : "EEPROM"); | |
8c8661e4 BH |
956 | rc = -EIO; |
957 | goto out; | |
958 | } | |
959 | ||
960 | magic_num = le16_to_cpu(nvconfig->board_magic_num); | |
961 | struct_ver = le16_to_cpu(nvconfig->board_struct_ver); | |
962 | ||
963 | rc = -EINVAL; | |
3e6c4538 | 964 | if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) { |
62776d03 BH |
965 | netif_err(efx, hw, efx->net_dev, |
966 | "NVRAM bad magic 0x%x\n", magic_num); | |
8c8661e4 BH |
967 | goto out; |
968 | } | |
969 | if (struct_ver < 2) { | |
62776d03 BH |
970 | netif_err(efx, hw, efx->net_dev, |
971 | "NVRAM has ancient version 0x%x\n", struct_ver); | |
8c8661e4 BH |
972 | goto out; |
973 | } else if (struct_ver < 4) { | |
974 | word = &nvconfig->board_magic_num; | |
975 | limit = (__le16 *) (nvconfig + 1); | |
976 | } else { | |
977 | word = region; | |
0a95f563 | 978 | limit = region + FALCON_NVCONFIG_END; |
8c8661e4 BH |
979 | } |
980 | for (csum = 0; word < limit; ++word) | |
981 | csum += le16_to_cpu(*word); | |
982 | ||
983 | if (~csum & 0xffff) { | |
62776d03 BH |
984 | netif_err(efx, hw, efx->net_dev, |
985 | "NVRAM has incorrect checksum\n"); | |
8c8661e4 BH |
986 | goto out; |
987 | } | |
988 | ||
989 | rc = 0; | |
990 | if (nvconfig_out) | |
991 | memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig)); | |
992 | ||
993 | out: | |
994 | kfree(region); | |
995 | return rc; | |
996 | } | |
997 | ||
0aa3fbaa BH |
998 | static int falcon_test_nvram(struct efx_nic *efx) |
999 | { | |
1000 | return falcon_read_nvram(efx, NULL); | |
1001 | } | |
1002 | ||
152b6a62 | 1003 | static const struct efx_nic_register_test falcon_b0_register_tests[] = { |
3e6c4538 | 1004 | { FR_AZ_ADR_REGION, |
4cddca54 | 1005 | EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, |
3e6c4538 | 1006 | { FR_AZ_RX_CFG, |
8c8661e4 | 1007 | EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, |
3e6c4538 | 1008 | { FR_AZ_TX_CFG, |
8c8661e4 | 1009 | EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1010 | { FR_AZ_TX_RESERVED, |
8c8661e4 | 1011 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, |
3e6c4538 | 1012 | { FR_AB_MAC_CTRL, |
8c8661e4 | 1013 | EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1014 | { FR_AZ_SRM_TX_DC_CFG, |
8c8661e4 | 1015 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1016 | { FR_AZ_RX_DC_CFG, |
8c8661e4 | 1017 | EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1018 | { FR_AZ_RX_DC_PF_WM, |
8c8661e4 | 1019 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1020 | { FR_BZ_DP_CTRL, |
8c8661e4 | 1021 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1022 | { FR_AB_GM_CFG2, |
177dfcd8 | 1023 | EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1024 | { FR_AB_GMF_CFG0, |
177dfcd8 | 1025 | EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1026 | { FR_AB_XM_GLB_CFG, |
8c8661e4 | 1027 | EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1028 | { FR_AB_XM_TX_CFG, |
8c8661e4 | 1029 | EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1030 | { FR_AB_XM_RX_CFG, |
8c8661e4 | 1031 | EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1032 | { FR_AB_XM_RX_PARAM, |
8c8661e4 | 1033 | EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1034 | { FR_AB_XM_FC, |
8c8661e4 | 1035 | EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1036 | { FR_AB_XM_ADR_LO, |
8c8661e4 | 1037 | EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1038 | { FR_AB_XX_SD_CTL, |
8c8661e4 BH |
1039 | EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, |
1040 | }; | |
1041 | ||
152b6a62 BH |
1042 | static int falcon_b0_test_registers(struct efx_nic *efx) |
1043 | { | |
1044 | return efx_nic_test_registers(efx, falcon_b0_register_tests, | |
1045 | ARRAY_SIZE(falcon_b0_register_tests)); | |
1046 | } | |
1047 | ||
8ceee660 BH |
1048 | /************************************************************************** |
1049 | * | |
1050 | * Device reset | |
1051 | * | |
1052 | ************************************************************************** | |
1053 | */ | |
1054 | ||
0e2a9c7c BH |
1055 | static enum reset_type falcon_map_reset_reason(enum reset_type reason) |
1056 | { | |
1057 | switch (reason) { | |
1058 | case RESET_TYPE_RX_RECOVERY: | |
1059 | case RESET_TYPE_RX_DESC_FETCH: | |
1060 | case RESET_TYPE_TX_DESC_FETCH: | |
1061 | case RESET_TYPE_TX_SKIP: | |
1062 | /* These can occasionally occur due to hardware bugs. | |
1063 | * We try to reset without disrupting the link. | |
1064 | */ | |
1065 | return RESET_TYPE_INVISIBLE; | |
1066 | default: | |
1067 | return RESET_TYPE_ALL; | |
1068 | } | |
1069 | } | |
1070 | ||
1071 | static int falcon_map_reset_flags(u32 *flags) | |
1072 | { | |
1073 | enum { | |
1074 | FALCON_RESET_INVISIBLE = (ETH_RESET_DMA | ETH_RESET_FILTER | | |
1075 | ETH_RESET_OFFLOAD | ETH_RESET_MAC), | |
1076 | FALCON_RESET_ALL = FALCON_RESET_INVISIBLE | ETH_RESET_PHY, | |
1077 | FALCON_RESET_WORLD = FALCON_RESET_ALL | ETH_RESET_IRQ, | |
1078 | }; | |
1079 | ||
1080 | if ((*flags & FALCON_RESET_WORLD) == FALCON_RESET_WORLD) { | |
1081 | *flags &= ~FALCON_RESET_WORLD; | |
1082 | return RESET_TYPE_WORLD; | |
1083 | } | |
1084 | ||
1085 | if ((*flags & FALCON_RESET_ALL) == FALCON_RESET_ALL) { | |
1086 | *flags &= ~FALCON_RESET_ALL; | |
1087 | return RESET_TYPE_ALL; | |
1088 | } | |
1089 | ||
1090 | if ((*flags & FALCON_RESET_INVISIBLE) == FALCON_RESET_INVISIBLE) { | |
1091 | *flags &= ~FALCON_RESET_INVISIBLE; | |
1092 | return RESET_TYPE_INVISIBLE; | |
1093 | } | |
1094 | ||
1095 | return -EINVAL; | |
1096 | } | |
1097 | ||
8ceee660 BH |
1098 | /* Resets NIC to known state. This routine must be called in process |
1099 | * context and is allowed to sleep. */ | |
4de92180 | 1100 | static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method) |
8ceee660 BH |
1101 | { |
1102 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1103 | efx_oword_t glb_ctl_reg_ker; | |
1104 | int rc; | |
1105 | ||
62776d03 BH |
1106 | netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n", |
1107 | RESET_TYPE(method)); | |
8ceee660 BH |
1108 | |
1109 | /* Initiate device reset */ | |
1110 | if (method == RESET_TYPE_WORLD) { | |
1111 | rc = pci_save_state(efx->pci_dev); | |
1112 | if (rc) { | |
62776d03 BH |
1113 | netif_err(efx, drv, efx->net_dev, |
1114 | "failed to backup PCI state of primary " | |
1115 | "function prior to hardware reset\n"); | |
8ceee660 BH |
1116 | goto fail1; |
1117 | } | |
152b6a62 | 1118 | if (efx_nic_is_dual_func(efx)) { |
8ceee660 BH |
1119 | rc = pci_save_state(nic_data->pci_dev2); |
1120 | if (rc) { | |
62776d03 BH |
1121 | netif_err(efx, drv, efx->net_dev, |
1122 | "failed to backup PCI state of " | |
1123 | "secondary function prior to " | |
1124 | "hardware reset\n"); | |
8ceee660 BH |
1125 | goto fail2; |
1126 | } | |
1127 | } | |
1128 | ||
1129 | EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, | |
3e6c4538 BH |
1130 | FRF_AB_EXT_PHY_RST_DUR, |
1131 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
1132 | FRF_AB_SWRST, 1); | |
8ceee660 | 1133 | } else { |
8ceee660 | 1134 | EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, |
3e6c4538 BH |
1135 | /* exclude PHY from "invisible" reset */ |
1136 | FRF_AB_EXT_PHY_RST_CTL, | |
1137 | method == RESET_TYPE_INVISIBLE, | |
1138 | /* exclude EEPROM/flash and PCIe */ | |
1139 | FRF_AB_PCIE_CORE_RST_CTL, 1, | |
1140 | FRF_AB_PCIE_NSTKY_RST_CTL, 1, | |
1141 | FRF_AB_PCIE_SD_RST_CTL, 1, | |
1142 | FRF_AB_EE_RST_CTL, 1, | |
1143 | FRF_AB_EXT_PHY_RST_DUR, | |
1144 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
1145 | FRF_AB_SWRST, 1); | |
1146 | } | |
12d00cad | 1147 | efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
8ceee660 | 1148 | |
62776d03 | 1149 | netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n"); |
8ceee660 BH |
1150 | schedule_timeout_uninterruptible(HZ / 20); |
1151 | ||
1152 | /* Restore PCI configuration if needed */ | |
1153 | if (method == RESET_TYPE_WORLD) { | |
1d3c16a8 JM |
1154 | if (efx_nic_is_dual_func(efx)) |
1155 | pci_restore_state(nic_data->pci_dev2); | |
1156 | pci_restore_state(efx->pci_dev); | |
62776d03 BH |
1157 | netif_dbg(efx, drv, efx->net_dev, |
1158 | "successfully restored PCI config\n"); | |
8ceee660 BH |
1159 | } |
1160 | ||
1161 | /* Assert that reset complete */ | |
12d00cad | 1162 | efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
3e6c4538 | 1163 | if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) { |
8ceee660 | 1164 | rc = -ETIMEDOUT; |
62776d03 BH |
1165 | netif_err(efx, hw, efx->net_dev, |
1166 | "timed out waiting for hardware reset\n"); | |
1d3c16a8 | 1167 | goto fail3; |
8ceee660 | 1168 | } |
62776d03 | 1169 | netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n"); |
8ceee660 BH |
1170 | |
1171 | return 0; | |
1172 | ||
1173 | /* pci_save_state() and pci_restore_state() MUST be called in pairs */ | |
1174 | fail2: | |
8ceee660 BH |
1175 | pci_restore_state(efx->pci_dev); |
1176 | fail1: | |
1d3c16a8 | 1177 | fail3: |
8ceee660 BH |
1178 | return rc; |
1179 | } | |
1180 | ||
4de92180 BH |
1181 | static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method) |
1182 | { | |
1183 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1184 | int rc; | |
1185 | ||
1186 | mutex_lock(&nic_data->spi_lock); | |
1187 | rc = __falcon_reset_hw(efx, method); | |
1188 | mutex_unlock(&nic_data->spi_lock); | |
1189 | ||
1190 | return rc; | |
1191 | } | |
1192 | ||
ef2b90ee | 1193 | static void falcon_monitor(struct efx_nic *efx) |
fe75820b | 1194 | { |
fdaa9aed | 1195 | bool link_changed; |
fe75820b BH |
1196 | int rc; |
1197 | ||
fdaa9aed SH |
1198 | BUG_ON(!mutex_is_locked(&efx->mac_lock)); |
1199 | ||
fe75820b BH |
1200 | rc = falcon_board(efx)->type->monitor(efx); |
1201 | if (rc) { | |
62776d03 BH |
1202 | netif_err(efx, hw, efx->net_dev, |
1203 | "Board sensor %s; shutting down PHY\n", | |
1204 | (rc == -ERANGE) ? "reported fault" : "failed"); | |
fe75820b | 1205 | efx->phy_mode |= PHY_MODE_LOW_POWER; |
d3245b28 BH |
1206 | rc = __efx_reconfigure_port(efx); |
1207 | WARN_ON(rc); | |
fe75820b | 1208 | } |
fdaa9aed SH |
1209 | |
1210 | if (LOOPBACK_INTERNAL(efx)) | |
1211 | link_changed = falcon_loopback_link_poll(efx); | |
1212 | else | |
1213 | link_changed = efx->phy_op->poll(efx); | |
1214 | ||
1215 | if (link_changed) { | |
1216 | falcon_stop_nic_stats(efx); | |
1217 | falcon_deconfigure_mac_wrapper(efx); | |
1218 | ||
8fbca791 | 1219 | falcon_reset_macs(efx); |
710b208d | 1220 | rc = falcon_reconfigure_xmac(efx); |
d3245b28 | 1221 | BUG_ON(rc); |
fdaa9aed SH |
1222 | |
1223 | falcon_start_nic_stats(efx); | |
1224 | ||
1225 | efx_link_status_changed(efx); | |
1226 | } | |
1227 | ||
8fbca791 | 1228 | falcon_poll_xmac(efx); |
fe75820b BH |
1229 | } |
1230 | ||
8ceee660 BH |
1231 | /* Zeroes out the SRAM contents. This routine must be called in |
1232 | * process context and is allowed to sleep. | |
1233 | */ | |
1234 | static int falcon_reset_sram(struct efx_nic *efx) | |
1235 | { | |
1236 | efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; | |
1237 | int count; | |
1238 | ||
1239 | /* Set the SRAM wake/sleep GPIO appropriately. */ | |
12d00cad | 1240 | efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
3e6c4538 BH |
1241 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1); |
1242 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1); | |
12d00cad | 1243 | efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
8ceee660 BH |
1244 | |
1245 | /* Initiate SRAM reset */ | |
1246 | EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, | |
3e6c4538 BH |
1247 | FRF_AZ_SRM_INIT_EN, 1, |
1248 | FRF_AZ_SRM_NB_SZ, 0); | |
12d00cad | 1249 | efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
8ceee660 BH |
1250 | |
1251 | /* Wait for SRAM reset to complete */ | |
1252 | count = 0; | |
1253 | do { | |
62776d03 BH |
1254 | netif_dbg(efx, hw, efx->net_dev, |
1255 | "waiting for SRAM reset (attempt %d)...\n", count); | |
8ceee660 BH |
1256 | |
1257 | /* SRAM reset is slow; expect around 16ms */ | |
1258 | schedule_timeout_uninterruptible(HZ / 50); | |
1259 | ||
1260 | /* Check for reset complete */ | |
12d00cad | 1261 | efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
3e6c4538 | 1262 | if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) { |
62776d03 BH |
1263 | netif_dbg(efx, hw, efx->net_dev, |
1264 | "SRAM reset complete\n"); | |
8ceee660 BH |
1265 | |
1266 | return 0; | |
1267 | } | |
25985edc | 1268 | } while (++count < 20); /* wait up to 0.4 sec */ |
8ceee660 | 1269 | |
62776d03 | 1270 | netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n"); |
8ceee660 BH |
1271 | return -ETIMEDOUT; |
1272 | } | |
1273 | ||
4de92180 BH |
1274 | static void falcon_spi_device_init(struct efx_nic *efx, |
1275 | struct efx_spi_device *spi_device, | |
4a5b504d BH |
1276 | unsigned int device_id, u32 device_type) |
1277 | { | |
4a5b504d | 1278 | if (device_type != 0) { |
4a5b504d BH |
1279 | spi_device->device_id = device_id; |
1280 | spi_device->size = | |
1281 | 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE); | |
1282 | spi_device->addr_len = | |
1283 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN); | |
1284 | spi_device->munge_address = (spi_device->size == 1 << 9 && | |
1285 | spi_device->addr_len == 1); | |
f4150724 BH |
1286 | spi_device->erase_command = |
1287 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD); | |
1288 | spi_device->erase_size = | |
1289 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
1290 | SPI_DEV_TYPE_ERASE_SIZE); | |
4a5b504d BH |
1291 | spi_device->block_size = |
1292 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
1293 | SPI_DEV_TYPE_BLOCK_SIZE); | |
4a5b504d | 1294 | } else { |
4de92180 | 1295 | spi_device->size = 0; |
4a5b504d | 1296 | } |
4a5b504d BH |
1297 | } |
1298 | ||
8ceee660 BH |
1299 | /* Extract non-volatile configuration */ |
1300 | static int falcon_probe_nvconfig(struct efx_nic *efx) | |
1301 | { | |
4de92180 | 1302 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 1303 | struct falcon_nvconfig *nvconfig; |
8ceee660 BH |
1304 | int rc; |
1305 | ||
8ceee660 | 1306 | nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); |
4a5b504d BH |
1307 | if (!nvconfig) |
1308 | return -ENOMEM; | |
8ceee660 | 1309 | |
8c8661e4 | 1310 | rc = falcon_read_nvram(efx, nvconfig); |
6c88b0b6 | 1311 | if (rc) |
4de92180 | 1312 | goto out; |
6c88b0b6 BH |
1313 | |
1314 | efx->phy_type = nvconfig->board_v2.port0_phy_type; | |
1315 | efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr; | |
1316 | ||
1317 | if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { | |
4de92180 BH |
1318 | falcon_spi_device_init( |
1319 | efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH, | |
6c88b0b6 BH |
1320 | le32_to_cpu(nvconfig->board_v3 |
1321 | .spi_device_type[FFE_AB_SPI_DEVICE_FLASH])); | |
4de92180 BH |
1322 | falcon_spi_device_init( |
1323 | efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM, | |
6c88b0b6 BH |
1324 | le32_to_cpu(nvconfig->board_v3 |
1325 | .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM])); | |
8ceee660 BH |
1326 | } |
1327 | ||
8c8661e4 | 1328 | /* Read the MAC addresses */ |
7e300bc8 | 1329 | memcpy(efx->net_dev->perm_addr, nvconfig->mac_address[0], ETH_ALEN); |
8c8661e4 | 1330 | |
62776d03 BH |
1331 | netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n", |
1332 | efx->phy_type, efx->mdio.prtad); | |
8ceee660 | 1333 | |
6c88b0b6 BH |
1334 | rc = falcon_probe_board(efx, |
1335 | le16_to_cpu(nvconfig->board_v2.board_revision)); | |
4de92180 | 1336 | out: |
8ceee660 BH |
1337 | kfree(nvconfig); |
1338 | return rc; | |
1339 | } | |
1340 | ||
4a5b504d BH |
1341 | /* Probe all SPI devices on the NIC */ |
1342 | static void falcon_probe_spi_devices(struct efx_nic *efx) | |
1343 | { | |
4de92180 | 1344 | struct falcon_nic_data *nic_data = efx->nic_data; |
4a5b504d | 1345 | efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; |
2f7f5730 | 1346 | int boot_dev; |
4a5b504d | 1347 | |
12d00cad BH |
1348 | efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL); |
1349 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
1350 | efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); | |
4a5b504d | 1351 | |
3e6c4538 BH |
1352 | if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) { |
1353 | boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ? | |
1354 | FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM); | |
62776d03 BH |
1355 | netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n", |
1356 | boot_dev == FFE_AB_SPI_DEVICE_FLASH ? | |
1357 | "flash" : "EEPROM"); | |
2f7f5730 BH |
1358 | } else { |
1359 | /* Disable VPD and set clock dividers to safe | |
1360 | * values for initial programming. */ | |
1361 | boot_dev = -1; | |
62776d03 BH |
1362 | netif_dbg(efx, probe, efx->net_dev, |
1363 | "Booted from internal ASIC settings;" | |
1364 | " setting SPI config\n"); | |
3e6c4538 | 1365 | EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0, |
2f7f5730 | 1366 | /* 125 MHz / 7 ~= 20 MHz */ |
3e6c4538 | 1367 | FRF_AB_EE_SF_CLOCK_DIV, 7, |
2f7f5730 | 1368 | /* 125 MHz / 63 ~= 2 MHz */ |
3e6c4538 | 1369 | FRF_AB_EE_EE_CLOCK_DIV, 63); |
12d00cad | 1370 | efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); |
4a5b504d BH |
1371 | } |
1372 | ||
4de92180 BH |
1373 | mutex_init(&nic_data->spi_lock); |
1374 | ||
3e6c4538 | 1375 | if (boot_dev == FFE_AB_SPI_DEVICE_FLASH) |
4de92180 | 1376 | falcon_spi_device_init(efx, &nic_data->spi_flash, |
3e6c4538 | 1377 | FFE_AB_SPI_DEVICE_FLASH, |
2f7f5730 | 1378 | default_flash_type); |
3e6c4538 | 1379 | if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM) |
4de92180 | 1380 | falcon_spi_device_init(efx, &nic_data->spi_eeprom, |
3e6c4538 | 1381 | FFE_AB_SPI_DEVICE_EEPROM, |
2f7f5730 | 1382 | large_eeprom_type); |
4a5b504d BH |
1383 | } |
1384 | ||
ef2b90ee | 1385 | static int falcon_probe_nic(struct efx_nic *efx) |
8ceee660 BH |
1386 | { |
1387 | struct falcon_nic_data *nic_data; | |
e775fb93 | 1388 | struct falcon_board *board; |
8ceee660 BH |
1389 | int rc; |
1390 | ||
8ceee660 BH |
1391 | /* Allocate storage for hardware specific data */ |
1392 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); | |
88c59425 BH |
1393 | if (!nic_data) |
1394 | return -ENOMEM; | |
5daab96d | 1395 | efx->nic_data = nic_data; |
8ceee660 | 1396 | |
57849460 BH |
1397 | rc = -ENODEV; |
1398 | ||
1399 | if (efx_nic_fpga_ver(efx) != 0) { | |
62776d03 BH |
1400 | netif_err(efx, probe, efx->net_dev, |
1401 | "Falcon FPGA not supported\n"); | |
8ceee660 | 1402 | goto fail1; |
57849460 BH |
1403 | } |
1404 | ||
1405 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { | |
1406 | efx_oword_t nic_stat; | |
1407 | struct pci_dev *dev; | |
1408 | u8 pci_rev = efx->pci_dev->revision; | |
8ceee660 | 1409 | |
57849460 | 1410 | if ((pci_rev == 0xff) || (pci_rev == 0)) { |
62776d03 BH |
1411 | netif_err(efx, probe, efx->net_dev, |
1412 | "Falcon rev A0 not supported\n"); | |
57849460 BH |
1413 | goto fail1; |
1414 | } | |
1415 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
1416 | if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) { | |
62776d03 BH |
1417 | netif_err(efx, probe, efx->net_dev, |
1418 | "Falcon rev A1 1G not supported\n"); | |
57849460 BH |
1419 | goto fail1; |
1420 | } | |
1421 | if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) { | |
62776d03 BH |
1422 | netif_err(efx, probe, efx->net_dev, |
1423 | "Falcon rev A1 PCI-X not supported\n"); | |
57849460 BH |
1424 | goto fail1; |
1425 | } | |
8ceee660 | 1426 | |
57849460 | 1427 | dev = pci_dev_get(efx->pci_dev); |
937383a5 BH |
1428 | while ((dev = pci_get_device(PCI_VENDOR_ID_SOLARFLARE, |
1429 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, | |
8ceee660 BH |
1430 | dev))) { |
1431 | if (dev->bus == efx->pci_dev->bus && | |
1432 | dev->devfn == efx->pci_dev->devfn + 1) { | |
1433 | nic_data->pci_dev2 = dev; | |
1434 | break; | |
1435 | } | |
1436 | } | |
1437 | if (!nic_data->pci_dev2) { | |
62776d03 BH |
1438 | netif_err(efx, probe, efx->net_dev, |
1439 | "failed to find secondary function\n"); | |
8ceee660 BH |
1440 | rc = -ENODEV; |
1441 | goto fail2; | |
1442 | } | |
1443 | } | |
1444 | ||
1445 | /* Now we can reset the NIC */ | |
4de92180 | 1446 | rc = __falcon_reset_hw(efx, RESET_TYPE_ALL); |
8ceee660 | 1447 | if (rc) { |
62776d03 | 1448 | netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n"); |
8ceee660 BH |
1449 | goto fail3; |
1450 | } | |
1451 | ||
1452 | /* Allocate memory for INT_KER */ | |
152b6a62 | 1453 | rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); |
8ceee660 BH |
1454 | if (rc) |
1455 | goto fail4; | |
1456 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | |
1457 | ||
62776d03 BH |
1458 | netif_dbg(efx, probe, efx->net_dev, |
1459 | "INT_KER at %llx (virt %p phys %llx)\n", | |
1460 | (u64)efx->irq_status.dma_addr, | |
1461 | efx->irq_status.addr, | |
1462 | (u64)virt_to_phys(efx->irq_status.addr)); | |
8ceee660 | 1463 | |
4a5b504d BH |
1464 | falcon_probe_spi_devices(efx); |
1465 | ||
8ceee660 BH |
1466 | /* Read in the non-volatile configuration */ |
1467 | rc = falcon_probe_nvconfig(efx); | |
6c88b0b6 BH |
1468 | if (rc) { |
1469 | if (rc == -EINVAL) | |
1470 | netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n"); | |
8ceee660 | 1471 | goto fail5; |
6c88b0b6 | 1472 | } |
8ceee660 | 1473 | |
37b5a603 | 1474 | /* Initialise I2C adapter */ |
e775fb93 BH |
1475 | board = falcon_board(efx); |
1476 | board->i2c_adap.owner = THIS_MODULE; | |
1477 | board->i2c_data = falcon_i2c_bit_operations; | |
1478 | board->i2c_data.data = efx; | |
1479 | board->i2c_adap.algo_data = &board->i2c_data; | |
1480 | board->i2c_adap.dev.parent = &efx->pci_dev->dev; | |
1481 | strlcpy(board->i2c_adap.name, "SFC4000 GPIO", | |
1482 | sizeof(board->i2c_adap.name)); | |
1483 | rc = i2c_bit_add_bus(&board->i2c_adap); | |
37b5a603 BH |
1484 | if (rc) |
1485 | goto fail5; | |
1486 | ||
44838a44 | 1487 | rc = falcon_board(efx)->type->init(efx); |
278c0621 | 1488 | if (rc) { |
62776d03 BH |
1489 | netif_err(efx, probe, efx->net_dev, |
1490 | "failed to initialise board\n"); | |
278c0621 BH |
1491 | goto fail6; |
1492 | } | |
1493 | ||
55edc6e6 BH |
1494 | nic_data->stats_disable_count = 1; |
1495 | setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func, | |
1496 | (unsigned long)efx); | |
1497 | ||
8ceee660 BH |
1498 | return 0; |
1499 | ||
278c0621 | 1500 | fail6: |
e775fb93 BH |
1501 | BUG_ON(i2c_del_adapter(&board->i2c_adap)); |
1502 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); | |
8ceee660 | 1503 | fail5: |
152b6a62 | 1504 | efx_nic_free_buffer(efx, &efx->irq_status); |
8ceee660 | 1505 | fail4: |
8ceee660 BH |
1506 | fail3: |
1507 | if (nic_data->pci_dev2) { | |
1508 | pci_dev_put(nic_data->pci_dev2); | |
1509 | nic_data->pci_dev2 = NULL; | |
1510 | } | |
1511 | fail2: | |
8ceee660 BH |
1512 | fail1: |
1513 | kfree(efx->nic_data); | |
1514 | return rc; | |
1515 | } | |
1516 | ||
56241ceb BH |
1517 | static void falcon_init_rx_cfg(struct efx_nic *efx) |
1518 | { | |
1519 | /* Prior to Siena the RX DMA engine will split each frame at | |
1520 | * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to | |
1521 | * be so large that that never happens. */ | |
1522 | const unsigned huge_buf_size = (3 * 4096) >> 5; | |
1523 | /* RX control FIFO thresholds (32 entries) */ | |
1524 | const unsigned ctrl_xon_thr = 20; | |
1525 | const unsigned ctrl_xoff_thr = 25; | |
56241ceb BH |
1526 | efx_oword_t reg; |
1527 | ||
12d00cad | 1528 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
daeda630 | 1529 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { |
625b4514 | 1530 | /* Data FIFO size is 5.5K */ |
3e6c4538 BH |
1531 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); |
1532 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, | |
1533 | huge_buf_size); | |
5fb6b06d BH |
1534 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8); |
1535 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8); | |
3e6c4538 BH |
1536 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); |
1537 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
56241ceb | 1538 | } else { |
625b4514 | 1539 | /* Data FIFO size is 80K; register fields moved */ |
3e6c4538 BH |
1540 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); |
1541 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, | |
1542 | huge_buf_size); | |
5fb6b06d BH |
1543 | /* Send XON and XOFF at ~3 * max MTU away from empty/full */ |
1544 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8); | |
1545 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8); | |
3e6c4538 BH |
1546 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); |
1547 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
1548 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); | |
477e54eb BH |
1549 | |
1550 | /* Enable hash insertion. This is broken for the | |
1551 | * 'Falcon' hash so also select Toeplitz TCP/IPv4 and | |
1552 | * IPv4 hashes. */ | |
1553 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1); | |
1554 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1); | |
1555 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1); | |
56241ceb | 1556 | } |
4b0d29dc BH |
1557 | /* Always enable XOFF signal from RX FIFO. We enable |
1558 | * or disable transmission of pause frames at the MAC. */ | |
1559 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); | |
12d00cad | 1560 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
56241ceb BH |
1561 | } |
1562 | ||
152b6a62 BH |
1563 | /* This call performs hardware-specific global initialisation, such as |
1564 | * defining the descriptor cache sizes and number of RSS channels. | |
1565 | * It does not set up any buffers, descriptor rings or event queues. | |
1566 | */ | |
1567 | static int falcon_init_nic(struct efx_nic *efx) | |
1568 | { | |
1569 | efx_oword_t temp; | |
1570 | int rc; | |
1571 | ||
1572 | /* Use on-chip SRAM */ | |
1573 | efx_reado(efx, &temp, FR_AB_NIC_STAT); | |
1574 | EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); | |
1575 | efx_writeo(efx, &temp, FR_AB_NIC_STAT); | |
1576 | ||
152b6a62 BH |
1577 | rc = falcon_reset_sram(efx); |
1578 | if (rc) | |
1579 | return rc; | |
1580 | ||
1581 | /* Clear the parity enables on the TX data fifos as | |
1582 | * they produce false parity errors because of timing issues | |
1583 | */ | |
1584 | if (EFX_WORKAROUND_5129(efx)) { | |
1585 | efx_reado(efx, &temp, FR_AZ_CSR_SPARE); | |
1586 | EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0); | |
1587 | efx_writeo(efx, &temp, FR_AZ_CSR_SPARE); | |
1588 | } | |
1589 | ||
8ceee660 | 1590 | if (EFX_WORKAROUND_7244(efx)) { |
12d00cad | 1591 | efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL); |
3e6c4538 BH |
1592 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8); |
1593 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8); | |
1594 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8); | |
1595 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8); | |
12d00cad | 1596 | efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL); |
8ceee660 | 1597 | } |
8ceee660 | 1598 | |
3e6c4538 | 1599 | /* XXX This is documented only for Falcon A0/A1 */ |
8ceee660 BH |
1600 | /* Setup RX. Wait for descriptor is broken and must |
1601 | * be disabled. RXDP recovery shouldn't be needed, but is. | |
1602 | */ | |
12d00cad | 1603 | efx_reado(efx, &temp, FR_AA_RX_SELF_RST); |
3e6c4538 BH |
1604 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1); |
1605 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1); | |
8ceee660 | 1606 | if (EFX_WORKAROUND_5583(efx)) |
3e6c4538 | 1607 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1); |
12d00cad | 1608 | efx_writeo(efx, &temp, FR_AA_RX_SELF_RST); |
8ceee660 | 1609 | |
8ceee660 BH |
1610 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 |
1611 | * descriptors (which is bad). | |
1612 | */ | |
12d00cad | 1613 | efx_reado(efx, &temp, FR_AZ_TX_CFG); |
3e6c4538 | 1614 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); |
12d00cad | 1615 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); |
8ceee660 | 1616 | |
56241ceb | 1617 | falcon_init_rx_cfg(efx); |
8ceee660 | 1618 | |
daeda630 | 1619 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
477e54eb BH |
1620 | /* Set hash key for IPv4 */ |
1621 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); | |
1622 | efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY); | |
1623 | ||
1624 | /* Set destination of both TX and RX Flush events */ | |
3e6c4538 | 1625 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); |
12d00cad | 1626 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); |
8ceee660 BH |
1627 | } |
1628 | ||
152b6a62 BH |
1629 | efx_nic_init_common(efx); |
1630 | ||
8ceee660 BH |
1631 | return 0; |
1632 | } | |
1633 | ||
ef2b90ee | 1634 | static void falcon_remove_nic(struct efx_nic *efx) |
8ceee660 BH |
1635 | { |
1636 | struct falcon_nic_data *nic_data = efx->nic_data; | |
e775fb93 | 1637 | struct falcon_board *board = falcon_board(efx); |
37b5a603 BH |
1638 | int rc; |
1639 | ||
44838a44 | 1640 | board->type->fini(efx); |
278c0621 | 1641 | |
8c870379 | 1642 | /* Remove I2C adapter and clear it in preparation for a retry */ |
e775fb93 | 1643 | rc = i2c_del_adapter(&board->i2c_adap); |
37b5a603 | 1644 | BUG_ON(rc); |
e775fb93 | 1645 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); |
8ceee660 | 1646 | |
152b6a62 | 1647 | efx_nic_free_buffer(efx, &efx->irq_status); |
8ceee660 | 1648 | |
4de92180 | 1649 | __falcon_reset_hw(efx, RESET_TYPE_ALL); |
8ceee660 BH |
1650 | |
1651 | /* Release the second function after the reset */ | |
1652 | if (nic_data->pci_dev2) { | |
1653 | pci_dev_put(nic_data->pci_dev2); | |
1654 | nic_data->pci_dev2 = NULL; | |
1655 | } | |
1656 | ||
1657 | /* Tear down the private nic state */ | |
1658 | kfree(efx->nic_data); | |
1659 | efx->nic_data = NULL; | |
1660 | } | |
1661 | ||
ef2b90ee | 1662 | static void falcon_update_nic_stats(struct efx_nic *efx) |
8ceee660 | 1663 | { |
55edc6e6 | 1664 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 BH |
1665 | efx_oword_t cnt; |
1666 | ||
55edc6e6 BH |
1667 | if (nic_data->stats_disable_count) |
1668 | return; | |
1669 | ||
12d00cad | 1670 | efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP); |
3e6c4538 BH |
1671 | efx->n_rx_nodesc_drop_cnt += |
1672 | EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT); | |
55edc6e6 BH |
1673 | |
1674 | if (nic_data->stats_pending && | |
1675 | *nic_data->stats_dma_done == FALCON_STATS_DONE) { | |
1676 | nic_data->stats_pending = false; | |
1677 | rmb(); /* read the done flag before the stats */ | |
710b208d | 1678 | falcon_update_stats_xmac(efx); |
55edc6e6 BH |
1679 | } |
1680 | } | |
1681 | ||
1682 | void falcon_start_nic_stats(struct efx_nic *efx) | |
1683 | { | |
1684 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1685 | ||
1686 | spin_lock_bh(&efx->stats_lock); | |
1687 | if (--nic_data->stats_disable_count == 0) | |
1688 | falcon_stats_request(efx); | |
1689 | spin_unlock_bh(&efx->stats_lock); | |
1690 | } | |
1691 | ||
1692 | void falcon_stop_nic_stats(struct efx_nic *efx) | |
1693 | { | |
1694 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1695 | int i; | |
1696 | ||
1697 | might_sleep(); | |
1698 | ||
1699 | spin_lock_bh(&efx->stats_lock); | |
1700 | ++nic_data->stats_disable_count; | |
1701 | spin_unlock_bh(&efx->stats_lock); | |
1702 | ||
1703 | del_timer_sync(&nic_data->stats_timer); | |
1704 | ||
1705 | /* Wait enough time for the most recent transfer to | |
1706 | * complete. */ | |
1707 | for (i = 0; i < 4 && nic_data->stats_pending; i++) { | |
1708 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) | |
1709 | break; | |
1710 | msleep(1); | |
1711 | } | |
1712 | ||
1713 | spin_lock_bh(&efx->stats_lock); | |
1714 | falcon_stats_complete(efx); | |
1715 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
1716 | } |
1717 | ||
06629f07 BH |
1718 | static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
1719 | { | |
1720 | falcon_board(efx)->type->set_id_led(efx, mode); | |
1721 | } | |
1722 | ||
89c758fa BH |
1723 | /************************************************************************** |
1724 | * | |
1725 | * Wake on LAN | |
1726 | * | |
1727 | ************************************************************************** | |
1728 | */ | |
1729 | ||
1730 | static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) | |
1731 | { | |
1732 | wol->supported = 0; | |
1733 | wol->wolopts = 0; | |
1734 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
1735 | } | |
1736 | ||
1737 | static int falcon_set_wol(struct efx_nic *efx, u32 type) | |
1738 | { | |
1739 | if (type != 0) | |
1740 | return -EINVAL; | |
1741 | return 0; | |
1742 | } | |
1743 | ||
8ceee660 BH |
1744 | /************************************************************************** |
1745 | * | |
754c653a | 1746 | * Revision-dependent attributes used by efx.c and nic.c |
8ceee660 BH |
1747 | * |
1748 | ************************************************************************** | |
1749 | */ | |
1750 | ||
6c8c2513 | 1751 | const struct efx_nic_type falcon_a1_nic_type = { |
ef2b90ee BH |
1752 | .probe = falcon_probe_nic, |
1753 | .remove = falcon_remove_nic, | |
1754 | .init = falcon_init_nic, | |
1755 | .fini = efx_port_dummy_op_void, | |
1756 | .monitor = falcon_monitor, | |
0e2a9c7c BH |
1757 | .map_reset_reason = falcon_map_reset_reason, |
1758 | .map_reset_flags = falcon_map_reset_flags, | |
ef2b90ee BH |
1759 | .reset = falcon_reset_hw, |
1760 | .probe_port = falcon_probe_port, | |
1761 | .remove_port = falcon_remove_port, | |
40641ed9 | 1762 | .handle_global_event = falcon_handle_global_event, |
ef2b90ee BH |
1763 | .prepare_flush = falcon_prepare_flush, |
1764 | .update_stats = falcon_update_nic_stats, | |
1765 | .start_stats = falcon_start_nic_stats, | |
1766 | .stop_stats = falcon_stop_nic_stats, | |
06629f07 | 1767 | .set_id_led = falcon_set_id_led, |
ef2b90ee | 1768 | .push_irq_moderation = falcon_push_irq_moderation, |
d3245b28 | 1769 | .reconfigure_port = falcon_reconfigure_port, |
710b208d BH |
1770 | .reconfigure_mac = falcon_reconfigure_xmac, |
1771 | .check_mac_fault = falcon_xmac_check_fault, | |
89c758fa BH |
1772 | .get_wol = falcon_get_wol, |
1773 | .set_wol = falcon_set_wol, | |
1774 | .resume_wol = efx_port_dummy_op_void, | |
0aa3fbaa | 1775 | .test_nvram = falcon_test_nvram, |
b895d73e | 1776 | |
daeda630 | 1777 | .revision = EFX_REV_FALCON_A1, |
8ceee660 | 1778 | .mem_map_size = 0x20000, |
3e6c4538 BH |
1779 | .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER, |
1780 | .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER, | |
1781 | .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER, | |
1782 | .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER, | |
1783 | .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER, | |
6d51d307 | 1784 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
8ceee660 BH |
1785 | .rx_buffer_padding = 0x24, |
1786 | .max_interrupt_mode = EFX_INT_MODE_MSI, | |
1787 | .phys_addr_channels = 4, | |
0228f5cd BH |
1788 | .tx_dc_base = 0x130000, |
1789 | .rx_dc_base = 0x100000, | |
c383b537 | 1790 | .offload_features = NETIF_F_IP_CSUM, |
8ceee660 BH |
1791 | }; |
1792 | ||
6c8c2513 | 1793 | const struct efx_nic_type falcon_b0_nic_type = { |
ef2b90ee BH |
1794 | .probe = falcon_probe_nic, |
1795 | .remove = falcon_remove_nic, | |
1796 | .init = falcon_init_nic, | |
1797 | .fini = efx_port_dummy_op_void, | |
1798 | .monitor = falcon_monitor, | |
0e2a9c7c BH |
1799 | .map_reset_reason = falcon_map_reset_reason, |
1800 | .map_reset_flags = falcon_map_reset_flags, | |
ef2b90ee BH |
1801 | .reset = falcon_reset_hw, |
1802 | .probe_port = falcon_probe_port, | |
1803 | .remove_port = falcon_remove_port, | |
40641ed9 | 1804 | .handle_global_event = falcon_handle_global_event, |
ef2b90ee BH |
1805 | .prepare_flush = falcon_prepare_flush, |
1806 | .update_stats = falcon_update_nic_stats, | |
1807 | .start_stats = falcon_start_nic_stats, | |
1808 | .stop_stats = falcon_stop_nic_stats, | |
06629f07 | 1809 | .set_id_led = falcon_set_id_led, |
ef2b90ee | 1810 | .push_irq_moderation = falcon_push_irq_moderation, |
d3245b28 | 1811 | .reconfigure_port = falcon_reconfigure_port, |
710b208d BH |
1812 | .reconfigure_mac = falcon_reconfigure_xmac, |
1813 | .check_mac_fault = falcon_xmac_check_fault, | |
89c758fa BH |
1814 | .get_wol = falcon_get_wol, |
1815 | .set_wol = falcon_set_wol, | |
1816 | .resume_wol = efx_port_dummy_op_void, | |
9bfc4bb1 | 1817 | .test_registers = falcon_b0_test_registers, |
0aa3fbaa | 1818 | .test_nvram = falcon_test_nvram, |
b895d73e | 1819 | |
daeda630 | 1820 | .revision = EFX_REV_FALCON_B0, |
8ceee660 BH |
1821 | /* Map everything up to and including the RSS indirection |
1822 | * table. Don't map MSI-X table, MSI-X PBA since Linux | |
1823 | * requires that they not be mapped. */ | |
3e6c4538 BH |
1824 | .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL + |
1825 | FR_BZ_RX_INDIRECTION_TBL_STEP * | |
1826 | FR_BZ_RX_INDIRECTION_TBL_ROWS), | |
1827 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, | |
1828 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | |
1829 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | |
1830 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, | |
1831 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, | |
6d51d307 | 1832 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
39c9cf07 | 1833 | .rx_buffer_hash_size = 0x10, |
8ceee660 BH |
1834 | .rx_buffer_padding = 0, |
1835 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | |
1836 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy | |
1837 | * interrupt handler only supports 32 | |
1838 | * channels */ | |
0228f5cd BH |
1839 | .tx_dc_base = 0x130000, |
1840 | .rx_dc_base = 0x100000, | |
b4187e42 | 1841 | .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE, |
8ceee660 BH |
1842 | }; |
1843 |