sfc: Add RX packet timestamping for EF10
[deliverable/linux.git] / drivers / net / ethernet / sfc / mcdi.c
CommitLineData
afd4aea0 1/****************************************************************************
f7a6d2c4
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2 * Driver for Solarflare network controllers and boards
3 * Copyright 2008-2013 Solarflare Communications Inc.
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include <linux/delay.h>
251111d9 11#include <asm/cmpxchg.h>
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12#include "net_driver.h"
13#include "nic.h"
14#include "io.h"
8b8a95a1 15#include "farch_regs.h"
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16#include "mcdi_pcol.h"
17#include "phy.h"
18
19/**************************************************************************
20 *
21 * Management-Controller-to-Driver Interface
22 *
23 **************************************************************************
24 */
25
ebf98e79 26#define MCDI_RPC_TIMEOUT (10 * HZ)
afd4aea0 27
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28/* A reboot/assertion causes the MCDI status word to be set after the
29 * command word is set or a REBOOT event is sent. If we notice a reboot
b2d32f03 30 * via these mechanisms then wait 250ms for the status word to be set.
d36a08b4 31 */
3f713bf4 32#define MCDI_STATUS_DELAY_US 100
b2d32f03 33#define MCDI_STATUS_DELAY_COUNT 2500
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34#define MCDI_STATUS_SLEEP_MS \
35 (MCDI_STATUS_DELAY_US * MCDI_STATUS_DELAY_COUNT / 1000)
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36
37#define SEQ_MASK \
38 EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
39
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40struct efx_mcdi_async_param {
41 struct list_head list;
42 unsigned int cmd;
43 size_t inlen;
44 size_t outlen;
1e0b8120 45 bool quiet;
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46 efx_mcdi_async_completer *complete;
47 unsigned long cookie;
48 /* followed by request/response buffer */
49};
50
51static void efx_mcdi_timeout_async(unsigned long context);
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52static int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
53 bool *was_attached_out);
5731d7b3 54static bool efx_mcdi_poll_once(struct efx_nic *efx);
cade715f 55
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56static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
57{
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58 EFX_BUG_ON_PARANOID(!efx->mcdi);
59 return &efx->mcdi->iface;
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60}
61
f073dde0 62int efx_mcdi_init(struct efx_nic *efx)
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63{
64 struct efx_mcdi_iface *mcdi;
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65 bool already_attached;
66 int rc;
afd4aea0 67
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68 efx->mcdi = kzalloc(sizeof(*efx->mcdi), GFP_KERNEL);
69 if (!efx->mcdi)
70 return -ENOMEM;
71
afd4aea0 72 mcdi = efx_mcdi(efx);
cade715f 73 mcdi->efx = efx;
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74 init_waitqueue_head(&mcdi->wq);
75 spin_lock_init(&mcdi->iface_lock);
251111d9 76 mcdi->state = MCDI_STATE_QUIESCENT;
afd4aea0 77 mcdi->mode = MCDI_MODE_POLL;
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78 spin_lock_init(&mcdi->async_lock);
79 INIT_LIST_HEAD(&mcdi->async_list);
80 setup_timer(&mcdi->async_timer, efx_mcdi_timeout_async,
81 (unsigned long)mcdi);
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82
83 (void) efx_mcdi_poll_reboot(efx);
d36a08b4 84 mcdi->new_epoch = true;
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85
86 /* Recover from a failed assertion before probing */
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87 rc = efx_mcdi_handle_assertion(efx);
88 if (rc)
89 return rc;
90
91 /* Let the MC (and BMC, if this is a LOM) know that the driver
92 * is loaded. We should do this before we reset the NIC.
93 */
94 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
95 if (rc) {
96 netif_err(efx, probe, efx->net_dev,
97 "Unable to register driver with MCPU\n");
98 return rc;
99 }
100 if (already_attached)
101 /* Not a fatal error */
102 netif_err(efx, probe, efx->net_dev,
103 "Host already registered with MCPU\n");
104
105 return 0;
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106}
107
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108void efx_mcdi_fini(struct efx_nic *efx)
109{
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110 if (!efx->mcdi)
111 return;
112
113 BUG_ON(efx->mcdi->iface.state != MCDI_STATE_QUIESCENT);
114
115 /* Relinquish the device (back to the BMC, if this is a LOM) */
116 efx_mcdi_drv_attach(efx, false, NULL);
117
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118 kfree(efx->mcdi);
119}
120
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121static void efx_mcdi_send_request(struct efx_nic *efx, unsigned cmd,
122 const efx_dword_t *inbuf, size_t inlen)
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123{
124 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
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125 efx_dword_t hdr[2];
126 size_t hdr_len;
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127 u32 xflags, seqno;
128
251111d9 129 BUG_ON(mcdi->state == MCDI_STATE_QUIESCENT);
afd4aea0 130
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131 /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
132 spin_lock_bh(&mcdi->iface_lock);
133 ++mcdi->seqno;
134 spin_unlock_bh(&mcdi->iface_lock);
135
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136 seqno = mcdi->seqno & SEQ_MASK;
137 xflags = 0;
138 if (mcdi->mode == MCDI_MODE_EVENTS)
139 xflags |= MCDI_HEADER_XFLAGS_EVREQ;
140
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141 if (efx->type->mcdi_max_ver == 1) {
142 /* MCDI v1 */
d36a08b4 143 EFX_POPULATE_DWORD_7(hdr[0],
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144 MCDI_HEADER_RESPONSE, 0,
145 MCDI_HEADER_RESYNC, 1,
146 MCDI_HEADER_CODE, cmd,
147 MCDI_HEADER_DATALEN, inlen,
148 MCDI_HEADER_SEQ, seqno,
d36a08b4
DP
149 MCDI_HEADER_XFLAGS, xflags,
150 MCDI_HEADER_NOT_EPOCH, !mcdi->new_epoch);
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151 hdr_len = 4;
152 } else {
153 /* MCDI v2 */
154 BUG_ON(inlen > MCDI_CTL_SDU_LEN_MAX_V2);
d36a08b4 155 EFX_POPULATE_DWORD_7(hdr[0],
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156 MCDI_HEADER_RESPONSE, 0,
157 MCDI_HEADER_RESYNC, 1,
158 MCDI_HEADER_CODE, MC_CMD_V2_EXTN,
159 MCDI_HEADER_DATALEN, 0,
160 MCDI_HEADER_SEQ, seqno,
d36a08b4
DP
161 MCDI_HEADER_XFLAGS, xflags,
162 MCDI_HEADER_NOT_EPOCH, !mcdi->new_epoch);
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163 EFX_POPULATE_DWORD_2(hdr[1],
164 MC_CMD_V2_EXTN_IN_EXTENDED_CMD, cmd,
165 MC_CMD_V2_EXTN_IN_ACTUAL_LEN, inlen);
166 hdr_len = 8;
167 }
afd4aea0 168
df2cd8af 169 efx->type->mcdi_request(efx, hdr, hdr_len, inbuf, inlen);
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170
171 mcdi->new_epoch = false;
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172}
173
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174static int efx_mcdi_errno(unsigned int mcdi_err)
175{
176 switch (mcdi_err) {
177 case 0:
178 return 0;
179#define TRANSLATE_ERROR(name) \
180 case MC_CMD_ERR_ ## name: \
181 return -name;
df2cd8af 182 TRANSLATE_ERROR(EPERM);
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183 TRANSLATE_ERROR(ENOENT);
184 TRANSLATE_ERROR(EINTR);
df2cd8af 185 TRANSLATE_ERROR(EAGAIN);
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186 TRANSLATE_ERROR(EACCES);
187 TRANSLATE_ERROR(EBUSY);
188 TRANSLATE_ERROR(EINVAL);
189 TRANSLATE_ERROR(EDEADLK);
190 TRANSLATE_ERROR(ENOSYS);
191 TRANSLATE_ERROR(ETIME);
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192 TRANSLATE_ERROR(EALREADY);
193 TRANSLATE_ERROR(ENOSPC);
5bc283e5 194#undef TRANSLATE_ERROR
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195 case MC_CMD_ERR_ENOTSUP:
196 return -EOPNOTSUPP;
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197 case MC_CMD_ERR_ALLOC_FAIL:
198 return -ENOBUFS;
199 case MC_CMD_ERR_MAC_EXIST:
200 return -EADDRINUSE;
5bc283e5 201 default:
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202 return -EPROTO;
203 }
204}
205
206static void efx_mcdi_read_response_header(struct efx_nic *efx)
207{
208 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
209 unsigned int respseq, respcmd, error;
210 efx_dword_t hdr;
211
212 efx->type->mcdi_read_response(efx, &hdr, 0, 4);
213 respseq = EFX_DWORD_FIELD(hdr, MCDI_HEADER_SEQ);
214 respcmd = EFX_DWORD_FIELD(hdr, MCDI_HEADER_CODE);
215 error = EFX_DWORD_FIELD(hdr, MCDI_HEADER_ERROR);
216
217 if (respcmd != MC_CMD_V2_EXTN) {
218 mcdi->resp_hdr_len = 4;
219 mcdi->resp_data_len = EFX_DWORD_FIELD(hdr, MCDI_HEADER_DATALEN);
220 } else {
221 efx->type->mcdi_read_response(efx, &hdr, 4, 4);
222 mcdi->resp_hdr_len = 8;
223 mcdi->resp_data_len =
224 EFX_DWORD_FIELD(hdr, MC_CMD_V2_EXTN_IN_ACTUAL_LEN);
225 }
226
227 if (error && mcdi->resp_data_len == 0) {
228 netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
229 mcdi->resprc = -EIO;
230 } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
231 netif_err(efx, hw, efx->net_dev,
232 "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
233 respseq, mcdi->seqno);
234 mcdi->resprc = -EIO;
235 } else if (error) {
236 efx->type->mcdi_read_response(efx, &hdr, mcdi->resp_hdr_len, 4);
237 mcdi->resprc =
238 efx_mcdi_errno(EFX_DWORD_FIELD(hdr, EFX_DWORD_0));
239 } else {
240 mcdi->resprc = 0;
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241 }
242}
243
5731d7b3
RS
244static bool efx_mcdi_poll_once(struct efx_nic *efx)
245{
246 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
247
248 rmb();
249 if (!efx->type->mcdi_poll_response(efx))
250 return false;
251
252 spin_lock_bh(&mcdi->iface_lock);
253 efx_mcdi_read_response_header(efx);
254 spin_unlock_bh(&mcdi->iface_lock);
255
256 return true;
257}
258
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259static int efx_mcdi_poll(struct efx_nic *efx)
260{
261 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
ebf98e79 262 unsigned long time, finish;
5bc283e5 263 unsigned int spins;
5bc283e5 264 int rc;
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265
266 /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
5bc283e5 267 rc = efx_mcdi_poll_reboot(efx);
df2cd8af 268 if (rc) {
369327fa 269 spin_lock_bh(&mcdi->iface_lock);
df2cd8af
BH
270 mcdi->resprc = rc;
271 mcdi->resp_hdr_len = 0;
272 mcdi->resp_data_len = 0;
369327fa 273 spin_unlock_bh(&mcdi->iface_lock);
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274 return 0;
275 }
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276
277 /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
278 * because generally mcdi responses are fast. After that, back off
279 * and poll once a jiffy (approximately)
280 */
281 spins = TICK_USEC;
ebf98e79 282 finish = jiffies + MCDI_RPC_TIMEOUT;
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283
284 while (1) {
285 if (spins != 0) {
286 --spins;
287 udelay(1);
55029c1d
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288 } else {
289 schedule_timeout_uninterruptible(1);
290 }
afd4aea0 291
ebf98e79 292 time = jiffies;
afd4aea0 293
5731d7b3 294 if (efx_mcdi_poll_once(efx))
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295 break;
296
ebf98e79 297 if (time_after(time, finish))
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298 return -ETIMEDOUT;
299 }
300
afd4aea0
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301 /* Return rc=0 like wait_event_timeout() */
302 return 0;
303}
304
876be083
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305/* Test and clear MC-rebooted flag for this port/function; reset
306 * software state as necessary.
307 */
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308int efx_mcdi_poll_reboot(struct efx_nic *efx)
309{
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310 if (!efx->mcdi)
311 return 0;
afd4aea0 312
cd0ecc9a 313 return efx->type->mcdi_poll_reboot(efx);
afd4aea0
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314}
315
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316static bool efx_mcdi_acquire_async(struct efx_mcdi_iface *mcdi)
317{
318 return cmpxchg(&mcdi->state,
319 MCDI_STATE_QUIESCENT, MCDI_STATE_RUNNING_ASYNC) ==
320 MCDI_STATE_QUIESCENT;
321}
322
323static void efx_mcdi_acquire_sync(struct efx_mcdi_iface *mcdi)
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324{
325 /* Wait until the interface becomes QUIESCENT and we win the race
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326 * to mark it RUNNING_SYNC.
327 */
afd4aea0 328 wait_event(mcdi->wq,
251111d9 329 cmpxchg(&mcdi->state,
cade715f 330 MCDI_STATE_QUIESCENT, MCDI_STATE_RUNNING_SYNC) ==
251111d9 331 MCDI_STATE_QUIESCENT);
afd4aea0
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332}
333
334static int efx_mcdi_await_completion(struct efx_nic *efx)
335{
336 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
337
251111d9
BH
338 if (wait_event_timeout(mcdi->wq, mcdi->state == MCDI_STATE_COMPLETED,
339 MCDI_RPC_TIMEOUT) == 0)
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340 return -ETIMEDOUT;
341
342 /* Check if efx_mcdi_set_mode() switched us back to polled completions.
343 * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
344 * completed the request first, then we'll just end up completing the
345 * request again, which is safe.
346 *
347 * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
348 * wait_event_timeout() implicitly provides.
349 */
350 if (mcdi->mode == MCDI_MODE_POLL)
351 return efx_mcdi_poll(efx);
352
353 return 0;
354}
355
cade715f
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356/* If the interface is RUNNING_SYNC, switch to COMPLETED and wake the
357 * requester. Return whether this was done. Does not take any locks.
358 */
359static bool efx_mcdi_complete_sync(struct efx_mcdi_iface *mcdi)
afd4aea0 360{
cade715f
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361 if (cmpxchg(&mcdi->state,
362 MCDI_STATE_RUNNING_SYNC, MCDI_STATE_COMPLETED) ==
363 MCDI_STATE_RUNNING_SYNC) {
afd4aea0
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364 wake_up(&mcdi->wq);
365 return true;
366 }
367
368 return false;
369}
370
371static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
372{
cade715f
BH
373 if (mcdi->mode == MCDI_MODE_EVENTS) {
374 struct efx_mcdi_async_param *async;
375 struct efx_nic *efx = mcdi->efx;
376
377 /* Process the asynchronous request queue */
378 spin_lock_bh(&mcdi->async_lock);
379 async = list_first_entry_or_null(
380 &mcdi->async_list, struct efx_mcdi_async_param, list);
381 if (async) {
382 mcdi->state = MCDI_STATE_RUNNING_ASYNC;
383 efx_mcdi_send_request(efx, async->cmd,
384 (const efx_dword_t *)(async + 1),
385 async->inlen);
386 mod_timer(&mcdi->async_timer,
387 jiffies + MCDI_RPC_TIMEOUT);
388 }
389 spin_unlock_bh(&mcdi->async_lock);
390
391 if (async)
392 return;
393 }
394
251111d9 395 mcdi->state = MCDI_STATE_QUIESCENT;
afd4aea0
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396 wake_up(&mcdi->wq);
397}
398
cade715f
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399/* If the interface is RUNNING_ASYNC, switch to COMPLETED, call the
400 * asynchronous completion function, and release the interface.
401 * Return whether this was done. Must be called in bh-disabled
402 * context. Will take iface_lock and async_lock.
403 */
404static bool efx_mcdi_complete_async(struct efx_mcdi_iface *mcdi, bool timeout)
405{
406 struct efx_nic *efx = mcdi->efx;
407 struct efx_mcdi_async_param *async;
1e0b8120 408 size_t hdr_len, data_len, err_len;
cade715f 409 efx_dword_t *outbuf;
1e0b8120 410 MCDI_DECLARE_BUF_OUT_OR_ERR(errbuf, 0);
cade715f
BH
411 int rc;
412
413 if (cmpxchg(&mcdi->state,
414 MCDI_STATE_RUNNING_ASYNC, MCDI_STATE_COMPLETED) !=
415 MCDI_STATE_RUNNING_ASYNC)
416 return false;
417
418 spin_lock(&mcdi->iface_lock);
419 if (timeout) {
420 /* Ensure that if the completion event arrives later,
421 * the seqno check in efx_mcdi_ev_cpl() will fail
422 */
423 ++mcdi->seqno;
424 ++mcdi->credits;
425 rc = -ETIMEDOUT;
426 hdr_len = 0;
427 data_len = 0;
428 } else {
429 rc = mcdi->resprc;
430 hdr_len = mcdi->resp_hdr_len;
431 data_len = mcdi->resp_data_len;
432 }
433 spin_unlock(&mcdi->iface_lock);
434
435 /* Stop the timer. In case the timer function is running, we
436 * must wait for it to return so that there is no possibility
437 * of it aborting the next request.
438 */
439 if (!timeout)
440 del_timer_sync(&mcdi->async_timer);
441
442 spin_lock(&mcdi->async_lock);
443 async = list_first_entry(&mcdi->async_list,
444 struct efx_mcdi_async_param, list);
445 list_del(&async->list);
446 spin_unlock(&mcdi->async_lock);
447
448 outbuf = (efx_dword_t *)(async + 1);
449 efx->type->mcdi_read_response(efx, outbuf, hdr_len,
450 min(async->outlen, data_len));
1e0b8120
EC
451 if (!timeout && rc && !async->quiet) {
452 err_len = min(sizeof(errbuf), data_len);
453 efx->type->mcdi_read_response(efx, errbuf, hdr_len,
454 sizeof(errbuf));
455 efx_mcdi_display_error(efx, async->cmd, async->inlen, errbuf,
456 err_len, rc);
457 }
cade715f
BH
458 async->complete(efx, async->cookie, rc, outbuf, data_len);
459 kfree(async);
460
461 efx_mcdi_release(mcdi);
462
463 return true;
464}
465
afd4aea0 466static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
5bc283e5 467 unsigned int datalen, unsigned int mcdi_err)
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468{
469 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
470 bool wake = false;
471
472 spin_lock(&mcdi->iface_lock);
473
474 if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
475 if (mcdi->credits)
476 /* The request has been cancelled */
477 --mcdi->credits;
478 else
62776d03
BH
479 netif_err(efx, hw, efx->net_dev,
480 "MC response mismatch tx seq 0x%x rx "
481 "seq 0x%x\n", seqno, mcdi->seqno);
afd4aea0 482 } else {
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483 if (efx->type->mcdi_max_ver >= 2) {
484 /* MCDI v2 responses don't fit in an event */
485 efx_mcdi_read_response_header(efx);
486 } else {
487 mcdi->resprc = efx_mcdi_errno(mcdi_err);
488 mcdi->resp_hdr_len = 4;
489 mcdi->resp_data_len = datalen;
490 }
afd4aea0
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491
492 wake = true;
493 }
494
495 spin_unlock(&mcdi->iface_lock);
496
cade715f
BH
497 if (wake) {
498 if (!efx_mcdi_complete_async(mcdi, false))
499 (void) efx_mcdi_complete_sync(mcdi);
500
501 /* If the interface isn't RUNNING_ASYNC or
502 * RUNNING_SYNC then we've received a duplicate
503 * completion after we've already transitioned back to
504 * QUIESCENT. [A subsequent invocation would increment
505 * seqno, so would have failed the seqno check].
506 */
507 }
508}
509
510static void efx_mcdi_timeout_async(unsigned long context)
511{
512 struct efx_mcdi_iface *mcdi = (struct efx_mcdi_iface *)context;
513
514 efx_mcdi_complete_async(mcdi, true);
afd4aea0
BH
515}
516
2f4bcdcc
BH
517static int
518efx_mcdi_check_supported(struct efx_nic *efx, unsigned int cmd, size_t inlen)
519{
520 if (efx->type->mcdi_max_ver < 0 ||
521 (efx->type->mcdi_max_ver < 2 &&
522 cmd > MC_CMD_CMD_SPACE_ESCAPE_7))
523 return -EINVAL;
524
525 if (inlen > MCDI_CTL_SDU_LEN_MAX_V2 ||
526 (efx->type->mcdi_max_ver < 2 &&
527 inlen > MCDI_CTL_SDU_LEN_MAX_V1))
528 return -EMSGSIZE;
529
530 return 0;
531}
532
1e0b8120
EC
533static int _efx_mcdi_rpc_finish(struct efx_nic *efx, unsigned cmd, size_t inlen,
534 efx_dword_t *outbuf, size_t outlen,
535 size_t *outlen_actual, bool quiet)
536{
537 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
538 MCDI_DECLARE_BUF_OUT_OR_ERR(errbuf, 0);
539 int rc;
540
541 if (mcdi->mode == MCDI_MODE_POLL)
542 rc = efx_mcdi_poll(efx);
543 else
544 rc = efx_mcdi_await_completion(efx);
545
546 if (rc != 0) {
547 netif_err(efx, hw, efx->net_dev,
548 "MC command 0x%x inlen %d mode %d timed out\n",
549 cmd, (int)inlen, mcdi->mode);
550
551 if (mcdi->mode == MCDI_MODE_EVENTS && efx_mcdi_poll_once(efx)) {
552 netif_err(efx, hw, efx->net_dev,
553 "MCDI request was completed without an event\n");
554 rc = 0;
555 }
556
557 /* Close the race with efx_mcdi_ev_cpl() executing just too late
558 * and completing a request we've just cancelled, by ensuring
559 * that the seqno check therein fails.
560 */
561 spin_lock_bh(&mcdi->iface_lock);
562 ++mcdi->seqno;
563 ++mcdi->credits;
564 spin_unlock_bh(&mcdi->iface_lock);
565 }
566
567 if (rc != 0) {
568 if (outlen_actual)
569 *outlen_actual = 0;
570 } else {
571 size_t hdr_len, data_len, err_len;
572
573 /* At the very least we need a memory barrier here to ensure
574 * we pick up changes from efx_mcdi_ev_cpl(). Protect against
575 * a spurious efx_mcdi_ev_cpl() running concurrently by
576 * acquiring the iface_lock. */
577 spin_lock_bh(&mcdi->iface_lock);
578 rc = mcdi->resprc;
579 hdr_len = mcdi->resp_hdr_len;
580 data_len = mcdi->resp_data_len;
581 err_len = min(sizeof(errbuf), data_len);
582 spin_unlock_bh(&mcdi->iface_lock);
583
584 BUG_ON(rc > 0);
585
586 efx->type->mcdi_read_response(efx, outbuf, hdr_len,
587 min(outlen, data_len));
588 if (outlen_actual)
589 *outlen_actual = data_len;
590
591 efx->type->mcdi_read_response(efx, errbuf, hdr_len, err_len);
592
593 if (cmd == MC_CMD_REBOOT && rc == -EIO) {
594 /* Don't reset if MC_CMD_REBOOT returns EIO */
595 } else if (rc == -EIO || rc == -EINTR) {
596 netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
597 -rc);
598 efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
599 } else if (rc && !quiet) {
600 efx_mcdi_display_error(efx, cmd, inlen, errbuf, err_len,
601 rc);
602 }
603
604 if (rc == -EIO || rc == -EINTR) {
605 msleep(MCDI_STATUS_SLEEP_MS);
606 efx_mcdi_poll_reboot(efx);
607 mcdi->new_epoch = true;
608 }
609 }
610
611 efx_mcdi_release(mcdi);
612 return rc;
613}
614
615static int _efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
616 const efx_dword_t *inbuf, size_t inlen,
617 efx_dword_t *outbuf, size_t outlen,
618 size_t *outlen_actual, bool quiet)
619{
620 int rc;
621
622 rc = efx_mcdi_rpc_start(efx, cmd, inbuf, inlen);
623 if (rc) {
624 if (outlen_actual)
625 *outlen_actual = 0;
626 return rc;
627 }
628 return _efx_mcdi_rpc_finish(efx, cmd, inlen, outbuf, outlen,
629 outlen_actual, quiet);
630}
631
afd4aea0 632int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
9528b921
BH
633 const efx_dword_t *inbuf, size_t inlen,
634 efx_dword_t *outbuf, size_t outlen,
afd4aea0 635 size_t *outlen_actual)
c3cba721 636{
1e0b8120
EC
637 return _efx_mcdi_rpc(efx, cmd, inbuf, inlen, outbuf, outlen,
638 outlen_actual, false);
639}
df2cd8af 640
1e0b8120
EC
641/* Normally, on receiving an error code in the MCDI response,
642 * efx_mcdi_rpc will log an error message containing (among other
643 * things) the raw error code, by means of efx_mcdi_display_error.
644 * This _quiet version suppresses that; if the caller wishes to log
645 * the error conditionally on the return code, it should call this
646 * function and is then responsible for calling efx_mcdi_display_error
647 * as needed.
648 */
649int efx_mcdi_rpc_quiet(struct efx_nic *efx, unsigned cmd,
650 const efx_dword_t *inbuf, size_t inlen,
651 efx_dword_t *outbuf, size_t outlen,
652 size_t *outlen_actual)
653{
654 return _efx_mcdi_rpc(efx, cmd, inbuf, inlen, outbuf, outlen,
655 outlen_actual, true);
c3cba721
SH
656}
657
df2cd8af
BH
658int efx_mcdi_rpc_start(struct efx_nic *efx, unsigned cmd,
659 const efx_dword_t *inbuf, size_t inlen)
afd4aea0
BH
660{
661 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
2f4bcdcc 662 int rc;
c3cba721 663
2f4bcdcc
BH
664 rc = efx_mcdi_check_supported(efx, cmd, inlen);
665 if (rc)
666 return rc;
df2cd8af 667
74cd60a4
JC
668 if (efx->mc_bist_for_other_fn)
669 return -ENETDOWN;
670
cade715f 671 efx_mcdi_acquire_sync(mcdi);
2f4bcdcc 672 efx_mcdi_send_request(efx, cmd, inbuf, inlen);
df2cd8af 673 return 0;
c3cba721
SH
674}
675
1e0b8120
EC
676static int _efx_mcdi_rpc_async(struct efx_nic *efx, unsigned int cmd,
677 const efx_dword_t *inbuf, size_t inlen,
678 size_t outlen,
679 efx_mcdi_async_completer *complete,
680 unsigned long cookie, bool quiet)
cade715f
BH
681{
682 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
683 struct efx_mcdi_async_param *async;
684 int rc;
685
686 rc = efx_mcdi_check_supported(efx, cmd, inlen);
687 if (rc)
688 return rc;
689
74cd60a4
JC
690 if (efx->mc_bist_for_other_fn)
691 return -ENETDOWN;
692
cade715f
BH
693 async = kmalloc(sizeof(*async) + ALIGN(max(inlen, outlen), 4),
694 GFP_ATOMIC);
695 if (!async)
696 return -ENOMEM;
697
698 async->cmd = cmd;
699 async->inlen = inlen;
700 async->outlen = outlen;
1e0b8120 701 async->quiet = quiet;
cade715f
BH
702 async->complete = complete;
703 async->cookie = cookie;
704 memcpy(async + 1, inbuf, inlen);
705
706 spin_lock_bh(&mcdi->async_lock);
707
708 if (mcdi->mode == MCDI_MODE_EVENTS) {
709 list_add_tail(&async->list, &mcdi->async_list);
710
711 /* If this is at the front of the queue, try to start it
712 * immediately
713 */
714 if (mcdi->async_list.next == &async->list &&
715 efx_mcdi_acquire_async(mcdi)) {
716 efx_mcdi_send_request(efx, cmd, inbuf, inlen);
717 mod_timer(&mcdi->async_timer,
718 jiffies + MCDI_RPC_TIMEOUT);
719 }
720 } else {
721 kfree(async);
722 rc = -ENETDOWN;
723 }
724
725 spin_unlock_bh(&mcdi->async_lock);
726
727 return rc;
728}
729
1e0b8120
EC
730/**
731 * efx_mcdi_rpc_async - Schedule an MCDI command to run asynchronously
732 * @efx: NIC through which to issue the command
733 * @cmd: Command type number
734 * @inbuf: Command parameters
735 * @inlen: Length of command parameters, in bytes
736 * @outlen: Length to allocate for response buffer, in bytes
737 * @complete: Function to be called on completion or cancellation.
738 * @cookie: Arbitrary value to be passed to @complete.
739 *
740 * This function does not sleep and therefore may be called in atomic
741 * context. It will fail if event queues are disabled or if MCDI
742 * event completions have been disabled due to an error.
743 *
744 * If it succeeds, the @complete function will be called exactly once
745 * in atomic context, when one of the following occurs:
746 * (a) the completion event is received (in NAPI context)
747 * (b) event queues are disabled (in the process that disables them)
748 * (c) the request times-out (in timer context)
749 */
750int
751efx_mcdi_rpc_async(struct efx_nic *efx, unsigned int cmd,
752 const efx_dword_t *inbuf, size_t inlen, size_t outlen,
753 efx_mcdi_async_completer *complete, unsigned long cookie)
754{
755 return _efx_mcdi_rpc_async(efx, cmd, inbuf, inlen, outlen, complete,
756 cookie, false);
757}
758
759int efx_mcdi_rpc_async_quiet(struct efx_nic *efx, unsigned int cmd,
760 const efx_dword_t *inbuf, size_t inlen,
761 size_t outlen, efx_mcdi_async_completer *complete,
762 unsigned long cookie)
763{
764 return _efx_mcdi_rpc_async(efx, cmd, inbuf, inlen, outlen, complete,
765 cookie, true);
766}
767
c3cba721 768int efx_mcdi_rpc_finish(struct efx_nic *efx, unsigned cmd, size_t inlen,
9528b921
BH
769 efx_dword_t *outbuf, size_t outlen,
770 size_t *outlen_actual)
c3cba721 771{
1e0b8120
EC
772 return _efx_mcdi_rpc_finish(efx, cmd, inlen, outbuf, outlen,
773 outlen_actual, false);
774}
5bc283e5 775
1e0b8120
EC
776int efx_mcdi_rpc_finish_quiet(struct efx_nic *efx, unsigned cmd, size_t inlen,
777 efx_dword_t *outbuf, size_t outlen,
778 size_t *outlen_actual)
779{
780 return _efx_mcdi_rpc_finish(efx, cmd, inlen, outbuf, outlen,
781 outlen_actual, true);
782}
3f713bf4 783
1e0b8120
EC
784void efx_mcdi_display_error(struct efx_nic *efx, unsigned cmd,
785 size_t inlen, efx_dword_t *outbuf,
786 size_t outlen, int rc)
787{
788 int code = 0, err_arg = 0;
afd4aea0 789
1e0b8120
EC
790 if (outlen >= MC_CMD_ERR_CODE_OFST + 4)
791 code = MCDI_DWORD(outbuf, ERR_CODE);
792 if (outlen >= MC_CMD_ERR_ARG_OFST + 4)
793 err_arg = MCDI_DWORD(outbuf, ERR_ARG);
794 netif_err(efx, hw, efx->net_dev,
795 "MC command 0x%x inlen %d failed rc=%d (raw=%d) arg=%d\n",
796 cmd, (int)inlen, rc, code, err_arg);
afd4aea0
BH
797}
798
cade715f
BH
799/* Switch to polled MCDI completions. This can be called in various
800 * error conditions with various locks held, so it must be lockless.
801 * Caller is responsible for flushing asynchronous requests later.
802 */
afd4aea0
BH
803void efx_mcdi_mode_poll(struct efx_nic *efx)
804{
805 struct efx_mcdi_iface *mcdi;
806
f3ad5003 807 if (!efx->mcdi)
afd4aea0
BH
808 return;
809
810 mcdi = efx_mcdi(efx);
811 if (mcdi->mode == MCDI_MODE_POLL)
812 return;
813
814 /* We can switch from event completion to polled completion, because
815 * mcdi requests are always completed in shared memory. We do this by
816 * switching the mode to POLL'd then completing the request.
817 * efx_mcdi_await_completion() will then call efx_mcdi_poll().
818 *
819 * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
cade715f 820 * which efx_mcdi_complete_sync() provides for us.
afd4aea0
BH
821 */
822 mcdi->mode = MCDI_MODE_POLL;
823
cade715f
BH
824 efx_mcdi_complete_sync(mcdi);
825}
826
827/* Flush any running or queued asynchronous requests, after event processing
828 * is stopped
829 */
830void efx_mcdi_flush_async(struct efx_nic *efx)
831{
832 struct efx_mcdi_async_param *async, *next;
833 struct efx_mcdi_iface *mcdi;
834
835 if (!efx->mcdi)
836 return;
837
838 mcdi = efx_mcdi(efx);
839
840 /* We must be in polling mode so no more requests can be queued */
841 BUG_ON(mcdi->mode != MCDI_MODE_POLL);
842
843 del_timer_sync(&mcdi->async_timer);
844
845 /* If a request is still running, make sure we give the MC
846 * time to complete it so that the response won't overwrite our
847 * next request.
848 */
849 if (mcdi->state == MCDI_STATE_RUNNING_ASYNC) {
850 efx_mcdi_poll(efx);
851 mcdi->state = MCDI_STATE_QUIESCENT;
852 }
853
854 /* Nothing else will access the async list now, so it is safe
855 * to walk it without holding async_lock. If we hold it while
856 * calling a completer then lockdep may warn that we have
857 * acquired locks in the wrong order.
858 */
859 list_for_each_entry_safe(async, next, &mcdi->async_list, list) {
860 async->complete(efx, async->cookie, -ENETDOWN, NULL, 0);
861 list_del(&async->list);
862 kfree(async);
863 }
afd4aea0
BH
864}
865
866void efx_mcdi_mode_event(struct efx_nic *efx)
867{
868 struct efx_mcdi_iface *mcdi;
869
f3ad5003 870 if (!efx->mcdi)
afd4aea0
BH
871 return;
872
873 mcdi = efx_mcdi(efx);
874
875 if (mcdi->mode == MCDI_MODE_EVENTS)
876 return;
877
878 /* We can't switch from polled to event completion in the middle of a
879 * request, because the completion method is specified in the request.
880 * So acquire the interface to serialise the requestors. We don't need
881 * to acquire the iface_lock to change the mode here, but we do need a
882 * write memory barrier ensure that efx_mcdi_rpc() sees it, which
883 * efx_mcdi_acquire() provides.
884 */
cade715f 885 efx_mcdi_acquire_sync(mcdi);
afd4aea0
BH
886 mcdi->mode = MCDI_MODE_EVENTS;
887 efx_mcdi_release(mcdi);
888}
889
890static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
891{
892 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
893
894 /* If there is an outstanding MCDI request, it has been terminated
895 * either by a BADASSERT or REBOOT event. If the mcdi interface is
896 * in polled mode, then do nothing because the MC reboot handler will
897 * set the header correctly. However, if the mcdi interface is waiting
898 * for a CMDDONE event it won't receive it [and since all MCDI events
899 * are sent to the same queue, we can't be racing with
900 * efx_mcdi_ev_cpl()]
901 *
cade715f
BH
902 * If there is an outstanding asynchronous request, we can't
903 * complete it now (efx_mcdi_complete() would deadlock). The
904 * reset process will take care of this.
905 *
906 * There's a race here with efx_mcdi_send_request(), because
907 * we might receive a REBOOT event *before* the request has
908 * been copied out. In polled mode (during startup) this is
909 * irrelevant, because efx_mcdi_complete_sync() is ignored. In
910 * event mode, this condition is just an edge-case of
911 * receiving a REBOOT event after posting the MCDI
912 * request. Did the mc reboot before or after the copyout? The
913 * best we can do always is just return failure.
afd4aea0
BH
914 */
915 spin_lock(&mcdi->iface_lock);
cade715f 916 if (efx_mcdi_complete_sync(mcdi)) {
afd4aea0
BH
917 if (mcdi->mode == MCDI_MODE_EVENTS) {
918 mcdi->resprc = rc;
df2cd8af
BH
919 mcdi->resp_hdr_len = 0;
920 mcdi->resp_data_len = 0;
18e3ee2c 921 ++mcdi->credits;
afd4aea0 922 }
3f713bf4
BH
923 } else {
924 int count;
925
3f713bf4
BH
926 /* Consume the status word since efx_mcdi_rpc_finish() won't */
927 for (count = 0; count < MCDI_STATUS_DELAY_COUNT; ++count) {
928 if (efx_mcdi_poll_reboot(efx))
929 break;
930 udelay(MCDI_STATUS_DELAY_US);
931 }
d36a08b4 932 mcdi->new_epoch = true;
dfdaa95c
DP
933
934 /* Nobody was waiting for an MCDI request, so trigger a reset */
935 efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
3f713bf4
BH
936 }
937
afd4aea0
BH
938 spin_unlock(&mcdi->iface_lock);
939}
940
74cd60a4
JC
941/* The MC is going down in to BIST mode. set the BIST flag to block
942 * new MCDI, cancel any outstanding MCDI and and schedule a BIST-type reset
943 * (which doesn't actually execute a reset, it waits for the controlling
944 * function to reset it).
945 */
946static void efx_mcdi_ev_bist(struct efx_nic *efx)
947{
948 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
949
950 spin_lock(&mcdi->iface_lock);
951 efx->mc_bist_for_other_fn = true;
952 if (efx_mcdi_complete_sync(mcdi)) {
953 if (mcdi->mode == MCDI_MODE_EVENTS) {
954 mcdi->resprc = -EIO;
955 mcdi->resp_hdr_len = 0;
956 mcdi->resp_data_len = 0;
957 ++mcdi->credits;
958 }
959 }
960 mcdi->new_epoch = true;
961 efx_schedule_reset(efx, RESET_TYPE_MC_BIST);
962 spin_unlock(&mcdi->iface_lock);
963}
964
afd4aea0
BH
965/* Called from falcon_process_eventq for MCDI events */
966void efx_mcdi_process_event(struct efx_channel *channel,
967 efx_qword_t *event)
968{
969 struct efx_nic *efx = channel->efx;
970 int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
971 u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
972
973 switch (code) {
974 case MCDI_EVENT_CODE_BADSSERT:
62776d03
BH
975 netif_err(efx, hw, efx->net_dev,
976 "MC watchdog or assertion failure at 0x%x\n", data);
5bc283e5 977 efx_mcdi_ev_death(efx, -EINTR);
afd4aea0
BH
978 break;
979
980 case MCDI_EVENT_CODE_PMNOTICE:
62776d03 981 netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
afd4aea0
BH
982 break;
983
984 case MCDI_EVENT_CODE_CMDDONE:
985 efx_mcdi_ev_cpl(efx,
986 MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
987 MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
988 MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
989 break;
990
991 case MCDI_EVENT_CODE_LINKCHANGE:
992 efx_mcdi_process_link_change(efx, event);
993 break;
994 case MCDI_EVENT_CODE_SENSOREVT:
995 efx_mcdi_sensor_event(efx, event);
996 break;
997 case MCDI_EVENT_CODE_SCHEDERR:
2d9955be
RS
998 netif_dbg(efx, hw, efx->net_dev,
999 "MC Scheduler alert (0x%x)\n", data);
afd4aea0
BH
1000 break;
1001 case MCDI_EVENT_CODE_REBOOT:
8127d661 1002 case MCDI_EVENT_CODE_MC_REBOOT:
62776d03 1003 netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
5bc283e5 1004 efx_mcdi_ev_death(efx, -EIO);
afd4aea0 1005 break;
74cd60a4
JC
1006 case MCDI_EVENT_CODE_MC_BIST:
1007 netif_info(efx, hw, efx->net_dev, "MC entered BIST mode\n");
1008 efx_mcdi_ev_bist(efx);
1009 break;
afd4aea0
BH
1010 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1011 /* MAC stats are gather lazily. We can ignore this. */
1012 break;
cd2d5b52
BH
1013 case MCDI_EVENT_CODE_FLR:
1014 efx_sriov_flr(efx, MCDI_EVENT_FIELD(*event, FLR_VF));
1015 break;
7c236c43
SH
1016 case MCDI_EVENT_CODE_PTP_RX:
1017 case MCDI_EVENT_CODE_PTP_FAULT:
1018 case MCDI_EVENT_CODE_PTP_PPS:
1019 efx_ptp_event(efx, event);
1020 break;
bd9a265d
JC
1021 case MCDI_EVENT_CODE_PTP_TIME:
1022 efx_time_sync_event(channel, event);
1023 break;
8127d661
BH
1024 case MCDI_EVENT_CODE_TX_FLUSH:
1025 case MCDI_EVENT_CODE_RX_FLUSH:
1026 /* Two flush events will be sent: one to the same event
1027 * queue as completions, and one to event queue 0.
1028 * In the latter case the {RX,TX}_FLUSH_TO_DRIVER
1029 * flag will be set, and we should ignore the event
1030 * because we want to wait for all completions.
1031 */
1032 BUILD_BUG_ON(MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN !=
1033 MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN);
1034 if (!MCDI_EVENT_FIELD(*event, TX_FLUSH_TO_DRIVER))
1035 efx_ef10_handle_drain_event(efx);
1036 break;
3de82b91
AR
1037 case MCDI_EVENT_CODE_TX_ERR:
1038 case MCDI_EVENT_CODE_RX_ERR:
1039 netif_err(efx, hw, efx->net_dev,
1040 "%s DMA error (event: "EFX_QWORD_FMT")\n",
1041 code == MCDI_EVENT_CODE_TX_ERR ? "TX" : "RX",
1042 EFX_QWORD_VAL(*event));
1043 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
1044 break;
afd4aea0 1045 default:
62776d03
BH
1046 netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
1047 code);
afd4aea0
BH
1048 }
1049}
1050
1051/**************************************************************************
1052 *
1053 * Specific request functions
1054 *
1055 **************************************************************************
1056 */
1057
e5f0fd27 1058void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len)
afd4aea0 1059{
8127d661
BH
1060 MCDI_DECLARE_BUF(outbuf,
1061 max(MC_CMD_GET_VERSION_OUT_LEN,
1062 MC_CMD_GET_CAPABILITIES_OUT_LEN));
afd4aea0
BH
1063 size_t outlength;
1064 const __le16 *ver_words;
8127d661 1065 size_t offset;
afd4aea0
BH
1066 int rc;
1067
1068 BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
afd4aea0
BH
1069 rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
1070 outbuf, sizeof(outbuf), &outlength);
1071 if (rc)
1072 goto fail;
05a9320f 1073 if (outlength < MC_CMD_GET_VERSION_OUT_LEN) {
00bbb4a5 1074 rc = -EIO;
afd4aea0
BH
1075 goto fail;
1076 }
1077
1078 ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
8127d661
BH
1079 offset = snprintf(buf, len, "%u.%u.%u.%u",
1080 le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]),
1081 le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3]));
1082
1083 /* EF10 may have multiple datapath firmware variants within a
1084 * single version. Report which variants are running.
1085 */
1086 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) {
1087 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
1088 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
1089 outbuf, sizeof(outbuf), &outlength);
1090 if (rc || outlength < MC_CMD_GET_CAPABILITIES_OUT_LEN)
1091 offset += snprintf(
1092 buf + offset, len - offset, " rx? tx?");
1093 else
1094 offset += snprintf(
1095 buf + offset, len - offset, " rx%x tx%x",
1096 MCDI_WORD(outbuf,
1097 GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID),
1098 MCDI_WORD(outbuf,
1099 GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID));
1100
1101 /* It's theoretically possible for the string to exceed 31
1102 * characters, though in practice the first three version
1103 * components are short enough that this doesn't happen.
1104 */
1105 if (WARN_ON(offset >= len))
1106 buf[0] = 0;
1107 }
1108
e5f0fd27 1109 return;
afd4aea0
BH
1110
1111fail:
62776d03 1112 netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
e5f0fd27 1113 buf[0] = 0;
afd4aea0
BH
1114}
1115
4c75b43a
BH
1116static int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
1117 bool *was_attached)
afd4aea0 1118{
59cfc479 1119 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRV_ATTACH_IN_LEN);
ecb1c9cc 1120 MCDI_DECLARE_BUF(outbuf, MC_CMD_DRV_ATTACH_EXT_OUT_LEN);
afd4aea0
BH
1121 size_t outlen;
1122 int rc;
1123
1124 MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
1125 driver_operating ? 1 : 0);
1126 MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
f2b0befd 1127 MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_FIRMWARE_ID, MC_CMD_FW_LOW_LATENCY);
afd4aea0
BH
1128
1129 rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
1130 outbuf, sizeof(outbuf), &outlen);
1131 if (rc)
1132 goto fail;
00bbb4a5
BH
1133 if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
1134 rc = -EIO;
afd4aea0 1135 goto fail;
00bbb4a5 1136 }
afd4aea0 1137
8349f7f6
BH
1138 if (driver_operating) {
1139 if (outlen >= MC_CMD_DRV_ATTACH_EXT_OUT_LEN) {
1140 efx->mcdi->fn_flags =
1141 MCDI_DWORD(outbuf,
1142 DRV_ATTACH_EXT_OUT_FUNC_FLAGS);
1143 } else {
1144 /* Synthesise flags for Siena */
1145 efx->mcdi->fn_flags =
1146 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL |
1147 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED |
1148 (efx_port_num(efx) == 0) <<
1149 MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY;
1150 }
1151 }
1152
ecb1c9cc
BH
1153 /* We currently assume we have control of the external link
1154 * and are completely trusted by firmware. Abort probing
1155 * if that's not true for this function.
1156 */
1157 if (driver_operating &&
8349f7f6 1158 (efx->mcdi->fn_flags &
ecb1c9cc
BH
1159 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL |
1160 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) !=
1161 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL |
1162 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) {
1163 netif_err(efx, probe, efx->net_dev,
1164 "This driver version only supports one function per port\n");
1165 return -ENODEV;
1166 }
1167
afd4aea0
BH
1168 if (was_attached != NULL)
1169 *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
1170 return 0;
1171
1172fail:
62776d03 1173 netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH
1174 return rc;
1175}
1176
1177int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
6aa9c7f6 1178 u16 *fw_subtype_list, u32 *capabilities)
afd4aea0 1179{
59cfc479 1180 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_BOARD_CFG_OUT_LENMAX);
c5bb0e98 1181 size_t outlen, i;
afd4aea0 1182 int port_num = efx_port_num(efx);
afd4aea0
BH
1183 int rc;
1184
1185 BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
1186
1187 rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
1188 outbuf, sizeof(outbuf), &outlen);
1189 if (rc)
1190 goto fail;
1191
05a9320f 1192 if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) {
00bbb4a5 1193 rc = -EIO;
afd4aea0
BH
1194 goto fail;
1195 }
1196
afd4aea0 1197 if (mac_address)
c5bb0e98
BH
1198 memcpy(mac_address,
1199 port_num ?
1200 MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1) :
1201 MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0),
1202 ETH_ALEN);
bfeed902 1203 if (fw_subtype_list) {
bfeed902 1204 for (i = 0;
c5bb0e98
BH
1205 i < MCDI_VAR_ARRAY_LEN(outlen,
1206 GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST);
1207 i++)
1208 fw_subtype_list[i] = MCDI_ARRAY_WORD(
1209 outbuf, GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST, i);
1210 for (; i < MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM; i++)
1211 fw_subtype_list[i] = 0;
bfeed902 1212 }
6aa9c7f6
MS
1213 if (capabilities) {
1214 if (port_num)
1215 *capabilities = MCDI_DWORD(outbuf,
1216 GET_BOARD_CFG_OUT_CAPABILITIES_PORT1);
1217 else
1218 *capabilities = MCDI_DWORD(outbuf,
1219 GET_BOARD_CFG_OUT_CAPABILITIES_PORT0);
1220 }
afd4aea0
BH
1221
1222 return 0;
1223
1224fail:
62776d03
BH
1225 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
1226 __func__, rc, (int)outlen);
afd4aea0
BH
1227
1228 return rc;
1229}
1230
1231int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
1232{
59cfc479 1233 MCDI_DECLARE_BUF(inbuf, MC_CMD_LOG_CTRL_IN_LEN);
afd4aea0
BH
1234 u32 dest = 0;
1235 int rc;
1236
1237 if (uart)
1238 dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
1239 if (evq)
1240 dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
1241
1242 MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
1243 MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
1244
1245 BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
1246
1247 rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
1248 NULL, 0, NULL);
afd4aea0
BH
1249 return rc;
1250}
1251
1252int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
1253{
59cfc479 1254 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TYPES_OUT_LEN);
afd4aea0
BH
1255 size_t outlen;
1256 int rc;
1257
1258 BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
1259
1260 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
1261 outbuf, sizeof(outbuf), &outlen);
1262 if (rc)
1263 goto fail;
00bbb4a5
BH
1264 if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
1265 rc = -EIO;
afd4aea0 1266 goto fail;
00bbb4a5 1267 }
afd4aea0
BH
1268
1269 *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
1270 return 0;
1271
1272fail:
62776d03
BH
1273 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
1274 __func__, rc);
afd4aea0
BH
1275 return rc;
1276}
1277
1278int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
1279 size_t *size_out, size_t *erase_size_out,
1280 bool *protected_out)
1281{
59cfc479
BH
1282 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_INFO_IN_LEN);
1283 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_INFO_OUT_LEN);
afd4aea0
BH
1284 size_t outlen;
1285 int rc;
1286
1287 MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
1288
1289 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
1290 outbuf, sizeof(outbuf), &outlen);
1291 if (rc)
1292 goto fail;
00bbb4a5
BH
1293 if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
1294 rc = -EIO;
afd4aea0 1295 goto fail;
00bbb4a5 1296 }
afd4aea0
BH
1297
1298 *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
1299 *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
1300 *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
05a9320f 1301 (1 << MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN));
afd4aea0
BH
1302 return 0;
1303
1304fail:
62776d03 1305 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH
1306 return rc;
1307}
1308
2e803407
BH
1309static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
1310{
59cfc479
BH
1311 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_TEST_IN_LEN);
1312 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TEST_OUT_LEN);
2e803407
BH
1313 int rc;
1314
1315 MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
1316
1317 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
1318 outbuf, sizeof(outbuf), NULL);
1319 if (rc)
1320 return rc;
1321
1322 switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
1323 case MC_CMD_NVRAM_TEST_PASS:
1324 case MC_CMD_NVRAM_TEST_NOTSUPP:
1325 return 0;
1326 default:
1327 return -EIO;
1328 }
1329}
1330
1331int efx_mcdi_nvram_test_all(struct efx_nic *efx)
1332{
1333 u32 nvram_types;
1334 unsigned int type;
1335 int rc;
1336
1337 rc = efx_mcdi_nvram_types(efx, &nvram_types);
1338 if (rc)
b548a988 1339 goto fail1;
2e803407
BH
1340
1341 type = 0;
1342 while (nvram_types != 0) {
1343 if (nvram_types & 1) {
1344 rc = efx_mcdi_nvram_test(efx, type);
1345 if (rc)
b548a988 1346 goto fail2;
2e803407
BH
1347 }
1348 type++;
1349 nvram_types >>= 1;
1350 }
1351
1352 return 0;
b548a988
BH
1353
1354fail2:
62776d03
BH
1355 netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
1356 __func__, type);
b548a988 1357fail1:
62776d03 1358 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
b548a988 1359 return rc;
2e803407
BH
1360}
1361
8b2103ad 1362static int efx_mcdi_read_assertion(struct efx_nic *efx)
afd4aea0 1363{
59cfc479 1364 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_ASSERTS_IN_LEN);
1e0b8120 1365 MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, MC_CMD_GET_ASSERTS_OUT_LEN);
c5bb0e98 1366 unsigned int flags, index;
afd4aea0
BH
1367 const char *reason;
1368 size_t outlen;
1369 int retry;
1370 int rc;
1371
8b2103ad
SH
1372 /* Attempt to read any stored assertion state before we reboot
1373 * the mcfw out of the assertion handler. Retry twice, once
afd4aea0
BH
1374 * because a boot-time assertion might cause this command to fail
1375 * with EINTR. And once again because GET_ASSERTS can race with
1376 * MC_CMD_REBOOT running on the other port. */
1377 retry = 2;
1378 do {
8b2103ad 1379 MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
1e0b8120
EC
1380 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_ASSERTS,
1381 inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
1382 outbuf, sizeof(outbuf), &outlen);
afd4aea0
BH
1383 } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
1384
1e0b8120
EC
1385 if (rc) {
1386 efx_mcdi_display_error(efx, MC_CMD_GET_ASSERTS,
1387 MC_CMD_GET_ASSERTS_IN_LEN, outbuf,
1388 outlen, rc);
afd4aea0 1389 return rc;
1e0b8120 1390 }
afd4aea0 1391 if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
00bbb4a5 1392 return -EIO;
afd4aea0 1393
8b2103ad
SH
1394 /* Print out any recorded assertion state */
1395 flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
afd4aea0
BH
1396 if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
1397 return 0;
1398
afd4aea0
BH
1399 reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
1400 ? "system-level assertion"
1401 : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
1402 ? "thread-level assertion"
1403 : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
1404 ? "watchdog reset"
1405 : "unknown assertion";
62776d03
BH
1406 netif_err(efx, hw, efx->net_dev,
1407 "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
1408 MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
1409 MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
afd4aea0
BH
1410
1411 /* Print out the registers */
c5bb0e98
BH
1412 for (index = 0;
1413 index < MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM;
1414 index++)
1415 netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n",
1416 1 + index,
1417 MCDI_ARRAY_DWORD(outbuf, GET_ASSERTS_OUT_GP_REGS_OFFS,
1418 index));
afd4aea0
BH
1419
1420 return 0;
1421}
1422
8b2103ad
SH
1423static void efx_mcdi_exit_assertion(struct efx_nic *efx)
1424{
59cfc479 1425 MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN);
8b2103ad 1426
0f1e54ae
BH
1427 /* If the MC is running debug firmware, it might now be
1428 * waiting for a debugger to attach, but we just want it to
1429 * reboot. We set a flag that makes the command a no-op if it
1430 * has already done so. We don't know what return code to
1431 * expect (0 or -EIO), so ignore it.
1432 */
8b2103ad
SH
1433 BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
1434 MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
1435 MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
0f1e54ae
BH
1436 (void) efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
1437 NULL, 0, NULL);
8b2103ad
SH
1438}
1439
1440int efx_mcdi_handle_assertion(struct efx_nic *efx)
1441{
1442 int rc;
1443
1444 rc = efx_mcdi_read_assertion(efx);
1445 if (rc)
1446 return rc;
1447
1448 efx_mcdi_exit_assertion(efx);
1449
1450 return 0;
1451}
1452
afd4aea0
BH
1453void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1454{
59cfc479 1455 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_ID_LED_IN_LEN);
afd4aea0
BH
1456 int rc;
1457
1458 BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
1459 BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
1460 BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
1461
1462 BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
1463
1464 MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
1465
1466 rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
1467 NULL, 0, NULL);
afd4aea0
BH
1468}
1469
6bff861d 1470static int efx_mcdi_reset_port(struct efx_nic *efx)
afd4aea0 1471{
1e0b8120 1472 return efx_mcdi_rpc(efx, MC_CMD_ENTITY_RESET, NULL, 0, NULL, 0, NULL);
afd4aea0
BH
1473}
1474
6bff861d 1475static int efx_mcdi_reset_mc(struct efx_nic *efx)
afd4aea0 1476{
59cfc479 1477 MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN);
afd4aea0
BH
1478 int rc;
1479
1480 BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
1481 MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
1482 rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
1483 NULL, 0, NULL);
1484 /* White is black, and up is down */
1485 if (rc == -EIO)
1486 return 0;
1487 if (rc == 0)
1488 rc = -EIO;
afd4aea0
BH
1489 return rc;
1490}
1491
6bff861d
BH
1492enum reset_type efx_mcdi_map_reset_reason(enum reset_type reason)
1493{
1494 return RESET_TYPE_RECOVER_OR_ALL;
1495}
1496
1497int efx_mcdi_reset(struct efx_nic *efx, enum reset_type method)
1498{
1499 int rc;
1500
1501 /* Recover from a failed assertion pre-reset */
1502 rc = efx_mcdi_handle_assertion(efx);
1503 if (rc)
1504 return rc;
1505
1506 if (method == RESET_TYPE_WORLD)
1507 return efx_mcdi_reset_mc(efx);
1508 else
1509 return efx_mcdi_reset_port(efx);
1510}
1511
d215697f 1512static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
1513 const u8 *mac, int *id_out)
afd4aea0 1514{
59cfc479
BH
1515 MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_SET_IN_LEN);
1516 MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_SET_OUT_LEN);
afd4aea0
BH
1517 size_t outlen;
1518 int rc;
1519
1520 MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
1521 MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
1522 MC_CMD_FILTER_MODE_SIMPLE);
1523 memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
1524
1525 rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
1526 outbuf, sizeof(outbuf), &outlen);
1527 if (rc)
1528 goto fail;
1529
1530 if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
00bbb4a5 1531 rc = -EIO;
afd4aea0
BH
1532 goto fail;
1533 }
1534
1535 *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
1536
1537 return 0;
1538
1539fail:
1540 *id_out = -1;
62776d03 1541 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH
1542 return rc;
1543
1544}
1545
1546
1547int
1548efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
1549{
1550 return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
1551}
1552
1553
1554int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
1555{
59cfc479 1556 MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_GET_OUT_LEN);
afd4aea0
BH
1557 size_t outlen;
1558 int rc;
1559
1560 rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
1561 outbuf, sizeof(outbuf), &outlen);
1562 if (rc)
1563 goto fail;
1564
1565 if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
00bbb4a5 1566 rc = -EIO;
afd4aea0
BH
1567 goto fail;
1568 }
1569
1570 *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
1571
1572 return 0;
1573
1574fail:
1575 *id_out = -1;
62776d03 1576 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH
1577 return rc;
1578}
1579
1580
1581int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
1582{
59cfc479 1583 MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_REMOVE_IN_LEN);
afd4aea0
BH
1584 int rc;
1585
1586 MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
1587
1588 rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
1589 NULL, 0, NULL);
afd4aea0
BH
1590 return rc;
1591}
1592
cd2d5b52
BH
1593int efx_mcdi_flush_rxqs(struct efx_nic *efx)
1594{
1595 struct efx_channel *channel;
1596 struct efx_rx_queue *rx_queue;
c5bb0e98
BH
1597 MCDI_DECLARE_BUF(inbuf,
1598 MC_CMD_FLUSH_RX_QUEUES_IN_LEN(EFX_MAX_CHANNELS));
cd2d5b52
BH
1599 int rc, count;
1600
45078374
BH
1601 BUILD_BUG_ON(EFX_MAX_CHANNELS >
1602 MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM);
1603
cd2d5b52
BH
1604 count = 0;
1605 efx_for_each_channel(channel, efx) {
1606 efx_for_each_channel_rx_queue(rx_queue, channel) {
1607 if (rx_queue->flush_pending) {
1608 rx_queue->flush_pending = false;
1609 atomic_dec(&efx->rxq_flush_pending);
c5bb0e98
BH
1610 MCDI_SET_ARRAY_DWORD(
1611 inbuf, FLUSH_RX_QUEUES_IN_QID_OFST,
1612 count, efx_rx_queue_index(rx_queue));
1613 count++;
cd2d5b52
BH
1614 }
1615 }
1616 }
1617
c5bb0e98
BH
1618 rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, inbuf,
1619 MC_CMD_FLUSH_RX_QUEUES_IN_LEN(count), NULL, 0, NULL);
bbec969b 1620 WARN_ON(rc < 0);
cd2d5b52 1621
cd2d5b52
BH
1622 return rc;
1623}
afd4aea0
BH
1624
1625int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
1626{
1627 int rc;
1628
1629 rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
afd4aea0
BH
1630 return rc;
1631}
1632
8127d661
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1633int efx_mcdi_set_workaround(struct efx_nic *efx, u32 type, bool enabled)
1634{
1635 MCDI_DECLARE_BUF(inbuf, MC_CMD_WORKAROUND_IN_LEN);
1636
1637 BUILD_BUG_ON(MC_CMD_WORKAROUND_OUT_LEN != 0);
1638 MCDI_SET_DWORD(inbuf, WORKAROUND_IN_TYPE, type);
1639 MCDI_SET_DWORD(inbuf, WORKAROUND_IN_ENABLED, enabled);
1640 return efx_mcdi_rpc(efx, MC_CMD_WORKAROUND, inbuf, sizeof(inbuf),
1641 NULL, 0, NULL);
1642}
1643
45a3fd55
BH
1644#ifdef CONFIG_SFC_MTD
1645
1646#define EFX_MCDI_NVRAM_LEN_MAX 128
1647
1648static int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
1649{
1650 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_START_IN_LEN);
1651 int rc;
1652
1653 MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
1654
1655 BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
1656
1657 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
1658 NULL, 0, NULL);
45a3fd55
BH
1659 return rc;
1660}
1661
1662static int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
1663 loff_t offset, u8 *buffer, size_t length)
1664{
1665 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_READ_IN_LEN);
1666 MCDI_DECLARE_BUF(outbuf,
1667 MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX));
1668 size_t outlen;
1669 int rc;
1670
1671 MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
1672 MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
1673 MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
1674
1675 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
1676 outbuf, sizeof(outbuf), &outlen);
1677 if (rc)
1e0b8120 1678 return rc;
45a3fd55
BH
1679
1680 memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
1681 return 0;
45a3fd55
BH
1682}
1683
1684static int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
1685 loff_t offset, const u8 *buffer, size_t length)
1686{
1687 MCDI_DECLARE_BUF(inbuf,
1688 MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX));
1689 int rc;
1690
1691 MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
1692 MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
1693 MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
1694 memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
1695
1696 BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
1697
1698 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
1699 ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
1700 NULL, 0, NULL);
45a3fd55
BH
1701 return rc;
1702}
1703
1704static int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
1705 loff_t offset, size_t length)
1706{
1707 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_ERASE_IN_LEN);
1708 int rc;
1709
1710 MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
1711 MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
1712 MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
1713
1714 BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
1715
1716 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
1717 NULL, 0, NULL);
45a3fd55
BH
1718 return rc;
1719}
1720
1721static int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
1722{
1723 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN);
1724 int rc;
1725
1726 MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
1727
1728 BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
1729
1730 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
1731 NULL, 0, NULL);
45a3fd55
BH
1732 return rc;
1733}
1734
1735int efx_mcdi_mtd_read(struct mtd_info *mtd, loff_t start,
1736 size_t len, size_t *retlen, u8 *buffer)
1737{
1738 struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd);
1739 struct efx_nic *efx = mtd->priv;
1740 loff_t offset = start;
1741 loff_t end = min_t(loff_t, start + len, mtd->size);
1742 size_t chunk;
1743 int rc = 0;
1744
1745 while (offset < end) {
1746 chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
1747 rc = efx_mcdi_nvram_read(efx, part->nvram_type, offset,
1748 buffer, chunk);
1749 if (rc)
1750 goto out;
1751 offset += chunk;
1752 buffer += chunk;
1753 }
1754out:
1755 *retlen = offset - start;
1756 return rc;
1757}
1758
1759int efx_mcdi_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
1760{
1761 struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd);
1762 struct efx_nic *efx = mtd->priv;
1763 loff_t offset = start & ~((loff_t)(mtd->erasesize - 1));
1764 loff_t end = min_t(loff_t, start + len, mtd->size);
1765 size_t chunk = part->common.mtd.erasesize;
1766 int rc = 0;
1767
1768 if (!part->updating) {
1769 rc = efx_mcdi_nvram_update_start(efx, part->nvram_type);
1770 if (rc)
1771 goto out;
1772 part->updating = true;
1773 }
1774
1775 /* The MCDI interface can in fact do multiple erase blocks at once;
1776 * but erasing may be slow, so we make multiple calls here to avoid
1777 * tripping the MCDI RPC timeout. */
1778 while (offset < end) {
1779 rc = efx_mcdi_nvram_erase(efx, part->nvram_type, offset,
1780 chunk);
1781 if (rc)
1782 goto out;
1783 offset += chunk;
1784 }
1785out:
1786 return rc;
1787}
1788
1789int efx_mcdi_mtd_write(struct mtd_info *mtd, loff_t start,
1790 size_t len, size_t *retlen, const u8 *buffer)
1791{
1792 struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd);
1793 struct efx_nic *efx = mtd->priv;
1794 loff_t offset = start;
1795 loff_t end = min_t(loff_t, start + len, mtd->size);
1796 size_t chunk;
1797 int rc = 0;
1798
1799 if (!part->updating) {
1800 rc = efx_mcdi_nvram_update_start(efx, part->nvram_type);
1801 if (rc)
1802 goto out;
1803 part->updating = true;
1804 }
1805
1806 while (offset < end) {
1807 chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
1808 rc = efx_mcdi_nvram_write(efx, part->nvram_type, offset,
1809 buffer, chunk);
1810 if (rc)
1811 goto out;
1812 offset += chunk;
1813 buffer += chunk;
1814 }
1815out:
1816 *retlen = offset - start;
1817 return rc;
1818}
1819
1820int efx_mcdi_mtd_sync(struct mtd_info *mtd)
1821{
1822 struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd);
1823 struct efx_nic *efx = mtd->priv;
1824 int rc = 0;
1825
1826 if (part->updating) {
1827 part->updating = false;
1828 rc = efx_mcdi_nvram_update_finish(efx, part->nvram_type);
1829 }
1830
1831 return rc;
1832}
1833
1834void efx_mcdi_mtd_rename(struct efx_mtd_partition *part)
1835{
1836 struct efx_mcdi_mtd_partition *mcdi_part =
1837 container_of(part, struct efx_mcdi_mtd_partition, common);
1838 struct efx_nic *efx = part->mtd.priv;
1839
1840 snprintf(part->name, sizeof(part->name), "%s %s:%02x",
1841 efx->name, part->type_name, mcdi_part->fw_subtype);
1842}
1843
1844#endif /* CONFIG_SFC_MTD */
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