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f0d37f42 | 1 | /**************************************************************************** |
f2b0befd BH |
2 | * Driver for Solarflare network controllers and boards |
3 | * Copyright 2009-2013 Solarflare Communications Inc. | |
f0d37f42 SH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | ||
11 | #ifndef MCDI_PCOL_H | |
12 | #define MCDI_PCOL_H | |
13 | ||
14 | /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ | |
15 | /* Power-on reset state */ | |
16 | #define MC_FW_STATE_POR (1) | |
17 | /* If this is set in MC_RESET_STATE_REG then it should be | |
18 | * possible to jump into IMEM without loading code from flash. */ | |
19 | #define MC_FW_WARM_BOOT_OK (2) | |
20 | /* The MC main image has started to boot. */ | |
21 | #define MC_FW_STATE_BOOTING (4) | |
22 | /* The Scheduler has started. */ | |
23 | #define MC_FW_STATE_SCHED (8) | |
f2b0befd BH |
24 | /* If this is set in MC_RESET_STATE_REG then it should be |
25 | * possible to jump into IMEM without loading code from flash. | |
26 | * Unlike a warm boot, assume DMEM has been reloaded, so that | |
27 | * the MC persistent data must be reinitialised. */ | |
28 | #define MC_FW_TEPID_BOOT_OK (16) | |
29 | /* BIST state has been initialized */ | |
30 | #define MC_FW_BIST_INIT_OK (128) | |
f0d37f42 | 31 | |
05a9320f BH |
32 | /* Siena MC shared memmory offsets */ |
33 | /* The 'doorbell' addresses are hard-wired to alert the MC when written */ | |
34 | #define MC_SMEM_P0_DOORBELL_OFST 0x000 | |
35 | #define MC_SMEM_P1_DOORBELL_OFST 0x004 | |
36 | /* The rest of these are firmware-defined */ | |
37 | #define MC_SMEM_P0_PDU_OFST 0x008 | |
38 | #define MC_SMEM_P1_PDU_OFST 0x108 | |
39 | #define MC_SMEM_PDU_LEN 0x100 | |
40 | #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 | |
41 | #define MC_SMEM_P0_STATUS_OFST 0x7f8 | |
42 | #define MC_SMEM_P1_STATUS_OFST 0x7fc | |
43 | ||
f0d37f42 SH |
44 | /* Values to be written to the per-port status dword in shared |
45 | * memory on reboot and assert */ | |
46 | #define MC_STATUS_DWORD_REBOOT (0xb007b007) | |
47 | #define MC_STATUS_DWORD_ASSERT (0xdeaddead) | |
48 | ||
f2b0befd BH |
49 | /* Check whether an mcfw version (in host order) belongs to a bootloader */ |
50 | #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) | |
51 | ||
f0d37f42 SH |
52 | /* The current version of the MCDI protocol. |
53 | * | |
54 | * Note that the ROM burnt into the card only talks V0, so at the very | |
55 | * least every driver must support version 0 and MCDI_PCOL_VERSION | |
56 | */ | |
f2b0befd | 57 | #define MCDI_PCOL_VERSION 2 |
f0d37f42 | 58 | |
05a9320f BH |
59 | /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ |
60 | ||
1aa8b471 | 61 | /* MCDI version 1 |
f0d37f42 | 62 | * |
f2b0befd | 63 | * Each MCDI request starts with an MCDI_HEADER, which is a 32bit |
f0d37f42 SH |
64 | * structure, filled in by the client. |
65 | * | |
66 | * 0 7 8 16 20 22 23 24 31 | |
67 | * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | | |
68 | * | | | | |
69 | * | | \--- Response | |
70 | * | \------- Error | |
71 | * \------------------------------ Resync (always set) | |
72 | * | |
73 | * The client writes it's request into MC shared memory, and rings the | |
74 | * doorbell. Each request is completed by either by the MC writting | |
75 | * back into shared memory, or by writting out an event. | |
76 | * | |
77 | * All MCDI commands support completion by shared memory response. Each | |
78 | * request may also contain additional data (accounted for by HEADER.LEN), | |
79 | * and some response's may also contain additional data (again, accounted | |
80 | * for by HEADER.LEN). | |
81 | * | |
82 | * Some MCDI commands support completion by event, in which any associated | |
83 | * response data is included in the event. | |
84 | * | |
85 | * The protocol requires one response to be delivered for every request, a | |
86 | * request should not be sent unless the response for the previous request | |
87 | * has been received (either by polling shared memory, or by receiving | |
88 | * an event). | |
89 | */ | |
90 | ||
91 | /** Request/Response structure */ | |
92 | #define MCDI_HEADER_OFST 0 | |
93 | #define MCDI_HEADER_CODE_LBN 0 | |
94 | #define MCDI_HEADER_CODE_WIDTH 7 | |
95 | #define MCDI_HEADER_RESYNC_LBN 7 | |
96 | #define MCDI_HEADER_RESYNC_WIDTH 1 | |
97 | #define MCDI_HEADER_DATALEN_LBN 8 | |
98 | #define MCDI_HEADER_DATALEN_WIDTH 8 | |
99 | #define MCDI_HEADER_SEQ_LBN 16 | |
f0d37f42 | 100 | #define MCDI_HEADER_SEQ_WIDTH 4 |
f2b0befd BH |
101 | #define MCDI_HEADER_RSVD_LBN 20 |
102 | #define MCDI_HEADER_RSVD_WIDTH 1 | |
103 | #define MCDI_HEADER_NOT_EPOCH_LBN 21 | |
104 | #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 | |
f0d37f42 SH |
105 | #define MCDI_HEADER_ERROR_LBN 22 |
106 | #define MCDI_HEADER_ERROR_WIDTH 1 | |
107 | #define MCDI_HEADER_RESPONSE_LBN 23 | |
108 | #define MCDI_HEADER_RESPONSE_WIDTH 1 | |
109 | #define MCDI_HEADER_XFLAGS_LBN 24 | |
110 | #define MCDI_HEADER_XFLAGS_WIDTH 8 | |
111 | /* Request response using event */ | |
112 | #define MCDI_HEADER_XFLAGS_EVREQ 0x01 | |
113 | ||
114 | /* Maximum number of payload bytes */ | |
d0c2ee99 | 115 | #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc |
f2b0befd BH |
116 | #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 |
117 | ||
118 | #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 | |
d0c2ee99 | 119 | |
f0d37f42 SH |
120 | |
121 | /* The MC can generate events for two reasons: | |
122 | * - To complete a shared memory request if XFLAGS_EVREQ was set | |
123 | * - As a notification (link state, i2c event), controlled | |
124 | * via MC_CMD_LOG_CTRL | |
125 | * | |
126 | * Both events share a common structure: | |
127 | * | |
128 | * 0 32 33 36 44 52 60 | |
129 | * | Data | Cont | Level | Src | Code | Rsvd | | |
130 | * | | |
131 | * \ There is another event pending in this notification | |
132 | * | |
133 | * If Code==CMDDONE, then the fields are further interpreted as: | |
134 | * | |
25985edc | 135 | * - LEVEL==INFO Command succeeded |
f0d37f42 SH |
136 | * - LEVEL==ERR Command failed |
137 | * | |
138 | * 0 8 16 24 32 | |
139 | * | Seq | Datalen | Errno | Rsvd | | |
140 | * | |
141 | * These fields are taken directly out of the standard MCDI header, i.e., | |
142 | * LEVEL==ERR, Datalen == 0 => Reboot | |
143 | * | |
144 | * Events can be squirted out of the UART (using LOG_CTRL) without a | |
145 | * MCDI header. An event can be distinguished from a MCDI response by | |
146 | * examining the first byte which is 0xc0. This corresponds to the | |
147 | * non-existent MCDI command MC_CMD_DEBUG_LOG. | |
148 | * | |
149 | * 0 7 8 | |
150 | * | command | Resync | = 0xc0 | |
151 | * | |
152 | * Since the event is written in big-endian byte order, this works | |
153 | * providing bits 56-63 of the event are 0xc0. | |
154 | * | |
155 | * 56 60 63 | |
156 | * | Rsvd | Code | = 0xc0 | |
157 | * | |
158 | * Which means for convenience the event code is 0xc for all MC | |
159 | * generated events. | |
160 | */ | |
161 | #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc | |
162 | ||
f0d37f42 | 163 | |
f2b0befd BH |
164 | /* Operation not permitted. */ |
165 | #define MC_CMD_ERR_EPERM 1 | |
f0d37f42 SH |
166 | /* Non-existent command target */ |
167 | #define MC_CMD_ERR_ENOENT 2 | |
168 | /* assert() has killed the MC */ | |
169 | #define MC_CMD_ERR_EINTR 4 | |
f2b0befd BH |
170 | /* I/O failure */ |
171 | #define MC_CMD_ERR_EIO 5 | |
172 | /* Try again */ | |
173 | #define MC_CMD_ERR_EAGAIN 11 | |
174 | /* Out of memory */ | |
175 | #define MC_CMD_ERR_ENOMEM 12 | |
f0d37f42 SH |
176 | /* Caller does not hold required locks */ |
177 | #define MC_CMD_ERR_EACCES 13 | |
178 | /* Resource is currently unavailable (e.g. lock contention) */ | |
179 | #define MC_CMD_ERR_EBUSY 16 | |
f2b0befd BH |
180 | /* No such device */ |
181 | #define MC_CMD_ERR_ENODEV 19 | |
f0d37f42 SH |
182 | /* Invalid argument to target */ |
183 | #define MC_CMD_ERR_EINVAL 22 | |
f2b0befd BH |
184 | /* Out of range */ |
185 | #define MC_CMD_ERR_ERANGE 34 | |
f0d37f42 SH |
186 | /* Non-recursive resource is already acquired */ |
187 | #define MC_CMD_ERR_EDEADLK 35 | |
188 | /* Operation not implemented */ | |
189 | #define MC_CMD_ERR_ENOSYS 38 | |
190 | /* Operation timed out */ | |
191 | #define MC_CMD_ERR_ETIME 62 | |
f2b0befd BH |
192 | /* Link has been severed */ |
193 | #define MC_CMD_ERR_ENOLINK 67 | |
194 | /* Protocol error */ | |
195 | #define MC_CMD_ERR_EPROTO 71 | |
196 | /* Operation not supported */ | |
197 | #define MC_CMD_ERR_ENOTSUP 95 | |
198 | /* Address not available */ | |
199 | #define MC_CMD_ERR_EADDRNOTAVAIL 99 | |
200 | /* Not connected */ | |
201 | #define MC_CMD_ERR_ENOTCONN 107 | |
202 | /* Operation already in progress */ | |
203 | #define MC_CMD_ERR_EALREADY 114 | |
204 | ||
205 | /* Resource allocation failed. */ | |
206 | #define MC_CMD_ERR_ALLOC_FAIL 0x1000 | |
207 | /* V-adaptor not found. */ | |
208 | #define MC_CMD_ERR_NO_VADAPTOR 0x1001 | |
209 | /* EVB port not found. */ | |
210 | #define MC_CMD_ERR_NO_EVB_PORT 0x1002 | |
211 | /* V-switch not found. */ | |
212 | #define MC_CMD_ERR_NO_VSWITCH 0x1003 | |
213 | /* Too many VLAN tags. */ | |
214 | #define MC_CMD_ERR_VLAN_LIMIT 0x1004 | |
215 | /* Bad PCI function number. */ | |
216 | #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 | |
217 | /* Invalid VLAN mode. */ | |
218 | #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 | |
219 | /* Invalid v-switch type. */ | |
220 | #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 | |
221 | /* Invalid v-port type. */ | |
222 | #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 | |
223 | /* MAC address exists. */ | |
224 | #define MC_CMD_ERR_MAC_EXIST 0x1009 | |
225 | /* Slave core not present */ | |
226 | #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a | |
512bb06c BH |
227 | /* The datapath is disabled. */ |
228 | #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b | |
f0d37f42 SH |
229 | |
230 | #define MC_CMD_ERR_CODE_OFST 0 | |
231 | ||
05a9320f BH |
232 | /* We define 8 "escape" commands to allow |
233 | for command number space extension */ | |
234 | ||
235 | #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 | |
236 | #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 | |
237 | #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A | |
238 | #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B | |
239 | #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C | |
240 | #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D | |
241 | #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E | |
242 | #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F | |
243 | ||
244 | /* Vectors in the boot ROM */ | |
245 | /* Point to the copycode entry point. */ | |
f2b0befd BH |
246 | #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) |
247 | #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) | |
05a9320f | 248 | /* Points to the recovery mode entry point. */ |
f2b0befd BH |
249 | #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) |
250 | #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) | |
f0d37f42 | 251 | |
f0d37f42 SH |
252 | /* The command set exported by the boot ROM (MCDI v0) */ |
253 | #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ | |
254 | (1 << MC_CMD_READ32) | \ | |
255 | (1 << MC_CMD_WRITE32) | \ | |
256 | (1 << MC_CMD_COPYCODE) | \ | |
257 | (1 << MC_CMD_GET_VERSION), \ | |
258 | 0, 0, 0 } | |
f0d37f42 | 259 | |
05a9320f BH |
260 | #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ |
261 | (MC_CMD_SENSOR_ENTRY_OFST + (_x)) | |
262 | ||
263 | #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ | |
264 | (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ | |
265 | MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ | |
266 | (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) | |
267 | ||
268 | #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ | |
269 | (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ | |
270 | MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ | |
271 | (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) | |
272 | ||
273 | #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ | |
274 | (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ | |
275 | MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ | |
276 | (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) | |
277 | ||
278 | ||
f2b0befd BH |
279 | /* Version 2 adds an optional argument to error returns: the errno value |
280 | * may be followed by the (0-based) number of the first argument that | |
281 | * could not be processed. | |
282 | */ | |
283 | #define MC_CMD_ERR_ARG_OFST 4 | |
284 | ||
285 | /* No space */ | |
286 | #define MC_CMD_ERR_ENOSPC 28 | |
287 | ||
05a9320f BH |
288 | /* MCDI_EVENT structuredef */ |
289 | #define MCDI_EVENT_LEN 8 | |
290 | #define MCDI_EVENT_CONT_LBN 32 | |
291 | #define MCDI_EVENT_CONT_WIDTH 1 | |
292 | #define MCDI_EVENT_LEVEL_LBN 33 | |
293 | #define MCDI_EVENT_LEVEL_WIDTH 3 | |
f2b0befd BH |
294 | /* enum: Info. */ |
295 | #define MCDI_EVENT_LEVEL_INFO 0x0 | |
296 | /* enum: Warning. */ | |
297 | #define MCDI_EVENT_LEVEL_WARN 0x1 | |
298 | /* enum: Error. */ | |
299 | #define MCDI_EVENT_LEVEL_ERR 0x2 | |
300 | /* enum: Fatal. */ | |
301 | #define MCDI_EVENT_LEVEL_FATAL 0x3 | |
05a9320f BH |
302 | #define MCDI_EVENT_DATA_OFST 0 |
303 | #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 | |
304 | #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 | |
305 | #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 | |
306 | #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 | |
307 | #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 | |
308 | #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 | |
309 | #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 | |
310 | #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 | |
311 | #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 | |
312 | #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 | |
f2b0befd BH |
313 | /* enum: 100Mbs */ |
314 | #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 | |
315 | /* enum: 1Gbs */ | |
316 | #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 | |
317 | /* enum: 10Gbs */ | |
318 | #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 | |
319 | /* enum: 40Gbs */ | |
320 | #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 | |
05a9320f BH |
321 | #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 |
322 | #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 | |
323 | #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 | |
324 | #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 | |
325 | #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 | |
326 | #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 | |
327 | #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 | |
328 | #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 | |
329 | #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 | |
330 | #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 | |
331 | #define MCDI_EVENT_FWALERT_DATA_LBN 8 | |
332 | #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 | |
333 | #define MCDI_EVENT_FWALERT_REASON_LBN 0 | |
334 | #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 | |
f2b0befd BH |
335 | /* enum: SRAM Access. */ |
336 | #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 | |
05a9320f BH |
337 | #define MCDI_EVENT_FLR_VF_LBN 0 |
338 | #define MCDI_EVENT_FLR_VF_WIDTH 8 | |
339 | #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 | |
340 | #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 | |
341 | #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 | |
342 | #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 | |
f2b0befd BH |
343 | /* enum: Descriptor loader reported failure */ |
344 | #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 | |
345 | /* enum: Descriptor ring empty and no EOP seen for packet */ | |
346 | #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 | |
347 | /* enum: Overlength packet */ | |
348 | #define MCDI_EVENT_TX_ERR_2BIG 0x3 | |
349 | /* enum: Malformed option descriptor */ | |
350 | #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 | |
351 | /* enum: Option descriptor part way through a packet */ | |
352 | #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 | |
353 | /* enum: DMA or PIO data access error */ | |
354 | #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 | |
05a9320f BH |
355 | #define MCDI_EVENT_TX_ERR_INFO_LBN 16 |
356 | #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 | |
f2b0befd BH |
357 | #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 |
358 | #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 | |
05a9320f BH |
359 | #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 |
360 | #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 | |
361 | #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 | |
362 | #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 | |
f2b0befd BH |
363 | /* enum: PLL lost lock */ |
364 | #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 | |
365 | /* enum: Filter overflow (PDMA) */ | |
366 | #define MCDI_EVENT_PTP_ERR_FILTER 0x2 | |
367 | /* enum: FIFO overflow (FPGA) */ | |
368 | #define MCDI_EVENT_PTP_ERR_FIFO 0x3 | |
369 | /* enum: Merge queue overflow */ | |
370 | #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 | |
371 | #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 | |
372 | #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 | |
373 | /* enum: AOE failed to load - no valid image? */ | |
374 | #define MCDI_EVENT_AOE_NO_LOAD 0x1 | |
375 | /* enum: AOE FC reported an exception */ | |
376 | #define MCDI_EVENT_AOE_FC_ASSERT 0x2 | |
377 | /* enum: AOE FC watchdogged */ | |
378 | #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 | |
379 | /* enum: AOE FC failed to start */ | |
380 | #define MCDI_EVENT_AOE_FC_NO_START 0x4 | |
381 | /* enum: Generic AOE fault - likely to have been reported via other means too | |
382 | * but intended for use by aoex driver. | |
383 | */ | |
384 | #define MCDI_EVENT_AOE_FAULT 0x5 | |
385 | /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ | |
386 | #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 | |
387 | /* enum: AOE loaded successfully */ | |
388 | #define MCDI_EVENT_AOE_LOAD 0x7 | |
389 | /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ | |
390 | #define MCDI_EVENT_AOE_DMA 0x8 | |
391 | /* enum: AOE byteblaster connected/disconnected (Connection status in | |
392 | * AOE_ERR_DATA) | |
393 | */ | |
394 | #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 | |
512bb06c BH |
395 | /* enum: DDR ECC status update */ |
396 | #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa | |
f2b0befd BH |
397 | #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 |
398 | #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 | |
399 | #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 | |
400 | #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 | |
401 | #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 | |
402 | #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 | |
403 | #define MCDI_EVENT_RX_ERR_INFO_LBN 16 | |
404 | #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 | |
405 | #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 | |
406 | #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 | |
407 | #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 | |
408 | #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 | |
409 | #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 | |
410 | #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 | |
05a9320f BH |
411 | #define MCDI_EVENT_DATA_LBN 0 |
412 | #define MCDI_EVENT_DATA_WIDTH 32 | |
413 | #define MCDI_EVENT_SRC_LBN 36 | |
414 | #define MCDI_EVENT_SRC_WIDTH 8 | |
415 | #define MCDI_EVENT_EV_CODE_LBN 60 | |
416 | #define MCDI_EVENT_EV_CODE_WIDTH 4 | |
417 | #define MCDI_EVENT_CODE_LBN 44 | |
418 | #define MCDI_EVENT_CODE_WIDTH 8 | |
f2b0befd BH |
419 | /* enum: Bad assert. */ |
420 | #define MCDI_EVENT_CODE_BADSSERT 0x1 | |
421 | /* enum: PM Notice. */ | |
422 | #define MCDI_EVENT_CODE_PMNOTICE 0x2 | |
423 | /* enum: Command done. */ | |
424 | #define MCDI_EVENT_CODE_CMDDONE 0x3 | |
425 | /* enum: Link change. */ | |
426 | #define MCDI_EVENT_CODE_LINKCHANGE 0x4 | |
427 | /* enum: Sensor Event. */ | |
428 | #define MCDI_EVENT_CODE_SENSOREVT 0x5 | |
429 | /* enum: Schedule error. */ | |
430 | #define MCDI_EVENT_CODE_SCHEDERR 0x6 | |
431 | /* enum: Reboot. */ | |
432 | #define MCDI_EVENT_CODE_REBOOT 0x7 | |
433 | /* enum: Mac stats DMA. */ | |
434 | #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 | |
435 | /* enum: Firmware alert. */ | |
436 | #define MCDI_EVENT_CODE_FWALERT 0x9 | |
437 | /* enum: Function level reset. */ | |
438 | #define MCDI_EVENT_CODE_FLR 0xa | |
439 | /* enum: Transmit error */ | |
440 | #define MCDI_EVENT_CODE_TX_ERR 0xb | |
441 | /* enum: Tx flush has completed */ | |
442 | #define MCDI_EVENT_CODE_TX_FLUSH 0xc | |
443 | /* enum: PTP packet received timestamp */ | |
444 | #define MCDI_EVENT_CODE_PTP_RX 0xd | |
445 | /* enum: PTP NIC failure */ | |
446 | #define MCDI_EVENT_CODE_PTP_FAULT 0xe | |
447 | /* enum: PTP PPS event */ | |
448 | #define MCDI_EVENT_CODE_PTP_PPS 0xf | |
449 | /* enum: Rx flush has completed */ | |
450 | #define MCDI_EVENT_CODE_RX_FLUSH 0x10 | |
451 | /* enum: Receive error */ | |
452 | #define MCDI_EVENT_CODE_RX_ERR 0x11 | |
453 | /* enum: AOE fault */ | |
454 | #define MCDI_EVENT_CODE_AOE 0x12 | |
455 | /* enum: Network port calibration failed (VCAL). */ | |
456 | #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 | |
457 | /* enum: HW PPS event */ | |
458 | #define MCDI_EVENT_CODE_HW_PPS 0x14 | |
459 | /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and | |
460 | * a different format) | |
461 | */ | |
462 | #define MCDI_EVENT_CODE_MC_REBOOT 0x15 | |
463 | /* enum: the MC has detected a parity error */ | |
464 | #define MCDI_EVENT_CODE_PAR_ERR 0x16 | |
465 | /* enum: the MC has detected a correctable error */ | |
466 | #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 | |
467 | /* enum: the MC has detected an uncorrectable error */ | |
468 | #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 | |
512bb06c BH |
469 | /* enum: The MC has entered offline BIST mode */ |
470 | #define MCDI_EVENT_CODE_MC_BIST 0x19 | |
471 | /* enum: PTP tick event providing current NIC time */ | |
472 | #define MCDI_EVENT_CODE_PTP_TIME 0x1a | |
f2b0befd BH |
473 | /* enum: Artificial event generated by host and posted via MC for test |
474 | * purposes. | |
475 | */ | |
476 | #define MCDI_EVENT_CODE_TESTGEN 0xfa | |
05a9320f BH |
477 | #define MCDI_EVENT_CMDDONE_DATA_OFST 0 |
478 | #define MCDI_EVENT_CMDDONE_DATA_LBN 0 | |
479 | #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 | |
480 | #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 | |
481 | #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 | |
482 | #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 | |
483 | #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 | |
484 | #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 | |
485 | #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 | |
486 | #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 | |
487 | #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 | |
488 | #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 | |
489 | #define MCDI_EVENT_TX_ERR_DATA_OFST 0 | |
490 | #define MCDI_EVENT_TX_ERR_DATA_LBN 0 | |
491 | #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 | |
512bb06c BH |
492 | /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of |
493 | * timestamp | |
494 | */ | |
05a9320f BH |
495 | #define MCDI_EVENT_PTP_SECONDS_OFST 0 |
496 | #define MCDI_EVENT_PTP_SECONDS_LBN 0 | |
497 | #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 | |
512bb06c BH |
498 | /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of |
499 | * timestamp | |
500 | */ | |
501 | #define MCDI_EVENT_PTP_MAJOR_OFST 0 | |
502 | #define MCDI_EVENT_PTP_MAJOR_LBN 0 | |
503 | #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 | |
504 | /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field | |
505 | * of timestamp | |
506 | */ | |
05a9320f BH |
507 | #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 |
508 | #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 | |
509 | #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 | |
512bb06c BH |
510 | /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of |
511 | * timestamp | |
512 | */ | |
513 | #define MCDI_EVENT_PTP_MINOR_OFST 0 | |
514 | #define MCDI_EVENT_PTP_MINOR_LBN 0 | |
515 | #define MCDI_EVENT_PTP_MINOR_WIDTH 32 | |
516 | /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet | |
517 | */ | |
05a9320f BH |
518 | #define MCDI_EVENT_PTP_UUID_OFST 0 |
519 | #define MCDI_EVENT_PTP_UUID_LBN 0 | |
520 | #define MCDI_EVENT_PTP_UUID_WIDTH 32 | |
f2b0befd BH |
521 | #define MCDI_EVENT_RX_ERR_DATA_OFST 0 |
522 | #define MCDI_EVENT_RX_ERR_DATA_LBN 0 | |
523 | #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 | |
524 | #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 | |
525 | #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 | |
526 | #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 | |
527 | #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 | |
528 | #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 | |
529 | #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 | |
530 | #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 | |
531 | #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 | |
532 | #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 | |
512bb06c BH |
533 | /* For CODE_PTP_TIME events, the major value of the PTP clock */ |
534 | #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 | |
535 | #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 | |
536 | #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 | |
537 | /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ | |
538 | #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 | |
539 | #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 | |
f2b0befd BH |
540 | |
541 | /* FCDI_EVENT structuredef */ | |
542 | #define FCDI_EVENT_LEN 8 | |
543 | #define FCDI_EVENT_CONT_LBN 32 | |
544 | #define FCDI_EVENT_CONT_WIDTH 1 | |
545 | #define FCDI_EVENT_LEVEL_LBN 33 | |
546 | #define FCDI_EVENT_LEVEL_WIDTH 3 | |
547 | /* enum: Info. */ | |
548 | #define FCDI_EVENT_LEVEL_INFO 0x0 | |
549 | /* enum: Warning. */ | |
550 | #define FCDI_EVENT_LEVEL_WARN 0x1 | |
551 | /* enum: Error. */ | |
552 | #define FCDI_EVENT_LEVEL_ERR 0x2 | |
553 | /* enum: Fatal. */ | |
554 | #define FCDI_EVENT_LEVEL_FATAL 0x3 | |
555 | #define FCDI_EVENT_DATA_OFST 0 | |
556 | #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 | |
557 | #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 | |
558 | #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ | |
559 | #define FCDI_EVENT_LINK_UP 0x1 /* enum */ | |
560 | #define FCDI_EVENT_DATA_LBN 0 | |
561 | #define FCDI_EVENT_DATA_WIDTH 32 | |
562 | #define FCDI_EVENT_SRC_LBN 36 | |
563 | #define FCDI_EVENT_SRC_WIDTH 8 | |
564 | #define FCDI_EVENT_EV_CODE_LBN 60 | |
565 | #define FCDI_EVENT_EV_CODE_WIDTH 4 | |
566 | #define FCDI_EVENT_CODE_LBN 44 | |
567 | #define FCDI_EVENT_CODE_WIDTH 8 | |
568 | /* enum: The FC was rebooted. */ | |
569 | #define FCDI_EVENT_CODE_REBOOT 0x1 | |
570 | /* enum: Bad assert. */ | |
571 | #define FCDI_EVENT_CODE_ASSERT 0x2 | |
572 | /* enum: DDR3 test result. */ | |
573 | #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 | |
574 | /* enum: Link status. */ | |
575 | #define FCDI_EVENT_CODE_LINK_STATE 0x4 | |
576 | /* enum: A timed read is ready to be serviced. */ | |
577 | #define FCDI_EVENT_CODE_TIMED_READ 0x5 | |
578 | /* enum: One or more PPS IN events */ | |
579 | #define FCDI_EVENT_CODE_PPS_IN 0x6 | |
512bb06c BH |
580 | /* enum: Tick event from PTP clock */ |
581 | #define FCDI_EVENT_CODE_PTP_TICK 0x7 | |
582 | /* enum: ECC error counters */ | |
583 | #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 | |
f2b0befd BH |
584 | #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 |
585 | #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 | |
586 | #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 | |
587 | #define FCDI_EVENT_ASSERT_TYPE_LBN 36 | |
588 | #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 | |
589 | #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 | |
590 | #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 | |
591 | #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 | |
592 | #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 | |
593 | #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 | |
594 | #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 | |
595 | #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 | |
596 | #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 | |
512bb06c BH |
597 | #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 |
598 | #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 | |
599 | #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 | |
600 | #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 | |
601 | #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 | |
602 | ||
603 | /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events | |
604 | * to the MC. Note that this structure | is overlayed over a normal FCDI event | |
605 | * such that bits 32-63 containing | event code, level, source etc remain the | |
606 | * same. In this case the data | field of the header is defined to be the | |
607 | * number of timestamps | |
608 | */ | |
609 | #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 | |
610 | #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 | |
611 | #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) | |
f2b0befd BH |
612 | /* Number of timestamps following */ |
613 | #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 | |
614 | #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 | |
615 | #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 | |
616 | /* Seconds field of a timestamp record */ | |
617 | #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 | |
618 | #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 | |
619 | #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 | |
620 | /* Nanoseconds field of a timestamp record */ | |
621 | #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 | |
622 | #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 | |
623 | #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 | |
624 | /* Timestamp records comprising the event */ | |
512bb06c BH |
625 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 |
626 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 | |
627 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 | |
628 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 | |
629 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 | |
630 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 | |
631 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 | |
632 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 | |
05a9320f BH |
633 | |
634 | ||
635 | /***********************************/ | |
636 | /* MC_CMD_READ32 | |
637 | * Read multiple 32byte words from MC memory. | |
638 | */ | |
639 | #define MC_CMD_READ32 0x1 | |
640 | ||
75122ec8 SS |
641 | #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
642 | ||
05a9320f BH |
643 | /* MC_CMD_READ32_IN msgrequest */ |
644 | #define MC_CMD_READ32_IN_LEN 8 | |
645 | #define MC_CMD_READ32_IN_ADDR_OFST 0 | |
646 | #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 | |
647 | ||
648 | /* MC_CMD_READ32_OUT msgresponse */ | |
649 | #define MC_CMD_READ32_OUT_LENMIN 4 | |
650 | #define MC_CMD_READ32_OUT_LENMAX 252 | |
651 | #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) | |
652 | #define MC_CMD_READ32_OUT_BUFFER_OFST 0 | |
653 | #define MC_CMD_READ32_OUT_BUFFER_LEN 4 | |
654 | #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 | |
655 | #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 | |
656 | ||
657 | ||
658 | /***********************************/ | |
659 | /* MC_CMD_WRITE32 | |
660 | * Write multiple 32byte words to MC memory. | |
661 | */ | |
662 | #define MC_CMD_WRITE32 0x2 | |
663 | ||
75122ec8 SS |
664 | #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
665 | ||
05a9320f BH |
666 | /* MC_CMD_WRITE32_IN msgrequest */ |
667 | #define MC_CMD_WRITE32_IN_LENMIN 8 | |
668 | #define MC_CMD_WRITE32_IN_LENMAX 252 | |
669 | #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) | |
670 | #define MC_CMD_WRITE32_IN_ADDR_OFST 0 | |
671 | #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 | |
672 | #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 | |
673 | #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 | |
674 | #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 | |
675 | ||
676 | /* MC_CMD_WRITE32_OUT msgresponse */ | |
677 | #define MC_CMD_WRITE32_OUT_LEN 0 | |
678 | ||
679 | ||
680 | /***********************************/ | |
681 | /* MC_CMD_COPYCODE | |
682 | * Copy MC code between two locations and jump. | |
683 | */ | |
684 | #define MC_CMD_COPYCODE 0x3 | |
685 | ||
75122ec8 SS |
686 | #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
687 | ||
05a9320f BH |
688 | /* MC_CMD_COPYCODE_IN msgrequest */ |
689 | #define MC_CMD_COPYCODE_IN_LEN 16 | |
f2b0befd | 690 | /* Source address */ |
05a9320f | 691 | #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 |
512bb06c BH |
692 | /* enum: The main image should be entered via a copy of a single word from and |
693 | * to this address when none of the other magic behaviours are required. | |
694 | */ | |
695 | #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 | |
f2b0befd BH |
696 | /* enum: Entering the main image via a copy of a single word from and to this |
697 | * address indicates that it should not attempt to start the datapath CPUs. | |
698 | * This is useful for certain soft rebooting scenarios. (Huntington only) | |
699 | */ | |
700 | #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 | |
701 | /* enum: Entering the main image via a copy of a single word from and to this | |
702 | * address indicates that it should not attempt to parse any configuration from | |
703 | * flash. (In addition, the datapath CPUs will not be started, as for | |
704 | * MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR above.) This is useful for | |
705 | * certain soft rebooting scenarios. (Huntington only) | |
706 | */ | |
707 | #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc | |
708 | /* Destination address */ | |
05a9320f BH |
709 | #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 |
710 | #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 | |
f2b0befd | 711 | /* Address of where to jump after copy. */ |
05a9320f | 712 | #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 |
f2b0befd BH |
713 | /* enum: Control should return to the caller rather than jumping */ |
714 | #define MC_CMD_COPYCODE_JUMP_NONE 0x1 | |
05a9320f BH |
715 | |
716 | /* MC_CMD_COPYCODE_OUT msgresponse */ | |
717 | #define MC_CMD_COPYCODE_OUT_LEN 0 | |
718 | ||
719 | ||
720 | /***********************************/ | |
721 | /* MC_CMD_SET_FUNC | |
f2b0befd | 722 | * Select function for function-specific commands. |
05a9320f BH |
723 | */ |
724 | #define MC_CMD_SET_FUNC 0x4 | |
725 | ||
75122ec8 SS |
726 | #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
727 | ||
05a9320f BH |
728 | /* MC_CMD_SET_FUNC_IN msgrequest */ |
729 | #define MC_CMD_SET_FUNC_IN_LEN 4 | |
f2b0befd | 730 | /* Set function */ |
05a9320f BH |
731 | #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 |
732 | ||
733 | /* MC_CMD_SET_FUNC_OUT msgresponse */ | |
734 | #define MC_CMD_SET_FUNC_OUT_LEN 0 | |
735 | ||
736 | ||
737 | /***********************************/ | |
738 | /* MC_CMD_GET_BOOT_STATUS | |
f2b0befd | 739 | * Get the instruction address from which the MC booted. |
05a9320f BH |
740 | */ |
741 | #define MC_CMD_GET_BOOT_STATUS 0x5 | |
742 | ||
75122ec8 SS |
743 | #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
744 | ||
05a9320f BH |
745 | /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ |
746 | #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 | |
747 | ||
748 | /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ | |
749 | #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 | |
f2b0befd | 750 | /* ?? */ |
05a9320f | 751 | #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 |
f2b0befd BH |
752 | /* enum: indicates that the MC wasn't flash booted */ |
753 | #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef | |
05a9320f BH |
754 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 |
755 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 | |
756 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 | |
757 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 | |
758 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 | |
759 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 | |
760 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 | |
f0d37f42 | 761 | |
f0d37f42 | 762 | |
05a9320f BH |
763 | /***********************************/ |
764 | /* MC_CMD_GET_ASSERTS | |
f2b0befd BH |
765 | * Get (and optionally clear) the current assertion status. Only |
766 | * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other | |
767 | * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS | |
f0d37f42 | 768 | */ |
05a9320f | 769 | #define MC_CMD_GET_ASSERTS 0x6 |
f0d37f42 | 770 | |
75122ec8 SS |
771 | #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
772 | ||
05a9320f BH |
773 | /* MC_CMD_GET_ASSERTS_IN msgrequest */ |
774 | #define MC_CMD_GET_ASSERTS_IN_LEN 4 | |
f2b0befd | 775 | /* Set to clear assertion */ |
05a9320f BH |
776 | #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 |
777 | ||
778 | /* MC_CMD_GET_ASSERTS_OUT msgresponse */ | |
779 | #define MC_CMD_GET_ASSERTS_OUT_LEN 140 | |
f2b0befd | 780 | /* Assertion status flag. */ |
05a9320f | 781 | #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 |
f2b0befd BH |
782 | /* enum: No assertions have failed. */ |
783 | #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 | |
784 | /* enum: A system-level assertion has failed. */ | |
785 | #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 | |
786 | /* enum: A thread-level assertion has failed. */ | |
787 | #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 | |
788 | /* enum: The system was reset by the watchdog. */ | |
789 | #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 | |
790 | /* enum: An illegal address trap stopped the system (huntington and later) */ | |
791 | #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 | |
792 | /* Failing PC value */ | |
05a9320f | 793 | #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 |
f2b0befd | 794 | /* Saved GP regs */ |
05a9320f BH |
795 | #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 |
796 | #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 | |
797 | #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 | |
f2b0befd | 798 | /* Failing thread address */ |
05a9320f BH |
799 | #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 |
800 | #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 | |
f0d37f42 | 801 | |
05a9320f BH |
802 | |
803 | /***********************************/ | |
804 | /* MC_CMD_LOG_CTRL | |
805 | * Configure the output stream for various events and messages. | |
806 | */ | |
807 | #define MC_CMD_LOG_CTRL 0x7 | |
808 | ||
75122ec8 SS |
809 | #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
810 | ||
05a9320f BH |
811 | /* MC_CMD_LOG_CTRL_IN msgrequest */ |
812 | #define MC_CMD_LOG_CTRL_IN_LEN 8 | |
f2b0befd | 813 | /* Log destination */ |
05a9320f | 814 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 |
f2b0befd BH |
815 | /* enum: UART. */ |
816 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 | |
817 | /* enum: Event queue. */ | |
818 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 | |
05a9320f BH |
819 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 |
820 | ||
821 | /* MC_CMD_LOG_CTRL_OUT msgresponse */ | |
822 | #define MC_CMD_LOG_CTRL_OUT_LEN 0 | |
823 | ||
824 | ||
825 | /***********************************/ | |
826 | /* MC_CMD_GET_VERSION | |
827 | * Get version information about the MC firmware. | |
828 | */ | |
829 | #define MC_CMD_GET_VERSION 0x8 | |
830 | ||
75122ec8 SS |
831 | #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
832 | ||
05a9320f BH |
833 | /* MC_CMD_GET_VERSION_IN msgrequest */ |
834 | #define MC_CMD_GET_VERSION_IN_LEN 0 | |
835 | ||
f2b0befd BH |
836 | /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ |
837 | #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 | |
838 | /* placeholder, set to 0 */ | |
839 | #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 | |
840 | ||
841 | /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ | |
05a9320f BH |
842 | #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 |
843 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 | |
f2b0befd BH |
844 | /* enum: Reserved version number to indicate "any" version. */ |
845 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff | |
846 | /* enum: Bootrom version value for Siena. */ | |
847 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 | |
848 | /* enum: Bootrom version value for Huntington. */ | |
849 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 | |
05a9320f BH |
850 | |
851 | /* MC_CMD_GET_VERSION_OUT msgresponse */ | |
852 | #define MC_CMD_GET_VERSION_OUT_LEN 32 | |
853 | /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ | |
854 | /* Enum values, see field(s): */ | |
855 | /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ | |
856 | #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 | |
f2b0befd | 857 | /* 128bit mask of functions supported by the current firmware */ |
05a9320f BH |
858 | #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 |
859 | #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 | |
860 | #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 | |
861 | #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 | |
862 | #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 | |
863 | #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 | |
864 | ||
f2b0befd BH |
865 | /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ |
866 | #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 | |
867 | /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ | |
868 | /* Enum values, see field(s): */ | |
869 | /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ | |
870 | #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 | |
871 | /* 128bit mask of functions supported by the current firmware */ | |
872 | #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 | |
873 | #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 | |
874 | #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 | |
875 | #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 | |
876 | #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 | |
877 | #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 | |
878 | /* extra info */ | |
879 | #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 | |
880 | #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 | |
05a9320f BH |
881 | |
882 | ||
883 | /***********************************/ | |
884 | /* MC_CMD_PTP | |
885 | * Perform PTP operation | |
886 | */ | |
887 | #define MC_CMD_PTP 0xb | |
888 | ||
75122ec8 SS |
889 | #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
890 | ||
05a9320f BH |
891 | /* MC_CMD_PTP_IN msgrequest */ |
892 | #define MC_CMD_PTP_IN_LEN 1 | |
f2b0befd | 893 | /* PTP operation code */ |
05a9320f BH |
894 | #define MC_CMD_PTP_IN_OP_OFST 0 |
895 | #define MC_CMD_PTP_IN_OP_LEN 1 | |
f2b0befd BH |
896 | /* enum: Enable PTP packet timestamping operation. */ |
897 | #define MC_CMD_PTP_OP_ENABLE 0x1 | |
898 | /* enum: Disable PTP packet timestamping operation. */ | |
899 | #define MC_CMD_PTP_OP_DISABLE 0x2 | |
900 | /* enum: Send a PTP packet. */ | |
901 | #define MC_CMD_PTP_OP_TRANSMIT 0x3 | |
902 | /* enum: Read the current NIC time. */ | |
903 | #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 | |
904 | /* enum: Get the current PTP status. */ | |
905 | #define MC_CMD_PTP_OP_STATUS 0x5 | |
906 | /* enum: Adjust the PTP NIC's time. */ | |
907 | #define MC_CMD_PTP_OP_ADJUST 0x6 | |
908 | /* enum: Synchronize host and NIC time. */ | |
909 | #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 | |
910 | /* enum: Basic manufacturing tests. */ | |
911 | #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 | |
912 | /* enum: Packet based manufacturing tests. */ | |
913 | #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 | |
914 | /* enum: Reset some of the PTP related statistics */ | |
915 | #define MC_CMD_PTP_OP_RESET_STATS 0xa | |
916 | /* enum: Debug operations to MC. */ | |
917 | #define MC_CMD_PTP_OP_DEBUG 0xb | |
918 | /* enum: Read an FPGA register */ | |
919 | #define MC_CMD_PTP_OP_FPGAREAD 0xc | |
920 | /* enum: Write an FPGA register */ | |
921 | #define MC_CMD_PTP_OP_FPGAWRITE 0xd | |
922 | /* enum: Apply an offset to the NIC clock */ | |
923 | #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe | |
924 | /* enum: Change Apply an offset to the NIC clock */ | |
925 | #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf | |
926 | /* enum: Set the MC packet filter VLAN tags for received PTP packets */ | |
927 | #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 | |
928 | /* enum: Set the MC packet filter UUID for received PTP packets */ | |
929 | #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 | |
930 | /* enum: Set the MC packet filter Domain for received PTP packets */ | |
931 | #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 | |
932 | /* enum: Set the clock source */ | |
933 | #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 | |
934 | /* enum: Reset value of Timer Reg. */ | |
935 | #define MC_CMD_PTP_OP_RST_CLK 0x14 | |
936 | /* enum: Enable the forwarding of PPS events to the host */ | |
937 | #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 | |
512bb06c BH |
938 | /* enum: Get the time format used by this NIC for PTP operations */ |
939 | #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 | |
940 | /* enum: Get the clock attributes. NOTE- extended version of | |
941 | * MC_CMD_PTP_OP_GET_TIME_FORMAT | |
942 | */ | |
943 | #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 | |
944 | /* enum: Get corrections that should be applied to the various different | |
945 | * timestamps | |
946 | */ | |
947 | #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 | |
948 | /* enum: Subscribe to receive periodic time events indicating the current NIC | |
949 | * time | |
950 | */ | |
951 | #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 | |
952 | /* enum: Unsubscribe to stop receiving time events */ | |
953 | #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 | |
954 | /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS | |
955 | * input on the same NIC. | |
956 | */ | |
957 | #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a | |
f2b0befd | 958 | /* enum: Above this for future use. */ |
512bb06c | 959 | #define MC_CMD_PTP_OP_MAX 0x1b |
05a9320f BH |
960 | |
961 | /* MC_CMD_PTP_IN_ENABLE msgrequest */ | |
962 | #define MC_CMD_PTP_IN_ENABLE_LEN 16 | |
963 | #define MC_CMD_PTP_IN_CMD_OFST 0 | |
964 | #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 | |
f2b0befd | 965 | /* Event queue for PTP events */ |
05a9320f | 966 | #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 |
f2b0befd | 967 | /* PTP timestamping mode */ |
05a9320f | 968 | #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 |
f2b0befd BH |
969 | /* enum: PTP, version 1 */ |
970 | #define MC_CMD_PTP_MODE_V1 0x0 | |
971 | /* enum: PTP, version 1, with VLAN headers - deprecated */ | |
972 | #define MC_CMD_PTP_MODE_V1_VLAN 0x1 | |
973 | /* enum: PTP, version 2 */ | |
974 | #define MC_CMD_PTP_MODE_V2 0x2 | |
975 | /* enum: PTP, version 2, with VLAN headers - deprecated */ | |
976 | #define MC_CMD_PTP_MODE_V2_VLAN 0x3 | |
977 | /* enum: PTP, version 2, with improved UUID filtering */ | |
978 | #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 | |
979 | /* enum: FCoE (seconds and microseconds) */ | |
980 | #define MC_CMD_PTP_MODE_FCOE 0x5 | |
05a9320f BH |
981 | |
982 | /* MC_CMD_PTP_IN_DISABLE msgrequest */ | |
983 | #define MC_CMD_PTP_IN_DISABLE_LEN 8 | |
984 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
985 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
986 | ||
987 | /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ | |
988 | #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 | |
576eda8b | 989 | #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 |
05a9320f BH |
990 | #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) |
991 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
992 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 993 | /* Transmit packet length */ |
05a9320f | 994 | #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 |
f2b0befd | 995 | /* Transmit packet data */ |
05a9320f BH |
996 | #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 |
997 | #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 | |
998 | #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 | |
576eda8b | 999 | #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 |
05a9320f BH |
1000 | |
1001 | /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ | |
1002 | #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 | |
1003 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1004 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1005 | ||
1006 | /* MC_CMD_PTP_IN_STATUS msgrequest */ | |
1007 | #define MC_CMD_PTP_IN_STATUS_LEN 8 | |
1008 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1009 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1010 | ||
1011 | /* MC_CMD_PTP_IN_ADJUST msgrequest */ | |
1012 | #define MC_CMD_PTP_IN_ADJUST_LEN 24 | |
1013 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1014 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 1015 | /* Frequency adjustment 40 bit fixed point ns */ |
05a9320f BH |
1016 | #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 |
1017 | #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 | |
1018 | #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 | |
1019 | #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 | |
f2b0befd BH |
1020 | /* enum: Number of fractional bits in frequency adjustment */ |
1021 | #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 | |
1022 | /* Time adjustment in seconds */ | |
05a9320f | 1023 | #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 |
512bb06c BH |
1024 | /* Time adjustment major value */ |
1025 | #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 | |
f2b0befd | 1026 | /* Time adjustment in nanoseconds */ |
05a9320f | 1027 | #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 |
512bb06c BH |
1028 | /* Time adjustment minor value */ |
1029 | #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 | |
05a9320f BH |
1030 | |
1031 | /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ | |
1032 | #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 | |
1033 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1034 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 1035 | /* Number of time readings to capture */ |
05a9320f | 1036 | #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 |
f2b0befd BH |
1037 | /* Host address in which to write "synchronization started" indication (64 |
1038 | * bits) | |
1039 | */ | |
05a9320f BH |
1040 | #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 |
1041 | #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 | |
1042 | #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 | |
1043 | #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 | |
1044 | ||
1045 | /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ | |
1046 | #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 | |
1047 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1048 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1049 | ||
1050 | /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ | |
1051 | #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 | |
1052 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1053 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 1054 | /* Enable or disable packet testing */ |
05a9320f BH |
1055 | #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 |
1056 | ||
1057 | /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ | |
1058 | #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 | |
1059 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
f2b0befd | 1060 | /* Reset PTP statistics */ |
05a9320f BH |
1061 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
1062 | ||
1063 | /* MC_CMD_PTP_IN_DEBUG msgrequest */ | |
1064 | #define MC_CMD_PTP_IN_DEBUG_LEN 12 | |
1065 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1066 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 1067 | /* Debug operations */ |
05a9320f BH |
1068 | #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 |
1069 | ||
f2b0befd BH |
1070 | /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ |
1071 | #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 | |
1072 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1073 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1074 | #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 | |
1075 | #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 | |
1076 | ||
1077 | /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ | |
1078 | #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 | |
1079 | #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 | |
1080 | #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) | |
1081 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1082 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1083 | #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 | |
1084 | #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 | |
1085 | #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 | |
1086 | #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 | |
1087 | #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 | |
1088 | ||
1089 | /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ | |
1090 | #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 | |
1091 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1092 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1093 | /* Time adjustment in seconds */ | |
1094 | #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 | |
512bb06c BH |
1095 | /* Time adjustment major value */ |
1096 | #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 | |
f2b0befd BH |
1097 | /* Time adjustment in nanoseconds */ |
1098 | #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 | |
512bb06c BH |
1099 | /* Time adjustment minor value */ |
1100 | #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 | |
f2b0befd BH |
1101 | |
1102 | /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ | |
1103 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 | |
1104 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1105 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1106 | /* Frequency adjustment 40 bit fixed point ns */ | |
1107 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 | |
1108 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 | |
1109 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 | |
1110 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 | |
1111 | /* enum: Number of fractional bits in frequency adjustment */ | |
1112 | /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ | |
1113 | ||
1114 | /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ | |
1115 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 | |
1116 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1117 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1118 | /* Number of VLAN tags, 0 if not VLAN */ | |
1119 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 | |
1120 | /* Set of VLAN tags to filter against */ | |
1121 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 | |
1122 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 | |
1123 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 | |
1124 | ||
1125 | /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ | |
1126 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 | |
1127 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1128 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1129 | /* 1 to enable UUID filtering, 0 to disable */ | |
1130 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 | |
1131 | /* UUID to filter against */ | |
1132 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 | |
1133 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 | |
1134 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 | |
1135 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 | |
1136 | ||
1137 | /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ | |
1138 | #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 | |
1139 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1140 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1141 | /* 1 to enable Domain filtering, 0 to disable */ | |
1142 | #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 | |
1143 | /* Domain number to filter against */ | |
1144 | #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 | |
1145 | ||
1146 | /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ | |
1147 | #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 | |
1148 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1149 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1150 | /* Set the clock source. */ | |
1151 | #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 | |
1152 | /* enum: Internal. */ | |
1153 | #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 | |
1154 | /* enum: External. */ | |
1155 | #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 | |
1156 | ||
1157 | /* MC_CMD_PTP_IN_RST_CLK msgrequest */ | |
1158 | #define MC_CMD_PTP_IN_RST_CLK_LEN 8 | |
1159 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1160 | /* Reset value of Timer Reg. */ | |
1161 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1162 | ||
1163 | /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ | |
1164 | #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 | |
1165 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1166 | /* Enable or disable */ | |
1167 | #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 | |
1168 | /* enum: Enable */ | |
1169 | #define MC_CMD_PTP_ENABLE_PPS 0x0 | |
1170 | /* enum: Disable */ | |
1171 | #define MC_CMD_PTP_DISABLE_PPS 0x1 | |
512bb06c | 1172 | /* Queue id to send events back */ |
f2b0befd BH |
1173 | #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 |
1174 | ||
512bb06c BH |
1175 | /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ |
1176 | #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 | |
1177 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1178 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1179 | ||
1180 | /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ | |
1181 | #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 | |
1182 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1183 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1184 | ||
1185 | /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ | |
1186 | #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 | |
1187 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1188 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1189 | ||
1190 | /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ | |
1191 | #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 | |
1192 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1193 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1194 | /* Event queue to send PTP time events to */ | |
1195 | #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 | |
1196 | ||
1197 | /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ | |
1198 | #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 | |
1199 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1200 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1201 | /* Unsubscribe options */ | |
1202 | #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 | |
1203 | /* enum: Unsubscribe a single queue */ | |
1204 | #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 | |
1205 | /* enum: Unsubscribe all queues */ | |
1206 | #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 | |
1207 | /* Event queue ID */ | |
1208 | #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 | |
1209 | ||
1210 | /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ | |
1211 | #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 | |
1212 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1213 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1214 | /* 1 to enable PPS test mode, 0 to disable and return result. */ | |
1215 | #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 | |
1216 | ||
05a9320f BH |
1217 | /* MC_CMD_PTP_OUT msgresponse */ |
1218 | #define MC_CMD_PTP_OUT_LEN 0 | |
1219 | ||
1220 | /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ | |
1221 | #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 | |
f2b0befd | 1222 | /* Value of seconds timestamp */ |
05a9320f | 1223 | #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 |
512bb06c BH |
1224 | /* Timestamp major value */ |
1225 | #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 | |
f2b0befd | 1226 | /* Value of nanoseconds timestamp */ |
05a9320f | 1227 | #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 |
512bb06c BH |
1228 | /* Timestamp minor value */ |
1229 | #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 | |
1230 | ||
1231 | /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ | |
1232 | #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 | |
1233 | ||
1234 | /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ | |
1235 | #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 | |
05a9320f BH |
1236 | |
1237 | /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ | |
1238 | #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 | |
f2b0befd | 1239 | /* Value of seconds timestamp */ |
05a9320f | 1240 | #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 |
512bb06c BH |
1241 | /* Timestamp major value */ |
1242 | #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 | |
f2b0befd | 1243 | /* Value of nanoseconds timestamp */ |
05a9320f | 1244 | #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 |
512bb06c BH |
1245 | /* Timestamp minor value */ |
1246 | #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 | |
05a9320f BH |
1247 | |
1248 | /* MC_CMD_PTP_OUT_STATUS msgresponse */ | |
1249 | #define MC_CMD_PTP_OUT_STATUS_LEN 64 | |
f2b0befd | 1250 | /* Frequency of NIC's hardware clock */ |
05a9320f | 1251 | #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 |
f2b0befd | 1252 | /* Number of packets transmitted and timestamped */ |
05a9320f | 1253 | #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 |
f2b0befd | 1254 | /* Number of packets received and timestamped */ |
05a9320f | 1255 | #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 |
f2b0befd | 1256 | /* Number of packets timestamped by the FPGA */ |
05a9320f | 1257 | #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 |
f2b0befd | 1258 | /* Number of packets filter matched */ |
05a9320f | 1259 | #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 |
f2b0befd | 1260 | /* Number of packets not filter matched */ |
05a9320f | 1261 | #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 |
f2b0befd | 1262 | /* Number of PPS overflows (noise on input?) */ |
05a9320f | 1263 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 |
f2b0befd | 1264 | /* Number of PPS bad periods */ |
05a9320f | 1265 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 |
512bb06c | 1266 | /* Minimum period of PPS pulse in nanoseconds */ |
05a9320f | 1267 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 |
512bb06c | 1268 | /* Maximum period of PPS pulse in nanoseconds */ |
05a9320f | 1269 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 |
512bb06c | 1270 | /* Last period of PPS pulse in nanoseconds */ |
05a9320f | 1271 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 |
512bb06c | 1272 | /* Mean period of PPS pulse in nanoseconds */ |
05a9320f | 1273 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 |
512bb06c | 1274 | /* Minimum offset of PPS pulse in nanoseconds (signed) */ |
05a9320f | 1275 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 |
512bb06c | 1276 | /* Maximum offset of PPS pulse in nanoseconds (signed) */ |
05a9320f | 1277 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 |
512bb06c | 1278 | /* Last offset of PPS pulse in nanoseconds (signed) */ |
05a9320f | 1279 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 |
512bb06c | 1280 | /* Mean offset of PPS pulse in nanoseconds (signed) */ |
05a9320f BH |
1281 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 |
1282 | ||
1283 | /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ | |
1284 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 | |
1285 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 | |
1286 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) | |
f2b0befd | 1287 | /* A set of host and NIC times */ |
05a9320f BH |
1288 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 |
1289 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 | |
1290 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 | |
1291 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 | |
f2b0befd | 1292 | /* Host time immediately before NIC's hardware clock read */ |
05a9320f | 1293 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 |
f2b0befd | 1294 | /* Value of seconds timestamp */ |
05a9320f | 1295 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 |
512bb06c BH |
1296 | /* Timestamp major value */ |
1297 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 | |
f2b0befd | 1298 | /* Value of nanoseconds timestamp */ |
05a9320f | 1299 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 |
512bb06c BH |
1300 | /* Timestamp minor value */ |
1301 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 | |
f2b0befd | 1302 | /* Host time immediately after NIC's hardware clock read */ |
05a9320f | 1303 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 |
f2b0befd | 1304 | /* Number of nanoseconds waited after reading NIC's hardware clock */ |
05a9320f BH |
1305 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 |
1306 | ||
1307 | /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ | |
1308 | #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 | |
f2b0befd | 1309 | /* Results of testing */ |
05a9320f | 1310 | #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 |
f2b0befd BH |
1311 | /* enum: Successful test */ |
1312 | #define MC_CMD_PTP_MANF_SUCCESS 0x0 | |
1313 | /* enum: FPGA load failed */ | |
1314 | #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 | |
1315 | /* enum: FPGA version invalid */ | |
1316 | #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 | |
1317 | /* enum: FPGA registers incorrect */ | |
1318 | #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 | |
1319 | /* enum: Oscillator possibly not working? */ | |
1320 | #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 | |
1321 | /* enum: Timestamps not increasing */ | |
1322 | #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 | |
1323 | /* enum: Mismatched packet count */ | |
1324 | #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 | |
1325 | /* enum: Mismatched packet count (Siena filter and FPGA) */ | |
1326 | #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 | |
1327 | /* enum: Not enough packets to perform timestamp check */ | |
1328 | #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 | |
1329 | /* enum: Timestamp trigger GPIO not working */ | |
1330 | #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 | |
512bb06c BH |
1331 | /* enum: Insufficient PPS events to perform checks */ |
1332 | #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa | |
1333 | /* enum: PPS time event period not sufficiently close to 1s. */ | |
1334 | #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb | |
1335 | /* enum: PPS time event nS reading not sufficiently close to zero. */ | |
1336 | #define MC_CMD_PTP_MANF_PPS_NS 0xc | |
1337 | /* enum: PTP peripheral registers incorrect */ | |
1338 | #define MC_CMD_PTP_MANF_REGISTERS 0xd | |
1339 | /* enum: Failed to read time from PTP peripheral */ | |
1340 | #define MC_CMD_PTP_MANF_CLOCK_READ 0xe | |
f2b0befd | 1341 | /* Presence of external oscillator */ |
05a9320f BH |
1342 | #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 |
1343 | ||
1344 | /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ | |
1345 | #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 | |
f2b0befd | 1346 | /* Results of testing */ |
05a9320f | 1347 | #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 |
f2b0befd | 1348 | /* Number of packets received by FPGA */ |
05a9320f | 1349 | #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 |
f2b0befd | 1350 | /* Number of packets received by Siena filters */ |
05a9320f BH |
1351 | #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 |
1352 | ||
f2b0befd BH |
1353 | /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ |
1354 | #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 | |
1355 | #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 | |
1356 | #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) | |
1357 | #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 | |
1358 | #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 | |
1359 | #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 | |
1360 | #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 | |
1361 | ||
512bb06c BH |
1362 | /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ |
1363 | #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 | |
1364 | /* Time format required/used by for this NIC. Applies to all PTP MCDI | |
1365 | * operations that pass times between the host and firmware. If this operation | |
1366 | * is not supported (older firmware) a format of seconds and nanoseconds should | |
1367 | * be assumed. | |
1368 | */ | |
1369 | #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 | |
1370 | /* enum: Times are in seconds and nanoseconds */ | |
1371 | #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 | |
1372 | /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ | |
1373 | #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 | |
1374 | /* enum: Major register has units of seconds, minor 2^-27s per tick */ | |
1375 | #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 | |
1376 | ||
1377 | /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ | |
1378 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 8 | |
1379 | /* Time format required/used by for this NIC. Applies to all PTP MCDI | |
1380 | * operations that pass times between the host and firmware. If this operation | |
1381 | * is not supported (older firmware) a format of seconds and nanoseconds should | |
1382 | * be assumed. | |
1383 | */ | |
1384 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 | |
1385 | /* enum: Times are in seconds and nanoseconds */ | |
1386 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 | |
1387 | /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ | |
1388 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 | |
1389 | /* enum: Major register has units of seconds, minor 2^-27s per tick */ | |
1390 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 | |
1391 | /* Minimum acceptable value for a corrected synchronization timeset. When | |
1392 | * comparing host and NIC clock times, the MC returns a set of samples that | |
1393 | * contain the host start and end time, the MC time when the host start was | |
1394 | * detected and the time the MC waited between reading the time and detecting | |
1395 | * the host end. The corrected sync window is the difference between the host | |
1396 | * end and start times minus the time that the MC waited for host end. | |
1397 | */ | |
1398 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 | |
1399 | ||
1400 | /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ | |
1401 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 | |
1402 | /* Uncorrected error on transmit timestamps in NIC clock format */ | |
1403 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 | |
1404 | /* Uncorrected error on receive timestamps in NIC clock format */ | |
1405 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 | |
1406 | /* Uncorrected error on PPS output in NIC clock format */ | |
1407 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 | |
1408 | /* Uncorrected error on PPS input in NIC clock format */ | |
1409 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 | |
1410 | ||
1411 | /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ | |
1412 | #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 | |
1413 | /* Results of testing */ | |
1414 | #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 | |
1415 | /* Enum values, see field(s): */ | |
1416 | /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ | |
1417 | ||
05a9320f BH |
1418 | |
1419 | /***********************************/ | |
1420 | /* MC_CMD_CSR_READ32 | |
1421 | * Read 32bit words from the indirect memory map. | |
1422 | */ | |
1423 | #define MC_CMD_CSR_READ32 0xc | |
1424 | ||
75122ec8 SS |
1425 | #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1426 | ||
05a9320f BH |
1427 | /* MC_CMD_CSR_READ32_IN msgrequest */ |
1428 | #define MC_CMD_CSR_READ32_IN_LEN 12 | |
f2b0befd | 1429 | /* Address */ |
05a9320f BH |
1430 | #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 |
1431 | #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 | |
1432 | #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 | |
1433 | ||
1434 | /* MC_CMD_CSR_READ32_OUT msgresponse */ | |
1435 | #define MC_CMD_CSR_READ32_OUT_LENMIN 4 | |
1436 | #define MC_CMD_CSR_READ32_OUT_LENMAX 252 | |
1437 | #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) | |
f2b0befd | 1438 | /* The last dword is the status, not a value read */ |
05a9320f BH |
1439 | #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 |
1440 | #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 | |
1441 | #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 | |
1442 | #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 | |
1443 | ||
1444 | ||
1445 | /***********************************/ | |
1446 | /* MC_CMD_CSR_WRITE32 | |
1447 | * Write 32bit dwords to the indirect memory map. | |
1448 | */ | |
1449 | #define MC_CMD_CSR_WRITE32 0xd | |
1450 | ||
75122ec8 SS |
1451 | #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1452 | ||
05a9320f BH |
1453 | /* MC_CMD_CSR_WRITE32_IN msgrequest */ |
1454 | #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 | |
1455 | #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 | |
1456 | #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) | |
f2b0befd | 1457 | /* Address */ |
05a9320f BH |
1458 | #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 |
1459 | #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 | |
1460 | #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 | |
1461 | #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 | |
1462 | #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 | |
1463 | #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 | |
1464 | ||
1465 | /* MC_CMD_CSR_WRITE32_OUT msgresponse */ | |
1466 | #define MC_CMD_CSR_WRITE32_OUT_LEN 4 | |
1467 | #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 | |
1468 | ||
1469 | ||
f2b0befd BH |
1470 | /***********************************/ |
1471 | /* MC_CMD_HP | |
1472 | * These commands are used for HP related features. They are grouped under one | |
1473 | * MCDI command to avoid creating too many MCDI commands. | |
1474 | */ | |
1475 | #define MC_CMD_HP 0x54 | |
1476 | ||
75122ec8 SS |
1477 | #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1478 | ||
f2b0befd BH |
1479 | /* MC_CMD_HP_IN msgrequest */ |
1480 | #define MC_CMD_HP_IN_LEN 16 | |
1481 | /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at | |
1482 | * the specified address with the specified interval.When address is NULL, | |
1483 | * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current | |
1484 | * state / 2: (debug) Show temperature reported by one of the supported | |
1485 | * sensors. | |
1486 | */ | |
1487 | #define MC_CMD_HP_IN_SUBCMD_OFST 0 | |
1488 | /* enum: OCSD (Option Card Sensor Data) sub-command. */ | |
1489 | #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 | |
1490 | /* enum: Last known valid HP sub-command. */ | |
1491 | #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 | |
1492 | /* The address to the array of sensor fields. (Or NULL to use a sub-command.) | |
1493 | */ | |
1494 | #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 | |
1495 | #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 | |
1496 | #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 | |
1497 | #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 | |
1498 | /* The requested update interval, in seconds. (Or the sub-command if ADDR is | |
1499 | * NULL.) | |
1500 | */ | |
1501 | #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 | |
1502 | ||
1503 | /* MC_CMD_HP_OUT msgresponse */ | |
1504 | #define MC_CMD_HP_OUT_LEN 4 | |
1505 | #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 | |
1506 | /* enum: OCSD stopped for this card. */ | |
1507 | #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 | |
1508 | /* enum: OCSD was successfully started with the address provided. */ | |
1509 | #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 | |
1510 | /* enum: OCSD was already started for this card. */ | |
1511 | #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 | |
1512 | ||
1513 | ||
05a9320f BH |
1514 | /***********************************/ |
1515 | /* MC_CMD_STACKINFO | |
1516 | * Get stack information. | |
1517 | */ | |
1518 | #define MC_CMD_STACKINFO 0xf | |
1519 | ||
75122ec8 SS |
1520 | #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1521 | ||
05a9320f BH |
1522 | /* MC_CMD_STACKINFO_IN msgrequest */ |
1523 | #define MC_CMD_STACKINFO_IN_LEN 0 | |
1524 | ||
1525 | /* MC_CMD_STACKINFO_OUT msgresponse */ | |
1526 | #define MC_CMD_STACKINFO_OUT_LENMIN 12 | |
1527 | #define MC_CMD_STACKINFO_OUT_LENMAX 252 | |
1528 | #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) | |
f2b0befd | 1529 | /* (thread ptr, stack size, free space) for each thread in system */ |
05a9320f BH |
1530 | #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 |
1531 | #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 | |
1532 | #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 | |
1533 | #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 | |
1534 | ||
1535 | ||
1536 | /***********************************/ | |
1537 | /* MC_CMD_MDIO_READ | |
1538 | * MDIO register read. | |
f0d37f42 SH |
1539 | */ |
1540 | #define MC_CMD_MDIO_READ 0x10 | |
f0d37f42 | 1541 | |
75122ec8 SS |
1542 | #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
1543 | ||
05a9320f BH |
1544 | /* MC_CMD_MDIO_READ_IN msgrequest */ |
1545 | #define MC_CMD_MDIO_READ_IN_LEN 16 | |
f2b0befd BH |
1546 | /* Bus number; there are two MDIO buses: one for the internal PHY, and one for |
1547 | * external devices. | |
1548 | */ | |
05a9320f | 1549 | #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 |
f2b0befd BH |
1550 | /* enum: Internal. */ |
1551 | #define MC_CMD_MDIO_BUS_INTERNAL 0x0 | |
1552 | /* enum: External. */ | |
1553 | #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 | |
1554 | /* Port address */ | |
05a9320f | 1555 | #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 |
f2b0befd | 1556 | /* Device Address or clause 22. */ |
05a9320f | 1557 | #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 |
f2b0befd BH |
1558 | /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you |
1559 | * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. | |
1560 | */ | |
1561 | #define MC_CMD_MDIO_CLAUSE22 0x20 | |
1562 | /* Address */ | |
05a9320f | 1563 | #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 |
f0d37f42 | 1564 | |
05a9320f BH |
1565 | /* MC_CMD_MDIO_READ_OUT msgresponse */ |
1566 | #define MC_CMD_MDIO_READ_OUT_LEN 8 | |
f2b0befd | 1567 | /* Value */ |
05a9320f | 1568 | #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 |
f2b0befd BH |
1569 | /* Status the MDIO commands return the raw status bits from the MDIO block. A |
1570 | * "good" transaction should have the DONE bit set and all other bits clear. | |
1571 | */ | |
05a9320f | 1572 | #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 |
f2b0befd BH |
1573 | /* enum: Good. */ |
1574 | #define MC_CMD_MDIO_STATUS_GOOD 0x8 | |
f0d37f42 | 1575 | |
05a9320f BH |
1576 | |
1577 | /***********************************/ | |
1578 | /* MC_CMD_MDIO_WRITE | |
1579 | * MDIO register write. | |
f0d37f42 | 1580 | */ |
05a9320f | 1581 | #define MC_CMD_MDIO_WRITE 0x11 |
f0d37f42 | 1582 | |
75122ec8 SS |
1583 | #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1584 | ||
05a9320f BH |
1585 | /* MC_CMD_MDIO_WRITE_IN msgrequest */ |
1586 | #define MC_CMD_MDIO_WRITE_IN_LEN 20 | |
f2b0befd BH |
1587 | /* Bus number; there are two MDIO buses: one for the internal PHY, and one for |
1588 | * external devices. | |
1589 | */ | |
05a9320f | 1590 | #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 |
f2b0befd | 1591 | /* enum: Internal. */ |
05a9320f | 1592 | /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ |
f2b0befd | 1593 | /* enum: External. */ |
05a9320f | 1594 | /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ |
f2b0befd | 1595 | /* Port address */ |
05a9320f | 1596 | #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 |
f2b0befd | 1597 | /* Device Address or clause 22. */ |
05a9320f | 1598 | #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 |
f2b0befd BH |
1599 | /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you |
1600 | * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. | |
1601 | */ | |
05a9320f | 1602 | /* MC_CMD_MDIO_CLAUSE22 0x20 */ |
f2b0befd | 1603 | /* Address */ |
05a9320f | 1604 | #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 |
f2b0befd | 1605 | /* Value */ |
05a9320f | 1606 | #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 |
f0d37f42 | 1607 | |
05a9320f BH |
1608 | /* MC_CMD_MDIO_WRITE_OUT msgresponse */ |
1609 | #define MC_CMD_MDIO_WRITE_OUT_LEN 4 | |
f2b0befd BH |
1610 | /* Status; the MDIO commands return the raw status bits from the MDIO block. A |
1611 | * "good" transaction should have the DONE bit set and all other bits clear. | |
1612 | */ | |
05a9320f | 1613 | #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 |
f2b0befd | 1614 | /* enum: Good. */ |
05a9320f BH |
1615 | /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ |
1616 | ||
1617 | ||
1618 | /***********************************/ | |
1619 | /* MC_CMD_DBI_WRITE | |
1620 | * Write DBI register(s). | |
f0d37f42 SH |
1621 | */ |
1622 | #define MC_CMD_DBI_WRITE 0x12 | |
05a9320f | 1623 | |
75122ec8 SS |
1624 | #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1625 | ||
05a9320f BH |
1626 | /* MC_CMD_DBI_WRITE_IN msgrequest */ |
1627 | #define MC_CMD_DBI_WRITE_IN_LENMIN 12 | |
1628 | #define MC_CMD_DBI_WRITE_IN_LENMAX 252 | |
1629 | #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) | |
f2b0befd BH |
1630 | /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset |
1631 | * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. | |
1632 | */ | |
05a9320f BH |
1633 | #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 |
1634 | #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 | |
1635 | #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 | |
1636 | #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 | |
1637 | ||
1638 | /* MC_CMD_DBI_WRITE_OUT msgresponse */ | |
1639 | #define MC_CMD_DBI_WRITE_OUT_LEN 0 | |
1640 | ||
1641 | /* MC_CMD_DBIWROP_TYPEDEF structuredef */ | |
1642 | #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 | |
1643 | #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 | |
1644 | #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 | |
1645 | #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 | |
f2b0befd BH |
1646 | #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 |
1647 | #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 | |
1648 | #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 | |
1649 | #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 | |
1650 | #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 | |
1651 | #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 | |
1652 | #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 | |
1653 | #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 | |
1654 | #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 | |
05a9320f BH |
1655 | #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 |
1656 | #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 | |
1657 | #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 | |
1658 | ||
1659 | ||
1660 | /***********************************/ | |
1661 | /* MC_CMD_PORT_READ32 | |
f2b0befd BH |
1662 | * Read a 32-bit register from the indirect port register map. The port to |
1663 | * access is implied by the Shared memory channel used. | |
f0d37f42 SH |
1664 | */ |
1665 | #define MC_CMD_PORT_READ32 0x14 | |
f0d37f42 | 1666 | |
05a9320f BH |
1667 | /* MC_CMD_PORT_READ32_IN msgrequest */ |
1668 | #define MC_CMD_PORT_READ32_IN_LEN 4 | |
f2b0befd | 1669 | /* Address */ |
05a9320f BH |
1670 | #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 |
1671 | ||
1672 | /* MC_CMD_PORT_READ32_OUT msgresponse */ | |
1673 | #define MC_CMD_PORT_READ32_OUT_LEN 8 | |
f2b0befd | 1674 | /* Value */ |
05a9320f | 1675 | #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 |
f2b0befd | 1676 | /* Status */ |
05a9320f BH |
1677 | #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 |
1678 | ||
1679 | ||
1680 | /***********************************/ | |
1681 | /* MC_CMD_PORT_WRITE32 | |
f2b0befd BH |
1682 | * Write a 32-bit register to the indirect port register map. The port to |
1683 | * access is implied by the Shared memory channel used. | |
f0d37f42 SH |
1684 | */ |
1685 | #define MC_CMD_PORT_WRITE32 0x15 | |
05a9320f BH |
1686 | |
1687 | /* MC_CMD_PORT_WRITE32_IN msgrequest */ | |
1688 | #define MC_CMD_PORT_WRITE32_IN_LEN 8 | |
f2b0befd | 1689 | /* Address */ |
05a9320f | 1690 | #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 |
f2b0befd | 1691 | /* Value */ |
05a9320f BH |
1692 | #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 |
1693 | ||
1694 | /* MC_CMD_PORT_WRITE32_OUT msgresponse */ | |
1695 | #define MC_CMD_PORT_WRITE32_OUT_LEN 4 | |
f2b0befd | 1696 | /* Status */ |
05a9320f BH |
1697 | #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 |
1698 | ||
1699 | ||
1700 | /***********************************/ | |
1701 | /* MC_CMD_PORT_READ128 | |
f2b0befd BH |
1702 | * Read a 128-bit register from the indirect port register map. The port to |
1703 | * access is implied by the Shared memory channel used. | |
f0d37f42 SH |
1704 | */ |
1705 | #define MC_CMD_PORT_READ128 0x16 | |
05a9320f BH |
1706 | |
1707 | /* MC_CMD_PORT_READ128_IN msgrequest */ | |
1708 | #define MC_CMD_PORT_READ128_IN_LEN 4 | |
f2b0befd | 1709 | /* Address */ |
05a9320f BH |
1710 | #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 |
1711 | ||
1712 | /* MC_CMD_PORT_READ128_OUT msgresponse */ | |
1713 | #define MC_CMD_PORT_READ128_OUT_LEN 20 | |
f2b0befd | 1714 | /* Value */ |
05a9320f BH |
1715 | #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 |
1716 | #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 | |
f2b0befd | 1717 | /* Status */ |
05a9320f BH |
1718 | #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 |
1719 | ||
1720 | ||
1721 | /***********************************/ | |
1722 | /* MC_CMD_PORT_WRITE128 | |
f2b0befd BH |
1723 | * Write a 128-bit register to the indirect port register map. The port to |
1724 | * access is implied by the Shared memory channel used. | |
f0d37f42 SH |
1725 | */ |
1726 | #define MC_CMD_PORT_WRITE128 0x17 | |
05a9320f BH |
1727 | |
1728 | /* MC_CMD_PORT_WRITE128_IN msgrequest */ | |
1729 | #define MC_CMD_PORT_WRITE128_IN_LEN 20 | |
f2b0befd | 1730 | /* Address */ |
05a9320f | 1731 | #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 |
f2b0befd | 1732 | /* Value */ |
05a9320f BH |
1733 | #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 |
1734 | #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 | |
1735 | ||
1736 | /* MC_CMD_PORT_WRITE128_OUT msgresponse */ | |
1737 | #define MC_CMD_PORT_WRITE128_OUT_LEN 4 | |
f2b0befd | 1738 | /* Status */ |
05a9320f BH |
1739 | #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 |
1740 | ||
f2b0befd BH |
1741 | /* MC_CMD_CAPABILITIES structuredef */ |
1742 | #define MC_CMD_CAPABILITIES_LEN 4 | |
1743 | /* Small buf table. */ | |
1744 | #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 | |
1745 | #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 | |
1746 | /* Turbo mode (for Maranello). */ | |
1747 | #define MC_CMD_CAPABILITIES_TURBO_LBN 1 | |
1748 | #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 | |
1749 | /* Turbo mode active (for Maranello). */ | |
1750 | #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 | |
1751 | #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 | |
1752 | /* PTP offload. */ | |
1753 | #define MC_CMD_CAPABILITIES_PTP_LBN 3 | |
1754 | #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 | |
1755 | /* AOE mode. */ | |
1756 | #define MC_CMD_CAPABILITIES_AOE_LBN 4 | |
1757 | #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 | |
1758 | /* AOE mode active. */ | |
1759 | #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 | |
1760 | #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 | |
1761 | /* AOE mode active. */ | |
1762 | #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 | |
1763 | #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 | |
1764 | #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 | |
1765 | #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 | |
1766 | ||
05a9320f BH |
1767 | |
1768 | /***********************************/ | |
1769 | /* MC_CMD_GET_BOARD_CFG | |
1770 | * Returns the MC firmware configuration structure. | |
f0d37f42 SH |
1771 | */ |
1772 | #define MC_CMD_GET_BOARD_CFG 0x18 | |
05a9320f | 1773 | |
75122ec8 SS |
1774 | #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
1775 | ||
05a9320f BH |
1776 | /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ |
1777 | #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 | |
1778 | ||
1779 | /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ | |
1780 | #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 | |
1781 | #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 | |
1782 | #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) | |
1783 | #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 | |
1784 | #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 | |
1785 | #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 | |
f2b0befd | 1786 | /* See MC_CMD_CAPABILITIES */ |
05a9320f | 1787 | #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 |
f2b0befd | 1788 | /* See MC_CMD_CAPABILITIES */ |
05a9320f | 1789 | #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 |
05a9320f BH |
1790 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 |
1791 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 | |
1792 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 | |
1793 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 | |
1794 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 | |
1795 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 | |
1796 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 | |
1797 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 | |
f2b0befd BH |
1798 | /* This field contains a 16-bit value for each of the types of NVRAM area. The |
1799 | * values are defined in the firmware/mc/platform/.c file for a specific board | |
1800 | * type, but otherwise have no meaning to the MC; they are used by the driver | |
1801 | * to manage selection of appropriate firmware updates. | |
1802 | */ | |
05a9320f BH |
1803 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 |
1804 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 | |
1805 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 | |
1806 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 | |
1807 | ||
1808 | ||
1809 | /***********************************/ | |
1810 | /* MC_CMD_DBI_READX | |
f2b0befd | 1811 | * Read DBI register(s) -- extended functionality |
f0d37f42 SH |
1812 | */ |
1813 | #define MC_CMD_DBI_READX 0x19 | |
f0d37f42 | 1814 | |
75122ec8 SS |
1815 | #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1816 | ||
05a9320f BH |
1817 | /* MC_CMD_DBI_READX_IN msgrequest */ |
1818 | #define MC_CMD_DBI_READX_IN_LENMIN 8 | |
1819 | #define MC_CMD_DBI_READX_IN_LENMAX 248 | |
1820 | #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) | |
f2b0befd | 1821 | /* Each Read op consists of an address (offset 0), VF/CS2) */ |
05a9320f BH |
1822 | #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 |
1823 | #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 | |
1824 | #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 | |
1825 | #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 | |
1826 | #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 | |
1827 | #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 | |
1828 | ||
1829 | /* MC_CMD_DBI_READX_OUT msgresponse */ | |
1830 | #define MC_CMD_DBI_READX_OUT_LENMIN 4 | |
1831 | #define MC_CMD_DBI_READX_OUT_LENMAX 252 | |
1832 | #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) | |
f2b0befd | 1833 | /* Value */ |
05a9320f BH |
1834 | #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 |
1835 | #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 | |
1836 | #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 | |
1837 | #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 | |
1838 | ||
f2b0befd BH |
1839 | /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ |
1840 | #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 | |
1841 | #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 | |
1842 | #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 | |
1843 | #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 | |
1844 | #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 | |
1845 | #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 | |
1846 | #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 | |
1847 | #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 | |
1848 | #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 | |
1849 | #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 | |
1850 | #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 | |
1851 | #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 | |
1852 | #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 | |
1853 | ||
05a9320f BH |
1854 | |
1855 | /***********************************/ | |
1856 | /* MC_CMD_SET_RAND_SEED | |
1857 | * Set the 16byte seed for the MC pseudo-random generator. | |
f0d37f42 SH |
1858 | */ |
1859 | #define MC_CMD_SET_RAND_SEED 0x1a | |
f0d37f42 | 1860 | |
75122ec8 SS |
1861 | #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1862 | ||
05a9320f BH |
1863 | /* MC_CMD_SET_RAND_SEED_IN msgrequest */ |
1864 | #define MC_CMD_SET_RAND_SEED_IN_LEN 16 | |
f2b0befd | 1865 | /* Seed value. */ |
05a9320f BH |
1866 | #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 |
1867 | #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 | |
1868 | ||
1869 | /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ | |
1870 | #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 | |
1871 | ||
1872 | ||
1873 | /***********************************/ | |
1874 | /* MC_CMD_LTSSM_HIST | |
f2b0befd | 1875 | * Retrieve the history of the LTSSM, if the build supports it. |
f0d37f42 SH |
1876 | */ |
1877 | #define MC_CMD_LTSSM_HIST 0x1b | |
1878 | ||
05a9320f BH |
1879 | /* MC_CMD_LTSSM_HIST_IN msgrequest */ |
1880 | #define MC_CMD_LTSSM_HIST_IN_LEN 0 | |
1881 | ||
1882 | /* MC_CMD_LTSSM_HIST_OUT msgresponse */ | |
1883 | #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 | |
1884 | #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 | |
1885 | #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) | |
f2b0befd | 1886 | /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ |
05a9320f BH |
1887 | #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 |
1888 | #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 | |
1889 | #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 | |
1890 | #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 | |
1891 | ||
1892 | ||
1893 | /***********************************/ | |
1894 | /* MC_CMD_DRV_ATTACH | |
f2b0befd BH |
1895 | * Inform MCPU that this port is managed on the host (i.e. driver active). For |
1896 | * Huntington, also request the preferred datapath firmware to use if possible | |
1897 | * (it may not be possible for this request to be fulfilled; the driver must | |
1898 | * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which | |
1899 | * features are actually available). The FIRMWARE_ID field is ignored by older | |
1900 | * platforms. | |
f0d37f42 SH |
1901 | */ |
1902 | #define MC_CMD_DRV_ATTACH 0x1c | |
f0d37f42 | 1903 | |
75122ec8 SS |
1904 | #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
1905 | ||
05a9320f | 1906 | /* MC_CMD_DRV_ATTACH_IN msgrequest */ |
f2b0befd BH |
1907 | #define MC_CMD_DRV_ATTACH_IN_LEN 12 |
1908 | /* new state (0=detached, 1=attached) to set if UPDATE=1 */ | |
05a9320f | 1909 | #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 |
f2b0befd | 1910 | /* 1 to set new state, or 0 to just report the existing state */ |
05a9320f | 1911 | #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 |
f2b0befd BH |
1912 | /* preferred datapath firmware (for Huntington; ignored for Siena) */ |
1913 | #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 | |
1914 | /* enum: Prefer to use full featured firmware */ | |
1915 | #define MC_CMD_FW_FULL_FEATURED 0x0 | |
1916 | /* enum: Prefer to use firmware with fewer features but lower latency */ | |
1917 | #define MC_CMD_FW_LOW_LATENCY 0x1 | |
267d9d73 EC |
1918 | /* enum: Only this option is allowed for non-admin functions */ |
1919 | #define MC_CMD_FW_DONT_CARE 0xffffffff | |
05a9320f BH |
1920 | |
1921 | /* MC_CMD_DRV_ATTACH_OUT msgresponse */ | |
1922 | #define MC_CMD_DRV_ATTACH_OUT_LEN 4 | |
f2b0befd | 1923 | /* previous or existing state (0=detached, 1=attached) */ |
05a9320f BH |
1924 | #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 |
1925 | ||
f2b0befd BH |
1926 | /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ |
1927 | #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 | |
1928 | /* previous or existing state (0=detached, 1=attached) */ | |
1929 | #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 | |
1930 | /* Flags associated with this function */ | |
1931 | #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 | |
1932 | /* enum: Labels the lowest-numbered function visible to the OS */ | |
1933 | #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 | |
1934 | /* enum: The function can control the link state of the physical port it is | |
1935 | * bound to. | |
f0d37f42 | 1936 | */ |
f2b0befd BH |
1937 | #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 |
1938 | /* enum: The function can perform privileged operations */ | |
1939 | #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 | |
05a9320f BH |
1940 | |
1941 | ||
1942 | /***********************************/ | |
1943 | /* MC_CMD_SHMUART | |
f0d37f42 SH |
1944 | * Route UART output to circular buffer in shared memory instead. |
1945 | */ | |
1946 | #define MC_CMD_SHMUART 0x1f | |
f0d37f42 | 1947 | |
05a9320f BH |
1948 | /* MC_CMD_SHMUART_IN msgrequest */ |
1949 | #define MC_CMD_SHMUART_IN_LEN 4 | |
f2b0befd | 1950 | /* ??? */ |
05a9320f BH |
1951 | #define MC_CMD_SHMUART_IN_FLAG_OFST 0 |
1952 | ||
1953 | /* MC_CMD_SHMUART_OUT msgresponse */ | |
1954 | #define MC_CMD_SHMUART_OUT_LEN 0 | |
1955 | ||
1956 | ||
f2b0befd BH |
1957 | /***********************************/ |
1958 | /* MC_CMD_PORT_RESET | |
1959 | * Generic per-port reset. There is no equivalent for per-board reset. Locks | |
1960 | * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - | |
1961 | * use MC_CMD_ENTITY_RESET instead. | |
1962 | */ | |
1963 | #define MC_CMD_PORT_RESET 0x20 | |
1964 | ||
75122ec8 SS |
1965 | #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
1966 | ||
f2b0befd BH |
1967 | /* MC_CMD_PORT_RESET_IN msgrequest */ |
1968 | #define MC_CMD_PORT_RESET_IN_LEN 0 | |
1969 | ||
1970 | /* MC_CMD_PORT_RESET_OUT msgresponse */ | |
1971 | #define MC_CMD_PORT_RESET_OUT_LEN 0 | |
1972 | ||
1973 | ||
05a9320f BH |
1974 | /***********************************/ |
1975 | /* MC_CMD_ENTITY_RESET | |
f2b0befd BH |
1976 | * Generic per-resource reset. There is no equivalent for per-board reset. |
1977 | * Locks required: None; Return code: 0, ETIME. NOTE: This command is an | |
1978 | * extended version of the deprecated MC_CMD_PORT_RESET with added fields. | |
05a9320f BH |
1979 | */ |
1980 | #define MC_CMD_ENTITY_RESET 0x20 | |
75122ec8 | 1981 | /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ |
05a9320f BH |
1982 | |
1983 | /* MC_CMD_ENTITY_RESET_IN msgrequest */ | |
1984 | #define MC_CMD_ENTITY_RESET_IN_LEN 4 | |
f2b0befd BH |
1985 | /* Optional flags field. Omitting this will perform a "legacy" reset action |
1986 | * (TBD). | |
1987 | */ | |
05a9320f BH |
1988 | #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 |
1989 | #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 | |
1990 | #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 | |
1991 | ||
1992 | /* MC_CMD_ENTITY_RESET_OUT msgresponse */ | |
1993 | #define MC_CMD_ENTITY_RESET_OUT_LEN 0 | |
1994 | ||
1995 | ||
1996 | /***********************************/ | |
1997 | /* MC_CMD_PCIE_CREDITS | |
1998 | * Read instantaneous and minimum flow control thresholds. | |
1999 | */ | |
2000 | #define MC_CMD_PCIE_CREDITS 0x21 | |
2001 | ||
2002 | /* MC_CMD_PCIE_CREDITS_IN msgrequest */ | |
2003 | #define MC_CMD_PCIE_CREDITS_IN_LEN 8 | |
f2b0befd | 2004 | /* poll period. 0 is disabled */ |
05a9320f | 2005 | #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 |
f2b0befd | 2006 | /* wipe statistics */ |
05a9320f BH |
2007 | #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 |
2008 | ||
2009 | /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ | |
2010 | #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 | |
2011 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 | |
2012 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 | |
2013 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 | |
2014 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 | |
2015 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 | |
2016 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 | |
2017 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 | |
2018 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 | |
2019 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 | |
2020 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 | |
2021 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 | |
2022 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 | |
2023 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 | |
2024 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 | |
2025 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 | |
2026 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 | |
2027 | ||
2028 | ||
2029 | /***********************************/ | |
2030 | /* MC_CMD_RXD_MONITOR | |
2031 | * Get histogram of RX queue fill level. | |
2032 | */ | |
2033 | #define MC_CMD_RXD_MONITOR 0x22 | |
2034 | ||
2035 | /* MC_CMD_RXD_MONITOR_IN msgrequest */ | |
2036 | #define MC_CMD_RXD_MONITOR_IN_LEN 12 | |
2037 | #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 | |
2038 | #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 | |
2039 | #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 | |
2040 | ||
2041 | /* MC_CMD_RXD_MONITOR_OUT msgresponse */ | |
2042 | #define MC_CMD_RXD_MONITOR_OUT_LEN 80 | |
2043 | #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 | |
2044 | #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 | |
2045 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 | |
2046 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 | |
2047 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 | |
2048 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 | |
2049 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 | |
2050 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 | |
2051 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 | |
2052 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 | |
2053 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 | |
2054 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 | |
2055 | #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 | |
2056 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 | |
2057 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 | |
2058 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 | |
2059 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 | |
2060 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 | |
2061 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 | |
2062 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 | |
2063 | ||
2064 | ||
2065 | /***********************************/ | |
2066 | /* MC_CMD_PUTS | |
f2b0befd | 2067 | * Copy the given ASCII string out onto UART and/or out of the network port. |
05a9320f BH |
2068 | */ |
2069 | #define MC_CMD_PUTS 0x23 | |
2070 | ||
75122ec8 SS |
2071 | #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
2072 | ||
05a9320f BH |
2073 | /* MC_CMD_PUTS_IN msgrequest */ |
2074 | #define MC_CMD_PUTS_IN_LENMIN 13 | |
576eda8b | 2075 | #define MC_CMD_PUTS_IN_LENMAX 252 |
05a9320f BH |
2076 | #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) |
2077 | #define MC_CMD_PUTS_IN_DEST_OFST 0 | |
2078 | #define MC_CMD_PUTS_IN_UART_LBN 0 | |
2079 | #define MC_CMD_PUTS_IN_UART_WIDTH 1 | |
2080 | #define MC_CMD_PUTS_IN_PORT_LBN 1 | |
2081 | #define MC_CMD_PUTS_IN_PORT_WIDTH 1 | |
2082 | #define MC_CMD_PUTS_IN_DHOST_OFST 4 | |
2083 | #define MC_CMD_PUTS_IN_DHOST_LEN 6 | |
2084 | #define MC_CMD_PUTS_IN_STRING_OFST 12 | |
2085 | #define MC_CMD_PUTS_IN_STRING_LEN 1 | |
2086 | #define MC_CMD_PUTS_IN_STRING_MINNUM 1 | |
576eda8b | 2087 | #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 |
05a9320f BH |
2088 | |
2089 | /* MC_CMD_PUTS_OUT msgresponse */ | |
2090 | #define MC_CMD_PUTS_OUT_LEN 0 | |
2091 | ||
2092 | ||
2093 | /***********************************/ | |
2094 | /* MC_CMD_GET_PHY_CFG | |
f2b0befd BH |
2095 | * Report PHY configuration. This guarantees to succeed even if the PHY is in a |
2096 | * 'zombie' state. Locks required: None | |
f0d37f42 SH |
2097 | */ |
2098 | #define MC_CMD_GET_PHY_CFG 0x24 | |
2099 | ||
75122ec8 SS |
2100 | #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
2101 | ||
05a9320f BH |
2102 | /* MC_CMD_GET_PHY_CFG_IN msgrequest */ |
2103 | #define MC_CMD_GET_PHY_CFG_IN_LEN 0 | |
2104 | ||
2105 | /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ | |
2106 | #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 | |
f2b0befd | 2107 | /* flags */ |
05a9320f BH |
2108 | #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 |
2109 | #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 | |
2110 | #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 | |
2111 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 | |
2112 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 | |
2113 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 | |
2114 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 | |
2115 | #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 | |
2116 | #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 | |
2117 | #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 | |
2118 | #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 | |
2119 | #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 | |
2120 | #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 | |
2121 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 | |
2122 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 | |
f2b0befd | 2123 | /* ?? */ |
05a9320f | 2124 | #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 |
f2b0befd | 2125 | /* Bitmask of supported capabilities */ |
05a9320f BH |
2126 | #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 |
2127 | #define MC_CMD_PHY_CAP_10HDX_LBN 1 | |
2128 | #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 | |
2129 | #define MC_CMD_PHY_CAP_10FDX_LBN 2 | |
2130 | #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 | |
2131 | #define MC_CMD_PHY_CAP_100HDX_LBN 3 | |
2132 | #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 | |
2133 | #define MC_CMD_PHY_CAP_100FDX_LBN 4 | |
2134 | #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 | |
2135 | #define MC_CMD_PHY_CAP_1000HDX_LBN 5 | |
2136 | #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 | |
2137 | #define MC_CMD_PHY_CAP_1000FDX_LBN 6 | |
2138 | #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 | |
2139 | #define MC_CMD_PHY_CAP_10000FDX_LBN 7 | |
2140 | #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 | |
2141 | #define MC_CMD_PHY_CAP_PAUSE_LBN 8 | |
2142 | #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 | |
2143 | #define MC_CMD_PHY_CAP_ASYM_LBN 9 | |
2144 | #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 | |
2145 | #define MC_CMD_PHY_CAP_AN_LBN 10 | |
2146 | #define MC_CMD_PHY_CAP_AN_WIDTH 1 | |
f2b0befd BH |
2147 | #define MC_CMD_PHY_CAP_40000FDX_LBN 11 |
2148 | #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 | |
2149 | #define MC_CMD_PHY_CAP_DDM_LBN 12 | |
2150 | #define MC_CMD_PHY_CAP_DDM_WIDTH 1 | |
2151 | /* ?? */ | |
05a9320f | 2152 | #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 |
f2b0befd | 2153 | /* ?? */ |
05a9320f | 2154 | #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 |
f2b0befd | 2155 | /* ?? */ |
05a9320f | 2156 | #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 |
f2b0befd | 2157 | /* ?? */ |
05a9320f BH |
2158 | #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 |
2159 | #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 | |
f2b0befd | 2160 | /* ?? */ |
05a9320f | 2161 | #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 |
f2b0befd BH |
2162 | /* enum: Xaui. */ |
2163 | #define MC_CMD_MEDIA_XAUI 0x1 | |
2164 | /* enum: CX4. */ | |
2165 | #define MC_CMD_MEDIA_CX4 0x2 | |
2166 | /* enum: KX4. */ | |
2167 | #define MC_CMD_MEDIA_KX4 0x3 | |
2168 | /* enum: XFP Far. */ | |
2169 | #define MC_CMD_MEDIA_XFP 0x4 | |
2170 | /* enum: SFP+. */ | |
2171 | #define MC_CMD_MEDIA_SFP_PLUS 0x5 | |
2172 | /* enum: 10GBaseT. */ | |
2173 | #define MC_CMD_MEDIA_BASE_T 0x6 | |
512bb06c BH |
2174 | /* enum: QSFP+. */ |
2175 | #define MC_CMD_MEDIA_QSFP_PLUS 0x7 | |
05a9320f | 2176 | #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 |
f2b0befd BH |
2177 | /* enum: Native clause 22 */ |
2178 | #define MC_CMD_MMD_CLAUSE22 0x0 | |
05a9320f BH |
2179 | #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ |
2180 | #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ | |
2181 | #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ | |
2182 | #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ | |
2183 | #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ | |
2184 | #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ | |
2185 | #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ | |
f2b0befd BH |
2186 | /* enum: Clause22 proxied over clause45 by PHY. */ |
2187 | #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d | |
05a9320f BH |
2188 | #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ |
2189 | #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ | |
2190 | #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 | |
2191 | #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 | |
2192 | ||
2193 | ||
2194 | /***********************************/ | |
2195 | /* MC_CMD_START_BIST | |
f2b0befd BH |
2196 | * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST |
2197 | * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) | |
f0d37f42 SH |
2198 | */ |
2199 | #define MC_CMD_START_BIST 0x25 | |
05a9320f | 2200 | |
75122ec8 SS |
2201 | #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
2202 | ||
05a9320f BH |
2203 | /* MC_CMD_START_BIST_IN msgrequest */ |
2204 | #define MC_CMD_START_BIST_IN_LEN 4 | |
f2b0befd | 2205 | /* Type of test. */ |
05a9320f | 2206 | #define MC_CMD_START_BIST_IN_TYPE_OFST 0 |
f2b0befd BH |
2207 | /* enum: Run the PHY's short cable BIST. */ |
2208 | #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 | |
2209 | /* enum: Run the PHY's long cable BIST. */ | |
2210 | #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 | |
2211 | /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ | |
2212 | #define MC_CMD_BPX_SERDES_BIST 0x3 | |
2213 | /* enum: Run the MC loopback tests. */ | |
2214 | #define MC_CMD_MC_LOOPBACK_BIST 0x4 | |
2215 | /* enum: Run the PHY's standard BIST. */ | |
2216 | #define MC_CMD_PHY_BIST 0x5 | |
2217 | /* enum: Run MC RAM test. */ | |
2218 | #define MC_CMD_MC_MEM_BIST 0x6 | |
2219 | /* enum: Run Port RAM test. */ | |
2220 | #define MC_CMD_PORT_MEM_BIST 0x7 | |
2221 | /* enum: Run register test. */ | |
2222 | #define MC_CMD_REG_BIST 0x8 | |
05a9320f BH |
2223 | |
2224 | /* MC_CMD_START_BIST_OUT msgresponse */ | |
2225 | #define MC_CMD_START_BIST_OUT_LEN 0 | |
2226 | ||
2227 | ||
2228 | /***********************************/ | |
2229 | /* MC_CMD_POLL_BIST | |
f2b0befd BH |
2230 | * Poll for BIST completion. Returns a single status code, and optionally some |
2231 | * PHY specific bist output. The driver should only consume the BIST output | |
2232 | * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't | |
2233 | * successfully parse the BIST output, it should still respect the pass/Fail in | |
2234 | * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, | |
2235 | * EACCES (if PHY_LOCK is not held). | |
f0d37f42 SH |
2236 | */ |
2237 | #define MC_CMD_POLL_BIST 0x26 | |
05a9320f | 2238 | |
75122ec8 SS |
2239 | #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
2240 | ||
05a9320f BH |
2241 | /* MC_CMD_POLL_BIST_IN msgrequest */ |
2242 | #define MC_CMD_POLL_BIST_IN_LEN 0 | |
2243 | ||
2244 | /* MC_CMD_POLL_BIST_OUT msgresponse */ | |
2245 | #define MC_CMD_POLL_BIST_OUT_LEN 8 | |
f2b0befd | 2246 | /* result */ |
05a9320f | 2247 | #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 |
f2b0befd BH |
2248 | /* enum: Running. */ |
2249 | #define MC_CMD_POLL_BIST_RUNNING 0x1 | |
2250 | /* enum: Passed. */ | |
2251 | #define MC_CMD_POLL_BIST_PASSED 0x2 | |
2252 | /* enum: Failed. */ | |
2253 | #define MC_CMD_POLL_BIST_FAILED 0x3 | |
2254 | /* enum: Timed-out. */ | |
2255 | #define MC_CMD_POLL_BIST_TIMEOUT 0x4 | |
05a9320f BH |
2256 | #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 |
2257 | ||
2258 | /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ | |
2259 | #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 | |
f2b0befd | 2260 | /* result */ |
05a9320f BH |
2261 | /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ |
2262 | /* Enum values, see field(s): */ | |
2263 | /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ | |
2264 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 | |
2265 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 | |
2266 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 | |
2267 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 | |
f2b0befd | 2268 | /* Status of each channel A */ |
05a9320f | 2269 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 |
f2b0befd BH |
2270 | /* enum: Ok. */ |
2271 | #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 | |
2272 | /* enum: Open. */ | |
2273 | #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 | |
2274 | /* enum: Intra-pair short. */ | |
2275 | #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 | |
2276 | /* enum: Inter-pair short. */ | |
2277 | #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 | |
2278 | /* enum: Busy. */ | |
2279 | #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 | |
2280 | /* Status of each channel B */ | |
05a9320f BH |
2281 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 |
2282 | /* Enum values, see field(s): */ | |
2283 | /* CABLE_STATUS_A */ | |
f2b0befd | 2284 | /* Status of each channel C */ |
05a9320f BH |
2285 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 |
2286 | /* Enum values, see field(s): */ | |
2287 | /* CABLE_STATUS_A */ | |
f2b0befd | 2288 | /* Status of each channel D */ |
05a9320f BH |
2289 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 |
2290 | /* Enum values, see field(s): */ | |
2291 | /* CABLE_STATUS_A */ | |
2292 | ||
2293 | /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ | |
2294 | #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 | |
f2b0befd | 2295 | /* result */ |
05a9320f BH |
2296 | /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ |
2297 | /* Enum values, see field(s): */ | |
2298 | /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ | |
2299 | #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 | |
f2b0befd BH |
2300 | /* enum: Complete. */ |
2301 | #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 | |
2302 | /* enum: Bus switch off I2C write. */ | |
2303 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 | |
2304 | /* enum: Bus switch off I2C no access IO exp. */ | |
2305 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 | |
2306 | /* enum: Bus switch off I2C no access module. */ | |
2307 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 | |
2308 | /* enum: IO exp I2C configure. */ | |
2309 | #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 | |
2310 | /* enum: Bus switch I2C no cross talk. */ | |
2311 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 | |
2312 | /* enum: Module presence. */ | |
2313 | #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 | |
2314 | /* enum: Module ID I2C access. */ | |
2315 | #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 | |
2316 | /* enum: Module ID sane value. */ | |
2317 | #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 | |
2318 | ||
2319 | /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ | |
2320 | #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 | |
2321 | /* result */ | |
2322 | /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ | |
2323 | /* Enum values, see field(s): */ | |
2324 | /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ | |
2325 | #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 | |
2326 | /* enum: Test has completed. */ | |
2327 | #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 | |
2328 | /* enum: RAM test - walk ones. */ | |
2329 | #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 | |
2330 | /* enum: RAM test - walk zeros. */ | |
2331 | #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 | |
2332 | /* enum: RAM test - walking inversions zeros/ones. */ | |
2333 | #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 | |
2334 | /* enum: RAM test - walking inversions checkerboard. */ | |
2335 | #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 | |
2336 | /* enum: Register test - set / clear individual bits. */ | |
2337 | #define MC_CMD_POLL_BIST_MEM_REG 0x5 | |
2338 | /* enum: ECC error detected. */ | |
2339 | #define MC_CMD_POLL_BIST_MEM_ECC 0x6 | |
2340 | /* Failure address, only valid if result is POLL_BIST_FAILED */ | |
2341 | #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 | |
2342 | /* Bus or address space to which the failure address corresponds */ | |
2343 | #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 | |
2344 | /* enum: MC MIPS bus. */ | |
2345 | #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 | |
2346 | /* enum: CSR IREG bus. */ | |
2347 | #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 | |
2348 | /* enum: RX DPCPU bus. */ | |
2349 | #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 | |
2350 | /* enum: TX0 DPCPU bus. */ | |
2351 | #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 | |
2352 | /* enum: TX1 DPCPU bus. */ | |
2353 | #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 | |
2354 | /* enum: RX DICPU bus. */ | |
2355 | #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 | |
2356 | /* enum: TX DICPU bus. */ | |
2357 | #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 | |
2358 | /* Pattern written to RAM / register */ | |
2359 | #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 | |
2360 | /* Actual value read from RAM / register */ | |
2361 | #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 | |
2362 | /* ECC error mask */ | |
2363 | #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 | |
2364 | /* ECC parity error mask */ | |
2365 | #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 | |
2366 | /* ECC fatal error mask */ | |
2367 | #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 | |
05a9320f BH |
2368 | |
2369 | ||
2370 | /***********************************/ | |
2371 | /* MC_CMD_FLUSH_RX_QUEUES | |
f2b0befd BH |
2372 | * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ |
2373 | * flushes should be initiated via this MCDI operation, rather than via | |
2374 | * directly writing FLUSH_CMD. | |
2375 | * | |
2376 | * The flush is completed (either done/fail) asynchronously (after this command | |
2377 | * returns). The driver must still wait for flush done/failure events as usual. | |
05a9320f BH |
2378 | */ |
2379 | #define MC_CMD_FLUSH_RX_QUEUES 0x27 | |
2380 | ||
2381 | /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ | |
2382 | #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 | |
2383 | #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 | |
2384 | #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) | |
2385 | #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 | |
2386 | #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 | |
2387 | #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 | |
2388 | #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 | |
2389 | ||
2390 | /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ | |
2391 | #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 | |
2392 | ||
2393 | ||
2394 | /***********************************/ | |
2395 | /* MC_CMD_GET_LOOPBACK_MODES | |
f2b0befd | 2396 | * Returns a bitmask of loopback modes available at each speed. |
f0d37f42 SH |
2397 | */ |
2398 | #define MC_CMD_GET_LOOPBACK_MODES 0x28 | |
05a9320f | 2399 | |
75122ec8 SS |
2400 | #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
2401 | ||
05a9320f BH |
2402 | /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ |
2403 | #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 | |
2404 | ||
2405 | /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ | |
f2b0befd BH |
2406 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 |
2407 | /* Supported loopbacks. */ | |
05a9320f BH |
2408 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 |
2409 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 | |
2410 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 | |
2411 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 | |
f2b0befd BH |
2412 | /* enum: None. */ |
2413 | #define MC_CMD_LOOPBACK_NONE 0x0 | |
2414 | /* enum: Data. */ | |
2415 | #define MC_CMD_LOOPBACK_DATA 0x1 | |
2416 | /* enum: GMAC. */ | |
2417 | #define MC_CMD_LOOPBACK_GMAC 0x2 | |
2418 | /* enum: XGMII. */ | |
2419 | #define MC_CMD_LOOPBACK_XGMII 0x3 | |
2420 | /* enum: XGXS. */ | |
2421 | #define MC_CMD_LOOPBACK_XGXS 0x4 | |
2422 | /* enum: XAUI. */ | |
2423 | #define MC_CMD_LOOPBACK_XAUI 0x5 | |
2424 | /* enum: GMII. */ | |
2425 | #define MC_CMD_LOOPBACK_GMII 0x6 | |
2426 | /* enum: SGMII. */ | |
2427 | #define MC_CMD_LOOPBACK_SGMII 0x7 | |
2428 | /* enum: XGBR. */ | |
2429 | #define MC_CMD_LOOPBACK_XGBR 0x8 | |
2430 | /* enum: XFI. */ | |
2431 | #define MC_CMD_LOOPBACK_XFI 0x9 | |
2432 | /* enum: XAUI Far. */ | |
2433 | #define MC_CMD_LOOPBACK_XAUI_FAR 0xa | |
2434 | /* enum: GMII Far. */ | |
2435 | #define MC_CMD_LOOPBACK_GMII_FAR 0xb | |
2436 | /* enum: SGMII Far. */ | |
2437 | #define MC_CMD_LOOPBACK_SGMII_FAR 0xc | |
2438 | /* enum: XFI Far. */ | |
2439 | #define MC_CMD_LOOPBACK_XFI_FAR 0xd | |
2440 | /* enum: GPhy. */ | |
2441 | #define MC_CMD_LOOPBACK_GPHY 0xe | |
2442 | /* enum: PhyXS. */ | |
2443 | #define MC_CMD_LOOPBACK_PHYXS 0xf | |
2444 | /* enum: PCS. */ | |
2445 | #define MC_CMD_LOOPBACK_PCS 0x10 | |
2446 | /* enum: PMA-PMD. */ | |
2447 | #define MC_CMD_LOOPBACK_PMAPMD 0x11 | |
2448 | /* enum: Cross-Port. */ | |
2449 | #define MC_CMD_LOOPBACK_XPORT 0x12 | |
2450 | /* enum: XGMII-Wireside. */ | |
2451 | #define MC_CMD_LOOPBACK_XGMII_WS 0x13 | |
2452 | /* enum: XAUI Wireside. */ | |
2453 | #define MC_CMD_LOOPBACK_XAUI_WS 0x14 | |
2454 | /* enum: XAUI Wireside Far. */ | |
2455 | #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 | |
2456 | /* enum: XAUI Wireside near. */ | |
2457 | #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 | |
2458 | /* enum: GMII Wireside. */ | |
2459 | #define MC_CMD_LOOPBACK_GMII_WS 0x17 | |
2460 | /* enum: XFI Wireside. */ | |
2461 | #define MC_CMD_LOOPBACK_XFI_WS 0x18 | |
2462 | /* enum: XFI Wireside Far. */ | |
2463 | #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 | |
2464 | /* enum: PhyXS Wireside. */ | |
2465 | #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a | |
2466 | /* enum: PMA lanes MAC-Serdes. */ | |
2467 | #define MC_CMD_LOOPBACK_PMA_INT 0x1b | |
2468 | /* enum: KR Serdes Parallel (Encoder). */ | |
2469 | #define MC_CMD_LOOPBACK_SD_NEAR 0x1c | |
2470 | /* enum: KR Serdes Serial. */ | |
2471 | #define MC_CMD_LOOPBACK_SD_FAR 0x1d | |
2472 | /* enum: PMA lanes MAC-Serdes Wireside. */ | |
2473 | #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e | |
2474 | /* enum: KR Serdes Parallel Wireside (Full PCS). */ | |
2475 | #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f | |
2476 | /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ | |
2477 | #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 | |
2478 | /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ | |
2479 | #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 | |
2480 | /* enum: KR Serdes Serial Wireside. */ | |
2481 | #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 | |
512bb06c BH |
2482 | /* enum: Near side of AOE Siena side port */ |
2483 | #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 | |
f2b0befd | 2484 | /* Supported loopbacks. */ |
05a9320f BH |
2485 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 |
2486 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 | |
2487 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 | |
2488 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 | |
2489 | /* Enum values, see field(s): */ | |
2490 | /* 100M */ | |
f2b0befd | 2491 | /* Supported loopbacks. */ |
05a9320f BH |
2492 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 |
2493 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 | |
2494 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 | |
2495 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 | |
2496 | /* Enum values, see field(s): */ | |
2497 | /* 100M */ | |
f2b0befd | 2498 | /* Supported loopbacks. */ |
05a9320f BH |
2499 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 |
2500 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 | |
2501 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 | |
2502 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 | |
2503 | /* Enum values, see field(s): */ | |
2504 | /* 100M */ | |
f2b0befd BH |
2505 | /* Supported loopbacks. */ |
2506 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 | |
2507 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 | |
2508 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 | |
2509 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 | |
2510 | /* Enum values, see field(s): */ | |
2511 | /* 100M */ | |
05a9320f BH |
2512 | |
2513 | ||
2514 | /***********************************/ | |
2515 | /* MC_CMD_GET_LINK | |
f2b0befd BH |
2516 | * Read the unified MAC/PHY link state. Locks required: None Return code: 0, |
2517 | * ETIME. | |
f0d37f42 SH |
2518 | */ |
2519 | #define MC_CMD_GET_LINK 0x29 | |
05a9320f | 2520 | |
75122ec8 SS |
2521 | #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
2522 | ||
05a9320f BH |
2523 | /* MC_CMD_GET_LINK_IN msgrequest */ |
2524 | #define MC_CMD_GET_LINK_IN_LEN 0 | |
2525 | ||
2526 | /* MC_CMD_GET_LINK_OUT msgresponse */ | |
2527 | #define MC_CMD_GET_LINK_OUT_LEN 28 | |
f2b0befd | 2528 | /* near-side advertised capabilities */ |
05a9320f | 2529 | #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 |
f2b0befd | 2530 | /* link-partner advertised capabilities */ |
05a9320f | 2531 | #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 |
f2b0befd BH |
2532 | /* Autonegotiated speed in mbit/s. The link may still be down even if this |
2533 | * reads non-zero. | |
2534 | */ | |
05a9320f | 2535 | #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 |
f2b0befd | 2536 | /* Current loopback setting. */ |
05a9320f BH |
2537 | #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 |
2538 | /* Enum values, see field(s): */ | |
2539 | /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ | |
2540 | #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 | |
2541 | #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 | |
2542 | #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 | |
2543 | #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 | |
2544 | #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 | |
2545 | #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 | |
2546 | #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 | |
2547 | #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 | |
2548 | #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 | |
512bb06c BH |
2549 | #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 |
2550 | #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 | |
2551 | #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 | |
2552 | #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 | |
f2b0befd | 2553 | /* This returns the negotiated flow control value. */ |
05a9320f | 2554 | #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 |
f2b0befd BH |
2555 | /* enum: Flow control is off. */ |
2556 | #define MC_CMD_FCNTL_OFF 0x0 | |
2557 | /* enum: Respond to flow control. */ | |
2558 | #define MC_CMD_FCNTL_RESPOND 0x1 | |
2559 | /* enum: Respond to and Issue flow control. */ | |
2560 | #define MC_CMD_FCNTL_BIDIR 0x2 | |
05a9320f BH |
2561 | #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 |
2562 | #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 | |
2563 | #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 | |
2564 | #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 | |
2565 | #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 | |
2566 | #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 | |
2567 | #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 | |
2568 | #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 | |
2569 | #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 | |
2570 | ||
2571 | ||
2572 | /***********************************/ | |
2573 | /* MC_CMD_SET_LINK | |
f2b0befd BH |
2574 | * Write the unified MAC/PHY link configuration. Locks required: None. Return |
2575 | * code: 0, EINVAL, ETIME | |
f0d37f42 SH |
2576 | */ |
2577 | #define MC_CMD_SET_LINK 0x2a | |
05a9320f | 2578 | |
75122ec8 SS |
2579 | #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK |
2580 | ||
05a9320f BH |
2581 | /* MC_CMD_SET_LINK_IN msgrequest */ |
2582 | #define MC_CMD_SET_LINK_IN_LEN 16 | |
f2b0befd | 2583 | /* ??? */ |
05a9320f | 2584 | #define MC_CMD_SET_LINK_IN_CAP_OFST 0 |
f2b0befd | 2585 | /* Flags */ |
05a9320f BH |
2586 | #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 |
2587 | #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 | |
2588 | #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 | |
2589 | #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 | |
2590 | #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 | |
2591 | #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 | |
2592 | #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 | |
f2b0befd | 2593 | /* Loopback mode. */ |
05a9320f BH |
2594 | #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 |
2595 | /* Enum values, see field(s): */ | |
2596 | /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ | |
f2b0befd BH |
2597 | /* A loopback speed of "0" is supported, and means (choose any available |
2598 | * speed). | |
2599 | */ | |
05a9320f BH |
2600 | #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 |
2601 | ||
2602 | /* MC_CMD_SET_LINK_OUT msgresponse */ | |
2603 | #define MC_CMD_SET_LINK_OUT_LEN 0 | |
2604 | ||
2605 | ||
2606 | /***********************************/ | |
2607 | /* MC_CMD_SET_ID_LED | |
f2b0befd | 2608 | * Set identification LED state. Locks required: None. Return code: 0, EINVAL |
f0d37f42 SH |
2609 | */ |
2610 | #define MC_CMD_SET_ID_LED 0x2b | |
05a9320f | 2611 | |
75122ec8 SS |
2612 | #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK |
2613 | ||
05a9320f BH |
2614 | /* MC_CMD_SET_ID_LED_IN msgrequest */ |
2615 | #define MC_CMD_SET_ID_LED_IN_LEN 4 | |
f2b0befd | 2616 | /* Set LED state. */ |
05a9320f BH |
2617 | #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 |
2618 | #define MC_CMD_LED_OFF 0x0 /* enum */ | |
2619 | #define MC_CMD_LED_ON 0x1 /* enum */ | |
2620 | #define MC_CMD_LED_DEFAULT 0x2 /* enum */ | |
2621 | ||
2622 | /* MC_CMD_SET_ID_LED_OUT msgresponse */ | |
2623 | #define MC_CMD_SET_ID_LED_OUT_LEN 0 | |
2624 | ||
2625 | ||
2626 | /***********************************/ | |
2627 | /* MC_CMD_SET_MAC | |
f2b0befd | 2628 | * Set MAC configuration. Locks required: None. Return code: 0, EINVAL |
f0d37f42 SH |
2629 | */ |
2630 | #define MC_CMD_SET_MAC 0x2c | |
05a9320f | 2631 | |
75122ec8 SS |
2632 | #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_LINK |
2633 | ||
05a9320f BH |
2634 | /* MC_CMD_SET_MAC_IN msgrequest */ |
2635 | #define MC_CMD_SET_MAC_IN_LEN 24 | |
f2b0befd BH |
2636 | /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of |
2637 | * EtherII, VLAN, bug16011 padding). | |
2638 | */ | |
05a9320f BH |
2639 | #define MC_CMD_SET_MAC_IN_MTU_OFST 0 |
2640 | #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 | |
2641 | #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 | |
2642 | #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 | |
2643 | #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 | |
2644 | #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 | |
2645 | #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 | |
2646 | #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 | |
2647 | #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 | |
2648 | #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 | |
2649 | #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 | |
2650 | #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 | |
f2b0befd | 2651 | /* enum: Flow control is off. */ |
05a9320f | 2652 | /* MC_CMD_FCNTL_OFF 0x0 */ |
f2b0befd | 2653 | /* enum: Respond to flow control. */ |
05a9320f | 2654 | /* MC_CMD_FCNTL_RESPOND 0x1 */ |
f2b0befd | 2655 | /* enum: Respond to and Issue flow control. */ |
05a9320f | 2656 | /* MC_CMD_FCNTL_BIDIR 0x2 */ |
f2b0befd BH |
2657 | /* enum: Auto neg flow control. */ |
2658 | #define MC_CMD_FCNTL_AUTO 0x3 | |
05a9320f BH |
2659 | |
2660 | /* MC_CMD_SET_MAC_OUT msgresponse */ | |
2661 | #define MC_CMD_SET_MAC_OUT_LEN 0 | |
2662 | ||
2663 | ||
2664 | /***********************************/ | |
2665 | /* MC_CMD_PHY_STATS | |
f2b0befd BH |
2666 | * Get generic PHY statistics. This call returns the statistics for a generic |
2667 | * PHY in a sparse array (indexed by the enumerate). Each value is represented | |
2668 | * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the | |
2669 | * statistics may be read from the message response. If DMA_ADDR != 0, then the | |
2670 | * statistics are dmad to that (page-aligned location). Locks required: None. | |
2671 | * Returns: 0, ETIME | |
f0d37f42 SH |
2672 | */ |
2673 | #define MC_CMD_PHY_STATS 0x2d | |
f0d37f42 | 2674 | |
75122ec8 SS |
2675 | #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK |
2676 | ||
05a9320f BH |
2677 | /* MC_CMD_PHY_STATS_IN msgrequest */ |
2678 | #define MC_CMD_PHY_STATS_IN_LEN 8 | |
f2b0befd | 2679 | /* ??? */ |
05a9320f BH |
2680 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 |
2681 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 | |
2682 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 | |
2683 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 | |
2684 | ||
2685 | /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ | |
2686 | #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 | |
2687 | ||
2688 | /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ | |
2689 | #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) | |
2690 | #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 | |
2691 | #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 | |
2692 | #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS | |
f2b0befd BH |
2693 | /* enum: OUI. */ |
2694 | #define MC_CMD_OUI 0x0 | |
2695 | /* enum: PMA-PMD Link Up. */ | |
2696 | #define MC_CMD_PMA_PMD_LINK_UP 0x1 | |
2697 | /* enum: PMA-PMD RX Fault. */ | |
2698 | #define MC_CMD_PMA_PMD_RX_FAULT 0x2 | |
2699 | /* enum: PMA-PMD TX Fault. */ | |
2700 | #define MC_CMD_PMA_PMD_TX_FAULT 0x3 | |
2701 | /* enum: PMA-PMD Signal */ | |
2702 | #define MC_CMD_PMA_PMD_SIGNAL 0x4 | |
2703 | /* enum: PMA-PMD SNR A. */ | |
2704 | #define MC_CMD_PMA_PMD_SNR_A 0x5 | |
2705 | /* enum: PMA-PMD SNR B. */ | |
2706 | #define MC_CMD_PMA_PMD_SNR_B 0x6 | |
2707 | /* enum: PMA-PMD SNR C. */ | |
2708 | #define MC_CMD_PMA_PMD_SNR_C 0x7 | |
2709 | /* enum: PMA-PMD SNR D. */ | |
2710 | #define MC_CMD_PMA_PMD_SNR_D 0x8 | |
2711 | /* enum: PCS Link Up. */ | |
2712 | #define MC_CMD_PCS_LINK_UP 0x9 | |
2713 | /* enum: PCS RX Fault. */ | |
2714 | #define MC_CMD_PCS_RX_FAULT 0xa | |
2715 | /* enum: PCS TX Fault. */ | |
2716 | #define MC_CMD_PCS_TX_FAULT 0xb | |
2717 | /* enum: PCS BER. */ | |
2718 | #define MC_CMD_PCS_BER 0xc | |
2719 | /* enum: PCS Block Errors. */ | |
2720 | #define MC_CMD_PCS_BLOCK_ERRORS 0xd | |
2721 | /* enum: PhyXS Link Up. */ | |
2722 | #define MC_CMD_PHYXS_LINK_UP 0xe | |
2723 | /* enum: PhyXS RX Fault. */ | |
2724 | #define MC_CMD_PHYXS_RX_FAULT 0xf | |
2725 | /* enum: PhyXS TX Fault. */ | |
2726 | #define MC_CMD_PHYXS_TX_FAULT 0x10 | |
2727 | /* enum: PhyXS Align. */ | |
2728 | #define MC_CMD_PHYXS_ALIGN 0x11 | |
2729 | /* enum: PhyXS Sync. */ | |
2730 | #define MC_CMD_PHYXS_SYNC 0x12 | |
2731 | /* enum: AN link-up. */ | |
2732 | #define MC_CMD_AN_LINK_UP 0x13 | |
2733 | /* enum: AN Complete. */ | |
2734 | #define MC_CMD_AN_COMPLETE 0x14 | |
2735 | /* enum: AN 10GBaseT Status. */ | |
2736 | #define MC_CMD_AN_10GBT_STATUS 0x15 | |
2737 | /* enum: Clause 22 Link-Up. */ | |
2738 | #define MC_CMD_CL22_LINK_UP 0x16 | |
2739 | /* enum: (Last entry) */ | |
2740 | #define MC_CMD_PHY_NSTATS 0x17 | |
05a9320f BH |
2741 | |
2742 | ||
2743 | /***********************************/ | |
2744 | /* MC_CMD_MAC_STATS | |
f2b0befd BH |
2745 | * Get generic MAC statistics. This call returns unified statistics maintained |
2746 | * by the MC as it switches between the GMAC and XMAC. The MC will write out | |
2747 | * all supported stats. The driver should zero initialise the buffer to | |
2748 | * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is | |
2749 | * performed, and the statistics may be read from the message response. If | |
2750 | * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). | |
2751 | * Locks required: None. Returns: 0, ETIME | |
f0d37f42 | 2752 | */ |
05a9320f | 2753 | #define MC_CMD_MAC_STATS 0x2e |
f0d37f42 | 2754 | |
75122ec8 SS |
2755 | #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
2756 | ||
05a9320f BH |
2757 | /* MC_CMD_MAC_STATS_IN msgrequest */ |
2758 | #define MC_CMD_MAC_STATS_IN_LEN 16 | |
f2b0befd | 2759 | /* ??? */ |
05a9320f BH |
2760 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 |
2761 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 | |
2762 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 | |
2763 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 | |
2764 | #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 | |
2765 | #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 | |
2766 | #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 | |
2767 | #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 | |
2768 | #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 | |
2769 | #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 | |
2770 | #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 | |
2771 | #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 | |
2772 | #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 | |
2773 | #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 | |
2774 | #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 | |
2775 | #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 | |
2776 | #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 | |
2777 | #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 | |
2778 | #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 | |
2779 | #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 | |
2780 | ||
2781 | /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ | |
2782 | #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 | |
2783 | ||
2784 | /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ | |
2785 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) | |
2786 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 | |
2787 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 | |
2788 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 | |
2789 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 | |
2790 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS | |
2791 | #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ | |
2792 | #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ | |
2793 | #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ | |
2794 | #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ | |
2795 | #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ | |
2796 | #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ | |
2797 | #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ | |
2798 | #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ | |
2799 | #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ | |
2800 | #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ | |
2801 | #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ | |
2802 | #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ | |
2803 | #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ | |
2804 | #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ | |
2805 | #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ | |
2806 | #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ | |
2807 | #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ | |
2808 | #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ | |
2809 | #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ | |
2810 | #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ | |
2811 | #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ | |
2812 | #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ | |
2813 | #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ | |
2814 | #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ | |
2815 | #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ | |
2816 | #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ | |
2817 | #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ | |
2818 | #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ | |
2819 | #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ | |
2820 | #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ | |
2821 | #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ | |
2822 | #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ | |
2823 | #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ | |
2824 | #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ | |
2825 | #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ | |
2826 | #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ | |
2827 | #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ | |
2828 | #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ | |
2829 | #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ | |
2830 | #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ | |
2831 | #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ | |
2832 | #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ | |
2833 | #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ | |
2834 | #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ | |
2835 | #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ | |
2836 | #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ | |
2837 | #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ | |
2838 | #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ | |
2839 | #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ | |
2840 | #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ | |
2841 | #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ | |
2842 | #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ | |
2843 | #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ | |
2844 | #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ | |
2845 | #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ | |
2846 | #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ | |
2847 | #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ | |
2848 | #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ | |
2849 | #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ | |
2850 | #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ | |
2ca10a75 MS |
2851 | /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS |
2852 | * capability only. | |
2853 | */ | |
2854 | #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c | |
2855 | /* enum: PM discard_bb_overflow counter. Valid for EF10 with | |
2856 | * PM_AND_RXDP_COUNTERS capability only. | |
2857 | */ | |
2858 | #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d | |
2859 | /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS | |
2860 | * capability only. | |
2861 | */ | |
2862 | #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e | |
2863 | /* enum: PM discard_vfifo_full counter. Valid for EF10 with | |
2864 | * PM_AND_RXDP_COUNTERS capability only. | |
2865 | */ | |
2866 | #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f | |
2867 | /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS | |
2868 | * capability only. | |
2869 | */ | |
2870 | #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 | |
2871 | /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS | |
2872 | * capability only. | |
2873 | */ | |
2874 | #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 | |
2875 | /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS | |
2876 | * capability only. | |
2877 | */ | |
2878 | #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 | |
2879 | /* enum: RXDP counter: Number of packets dropped due to the queue being | |
2880 | * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. | |
2881 | */ | |
2882 | #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 | |
2883 | /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 | |
2884 | * with PM_AND_RXDP_COUNTERS capability only. | |
2885 | */ | |
2886 | #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 | |
2887 | /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with | |
2888 | * PM_AND_RXDP_COUNTERS capability only. | |
2889 | */ | |
2890 | #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 | |
2891 | /* enum: RXDP counter: Number of times an emergency descriptor fetch was | |
2892 | * performed. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. | |
2893 | */ | |
e80ca013 | 2894 | #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 |
2ca10a75 MS |
2895 | /* enum: RXDP counter: Number of times the DPCPU waited for an existing |
2896 | * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. | |
2897 | */ | |
e80ca013 | 2898 | #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 |
2ca10a75 MS |
2899 | /* enum: Start of GMAC stats buffer space, for Siena only. */ |
2900 | #define MC_CMD_GMAC_DMABUF_START 0x40 | |
2901 | /* enum: End of GMAC stats buffer space, for Siena only. */ | |
2902 | #define MC_CMD_GMAC_DMABUF_END 0x5f | |
05a9320f BH |
2903 | #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ |
2904 | #define MC_CMD_MAC_NSTATS 0x61 /* enum */ | |
2905 | ||
2906 | ||
2907 | /***********************************/ | |
2908 | /* MC_CMD_SRIOV | |
2909 | * to be documented | |
2910 | */ | |
2911 | #define MC_CMD_SRIOV 0x30 | |
2912 | ||
2913 | /* MC_CMD_SRIOV_IN msgrequest */ | |
2914 | #define MC_CMD_SRIOV_IN_LEN 12 | |
2915 | #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 | |
2916 | #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 | |
2917 | #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 | |
2918 | ||
2919 | /* MC_CMD_SRIOV_OUT msgresponse */ | |
2920 | #define MC_CMD_SRIOV_OUT_LEN 8 | |
2921 | #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 | |
2922 | #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 | |
2923 | ||
2924 | /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ | |
2925 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 | |
f2b0befd | 2926 | /* this is only used for the first record */ |
05a9320f BH |
2927 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 |
2928 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 | |
2929 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 | |
2930 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 | |
2931 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 | |
2932 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 | |
2933 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 | |
2934 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 | |
2935 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 | |
2936 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 | |
2937 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 | |
2938 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 | |
2939 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 | |
2940 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ | |
2941 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 | |
2942 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 | |
2943 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 | |
2944 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 | |
2945 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 | |
2946 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 | |
2947 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 | |
2948 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 | |
2949 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 | |
2950 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 | |
2951 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 | |
2952 | ||
2953 | ||
2954 | /***********************************/ | |
2955 | /* MC_CMD_MEMCPY | |
f2b0befd BH |
2956 | * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data |
2957 | * embedded directly in the command. | |
2958 | * | |
2959 | * A common pattern is for a client to use generation counts to signal a dma | |
2960 | * update of a datastructure. To facilitate this, this MCDI operation can | |
2961 | * contain multiple requests which are executed in strict order. Requests take | |
2962 | * the form of duplicating the entire MCDI request continuously (including the | |
2963 | * requests record, which is ignored in all but the first structure) | |
2964 | * | |
2965 | * The source data can either come from a DMA from the host, or it can be | |
2966 | * embedded within the request directly, thereby eliminating a DMA read. To | |
2967 | * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and | |
2968 | * ADDR_LO=offset, and inserts the data at %offset from the start of the | |
2969 | * payload. It's the callers responsibility to ensure that the embedded data | |
2970 | * doesn't overlap the records. | |
2971 | * | |
2972 | * Returns: 0, EINVAL (invalid RID) | |
05a9320f BH |
2973 | */ |
2974 | #define MC_CMD_MEMCPY 0x31 | |
2975 | ||
2976 | /* MC_CMD_MEMCPY_IN msgrequest */ | |
2977 | #define MC_CMD_MEMCPY_IN_LENMIN 32 | |
2978 | #define MC_CMD_MEMCPY_IN_LENMAX 224 | |
2979 | #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) | |
f2b0befd | 2980 | /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ |
05a9320f BH |
2981 | #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 |
2982 | #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 | |
2983 | #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 | |
2984 | #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 | |
2985 | ||
2986 | /* MC_CMD_MEMCPY_OUT msgresponse */ | |
2987 | #define MC_CMD_MEMCPY_OUT_LEN 0 | |
2988 | ||
2989 | ||
2990 | /***********************************/ | |
2991 | /* MC_CMD_WOL_FILTER_SET | |
2992 | * Set a WoL filter. | |
f0d37f42 SH |
2993 | */ |
2994 | #define MC_CMD_WOL_FILTER_SET 0x32 | |
05a9320f | 2995 | |
75122ec8 SS |
2996 | #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK |
2997 | ||
05a9320f BH |
2998 | /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ |
2999 | #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 | |
3000 | #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 | |
3001 | #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ | |
3002 | #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ | |
f2b0befd | 3003 | /* A type value of 1 is unused. */ |
05a9320f | 3004 | #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 |
f2b0befd BH |
3005 | /* enum: Magic */ |
3006 | #define MC_CMD_WOL_TYPE_MAGIC 0x0 | |
3007 | /* enum: MS Windows Magic */ | |
3008 | #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 | |
3009 | /* enum: IPv4 Syn */ | |
3010 | #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 | |
3011 | /* enum: IPv6 Syn */ | |
3012 | #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 | |
3013 | /* enum: Bitmap */ | |
3014 | #define MC_CMD_WOL_TYPE_BITMAP 0x5 | |
3015 | /* enum: Link */ | |
3016 | #define MC_CMD_WOL_TYPE_LINK 0x6 | |
3017 | /* enum: (Above this for future use) */ | |
3018 | #define MC_CMD_WOL_TYPE_MAX 0x7 | |
05a9320f BH |
3019 | #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 |
3020 | #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 | |
3021 | #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 | |
3022 | ||
3023 | /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ | |
3024 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 | |
3025 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
3026 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
3027 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 | |
3028 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 | |
3029 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 | |
3030 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 | |
3031 | ||
3032 | /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ | |
3033 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 | |
3034 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
3035 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
3036 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 | |
3037 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 | |
3038 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 | |
3039 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 | |
3040 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 | |
3041 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 | |
3042 | ||
3043 | /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ | |
3044 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 | |
3045 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
3046 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
3047 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 | |
3048 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 | |
3049 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 | |
3050 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 | |
3051 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 | |
3052 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 | |
3053 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 | |
3054 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 | |
3055 | ||
3056 | /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ | |
3057 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 | |
3058 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
3059 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
3060 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 | |
3061 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 | |
3062 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 | |
3063 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 | |
3064 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 | |
3065 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 | |
3066 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 | |
3067 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 | |
3068 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 | |
3069 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 | |
3070 | ||
3071 | /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ | |
3072 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 | |
3073 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
3074 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
3075 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 | |
3076 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 | |
3077 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 | |
3078 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 | |
3079 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 | |
3080 | ||
3081 | /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ | |
3082 | #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 | |
3083 | #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 | |
3084 | ||
3085 | ||
3086 | /***********************************/ | |
3087 | /* MC_CMD_WOL_FILTER_REMOVE | |
f2b0befd | 3088 | * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS |
f0d37f42 SH |
3089 | */ |
3090 | #define MC_CMD_WOL_FILTER_REMOVE 0x33 | |
f0d37f42 | 3091 | |
75122ec8 SS |
3092 | #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK |
3093 | ||
05a9320f BH |
3094 | /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ |
3095 | #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 | |
3096 | #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 | |
f0d37f42 | 3097 | |
05a9320f BH |
3098 | /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ |
3099 | #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 | |
3100 | ||
3101 | ||
3102 | /***********************************/ | |
3103 | /* MC_CMD_WOL_FILTER_RESET | |
f2b0befd BH |
3104 | * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, |
3105 | * ENOSYS | |
f0d37f42 SH |
3106 | */ |
3107 | #define MC_CMD_WOL_FILTER_RESET 0x34 | |
f0d37f42 | 3108 | |
75122ec8 SS |
3109 | #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK |
3110 | ||
05a9320f BH |
3111 | /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ |
3112 | #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 | |
3113 | #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 | |
3114 | #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ | |
3115 | #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ | |
3116 | ||
3117 | /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ | |
3118 | #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 | |
3119 | ||
3120 | ||
3121 | /***********************************/ | |
3122 | /* MC_CMD_SET_MCAST_HASH | |
f2b0befd | 3123 | * Set the MCAST hash value without otherwise reconfiguring the MAC |
f0d37f42 SH |
3124 | */ |
3125 | #define MC_CMD_SET_MCAST_HASH 0x35 | |
f0d37f42 | 3126 | |
05a9320f BH |
3127 | /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ |
3128 | #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 | |
3129 | #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 | |
3130 | #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 | |
3131 | #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 | |
3132 | #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 | |
3133 | ||
3134 | /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ | |
3135 | #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 | |
3136 | ||
3137 | ||
3138 | /***********************************/ | |
3139 | /* MC_CMD_NVRAM_TYPES | |
f2b0befd BH |
3140 | * Return bitfield indicating available types of virtual NVRAM partitions. |
3141 | * Locks required: none. Returns: 0 | |
f0d37f42 SH |
3142 | */ |
3143 | #define MC_CMD_NVRAM_TYPES 0x36 | |
05a9320f | 3144 | |
75122ec8 SS |
3145 | #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3146 | ||
05a9320f BH |
3147 | /* MC_CMD_NVRAM_TYPES_IN msgrequest */ |
3148 | #define MC_CMD_NVRAM_TYPES_IN_LEN 0 | |
3149 | ||
3150 | /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ | |
3151 | #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 | |
f2b0befd | 3152 | /* Bit mask of supported types. */ |
05a9320f | 3153 | #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 |
f2b0befd BH |
3154 | /* enum: Disabled callisto. */ |
3155 | #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 | |
3156 | /* enum: MC firmware. */ | |
3157 | #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 | |
3158 | /* enum: MC backup firmware. */ | |
3159 | #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 | |
3160 | /* enum: Static configuration Port0. */ | |
3161 | #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 | |
3162 | /* enum: Static configuration Port1. */ | |
3163 | #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 | |
3164 | /* enum: Dynamic configuration Port0. */ | |
3165 | #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 | |
3166 | /* enum: Dynamic configuration Port1. */ | |
3167 | #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 | |
3168 | /* enum: Expansion Rom. */ | |
3169 | #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 | |
3170 | /* enum: Expansion Rom Configuration Port0. */ | |
3171 | #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 | |
3172 | /* enum: Expansion Rom Configuration Port1. */ | |
3173 | #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 | |
3174 | /* enum: Phy Configuration Port0. */ | |
3175 | #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa | |
3176 | /* enum: Phy Configuration Port1. */ | |
3177 | #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb | |
3178 | /* enum: Log. */ | |
3179 | #define MC_CMD_NVRAM_TYPE_LOG 0xc | |
3180 | /* enum: FPGA image. */ | |
3181 | #define MC_CMD_NVRAM_TYPE_FPGA 0xd | |
3182 | /* enum: FPGA backup image */ | |
3183 | #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe | |
3184 | /* enum: FC firmware. */ | |
3185 | #define MC_CMD_NVRAM_TYPE_FC_FW 0xf | |
3186 | /* enum: FC backup firmware. */ | |
3187 | #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 | |
3188 | /* enum: CPLD image. */ | |
3189 | #define MC_CMD_NVRAM_TYPE_CPLD 0x11 | |
3190 | /* enum: Licensing information. */ | |
3191 | #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 | |
3192 | /* enum: FC Log. */ | |
3193 | #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 | |
05a9320f BH |
3194 | |
3195 | ||
3196 | /***********************************/ | |
3197 | /* MC_CMD_NVRAM_INFO | |
f2b0befd BH |
3198 | * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, |
3199 | * EINVAL (bad type). | |
f0d37f42 SH |
3200 | */ |
3201 | #define MC_CMD_NVRAM_INFO 0x37 | |
05a9320f | 3202 | |
75122ec8 SS |
3203 | #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3204 | ||
05a9320f BH |
3205 | /* MC_CMD_NVRAM_INFO_IN msgrequest */ |
3206 | #define MC_CMD_NVRAM_INFO_IN_LEN 4 | |
3207 | #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 | |
3208 | /* Enum values, see field(s): */ | |
3209 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3210 | ||
3211 | /* MC_CMD_NVRAM_INFO_OUT msgresponse */ | |
3212 | #define MC_CMD_NVRAM_INFO_OUT_LEN 24 | |
3213 | #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 | |
3214 | /* Enum values, see field(s): */ | |
3215 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3216 | #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 | |
3217 | #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 | |
3218 | #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 | |
3219 | #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 | |
3220 | #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 | |
f2b0befd BH |
3221 | #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 |
3222 | #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 | |
3223 | #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 | |
3224 | #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 | |
05a9320f BH |
3225 | #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 |
3226 | #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 | |
3227 | ||
3228 | ||
3229 | /***********************************/ | |
3230 | /* MC_CMD_NVRAM_UPDATE_START | |
f2b0befd BH |
3231 | * Start a group of update operations on a virtual NVRAM partition. Locks |
3232 | * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if | |
3233 | * PHY_LOCK required and not held). | |
f0d37f42 SH |
3234 | */ |
3235 | #define MC_CMD_NVRAM_UPDATE_START 0x38 | |
f0d37f42 | 3236 | |
75122ec8 SS |
3237 | #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3238 | ||
05a9320f BH |
3239 | /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ |
3240 | #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 | |
3241 | #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 | |
3242 | /* Enum values, see field(s): */ | |
3243 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3244 | ||
3245 | /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ | |
3246 | #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 | |
3247 | ||
3248 | ||
3249 | /***********************************/ | |
3250 | /* MC_CMD_NVRAM_READ | |
f2b0befd BH |
3251 | * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if |
3252 | * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if | |
3253 | * PHY_LOCK required and not held) | |
f0d37f42 SH |
3254 | */ |
3255 | #define MC_CMD_NVRAM_READ 0x39 | |
05a9320f | 3256 | |
75122ec8 SS |
3257 | #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3258 | ||
05a9320f BH |
3259 | /* MC_CMD_NVRAM_READ_IN msgrequest */ |
3260 | #define MC_CMD_NVRAM_READ_IN_LEN 12 | |
3261 | #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 | |
3262 | /* Enum values, see field(s): */ | |
3263 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3264 | #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 | |
f2b0befd | 3265 | /* amount to read in bytes */ |
05a9320f BH |
3266 | #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 |
3267 | ||
3268 | /* MC_CMD_NVRAM_READ_OUT msgresponse */ | |
3269 | #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 | |
576eda8b | 3270 | #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 |
05a9320f BH |
3271 | #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) |
3272 | #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 | |
3273 | #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 | |
3274 | #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 | |
576eda8b | 3275 | #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 |
05a9320f BH |
3276 | |
3277 | ||
3278 | /***********************************/ | |
3279 | /* MC_CMD_NVRAM_WRITE | |
f2b0befd BH |
3280 | * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if |
3281 | * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if | |
3282 | * PHY_LOCK required and not held) | |
f0d37f42 SH |
3283 | */ |
3284 | #define MC_CMD_NVRAM_WRITE 0x3a | |
05a9320f | 3285 | |
75122ec8 SS |
3286 | #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3287 | ||
05a9320f BH |
3288 | /* MC_CMD_NVRAM_WRITE_IN msgrequest */ |
3289 | #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 | |
576eda8b | 3290 | #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 |
05a9320f BH |
3291 | #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) |
3292 | #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 | |
3293 | /* Enum values, see field(s): */ | |
3294 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3295 | #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 | |
3296 | #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 | |
3297 | #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 | |
3298 | #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 | |
3299 | #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 | |
576eda8b | 3300 | #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 |
05a9320f BH |
3301 | |
3302 | /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ | |
3303 | #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 | |
3304 | ||
3305 | ||
3306 | /***********************************/ | |
3307 | /* MC_CMD_NVRAM_ERASE | |
f2b0befd BH |
3308 | * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if |
3309 | * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if | |
3310 | * PHY_LOCK required and not held) | |
f0d37f42 SH |
3311 | */ |
3312 | #define MC_CMD_NVRAM_ERASE 0x3b | |
05a9320f | 3313 | |
75122ec8 SS |
3314 | #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3315 | ||
05a9320f BH |
3316 | /* MC_CMD_NVRAM_ERASE_IN msgrequest */ |
3317 | #define MC_CMD_NVRAM_ERASE_IN_LEN 12 | |
3318 | #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 | |
3319 | /* Enum values, see field(s): */ | |
3320 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3321 | #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 | |
3322 | #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 | |
3323 | ||
3324 | /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ | |
3325 | #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 | |
3326 | ||
3327 | ||
3328 | /***********************************/ | |
3329 | /* MC_CMD_NVRAM_UPDATE_FINISH | |
f2b0befd BH |
3330 | * Finish a group of update operations on a virtual NVRAM partition. Locks |
3331 | * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad | |
3332 | * type/offset/length), EACCES (if PHY_LOCK required and not held) | |
f0d37f42 SH |
3333 | */ |
3334 | #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c | |
f0d37f42 | 3335 | |
75122ec8 SS |
3336 | #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3337 | ||
05a9320f BH |
3338 | /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ |
3339 | #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 | |
3340 | #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 | |
3341 | /* Enum values, see field(s): */ | |
3342 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3343 | #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 | |
3344 | ||
3345 | /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ | |
3346 | #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 | |
3347 | ||
3348 | ||
3349 | /***********************************/ | |
3350 | /* MC_CMD_REBOOT | |
5297a98d | 3351 | * Reboot the MC. |
f2b0befd BH |
3352 | * |
3353 | * The AFTER_ASSERTION flag is intended to be used when the driver notices an | |
3354 | * assertion failure (at which point it is expected to perform a complete tear | |
3355 | * down and reinitialise), to allow both ports to reset the MC once in an | |
3356 | * atomic fashion. | |
3357 | * | |
3358 | * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, | |
3359 | * which means that they will automatically reboot out of the assertion | |
3360 | * handler, so this is in practise an optional operation. It is still | |
3361 | * recommended that drivers execute this to support custom firmwares with | |
3362 | * REBOOT_ON_ASSERT=0. | |
3363 | * | |
3364 | * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, | |
3365 | * DATALEN=0 | |
f0d37f42 SH |
3366 | */ |
3367 | #define MC_CMD_REBOOT 0x3d | |
f0d37f42 | 3368 | |
75122ec8 SS |
3369 | #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3370 | ||
05a9320f BH |
3371 | /* MC_CMD_REBOOT_IN msgrequest */ |
3372 | #define MC_CMD_REBOOT_IN_LEN 4 | |
3373 | #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 | |
3374 | #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ | |
3375 | ||
3376 | /* MC_CMD_REBOOT_OUT msgresponse */ | |
3377 | #define MC_CMD_REBOOT_OUT_LEN 0 | |
3378 | ||
3379 | ||
3380 | /***********************************/ | |
3381 | /* MC_CMD_SCHEDINFO | |
f2b0befd BH |
3382 | * Request scheduler info. Locks required: NONE. Returns: An array of |
3383 | * (timeslice,maximum overrun), one for each thread, in ascending order of | |
3384 | * thread address. | |
f0d37f42 SH |
3385 | */ |
3386 | #define MC_CMD_SCHEDINFO 0x3e | |
f0d37f42 | 3387 | |
05a9320f BH |
3388 | /* MC_CMD_SCHEDINFO_IN msgrequest */ |
3389 | #define MC_CMD_SCHEDINFO_IN_LEN 0 | |
f0d37f42 | 3390 | |
05a9320f BH |
3391 | /* MC_CMD_SCHEDINFO_OUT msgresponse */ |
3392 | #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 | |
3393 | #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 | |
3394 | #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) | |
3395 | #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 | |
3396 | #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 | |
3397 | #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 | |
3398 | #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 | |
3399 | ||
3400 | ||
3401 | /***********************************/ | |
3402 | /* MC_CMD_REBOOT_MODE | |
f2b0befd BH |
3403 | * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot |
3404 | * mode to the specified value. Returns the old mode. | |
f0d37f42 SH |
3405 | */ |
3406 | #define MC_CMD_REBOOT_MODE 0x3f | |
05a9320f | 3407 | |
75122ec8 SS |
3408 | #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3409 | ||
05a9320f BH |
3410 | /* MC_CMD_REBOOT_MODE_IN msgrequest */ |
3411 | #define MC_CMD_REBOOT_MODE_IN_LEN 4 | |
3412 | #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 | |
f2b0befd BH |
3413 | /* enum: Normal. */ |
3414 | #define MC_CMD_REBOOT_MODE_NORMAL 0x0 | |
3415 | /* enum: Power-on Reset. */ | |
3416 | #define MC_CMD_REBOOT_MODE_POR 0x2 | |
3417 | /* enum: Snapper. */ | |
3418 | #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 | |
3419 | /* enum: snapper fake POR */ | |
3420 | #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 | |
3421 | #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 | |
3422 | #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 | |
05a9320f BH |
3423 | |
3424 | /* MC_CMD_REBOOT_MODE_OUT msgresponse */ | |
3425 | #define MC_CMD_REBOOT_MODE_OUT_LEN 4 | |
3426 | #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 | |
3427 | ||
3428 | ||
3429 | /***********************************/ | |
3430 | /* MC_CMD_SENSOR_INFO | |
f0d37f42 | 3431 | * Returns information about every available sensor. |
f2b0befd BH |
3432 | * |
3433 | * Each sensor has a single (16bit) value, and a corresponding state. The | |
3434 | * mapping between value and state is nominally determined by the MC, but may | |
3435 | * be implemented using up to 2 ranges per sensor. | |
3436 | * | |
3437 | * This call returns a mask (32bit) of the sensors that are supported by this | |
3438 | * platform, then an array of sensor information structures, in order of sensor | |
3439 | * type (but without gaps for unimplemented sensors). Each structure defines | |
3440 | * the ranges for the corresponding sensor. An unused range is indicated by | |
3441 | * equal limit values. If one range is used, a value outside that range results | |
3442 | * in STATE_FATAL. If two ranges are used, a value outside the second range | |
3443 | * results in STATE_FATAL while a value outside the first and inside the second | |
3444 | * range results in STATE_WARNING. | |
3445 | * | |
3446 | * Sensor masks and sensor information arrays are organised into pages. For | |
3447 | * backward compatibility, older host software can only use sensors in page 0. | |
3448 | * Bit 32 in the sensor mask was previously unused, and is no reserved for use | |
3449 | * as the next page flag. | |
3450 | * | |
3451 | * If the request does not contain a PAGE value then firmware will only return | |
3452 | * page 0 of sensor information, with bit 31 in the sensor mask cleared. | |
3453 | * | |
3454 | * If the request contains a PAGE value then firmware responds with the sensor | |
3455 | * mask and sensor information array for that page of sensors. In this case bit | |
3456 | * 31 in the mask is set if another page exists. | |
3457 | * | |
3458 | * Locks required: None Returns: 0 | |
f0d37f42 SH |
3459 | */ |
3460 | #define MC_CMD_SENSOR_INFO 0x41 | |
f0d37f42 | 3461 | |
75122ec8 SS |
3462 | #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3463 | ||
05a9320f BH |
3464 | /* MC_CMD_SENSOR_INFO_IN msgrequest */ |
3465 | #define MC_CMD_SENSOR_INFO_IN_LEN 0 | |
3466 | ||
f2b0befd BH |
3467 | /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ |
3468 | #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 | |
3469 | /* Which page of sensors to report. | |
3470 | * | |
3471 | * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). | |
3472 | * | |
3473 | * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. | |
3474 | */ | |
3475 | #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 | |
3476 | ||
05a9320f | 3477 | /* MC_CMD_SENSOR_INFO_OUT msgresponse */ |
512bb06c | 3478 | #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 |
05a9320f BH |
3479 | #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 |
3480 | #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) | |
3481 | #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 | |
f2b0befd BH |
3482 | /* enum: Controller temperature: degC */ |
3483 | #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 | |
3484 | /* enum: Phy common temperature: degC */ | |
3485 | #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 | |
3486 | /* enum: Controller cooling: bool */ | |
3487 | #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 | |
3488 | /* enum: Phy 0 temperature: degC */ | |
3489 | #define MC_CMD_SENSOR_PHY0_TEMP 0x3 | |
3490 | /* enum: Phy 0 cooling: bool */ | |
3491 | #define MC_CMD_SENSOR_PHY0_COOLING 0x4 | |
3492 | /* enum: Phy 1 temperature: degC */ | |
3493 | #define MC_CMD_SENSOR_PHY1_TEMP 0x5 | |
3494 | /* enum: Phy 1 cooling: bool */ | |
3495 | #define MC_CMD_SENSOR_PHY1_COOLING 0x6 | |
3496 | /* enum: 1.0v power: mV */ | |
3497 | #define MC_CMD_SENSOR_IN_1V0 0x7 | |
3498 | /* enum: 1.2v power: mV */ | |
3499 | #define MC_CMD_SENSOR_IN_1V2 0x8 | |
3500 | /* enum: 1.8v power: mV */ | |
3501 | #define MC_CMD_SENSOR_IN_1V8 0x9 | |
3502 | /* enum: 2.5v power: mV */ | |
3503 | #define MC_CMD_SENSOR_IN_2V5 0xa | |
3504 | /* enum: 3.3v power: mV */ | |
3505 | #define MC_CMD_SENSOR_IN_3V3 0xb | |
3506 | /* enum: 12v power: mV */ | |
3507 | #define MC_CMD_SENSOR_IN_12V0 0xc | |
3508 | /* enum: 1.2v analogue power: mV */ | |
3509 | #define MC_CMD_SENSOR_IN_1V2A 0xd | |
3510 | /* enum: reference voltage: mV */ | |
3511 | #define MC_CMD_SENSOR_IN_VREF 0xe | |
3512 | /* enum: AOE FPGA power: mV */ | |
3513 | #define MC_CMD_SENSOR_OUT_VAOE 0xf | |
3514 | /* enum: AOE FPGA temperature: degC */ | |
3515 | #define MC_CMD_SENSOR_AOE_TEMP 0x10 | |
3516 | /* enum: AOE FPGA PSU temperature: degC */ | |
3517 | #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 | |
3518 | /* enum: AOE PSU temperature: degC */ | |
3519 | #define MC_CMD_SENSOR_PSU_TEMP 0x12 | |
3520 | /* enum: Fan 0 speed: RPM */ | |
3521 | #define MC_CMD_SENSOR_FAN_0 0x13 | |
3522 | /* enum: Fan 1 speed: RPM */ | |
3523 | #define MC_CMD_SENSOR_FAN_1 0x14 | |
3524 | /* enum: Fan 2 speed: RPM */ | |
3525 | #define MC_CMD_SENSOR_FAN_2 0x15 | |
3526 | /* enum: Fan 3 speed: RPM */ | |
3527 | #define MC_CMD_SENSOR_FAN_3 0x16 | |
3528 | /* enum: Fan 4 speed: RPM */ | |
3529 | #define MC_CMD_SENSOR_FAN_4 0x17 | |
3530 | /* enum: AOE FPGA input power: mV */ | |
3531 | #define MC_CMD_SENSOR_IN_VAOE 0x18 | |
3532 | /* enum: AOE FPGA current: mA */ | |
3533 | #define MC_CMD_SENSOR_OUT_IAOE 0x19 | |
3534 | /* enum: AOE FPGA input current: mA */ | |
3535 | #define MC_CMD_SENSOR_IN_IAOE 0x1a | |
3536 | /* enum: NIC power consumption: W */ | |
3537 | #define MC_CMD_SENSOR_NIC_POWER 0x1b | |
3538 | /* enum: 0.9v power voltage: mV */ | |
3539 | #define MC_CMD_SENSOR_IN_0V9 0x1c | |
3540 | /* enum: 0.9v power current: mA */ | |
3541 | #define MC_CMD_SENSOR_IN_I0V9 0x1d | |
3542 | /* enum: 1.2v power current: mA */ | |
3543 | #define MC_CMD_SENSOR_IN_I1V2 0x1e | |
3544 | /* enum: Not a sensor: reserved for the next page flag */ | |
3545 | #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f | |
3546 | /* enum: 0.9v power voltage (at ADC): mV */ | |
3547 | #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 | |
3548 | /* enum: Controller temperature 2: degC */ | |
3549 | #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 | |
3550 | /* enum: Voltage regulator internal temperature: degC */ | |
3551 | #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 | |
3552 | /* enum: 0.9V voltage regulator temperature: degC */ | |
3553 | #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 | |
3554 | /* enum: 1.2V voltage regulator temperature: degC */ | |
3555 | #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 | |
3556 | /* enum: controller internal temperature sensor voltage (internal ADC): mV */ | |
3557 | #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 | |
3558 | /* enum: controller internal temperature (internal ADC): degC */ | |
3559 | #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 | |
3560 | /* enum: controller internal temperature sensor voltage (external ADC): mV */ | |
3561 | #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 | |
3562 | /* enum: controller internal temperature (external ADC): degC */ | |
3563 | #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 | |
3564 | /* enum: ambient temperature: degC */ | |
3565 | #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 | |
3566 | /* enum: air flow: bool */ | |
3567 | #define MC_CMD_SENSOR_AIRFLOW 0x2a | |
3568 | /* enum: voltage between VSS08D and VSS08D at CSR: mV */ | |
3569 | #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b | |
3570 | /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ | |
3571 | #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c | |
512bb06c BH |
3572 | /* enum: Hotpoint temperature: degC */ |
3573 | #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d | |
f2b0befd | 3574 | /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ |
05a9320f BH |
3575 | #define MC_CMD_SENSOR_ENTRY_OFST 4 |
3576 | #define MC_CMD_SENSOR_ENTRY_LEN 8 | |
3577 | #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 | |
3578 | #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 | |
512bb06c | 3579 | #define MC_CMD_SENSOR_ENTRY_MINNUM 0 |
05a9320f BH |
3580 | #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 |
3581 | ||
f2b0befd | 3582 | /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ |
512bb06c | 3583 | #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 |
f2b0befd BH |
3584 | #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 |
3585 | #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) | |
3586 | #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 | |
3587 | /* Enum values, see field(s): */ | |
3588 | /* MC_CMD_SENSOR_INFO_OUT */ | |
3589 | #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 | |
3590 | #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 | |
3591 | /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ | |
3592 | /* MC_CMD_SENSOR_ENTRY_OFST 4 */ | |
3593 | /* MC_CMD_SENSOR_ENTRY_LEN 8 */ | |
3594 | /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ | |
3595 | /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ | |
512bb06c | 3596 | /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ |
f2b0befd BH |
3597 | /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ |
3598 | ||
05a9320f BH |
3599 | /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ |
3600 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 | |
3601 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 | |
3602 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 | |
3603 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 | |
3604 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 | |
3605 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 | |
3606 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 | |
3607 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 | |
3608 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 | |
3609 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 | |
3610 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 | |
3611 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 | |
3612 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 | |
3613 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 | |
3614 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 | |
3615 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 | |
3616 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 | |
3617 | ||
3618 | ||
3619 | /***********************************/ | |
f0d37f42 | 3620 | /* MC_CMD_READ_SENSORS |
f2b0befd BH |
3621 | * Returns the current reading from each sensor. DMAs an array of sensor |
3622 | * readings, in order of sensor type (but without gaps for unimplemented | |
3623 | * sensors), into host memory. Each array element is a | |
3624 | * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. | |
3625 | * | |
3626 | * If the request does not contain the LENGTH field then only sensors 0 to 30 | |
3627 | * are reported, to avoid DMA buffer overflow in older host software. If the | |
3628 | * sensor reading require more space than the LENGTH allows, then return | |
3629 | * EINVAL. | |
3630 | * | |
3631 | * The MC will send a SENSOREVT event every time any sensor changes state. The | |
3632 | * driver is responsible for ensuring that it doesn't miss any events. The | |
3633 | * board will function normally if all sensors are in STATE_OK or | |
3634 | * STATE_WARNING. Otherwise the board should not be expected to function. | |
f0d37f42 SH |
3635 | */ |
3636 | #define MC_CMD_READ_SENSORS 0x42 | |
f0d37f42 | 3637 | |
75122ec8 SS |
3638 | #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3639 | ||
05a9320f BH |
3640 | /* MC_CMD_READ_SENSORS_IN msgrequest */ |
3641 | #define MC_CMD_READ_SENSORS_IN_LEN 8 | |
f2b0befd | 3642 | /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ |
05a9320f BH |
3643 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 |
3644 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 | |
3645 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 | |
3646 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 | |
3647 | ||
f2b0befd BH |
3648 | /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ |
3649 | #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 | |
3650 | /* DMA address of host buffer for sensor readings */ | |
3651 | #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 | |
3652 | #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 | |
3653 | #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 | |
3654 | #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 | |
3655 | /* Size in bytes of host buffer. */ | |
3656 | #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 | |
3657 | ||
05a9320f BH |
3658 | /* MC_CMD_READ_SENSORS_OUT msgresponse */ |
3659 | #define MC_CMD_READ_SENSORS_OUT_LEN 0 | |
3660 | ||
f2b0befd BH |
3661 | /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ |
3662 | #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 | |
3663 | ||
05a9320f | 3664 | /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ |
f2b0befd | 3665 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 |
05a9320f BH |
3666 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 |
3667 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 | |
3668 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 | |
3669 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 | |
3670 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 | |
3671 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 | |
f2b0befd BH |
3672 | /* enum: Ok. */ |
3673 | #define MC_CMD_SENSOR_STATE_OK 0x0 | |
3674 | /* enum: Breached warning threshold. */ | |
3675 | #define MC_CMD_SENSOR_STATE_WARNING 0x1 | |
3676 | /* enum: Breached fatal threshold. */ | |
3677 | #define MC_CMD_SENSOR_STATE_FATAL 0x2 | |
3678 | /* enum: Fault with sensor. */ | |
3679 | #define MC_CMD_SENSOR_STATE_BROKEN 0x3 | |
3680 | /* enum: Sensor is working but does not currently have a reading. */ | |
3681 | #define MC_CMD_SENSOR_STATE_NO_READING 0x4 | |
05a9320f BH |
3682 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 |
3683 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 | |
f2b0befd BH |
3684 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 |
3685 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 | |
3686 | /* Enum values, see field(s): */ | |
3687 | /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ | |
3688 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 | |
3689 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 | |
05a9320f BH |
3690 | |
3691 | ||
3692 | /***********************************/ | |
3693 | /* MC_CMD_GET_PHY_STATE | |
f2b0befd BH |
3694 | * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot |
3695 | * (e.g. due to missing or corrupted firmware). Locks required: None. Return | |
3696 | * code: 0 | |
f0d37f42 SH |
3697 | */ |
3698 | #define MC_CMD_GET_PHY_STATE 0x43 | |
3699 | ||
75122ec8 SS |
3700 | #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
3701 | ||
05a9320f BH |
3702 | /* MC_CMD_GET_PHY_STATE_IN msgrequest */ |
3703 | #define MC_CMD_GET_PHY_STATE_IN_LEN 0 | |
f0d37f42 | 3704 | |
05a9320f BH |
3705 | /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ |
3706 | #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 | |
3707 | #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 | |
f2b0befd BH |
3708 | /* enum: Ok. */ |
3709 | #define MC_CMD_PHY_STATE_OK 0x1 | |
3710 | /* enum: Faulty. */ | |
3711 | #define MC_CMD_PHY_STATE_ZOMBIE 0x2 | |
f0d37f42 | 3712 | |
05a9320f BH |
3713 | |
3714 | /***********************************/ | |
3715 | /* MC_CMD_SETUP_8021QBB | |
f2b0befd BH |
3716 | * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to |
3717 | * disable 802.Qbb for a given priority. | |
05a9320f | 3718 | */ |
f0d37f42 | 3719 | #define MC_CMD_SETUP_8021QBB 0x44 |
f0d37f42 | 3720 | |
05a9320f BH |
3721 | /* MC_CMD_SETUP_8021QBB_IN msgrequest */ |
3722 | #define MC_CMD_SETUP_8021QBB_IN_LEN 32 | |
3723 | #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 | |
3724 | #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 | |
f0d37f42 | 3725 | |
05a9320f BH |
3726 | /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ |
3727 | #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 | |
f0d37f42 SH |
3728 | |
3729 | ||
05a9320f BH |
3730 | /***********************************/ |
3731 | /* MC_CMD_WOL_FILTER_GET | |
f2b0befd | 3732 | * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS |
f0d37f42 | 3733 | */ |
05a9320f | 3734 | #define MC_CMD_WOL_FILTER_GET 0x45 |
f0d37f42 | 3735 | |
75122ec8 SS |
3736 | #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK |
3737 | ||
05a9320f BH |
3738 | /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ |
3739 | #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 | |
f0d37f42 | 3740 | |
05a9320f BH |
3741 | /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ |
3742 | #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 | |
3743 | #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 | |
f0d37f42 | 3744 | |
f0d37f42 | 3745 | |
05a9320f BH |
3746 | /***********************************/ |
3747 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD | |
f2b0befd BH |
3748 | * Add a protocol offload to NIC for lights-out state. Locks required: None. |
3749 | * Returns: 0, ENOSYS | |
05a9320f BH |
3750 | */ |
3751 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 | |
f0d37f42 | 3752 | |
75122ec8 SS |
3753 | #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK |
3754 | ||
05a9320f BH |
3755 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ |
3756 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 | |
3757 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 | |
3758 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) | |
3759 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 | |
3760 | #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ | |
3761 | #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ | |
3762 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 | |
3763 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 | |
3764 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 | |
3765 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 | |
3766 | ||
3767 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ | |
3768 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 | |
3769 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ | |
3770 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 | |
3771 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 | |
3772 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 | |
3773 | ||
3774 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ | |
3775 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 | |
3776 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ | |
3777 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 | |
3778 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 | |
3779 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 | |
3780 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 | |
3781 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 | |
3782 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 | |
3783 | ||
3784 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ | |
3785 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 | |
3786 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 | |
3787 | ||
3788 | ||
3789 | /***********************************/ | |
3790 | /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD | |
f2b0befd BH |
3791 | * Remove a protocol offload from NIC for lights-out state. Locks required: |
3792 | * None. Returns: 0, ENOSYS | |
f0d37f42 SH |
3793 | */ |
3794 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 | |
f0d37f42 | 3795 | |
75122ec8 SS |
3796 | #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK |
3797 | ||
05a9320f BH |
3798 | /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ |
3799 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 | |
3800 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 | |
3801 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 | |
f0d37f42 | 3802 | |
05a9320f BH |
3803 | /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ |
3804 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 | |
f0d37f42 SH |
3805 | |
3806 | ||
05a9320f BH |
3807 | /***********************************/ |
3808 | /* MC_CMD_MAC_RESET_RESTORE | |
f2b0befd | 3809 | * Restore MAC after block reset. Locks required: None. Returns: 0. |
f0d37f42 | 3810 | */ |
f0d37f42 | 3811 | #define MC_CMD_MAC_RESET_RESTORE 0x48 |
f0d37f42 | 3812 | |
05a9320f BH |
3813 | /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ |
3814 | #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 | |
3815 | ||
3816 | /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ | |
3817 | #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 | |
5297a98d | 3818 | |
5297a98d | 3819 | |
05a9320f BH |
3820 | /***********************************/ |
3821 | /* MC_CMD_TESTASSERT | |
f2b0befd BH |
3822 | * Deliberately trigger an assert-detonation in the firmware for testing |
3823 | * purposes (i.e. to allow tests that the driver copes gracefully). Locks | |
3824 | * required: None Returns: 0 | |
05a9320f | 3825 | */ |
5297a98d | 3826 | #define MC_CMD_TESTASSERT 0x49 |
5297a98d | 3827 | |
75122ec8 SS |
3828 | #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3829 | ||
05a9320f BH |
3830 | /* MC_CMD_TESTASSERT_IN msgrequest */ |
3831 | #define MC_CMD_TESTASSERT_IN_LEN 0 | |
3832 | ||
3833 | /* MC_CMD_TESTASSERT_OUT msgresponse */ | |
3834 | #define MC_CMD_TESTASSERT_OUT_LEN 0 | |
3835 | ||
3836 | ||
3837 | /***********************************/ | |
3838 | /* MC_CMD_WORKAROUND | |
f2b0befd BH |
3839 | * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't |
3840 | * understand the given workaround number - which should not be treated as a | |
3841 | * hard error by client code. This op does not imply any semantics about each | |
3842 | * workaround, that's between the driver and the mcfw on a per-workaround | |
3843 | * basis. Locks required: None. Returns: 0, EINVAL . | |
5297a98d BH |
3844 | */ |
3845 | #define MC_CMD_WORKAROUND 0x4a | |
05a9320f | 3846 | |
75122ec8 SS |
3847 | #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3848 | ||
05a9320f BH |
3849 | /* MC_CMD_WORKAROUND_IN msgrequest */ |
3850 | #define MC_CMD_WORKAROUND_IN_LEN 8 | |
3851 | #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 | |
f2b0befd BH |
3852 | /* enum: Bug 17230 work around. */ |
3853 | #define MC_CMD_WORKAROUND_BUG17230 0x1 | |
3854 | /* enum: Bug 35388 work around (unsafe EVQ writes). */ | |
3855 | #define MC_CMD_WORKAROUND_BUG35388 0x2 | |
3856 | /* enum: Bug35017 workaround (A64 tables must be identity map) */ | |
3857 | #define MC_CMD_WORKAROUND_BUG35017 0x3 | |
05a9320f BH |
3858 | #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 |
3859 | ||
3860 | /* MC_CMD_WORKAROUND_OUT msgresponse */ | |
3861 | #define MC_CMD_WORKAROUND_OUT_LEN 0 | |
3862 | ||
3863 | ||
3864 | /***********************************/ | |
3865 | /* MC_CMD_GET_PHY_MEDIA_INFO | |
f2b0befd BH |
3866 | * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for |
3867 | * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG | |
3868 | * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the | |
3869 | * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 | |
3870 | * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. | |
3871 | * Anything else: currently undefined. Locks required: None. Return code: 0. | |
5297a98d BH |
3872 | */ |
3873 | #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b | |
05a9320f | 3874 | |
75122ec8 SS |
3875 | #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3876 | ||
05a9320f BH |
3877 | /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ |
3878 | #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 | |
3879 | #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 | |
3880 | ||
3881 | /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ | |
3882 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 | |
576eda8b | 3883 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 |
05a9320f | 3884 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) |
f2b0befd | 3885 | /* in bytes */ |
05a9320f BH |
3886 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 |
3887 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 | |
3888 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 | |
3889 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 | |
576eda8b | 3890 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 |
05a9320f BH |
3891 | |
3892 | ||
3893 | /***********************************/ | |
3894 | /* MC_CMD_NVRAM_TEST | |
f2b0befd BH |
3895 | * Test a particular NVRAM partition for valid contents (where "valid" depends |
3896 | * on the type of partition). | |
5297a98d BH |
3897 | */ |
3898 | #define MC_CMD_NVRAM_TEST 0x4c | |
05a9320f | 3899 | |
75122ec8 SS |
3900 | #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3901 | ||
05a9320f BH |
3902 | /* MC_CMD_NVRAM_TEST_IN msgrequest */ |
3903 | #define MC_CMD_NVRAM_TEST_IN_LEN 4 | |
3904 | #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 | |
3905 | /* Enum values, see field(s): */ | |
3906 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3907 | ||
3908 | /* MC_CMD_NVRAM_TEST_OUT msgresponse */ | |
3909 | #define MC_CMD_NVRAM_TEST_OUT_LEN 4 | |
3910 | #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 | |
f2b0befd BH |
3911 | /* enum: Passed. */ |
3912 | #define MC_CMD_NVRAM_TEST_PASS 0x0 | |
3913 | /* enum: Failed. */ | |
3914 | #define MC_CMD_NVRAM_TEST_FAIL 0x1 | |
3915 | /* enum: Not supported. */ | |
3916 | #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 | |
05a9320f BH |
3917 | |
3918 | ||
3919 | /***********************************/ | |
3920 | /* MC_CMD_MRSFP_TWEAK | |
f2b0befd BH |
3921 | * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. |
3922 | * I2C I/O expander bits are always read; if equaliser parameters are supplied, | |
3923 | * they are configured first. Locks required: None. Return code: 0, EINVAL. | |
5297a98d BH |
3924 | */ |
3925 | #define MC_CMD_MRSFP_TWEAK 0x4d | |
05a9320f BH |
3926 | |
3927 | /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ | |
3928 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 | |
f2b0befd | 3929 | /* 0-6 low->high de-emph. */ |
05a9320f | 3930 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 |
f2b0befd | 3931 | /* 0-8 low->high ref.V */ |
05a9320f | 3932 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 |
f2b0befd | 3933 | /* 0-8 0-8 low->high boost */ |
05a9320f | 3934 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 |
f2b0befd | 3935 | /* 0-8 low->high ref.V */ |
05a9320f BH |
3936 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 |
3937 | ||
3938 | /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ | |
3939 | #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 | |
3940 | ||
3941 | /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ | |
3942 | #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 | |
f2b0befd | 3943 | /* input bits */ |
05a9320f | 3944 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 |
f2b0befd | 3945 | /* output bits */ |
05a9320f | 3946 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 |
f2b0befd | 3947 | /* direction */ |
05a9320f | 3948 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 |
f2b0befd BH |
3949 | /* enum: Out. */ |
3950 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 | |
3951 | /* enum: In. */ | |
3952 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 | |
05a9320f BH |
3953 | |
3954 | ||
3955 | /***********************************/ | |
3956 | /* MC_CMD_SENSOR_SET_LIMS | |
f2b0befd BH |
3957 | * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: |
3958 | * ENOENT if the sensor specified does not exist, EINVAL if the limits are out | |
3959 | * of range. | |
fbcfe8e1 BH |
3960 | */ |
3961 | #define MC_CMD_SENSOR_SET_LIMS 0x4e | |
05a9320f | 3962 | |
75122ec8 SS |
3963 | #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3964 | ||
05a9320f BH |
3965 | /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ |
3966 | #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 | |
3967 | #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 | |
3968 | /* Enum values, see field(s): */ | |
3969 | /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ | |
f2b0befd | 3970 | /* interpretation is is sensor-specific. */ |
05a9320f | 3971 | #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 |
f2b0befd | 3972 | /* interpretation is is sensor-specific. */ |
05a9320f | 3973 | #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 |
f2b0befd | 3974 | /* interpretation is is sensor-specific. */ |
05a9320f | 3975 | #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 |
f2b0befd | 3976 | /* interpretation is is sensor-specific. */ |
05a9320f BH |
3977 | #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 |
3978 | ||
3979 | /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ | |
3980 | #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 | |
3981 | ||
3982 | ||
3983 | /***********************************/ | |
3984 | /* MC_CMD_GET_RESOURCE_LIMITS | |
3985 | */ | |
3986 | #define MC_CMD_GET_RESOURCE_LIMITS 0x4f | |
3987 | ||
3988 | /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ | |
3989 | #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 | |
3990 | ||
3991 | /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ | |
3992 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 | |
3993 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 | |
3994 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 | |
3995 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 | |
3996 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 | |
3997 | ||
f2b0befd BH |
3998 | |
3999 | /***********************************/ | |
4000 | /* MC_CMD_NVRAM_PARTITIONS | |
4001 | * Reads the list of available virtual NVRAM partition types. Locks required: | |
4002 | * none. Returns: 0, EINVAL (bad type). | |
4003 | */ | |
4004 | #define MC_CMD_NVRAM_PARTITIONS 0x51 | |
4005 | ||
75122ec8 SS |
4006 | #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4007 | ||
f2b0befd BH |
4008 | /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ |
4009 | #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 | |
4010 | ||
4011 | /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ | |
4012 | #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 | |
4013 | #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 | |
4014 | #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) | |
4015 | /* total number of partitions */ | |
4016 | #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 | |
4017 | /* type ID code for each of NUM_PARTITIONS partitions */ | |
4018 | #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 | |
4019 | #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 | |
4020 | #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 | |
4021 | #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 | |
4022 | ||
4023 | ||
4024 | /***********************************/ | |
4025 | /* MC_CMD_NVRAM_METADATA | |
4026 | * Reads soft metadata for a virtual NVRAM partition type. Locks required: | |
4027 | * none. Returns: 0, EINVAL (bad type). | |
4028 | */ | |
4029 | #define MC_CMD_NVRAM_METADATA 0x52 | |
4030 | ||
75122ec8 SS |
4031 | #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4032 | ||
f2b0befd BH |
4033 | /* MC_CMD_NVRAM_METADATA_IN msgrequest */ |
4034 | #define MC_CMD_NVRAM_METADATA_IN_LEN 4 | |
4035 | /* Partition type ID code */ | |
4036 | #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 | |
4037 | ||
4038 | /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ | |
4039 | #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 | |
4040 | #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 | |
4041 | #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) | |
4042 | /* Partition type ID code */ | |
4043 | #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 | |
4044 | #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 | |
4045 | #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 | |
4046 | #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 | |
4047 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 | |
4048 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 | |
4049 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 | |
4050 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 | |
4051 | /* Subtype ID code for content of this partition */ | |
4052 | #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 | |
4053 | /* 1st component of W.X.Y.Z version number for content of this partition */ | |
4054 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 | |
4055 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 | |
4056 | /* 2nd component of W.X.Y.Z version number for content of this partition */ | |
4057 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 | |
4058 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 | |
4059 | /* 3rd component of W.X.Y.Z version number for content of this partition */ | |
4060 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 | |
4061 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 | |
4062 | /* 4th component of W.X.Y.Z version number for content of this partition */ | |
4063 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 | |
4064 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 | |
4065 | /* Zero-terminated string describing the content of this partition */ | |
4066 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 | |
4067 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 | |
4068 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 | |
4069 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 | |
4070 | ||
4071 | ||
4072 | /***********************************/ | |
4073 | /* MC_CMD_GET_MAC_ADDRESSES | |
4074 | * Returns the base MAC, count and stride for the requestiong function | |
4075 | */ | |
4076 | #define MC_CMD_GET_MAC_ADDRESSES 0x55 | |
4077 | ||
75122ec8 SS |
4078 | #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4079 | ||
f2b0befd BH |
4080 | /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ |
4081 | #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 | |
4082 | ||
4083 | /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ | |
4084 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 | |
4085 | /* Base MAC address */ | |
4086 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 | |
4087 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 | |
4088 | /* Padding */ | |
4089 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 | |
4090 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 | |
4091 | /* Number of allocated MAC addresses */ | |
4092 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 | |
4093 | /* Spacing of allocated MAC addresses */ | |
4094 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 | |
4095 | ||
05a9320f | 4096 | /* MC_CMD_RESOURCE_SPECIFIER enum */ |
f2b0befd BH |
4097 | /* enum: Any */ |
4098 | #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff | |
4099 | /* enum: None */ | |
4100 | #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe | |
4101 | ||
4102 | /* EVB_PORT_ID structuredef */ | |
4103 | #define EVB_PORT_ID_LEN 4 | |
4104 | #define EVB_PORT_ID_PORT_ID_OFST 0 | |
4105 | /* enum: An invalid port handle. */ | |
4106 | #define EVB_PORT_ID_NULL 0x0 | |
4107 | /* enum: The port assigned to this function.. */ | |
4108 | #define EVB_PORT_ID_ASSIGNED 0x1000000 | |
4109 | /* enum: External network port 0 */ | |
4110 | #define EVB_PORT_ID_MAC0 0x2000000 | |
4111 | /* enum: External network port 1 */ | |
4112 | #define EVB_PORT_ID_MAC1 0x2000001 | |
4113 | /* enum: External network port 2 */ | |
4114 | #define EVB_PORT_ID_MAC2 0x2000002 | |
4115 | /* enum: External network port 3 */ | |
4116 | #define EVB_PORT_ID_MAC3 0x2000003 | |
4117 | #define EVB_PORT_ID_PORT_ID_LBN 0 | |
4118 | #define EVB_PORT_ID_PORT_ID_WIDTH 32 | |
4119 | ||
4120 | /* EVB_VLAN_TAG structuredef */ | |
4121 | #define EVB_VLAN_TAG_LEN 2 | |
4122 | /* The VLAN tag value */ | |
4123 | #define EVB_VLAN_TAG_VLAN_ID_LBN 0 | |
4124 | #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 | |
4125 | #define EVB_VLAN_TAG_MODE_LBN 12 | |
4126 | #define EVB_VLAN_TAG_MODE_WIDTH 4 | |
4127 | /* enum: Insert the VLAN. */ | |
4128 | #define EVB_VLAN_TAG_INSERT 0x0 | |
4129 | /* enum: Replace the VLAN if already present. */ | |
4130 | #define EVB_VLAN_TAG_REPLACE 0x1 | |
4131 | ||
4132 | /* BUFTBL_ENTRY structuredef */ | |
4133 | #define BUFTBL_ENTRY_LEN 12 | |
4134 | /* the owner ID */ | |
4135 | #define BUFTBL_ENTRY_OID_OFST 0 | |
4136 | #define BUFTBL_ENTRY_OID_LEN 2 | |
4137 | #define BUFTBL_ENTRY_OID_LBN 0 | |
4138 | #define BUFTBL_ENTRY_OID_WIDTH 16 | |
4139 | /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ | |
4140 | #define BUFTBL_ENTRY_PGSZ_OFST 2 | |
4141 | #define BUFTBL_ENTRY_PGSZ_LEN 2 | |
4142 | #define BUFTBL_ENTRY_PGSZ_LBN 16 | |
4143 | #define BUFTBL_ENTRY_PGSZ_WIDTH 16 | |
4144 | /* the raw 64-bit address field from the SMC, not adjusted for page size */ | |
4145 | #define BUFTBL_ENTRY_RAWADDR_OFST 4 | |
4146 | #define BUFTBL_ENTRY_RAWADDR_LEN 8 | |
4147 | #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 | |
4148 | #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 | |
4149 | #define BUFTBL_ENTRY_RAWADDR_LBN 32 | |
4150 | #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 | |
4151 | ||
4152 | /* NVRAM_PARTITION_TYPE structuredef */ | |
4153 | #define NVRAM_PARTITION_TYPE_LEN 2 | |
4154 | #define NVRAM_PARTITION_TYPE_ID_OFST 0 | |
4155 | #define NVRAM_PARTITION_TYPE_ID_LEN 2 | |
4156 | /* enum: Primary MC firmware partition */ | |
4157 | #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 | |
4158 | /* enum: Secondary MC firmware partition */ | |
4159 | #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 | |
4160 | /* enum: Expansion ROM partition */ | |
4161 | #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 | |
4162 | /* enum: Static configuration TLV partition */ | |
4163 | #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 | |
4164 | /* enum: Dynamic configuration TLV partition */ | |
4165 | #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 | |
4166 | /* enum: Expansion ROM configuration data for port 0 */ | |
4167 | #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 | |
4168 | /* enum: Expansion ROM configuration data for port 1 */ | |
4169 | #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 | |
4170 | /* enum: Expansion ROM configuration data for port 2 */ | |
4171 | #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 | |
4172 | /* enum: Expansion ROM configuration data for port 3 */ | |
4173 | #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 | |
4174 | /* enum: Non-volatile log output partition */ | |
4175 | #define NVRAM_PARTITION_TYPE_LOG 0x700 | |
4176 | /* enum: Device state dump output partition */ | |
4177 | #define NVRAM_PARTITION_TYPE_DUMP 0x800 | |
4178 | /* enum: Application license key storage partition */ | |
4179 | #define NVRAM_PARTITION_TYPE_LICENSE 0x900 | |
bedca866 MS |
4180 | /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ |
4181 | #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 | |
4182 | /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ | |
4183 | #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff | |
f2b0befd BH |
4184 | /* enum: Start of reserved value range (firmware may use for any purpose) */ |
4185 | #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 | |
4186 | /* enum: End of reserved value range (firmware may use for any purpose) */ | |
4187 | #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd | |
4188 | /* enum: Recovery partition map (provided if real map is missing or corrupt) */ | |
4189 | #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe | |
4190 | /* enum: Partition map (real map as stored in flash) */ | |
4191 | #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff | |
4192 | #define NVRAM_PARTITION_TYPE_ID_LBN 0 | |
4193 | #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 | |
4194 | ||
512bb06c BH |
4195 | /* LICENSED_APP_ID structuredef */ |
4196 | #define LICENSED_APP_ID_LEN 4 | |
4197 | #define LICENSED_APP_ID_ID_OFST 0 | |
4198 | /* enum: OpenOnload */ | |
4199 | #define LICENSED_APP_ID_ONLOAD 0x1 | |
4200 | /* enum: PTP timestamping */ | |
4201 | #define LICENSED_APP_ID_PTP 0x2 | |
4202 | /* enum: SolarCapture Pro */ | |
4203 | #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 | |
4204 | #define LICENSED_APP_ID_ID_LBN 0 | |
4205 | #define LICENSED_APP_ID_ID_WIDTH 32 | |
4206 | ||
f2b0befd | 4207 | |
267d9d73 EC |
4208 | /***********************************/ |
4209 | /* MC_CMD_GET_WORKAROUNDS | |
4210 | * Read the list of all implemented and all currently enabled workarounds. The | |
4211 | * enums here must correspond with those in MC_CMD_WORKAROUND. | |
4212 | */ | |
4213 | #define MC_CMD_GET_WORKAROUNDS 0x59 | |
4214 | ||
4215 | /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ | |
4216 | #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 | |
4217 | /* Each workaround is represented by a single bit according to the enums below. | |
4218 | */ | |
4219 | #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 | |
4220 | #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 | |
4221 | /* enum: Bug 17230 work around. */ | |
4222 | #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 | |
4223 | /* enum: Bug 35388 work around (unsafe EVQ writes). */ | |
4224 | #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 | |
4225 | /* enum: Bug35017 workaround (A64 tables must be identity map) */ | |
4226 | #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 | |
4227 | ||
4228 | ||
4392dc69 EC |
4229 | /***********************************/ |
4230 | /* MC_CMD_LINK_STATE_MODE | |
4231 | * Read/set link state mode of a VF | |
4232 | */ | |
4233 | #define MC_CMD_LINK_STATE_MODE 0x5c | |
4234 | ||
4235 | #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
4236 | ||
4237 | /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ | |
4238 | #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 | |
4239 | /* The target function to have its link state mode read or set, must be a VF | |
4240 | * e.g. VF 1,3 = 0x00030001 | |
4241 | */ | |
4242 | #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 | |
4243 | #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 | |
4244 | #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 | |
4245 | #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 | |
4246 | #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 | |
4247 | /* New link state mode to be set */ | |
4248 | #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 | |
4249 | #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ | |
4250 | #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ | |
4251 | #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ | |
4252 | /* enum: Use this value to just read the existing setting without modifying it. | |
4253 | */ | |
4254 | #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff | |
4255 | ||
4256 | /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ | |
4257 | #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 | |
4258 | #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 | |
4259 | ||
4260 | ||
f2b0befd BH |
4261 | /***********************************/ |
4262 | /* MC_CMD_READ_REGS | |
4263 | * Get a dump of the MCPU registers | |
4264 | */ | |
4265 | #define MC_CMD_READ_REGS 0x50 | |
4266 | ||
75122ec8 SS |
4267 | #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4268 | ||
f2b0befd BH |
4269 | /* MC_CMD_READ_REGS_IN msgrequest */ |
4270 | #define MC_CMD_READ_REGS_IN_LEN 0 | |
4271 | ||
4272 | /* MC_CMD_READ_REGS_OUT msgresponse */ | |
4273 | #define MC_CMD_READ_REGS_OUT_LEN 308 | |
4274 | /* Whether the corresponding register entry contains a valid value */ | |
4275 | #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 | |
4276 | #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 | |
4277 | /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, | |
4278 | * fir, fp) | |
4279 | */ | |
4280 | #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 | |
4281 | #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 | |
4282 | #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 | |
4283 | ||
4284 | ||
4285 | /***********************************/ | |
4286 | /* MC_CMD_INIT_EVQ | |
4287 | * Set up an event queue according to the supplied parameters. The IN arguments | |
4288 | * end with an address for each 4k of host memory required to back the EVQ. | |
4289 | */ | |
4290 | #define MC_CMD_INIT_EVQ 0x80 | |
4291 | ||
75122ec8 SS |
4292 | #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4293 | ||
f2b0befd BH |
4294 | /* MC_CMD_INIT_EVQ_IN msgrequest */ |
4295 | #define MC_CMD_INIT_EVQ_IN_LENMIN 44 | |
4296 | #define MC_CMD_INIT_EVQ_IN_LENMAX 548 | |
4297 | #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) | |
4298 | /* Size, in entries */ | |
4299 | #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 | |
4300 | /* Desired instance. Must be set to a specific instance, which is a function | |
4301 | * local queue index. | |
4302 | */ | |
4303 | #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 | |
4304 | /* The initial timer value. The load value is ignored if the timer mode is DIS. | |
4305 | */ | |
4306 | #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 | |
4307 | /* The reload value is ignored in one-shot modes */ | |
4308 | #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 | |
4309 | /* tbd */ | |
4310 | #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 | |
4311 | #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 | |
4312 | #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 | |
4313 | #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 | |
4314 | #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 | |
4315 | #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 | |
4316 | #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 | |
4317 | #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 | |
4318 | #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 | |
4319 | #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 | |
4320 | #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 | |
4321 | #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 | |
4322 | #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 | |
4323 | #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 | |
4324 | /* enum: Disabled */ | |
4325 | #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 | |
4326 | /* enum: Immediate */ | |
4327 | #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 | |
4328 | /* enum: Triggered */ | |
4329 | #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 | |
4330 | /* enum: Hold-off */ | |
4331 | #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 | |
4332 | /* Target EVQ for wakeups if in wakeup mode. */ | |
4333 | #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 | |
4334 | /* Target interrupt if in interrupting mode (note union with target EVQ). Use | |
4335 | * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test | |
4336 | * purposes. | |
4337 | */ | |
4338 | #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 | |
4339 | /* Event Counter Mode. */ | |
4340 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 | |
4341 | /* enum: Disabled */ | |
4342 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 | |
4343 | /* enum: Disabled */ | |
4344 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 | |
4345 | /* enum: Disabled */ | |
4346 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 | |
4347 | /* enum: Disabled */ | |
4348 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 | |
4349 | /* Event queue packet count threshold. */ | |
4350 | #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 | |
4351 | /* 64-bit address of 4k of 4k-aligned host memory buffer */ | |
4352 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 | |
4353 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 | |
4354 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 | |
4355 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 | |
4356 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 | |
4357 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 | |
4358 | ||
4359 | /* MC_CMD_INIT_EVQ_OUT msgresponse */ | |
4360 | #define MC_CMD_INIT_EVQ_OUT_LEN 4 | |
4361 | /* Only valid if INTRFLAG was true */ | |
4362 | #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 | |
4363 | ||
4364 | /* QUEUE_CRC_MODE structuredef */ | |
4365 | #define QUEUE_CRC_MODE_LEN 1 | |
4366 | #define QUEUE_CRC_MODE_MODE_LBN 0 | |
4367 | #define QUEUE_CRC_MODE_MODE_WIDTH 4 | |
4368 | /* enum: No CRC. */ | |
4369 | #define QUEUE_CRC_MODE_NONE 0x0 | |
4370 | /* enum: CRC Fiber channel over ethernet. */ | |
4371 | #define QUEUE_CRC_MODE_FCOE 0x1 | |
4372 | /* enum: CRC (digest) iSCSI header only. */ | |
4373 | #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 | |
4374 | /* enum: CRC (digest) iSCSI header and payload. */ | |
4375 | #define QUEUE_CRC_MODE_ISCSI 0x3 | |
4376 | /* enum: CRC Fiber channel over IP over ethernet. */ | |
4377 | #define QUEUE_CRC_MODE_FCOIPOE 0x4 | |
4378 | /* enum: CRC MPA. */ | |
4379 | #define QUEUE_CRC_MODE_MPA 0x5 | |
4380 | #define QUEUE_CRC_MODE_SPARE_LBN 4 | |
4381 | #define QUEUE_CRC_MODE_SPARE_WIDTH 4 | |
4382 | ||
4383 | ||
4384 | /***********************************/ | |
4385 | /* MC_CMD_INIT_RXQ | |
4386 | * set up a receive queue according to the supplied parameters. The IN | |
4387 | * arguments end with an address for each 4k of host memory required to back | |
4388 | * the RXQ. | |
4389 | */ | |
4390 | #define MC_CMD_INIT_RXQ 0x81 | |
4391 | ||
75122ec8 SS |
4392 | #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4393 | ||
f2b0befd BH |
4394 | /* MC_CMD_INIT_RXQ_IN msgrequest */ |
4395 | #define MC_CMD_INIT_RXQ_IN_LENMIN 36 | |
4396 | #define MC_CMD_INIT_RXQ_IN_LENMAX 252 | |
4397 | #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) | |
4398 | /* Size, in entries */ | |
4399 | #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 | |
4400 | /* The EVQ to send events to. This is an index originally specified to INIT_EVQ | |
4401 | */ | |
4402 | #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 | |
4403 | /* The value to put in the event data. Check hardware spec. for valid range. */ | |
4404 | #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 | |
4405 | /* Desired instance. Must be set to a specific instance, which is a function | |
4406 | * local queue index. | |
4407 | */ | |
4408 | #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 | |
4409 | /* There will be more flags here. */ | |
4410 | #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 | |
4411 | #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 | |
4412 | #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 | |
4413 | #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 | |
4414 | #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 | |
4415 | #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 | |
4416 | #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 | |
4417 | #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 | |
4418 | #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 | |
4419 | #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 | |
4420 | #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 | |
4421 | #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 | |
4422 | #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 | |
512bb06c BH |
4423 | #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 |
4424 | #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 | |
f2b0befd BH |
4425 | /* Owner ID to use if in buffer mode (zero if physical) */ |
4426 | #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 | |
4427 | /* The port ID associated with the v-adaptor which should contain this DMAQ. */ | |
4428 | #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 | |
4429 | /* 64-bit address of 4k of 4k-aligned host memory buffer */ | |
4430 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 | |
4431 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 | |
4432 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 | |
4433 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 | |
4434 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 | |
4435 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 | |
4436 | ||
4437 | /* MC_CMD_INIT_RXQ_OUT msgresponse */ | |
4438 | #define MC_CMD_INIT_RXQ_OUT_LEN 0 | |
4439 | ||
4440 | ||
4441 | /***********************************/ | |
4442 | /* MC_CMD_INIT_TXQ | |
4443 | */ | |
4444 | #define MC_CMD_INIT_TXQ 0x82 | |
4445 | ||
75122ec8 SS |
4446 | #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4447 | ||
f2b0befd BH |
4448 | /* MC_CMD_INIT_TXQ_IN msgrequest */ |
4449 | #define MC_CMD_INIT_TXQ_IN_LENMIN 36 | |
4450 | #define MC_CMD_INIT_TXQ_IN_LENMAX 252 | |
4451 | #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) | |
4452 | /* Size, in entries */ | |
4453 | #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 | |
4454 | /* The EVQ to send events to. This is an index originally specified to | |
4455 | * INIT_EVQ. | |
4456 | */ | |
4457 | #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 | |
4458 | /* The value to put in the event data. Check hardware spec. for valid range. */ | |
4459 | #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 | |
4460 | /* Desired instance. Must be set to a specific instance, which is a function | |
4461 | * local queue index. | |
4462 | */ | |
4463 | #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 | |
4464 | /* There will be more flags here. */ | |
4465 | #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 | |
4466 | #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 | |
4467 | #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 | |
4468 | #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 | |
4469 | #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 | |
4470 | #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 | |
4471 | #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 | |
4472 | #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 | |
4473 | #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 | |
4474 | #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 | |
4475 | #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 | |
4476 | #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 | |
4477 | #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 | |
4478 | #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 | |
4479 | #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 | |
4480 | /* Owner ID to use if in buffer mode (zero if physical) */ | |
4481 | #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 | |
4482 | /* The port ID associated with the v-adaptor which should contain this DMAQ. */ | |
4483 | #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 | |
4484 | /* 64-bit address of 4k of 4k-aligned host memory buffer */ | |
4485 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 | |
4486 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 | |
4487 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 | |
4488 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 | |
4489 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 | |
4490 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 | |
4491 | ||
4492 | /* MC_CMD_INIT_TXQ_OUT msgresponse */ | |
4493 | #define MC_CMD_INIT_TXQ_OUT_LEN 0 | |
4494 | ||
4495 | ||
4496 | /***********************************/ | |
4497 | /* MC_CMD_FINI_EVQ | |
4498 | * Teardown an EVQ. | |
4499 | * | |
4500 | * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first | |
4501 | * or the operation will fail with EBUSY | |
4502 | */ | |
4503 | #define MC_CMD_FINI_EVQ 0x83 | |
4504 | ||
75122ec8 SS |
4505 | #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4506 | ||
f2b0befd BH |
4507 | /* MC_CMD_FINI_EVQ_IN msgrequest */ |
4508 | #define MC_CMD_FINI_EVQ_IN_LEN 4 | |
4509 | /* Instance of EVQ to destroy. Should be the same instance as that previously | |
4510 | * passed to INIT_EVQ | |
4511 | */ | |
4512 | #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 | |
4513 | ||
4514 | /* MC_CMD_FINI_EVQ_OUT msgresponse */ | |
4515 | #define MC_CMD_FINI_EVQ_OUT_LEN 0 | |
4516 | ||
4517 | ||
4518 | /***********************************/ | |
4519 | /* MC_CMD_FINI_RXQ | |
4520 | * Teardown a RXQ. | |
4521 | */ | |
4522 | #define MC_CMD_FINI_RXQ 0x84 | |
4523 | ||
75122ec8 SS |
4524 | #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4525 | ||
f2b0befd BH |
4526 | /* MC_CMD_FINI_RXQ_IN msgrequest */ |
4527 | #define MC_CMD_FINI_RXQ_IN_LEN 4 | |
4528 | /* Instance of RXQ to destroy */ | |
4529 | #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 | |
4530 | ||
4531 | /* MC_CMD_FINI_RXQ_OUT msgresponse */ | |
4532 | #define MC_CMD_FINI_RXQ_OUT_LEN 0 | |
4533 | ||
4534 | ||
4535 | /***********************************/ | |
4536 | /* MC_CMD_FINI_TXQ | |
4537 | * Teardown a TXQ. | |
4538 | */ | |
4539 | #define MC_CMD_FINI_TXQ 0x85 | |
4540 | ||
75122ec8 SS |
4541 | #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4542 | ||
f2b0befd BH |
4543 | /* MC_CMD_FINI_TXQ_IN msgrequest */ |
4544 | #define MC_CMD_FINI_TXQ_IN_LEN 4 | |
4545 | /* Instance of TXQ to destroy */ | |
4546 | #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 | |
4547 | ||
4548 | /* MC_CMD_FINI_TXQ_OUT msgresponse */ | |
4549 | #define MC_CMD_FINI_TXQ_OUT_LEN 0 | |
4550 | ||
4551 | ||
4552 | /***********************************/ | |
4553 | /* MC_CMD_DRIVER_EVENT | |
4554 | * Generate an event on an EVQ belonging to the function issuing the command. | |
4555 | */ | |
4556 | #define MC_CMD_DRIVER_EVENT 0x86 | |
4557 | ||
75122ec8 SS |
4558 | #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4559 | ||
f2b0befd BH |
4560 | /* MC_CMD_DRIVER_EVENT_IN msgrequest */ |
4561 | #define MC_CMD_DRIVER_EVENT_IN_LEN 12 | |
4562 | /* Handle of target EVQ */ | |
4563 | #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 | |
4564 | /* Bits 0 - 63 of event */ | |
4565 | #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 | |
4566 | #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 | |
4567 | #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 | |
4568 | #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 | |
4569 | ||
4570 | /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ | |
4571 | #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 | |
4572 | ||
4573 | ||
4574 | /***********************************/ | |
4575 | /* MC_CMD_PROXY_CMD | |
4576 | * Execute an arbitrary MCDI command on behalf of a different function, subject | |
4577 | * to security restrictions. The command to be proxied follows immediately | |
4578 | * afterward in the host buffer (or on the UART). This command supercedes | |
4579 | * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. | |
4580 | */ | |
4581 | #define MC_CMD_PROXY_CMD 0x5b | |
4582 | ||
75122ec8 SS |
4583 | #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4584 | ||
f2b0befd BH |
4585 | /* MC_CMD_PROXY_CMD_IN msgrequest */ |
4586 | #define MC_CMD_PROXY_CMD_IN_LEN 4 | |
4587 | /* The handle of the target function. */ | |
4588 | #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 | |
4589 | #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 | |
4590 | #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 | |
4591 | #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 | |
4592 | #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 | |
4593 | #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ | |
4594 | ||
512bb06c BH |
4595 | /* MC_CMD_PROXY_CMD_OUT msgresponse */ |
4596 | #define MC_CMD_PROXY_CMD_OUT_LEN 0 | |
4597 | ||
f2b0befd BH |
4598 | |
4599 | /***********************************/ | |
4600 | /* MC_CMD_ALLOC_BUFTBL_CHUNK | |
4601 | * Allocate a set of buffer table entries using the specified owner ID. This | |
4602 | * operation allocates the required buffer table entries (and fails if it | |
4603 | * cannot do so). The buffer table entries will initially be zeroed. | |
4604 | */ | |
4605 | #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 | |
4606 | ||
75122ec8 SS |
4607 | #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
4608 | ||
f2b0befd BH |
4609 | /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ |
4610 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 | |
4611 | /* Owner ID to use */ | |
4612 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 | |
4613 | /* Size of buffer table pages to use, in bytes (note that only a few values are | |
4614 | * legal on any specific hardware). | |
4615 | */ | |
4616 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 | |
4617 | ||
4618 | /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ | |
4619 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 | |
4620 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 | |
4621 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 | |
4622 | /* Buffer table IDs for use in DMA descriptors. */ | |
4623 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 | |
4624 | ||
4625 | ||
4626 | /***********************************/ | |
4627 | /* MC_CMD_PROGRAM_BUFTBL_ENTRIES | |
4628 | * Reprogram a set of buffer table entries in the specified chunk. | |
4629 | */ | |
4630 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 | |
4631 | ||
75122ec8 SS |
4632 | #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
4633 | ||
f2b0befd BH |
4634 | /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ |
4635 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 | |
512bb06c | 4636 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 |
f2b0befd BH |
4637 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) |
4638 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 | |
4639 | /* ID */ | |
4640 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 | |
4641 | /* Num entries */ | |
4642 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 | |
4643 | /* Buffer table entry address */ | |
4644 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 | |
4645 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 | |
4646 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 | |
4647 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 | |
4648 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 | |
512bb06c | 4649 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 |
f2b0befd BH |
4650 | |
4651 | /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ | |
4652 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 | |
4653 | ||
4654 | ||
4655 | /***********************************/ | |
4656 | /* MC_CMD_FREE_BUFTBL_CHUNK | |
4657 | */ | |
4658 | #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 | |
4659 | ||
75122ec8 SS |
4660 | #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
4661 | ||
f2b0befd BH |
4662 | /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ |
4663 | #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 | |
4664 | #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 | |
4665 | ||
4666 | /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ | |
4667 | #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 | |
4668 | ||
4669 | ||
4670 | /***********************************/ | |
4671 | /* MC_CMD_FILTER_OP | |
4672 | * Multiplexed MCDI call for filter operations | |
4673 | */ | |
4674 | #define MC_CMD_FILTER_OP 0x8a | |
4675 | ||
75122ec8 SS |
4676 | #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4677 | ||
f2b0befd BH |
4678 | /* MC_CMD_FILTER_OP_IN msgrequest */ |
4679 | #define MC_CMD_FILTER_OP_IN_LEN 108 | |
4680 | /* identifies the type of operation requested */ | |
4681 | #define MC_CMD_FILTER_OP_IN_OP_OFST 0 | |
4682 | /* enum: single-recipient filter insert */ | |
4683 | #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 | |
4684 | /* enum: single-recipient filter remove */ | |
4685 | #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 | |
4686 | /* enum: multi-recipient filter subscribe */ | |
4687 | #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 | |
4688 | /* enum: multi-recipient filter unsubscribe */ | |
4689 | #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 | |
4690 | /* enum: replace one recipient with another (warning - the filter handle may | |
4691 | * change) | |
4692 | */ | |
4693 | #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 | |
4694 | /* filter handle (for remove / unsubscribe operations) */ | |
4695 | #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 | |
4696 | #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 | |
4697 | #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 | |
4698 | #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 | |
4699 | /* The port ID associated with the v-adaptor which should contain this filter. | |
4700 | */ | |
4701 | #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 | |
4702 | /* fields to include in match criteria */ | |
4703 | #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 | |
4704 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 | |
4705 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 | |
4706 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 | |
4707 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 | |
4708 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 | |
4709 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 | |
4710 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 | |
4711 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 | |
4712 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 | |
4713 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 | |
4714 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 | |
4715 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 | |
4716 | #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 | |
4717 | #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 | |
4718 | #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 | |
4719 | #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 | |
4720 | #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 | |
4721 | #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 | |
4722 | #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 | |
4723 | #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 | |
4724 | #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 | |
4725 | #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 | |
4726 | #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 | |
4727 | #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 | |
4728 | #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 | |
4729 | #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 | |
4730 | #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 | |
4731 | #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 | |
4732 | /* receive destination */ | |
4733 | #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 | |
4734 | /* enum: drop packets */ | |
4735 | #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 | |
4736 | /* enum: receive to host */ | |
4737 | #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 | |
4738 | /* enum: receive to MC */ | |
4739 | #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 | |
4740 | /* enum: loop back to port 0 TX MAC */ | |
4741 | #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 | |
4742 | /* enum: loop back to port 1 TX MAC */ | |
4743 | #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 | |
4744 | /* receive queue handle (for multiple queue modes, this is the base queue) */ | |
4745 | #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 | |
4746 | /* receive mode */ | |
4747 | #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 | |
4748 | /* enum: receive to just the specified queue */ | |
4749 | #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 | |
4750 | /* enum: receive to multiple queues using RSS context */ | |
4751 | #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 | |
4752 | /* enum: receive to multiple queues using .1p mapping */ | |
4753 | #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 | |
4754 | /* enum: install a filter entry that will never match; for test purposes only | |
4755 | */ | |
4756 | #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 | |
4757 | /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for | |
4758 | * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or | |
4759 | * MC_CMD_DOT1P_MAPPING_ALLOC. Note that these handles should be considered | |
4760 | * opaque to the host, although a value of 0xFFFFFFFF is guaranteed never to be | |
4761 | * a valid handle. | |
4762 | */ | |
4763 | #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 | |
4764 | /* transmit domain (reserved; set to 0) */ | |
4765 | #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 | |
4766 | /* transmit destination (either set the MAC and/or PM bits for explicit | |
4767 | * control, or set this field to TX_DEST_DEFAULT for sensible default | |
4768 | * behaviour) | |
4769 | */ | |
4770 | #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 | |
4771 | /* enum: request default behaviour (based on filter type) */ | |
4772 | #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff | |
4773 | #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 | |
4774 | #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 | |
4775 | #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 | |
4776 | #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 | |
4777 | /* source MAC address to match (as bytes in network order) */ | |
4778 | #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 | |
4779 | #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 | |
4780 | /* source port to match (as bytes in network order) */ | |
4781 | #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 | |
4782 | #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 | |
4783 | /* destination MAC address to match (as bytes in network order) */ | |
4784 | #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 | |
4785 | #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 | |
4786 | /* destination port to match (as bytes in network order) */ | |
4787 | #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 | |
4788 | #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 | |
4789 | /* Ethernet type to match (as bytes in network order) */ | |
4790 | #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 | |
4791 | #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 | |
4792 | /* Inner VLAN tag to match (as bytes in network order) */ | |
4793 | #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 | |
4794 | #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 | |
4795 | /* Outer VLAN tag to match (as bytes in network order) */ | |
4796 | #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 | |
4797 | #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 | |
4798 | /* IP protocol to match (in low byte; set high byte to 0) */ | |
4799 | #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 | |
4800 | #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 | |
4801 | /* Firmware defined register 0 to match (reserved; set to 0) */ | |
4802 | #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 | |
4803 | /* Firmware defined register 1 to match (reserved; set to 0) */ | |
4804 | #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 | |
4805 | /* source IP address to match (as bytes in network order; set last 12 bytes to | |
4806 | * 0 for IPv4 address) | |
4807 | */ | |
4808 | #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 | |
4809 | #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 | |
4810 | /* destination IP address to match (as bytes in network order; set last 12 | |
4811 | * bytes to 0 for IPv4 address) | |
4812 | */ | |
4813 | #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 | |
4814 | #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 | |
4815 | ||
4816 | /* MC_CMD_FILTER_OP_OUT msgresponse */ | |
4817 | #define MC_CMD_FILTER_OP_OUT_LEN 12 | |
4818 | /* identifies the type of operation requested */ | |
4819 | #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 | |
4820 | /* Enum values, see field(s): */ | |
4821 | /* MC_CMD_FILTER_OP_IN/OP */ | |
4822 | /* Returned filter handle (for insert / subscribe operations). Note that these | |
4823 | * handles should be considered opaque to the host, although a value of | |
4824 | * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. | |
4825 | */ | |
4826 | #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 | |
4827 | #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 | |
4828 | #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 | |
4829 | #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 | |
4830 | ||
4831 | ||
4832 | /***********************************/ | |
4833 | /* MC_CMD_GET_PARSER_DISP_INFO | |
4834 | * Get information related to the parser-dispatcher subsystem | |
4835 | */ | |
4836 | #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 | |
4837 | ||
75122ec8 SS |
4838 | #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4839 | ||
f2b0befd BH |
4840 | /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ |
4841 | #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 | |
4842 | /* identifies the type of operation requested */ | |
4843 | #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 | |
4844 | /* enum: read the list of supported RX filter matches */ | |
4845 | #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 | |
4846 | ||
4847 | /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ | |
4848 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 | |
4849 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 | |
4850 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) | |
4851 | /* identifies the type of operation requested */ | |
4852 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 | |
4853 | /* Enum values, see field(s): */ | |
4854 | /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ | |
4855 | /* number of supported match types */ | |
4856 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 | |
4857 | /* array of supported match types (valid MATCH_FIELDS values for | |
4858 | * MC_CMD_FILTER_OP) sorted in decreasing priority order | |
4859 | */ | |
4860 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 | |
4861 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 | |
4862 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 | |
4863 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 | |
4864 | ||
4865 | ||
4866 | /***********************************/ | |
4867 | /* MC_CMD_PARSER_DISP_RW | |
4868 | * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging | |
4869 | */ | |
4870 | #define MC_CMD_PARSER_DISP_RW 0xe5 | |
4871 | ||
75122ec8 SS |
4872 | #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4873 | ||
f2b0befd BH |
4874 | /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ |
4875 | #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 | |
4876 | /* identifies the target of the operation */ | |
4877 | #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 | |
4878 | /* enum: RX dispatcher CPU */ | |
4879 | #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 | |
4880 | /* enum: TX dispatcher CPU */ | |
4881 | #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 | |
4882 | /* enum: Lookup engine */ | |
4883 | #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 | |
4884 | /* identifies the type of operation requested */ | |
4885 | #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 | |
4886 | /* enum: read a word of DICPU DMEM or a LUE entry */ | |
4887 | #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 | |
4888 | /* enum: write a word of DICPU DMEM or a LUE entry */ | |
4889 | #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 | |
4890 | /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ | |
4891 | #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 | |
4892 | /* data memory address or LUE index */ | |
4893 | #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 | |
4894 | /* value to write (for DMEM writes) */ | |
4895 | #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 | |
4896 | /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ | |
4897 | #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 | |
4898 | /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ | |
4899 | #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 | |
4900 | /* value to write (for LUE writes) */ | |
4901 | #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 | |
4902 | #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 | |
4903 | ||
4904 | /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ | |
4905 | #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 | |
4906 | /* value read (for DMEM reads) */ | |
4907 | #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 | |
4908 | /* value read (for LUE reads) */ | |
4909 | #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 | |
4910 | #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 | |
4911 | /* up to 8 32-bit words of additional soft state from the LUE manager (the | |
4912 | * exact content is firmware-dependent and intended only for debug use) | |
4913 | */ | |
4914 | #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 | |
4915 | #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 | |
4916 | ||
4917 | ||
4918 | /***********************************/ | |
4919 | /* MC_CMD_GET_PF_COUNT | |
4920 | * Get number of PFs on the device. | |
4921 | */ | |
4922 | #define MC_CMD_GET_PF_COUNT 0xb6 | |
4923 | ||
75122ec8 SS |
4924 | #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4925 | ||
f2b0befd BH |
4926 | /* MC_CMD_GET_PF_COUNT_IN msgrequest */ |
4927 | #define MC_CMD_GET_PF_COUNT_IN_LEN 0 | |
4928 | ||
4929 | /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ | |
4930 | #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 | |
4931 | /* Identifies the number of PFs on the device. */ | |
4932 | #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 | |
4933 | #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 | |
4934 | ||
4935 | ||
4936 | /***********************************/ | |
4937 | /* MC_CMD_SET_PF_COUNT | |
4938 | * Set number of PFs on the device. | |
4939 | */ | |
4940 | #define MC_CMD_SET_PF_COUNT 0xb7 | |
4941 | ||
4942 | /* MC_CMD_SET_PF_COUNT_IN msgrequest */ | |
4943 | #define MC_CMD_SET_PF_COUNT_IN_LEN 4 | |
4944 | /* New number of PFs on the device. */ | |
4945 | #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 | |
4946 | ||
4947 | /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ | |
4948 | #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 | |
4949 | ||
4950 | ||
4951 | /***********************************/ | |
4952 | /* MC_CMD_GET_PORT_ASSIGNMENT | |
4953 | * Get port assignment for current PCI function. | |
4954 | */ | |
4955 | #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 | |
4956 | ||
75122ec8 SS |
4957 | #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4958 | ||
f2b0befd BH |
4959 | /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ |
4960 | #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 | |
4961 | ||
4962 | /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ | |
4963 | #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 | |
4964 | /* Identifies the port assignment for this function. */ | |
4965 | #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 | |
4966 | ||
4967 | ||
4968 | /***********************************/ | |
4969 | /* MC_CMD_SET_PORT_ASSIGNMENT | |
4970 | * Set port assignment for current PCI function. | |
4971 | */ | |
4972 | #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 | |
4973 | ||
75122ec8 SS |
4974 | #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4975 | ||
f2b0befd BH |
4976 | /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ |
4977 | #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 | |
4978 | /* Identifies the port assignment for this function. */ | |
4979 | #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 | |
4980 | ||
4981 | /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ | |
4982 | #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 | |
4983 | ||
4984 | ||
4985 | /***********************************/ | |
4986 | /* MC_CMD_ALLOC_VIS | |
4987 | * Allocate VIs for current PCI function. | |
4988 | */ | |
4989 | #define MC_CMD_ALLOC_VIS 0x8b | |
4990 | ||
75122ec8 SS |
4991 | #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4992 | ||
f2b0befd BH |
4993 | /* MC_CMD_ALLOC_VIS_IN msgrequest */ |
4994 | #define MC_CMD_ALLOC_VIS_IN_LEN 8 | |
4995 | /* The minimum number of VIs that is acceptable */ | |
4996 | #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 | |
4997 | /* The maximum number of VIs that would be useful */ | |
4998 | #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 | |
4999 | ||
5000 | /* MC_CMD_ALLOC_VIS_OUT msgresponse */ | |
5001 | #define MC_CMD_ALLOC_VIS_OUT_LEN 8 | |
5002 | /* The number of VIs allocated on this function */ | |
5003 | #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 | |
5004 | /* The base absolute VI number allocated to this function. Required to | |
5005 | * correctly interpret wakeup events. | |
5006 | */ | |
5007 | #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 | |
5008 | ||
5009 | ||
5010 | /***********************************/ | |
5011 | /* MC_CMD_FREE_VIS | |
5012 | * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, | |
5013 | * but not freed. | |
5014 | */ | |
5015 | #define MC_CMD_FREE_VIS 0x8c | |
5016 | ||
75122ec8 SS |
5017 | #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5018 | ||
f2b0befd BH |
5019 | /* MC_CMD_FREE_VIS_IN msgrequest */ |
5020 | #define MC_CMD_FREE_VIS_IN_LEN 0 | |
5021 | ||
5022 | /* MC_CMD_FREE_VIS_OUT msgresponse */ | |
5023 | #define MC_CMD_FREE_VIS_OUT_LEN 0 | |
5024 | ||
5025 | ||
5026 | /***********************************/ | |
5027 | /* MC_CMD_GET_SRIOV_CFG | |
5028 | * Get SRIOV config for this PF. | |
5029 | */ | |
5030 | #define MC_CMD_GET_SRIOV_CFG 0xba | |
5031 | ||
75122ec8 SS |
5032 | #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5033 | ||
f2b0befd BH |
5034 | /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ |
5035 | #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 | |
5036 | ||
5037 | /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ | |
5038 | #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 | |
5039 | /* Number of VFs currently enabled. */ | |
5040 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 | |
5041 | /* Max number of VFs before sriov stride and offset may need to be changed. */ | |
5042 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 | |
5043 | #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 | |
5044 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 | |
5045 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 | |
5046 | /* RID offset of first VF from PF. */ | |
5047 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 | |
5048 | /* RID offset of each subsequent VF from the previous. */ | |
5049 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 | |
5050 | ||
5051 | ||
5052 | /***********************************/ | |
5053 | /* MC_CMD_SET_SRIOV_CFG | |
5054 | * Set SRIOV config for this PF. | |
5055 | */ | |
5056 | #define MC_CMD_SET_SRIOV_CFG 0xbb | |
5057 | ||
75122ec8 SS |
5058 | #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
5059 | ||
f2b0befd BH |
5060 | /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ |
5061 | #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 | |
5062 | /* Number of VFs currently enabled. */ | |
5063 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 | |
5064 | /* Max number of VFs before sriov stride and offset may need to be changed. */ | |
5065 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 | |
5066 | #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 | |
5067 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 | |
5068 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 | |
5069 | /* RID offset of first VF from PF, or 0 for no change, or | |
5070 | * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. | |
5071 | */ | |
5072 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 | |
5073 | /* RID offset of each subsequent VF from the previous, 0 for no change, or | |
5074 | * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. | |
5075 | */ | |
5076 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 | |
5077 | ||
5078 | /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ | |
5079 | #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 | |
5080 | ||
5081 | ||
5082 | /***********************************/ | |
5083 | /* MC_CMD_GET_VI_ALLOC_INFO | |
5084 | * Get information about number of VI's and base VI number allocated to this | |
5085 | * function. | |
5086 | */ | |
5087 | #define MC_CMD_GET_VI_ALLOC_INFO 0x8d | |
5088 | ||
75122ec8 SS |
5089 | #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5090 | ||
f2b0befd BH |
5091 | /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ |
5092 | #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 | |
5093 | ||
5094 | /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ | |
5095 | #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 8 | |
5096 | /* The number of VIs allocated on this function */ | |
5097 | #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 | |
5098 | /* The base absolute VI number allocated to this function. Required to | |
5099 | * correctly interpret wakeup events. | |
5100 | */ | |
5101 | #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 | |
5102 | ||
5103 | ||
5104 | /***********************************/ | |
5105 | /* MC_CMD_DUMP_VI_STATE | |
5106 | * For CmdClient use. Dump pertinent information on a specific absolute VI. | |
5107 | */ | |
5108 | #define MC_CMD_DUMP_VI_STATE 0x8e | |
5109 | ||
75122ec8 SS |
5110 | #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5111 | ||
f2b0befd BH |
5112 | /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ |
5113 | #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 | |
5114 | /* The VI number to query. */ | |
5115 | #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 | |
5116 | ||
5117 | /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ | |
5118 | #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 | |
5119 | /* The PF part of the function owning this VI. */ | |
5120 | #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 | |
5121 | #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 | |
5122 | /* The VF part of the function owning this VI. */ | |
5123 | #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 | |
5124 | #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 | |
5125 | /* Base of VIs allocated to this function. */ | |
5126 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 | |
5127 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 | |
5128 | /* Count of VIs allocated to the owner function. */ | |
5129 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 | |
5130 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 | |
5131 | /* Base interrupt vector allocated to this function. */ | |
5132 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 | |
5133 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 | |
5134 | /* Number of interrupt vectors allocated to this function. */ | |
5135 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 | |
5136 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 | |
5137 | /* Raw evq ptr table data. */ | |
5138 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 | |
5139 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 | |
5140 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 | |
5141 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 | |
5142 | /* Raw evq timer table data. */ | |
5143 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 | |
5144 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 | |
5145 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 | |
5146 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 | |
5147 | /* Combined metadata field. */ | |
5148 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 | |
5149 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 | |
5150 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 | |
5151 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 | |
5152 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 | |
5153 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 | |
5154 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 | |
5155 | /* TXDPCPU raw table data for queue. */ | |
5156 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 | |
5157 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 | |
5158 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 | |
5159 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 | |
5160 | /* TXDPCPU raw table data for queue. */ | |
5161 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 | |
5162 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 | |
5163 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 | |
5164 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 | |
5165 | /* TXDPCPU raw table data for queue. */ | |
5166 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 | |
5167 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 | |
5168 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 | |
5169 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 | |
5170 | /* Combined metadata field. */ | |
5171 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 | |
5172 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 | |
5173 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 | |
5174 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 | |
5175 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 | |
5176 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 | |
5177 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 | |
5178 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 | |
5179 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 | |
5180 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 | |
5181 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 | |
5182 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 | |
5183 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 | |
5184 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 | |
5185 | /* RXDPCPU raw table data for queue. */ | |
5186 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 | |
5187 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 | |
5188 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 | |
5189 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 | |
5190 | /* RXDPCPU raw table data for queue. */ | |
5191 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 | |
5192 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 | |
5193 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 | |
5194 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 | |
5195 | /* Reserved, currently 0. */ | |
5196 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 | |
5197 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 | |
5198 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 | |
5199 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 | |
5200 | /* Combined metadata field. */ | |
5201 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 | |
5202 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 | |
5203 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 | |
5204 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 | |
5205 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 | |
5206 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 | |
5207 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 | |
5208 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 | |
5209 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 | |
5210 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 | |
5211 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 | |
5212 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 | |
5213 | ||
5214 | ||
5215 | /***********************************/ | |
5216 | /* MC_CMD_ALLOC_PIOBUF | |
5217 | * Allocate a push I/O buffer for later use with a tx queue. | |
5218 | */ | |
5219 | #define MC_CMD_ALLOC_PIOBUF 0x8f | |
5220 | ||
75122ec8 SS |
5221 | #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
5222 | ||
f2b0befd BH |
5223 | /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ |
5224 | #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 | |
5225 | ||
5226 | /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ | |
5227 | #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 | |
5228 | /* Handle for allocated push I/O buffer. */ | |
5229 | #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 | |
5230 | ||
5231 | ||
5232 | /***********************************/ | |
5233 | /* MC_CMD_FREE_PIOBUF | |
5234 | * Free a push I/O buffer. | |
5235 | */ | |
5236 | #define MC_CMD_FREE_PIOBUF 0x90 | |
5237 | ||
75122ec8 SS |
5238 | #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
5239 | ||
f2b0befd BH |
5240 | /* MC_CMD_FREE_PIOBUF_IN msgrequest */ |
5241 | #define MC_CMD_FREE_PIOBUF_IN_LEN 4 | |
5242 | /* Handle for allocated push I/O buffer. */ | |
5243 | #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 | |
5244 | ||
5245 | /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ | |
5246 | #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 | |
5247 | ||
5248 | ||
5249 | /***********************************/ | |
5250 | /* MC_CMD_GET_VI_TLP_PROCESSING | |
5251 | * Get TLP steering and ordering information for a VI. | |
5252 | */ | |
5253 | #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 | |
5254 | ||
75122ec8 SS |
5255 | #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5256 | ||
f2b0befd BH |
5257 | /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ |
5258 | #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 | |
5259 | /* VI number to get information for. */ | |
5260 | #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 | |
5261 | ||
5262 | /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ | |
5263 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 | |
5264 | /* Transaction processing steering hint 1 for use with the Rx Queue. */ | |
5265 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 | |
5266 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 | |
5267 | /* Transaction processing steering hint 2 for use with the Ev Queue. */ | |
5268 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 | |
5269 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 | |
5270 | /* Use Relaxed ordering model for TLPs on this VI. */ | |
5271 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 | |
5272 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 | |
5273 | /* Use ID based ordering for TLPs on this VI. */ | |
5274 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 | |
5275 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 | |
5276 | /* Set no snoop bit for TLPs on this VI. */ | |
5277 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 | |
5278 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 | |
5279 | /* Enable TPH for TLPs on this VI. */ | |
5280 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 | |
5281 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 | |
5282 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 | |
5283 | ||
5284 | ||
5285 | /***********************************/ | |
5286 | /* MC_CMD_SET_VI_TLP_PROCESSING | |
5287 | * Set TLP steering and ordering information for a VI. | |
5288 | */ | |
5289 | #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 | |
5290 | ||
75122ec8 SS |
5291 | #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5292 | ||
f2b0befd BH |
5293 | /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ |
5294 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 | |
5295 | /* VI number to set information for. */ | |
5296 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 | |
5297 | /* Transaction processing steering hint 1 for use with the Rx Queue. */ | |
5298 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 | |
5299 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 | |
5300 | /* Transaction processing steering hint 2 for use with the Ev Queue. */ | |
5301 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 | |
5302 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 | |
5303 | /* Use Relaxed ordering model for TLPs on this VI. */ | |
5304 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 | |
5305 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 | |
5306 | /* Use ID based ordering for TLPs on this VI. */ | |
5307 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 | |
5308 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 | |
5309 | /* Set the no snoop bit for TLPs on this VI. */ | |
5310 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 | |
5311 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 | |
5312 | /* Enable TPH for TLPs on this VI. */ | |
5313 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 | |
5314 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 | |
5315 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 | |
5316 | ||
5317 | /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ | |
5318 | #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 | |
5319 | ||
5320 | ||
5321 | /***********************************/ | |
5322 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS | |
5323 | * Get global PCIe steering and transaction processing configuration. | |
5324 | */ | |
5325 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc | |
5326 | ||
75122ec8 SS |
5327 | #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
5328 | ||
f2b0befd BH |
5329 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ |
5330 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 | |
5331 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 | |
5332 | /* enum: MISC. */ | |
5333 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 | |
5334 | /* enum: IDO. */ | |
5335 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 | |
5336 | /* enum: RO. */ | |
5337 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 | |
5338 | /* enum: TPH Type. */ | |
5339 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 | |
5340 | ||
5341 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ | |
5342 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 | |
5343 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 | |
5344 | /* Enum values, see field(s): */ | |
5345 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ | |
5346 | /* Amalgamated TLP info word. */ | |
5347 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 | |
5348 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 | |
5349 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 | |
5350 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 | |
5351 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 | |
5352 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 | |
5353 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 | |
5354 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 | |
5355 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 | |
5356 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 | |
5357 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 | |
5358 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 | |
5359 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 | |
5360 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 | |
5361 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 | |
5362 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 | |
5363 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 | |
5364 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 | |
5365 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 | |
5366 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 | |
5367 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 | |
5368 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 | |
5369 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 | |
5370 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 | |
5371 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 | |
5372 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 | |
5373 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 | |
5374 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 | |
5375 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 | |
5376 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 | |
5377 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 | |
5378 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 | |
5379 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 | |
5380 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 | |
5381 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 | |
5382 | ||
5383 | ||
5384 | /***********************************/ | |
5385 | /* MC_CMD_SET_TLP_PROCESSING_GLOBALS | |
5386 | * Set global PCIe steering and transaction processing configuration. | |
5387 | */ | |
5388 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd | |
5389 | ||
75122ec8 SS |
5390 | #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
5391 | ||
f2b0befd BH |
5392 | /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ |
5393 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 | |
5394 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 | |
5395 | /* Enum values, see field(s): */ | |
5396 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ | |
5397 | /* Amalgamated TLP info word. */ | |
5398 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 | |
5399 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 | |
5400 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 | |
5401 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 | |
5402 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 | |
5403 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 | |
5404 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 | |
5405 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 | |
5406 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 | |
5407 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 | |
5408 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 | |
5409 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 | |
5410 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 | |
5411 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 | |
5412 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 | |
5413 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 | |
5414 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 | |
5415 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 | |
5416 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 | |
5417 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 | |
5418 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 | |
5419 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 | |
5420 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 | |
5421 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 | |
5422 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 | |
5423 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 | |
5424 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 | |
5425 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 | |
5426 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 | |
5427 | ||
5428 | /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ | |
5429 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 | |
5430 | ||
5431 | ||
5432 | /***********************************/ | |
5433 | /* MC_CMD_SATELLITE_DOWNLOAD | |
5434 | * Download a new set of images to the satellite CPUs from the host. | |
5435 | */ | |
5436 | #define MC_CMD_SATELLITE_DOWNLOAD 0x91 | |
5437 | ||
75122ec8 SS |
5438 | #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
5439 | ||
f2b0befd BH |
5440 | /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs |
5441 | * are subtle, and so downloads must proceed in a number of phases. | |
5442 | * | |
5443 | * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. | |
5444 | * | |
5445 | * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download | |
5446 | * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should | |
5447 | * be a checksum (a simple 32-bit sum) of the transferred data. An individual | |
5448 | * download may be aborted using CHUNK_ID_ABORT. | |
5449 | * | |
5450 | * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), | |
5451 | * similar to PHASE_IMEMS. | |
5452 | * | |
5453 | * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. | |
5454 | * | |
5455 | * After any error (a requested abort is not considered to be an error) the | |
5456 | * sequence must be restarted from PHASE_RESET. | |
5457 | */ | |
5458 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 | |
5459 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 | |
5460 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) | |
5461 | /* Download phase. (Note: the IDLE phase is used internally and is never valid | |
5462 | * in a command from the host.) | |
5463 | */ | |
5464 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 | |
5465 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ | |
5466 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ | |
5467 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ | |
5468 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ | |
5469 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ | |
5470 | /* Target for download. (These match the blob numbers defined in | |
5471 | * mc_flash_layout.h.) | |
5472 | */ | |
5473 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 | |
5474 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
5475 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 | |
5476 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
5477 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 | |
5478 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
5479 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 | |
5480 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
5481 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 | |
5482 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
5483 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 | |
5484 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
5485 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 | |
5486 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
5487 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 | |
5488 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
5489 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 | |
5490 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
5491 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 | |
5492 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
5493 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 | |
5494 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
5495 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa | |
5496 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
5497 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb | |
5498 | /* enum: Valid in phase 3 (PHASE_VECTORS) only */ | |
5499 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc | |
5500 | /* enum: Valid in phase 3 (PHASE_VECTORS) only */ | |
5501 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd | |
5502 | /* enum: Valid in phase 3 (PHASE_VECTORS) only */ | |
5503 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe | |
5504 | /* enum: Valid in phase 3 (PHASE_VECTORS) only */ | |
5505 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf | |
5506 | /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ | |
5507 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff | |
5508 | /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ | |
5509 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 | |
5510 | /* enum: Last chunk, containing checksum rather than data */ | |
5511 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff | |
5512 | /* enum: Abort download of this item */ | |
5513 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe | |
5514 | /* Length of this chunk in bytes */ | |
5515 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 | |
5516 | /* Data for this chunk */ | |
5517 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 | |
5518 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 | |
5519 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 | |
5520 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 | |
5521 | ||
5522 | /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ | |
5523 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 | |
5524 | /* Same as MC_CMD_ERR field, but included as 0 in success cases */ | |
5525 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 | |
5526 | /* Extra status information */ | |
5527 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 | |
5528 | /* enum: Code download OK, completed. */ | |
5529 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 | |
5530 | /* enum: Code download aborted as requested. */ | |
5531 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 | |
5532 | /* enum: Code download OK so far, send next chunk. */ | |
5533 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 | |
5534 | /* enum: Download phases out of sequence */ | |
5535 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 | |
5536 | /* enum: Bad target for this phase */ | |
5537 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 | |
5538 | /* enum: Chunk ID out of sequence */ | |
5539 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 | |
5540 | /* enum: Chunk length zero or too large */ | |
5541 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 | |
5542 | /* enum: Checksum was incorrect */ | |
5543 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 | |
5544 | ||
5545 | ||
5546 | /***********************************/ | |
5547 | /* MC_CMD_GET_CAPABILITIES | |
5548 | * Get device capabilities. | |
5549 | * | |
5550 | * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to | |
5551 | * reference inherent device capabilities as opposed to current NVRAM config. | |
5552 | */ | |
5553 | #define MC_CMD_GET_CAPABILITIES 0xbe | |
5554 | ||
75122ec8 | 5555 | #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
f2b0befd BH |
5556 | /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ |
5557 | #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 | |
5558 | ||
5559 | /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ | |
5560 | #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 | |
5561 | /* First word of flags. */ | |
5562 | #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 | |
5563 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 | |
5564 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 | |
5565 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 | |
5566 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 | |
5567 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 | |
5568 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 | |
5569 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 | |
5570 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 | |
5571 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 | |
5572 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 | |
5573 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 | |
5574 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 | |
5575 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 | |
5576 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 | |
5577 | #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 | |
5578 | #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 | |
2ca10a75 MS |
5579 | #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 |
5580 | #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 | |
f2b0befd BH |
5581 | /* RxDPCPU firmware id. */ |
5582 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 | |
5583 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 | |
5584 | /* enum: Standard RXDP firmware */ | |
5585 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 | |
5586 | /* enum: Low latency RXDP firmware */ | |
5587 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 | |
5588 | /* enum: RXDP Test firmware image 1 */ | |
5589 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 | |
5590 | /* enum: RXDP Test firmware image 2 */ | |
5591 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 | |
5592 | /* enum: RXDP Test firmware image 3 */ | |
5593 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 | |
5594 | /* enum: RXDP Test firmware image 4 */ | |
5595 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 | |
5596 | /* enum: RXDP Test firmware image 5 */ | |
5597 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 | |
5598 | /* enum: RXDP Test firmware image 6 */ | |
5599 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 | |
5600 | /* enum: RXDP Test firmware image 7 */ | |
5601 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 | |
5602 | /* enum: RXDP Test firmware image 8 */ | |
5603 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 | |
5604 | /* TxDPCPU firmware id. */ | |
5605 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 | |
5606 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 | |
5607 | /* enum: Standard TXDP firmware */ | |
5608 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 | |
5609 | /* enum: Low latency TXDP firmware */ | |
5610 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 | |
5611 | /* enum: TXDP Test firmware image 1 */ | |
5612 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 | |
5613 | /* enum: TXDP Test firmware image 2 */ | |
5614 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 | |
5615 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 | |
5616 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 | |
5617 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 | |
5618 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 | |
5619 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 | |
5620 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 | |
5621 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 /* enum */ | |
5622 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 /* enum */ | |
5623 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 /* enum */ | |
5624 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 /* enum */ | |
5625 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ | |
5626 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 | |
5627 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 | |
5628 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 | |
5629 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 | |
5630 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 | |
5631 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 | |
5632 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 /* enum */ | |
5633 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 /* enum */ | |
5634 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 /* enum */ | |
5635 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 /* enum */ | |
5636 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ | |
5637 | /* Hardware capabilities of NIC */ | |
5638 | #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 | |
5639 | /* Licensed capabilities */ | |
5640 | #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 | |
5641 | ||
5642 | ||
5643 | /***********************************/ | |
5644 | /* MC_CMD_V2_EXTN | |
5645 | * Encapsulation for a v2 extended command | |
5646 | */ | |
5647 | #define MC_CMD_V2_EXTN 0x7f | |
5648 | ||
5649 | /* MC_CMD_V2_EXTN_IN msgrequest */ | |
5650 | #define MC_CMD_V2_EXTN_IN_LEN 4 | |
5651 | /* the extended command number */ | |
5652 | #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 | |
5653 | #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 | |
5654 | #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 | |
5655 | #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 | |
5656 | /* the actual length of the encapsulated command (which is not in the v1 | |
5657 | * header) | |
5658 | */ | |
5659 | #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 | |
5660 | #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 | |
5661 | #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 | |
5662 | #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 | |
5663 | ||
5664 | ||
5665 | /***********************************/ | |
5666 | /* MC_CMD_TCM_BUCKET_ALLOC | |
5667 | * Allocate a pacer bucket (for qau rp or a snapper test) | |
5668 | */ | |
5669 | #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 | |
5670 | ||
75122ec8 SS |
5671 | #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5672 | ||
f2b0befd BH |
5673 | /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ |
5674 | #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 | |
5675 | ||
5676 | /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ | |
5677 | #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 | |
5678 | /* the bucket id */ | |
5679 | #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 | |
5680 | ||
5681 | ||
5682 | /***********************************/ | |
5683 | /* MC_CMD_TCM_BUCKET_FREE | |
5684 | * Free a pacer bucket | |
5685 | */ | |
5686 | #define MC_CMD_TCM_BUCKET_FREE 0xb3 | |
5687 | ||
75122ec8 SS |
5688 | #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5689 | ||
f2b0befd BH |
5690 | /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ |
5691 | #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 | |
5692 | /* the bucket id */ | |
5693 | #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 | |
5694 | ||
5695 | /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ | |
5696 | #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 | |
5697 | ||
5698 | ||
5699 | /***********************************/ | |
5700 | /* MC_CMD_TCM_BUCKET_INIT | |
5701 | * Initialise pacer bucket with a given rate | |
5702 | */ | |
5703 | #define MC_CMD_TCM_BUCKET_INIT 0xb4 | |
5704 | ||
75122ec8 SS |
5705 | #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5706 | ||
f2b0befd BH |
5707 | /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ |
5708 | #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 | |
5709 | /* the bucket id */ | |
5710 | #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 | |
5711 | /* the rate in mbps */ | |
5712 | #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 | |
5713 | ||
5714 | /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ | |
5715 | #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 | |
5716 | ||
5717 | ||
5718 | /***********************************/ | |
5719 | /* MC_CMD_TCM_TXQ_INIT | |
5720 | * Initialise txq in pacer with given options or set options | |
5721 | */ | |
5722 | #define MC_CMD_TCM_TXQ_INIT 0xb5 | |
5723 | ||
75122ec8 SS |
5724 | #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5725 | ||
f2b0befd BH |
5726 | /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ |
5727 | #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 | |
5728 | /* the txq id */ | |
5729 | #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 | |
5730 | /* the static priority associated with the txq */ | |
5731 | #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 | |
5732 | /* bitmask of the priority queues this txq is inserted into */ | |
5733 | #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 | |
5734 | /* the reaction point (RP) bucket */ | |
5735 | #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 | |
5736 | /* an already reserved bucket (typically set to bucket associated with outer | |
5737 | * vswitch) | |
5738 | */ | |
5739 | #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 | |
5740 | /* an already reserved bucket (typically set to bucket associated with inner | |
5741 | * vswitch) | |
5742 | */ | |
5743 | #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 | |
5744 | /* the min bucket (typically for ETS/minimum bandwidth) */ | |
5745 | #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 | |
5746 | ||
5747 | /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ | |
5748 | #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 | |
5749 | ||
5750 | ||
5751 | /***********************************/ | |
5752 | /* MC_CMD_LINK_PIOBUF | |
5753 | * Link a push I/O buffer to a TxQ | |
5754 | */ | |
5755 | #define MC_CMD_LINK_PIOBUF 0x92 | |
5756 | ||
75122ec8 SS |
5757 | #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
5758 | ||
f2b0befd BH |
5759 | /* MC_CMD_LINK_PIOBUF_IN msgrequest */ |
5760 | #define MC_CMD_LINK_PIOBUF_IN_LEN 8 | |
5761 | /* Handle for allocated push I/O buffer. */ | |
5762 | #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 | |
5763 | /* Function Local Instance (VI) number. */ | |
5764 | #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 | |
5765 | ||
5766 | /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ | |
5767 | #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 | |
5768 | ||
5769 | ||
5770 | /***********************************/ | |
5771 | /* MC_CMD_UNLINK_PIOBUF | |
5772 | * Unlink a push I/O buffer from a TxQ | |
5773 | */ | |
5774 | #define MC_CMD_UNLINK_PIOBUF 0x93 | |
5775 | ||
75122ec8 SS |
5776 | #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
5777 | ||
f2b0befd BH |
5778 | /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ |
5779 | #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 | |
5780 | /* Function Local Instance (VI) number. */ | |
5781 | #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 | |
5782 | ||
5783 | /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ | |
5784 | #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 | |
5785 | ||
5786 | ||
5787 | /***********************************/ | |
5788 | /* MC_CMD_VSWITCH_ALLOC | |
5789 | * allocate and initialise a v-switch. | |
5790 | */ | |
5791 | #define MC_CMD_VSWITCH_ALLOC 0x94 | |
5792 | ||
75122ec8 SS |
5793 | #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5794 | ||
f2b0befd BH |
5795 | /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ |
5796 | #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 | |
5797 | /* The port to connect to the v-switch's upstream port. */ | |
5798 | #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
5799 | /* The type of v-switch to create. */ | |
5800 | #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 | |
5801 | /* enum: VLAN */ | |
5802 | #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 | |
5803 | /* enum: VEB */ | |
5804 | #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 | |
5805 | /* enum: VEPA */ | |
5806 | #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 | |
5807 | /* Flags controlling v-port creation */ | |
5808 | #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 | |
5809 | #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 | |
5810 | #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 | |
5811 | /* The number of VLAN tags to support. */ | |
5812 | #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 | |
5813 | ||
5814 | /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ | |
5815 | #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 | |
5816 | ||
5817 | ||
5818 | /***********************************/ | |
5819 | /* MC_CMD_VSWITCH_FREE | |
5820 | * de-allocate a v-switch. | |
5821 | */ | |
5822 | #define MC_CMD_VSWITCH_FREE 0x95 | |
5823 | ||
75122ec8 SS |
5824 | #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5825 | ||
f2b0befd BH |
5826 | /* MC_CMD_VSWITCH_FREE_IN msgrequest */ |
5827 | #define MC_CMD_VSWITCH_FREE_IN_LEN 4 | |
5828 | /* The port to which the v-switch is connected. */ | |
5829 | #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 | |
5830 | ||
5831 | /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ | |
5832 | #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 | |
5833 | ||
5834 | ||
5835 | /***********************************/ | |
5836 | /* MC_CMD_VPORT_ALLOC | |
5837 | * allocate a v-port. | |
5838 | */ | |
5839 | #define MC_CMD_VPORT_ALLOC 0x96 | |
5840 | ||
75122ec8 SS |
5841 | #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5842 | ||
f2b0befd BH |
5843 | /* MC_CMD_VPORT_ALLOC_IN msgrequest */ |
5844 | #define MC_CMD_VPORT_ALLOC_IN_LEN 20 | |
5845 | /* The port to which the v-switch is connected. */ | |
5846 | #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
5847 | /* The type of the new v-port. */ | |
5848 | #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 | |
5849 | /* enum: VLAN (obsolete) */ | |
5850 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 | |
5851 | /* enum: VEB (obsolete) */ | |
5852 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 | |
5853 | /* enum: VEPA (obsolete) */ | |
5854 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 | |
5855 | /* enum: A normal v-port receives packets which match a specified MAC and/or | |
5856 | * VLAN. | |
5857 | */ | |
5858 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 | |
5859 | /* enum: An expansion v-port packets traffic which don't match any other | |
5860 | * v-port. | |
5861 | */ | |
5862 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 | |
5863 | /* enum: An test v-port receives packets which match any filters installed by | |
5864 | * its downstream components. | |
5865 | */ | |
5866 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 | |
5867 | /* Flags controlling v-port creation */ | |
5868 | #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 | |
5869 | #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 | |
5870 | #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 | |
5871 | /* The number of VLAN tags to insert/remove. */ | |
5872 | #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 | |
5873 | /* The actual VLAN tags to insert/remove */ | |
5874 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 | |
5875 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 | |
5876 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 | |
5877 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 | |
5878 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 | |
5879 | ||
5880 | /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ | |
5881 | #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 | |
5882 | /* The handle of the new v-port */ | |
5883 | #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 | |
5884 | ||
5885 | ||
5886 | /***********************************/ | |
5887 | /* MC_CMD_VPORT_FREE | |
5888 | * de-allocate a v-port. | |
5889 | */ | |
5890 | #define MC_CMD_VPORT_FREE 0x97 | |
5891 | ||
75122ec8 SS |
5892 | #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5893 | ||
f2b0befd BH |
5894 | /* MC_CMD_VPORT_FREE_IN msgrequest */ |
5895 | #define MC_CMD_VPORT_FREE_IN_LEN 4 | |
5896 | /* The handle of the v-port */ | |
5897 | #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 | |
5898 | ||
5899 | /* MC_CMD_VPORT_FREE_OUT msgresponse */ | |
5900 | #define MC_CMD_VPORT_FREE_OUT_LEN 0 | |
5901 | ||
5902 | ||
5903 | /***********************************/ | |
5904 | /* MC_CMD_VADAPTOR_ALLOC | |
5905 | * allocate a v-adaptor. | |
5906 | */ | |
5907 | #define MC_CMD_VADAPTOR_ALLOC 0x98 | |
5908 | ||
75122ec8 SS |
5909 | #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5910 | ||
f2b0befd | 5911 | /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ |
af6a074d | 5912 | #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 |
f2b0befd BH |
5913 | /* The port to connect to the v-adaptor's port. */ |
5914 | #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
5915 | /* Flags controlling v-adaptor creation */ | |
5916 | #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 | |
5917 | #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 | |
5918 | #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 | |
5919 | /* The number of VLAN tags to strip on receive */ | |
5920 | #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 | |
af6a074d SS |
5921 | /* The number of VLAN tags to transparently insert/remove. */ |
5922 | #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 | |
5923 | /* The actual VLAN tags to insert/remove */ | |
5924 | #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 | |
5925 | #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 | |
5926 | #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 | |
5927 | #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 | |
5928 | #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 | |
5929 | /* The MAC address to assign to this v-adaptor */ | |
5930 | #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 | |
5931 | #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 | |
5932 | /* enum: Derive the MAC address from the upstream port */ | |
5933 | #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 | |
f2b0befd BH |
5934 | |
5935 | /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ | |
5936 | #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 | |
5937 | ||
5938 | ||
5939 | /***********************************/ | |
5940 | /* MC_CMD_VADAPTOR_FREE | |
5941 | * de-allocate a v-adaptor. | |
5942 | */ | |
5943 | #define MC_CMD_VADAPTOR_FREE 0x99 | |
5944 | ||
75122ec8 SS |
5945 | #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5946 | ||
f2b0befd BH |
5947 | /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ |
5948 | #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 | |
5949 | /* The port to which the v-adaptor is connected. */ | |
5950 | #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 | |
5951 | ||
5952 | /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ | |
5953 | #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 | |
5954 | ||
5955 | ||
910c8789 SS |
5956 | /***********************************/ |
5957 | /* MC_CMD_VADAPTOR_SET_MAC | |
5958 | * assign a new MAC address to a v-adaptor. | |
5959 | */ | |
5960 | #define MC_CMD_VADAPTOR_SET_MAC 0x5d | |
5961 | ||
5962 | #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
5963 | ||
5964 | /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ | |
5965 | #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 | |
5966 | /* The port to which the v-adaptor is connected. */ | |
5967 | #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 | |
5968 | /* The new MAC address to assign to this v-adaptor */ | |
5969 | #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 | |
5970 | #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 | |
5971 | ||
5972 | /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ | |
5973 | #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 | |
5974 | ||
5975 | ||
5976 | /***********************************/ | |
5977 | /* MC_CMD_VADAPTOR_GET_MAC | |
5978 | * read the MAC address assigned to a v-adaptor. | |
5979 | */ | |
5980 | #define MC_CMD_VADAPTOR_GET_MAC 0x5e | |
5981 | ||
5982 | #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
5983 | ||
5984 | /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ | |
5985 | #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 | |
5986 | /* The port to which the v-adaptor is connected. */ | |
5987 | #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 | |
5988 | ||
5989 | /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ | |
5990 | #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 | |
5991 | /* The MAC address assigned to this v-adaptor */ | |
5992 | #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 | |
5993 | #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 | |
5994 | ||
5995 | ||
f2b0befd BH |
5996 | /***********************************/ |
5997 | /* MC_CMD_EVB_PORT_ASSIGN | |
5998 | * assign a port to a PCI function. | |
5999 | */ | |
6000 | #define MC_CMD_EVB_PORT_ASSIGN 0x9a | |
6001 | ||
75122ec8 SS |
6002 | #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6003 | ||
f2b0befd BH |
6004 | /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ |
6005 | #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 | |
6006 | /* The port to assign. */ | |
6007 | #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 | |
6008 | /* The target function to modify. */ | |
6009 | #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 | |
6010 | #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 | |
6011 | #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 | |
6012 | #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 | |
6013 | #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 | |
6014 | ||
6015 | /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ | |
6016 | #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 | |
6017 | ||
6018 | ||
6019 | /***********************************/ | |
6020 | /* MC_CMD_RDWR_A64_REGIONS | |
6021 | * Assign the 64 bit region addresses. | |
6022 | */ | |
6023 | #define MC_CMD_RDWR_A64_REGIONS 0x9b | |
6024 | ||
75122ec8 SS |
6025 | #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
6026 | ||
f2b0befd BH |
6027 | /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ |
6028 | #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 | |
6029 | #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 | |
6030 | #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 | |
6031 | #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 | |
6032 | #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 | |
6033 | /* Write enable bits 0-3, set to write, clear to read. */ | |
6034 | #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 | |
6035 | #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 | |
6036 | #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 | |
6037 | #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 | |
6038 | ||
6039 | /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included | |
6040 | * regardless of state of write bits in the request. | |
6041 | */ | |
6042 | #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 | |
6043 | #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 | |
6044 | #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 | |
6045 | #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 | |
6046 | #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 | |
6047 | ||
6048 | ||
6049 | /***********************************/ | |
6050 | /* MC_CMD_ONLOAD_STACK_ALLOC | |
6051 | * Allocate an Onload stack ID. | |
6052 | */ | |
6053 | #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c | |
6054 | ||
75122ec8 SS |
6055 | #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
6056 | ||
f2b0befd BH |
6057 | /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ |
6058 | #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 | |
6059 | /* The handle of the owning upstream port */ | |
6060 | #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
6061 | ||
6062 | /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ | |
6063 | #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 | |
6064 | /* The handle of the new Onload stack */ | |
6065 | #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 | |
6066 | ||
6067 | ||
6068 | /***********************************/ | |
6069 | /* MC_CMD_ONLOAD_STACK_FREE | |
6070 | * Free an Onload stack ID. | |
6071 | */ | |
6072 | #define MC_CMD_ONLOAD_STACK_FREE 0x9d | |
6073 | ||
75122ec8 SS |
6074 | #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
6075 | ||
f2b0befd BH |
6076 | /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ |
6077 | #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 | |
6078 | /* The handle of the Onload stack */ | |
6079 | #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 | |
6080 | ||
6081 | /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ | |
6082 | #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 | |
6083 | ||
6084 | ||
6085 | /***********************************/ | |
6086 | /* MC_CMD_RSS_CONTEXT_ALLOC | |
6087 | * Allocate an RSS context. | |
6088 | */ | |
6089 | #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e | |
6090 | ||
75122ec8 SS |
6091 | #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6092 | ||
f2b0befd BH |
6093 | /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ |
6094 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 | |
6095 | /* The handle of the owning upstream port */ | |
6096 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
6097 | /* The type of context to allocate */ | |
6098 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 | |
6099 | /* enum: Allocate a context for exclusive use. The key and indirection table | |
6100 | * must be explicitly configured. | |
6101 | */ | |
6102 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 | |
6103 | /* enum: Allocate a context for shared use; this will spread across a range of | |
6104 | * queues, but the key and indirection table are pre-configured and may not be | |
6105 | * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. | |
6106 | */ | |
6107 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 | |
6108 | /* Number of queues spanned by this context, in the range 1-64; valid offsets | |
6109 | * in the indirection table will be in the range 0 to NUM_QUEUES-1. | |
6110 | */ | |
6111 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 | |
6112 | ||
6113 | /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ | |
6114 | #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 | |
6115 | /* The handle of the new RSS context */ | |
6116 | #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 | |
6117 | ||
6118 | ||
6119 | /***********************************/ | |
6120 | /* MC_CMD_RSS_CONTEXT_FREE | |
6121 | * Free an RSS context. | |
6122 | */ | |
6123 | #define MC_CMD_RSS_CONTEXT_FREE 0x9f | |
6124 | ||
75122ec8 SS |
6125 | #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6126 | ||
f2b0befd BH |
6127 | /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ |
6128 | #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 | |
6129 | /* The handle of the RSS context */ | |
6130 | #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 | |
6131 | ||
6132 | /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ | |
6133 | #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 | |
6134 | ||
6135 | ||
6136 | /***********************************/ | |
6137 | /* MC_CMD_RSS_CONTEXT_SET_KEY | |
6138 | * Set the Toeplitz hash key for an RSS context. | |
6139 | */ | |
6140 | #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 | |
6141 | ||
75122ec8 SS |
6142 | #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6143 | ||
f2b0befd BH |
6144 | /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ |
6145 | #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 | |
6146 | /* The handle of the RSS context */ | |
6147 | #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 | |
6148 | /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ | |
6149 | #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 | |
6150 | #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 | |
6151 | ||
6152 | /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ | |
6153 | #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 | |
6154 | ||
6155 | ||
6156 | /***********************************/ | |
6157 | /* MC_CMD_RSS_CONTEXT_GET_KEY | |
6158 | * Get the Toeplitz hash key for an RSS context. | |
6159 | */ | |
6160 | #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 | |
6161 | ||
75122ec8 SS |
6162 | #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6163 | ||
f2b0befd BH |
6164 | /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ |
6165 | #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 | |
6166 | /* The handle of the RSS context */ | |
6167 | #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 | |
6168 | ||
6169 | /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ | |
6170 | #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 | |
6171 | /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ | |
6172 | #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 | |
6173 | #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 | |
6174 | ||
6175 | ||
6176 | /***********************************/ | |
6177 | /* MC_CMD_RSS_CONTEXT_SET_TABLE | |
6178 | * Set the indirection table for an RSS context. | |
6179 | */ | |
6180 | #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 | |
6181 | ||
75122ec8 SS |
6182 | #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6183 | ||
f2b0befd BH |
6184 | /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ |
6185 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 | |
6186 | /* The handle of the RSS context */ | |
6187 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 | |
6188 | /* The 128-byte indirection table (1 byte per entry) */ | |
6189 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 | |
6190 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 | |
6191 | ||
6192 | /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ | |
6193 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 | |
6194 | ||
6195 | ||
6196 | /***********************************/ | |
6197 | /* MC_CMD_RSS_CONTEXT_GET_TABLE | |
6198 | * Get the indirection table for an RSS context. | |
6199 | */ | |
6200 | #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 | |
6201 | ||
75122ec8 SS |
6202 | #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6203 | ||
f2b0befd BH |
6204 | /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ |
6205 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 | |
6206 | /* The handle of the RSS context */ | |
6207 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 | |
6208 | ||
6209 | /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ | |
6210 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 | |
6211 | /* The 128-byte indirection table (1 byte per entry) */ | |
6212 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 | |
6213 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 | |
6214 | ||
6215 | ||
6216 | /***********************************/ | |
6217 | /* MC_CMD_RSS_CONTEXT_SET_FLAGS | |
6218 | * Set various control flags for an RSS context. | |
6219 | */ | |
6220 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 | |
6221 | ||
75122ec8 SS |
6222 | #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6223 | ||
f2b0befd BH |
6224 | /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ |
6225 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 | |
6226 | /* The handle of the RSS context */ | |
6227 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 | |
6228 | /* Hash control flags */ | |
6229 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 | |
6230 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 | |
6231 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 | |
6232 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 | |
6233 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 | |
6234 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 | |
6235 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 | |
6236 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 | |
6237 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 | |
6238 | ||
6239 | /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ | |
6240 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 | |
6241 | ||
6242 | ||
6243 | /***********************************/ | |
6244 | /* MC_CMD_RSS_CONTEXT_GET_FLAGS | |
6245 | * Get various control flags for an RSS context. | |
6246 | */ | |
6247 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 | |
6248 | ||
75122ec8 SS |
6249 | #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6250 | ||
f2b0befd BH |
6251 | /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ |
6252 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 | |
6253 | /* The handle of the RSS context */ | |
6254 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 | |
6255 | ||
6256 | /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ | |
6257 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 | |
6258 | /* Hash control flags */ | |
6259 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 | |
6260 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 | |
6261 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 | |
6262 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 | |
6263 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 | |
6264 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 | |
6265 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 | |
6266 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 | |
6267 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 | |
6268 | ||
6269 | ||
6270 | /***********************************/ | |
6271 | /* MC_CMD_DOT1P_MAPPING_ALLOC | |
6272 | * Allocate a .1p mapping. | |
6273 | */ | |
6274 | #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 | |
6275 | ||
75122ec8 SS |
6276 | #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
6277 | ||
f2b0befd BH |
6278 | /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ |
6279 | #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 | |
6280 | /* The handle of the owning upstream port */ | |
6281 | #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
6282 | /* Number of queues spanned by this mapping, in the range 1-64; valid fixed | |
6283 | * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and | |
6284 | * referenced RSS contexts must span no more than this number. | |
6285 | */ | |
6286 | #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 | |
6287 | ||
6288 | /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ | |
6289 | #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 | |
6290 | /* The handle of the new .1p mapping */ | |
6291 | #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 | |
6292 | ||
6293 | ||
6294 | /***********************************/ | |
6295 | /* MC_CMD_DOT1P_MAPPING_FREE | |
6296 | * Free a .1p mapping. | |
6297 | */ | |
6298 | #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 | |
6299 | ||
75122ec8 SS |
6300 | #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
6301 | ||
f2b0befd BH |
6302 | /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ |
6303 | #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 | |
6304 | /* The handle of the .1p mapping */ | |
6305 | #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 | |
6306 | ||
6307 | /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ | |
6308 | #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 | |
6309 | ||
6310 | ||
6311 | /***********************************/ | |
6312 | /* MC_CMD_DOT1P_MAPPING_SET_TABLE | |
6313 | * Set the mapping table for a .1p mapping. | |
6314 | */ | |
6315 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 | |
6316 | ||
75122ec8 SS |
6317 | #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
6318 | ||
f2b0befd BH |
6319 | /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ |
6320 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 | |
6321 | /* The handle of the .1p mapping */ | |
6322 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 | |
6323 | /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context | |
6324 | * handle) | |
6325 | */ | |
6326 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 | |
6327 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 | |
6328 | ||
6329 | /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ | |
6330 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 | |
6331 | ||
6332 | ||
6333 | /***********************************/ | |
6334 | /* MC_CMD_DOT1P_MAPPING_GET_TABLE | |
6335 | * Get the mapping table for a .1p mapping. | |
6336 | */ | |
6337 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 | |
6338 | ||
75122ec8 SS |
6339 | #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
6340 | ||
f2b0befd BH |
6341 | /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ |
6342 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 | |
6343 | /* The handle of the .1p mapping */ | |
6344 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 | |
6345 | ||
6346 | /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ | |
6347 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 | |
6348 | /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context | |
6349 | * handle) | |
6350 | */ | |
6351 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 | |
6352 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 | |
6353 | ||
6354 | ||
6355 | /***********************************/ | |
6356 | /* MC_CMD_GET_VECTOR_CFG | |
6357 | * Get Interrupt Vector config for this PF. | |
6358 | */ | |
6359 | #define MC_CMD_GET_VECTOR_CFG 0xbf | |
6360 | ||
75122ec8 SS |
6361 | #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6362 | ||
f2b0befd BH |
6363 | /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ |
6364 | #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 | |
6365 | ||
6366 | /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ | |
6367 | #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 | |
6368 | /* Base absolute interrupt vector number. */ | |
6369 | #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 | |
6370 | /* Number of interrupt vectors allocate to this PF. */ | |
6371 | #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 | |
6372 | /* Number of interrupt vectors to allocate per VF. */ | |
6373 | #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 | |
6374 | ||
6375 | ||
6376 | /***********************************/ | |
6377 | /* MC_CMD_SET_VECTOR_CFG | |
6378 | * Set Interrupt Vector config for this PF. | |
6379 | */ | |
6380 | #define MC_CMD_SET_VECTOR_CFG 0xc0 | |
6381 | ||
75122ec8 SS |
6382 | #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6383 | ||
f2b0befd BH |
6384 | /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ |
6385 | #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 | |
6386 | /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to | |
6387 | * let the system find a suitable base. | |
6388 | */ | |
6389 | #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 | |
6390 | /* Number of interrupt vectors allocate to this PF. */ | |
6391 | #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 | |
6392 | /* Number of interrupt vectors to allocate per VF. */ | |
6393 | #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 | |
6394 | ||
6395 | /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ | |
6396 | #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 | |
6397 | ||
6398 | ||
6399 | /***********************************/ | |
6400 | /* MC_CMD_RMON_RX_CLASS_STATS | |
6401 | * Retrieve rmon rx class statistics | |
6402 | */ | |
6403 | #define MC_CMD_RMON_RX_CLASS_STATS 0xc3 | |
6404 | ||
6405 | /* MC_CMD_RMON_RX_CLASS_STATS_IN msgrequest */ | |
6406 | #define MC_CMD_RMON_RX_CLASS_STATS_IN_LEN 4 | |
6407 | /* flags */ | |
6408 | #define MC_CMD_RMON_RX_CLASS_STATS_IN_FLAGS_OFST 0 | |
6409 | #define MC_CMD_RMON_RX_CLASS_STATS_IN_CLASS_LBN 0 | |
6410 | #define MC_CMD_RMON_RX_CLASS_STATS_IN_CLASS_WIDTH 8 | |
6411 | #define MC_CMD_RMON_RX_CLASS_STATS_IN_RST_LBN 8 | |
6412 | #define MC_CMD_RMON_RX_CLASS_STATS_IN_RST_WIDTH 1 | |
6413 | ||
6414 | /* MC_CMD_RMON_RX_CLASS_STATS_OUT msgresponse */ | |
6415 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_LENMIN 4 | |
6416 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_LENMAX 252 | |
6417 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_LEN(num) (0+4*(num)) | |
6418 | /* Array of stats */ | |
6419 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_OFST 0 | |
6420 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_LEN 4 | |
6421 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_MINNUM 1 | |
6422 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_MAXNUM 63 | |
6423 | ||
6424 | ||
6425 | /***********************************/ | |
6426 | /* MC_CMD_RMON_TX_CLASS_STATS | |
6427 | * Retrieve rmon tx class statistics | |
6428 | */ | |
6429 | #define MC_CMD_RMON_TX_CLASS_STATS 0xc4 | |
6430 | ||
6431 | /* MC_CMD_RMON_TX_CLASS_STATS_IN msgrequest */ | |
6432 | #define MC_CMD_RMON_TX_CLASS_STATS_IN_LEN 4 | |
6433 | /* flags */ | |
6434 | #define MC_CMD_RMON_TX_CLASS_STATS_IN_FLAGS_OFST 0 | |
6435 | #define MC_CMD_RMON_TX_CLASS_STATS_IN_CLASS_LBN 0 | |
6436 | #define MC_CMD_RMON_TX_CLASS_STATS_IN_CLASS_WIDTH 8 | |
6437 | #define MC_CMD_RMON_TX_CLASS_STATS_IN_RST_LBN 8 | |
6438 | #define MC_CMD_RMON_TX_CLASS_STATS_IN_RST_WIDTH 1 | |
6439 | ||
6440 | /* MC_CMD_RMON_TX_CLASS_STATS_OUT msgresponse */ | |
6441 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_LENMIN 4 | |
6442 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_LENMAX 252 | |
6443 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_LEN(num) (0+4*(num)) | |
6444 | /* Array of stats */ | |
6445 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_OFST 0 | |
6446 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_LEN 4 | |
6447 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_MINNUM 1 | |
6448 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_MAXNUM 63 | |
6449 | ||
6450 | ||
6451 | /***********************************/ | |
6452 | /* MC_CMD_RMON_RX_SUPER_CLASS_STATS | |
6453 | * Retrieve rmon rx super_class statistics | |
6454 | */ | |
6455 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS 0xc5 | |
6456 | ||
6457 | /* MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN msgrequest */ | |
6458 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_LEN 4 | |
6459 | /* flags */ | |
6460 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_FLAGS_OFST 0 | |
6461 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_SUPER_CLASS_LBN 0 | |
6462 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_SUPER_CLASS_WIDTH 4 | |
6463 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_RST_LBN 4 | |
6464 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_RST_WIDTH 1 | |
6465 | ||
6466 | /* MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT msgresponse */ | |
6467 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LENMIN 4 | |
6468 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LENMAX 252 | |
6469 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LEN(num) (0+4*(num)) | |
6470 | /* Array of stats */ | |
6471 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_OFST 0 | |
6472 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_LEN 4 | |
6473 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_MINNUM 1 | |
6474 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_MAXNUM 63 | |
6475 | ||
6476 | ||
6477 | /***********************************/ | |
6478 | /* MC_CMD_RMON_TX_SUPER_CLASS_STATS | |
6479 | * Retrieve rmon tx super_class statistics | |
6480 | */ | |
6481 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS 0xc6 | |
6482 | ||
6483 | /* MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN msgrequest */ | |
6484 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_LEN 4 | |
6485 | /* flags */ | |
6486 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_FLAGS_OFST 0 | |
6487 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_SUPER_CLASS_LBN 0 | |
6488 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_SUPER_CLASS_WIDTH 4 | |
6489 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_RST_LBN 4 | |
6490 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_RST_WIDTH 1 | |
6491 | ||
6492 | /* MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT msgresponse */ | |
6493 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LENMIN 4 | |
6494 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LENMAX 252 | |
6495 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LEN(num) (0+4*(num)) | |
6496 | /* Array of stats */ | |
6497 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_OFST 0 | |
6498 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_LEN 4 | |
6499 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_MINNUM 1 | |
6500 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_MAXNUM 63 | |
6501 | ||
6502 | ||
6503 | /***********************************/ | |
6504 | /* MC_CMD_RMON_RX_ADD_QID_TO_CLASS | |
6505 | * Add qid to class for statistics collection | |
6506 | */ | |
6507 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS 0xc7 | |
6508 | ||
6509 | /* MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN msgrequest */ | |
6510 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_LEN 12 | |
6511 | /* class */ | |
6512 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_CLASS_OFST 0 | |
6513 | /* qid */ | |
6514 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_QID_OFST 4 | |
6515 | /* flags */ | |
6516 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8 | |
6517 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0 | |
6518 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4 | |
6519 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4 | |
6520 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4 | |
6521 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_MTU_LBN 8 | |
6522 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14 | |
6523 | ||
6524 | /* MC_CMD_RMON_RX_ADD_QID_TO_CLASS_OUT msgresponse */ | |
6525 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_OUT_LEN 0 | |
6526 | ||
6527 | ||
6528 | /***********************************/ | |
6529 | /* MC_CMD_RMON_TX_ADD_QID_TO_CLASS | |
6530 | * Add qid to class for statistics collection | |
6531 | */ | |
6532 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS 0xc8 | |
6533 | ||
6534 | /* MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN msgrequest */ | |
6535 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_LEN 12 | |
6536 | /* class */ | |
6537 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_CLASS_OFST 0 | |
6538 | /* qid */ | |
6539 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_QID_OFST 4 | |
6540 | /* flags */ | |
6541 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8 | |
6542 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0 | |
6543 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4 | |
6544 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4 | |
6545 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4 | |
6546 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_MTU_LBN 8 | |
6547 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14 | |
6548 | ||
6549 | /* MC_CMD_RMON_TX_ADD_QID_TO_CLASS_OUT msgresponse */ | |
6550 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_OUT_LEN 0 | |
6551 | ||
6552 | ||
6553 | /***********************************/ | |
6554 | /* MC_CMD_RMON_MC_ADD_QID_TO_CLASS | |
6555 | * Add qid to class for statistics collection | |
6556 | */ | |
6557 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS 0xc9 | |
6558 | ||
6559 | /* MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN msgrequest */ | |
6560 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_LEN 12 | |
6561 | /* class */ | |
6562 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_CLASS_OFST 0 | |
6563 | /* qid */ | |
6564 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_QID_OFST 4 | |
6565 | /* flags */ | |
6566 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8 | |
6567 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0 | |
6568 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4 | |
6569 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4 | |
6570 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4 | |
6571 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_MTU_LBN 8 | |
6572 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14 | |
6573 | ||
6574 | /* MC_CMD_RMON_MC_ADD_QID_TO_CLASS_OUT msgresponse */ | |
6575 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_OUT_LEN 0 | |
6576 | ||
6577 | ||
6578 | /***********************************/ | |
6579 | /* MC_CMD_RMON_ALLOC_CLASS | |
6580 | * Allocate an rmon class | |
6581 | */ | |
6582 | #define MC_CMD_RMON_ALLOC_CLASS 0xca | |
6583 | ||
6584 | /* MC_CMD_RMON_ALLOC_CLASS_IN msgrequest */ | |
6585 | #define MC_CMD_RMON_ALLOC_CLASS_IN_LEN 0 | |
6586 | ||
6587 | /* MC_CMD_RMON_ALLOC_CLASS_OUT msgresponse */ | |
6588 | #define MC_CMD_RMON_ALLOC_CLASS_OUT_LEN 4 | |
6589 | /* class */ | |
6590 | #define MC_CMD_RMON_ALLOC_CLASS_OUT_CLASS_OFST 0 | |
6591 | ||
6592 | ||
6593 | /***********************************/ | |
6594 | /* MC_CMD_RMON_DEALLOC_CLASS | |
6595 | * Deallocate an rmon class | |
6596 | */ | |
6597 | #define MC_CMD_RMON_DEALLOC_CLASS 0xcb | |
6598 | ||
6599 | /* MC_CMD_RMON_DEALLOC_CLASS_IN msgrequest */ | |
6600 | #define MC_CMD_RMON_DEALLOC_CLASS_IN_LEN 4 | |
6601 | /* class */ | |
6602 | #define MC_CMD_RMON_DEALLOC_CLASS_IN_CLASS_OFST 0 | |
6603 | ||
6604 | /* MC_CMD_RMON_DEALLOC_CLASS_OUT msgresponse */ | |
6605 | #define MC_CMD_RMON_DEALLOC_CLASS_OUT_LEN 0 | |
6606 | ||
6607 | ||
6608 | /***********************************/ | |
6609 | /* MC_CMD_RMON_ALLOC_SUPER_CLASS | |
6610 | * Allocate an rmon super_class | |
6611 | */ | |
6612 | #define MC_CMD_RMON_ALLOC_SUPER_CLASS 0xcc | |
6613 | ||
6614 | /* MC_CMD_RMON_ALLOC_SUPER_CLASS_IN msgrequest */ | |
6615 | #define MC_CMD_RMON_ALLOC_SUPER_CLASS_IN_LEN 0 | |
6616 | ||
6617 | /* MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT msgresponse */ | |
6618 | #define MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT_LEN 4 | |
6619 | /* super_class */ | |
6620 | #define MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT_SUPER_CLASS_OFST 0 | |
6621 | ||
6622 | ||
6623 | /***********************************/ | |
6624 | /* MC_CMD_RMON_DEALLOC_SUPER_CLASS | |
6625 | * Deallocate an rmon tx super_class | |
6626 | */ | |
6627 | #define MC_CMD_RMON_DEALLOC_SUPER_CLASS 0xcd | |
6628 | ||
6629 | /* MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN msgrequest */ | |
6630 | #define MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN_LEN 4 | |
6631 | /* super_class */ | |
6632 | #define MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN_SUPER_CLASS_OFST 0 | |
6633 | ||
6634 | /* MC_CMD_RMON_DEALLOC_SUPER_CLASS_OUT msgresponse */ | |
6635 | #define MC_CMD_RMON_DEALLOC_SUPER_CLASS_OUT_LEN 0 | |
6636 | ||
6637 | ||
6638 | /***********************************/ | |
6639 | /* MC_CMD_RMON_RX_UP_CONV_STATS | |
6640 | * Retrieve up converter statistics | |
6641 | */ | |
6642 | #define MC_CMD_RMON_RX_UP_CONV_STATS 0xce | |
6643 | ||
6644 | /* MC_CMD_RMON_RX_UP_CONV_STATS_IN msgrequest */ | |
6645 | #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_LEN 4 | |
6646 | /* flags */ | |
6647 | #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_FLAGS_OFST 0 | |
6648 | #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_PORT_LBN 0 | |
6649 | #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_PORT_WIDTH 2 | |
6650 | #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_RST_LBN 2 | |
6651 | #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_RST_WIDTH 1 | |
6652 | ||
6653 | /* MC_CMD_RMON_RX_UP_CONV_STATS_OUT msgresponse */ | |
6654 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LENMIN 4 | |
6655 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LENMAX 252 | |
6656 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LEN(num) (0+4*(num)) | |
6657 | /* Array of stats */ | |
6658 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_OFST 0 | |
6659 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_LEN 4 | |
6660 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_MINNUM 1 | |
6661 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_MAXNUM 63 | |
6662 | ||
6663 | ||
6664 | /***********************************/ | |
6665 | /* MC_CMD_RMON_RX_IPI_STATS | |
6666 | * Retrieve rx ipi stats | |
6667 | */ | |
6668 | #define MC_CMD_RMON_RX_IPI_STATS 0xcf | |
6669 | ||
6670 | /* MC_CMD_RMON_RX_IPI_STATS_IN msgrequest */ | |
6671 | #define MC_CMD_RMON_RX_IPI_STATS_IN_LEN 4 | |
6672 | /* flags */ | |
6673 | #define MC_CMD_RMON_RX_IPI_STATS_IN_FLAGS_OFST 0 | |
6674 | #define MC_CMD_RMON_RX_IPI_STATS_IN_VFIFO_LBN 0 | |
6675 | #define MC_CMD_RMON_RX_IPI_STATS_IN_VFIFO_WIDTH 5 | |
6676 | #define MC_CMD_RMON_RX_IPI_STATS_IN_RST_LBN 5 | |
6677 | #define MC_CMD_RMON_RX_IPI_STATS_IN_RST_WIDTH 1 | |
6678 | ||
6679 | /* MC_CMD_RMON_RX_IPI_STATS_OUT msgresponse */ | |
6680 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_LENMIN 4 | |
6681 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_LENMAX 252 | |
6682 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_LEN(num) (0+4*(num)) | |
6683 | /* Array of stats */ | |
6684 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_OFST 0 | |
6685 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_LEN 4 | |
6686 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_MINNUM 1 | |
6687 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_MAXNUM 63 | |
6688 | ||
6689 | ||
6690 | /***********************************/ | |
6691 | /* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS | |
6692 | * Retrieve rx ipsec cntxt_ptr indexed stats | |
6693 | */ | |
6694 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS 0xd0 | |
6695 | ||
6696 | /* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN msgrequest */ | |
6697 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_LEN 4 | |
6698 | /* flags */ | |
6699 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_FLAGS_OFST 0 | |
6700 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_LBN 0 | |
6701 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_WIDTH 9 | |
6702 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_RST_LBN 9 | |
6703 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_RST_WIDTH 1 | |
6704 | ||
6705 | /* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT msgresponse */ | |
6706 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LENMIN 4 | |
6707 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LENMAX 252 | |
6708 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LEN(num) (0+4*(num)) | |
6709 | /* Array of stats */ | |
6710 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_OFST 0 | |
6711 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_LEN 4 | |
6712 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MINNUM 1 | |
6713 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MAXNUM 63 | |
6714 | ||
6715 | ||
6716 | /***********************************/ | |
6717 | /* MC_CMD_RMON_RX_IPSEC_PORT_STATS | |
6718 | * Retrieve rx ipsec port indexed stats | |
6719 | */ | |
6720 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS 0xd1 | |
6721 | ||
6722 | /* MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN msgrequest */ | |
6723 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_LEN 4 | |
6724 | /* flags */ | |
6725 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_FLAGS_OFST 0 | |
6726 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_PORT_LBN 0 | |
6727 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_PORT_WIDTH 2 | |
6728 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_RST_LBN 2 | |
6729 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_RST_WIDTH 1 | |
6730 | ||
6731 | /* MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT msgresponse */ | |
6732 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LENMIN 4 | |
6733 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LENMAX 252 | |
6734 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LEN(num) (0+4*(num)) | |
6735 | /* Array of stats */ | |
6736 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_OFST 0 | |
6737 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_LEN 4 | |
6738 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_MINNUM 1 | |
6739 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_MAXNUM 63 | |
6740 | ||
6741 | ||
6742 | /***********************************/ | |
6743 | /* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS | |
6744 | * Retrieve tx ipsec overflow | |
6745 | */ | |
6746 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS 0xd2 | |
6747 | ||
6748 | /* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN msgrequest */ | |
6749 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_LEN 4 | |
6750 | /* flags */ | |
6751 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_FLAGS_OFST 0 | |
6752 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_PORT_LBN 0 | |
6753 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_PORT_WIDTH 2 | |
6754 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_RST_LBN 2 | |
6755 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_RST_WIDTH 1 | |
6756 | ||
6757 | /* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT msgresponse */ | |
6758 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LENMIN 4 | |
6759 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LENMAX 252 | |
6760 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LEN(num) (0+4*(num)) | |
6761 | /* Array of stats */ | |
6762 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_OFST 0 | |
6763 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_LEN 4 | |
6764 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_MINNUM 1 | |
6765 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_MAXNUM 63 | |
6766 | ||
6767 | ||
6768 | /***********************************/ | |
6769 | /* MC_CMD_VPORT_ADD_MAC_ADDRESS | |
6770 | * Add a MAC address to a v-port | |
6771 | */ | |
6772 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 | |
6773 | ||
75122ec8 SS |
6774 | #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6775 | ||
f2b0befd BH |
6776 | /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ |
6777 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 | |
6778 | /* The handle of the v-port */ | |
6779 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 | |
6780 | /* MAC address to add */ | |
6781 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 | |
6782 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 | |
6783 | ||
6784 | /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ | |
6785 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 | |
6786 | ||
6787 | ||
6788 | /***********************************/ | |
6789 | /* MC_CMD_VPORT_DEL_MAC_ADDRESS | |
6790 | * Delete a MAC address from a v-port | |
6791 | */ | |
6792 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 | |
6793 | ||
75122ec8 SS |
6794 | #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6795 | ||
f2b0befd BH |
6796 | /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ |
6797 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 | |
6798 | /* The handle of the v-port */ | |
6799 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 | |
6800 | /* MAC address to add */ | |
6801 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 | |
6802 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 | |
6803 | ||
6804 | /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ | |
6805 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 | |
6806 | ||
6807 | ||
6808 | /***********************************/ | |
6809 | /* MC_CMD_VPORT_GET_MAC_ADDRESSES | |
6810 | * Delete a MAC address from a v-port | |
6811 | */ | |
6812 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa | |
6813 | ||
75122ec8 SS |
6814 | #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6815 | ||
f2b0befd BH |
6816 | /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ |
6817 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 | |
6818 | /* The handle of the v-port */ | |
6819 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 | |
6820 | ||
6821 | /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ | |
6822 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 | |
6823 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 | |
6824 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) | |
6825 | /* The number of MAC addresses returned */ | |
6826 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 | |
6827 | /* Array of MAC addresses */ | |
6828 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 | |
6829 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 | |
6830 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 | |
6831 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 | |
6832 | ||
6833 | ||
6834 | /***********************************/ | |
6835 | /* MC_CMD_DUMP_BUFTBL_ENTRIES | |
6836 | * Dump buffer table entries, mainly for command client debug use. Dumps | |
6837 | * absolute entries, and does not use chunk handles. All entries must be in | |
6838 | * range, and used for q page mapping, Although the latter restriction may be | |
6839 | * lifted in future. | |
6840 | */ | |
6841 | #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab | |
6842 | ||
75122ec8 SS |
6843 | #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
6844 | ||
f2b0befd BH |
6845 | /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ |
6846 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 | |
6847 | /* Index of the first buffer table entry. */ | |
6848 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 | |
6849 | /* Number of buffer table entries to dump. */ | |
6850 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 | |
6851 | ||
6852 | /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ | |
6853 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 | |
6854 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 | |
6855 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) | |
dbedd44e | 6856 | /* Raw buffer table entries, laid out as BUFTBL_ENTRY. */ |
f2b0befd BH |
6857 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 |
6858 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 | |
6859 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 | |
6860 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 | |
6861 | ||
6862 | ||
6863 | /***********************************/ | |
6864 | /* MC_CMD_SET_RXDP_CONFIG | |
6865 | * Set global RXDP configuration settings | |
6866 | */ | |
6867 | #define MC_CMD_SET_RXDP_CONFIG 0xc1 | |
6868 | ||
75122ec8 SS |
6869 | #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
6870 | ||
f2b0befd BH |
6871 | /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ |
6872 | #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 | |
6873 | #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 | |
6874 | #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 | |
6875 | #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 | |
6876 | ||
6877 | /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ | |
6878 | #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 | |
6879 | ||
6880 | ||
6881 | /***********************************/ | |
6882 | /* MC_CMD_GET_RXDP_CONFIG | |
6883 | * Get global RXDP configuration settings | |
6884 | */ | |
6885 | #define MC_CMD_GET_RXDP_CONFIG 0xc2 | |
6886 | ||
75122ec8 SS |
6887 | #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
6888 | ||
f2b0befd BH |
6889 | /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ |
6890 | #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 | |
6891 | ||
6892 | /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ | |
6893 | #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 | |
6894 | #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 | |
6895 | #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 | |
6896 | #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 | |
6897 | ||
6898 | ||
6899 | /***********************************/ | |
6900 | /* MC_CMD_RMON_RX_CLASS_DROPS_STATS | |
6901 | * Retrieve rx class drop stats | |
6902 | */ | |
6903 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS 0xd3 | |
6904 | ||
6905 | /* MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN msgrequest */ | |
6906 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_LEN 4 | |
6907 | /* flags */ | |
6908 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_FLAGS_OFST 0 | |
6909 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_CLASS_LBN 0 | |
6910 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_CLASS_WIDTH 8 | |
6911 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_RST_LBN 8 | |
6912 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_RST_WIDTH 1 | |
6913 | ||
6914 | /* MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT msgresponse */ | |
6915 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LENMIN 4 | |
6916 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LENMAX 252 | |
6917 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LEN(num) (0+4*(num)) | |
6918 | /* Array of stats */ | |
6919 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_OFST 0 | |
6920 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_LEN 4 | |
6921 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_MINNUM 1 | |
6922 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_MAXNUM 63 | |
6923 | ||
6924 | ||
6925 | /***********************************/ | |
6926 | /* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS | |
6927 | * Retrieve rx super class drop stats | |
6928 | */ | |
6929 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS 0xd4 | |
6930 | ||
6931 | /* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN msgrequest */ | |
6932 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_LEN 4 | |
6933 | /* flags */ | |
6934 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_FLAGS_OFST 0 | |
6935 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_SUPER_CLASS_LBN 0 | |
6936 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_SUPER_CLASS_WIDTH 4 | |
6937 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_RST_LBN 4 | |
6938 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_RST_WIDTH 1 | |
6939 | ||
6940 | /* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT msgresponse */ | |
6941 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LENMIN 4 | |
6942 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LENMAX 252 | |
6943 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LEN(num) (0+4*(num)) | |
6944 | /* Array of stats */ | |
6945 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_OFST 0 | |
6946 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_LEN 4 | |
6947 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_MINNUM 1 | |
6948 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_MAXNUM 63 | |
6949 | ||
6950 | ||
6951 | /***********************************/ | |
6952 | /* MC_CMD_RMON_RX_ERRORS_STATS | |
6953 | * Retrieve rxdp errors | |
6954 | */ | |
6955 | #define MC_CMD_RMON_RX_ERRORS_STATS 0xd5 | |
6956 | ||
6957 | /* MC_CMD_RMON_RX_ERRORS_STATS_IN msgrequest */ | |
6958 | #define MC_CMD_RMON_RX_ERRORS_STATS_IN_LEN 4 | |
6959 | /* flags */ | |
6960 | #define MC_CMD_RMON_RX_ERRORS_STATS_IN_FLAGS_OFST 0 | |
6961 | #define MC_CMD_RMON_RX_ERRORS_STATS_IN_QID_LBN 0 | |
6962 | #define MC_CMD_RMON_RX_ERRORS_STATS_IN_QID_WIDTH 11 | |
6963 | #define MC_CMD_RMON_RX_ERRORS_STATS_IN_RST_LBN 11 | |
6964 | #define MC_CMD_RMON_RX_ERRORS_STATS_IN_RST_WIDTH 1 | |
6965 | ||
6966 | /* MC_CMD_RMON_RX_ERRORS_STATS_OUT msgresponse */ | |
6967 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LENMIN 4 | |
6968 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LENMAX 252 | |
6969 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LEN(num) (0+4*(num)) | |
6970 | /* Array of stats */ | |
6971 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_OFST 0 | |
6972 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_LEN 4 | |
6973 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_MINNUM 1 | |
6974 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_MAXNUM 63 | |
6975 | ||
6976 | ||
6977 | /***********************************/ | |
6978 | /* MC_CMD_RMON_RX_OVERFLOW_STATS | |
6979 | * Retrieve rxdp overflow | |
6980 | */ | |
6981 | #define MC_CMD_RMON_RX_OVERFLOW_STATS 0xd6 | |
6982 | ||
6983 | /* MC_CMD_RMON_RX_OVERFLOW_STATS_IN msgrequest */ | |
6984 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_LEN 4 | |
6985 | /* flags */ | |
6986 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_FLAGS_OFST 0 | |
6987 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_CLASS_LBN 0 | |
6988 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_CLASS_WIDTH 8 | |
6989 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_RST_LBN 8 | |
6990 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_RST_WIDTH 1 | |
6991 | ||
6992 | /* MC_CMD_RMON_RX_OVERFLOW_STATS_OUT msgresponse */ | |
6993 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LENMIN 4 | |
6994 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LENMAX 252 | |
6995 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LEN(num) (0+4*(num)) | |
6996 | /* Array of stats */ | |
6997 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_OFST 0 | |
6998 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_LEN 4 | |
6999 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_MINNUM 1 | |
7000 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_MAXNUM 63 | |
7001 | ||
7002 | ||
7003 | /***********************************/ | |
7004 | /* MC_CMD_RMON_TX_IPI_STATS | |
7005 | * Retrieve tx ipi stats | |
7006 | */ | |
7007 | #define MC_CMD_RMON_TX_IPI_STATS 0xd7 | |
7008 | ||
7009 | /* MC_CMD_RMON_TX_IPI_STATS_IN msgrequest */ | |
7010 | #define MC_CMD_RMON_TX_IPI_STATS_IN_LEN 4 | |
7011 | /* flags */ | |
7012 | #define MC_CMD_RMON_TX_IPI_STATS_IN_FLAGS_OFST 0 | |
7013 | #define MC_CMD_RMON_TX_IPI_STATS_IN_VFIFO_LBN 0 | |
7014 | #define MC_CMD_RMON_TX_IPI_STATS_IN_VFIFO_WIDTH 5 | |
7015 | #define MC_CMD_RMON_TX_IPI_STATS_IN_RST_LBN 5 | |
7016 | #define MC_CMD_RMON_TX_IPI_STATS_IN_RST_WIDTH 1 | |
7017 | ||
7018 | /* MC_CMD_RMON_TX_IPI_STATS_OUT msgresponse */ | |
7019 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_LENMIN 4 | |
7020 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_LENMAX 252 | |
7021 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_LEN(num) (0+4*(num)) | |
7022 | /* Array of stats */ | |
7023 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_OFST 0 | |
7024 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_LEN 4 | |
7025 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_MINNUM 1 | |
7026 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_MAXNUM 63 | |
7027 | ||
7028 | ||
7029 | /***********************************/ | |
7030 | /* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS | |
7031 | * Retrieve tx ipsec counters by cntxt_ptr | |
7032 | */ | |
7033 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS 0xd8 | |
7034 | ||
7035 | /* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN msgrequest */ | |
7036 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_LEN 4 | |
7037 | /* flags */ | |
7038 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_FLAGS_OFST 0 | |
7039 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_LBN 0 | |
7040 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_WIDTH 9 | |
7041 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_RST_LBN 9 | |
7042 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_RST_WIDTH 1 | |
7043 | ||
7044 | /* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT msgresponse */ | |
7045 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LENMIN 4 | |
7046 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LENMAX 252 | |
7047 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LEN(num) (0+4*(num)) | |
7048 | /* Array of stats */ | |
7049 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_OFST 0 | |
7050 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_LEN 4 | |
7051 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MINNUM 1 | |
7052 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MAXNUM 63 | |
7053 | ||
7054 | ||
7055 | /***********************************/ | |
7056 | /* MC_CMD_RMON_TX_IPSEC_PORT_STATS | |
7057 | * Retrieve tx ipsec counters by port | |
7058 | */ | |
7059 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS 0xd9 | |
7060 | ||
7061 | /* MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN msgrequest */ | |
7062 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_LEN 4 | |
7063 | /* flags */ | |
7064 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_FLAGS_OFST 0 | |
7065 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_PORT_LBN 0 | |
7066 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_PORT_WIDTH 2 | |
7067 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_RST_LBN 2 | |
7068 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_RST_WIDTH 1 | |
7069 | ||
7070 | /* MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT msgresponse */ | |
7071 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LENMIN 4 | |
7072 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LENMAX 252 | |
7073 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LEN(num) (0+4*(num)) | |
7074 | /* Array of stats */ | |
7075 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_OFST 0 | |
7076 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_LEN 4 | |
7077 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_MINNUM 1 | |
7078 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_MAXNUM 63 | |
7079 | ||
7080 | ||
7081 | /***********************************/ | |
7082 | /* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS | |
7083 | * Retrieve tx ipsec overflow | |
7084 | */ | |
7085 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS 0xda | |
7086 | ||
7087 | /* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN msgrequest */ | |
7088 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_LEN 4 | |
7089 | /* flags */ | |
7090 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_FLAGS_OFST 0 | |
7091 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_PORT_LBN 0 | |
7092 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_PORT_WIDTH 2 | |
7093 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_RST_LBN 2 | |
7094 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_RST_WIDTH 1 | |
7095 | ||
7096 | /* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT msgresponse */ | |
7097 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LENMIN 4 | |
7098 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LENMAX 252 | |
7099 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LEN(num) (0+4*(num)) | |
7100 | /* Array of stats */ | |
7101 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_OFST 0 | |
7102 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_LEN 4 | |
7103 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_MINNUM 1 | |
7104 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_MAXNUM 63 | |
7105 | ||
7106 | ||
7107 | /***********************************/ | |
7108 | /* MC_CMD_RMON_TX_NOWHERE_STATS | |
7109 | * Retrieve tx nowhere stats | |
7110 | */ | |
7111 | #define MC_CMD_RMON_TX_NOWHERE_STATS 0xdb | |
7112 | ||
7113 | /* MC_CMD_RMON_TX_NOWHERE_STATS_IN msgrequest */ | |
7114 | #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_LEN 4 | |
7115 | /* flags */ | |
7116 | #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_FLAGS_OFST 0 | |
7117 | #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_CLASS_LBN 0 | |
7118 | #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_CLASS_WIDTH 8 | |
7119 | #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_RST_LBN 8 | |
7120 | #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_RST_WIDTH 1 | |
7121 | ||
7122 | /* MC_CMD_RMON_TX_NOWHERE_STATS_OUT msgresponse */ | |
7123 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LENMIN 4 | |
7124 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LENMAX 252 | |
7125 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LEN(num) (0+4*(num)) | |
7126 | /* Array of stats */ | |
7127 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_OFST 0 | |
7128 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_LEN 4 | |
7129 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_MINNUM 1 | |
7130 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_MAXNUM 63 | |
7131 | ||
7132 | ||
7133 | /***********************************/ | |
7134 | /* MC_CMD_RMON_TX_NOWHERE_QBB_STATS | |
7135 | * Retrieve tx nowhere qbb stats | |
7136 | */ | |
7137 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS 0xdc | |
7138 | ||
7139 | /* MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN msgrequest */ | |
7140 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_LEN 4 | |
7141 | /* flags */ | |
7142 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_FLAGS_OFST 0 | |
7143 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_PRIORITY_LBN 0 | |
7144 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_PRIORITY_WIDTH 3 | |
7145 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_RST_LBN 3 | |
7146 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_RST_WIDTH 1 | |
7147 | ||
7148 | /* MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT msgresponse */ | |
7149 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LENMIN 4 | |
7150 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LENMAX 252 | |
7151 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LEN(num) (0+4*(num)) | |
7152 | /* Array of stats */ | |
7153 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_OFST 0 | |
7154 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_LEN 4 | |
7155 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_MINNUM 1 | |
7156 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_MAXNUM 63 | |
7157 | ||
7158 | ||
7159 | /***********************************/ | |
7160 | /* MC_CMD_RMON_TX_ERRORS_STATS | |
7161 | * Retrieve rxdp errors | |
7162 | */ | |
7163 | #define MC_CMD_RMON_TX_ERRORS_STATS 0xdd | |
7164 | ||
7165 | /* MC_CMD_RMON_TX_ERRORS_STATS_IN msgrequest */ | |
7166 | #define MC_CMD_RMON_TX_ERRORS_STATS_IN_LEN 4 | |
7167 | /* flags */ | |
7168 | #define MC_CMD_RMON_TX_ERRORS_STATS_IN_FLAGS_OFST 0 | |
7169 | #define MC_CMD_RMON_TX_ERRORS_STATS_IN_QID_LBN 0 | |
7170 | #define MC_CMD_RMON_TX_ERRORS_STATS_IN_QID_WIDTH 11 | |
7171 | #define MC_CMD_RMON_TX_ERRORS_STATS_IN_RST_LBN 11 | |
7172 | #define MC_CMD_RMON_TX_ERRORS_STATS_IN_RST_WIDTH 1 | |
7173 | ||
7174 | /* MC_CMD_RMON_TX_ERRORS_STATS_OUT msgresponse */ | |
7175 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LENMIN 4 | |
7176 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LENMAX 252 | |
7177 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LEN(num) (0+4*(num)) | |
7178 | /* Array of stats */ | |
7179 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_OFST 0 | |
7180 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_LEN 4 | |
7181 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_MINNUM 1 | |
7182 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_MAXNUM 63 | |
7183 | ||
7184 | ||
7185 | /***********************************/ | |
7186 | /* MC_CMD_RMON_TX_OVERFLOW_STATS | |
7187 | * Retrieve rxdp overflow | |
7188 | */ | |
7189 | #define MC_CMD_RMON_TX_OVERFLOW_STATS 0xde | |
7190 | ||
7191 | /* MC_CMD_RMON_TX_OVERFLOW_STATS_IN msgrequest */ | |
7192 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_LEN 4 | |
7193 | /* flags */ | |
7194 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_FLAGS_OFST 0 | |
7195 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_CLASS_LBN 0 | |
7196 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_CLASS_WIDTH 8 | |
7197 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_RST_LBN 8 | |
7198 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_RST_WIDTH 1 | |
7199 | ||
7200 | /* MC_CMD_RMON_TX_OVERFLOW_STATS_OUT msgresponse */ | |
7201 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LENMIN 4 | |
7202 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LENMAX 252 | |
7203 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LEN(num) (0+4*(num)) | |
7204 | /* Array of stats */ | |
7205 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_OFST 0 | |
7206 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_LEN 4 | |
7207 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_MINNUM 1 | |
7208 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_MAXNUM 63 | |
7209 | ||
7210 | ||
7211 | /***********************************/ | |
7212 | /* MC_CMD_RMON_COLLECT_CLASS_STATS | |
7213 | * Explicitly collect class stats at the specified evb port | |
7214 | */ | |
7215 | #define MC_CMD_RMON_COLLECT_CLASS_STATS 0xdf | |
7216 | ||
7217 | /* MC_CMD_RMON_COLLECT_CLASS_STATS_IN msgrequest */ | |
7218 | #define MC_CMD_RMON_COLLECT_CLASS_STATS_IN_LEN 4 | |
7219 | /* The port id associated with the vport/pport at which to collect class stats | |
7220 | */ | |
7221 | #define MC_CMD_RMON_COLLECT_CLASS_STATS_IN_PORT_ID_OFST 0 | |
7222 | ||
7223 | /* MC_CMD_RMON_COLLECT_CLASS_STATS_OUT msgresponse */ | |
7224 | #define MC_CMD_RMON_COLLECT_CLASS_STATS_OUT_LEN 4 | |
7225 | /* class */ | |
7226 | #define MC_CMD_RMON_COLLECT_CLASS_STATS_OUT_CLASS_OFST 0 | |
7227 | ||
7228 | ||
7229 | /***********************************/ | |
7230 | /* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS | |
7231 | * Explicitly collect class stats at the specified evb port | |
7232 | */ | |
7233 | #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS 0xe0 | |
7234 | ||
7235 | /* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN msgrequest */ | |
7236 | #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN_LEN 4 | |
7237 | /* The port id associated with the vport/pport at which to collect class stats | |
7238 | */ | |
7239 | #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN_PORT_ID_OFST 0 | |
7240 | ||
7241 | /* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT msgresponse */ | |
7242 | #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT_LEN 4 | |
7243 | /* super_class */ | |
7244 | #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT_SUPER_CLASS_OFST 0 | |
7245 | ||
7246 | ||
7247 | /***********************************/ | |
7248 | /* MC_CMD_GET_CLOCK | |
7249 | * Return the system and PDCPU clock frequencies. | |
7250 | */ | |
7251 | #define MC_CMD_GET_CLOCK 0xac | |
7252 | ||
75122ec8 SS |
7253 | #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
7254 | ||
f2b0befd BH |
7255 | /* MC_CMD_GET_CLOCK_IN msgrequest */ |
7256 | #define MC_CMD_GET_CLOCK_IN_LEN 0 | |
7257 | ||
7258 | /* MC_CMD_GET_CLOCK_OUT msgresponse */ | |
7259 | #define MC_CMD_GET_CLOCK_OUT_LEN 8 | |
7260 | /* System frequency, MHz */ | |
7261 | #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 | |
7262 | /* DPCPU frequency, MHz */ | |
7263 | #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 | |
7264 | ||
7265 | ||
7266 | /***********************************/ | |
7267 | /* MC_CMD_SET_CLOCK | |
7268 | * Control the system and DPCPU clock frequencies. Changes are lost reboot. | |
7269 | */ | |
7270 | #define MC_CMD_SET_CLOCK 0xad | |
7271 | ||
75122ec8 SS |
7272 | #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7273 | ||
f2b0befd BH |
7274 | /* MC_CMD_SET_CLOCK_IN msgrequest */ |
7275 | #define MC_CMD_SET_CLOCK_IN_LEN 12 | |
7276 | /* Requested system frequency in MHz; 0 leaves unchanged. */ | |
7277 | #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 | |
7278 | /* Requested inter-core frequency in MHz; 0 leaves unchanged. */ | |
7279 | #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 | |
7280 | /* Request DPCPU frequency in MHz; 0 leaves unchanged. */ | |
7281 | #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 | |
7282 | ||
7283 | /* MC_CMD_SET_CLOCK_OUT msgresponse */ | |
7284 | #define MC_CMD_SET_CLOCK_OUT_LEN 12 | |
7285 | /* Resulting system frequency in MHz */ | |
7286 | #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 | |
7287 | /* Resulting inter-core frequency in MHz */ | |
7288 | #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 | |
7289 | /* Resulting DPCPU frequency in MHz */ | |
7290 | #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 | |
7291 | ||
7292 | ||
7293 | /***********************************/ | |
7294 | /* MC_CMD_DPCPU_RPC | |
7295 | * Send an arbitrary DPCPU message. | |
7296 | */ | |
7297 | #define MC_CMD_DPCPU_RPC 0xae | |
7298 | ||
75122ec8 SS |
7299 | #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7300 | ||
f2b0befd BH |
7301 | /* MC_CMD_DPCPU_RPC_IN msgrequest */ |
7302 | #define MC_CMD_DPCPU_RPC_IN_LEN 36 | |
7303 | #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 | |
7304 | /* enum: RxDPCPU */ | |
7305 | #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x0 | |
7306 | /* enum: TxDPCPU0 */ | |
7307 | #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 | |
7308 | /* enum: TxDPCPU1 */ | |
7309 | #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 | |
7310 | /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be | |
7311 | * initialised to zero | |
7312 | */ | |
7313 | #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 | |
7314 | #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 | |
7315 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 | |
7316 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 | |
7317 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ | |
7318 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ | |
7319 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ | |
7320 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ | |
7321 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ | |
7322 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ | |
7323 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ | |
7324 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ | |
7325 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ | |
7326 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 | |
7327 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 | |
7328 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 | |
7329 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 | |
7330 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 | |
7331 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 | |
7332 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 | |
7333 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 | |
7334 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 | |
7335 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 | |
7336 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ | |
7337 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ | |
7338 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ | |
7339 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ | |
7340 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ | |
7341 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 | |
7342 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 | |
7343 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 | |
7344 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 | |
7345 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 | |
7346 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 | |
7347 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 | |
7348 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 | |
7349 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ | |
7350 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ | |
7351 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ | |
7352 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 | |
7353 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 | |
7354 | #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 | |
7355 | #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 | |
7356 | /* Register data to write. Only valid in write/write-read. */ | |
7357 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 | |
7358 | /* Register address. */ | |
7359 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 | |
7360 | ||
7361 | /* MC_CMD_DPCPU_RPC_OUT msgresponse */ | |
7362 | #define MC_CMD_DPCPU_RPC_OUT_LEN 36 | |
7363 | #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 | |
7364 | /* DATA */ | |
7365 | #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 | |
7366 | #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 | |
7367 | #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 | |
7368 | #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 | |
7369 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 | |
7370 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 | |
7371 | #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 | |
7372 | #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 | |
7373 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 | |
7374 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 | |
7375 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 | |
7376 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 | |
7377 | ||
7378 | ||
7379 | /***********************************/ | |
7380 | /* MC_CMD_TRIGGER_INTERRUPT | |
7381 | * Trigger an interrupt by prodding the BIU. | |
7382 | */ | |
7383 | #define MC_CMD_TRIGGER_INTERRUPT 0xe3 | |
7384 | ||
75122ec8 SS |
7385 | #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
7386 | ||
f2b0befd BH |
7387 | /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ |
7388 | #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 | |
7389 | /* Interrupt level relative to base for function. */ | |
7390 | #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 | |
7391 | ||
7392 | /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ | |
7393 | #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 | |
7394 | ||
7395 | ||
512bb06c BH |
7396 | /***********************************/ |
7397 | /* MC_CMD_CAP_BLK_READ | |
7398 | * Read multiple 64bit words from capture block memory | |
7399 | */ | |
7400 | #define MC_CMD_CAP_BLK_READ 0xe7 | |
7401 | ||
75122ec8 SS |
7402 | #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7403 | ||
512bb06c BH |
7404 | /* MC_CMD_CAP_BLK_READ_IN msgrequest */ |
7405 | #define MC_CMD_CAP_BLK_READ_IN_LEN 12 | |
7406 | #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 | |
7407 | #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 | |
7408 | #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 | |
7409 | ||
7410 | /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ | |
7411 | #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 | |
7412 | #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 | |
7413 | #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) | |
7414 | #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 | |
7415 | #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 | |
7416 | #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 | |
7417 | #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 | |
7418 | #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 | |
7419 | #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 | |
7420 | ||
7421 | ||
f2b0befd BH |
7422 | /***********************************/ |
7423 | /* MC_CMD_DUMP_DO | |
7424 | * Take a dump of the DUT state | |
7425 | */ | |
7426 | #define MC_CMD_DUMP_DO 0xe8 | |
7427 | ||
75122ec8 SS |
7428 | #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7429 | ||
f2b0befd BH |
7430 | /* MC_CMD_DUMP_DO_IN msgrequest */ |
7431 | #define MC_CMD_DUMP_DO_IN_LEN 52 | |
7432 | #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 | |
7433 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 | |
7434 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ | |
7435 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ | |
7436 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 | |
7437 | #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ | |
7438 | #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ | |
7439 | #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ | |
7440 | #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ | |
7441 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 | |
7442 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 | |
7443 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 | |
7444 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 | |
7445 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 | |
7446 | #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ | |
7447 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 | |
7448 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 | |
7449 | #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ | |
7450 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 | |
512bb06c BH |
7451 | /* enum: The uart port this command was received over (if using a uart |
7452 | * transport) | |
7453 | */ | |
7454 | #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff | |
f2b0befd BH |
7455 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 |
7456 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 | |
7457 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ | |
7458 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ | |
7459 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 | |
7460 | /* Enum values, see field(s): */ | |
7461 | /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ | |
7462 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 | |
7463 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 | |
7464 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 | |
7465 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 | |
7466 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 | |
7467 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 | |
7468 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 | |
7469 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 | |
7470 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 | |
7471 | ||
7472 | /* MC_CMD_DUMP_DO_OUT msgresponse */ | |
7473 | #define MC_CMD_DUMP_DO_OUT_LEN 4 | |
7474 | #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 | |
7475 | ||
7476 | ||
7477 | /***********************************/ | |
7478 | /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED | |
7479 | * Configure unsolicited dumps | |
7480 | */ | |
7481 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 | |
7482 | ||
75122ec8 SS |
7483 | #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7484 | ||
f2b0befd BH |
7485 | /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ |
7486 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 | |
7487 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 | |
7488 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 | |
7489 | /* Enum values, see field(s): */ | |
7490 | /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ | |
7491 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 | |
7492 | /* Enum values, see field(s): */ | |
7493 | /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ | |
7494 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 | |
7495 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 | |
7496 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 | |
7497 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 | |
7498 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 | |
7499 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 | |
7500 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 | |
7501 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 | |
7502 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 | |
7503 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 | |
7504 | /* Enum values, see field(s): */ | |
7505 | /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ | |
7506 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 | |
7507 | /* Enum values, see field(s): */ | |
7508 | /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ | |
7509 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 | |
7510 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 | |
7511 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 | |
7512 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 | |
7513 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 | |
7514 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 | |
7515 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 | |
7516 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 | |
7517 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 | |
7518 | ||
7519 | ||
7520 | /***********************************/ | |
7521 | /* MC_CMD_SET_PSU | |
7522 | * Adjusts power supply parameters. This is a warranty-voiding operation. | |
7523 | * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if | |
7524 | * the parameter is out of range. | |
7525 | */ | |
7526 | #define MC_CMD_SET_PSU 0xea | |
7527 | ||
75122ec8 SS |
7528 | #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7529 | ||
f2b0befd BH |
7530 | /* MC_CMD_SET_PSU_IN msgrequest */ |
7531 | #define MC_CMD_SET_PSU_IN_LEN 12 | |
7532 | #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 | |
7533 | #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ | |
7534 | #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 | |
7535 | #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ | |
7536 | #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ | |
7537 | /* desired value, eg voltage in mV */ | |
7538 | #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 | |
7539 | ||
7540 | /* MC_CMD_SET_PSU_OUT msgresponse */ | |
7541 | #define MC_CMD_SET_PSU_OUT_LEN 0 | |
7542 | ||
7543 | ||
7544 | /***********************************/ | |
7545 | /* MC_CMD_GET_FUNCTION_INFO | |
7546 | * Get function information. PF and VF number. | |
7547 | */ | |
7548 | #define MC_CMD_GET_FUNCTION_INFO 0xec | |
7549 | ||
75122ec8 SS |
7550 | #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
7551 | ||
f2b0befd BH |
7552 | /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ |
7553 | #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 | |
7554 | ||
7555 | /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ | |
7556 | #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 | |
7557 | #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 | |
7558 | #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 | |
7559 | ||
7560 | ||
7561 | /***********************************/ | |
7562 | /* MC_CMD_ENABLE_OFFLINE_BIST | |
7563 | * Enters offline BIST mode. All queues are torn down, chip enters quiescent | |
7564 | * mode, calling function gets exclusive MCDI ownership. The only way out is | |
7565 | * reboot. | |
7566 | */ | |
7567 | #define MC_CMD_ENABLE_OFFLINE_BIST 0xed | |
7568 | ||
75122ec8 SS |
7569 | #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7570 | ||
f2b0befd BH |
7571 | /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ |
7572 | #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 | |
7573 | ||
7574 | /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ | |
7575 | #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 | |
7576 | ||
7577 | ||
7578 | /***********************************/ | |
512bb06c BH |
7579 | /* MC_CMD_UART_SEND_DATA |
7580 | * Send checksummed[sic] block of data over the uart. Response is a placeholder | |
7581 | * should we wish to make this reliable; currently requests are fire-and- | |
7582 | * forget. | |
7583 | */ | |
7584 | #define MC_CMD_UART_SEND_DATA 0xee | |
7585 | ||
75122ec8 SS |
7586 | #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
7587 | ||
512bb06c BH |
7588 | /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ |
7589 | #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 | |
7590 | #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 | |
7591 | #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) | |
7592 | /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ | |
7593 | #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 | |
7594 | /* Offset at which to write the data */ | |
7595 | #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 | |
7596 | /* Length of data */ | |
7597 | #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 | |
7598 | /* Reserved for future use */ | |
7599 | #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 | |
7600 | #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 | |
7601 | #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 | |
7602 | #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 | |
7603 | #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 | |
7604 | ||
7605 | /* MC_CMD_UART_SEND_DATA_IN msgresponse */ | |
7606 | #define MC_CMD_UART_SEND_DATA_IN_LEN 0 | |
7607 | ||
7608 | ||
7609 | /***********************************/ | |
7610 | /* MC_CMD_UART_RECV_DATA | |
7611 | * Request checksummed[sic] block of data over the uart. Only a placeholder, | |
7612 | * subject to change and not currently implemented. | |
7613 | */ | |
7614 | #define MC_CMD_UART_RECV_DATA 0xef | |
7615 | ||
75122ec8 SS |
7616 | #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
7617 | ||
512bb06c BH |
7618 | /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ |
7619 | #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 | |
7620 | /* CRC32 over OFFSET, LENGTH, RESERVED */ | |
7621 | #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 | |
7622 | /* Offset from which to read the data */ | |
7623 | #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 | |
7624 | /* Length of data */ | |
7625 | #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 | |
7626 | /* Reserved for future use */ | |
7627 | #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 | |
7628 | ||
7629 | /* MC_CMD_UART_RECV_DATA_IN msgresponse */ | |
7630 | #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 | |
7631 | #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 | |
7632 | #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) | |
7633 | /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ | |
7634 | #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 | |
7635 | /* Offset at which to write the data */ | |
7636 | #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 | |
7637 | /* Length of data */ | |
7638 | #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 | |
7639 | /* Reserved for future use */ | |
7640 | #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 | |
7641 | #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 | |
7642 | #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 | |
7643 | #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 | |
7644 | #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 | |
f2b0befd BH |
7645 | |
7646 | ||
7647 | /***********************************/ | |
7648 | /* MC_CMD_READ_FUSES | |
7649 | * Read data programmed into the device One-Time-Programmable (OTP) Fuses | |
7650 | */ | |
7651 | #define MC_CMD_READ_FUSES 0xf0 | |
7652 | ||
75122ec8 SS |
7653 | #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7654 | ||
f2b0befd BH |
7655 | /* MC_CMD_READ_FUSES_IN msgrequest */ |
7656 | #define MC_CMD_READ_FUSES_IN_LEN 8 | |
7657 | /* Offset in OTP to read */ | |
7658 | #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 | |
7659 | /* Length of data to read in bytes */ | |
7660 | #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 | |
7661 | ||
7662 | /* MC_CMD_READ_FUSES_OUT msgresponse */ | |
7663 | #define MC_CMD_READ_FUSES_OUT_LENMIN 4 | |
7664 | #define MC_CMD_READ_FUSES_OUT_LENMAX 252 | |
7665 | #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) | |
7666 | /* Length of returned OTP data in bytes */ | |
7667 | #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 | |
7668 | /* Returned data */ | |
7669 | #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 | |
7670 | #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 | |
7671 | #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 | |
7672 | #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 | |
7673 | ||
7674 | ||
7675 | /***********************************/ | |
7676 | /* MC_CMD_KR_TUNE | |
7677 | * Get or set KR Serdes RXEQ and TX Driver settings | |
7678 | */ | |
7679 | #define MC_CMD_KR_TUNE 0xf1 | |
7680 | ||
75122ec8 SS |
7681 | #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7682 | ||
f2b0befd BH |
7683 | /* MC_CMD_KR_TUNE_IN msgrequest */ |
7684 | #define MC_CMD_KR_TUNE_IN_LENMIN 4 | |
7685 | #define MC_CMD_KR_TUNE_IN_LENMAX 252 | |
7686 | #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) | |
7687 | /* Requested operation */ | |
7688 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 | |
7689 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 | |
7690 | /* enum: Get current RXEQ settings */ | |
7691 | #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 | |
7692 | /* enum: Override RXEQ settings */ | |
7693 | #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 | |
7694 | /* enum: Get current TX Driver settings */ | |
7695 | #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 | |
7696 | /* enum: Override TX Driver settings */ | |
7697 | #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 | |
7698 | /* enum: Force KR Serdes reset / recalibration */ | |
7699 | #define MC_CMD_KR_TUNE_IN_RECAL 0x4 | |
512bb06c BH |
7700 | /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid |
7701 | * signal. | |
7702 | */ | |
7703 | #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 | |
7704 | /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The | |
7705 | * caller should call this command repeatedly after starting eye plot, until no | |
7706 | * more data is returned. | |
7707 | */ | |
7708 | #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 | |
f2b0befd BH |
7709 | /* Align the arguments to 32 bits */ |
7710 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 | |
7711 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 | |
7712 | /* Arguments specific to the operation */ | |
7713 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 | |
7714 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 | |
7715 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 | |
7716 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 | |
7717 | ||
7718 | /* MC_CMD_KR_TUNE_OUT msgresponse */ | |
7719 | #define MC_CMD_KR_TUNE_OUT_LEN 0 | |
7720 | ||
7721 | /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ | |
7722 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 | |
7723 | /* Requested operation */ | |
7724 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 | |
7725 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 | |
7726 | /* Align the arguments to 32 bits */ | |
7727 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 | |
7728 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 | |
7729 | ||
7730 | /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ | |
7731 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 | |
7732 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 | |
7733 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) | |
7734 | /* RXEQ Parameter */ | |
7735 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 | |
7736 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 | |
7737 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 | |
7738 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 | |
7739 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 | |
7740 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 | |
7741 | /* enum: Attenuation (0-15) */ | |
7742 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 | |
7743 | /* enum: CTLE Boost (0-15) */ | |
7744 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 | |
7745 | /* enum: Edge DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ | |
7746 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 | |
7747 | /* enum: Edge DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ | |
7748 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 | |
7749 | /* enum: Edge DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ | |
7750 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 | |
7751 | /* enum: Edge DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ | |
7752 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 | |
7753 | /* enum: Edge DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ | |
7754 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 | |
7755 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 | |
7756 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 | |
7757 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ | |
7758 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ | |
7759 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ | |
7760 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ | |
7761 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ | |
7762 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 | |
7763 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 | |
7764 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 | |
7765 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 | |
7766 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 | |
7767 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 | |
7768 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 | |
7769 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 | |
7770 | ||
7771 | /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ | |
7772 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 | |
7773 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 | |
7774 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) | |
7775 | /* Requested operation */ | |
7776 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 | |
7777 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 | |
7778 | /* Align the arguments to 32 bits */ | |
7779 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 | |
7780 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 | |
7781 | /* RXEQ Parameter */ | |
7782 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 | |
7783 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 | |
7784 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 | |
7785 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 | |
7786 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 | |
7787 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 | |
7788 | /* Enum values, see field(s): */ | |
7789 | /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ | |
7790 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 | |
7791 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 | |
7792 | /* Enum values, see field(s): */ | |
7793 | /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ | |
7794 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 | |
7795 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 | |
7796 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 | |
7797 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 | |
7798 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 | |
7799 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 | |
7800 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 | |
7801 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 | |
7802 | ||
7803 | /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ | |
7804 | #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 | |
7805 | ||
512bb06c BH |
7806 | /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ |
7807 | #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 | |
7808 | /* Requested operation */ | |
7809 | #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 | |
7810 | #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 | |
7811 | /* Align the arguments to 32 bits */ | |
7812 | #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 | |
7813 | #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 | |
7814 | ||
7815 | /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ | |
7816 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 | |
7817 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 | |
7818 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) | |
7819 | /* TXEQ Parameter */ | |
7820 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 | |
7821 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 | |
7822 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 | |
7823 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 | |
7824 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 | |
7825 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 | |
7826 | /* enum: TX Amplitude */ | |
7827 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 | |
7828 | /* enum: De-Emphasis Tap1 Magnitude (0-7) */ | |
7829 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 | |
7830 | /* enum: De-Emphasis Tap1 Fine */ | |
7831 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 | |
7832 | /* enum: De-Emphasis Tap2 Magnitude (0-6) */ | |
7833 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 | |
7834 | /* enum: De-Emphasis Tap2 Fine */ | |
7835 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 | |
7836 | /* enum: Pre-Emphasis Magnitude */ | |
7837 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 | |
7838 | /* enum: Pre-Emphasis Fine */ | |
7839 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 | |
7840 | /* enum: TX Slew Rate Coarse control */ | |
7841 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 | |
7842 | /* enum: TX Slew Rate Fine control */ | |
7843 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 | |
7844 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 | |
7845 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 | |
7846 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ | |
7847 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ | |
7848 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ | |
7849 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ | |
7850 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ | |
7851 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 | |
7852 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 | |
7853 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 | |
7854 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 | |
7855 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 | |
7856 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 | |
7857 | ||
7858 | /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ | |
7859 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 | |
7860 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 | |
7861 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) | |
7862 | /* Requested operation */ | |
7863 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 | |
7864 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 | |
7865 | /* Align the arguments to 32 bits */ | |
7866 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 | |
7867 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 | |
7868 | /* TXEQ Parameter */ | |
7869 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 | |
7870 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 | |
7871 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 | |
7872 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 | |
7873 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 | |
7874 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 | |
7875 | /* Enum values, see field(s): */ | |
7876 | /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ | |
7877 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 | |
7878 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 | |
7879 | /* Enum values, see field(s): */ | |
7880 | /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ | |
7881 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 | |
7882 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 | |
7883 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 | |
7884 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 | |
7885 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 | |
7886 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 | |
7887 | ||
7888 | /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ | |
7889 | #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 | |
7890 | ||
f2b0befd BH |
7891 | /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ |
7892 | #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 | |
7893 | /* Requested operation */ | |
7894 | #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 | |
7895 | #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 | |
7896 | /* Align the arguments to 32 bits */ | |
7897 | #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 | |
7898 | #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 | |
7899 | ||
7900 | /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ | |
7901 | #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 | |
7902 | ||
512bb06c BH |
7903 | /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ |
7904 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 | |
7905 | /* Requested operation */ | |
7906 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 | |
7907 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 | |
7908 | /* Align the arguments to 32 bits */ | |
7909 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 | |
7910 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 | |
7911 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 | |
7912 | ||
7913 | /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ | |
7914 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 | |
7915 | ||
7916 | /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ | |
7917 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 | |
7918 | /* Requested operation */ | |
7919 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 | |
7920 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 | |
7921 | /* Align the arguments to 32 bits */ | |
7922 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 | |
7923 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 | |
7924 | ||
7925 | /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ | |
7926 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 | |
7927 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 | |
7928 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) | |
7929 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 | |
7930 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 | |
7931 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 | |
7932 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 | |
7933 | ||
f2b0befd BH |
7934 | |
7935 | /***********************************/ | |
7936 | /* MC_CMD_PCIE_TUNE | |
7937 | * Get or set PCIE Serdes RXEQ and TX Driver settings | |
7938 | */ | |
7939 | #define MC_CMD_PCIE_TUNE 0xf2 | |
7940 | ||
75122ec8 SS |
7941 | #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7942 | ||
f2b0befd BH |
7943 | /* MC_CMD_PCIE_TUNE_IN msgrequest */ |
7944 | #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 | |
7945 | #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 | |
7946 | #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) | |
7947 | /* Requested operation */ | |
7948 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 | |
7949 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 | |
7950 | /* enum: Get current RXEQ settings */ | |
7951 | #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 | |
7952 | /* enum: Override RXEQ settings */ | |
7953 | #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 | |
7954 | /* enum: Get current TX Driver settings */ | |
7955 | #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 | |
7956 | /* enum: Override TX Driver settings */ | |
7957 | #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 | |
512bb06c BH |
7958 | /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ |
7959 | #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 | |
7960 | /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The | |
7961 | * caller should call this command repeatedly after starting eye plot, until no | |
7962 | * more data is returned. | |
7963 | */ | |
7964 | #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 | |
f2b0befd BH |
7965 | /* Align the arguments to 32 bits */ |
7966 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 | |
7967 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 | |
7968 | /* Arguments specific to the operation */ | |
7969 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 | |
7970 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 | |
7971 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 | |
7972 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 | |
7973 | ||
7974 | /* MC_CMD_PCIE_TUNE_OUT msgresponse */ | |
7975 | #define MC_CMD_PCIE_TUNE_OUT_LEN 0 | |
7976 | ||
7977 | /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ | |
7978 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 | |
7979 | /* Requested operation */ | |
7980 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 | |
7981 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 | |
7982 | /* Align the arguments to 32 bits */ | |
7983 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 | |
7984 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 | |
7985 | ||
7986 | /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ | |
7987 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 | |
7988 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 | |
7989 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) | |
7990 | /* RXEQ Parameter */ | |
7991 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 | |
7992 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 | |
7993 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 | |
7994 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 | |
7995 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 | |
7996 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 | |
7997 | /* enum: Attenuation (0-15) */ | |
7998 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 | |
7999 | /* enum: CTLE Boost (0-15) */ | |
8000 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 | |
8001 | /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ | |
8002 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 | |
8003 | /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ | |
8004 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 | |
8005 | /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ | |
8006 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 | |
8007 | /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ | |
8008 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 | |
8009 | /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ | |
8010 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 | |
8011 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 | |
8012 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 4 | |
8013 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ | |
8014 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ | |
8015 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ | |
8016 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ | |
8017 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ | |
8018 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ | |
8019 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ | |
8020 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ | |
8021 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x8 /* enum */ | |
8022 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 | |
8023 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 12 | |
8024 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 | |
8025 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 | |
8026 | ||
8027 | /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ | |
8028 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 | |
8029 | /* Requested operation */ | |
8030 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 | |
8031 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 | |
8032 | /* Align the arguments to 32 bits */ | |
8033 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 | |
8034 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 | |
8035 | ||
8036 | /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ | |
8037 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 | |
8038 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 | |
8039 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) | |
8040 | /* RXEQ Parameter */ | |
8041 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 | |
8042 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 | |
8043 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 | |
8044 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 | |
8045 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 | |
8046 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 | |
8047 | /* enum: TxMargin (PIPE) */ | |
8048 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 | |
8049 | /* enum: TxSwing (PIPE) */ | |
8050 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 | |
8051 | /* enum: De-emphasis coefficient C(-1) (PIPE) */ | |
8052 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 | |
8053 | /* enum: De-emphasis coefficient C(0) (PIPE) */ | |
8054 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 | |
8055 | /* enum: De-emphasis coefficient C(+1) (PIPE) */ | |
8056 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 | |
8057 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 | |
8058 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 | |
8059 | /* Enum values, see field(s): */ | |
8060 | /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ | |
8061 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 | |
8062 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 | |
8063 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 | |
8064 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 | |
8065 | ||
512bb06c BH |
8066 | /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ |
8067 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 | |
8068 | /* Requested operation */ | |
8069 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 | |
8070 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 | |
8071 | /* Align the arguments to 32 bits */ | |
8072 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 | |
8073 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 | |
8074 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 | |
8075 | ||
8076 | /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ | |
8077 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 | |
8078 | ||
8079 | /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ | |
8080 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 | |
8081 | /* Requested operation */ | |
8082 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 | |
8083 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 | |
8084 | /* Align the arguments to 32 bits */ | |
8085 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 | |
8086 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 | |
8087 | ||
8088 | /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ | |
8089 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 | |
8090 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 | |
8091 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) | |
8092 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 | |
8093 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 | |
8094 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 | |
8095 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 | |
8096 | ||
f2b0befd BH |
8097 | |
8098 | /***********************************/ | |
8099 | /* MC_CMD_LICENSING | |
8100 | * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition | |
8101 | */ | |
8102 | #define MC_CMD_LICENSING 0xf3 | |
8103 | ||
75122ec8 SS |
8104 | #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8105 | ||
f2b0befd BH |
8106 | /* MC_CMD_LICENSING_IN msgrequest */ |
8107 | #define MC_CMD_LICENSING_IN_LEN 4 | |
8108 | /* identifies the type of operation requested */ | |
8109 | #define MC_CMD_LICENSING_IN_OP_OFST 0 | |
8110 | /* enum: re-read and apply licenses after a license key partition update; note | |
8111 | * that this operation returns a zero-length response | |
8112 | */ | |
8113 | #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 | |
8114 | /* enum: report counts of installed licenses */ | |
8115 | #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 | |
8116 | ||
8117 | /* MC_CMD_LICENSING_OUT msgresponse */ | |
8118 | #define MC_CMD_LICENSING_OUT_LEN 28 | |
8119 | /* count of application keys which are valid */ | |
8120 | #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 | |
8121 | /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with | |
8122 | * MC_CMD_FC_OP_LICENSE) | |
8123 | */ | |
8124 | #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 | |
8125 | /* count of application keys which are invalid due to being blacklisted */ | |
8126 | #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 | |
8127 | /* count of application keys which are invalid due to being unverifiable */ | |
8128 | #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 | |
8129 | /* count of application keys which are invalid due to being for the wrong node | |
8130 | */ | |
8131 | #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 | |
8132 | /* licensing state (for diagnostics; the exact meaning of the bits in this | |
8133 | * field are private to the firmware) | |
8134 | */ | |
8135 | #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 | |
8136 | /* licensing subsystem self-test report (for manftest) */ | |
8137 | #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 | |
8138 | /* enum: licensing subsystem self-test failed */ | |
8139 | #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 | |
8140 | /* enum: licensing subsystem self-test passed */ | |
8141 | #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 | |
8142 | ||
8143 | ||
8144 | /***********************************/ | |
8145 | /* MC_CMD_MC2MC_PROXY | |
8146 | * Execute an arbitrary MCDI command on the slave MC of a dual-core device. | |
8147 | * This will fail on a single-core system. | |
8148 | */ | |
8149 | #define MC_CMD_MC2MC_PROXY 0xf4 | |
05a9320f | 8150 | |
75122ec8 SS |
8151 | #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8152 | ||
512bb06c BH |
8153 | /* MC_CMD_MC2MC_PROXY_IN msgrequest */ |
8154 | #define MC_CMD_MC2MC_PROXY_IN_LEN 0 | |
8155 | ||
8156 | /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ | |
8157 | #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 | |
8158 | ||
8159 | ||
8160 | /***********************************/ | |
8161 | /* MC_CMD_GET_LICENSED_APP_STATE | |
8162 | * Query the state of an individual licensed application. (Note that the actual | |
8163 | * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation | |
8164 | * or a reboot of the MC.) | |
8165 | */ | |
8166 | #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 | |
8167 | ||
75122ec8 SS |
8168 | #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8169 | ||
512bb06c BH |
8170 | /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ |
8171 | #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 | |
8172 | /* application ID to query (LICENSED_APP_ID_xxx) */ | |
8173 | #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 | |
8174 | ||
8175 | /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ | |
8176 | #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 | |
8177 | /* state of this application */ | |
8178 | #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 | |
8179 | /* enum: no (or invalid) license is present for the application */ | |
8180 | #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 | |
8181 | /* enum: a valid license is present for the application */ | |
8182 | #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 | |
8183 | ||
8184 | ||
8185 | /***********************************/ | |
8186 | /* MC_CMD_LICENSED_APP_OP | |
8187 | * Perform an action for an individual licensed application. | |
8188 | */ | |
8189 | #define MC_CMD_LICENSED_APP_OP 0xf6 | |
8190 | ||
75122ec8 SS |
8191 | #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8192 | ||
512bb06c BH |
8193 | /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ |
8194 | #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 | |
8195 | #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 | |
8196 | #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) | |
8197 | /* application ID */ | |
8198 | #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 | |
8199 | /* the type of operation requested */ | |
8200 | #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 | |
8201 | /* enum: validate application */ | |
8202 | #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 | |
8203 | /* arguments specific to this particular operation */ | |
8204 | #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 | |
8205 | #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 | |
8206 | #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 | |
8207 | #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 | |
8208 | ||
8209 | /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ | |
8210 | #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 | |
8211 | #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 | |
8212 | #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) | |
8213 | /* result specific to this particular operation */ | |
8214 | #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 | |
8215 | #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 | |
8216 | #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 | |
8217 | #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 | |
8218 | ||
8219 | /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ | |
8220 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 | |
8221 | /* application ID */ | |
8222 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 | |
8223 | /* the type of operation requested */ | |
8224 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 | |
8225 | /* validation challenge */ | |
8226 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 | |
8227 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 | |
8228 | ||
8229 | /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ | |
8230 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 | |
8231 | /* feature expiry (time_t) */ | |
8232 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 | |
8233 | /* validation response */ | |
8234 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 | |
8235 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 | |
8236 | ||
8237 | ||
8238 | /***********************************/ | |
8239 | /* MC_CMD_SET_PORT_SNIFF_CONFIG | |
8240 | * Configure port sniffing for the physical port associated with the calling | |
8241 | * function. Only a privileged function may change the port sniffing | |
8242 | * configuration. A copy of all traffic delivered to the host (non-promiscuous | |
8243 | * mode) or all traffic arriving at the port (promiscuous mode) may be | |
8244 | * delivered to a specific queue, or a set of queues with RSS. | |
8245 | */ | |
8246 | #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 | |
8247 | ||
75122ec8 SS |
8248 | #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
8249 | ||
512bb06c BH |
8250 | /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ |
8251 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 | |
8252 | /* configuration flags */ | |
8253 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 | |
8254 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 | |
8255 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 | |
8256 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 | |
8257 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 | |
8258 | /* receive queue handle (for RSS mode, this is the base queue) */ | |
8259 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 | |
8260 | /* receive mode */ | |
8261 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 | |
8262 | /* enum: receive to just the specified queue */ | |
8263 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 | |
8264 | /* enum: receive to multiple queues using RSS context */ | |
8265 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 | |
8266 | /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note | |
8267 | * that these handles should be considered opaque to the host, although a value | |
8268 | * of 0xFFFFFFFF is guaranteed never to be a valid handle. | |
8269 | */ | |
8270 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 | |
8271 | ||
8272 | /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ | |
8273 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 | |
8274 | ||
8275 | ||
8276 | /***********************************/ | |
8277 | /* MC_CMD_GET_PORT_SNIFF_CONFIG | |
8278 | * Obtain the current port sniffing configuration for the physical port | |
8279 | * associated with the calling function. Only a privileged function may read | |
8280 | * the configuration. | |
8281 | */ | |
8282 | #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 | |
8283 | ||
75122ec8 SS |
8284 | #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
8285 | ||
512bb06c BH |
8286 | /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ |
8287 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 | |
8288 | ||
8289 | /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ | |
8290 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 | |
8291 | /* configuration flags */ | |
8292 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 | |
8293 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 | |
8294 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 | |
8295 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 | |
8296 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 | |
8297 | /* receiving queue handle (for RSS mode, this is the base queue) */ | |
8298 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 | |
8299 | /* receive mode */ | |
8300 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 | |
8301 | /* enum: receiving to just the specified queue */ | |
8302 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 | |
8303 | /* enum: receiving to multiple queues using RSS context */ | |
8304 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 | |
8305 | /* RSS context (for RX_MODE_RSS) */ | |
8306 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 | |
8307 | ||
5297a98d | 8308 | |
f0d37f42 | 8309 | #endif /* MCDI_PCOL_H */ |