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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2005-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | /* Common definitions for all Efx net driver code */ | |
12 | ||
13 | #ifndef EFX_NET_DRIVER_H | |
14 | #define EFX_NET_DRIVER_H | |
15 | ||
8ceee660 BH |
16 | #include <linux/netdevice.h> |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/ethtool.h> | |
19 | #include <linux/if_vlan.h> | |
90d683af | 20 | #include <linux/timer.h> |
68e7f45e | 21 | #include <linux/mdio.h> |
8ceee660 BH |
22 | #include <linux/list.h> |
23 | #include <linux/pci.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/highmem.h> | |
26 | #include <linux/workqueue.h> | |
cd2d5b52 | 27 | #include <linux/mutex.h> |
0d322413 | 28 | #include <linux/rwsem.h> |
10ed61c4 | 29 | #include <linux/vmalloc.h> |
37b5a603 | 30 | #include <linux/i2c.h> |
45a3fd55 | 31 | #include <linux/mtd/mtd.h> |
36763266 | 32 | #include <net/busy_poll.h> |
8ceee660 BH |
33 | |
34 | #include "enum.h" | |
35 | #include "bitfield.h" | |
add72477 | 36 | #include "filter.h" |
8ceee660 | 37 | |
8ceee660 BH |
38 | /************************************************************************** |
39 | * | |
40 | * Build definitions | |
41 | * | |
42 | **************************************************************************/ | |
c5d5f5fd | 43 | |
8127d661 | 44 | #define EFX_DRIVER_VERSION "4.0" |
8ceee660 | 45 | |
5f3f9d6c | 46 | #ifdef DEBUG |
8ceee660 BH |
47 | #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) |
48 | #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) | |
49 | #else | |
50 | #define EFX_BUG_ON_PARANOID(x) do {} while (0) | |
51 | #define EFX_WARN_ON_PARANOID(x) do {} while (0) | |
52 | #endif | |
53 | ||
8ceee660 BH |
54 | /************************************************************************** |
55 | * | |
56 | * Efx data structures | |
57 | * | |
58 | **************************************************************************/ | |
59 | ||
a16e5b24 | 60 | #define EFX_MAX_CHANNELS 32U |
8ceee660 | 61 | #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS |
cd2d5b52 | 62 | #define EFX_EXTRA_CHANNEL_IOV 0 |
7c236c43 SH |
63 | #define EFX_EXTRA_CHANNEL_PTP 1 |
64 | #define EFX_MAX_EXTRA_CHANNELS 2U | |
8ceee660 | 65 | |
a4900ac9 BH |
66 | /* Checksum generation is a per-queue option in hardware, so each |
67 | * queue visible to the networking core is backed by two hardware TX | |
68 | * queues. */ | |
94b274bf BH |
69 | #define EFX_MAX_TX_TC 2 |
70 | #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) | |
71 | #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ | |
72 | #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ | |
73 | #define EFX_TXQ_TYPES 4 | |
74 | #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) | |
60ac1065 | 75 | |
85740cdf BH |
76 | /* Maximum possible MTU the driver supports */ |
77 | #define EFX_MAX_MTU (9 * 1024) | |
78 | ||
950c54df BH |
79 | /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page, |
80 | * and should be a multiple of the cache line size. | |
81 | */ | |
82 | #define EFX_RX_USR_BUF_SIZE (2048 - 256) | |
83 | ||
84 | /* If possible, we should ensure cache line alignment at start and end | |
85 | * of every buffer. Otherwise, we just need to ensure 4-byte | |
86 | * alignment of the network header. | |
87 | */ | |
88 | #if NET_IP_ALIGN == 0 | |
89 | #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES | |
90 | #else | |
91 | #define EFX_RX_BUF_ALIGNMENT 4 | |
92 | #endif | |
85740cdf | 93 | |
7c236c43 SH |
94 | /* Forward declare Precision Time Protocol (PTP) support structure. */ |
95 | struct efx_ptp_data; | |
9ec06595 | 96 | struct hwtstamp_config; |
7c236c43 | 97 | |
d4f2cecc BH |
98 | struct efx_self_tests; |
99 | ||
8ceee660 | 100 | /** |
caa75586 BH |
101 | * struct efx_buffer - A general-purpose DMA buffer |
102 | * @addr: host base address of the buffer | |
8ceee660 BH |
103 | * @dma_addr: DMA base address of the buffer |
104 | * @len: Buffer length, in bytes | |
8ceee660 | 105 | * |
caa75586 BH |
106 | * The NIC uses these buffers for its interrupt status registers and |
107 | * MAC stats dumps. | |
8ceee660 | 108 | */ |
caa75586 | 109 | struct efx_buffer { |
8ceee660 BH |
110 | void *addr; |
111 | dma_addr_t dma_addr; | |
112 | unsigned int len; | |
caa75586 BH |
113 | }; |
114 | ||
115 | /** | |
116 | * struct efx_special_buffer - DMA buffer entered into buffer table | |
117 | * @buf: Standard &struct efx_buffer | |
118 | * @index: Buffer index within controller;s buffer table | |
119 | * @entries: Number of buffer table entries | |
120 | * | |
121 | * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE. | |
122 | * Event and descriptor rings are addressed via one or more buffer | |
123 | * table entries (and so can be physically non-contiguous, although we | |
124 | * currently do not take advantage of that). On Falcon and Siena we | |
125 | * have to take care of allocating and initialising the entries | |
126 | * ourselves. On later hardware this is managed by the firmware and | |
127 | * @index and @entries are left as 0. | |
128 | */ | |
129 | struct efx_special_buffer { | |
130 | struct efx_buffer buf; | |
5bbe2f4f BH |
131 | unsigned int index; |
132 | unsigned int entries; | |
8ceee660 BH |
133 | }; |
134 | ||
135 | /** | |
7668ff9c BH |
136 | * struct efx_tx_buffer - buffer state for a TX descriptor |
137 | * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be | |
138 | * freed when descriptor completes | |
f7251a9c BH |
139 | * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be |
140 | * freed when descriptor completes. | |
ba8977bd | 141 | * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor. |
8ceee660 | 142 | * @dma_addr: DMA address of the fragment. |
7668ff9c | 143 | * @flags: Flags for allocation and DMA mapping type |
8ceee660 BH |
144 | * @len: Length of this fragment. |
145 | * This field is zero when the queue slot is empty. | |
8ceee660 | 146 | * @unmap_len: Length of this fragment to unmap |
2acdb92e AR |
147 | * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping. |
148 | * Only valid if @unmap_len != 0. | |
8ceee660 BH |
149 | */ |
150 | struct efx_tx_buffer { | |
7668ff9c BH |
151 | union { |
152 | const struct sk_buff *skb; | |
f7251a9c | 153 | void *heap_buf; |
7668ff9c | 154 | }; |
ba8977bd BH |
155 | union { |
156 | efx_qword_t option; | |
157 | dma_addr_t dma_addr; | |
158 | }; | |
7668ff9c | 159 | unsigned short flags; |
8ceee660 | 160 | unsigned short len; |
8ceee660 | 161 | unsigned short unmap_len; |
2acdb92e | 162 | unsigned short dma_offset; |
8ceee660 | 163 | }; |
7668ff9c BH |
164 | #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */ |
165 | #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */ | |
f7251a9c | 166 | #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */ |
7668ff9c | 167 | #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ |
ba8977bd | 168 | #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */ |
8ceee660 BH |
169 | |
170 | /** | |
171 | * struct efx_tx_queue - An Efx TX queue | |
172 | * | |
173 | * This is a ring buffer of TX fragments. | |
174 | * Since the TX completion path always executes on the same | |
175 | * CPU and the xmit path can operate on different CPUs, | |
176 | * performance is increased by ensuring that the completion | |
177 | * path and the xmit path operate on different cache lines. | |
178 | * This is particularly important if the xmit path is always | |
179 | * executing on one CPU which is different from the completion | |
180 | * path. There is also a cache line for members which are | |
181 | * read but not written on the fast path. | |
182 | * | |
183 | * @efx: The associated Efx NIC | |
184 | * @queue: DMA queue number | |
93171b14 | 185 | * @tso_version: Version of TSO in use for this queue. |
8ceee660 | 186 | * @channel: The associated channel |
c04bfc6b | 187 | * @core_txq: The networking core TX queue structure |
8ceee660 | 188 | * @buffer: The software buffer ring |
f7251a9c | 189 | * @tsoh_page: Array of pages of TSO header buffers |
8ceee660 | 190 | * @txd: The hardware descriptor ring |
ecc910f5 | 191 | * @ptr_mask: The size of the ring minus 1. |
183233be BH |
192 | * @piobuf: PIO buffer region for this TX queue (shared with its partner). |
193 | * Size of the region is efx_piobuf_size. | |
194 | * @piobuf_offset: Buffer offset to be specified in PIO descriptors | |
94b274bf | 195 | * @initialised: Has hardware queue been initialised? |
8ceee660 BH |
196 | * @read_count: Current read pointer. |
197 | * This is the number of buffers that have been removed from both rings. | |
cd38557d BH |
198 | * @old_write_count: The value of @write_count when last checked. |
199 | * This is here for performance reasons. The xmit path will | |
200 | * only get the up-to-date value of @write_count if this | |
201 | * variable indicates that the queue is empty. This is to | |
202 | * avoid cache-line ping-pong between the xmit path and the | |
203 | * completion path. | |
02e12165 | 204 | * @merge_events: Number of TX merged completion events |
8ceee660 BH |
205 | * @insert_count: Current insert pointer |
206 | * This is the number of buffers that have been added to the | |
207 | * software ring. | |
208 | * @write_count: Current write pointer | |
209 | * This is the number of buffers that have been added to the | |
210 | * hardware ring. | |
211 | * @old_read_count: The value of read_count when last checked. | |
212 | * This is here for performance reasons. The xmit path will | |
213 | * only get the up-to-date value of read_count if this | |
214 | * variable indicates that the queue is full. This is to | |
215 | * avoid cache-line ping-pong between the xmit path and the | |
216 | * completion path. | |
b9b39b62 BH |
217 | * @tso_bursts: Number of times TSO xmit invoked by kernel |
218 | * @tso_long_headers: Number of packets with headers too long for standard | |
219 | * blocks | |
220 | * @tso_packets: Number of packets via the TSO xmit path | |
cd38557d | 221 | * @pushes: Number of times the TX push feature has been used |
ee45fd92 | 222 | * @pio_packets: Number of times the TX PIO feature has been used |
b2663a4f | 223 | * @xmit_more_available: Are any packets waiting to be pushed to the NIC |
cd38557d BH |
224 | * @empty_read_count: If the completion path has seen the queue as empty |
225 | * and the transmission path has not yet checked this, the value of | |
226 | * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. | |
8ceee660 BH |
227 | */ |
228 | struct efx_tx_queue { | |
229 | /* Members which don't change on the fast path */ | |
230 | struct efx_nic *efx ____cacheline_aligned_in_smp; | |
a4900ac9 | 231 | unsigned queue; |
93171b14 | 232 | unsigned int tso_version; |
8ceee660 | 233 | struct efx_channel *channel; |
c04bfc6b | 234 | struct netdev_queue *core_txq; |
8ceee660 | 235 | struct efx_tx_buffer *buffer; |
f7251a9c | 236 | struct efx_buffer *tsoh_page; |
8ceee660 | 237 | struct efx_special_buffer txd; |
ecc910f5 | 238 | unsigned int ptr_mask; |
183233be BH |
239 | void __iomem *piobuf; |
240 | unsigned int piobuf_offset; | |
94b274bf | 241 | bool initialised; |
8ceee660 BH |
242 | |
243 | /* Members used mainly on the completion path */ | |
244 | unsigned int read_count ____cacheline_aligned_in_smp; | |
cd38557d | 245 | unsigned int old_write_count; |
02e12165 | 246 | unsigned int merge_events; |
c936835c PD |
247 | unsigned int bytes_compl; |
248 | unsigned int pkts_compl; | |
8ceee660 BH |
249 | |
250 | /* Members used only on the xmit path */ | |
251 | unsigned int insert_count ____cacheline_aligned_in_smp; | |
252 | unsigned int write_count; | |
253 | unsigned int old_read_count; | |
b9b39b62 BH |
254 | unsigned int tso_bursts; |
255 | unsigned int tso_long_headers; | |
256 | unsigned int tso_packets; | |
cd38557d | 257 | unsigned int pushes; |
ee45fd92 | 258 | unsigned int pio_packets; |
b2663a4f | 259 | bool xmit_more_available; |
8ccf3800 AR |
260 | /* Statistics to supplement MAC stats */ |
261 | unsigned long tx_packets; | |
cd38557d BH |
262 | |
263 | /* Members shared between paths and sometimes updated */ | |
264 | unsigned int empty_read_count ____cacheline_aligned_in_smp; | |
265 | #define EFX_EMPTY_COUNT_VALID 0x80000000 | |
525d9e82 | 266 | atomic_t flush_outstanding; |
8ceee660 BH |
267 | }; |
268 | ||
269 | /** | |
270 | * struct efx_rx_buffer - An Efx RX data buffer | |
271 | * @dma_addr: DMA base address of the buffer | |
97d48a10 | 272 | * @page: The associated page buffer. |
db339569 | 273 | * Will be %NULL if the buffer slot is currently free. |
b74e3e8c BH |
274 | * @page_offset: If pending: offset in @page of DMA base address. |
275 | * If completed: offset in @page of Ethernet header. | |
80c2e716 BH |
276 | * @len: If pending: length for DMA descriptor. |
277 | * If completed: received length, excluding hash prefix. | |
85740cdf BH |
278 | * @flags: Flags for buffer and packet state. These are only set on the |
279 | * first buffer of a scattered packet. | |
8ceee660 BH |
280 | */ |
281 | struct efx_rx_buffer { | |
282 | dma_addr_t dma_addr; | |
97d48a10 | 283 | struct page *page; |
b590ace0 BH |
284 | u16 page_offset; |
285 | u16 len; | |
db339569 | 286 | u16 flags; |
8ceee660 | 287 | }; |
179ea7f0 | 288 | #define EFX_RX_BUF_LAST_IN_PAGE 0x0001 |
db339569 BH |
289 | #define EFX_RX_PKT_CSUMMED 0x0002 |
290 | #define EFX_RX_PKT_DISCARD 0x0004 | |
d07df8ec | 291 | #define EFX_RX_PKT_TCP 0x0040 |
3dced740 | 292 | #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */ |
8ceee660 | 293 | |
62b330ba SH |
294 | /** |
295 | * struct efx_rx_page_state - Page-based rx buffer state | |
296 | * | |
297 | * Inserted at the start of every page allocated for receive buffers. | |
298 | * Used to facilitate sharing dma mappings between recycled rx buffers | |
299 | * and those passed up to the kernel. | |
300 | * | |
62b330ba SH |
301 | * @dma_addr: The dma address of this page. |
302 | */ | |
303 | struct efx_rx_page_state { | |
62b330ba SH |
304 | dma_addr_t dma_addr; |
305 | ||
306 | unsigned int __pad[0] ____cacheline_aligned; | |
307 | }; | |
308 | ||
8ceee660 BH |
309 | /** |
310 | * struct efx_rx_queue - An Efx RX queue | |
311 | * @efx: The associated Efx NIC | |
79d68b37 SH |
312 | * @core_index: Index of network core RX queue. Will be >= 0 iff this |
313 | * is associated with a real RX queue. | |
8ceee660 BH |
314 | * @buffer: The software buffer ring |
315 | * @rxd: The hardware descriptor ring | |
ecc910f5 | 316 | * @ptr_mask: The size of the ring minus 1. |
d8aec745 | 317 | * @refill_enabled: Enable refill whenever fill level is low |
9f2cb71c BH |
318 | * @flush_pending: Set when a RX flush is pending. Has the same lifetime as |
319 | * @rxq_flush_pending. | |
8ceee660 BH |
320 | * @added_count: Number of buffers added to the receive queue. |
321 | * @notified_count: Number of buffers given to NIC (<= @added_count). | |
322 | * @removed_count: Number of buffers removed from the receive queue. | |
e8c68c0a JC |
323 | * @scatter_n: Used by NIC specific receive code. |
324 | * @scatter_len: Used by NIC specific receive code. | |
2768935a DP |
325 | * @page_ring: The ring to store DMA mapped pages for reuse. |
326 | * @page_add: Counter to calculate the write pointer for the recycle ring. | |
327 | * @page_remove: Counter to calculate the read pointer for the recycle ring. | |
328 | * @page_recycle_count: The number of pages that have been recycled. | |
329 | * @page_recycle_failed: The number of pages that couldn't be recycled because | |
330 | * the kernel still held a reference to them. | |
331 | * @page_recycle_full: The number of pages that were released because the | |
332 | * recycle ring was full. | |
333 | * @page_ptr_mask: The number of pages in the RX recycle ring minus 1. | |
8ceee660 BH |
334 | * @max_fill: RX descriptor maximum fill level (<= ring size) |
335 | * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill | |
336 | * (<= @max_fill) | |
8ceee660 BH |
337 | * @min_fill: RX descriptor minimum non-zero fill level. |
338 | * This records the minimum fill level observed when a ring | |
339 | * refill was triggered. | |
2768935a | 340 | * @recycle_count: RX buffer recycle counter. |
90d683af | 341 | * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). |
8ceee660 BH |
342 | */ |
343 | struct efx_rx_queue { | |
344 | struct efx_nic *efx; | |
79d68b37 | 345 | int core_index; |
8ceee660 BH |
346 | struct efx_rx_buffer *buffer; |
347 | struct efx_special_buffer rxd; | |
ecc910f5 | 348 | unsigned int ptr_mask; |
d8aec745 | 349 | bool refill_enabled; |
9f2cb71c | 350 | bool flush_pending; |
8ceee660 | 351 | |
9bc2fc9b BH |
352 | unsigned int added_count; |
353 | unsigned int notified_count; | |
354 | unsigned int removed_count; | |
85740cdf | 355 | unsigned int scatter_n; |
e8c68c0a | 356 | unsigned int scatter_len; |
2768935a DP |
357 | struct page **page_ring; |
358 | unsigned int page_add; | |
359 | unsigned int page_remove; | |
360 | unsigned int page_recycle_count; | |
361 | unsigned int page_recycle_failed; | |
362 | unsigned int page_recycle_full; | |
363 | unsigned int page_ptr_mask; | |
8ceee660 BH |
364 | unsigned int max_fill; |
365 | unsigned int fast_fill_trigger; | |
8ceee660 BH |
366 | unsigned int min_fill; |
367 | unsigned int min_overfill; | |
2768935a | 368 | unsigned int recycle_count; |
90d683af | 369 | struct timer_list slow_fill; |
8ceee660 | 370 | unsigned int slow_fill_count; |
8ccf3800 AR |
371 | /* Statistics to supplement MAC stats */ |
372 | unsigned long rx_packets; | |
8ceee660 BH |
373 | }; |
374 | ||
bd9a265d JC |
375 | enum efx_sync_events_state { |
376 | SYNC_EVENTS_DISABLED = 0, | |
377 | SYNC_EVENTS_QUIESCENT, | |
378 | SYNC_EVENTS_REQUESTED, | |
379 | SYNC_EVENTS_VALID, | |
380 | }; | |
381 | ||
8ceee660 BH |
382 | /** |
383 | * struct efx_channel - An Efx channel | |
384 | * | |
385 | * A channel comprises an event queue, at least one TX queue, at least | |
386 | * one RX queue, and an associated tasklet for processing the event | |
387 | * queue. | |
388 | * | |
389 | * @efx: Associated Efx NIC | |
8ceee660 | 390 | * @channel: Channel instance number |
7f967c01 | 391 | * @type: Channel type definition |
be3fc09c | 392 | * @eventq_init: Event queue initialised flag |
8ceee660 BH |
393 | * @enabled: Channel enabled indicator |
394 | * @irq: IRQ number (MSI and MSI-X only) | |
0d86ebd8 | 395 | * @irq_moderation: IRQ moderation value (in hardware ticks) |
8ceee660 BH |
396 | * @napi_dev: Net device used with NAPI |
397 | * @napi_str: NAPI control structure | |
36763266 AR |
398 | * @state: state for NAPI vs busy polling |
399 | * @state_lock: lock protecting @state | |
8ceee660 | 400 | * @eventq: Event queue buffer |
ecc910f5 | 401 | * @eventq_mask: Event queue pointer mask |
8ceee660 | 402 | * @eventq_read_ptr: Event queue read pointer |
dd40781e | 403 | * @event_test_cpu: Last CPU to handle interrupt or test event for this channel |
6fb70fd1 BH |
404 | * @irq_count: Number of IRQs since last adaptive moderation decision |
405 | * @irq_mod_score: IRQ moderation score | |
faf8dcc1 JC |
406 | * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS, |
407 | * indexed by filter ID | |
8ceee660 | 408 | * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors |
8ceee660 BH |
409 | * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors |
410 | * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors | |
c1ac403b | 411 | * @n_rx_mcast_mismatch: Count of unmatched multicast frames |
8ceee660 BH |
412 | * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors |
413 | * @n_rx_overlength: Count of RX_OVERLENGTH errors | |
414 | * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun | |
85740cdf BH |
415 | * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to |
416 | * lack of descriptors | |
8127d661 BH |
417 | * @n_rx_merge_events: Number of RX merged completion events |
418 | * @n_rx_merge_packets: Number of RX packets completed by merged events | |
85740cdf BH |
419 | * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by |
420 | * __efx_rx_packet(), or zero if there is none | |
421 | * @rx_pkt_index: Ring index of first buffer for next packet to be delivered | |
422 | * by __efx_rx_packet(), if @rx_pkt_n_frags != 0 | |
8313aca3 | 423 | * @rx_queue: RX queue for this channel |
8313aca3 | 424 | * @tx_queue: TX queues for this channel |
bd9a265d JC |
425 | * @sync_events_state: Current state of sync events on this channel |
426 | * @sync_timestamp_major: Major part of the last ptp sync event | |
427 | * @sync_timestamp_minor: Minor part of the last ptp sync event | |
8ceee660 BH |
428 | */ |
429 | struct efx_channel { | |
430 | struct efx_nic *efx; | |
8ceee660 | 431 | int channel; |
7f967c01 | 432 | const struct efx_channel_type *type; |
be3fc09c | 433 | bool eventq_init; |
dc8cfa55 | 434 | bool enabled; |
8ceee660 | 435 | int irq; |
8ceee660 BH |
436 | unsigned int irq_moderation; |
437 | struct net_device *napi_dev; | |
438 | struct napi_struct napi_str; | |
36763266 | 439 | #ifdef CONFIG_NET_RX_BUSY_POLL |
c0f9c7e4 BK |
440 | unsigned long busy_poll_state; |
441 | #endif | |
8ceee660 | 442 | struct efx_special_buffer eventq; |
ecc910f5 | 443 | unsigned int eventq_mask; |
8ceee660 | 444 | unsigned int eventq_read_ptr; |
dd40781e | 445 | int event_test_cpu; |
8ceee660 | 446 | |
6fb70fd1 BH |
447 | unsigned int irq_count; |
448 | unsigned int irq_mod_score; | |
64d8ad6d BH |
449 | #ifdef CONFIG_RFS_ACCEL |
450 | unsigned int rfs_filters_added; | |
faf8dcc1 JC |
451 | #define RPS_FLOW_ID_INVALID 0xFFFFFFFF |
452 | u32 *rps_flow_id; | |
64d8ad6d | 453 | #endif |
6fb70fd1 | 454 | |
8ceee660 | 455 | unsigned n_rx_tobe_disc; |
8ceee660 BH |
456 | unsigned n_rx_ip_hdr_chksum_err; |
457 | unsigned n_rx_tcp_udp_chksum_err; | |
c1ac403b | 458 | unsigned n_rx_mcast_mismatch; |
8ceee660 BH |
459 | unsigned n_rx_frm_trunc; |
460 | unsigned n_rx_overlength; | |
461 | unsigned n_skbuff_leaks; | |
85740cdf | 462 | unsigned int n_rx_nodesc_trunc; |
8127d661 BH |
463 | unsigned int n_rx_merge_events; |
464 | unsigned int n_rx_merge_packets; | |
8ceee660 | 465 | |
85740cdf BH |
466 | unsigned int rx_pkt_n_frags; |
467 | unsigned int rx_pkt_index; | |
8ceee660 | 468 | |
8313aca3 | 469 | struct efx_rx_queue rx_queue; |
94b274bf | 470 | struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; |
bd9a265d JC |
471 | |
472 | enum efx_sync_events_state sync_events_state; | |
473 | u32 sync_timestamp_major; | |
474 | u32 sync_timestamp_minor; | |
8ceee660 BH |
475 | }; |
476 | ||
36763266 | 477 | #ifdef CONFIG_NET_RX_BUSY_POLL |
c0f9c7e4 BK |
478 | enum efx_channel_busy_poll_state { |
479 | EFX_CHANNEL_STATE_IDLE = 0, | |
480 | EFX_CHANNEL_STATE_NAPI = BIT(0), | |
481 | EFX_CHANNEL_STATE_NAPI_REQ_BIT = 1, | |
482 | EFX_CHANNEL_STATE_NAPI_REQ = BIT(1), | |
483 | EFX_CHANNEL_STATE_POLL_BIT = 2, | |
484 | EFX_CHANNEL_STATE_POLL = BIT(2), | |
485 | EFX_CHANNEL_STATE_DISABLE_BIT = 3, | |
486 | }; | |
487 | ||
488 | static inline void efx_channel_busy_poll_init(struct efx_channel *channel) | |
36763266 | 489 | { |
c0f9c7e4 | 490 | WRITE_ONCE(channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE); |
36763266 AR |
491 | } |
492 | ||
493 | /* Called from the device poll routine to get ownership of a channel. */ | |
494 | static inline bool efx_channel_lock_napi(struct efx_channel *channel) | |
495 | { | |
c0f9c7e4 BK |
496 | unsigned long prev, old = READ_ONCE(channel->busy_poll_state); |
497 | ||
498 | while (1) { | |
499 | switch (old) { | |
500 | case EFX_CHANNEL_STATE_POLL: | |
501 | /* Ensure efx_channel_try_lock_poll() wont starve us */ | |
502 | set_bit(EFX_CHANNEL_STATE_NAPI_REQ_BIT, | |
503 | &channel->busy_poll_state); | |
504 | /* fallthrough */ | |
505 | case EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_NAPI_REQ: | |
506 | return false; | |
507 | default: | |
508 | break; | |
509 | } | |
510 | prev = cmpxchg(&channel->busy_poll_state, old, | |
511 | EFX_CHANNEL_STATE_NAPI); | |
512 | if (unlikely(prev != old)) { | |
513 | /* This is likely to mean we've just entered polling | |
514 | * state. Go back round to set the REQ bit. | |
515 | */ | |
516 | old = prev; | |
517 | continue; | |
518 | } | |
519 | return true; | |
36763266 | 520 | } |
36763266 AR |
521 | } |
522 | ||
523 | static inline void efx_channel_unlock_napi(struct efx_channel *channel) | |
524 | { | |
c0f9c7e4 BK |
525 | /* Make sure write has completed from efx_channel_lock_napi() */ |
526 | smp_wmb(); | |
527 | WRITE_ONCE(channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE); | |
36763266 AR |
528 | } |
529 | ||
530 | /* Called from efx_busy_poll(). */ | |
c0f9c7e4 | 531 | static inline bool efx_channel_try_lock_poll(struct efx_channel *channel) |
36763266 | 532 | { |
c0f9c7e4 BK |
533 | return cmpxchg(&channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE, |
534 | EFX_CHANNEL_STATE_POLL) == EFX_CHANNEL_STATE_IDLE; | |
36763266 AR |
535 | } |
536 | ||
36763266 AR |
537 | static inline void efx_channel_unlock_poll(struct efx_channel *channel) |
538 | { | |
c0f9c7e4 | 539 | clear_bit_unlock(EFX_CHANNEL_STATE_POLL_BIT, &channel->busy_poll_state); |
36763266 AR |
540 | } |
541 | ||
36763266 AR |
542 | static inline bool efx_channel_busy_polling(struct efx_channel *channel) |
543 | { | |
c0f9c7e4 | 544 | return test_bit(EFX_CHANNEL_STATE_POLL_BIT, &channel->busy_poll_state); |
36763266 AR |
545 | } |
546 | ||
547 | static inline void efx_channel_enable(struct efx_channel *channel) | |
548 | { | |
c0f9c7e4 BK |
549 | clear_bit_unlock(EFX_CHANNEL_STATE_DISABLE_BIT, |
550 | &channel->busy_poll_state); | |
36763266 AR |
551 | } |
552 | ||
c0f9c7e4 BK |
553 | /* Stop further polling or napi access. |
554 | * Returns false if the channel is currently busy polling. | |
555 | */ | |
36763266 AR |
556 | static inline bool efx_channel_disable(struct efx_channel *channel) |
557 | { | |
c0f9c7e4 BK |
558 | set_bit(EFX_CHANNEL_STATE_DISABLE_BIT, &channel->busy_poll_state); |
559 | /* Implicit barrier in efx_channel_busy_polling() */ | |
560 | return !efx_channel_busy_polling(channel); | |
36763266 AR |
561 | } |
562 | ||
563 | #else /* CONFIG_NET_RX_BUSY_POLL */ | |
564 | ||
c0f9c7e4 | 565 | static inline void efx_channel_busy_poll_init(struct efx_channel *channel) |
36763266 AR |
566 | { |
567 | } | |
568 | ||
569 | static inline bool efx_channel_lock_napi(struct efx_channel *channel) | |
570 | { | |
571 | return true; | |
572 | } | |
573 | ||
574 | static inline void efx_channel_unlock_napi(struct efx_channel *channel) | |
575 | { | |
576 | } | |
577 | ||
c0f9c7e4 | 578 | static inline bool efx_channel_try_lock_poll(struct efx_channel *channel) |
36763266 AR |
579 | { |
580 | return false; | |
581 | } | |
582 | ||
583 | static inline void efx_channel_unlock_poll(struct efx_channel *channel) | |
584 | { | |
585 | } | |
586 | ||
587 | static inline bool efx_channel_busy_polling(struct efx_channel *channel) | |
588 | { | |
589 | return false; | |
590 | } | |
591 | ||
592 | static inline void efx_channel_enable(struct efx_channel *channel) | |
593 | { | |
594 | } | |
595 | ||
596 | static inline bool efx_channel_disable(struct efx_channel *channel) | |
597 | { | |
598 | return true; | |
599 | } | |
600 | #endif /* CONFIG_NET_RX_BUSY_POLL */ | |
601 | ||
d8291187 BH |
602 | /** |
603 | * struct efx_msi_context - Context for each MSI | |
604 | * @efx: The associated NIC | |
605 | * @index: Index of the channel/IRQ | |
606 | * @name: Name of the channel/IRQ | |
607 | * | |
608 | * Unlike &struct efx_channel, this is never reallocated and is always | |
609 | * safe for the IRQ handler to access. | |
610 | */ | |
611 | struct efx_msi_context { | |
612 | struct efx_nic *efx; | |
613 | unsigned int index; | |
614 | char name[IFNAMSIZ + 6]; | |
615 | }; | |
616 | ||
7f967c01 BH |
617 | /** |
618 | * struct efx_channel_type - distinguishes traffic and extra channels | |
619 | * @handle_no_channel: Handle failure to allocate an extra channel | |
620 | * @pre_probe: Set up extra state prior to initialisation | |
621 | * @post_remove: Tear down extra state after finalisation, if allocated. | |
622 | * May be called on channels that have not been probed. | |
623 | * @get_name: Generate the channel's name (used for its IRQ handler) | |
624 | * @copy: Copy the channel state prior to reallocation. May be %NULL if | |
625 | * reallocation is not supported. | |
c31e5f9f | 626 | * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() |
7f967c01 BH |
627 | * @keep_eventq: Flag for whether event queue should be kept initialised |
628 | * while the device is stopped | |
629 | */ | |
630 | struct efx_channel_type { | |
631 | void (*handle_no_channel)(struct efx_nic *); | |
632 | int (*pre_probe)(struct efx_channel *); | |
c31e5f9f | 633 | void (*post_remove)(struct efx_channel *); |
7f967c01 BH |
634 | void (*get_name)(struct efx_channel *, char *buf, size_t len); |
635 | struct efx_channel *(*copy)(const struct efx_channel *); | |
4a74dc65 | 636 | bool (*receive_skb)(struct efx_channel *, struct sk_buff *); |
7f967c01 BH |
637 | bool keep_eventq; |
638 | }; | |
639 | ||
398468ed BH |
640 | enum efx_led_mode { |
641 | EFX_LED_OFF = 0, | |
642 | EFX_LED_ON = 1, | |
643 | EFX_LED_DEFAULT = 2 | |
644 | }; | |
645 | ||
c459302d BH |
646 | #define STRING_TABLE_LOOKUP(val, member) \ |
647 | ((val) < member ## _max) ? member ## _names[val] : "(invalid)" | |
648 | ||
18e83e4c | 649 | extern const char *const efx_loopback_mode_names[]; |
c459302d BH |
650 | extern const unsigned int efx_loopback_mode_max; |
651 | #define LOOPBACK_MODE(efx) \ | |
652 | STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) | |
653 | ||
18e83e4c | 654 | extern const char *const efx_reset_type_names[]; |
c459302d BH |
655 | extern const unsigned int efx_reset_type_max; |
656 | #define RESET_TYPE(type) \ | |
657 | STRING_TABLE_LOOKUP(type, efx_reset_type) | |
3273c2e8 | 658 | |
8ceee660 BH |
659 | enum efx_int_mode { |
660 | /* Be careful if altering to correct macro below */ | |
661 | EFX_INT_MODE_MSIX = 0, | |
662 | EFX_INT_MODE_MSI = 1, | |
663 | EFX_INT_MODE_LEGACY = 2, | |
664 | EFX_INT_MODE_MAX /* Insert any new items before this */ | |
665 | }; | |
666 | #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) | |
667 | ||
8ceee660 | 668 | enum nic_state { |
f16aeea0 BH |
669 | STATE_UNINIT = 0, /* device being probed/removed or is frozen */ |
670 | STATE_READY = 1, /* hardware ready and netdev registered */ | |
671 | STATE_DISABLED = 2, /* device disabled due to hardware errors */ | |
626950db | 672 | STATE_RECOVERY = 3, /* device recovering from PCI error */ |
8ceee660 BH |
673 | }; |
674 | ||
8ceee660 BH |
675 | /* Forward declaration */ |
676 | struct efx_nic; | |
677 | ||
678 | /* Pseudo bit-mask flow control field */ | |
b5626946 DM |
679 | #define EFX_FC_RX FLOW_CTRL_RX |
680 | #define EFX_FC_TX FLOW_CTRL_TX | |
681 | #define EFX_FC_AUTO 4 | |
8ceee660 | 682 | |
eb50c0d6 BH |
683 | /** |
684 | * struct efx_link_state - Current state of the link | |
685 | * @up: Link is up | |
686 | * @fd: Link is full-duplex | |
687 | * @fc: Actual flow control flags | |
688 | * @speed: Link speed (Mbps) | |
689 | */ | |
690 | struct efx_link_state { | |
691 | bool up; | |
692 | bool fd; | |
b5626946 | 693 | u8 fc; |
eb50c0d6 BH |
694 | unsigned int speed; |
695 | }; | |
696 | ||
fdaa9aed SH |
697 | static inline bool efx_link_state_equal(const struct efx_link_state *left, |
698 | const struct efx_link_state *right) | |
699 | { | |
700 | return left->up == right->up && left->fd == right->fd && | |
701 | left->fc == right->fc && left->speed == right->speed; | |
702 | } | |
703 | ||
8ceee660 BH |
704 | /** |
705 | * struct efx_phy_operations - Efx PHY operations table | |
c1c4f453 BH |
706 | * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, |
707 | * efx->loopback_modes. | |
8ceee660 BH |
708 | * @init: Initialise PHY |
709 | * @fini: Shut down PHY | |
710 | * @reconfigure: Reconfigure PHY (e.g. for new link parameters) | |
fdaa9aed SH |
711 | * @poll: Update @link_state and report whether it changed. |
712 | * Serialised by the mac_lock. | |
177dfcd8 BH |
713 | * @get_settings: Get ethtool settings. Serialised by the mac_lock. |
714 | * @set_settings: Set ethtool settings. Serialised by the mac_lock. | |
af4ad9bc | 715 | * @set_npage_adv: Set abilities advertised in (Extended) Next Page |
04cc8cac | 716 | * (only needed where AN bit is set in mmds) |
4f16c073 | 717 | * @test_alive: Test that PHY is 'alive' (online) |
c1c4f453 | 718 | * @test_name: Get the name of a PHY-specific test/result |
4f16c073 | 719 | * @run_tests: Run tests and record results as appropriate (offline). |
1796721a | 720 | * Flags are the ethtool tests flags. |
8ceee660 BH |
721 | */ |
722 | struct efx_phy_operations { | |
c1c4f453 | 723 | int (*probe) (struct efx_nic *efx); |
8ceee660 BH |
724 | int (*init) (struct efx_nic *efx); |
725 | void (*fini) (struct efx_nic *efx); | |
ff3b00a0 | 726 | void (*remove) (struct efx_nic *efx); |
d3245b28 | 727 | int (*reconfigure) (struct efx_nic *efx); |
fdaa9aed | 728 | bool (*poll) (struct efx_nic *efx); |
177dfcd8 BH |
729 | void (*get_settings) (struct efx_nic *efx, |
730 | struct ethtool_cmd *ecmd); | |
731 | int (*set_settings) (struct efx_nic *efx, | |
732 | struct ethtool_cmd *ecmd); | |
af4ad9bc | 733 | void (*set_npage_adv) (struct efx_nic *efx, u32); |
4f16c073 | 734 | int (*test_alive) (struct efx_nic *efx); |
c1c4f453 | 735 | const char *(*test_name) (struct efx_nic *efx, unsigned int index); |
1796721a | 736 | int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); |
c087bd2c SH |
737 | int (*get_module_eeprom) (struct efx_nic *efx, |
738 | struct ethtool_eeprom *ee, | |
739 | u8 *data); | |
740 | int (*get_module_info) (struct efx_nic *efx, | |
741 | struct ethtool_modinfo *modinfo); | |
8ceee660 BH |
742 | }; |
743 | ||
f8b87c17 | 744 | /** |
49ce9c2c | 745 | * enum efx_phy_mode - PHY operating mode flags |
f8b87c17 BH |
746 | * @PHY_MODE_NORMAL: on and should pass traffic |
747 | * @PHY_MODE_TX_DISABLED: on with TX disabled | |
3e133c44 BH |
748 | * @PHY_MODE_LOW_POWER: set to low power through MDIO |
749 | * @PHY_MODE_OFF: switched off through external control | |
f8b87c17 BH |
750 | * @PHY_MODE_SPECIAL: on but will not pass traffic |
751 | */ | |
752 | enum efx_phy_mode { | |
753 | PHY_MODE_NORMAL = 0, | |
754 | PHY_MODE_TX_DISABLED = 1, | |
3e133c44 BH |
755 | PHY_MODE_LOW_POWER = 2, |
756 | PHY_MODE_OFF = 4, | |
f8b87c17 BH |
757 | PHY_MODE_SPECIAL = 8, |
758 | }; | |
759 | ||
760 | static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) | |
761 | { | |
8c8661e4 | 762 | return !!(mode & ~PHY_MODE_TX_DISABLED); |
f8b87c17 BH |
763 | } |
764 | ||
cd0ecc9a BH |
765 | /** |
766 | * struct efx_hw_stat_desc - Description of a hardware statistic | |
767 | * @name: Name of the statistic as visible through ethtool, or %NULL if | |
768 | * it should not be exposed | |
769 | * @dma_width: Width in bits (0 for non-DMA statistics) | |
770 | * @offset: Offset within stats (ignored for non-DMA statistics) | |
8ceee660 | 771 | */ |
cd0ecc9a BH |
772 | struct efx_hw_stat_desc { |
773 | const char *name; | |
774 | u16 dma_width; | |
775 | u16 offset; | |
8ceee660 BH |
776 | }; |
777 | ||
778 | /* Number of bits used in a multicast filter hash address */ | |
779 | #define EFX_MCAST_HASH_BITS 8 | |
780 | ||
781 | /* Number of (single-bit) entries in a multicast filter hash */ | |
782 | #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) | |
783 | ||
784 | /* An Efx multicast filter hash */ | |
785 | union efx_multicast_hash { | |
786 | u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; | |
787 | efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; | |
788 | }; | |
789 | ||
cd2d5b52 | 790 | struct vfdi_status; |
64eebcfd | 791 | |
8ceee660 BH |
792 | /** |
793 | * struct efx_nic - an Efx NIC | |
794 | * @name: Device name (net device name or bus id before net device registered) | |
795 | * @pci_dev: The PCI device | |
0bcf4a64 BH |
796 | * @node: List node for maintaning primary/secondary function lists |
797 | * @primary: &struct efx_nic instance for the primary function of this | |
798 | * controller. May be the same structure, and may be %NULL if no | |
799 | * primary function is bound. Serialised by rtnl_lock. | |
800 | * @secondary_list: List of &struct efx_nic instances for the secondary PCI | |
801 | * functions of the controller, if this is for the primary function. | |
802 | * Serialised by rtnl_lock. | |
8ceee660 BH |
803 | * @type: Controller type attributes |
804 | * @legacy_irq: IRQ number | |
8d9853d9 BH |
805 | * @workqueue: Workqueue for port reconfigures and the HW monitor. |
806 | * Work items do not hold and must not acquire RTNL. | |
6977dc63 | 807 | * @workqueue_name: Name of workqueue |
8ceee660 | 808 | * @reset_work: Scheduled reset workitem |
8ceee660 BH |
809 | * @membase_phys: Memory BAR value as physical address |
810 | * @membase: Memory BAR value | |
8ceee660 | 811 | * @interrupt_mode: Interrupt mode |
cc180b69 | 812 | * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds |
6fb70fd1 BH |
813 | * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues |
814 | * @irq_rx_moderation: IRQ moderation time for RX event queues | |
62776d03 | 815 | * @msg_enable: Log message enable flags |
f16aeea0 | 816 | * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. |
a7d529ae | 817 | * @reset_pending: Bitmask for pending resets |
8ceee660 BH |
818 | * @tx_queue: TX DMA queues |
819 | * @rx_queue: RX DMA queues | |
820 | * @channel: Channels | |
d8291187 | 821 | * @msi_context: Context for each MSI |
7f967c01 BH |
822 | * @extra_channel_types: Types of extra (non-traffic) channels that |
823 | * should be allocated for this NIC | |
ecc910f5 SH |
824 | * @rxq_entries: Size of receive queues requested by user. |
825 | * @txq_entries: Size of transmit queues requested by user. | |
14bf718f BH |
826 | * @txq_stop_thresh: TX queue fill level at or above which we stop it. |
827 | * @txq_wake_thresh: TX queue fill level at or below which we wake it. | |
28e47c49 BH |
828 | * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches |
829 | * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches | |
830 | * @sram_lim_qw: Qword address limit of SRAM | |
0484e0db | 831 | * @next_buffer_table: First available buffer table id |
28b581ab | 832 | * @n_channels: Number of channels in use |
a4900ac9 BH |
833 | * @n_rx_channels: Number of channels used for RX (= number of RX queues) |
834 | * @n_tx_channels: Number of channels used for TX | |
2ec03014 AR |
835 | * @rx_ip_align: RX DMA address offset to have IP header aligned in |
836 | * in accordance with NET_IP_ALIGN | |
272baeeb | 837 | * @rx_dma_len: Current maximum RX DMA length |
8ceee660 | 838 | * @rx_buffer_order: Order (log2) of number of pages for each RX buffer |
85740cdf BH |
839 | * @rx_buffer_truesize: Amortised allocation size of an RX buffer, |
840 | * for use in sk_buff::truesize | |
43a3739d JC |
841 | * @rx_prefix_size: Size of RX prefix before packet data |
842 | * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data | |
843 | * (valid only if @rx_prefix_size != 0; always negative) | |
3dced740 BH |
844 | * @rx_packet_len_offset: Offset of RX packet length from start of packet data |
845 | * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative) | |
bd9a265d JC |
846 | * @rx_packet_ts_offset: Offset of timestamp from start of packet data |
847 | * (valid only if channel->sync_timestamps_enabled; always negative) | |
78d4189d | 848 | * @rx_hash_key: Toeplitz hash key for RSS |
765c9f46 | 849 | * @rx_indir_table: Indirection table for RSS |
85740cdf | 850 | * @rx_scatter: Scatter mode enabled for receives |
0484e0db BH |
851 | * @int_error_count: Number of internal errors seen recently |
852 | * @int_error_expire: Time at which error count will be expired | |
d8291187 BH |
853 | * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will |
854 | * acknowledge but do nothing else. | |
8ceee660 | 855 | * @irq_status: Interrupt status buffer |
c28884c5 | 856 | * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 |
1646a6f3 | 857 | * @irq_level: IRQ level/index for IRQs not triggered by an event queue |
dd40781e | 858 | * @selftest_work: Work item for asynchronous self-test |
76884835 | 859 | * @mtd_list: List of MTDs attached to the NIC |
25985edc | 860 | * @nic_data: Hardware dependent state |
f3ad5003 | 861 | * @mcdi: Management-Controller-to-Driver Interface state |
8c8661e4 | 862 | * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, |
e4abce85 | 863 | * efx_monitor() and efx_reconfigure_port() |
8ceee660 | 864 | * @port_enabled: Port enabled indicator. |
fdaa9aed SH |
865 | * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and |
866 | * efx_mac_work() with kernel interfaces. Safe to read under any | |
867 | * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must | |
868 | * be held to modify it. | |
8ceee660 BH |
869 | * @port_initialized: Port initialized? |
870 | * @net_dev: Operating system network device. Consider holding the rtnl lock | |
ebfcd0fd | 871 | * @fixed_features: Features which cannot be turned off |
8ceee660 | 872 | * @stats_buffer: DMA buffer for statistics |
8ceee660 | 873 | * @phy_type: PHY type |
8ceee660 BH |
874 | * @phy_op: PHY interface |
875 | * @phy_data: PHY private data (including PHY-specific stats) | |
68e7f45e | 876 | * @mdio: PHY MDIO interface |
8880f4ec | 877 | * @mdio_bus: PHY MDIO bus ID (only used by Siena) |
8c8661e4 | 878 | * @phy_mode: PHY operating mode. Serialised by @mac_lock. |
d3245b28 | 879 | * @link_advertising: Autonegotiation advertising flags |
eb50c0d6 | 880 | * @link_state: Current state of the link |
8ceee660 | 881 | * @n_link_state_changes: Number of times the link has changed state |
964e6135 BH |
882 | * @unicast_filter: Flag for Falcon-arch simple unicast filter. |
883 | * Protected by @mac_lock. | |
884 | * @multicast_hash: Multicast hash table for Falcon-arch. | |
885 | * Protected by @mac_lock. | |
04cc8cac | 886 | * @wanted_fc: Wanted flow control flags |
a606f432 SH |
887 | * @fc_disable: When non-zero flow control is disabled. Typically used to |
888 | * ensure that network back pressure doesn't delay dma queue flushes. | |
889 | * Serialised by the rtnl lock. | |
8be4f3e6 | 890 | * @mac_work: Work item for changing MAC promiscuity and multicast hash |
3273c2e8 BH |
891 | * @loopback_mode: Loopback status |
892 | * @loopback_modes: Supported loopback mode bitmask | |
893 | * @loopback_selftest: Offline self-test private state | |
0d322413 EC |
894 | * @filter_sem: Filter table rw_semaphore, for freeing the table |
895 | * @filter_lock: Filter table lock, for mere content changes | |
6d661cec | 896 | * @filter_state: Architecture-dependent filter table state |
faf8dcc1 JC |
897 | * @rps_expire_channel: Next channel to check for expiry |
898 | * @rps_expire_index: Next index to check for expiry in | |
899 | * @rps_expire_channel's @rps_flow_id | |
3881d8ab | 900 | * @active_queues: Count of RX and TX queues that haven't been flushed and drained. |
9f2cb71c BH |
901 | * @rxq_flush_pending: Count of number of receive queues that need to be flushed. |
902 | * Decremented when the efx_flush_rx_queue() is called. | |
903 | * @rxq_flush_outstanding: Count of number of RX flushes started but not yet | |
904 | * completed (either success or failure). Not used when MCDI is used to | |
905 | * flush receive queues. | |
906 | * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. | |
cd2d5b52 BH |
907 | * @vf_count: Number of VFs intended to be enabled. |
908 | * @vf_init_count: Number of VFs that have been fully initialised. | |
909 | * @vi_scale: log2 number of vnics per VF. | |
7c236c43 | 910 | * @ptp_data: PTP state data |
ef215e64 | 911 | * @vpd_sn: Serial number read from VPD |
ab28c12a BH |
912 | * @monitor_work: Hardware monitor workitem |
913 | * @biu_lock: BIU (bus interface unit) lock | |
1646a6f3 BH |
914 | * @last_irq_cpu: Last CPU to handle a possible test interrupt. This |
915 | * field is used by efx_test_interrupts() to verify that an | |
916 | * interrupt has occurred. | |
cd0ecc9a BH |
917 | * @stats_lock: Statistics update lock. Must be held when calling |
918 | * efx_nic_type::{update,start,stop}_stats. | |
e4d112e4 | 919 | * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb |
8ceee660 | 920 | * |
754c653a | 921 | * This is stored in the private area of the &struct net_device. |
8ceee660 BH |
922 | */ |
923 | struct efx_nic { | |
ab28c12a BH |
924 | /* The following fields should be written very rarely */ |
925 | ||
8ceee660 | 926 | char name[IFNAMSIZ]; |
0bcf4a64 BH |
927 | struct list_head node; |
928 | struct efx_nic *primary; | |
929 | struct list_head secondary_list; | |
8ceee660 | 930 | struct pci_dev *pci_dev; |
6602041b | 931 | unsigned int port_num; |
8ceee660 BH |
932 | const struct efx_nic_type *type; |
933 | int legacy_irq; | |
b28405b0 | 934 | bool eeh_disabled_legacy_irq; |
8ceee660 | 935 | struct workqueue_struct *workqueue; |
6977dc63 | 936 | char workqueue_name[16]; |
8ceee660 | 937 | struct work_struct reset_work; |
086ea356 | 938 | resource_size_t membase_phys; |
8ceee660 | 939 | void __iomem *membase; |
ab28c12a | 940 | |
8ceee660 | 941 | enum efx_int_mode interrupt_mode; |
cc180b69 | 942 | unsigned int timer_quantum_ns; |
6fb70fd1 BH |
943 | bool irq_rx_adaptive; |
944 | unsigned int irq_rx_moderation; | |
62776d03 | 945 | u32 msg_enable; |
8ceee660 | 946 | |
8ceee660 | 947 | enum nic_state state; |
a7d529ae | 948 | unsigned long reset_pending; |
8ceee660 | 949 | |
8313aca3 | 950 | struct efx_channel *channel[EFX_MAX_CHANNELS]; |
d8291187 | 951 | struct efx_msi_context msi_context[EFX_MAX_CHANNELS]; |
7f967c01 BH |
952 | const struct efx_channel_type * |
953 | extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; | |
8ceee660 | 954 | |
ecc910f5 SH |
955 | unsigned rxq_entries; |
956 | unsigned txq_entries; | |
14bf718f BH |
957 | unsigned int txq_stop_thresh; |
958 | unsigned int txq_wake_thresh; | |
959 | ||
28e47c49 BH |
960 | unsigned tx_dc_base; |
961 | unsigned rx_dc_base; | |
962 | unsigned sram_lim_qw; | |
0484e0db | 963 | unsigned next_buffer_table; |
b105798f BH |
964 | |
965 | unsigned int max_channels; | |
b0fbdae1 | 966 | unsigned int max_tx_channels; |
a4900ac9 BH |
967 | unsigned n_channels; |
968 | unsigned n_rx_channels; | |
cd2d5b52 | 969 | unsigned rss_spread; |
97653431 | 970 | unsigned tx_channel_offset; |
a4900ac9 | 971 | unsigned n_tx_channels; |
2ec03014 | 972 | unsigned int rx_ip_align; |
272baeeb | 973 | unsigned int rx_dma_len; |
8ceee660 | 974 | unsigned int rx_buffer_order; |
85740cdf | 975 | unsigned int rx_buffer_truesize; |
1648a23f | 976 | unsigned int rx_page_buf_step; |
2768935a | 977 | unsigned int rx_bufs_per_page; |
1648a23f | 978 | unsigned int rx_pages_per_batch; |
43a3739d JC |
979 | unsigned int rx_prefix_size; |
980 | int rx_packet_hash_offset; | |
3dced740 | 981 | int rx_packet_len_offset; |
bd9a265d | 982 | int rx_packet_ts_offset; |
5d3a6fca | 983 | u8 rx_hash_key[40]; |
765c9f46 | 984 | u32 rx_indir_table[128]; |
85740cdf | 985 | bool rx_scatter; |
8ceee660 | 986 | |
0484e0db BH |
987 | unsigned int_error_count; |
988 | unsigned long int_error_expire; | |
989 | ||
d8291187 | 990 | bool irq_soft_enabled; |
8ceee660 | 991 | struct efx_buffer irq_status; |
c28884c5 | 992 | unsigned irq_zero_count; |
1646a6f3 | 993 | unsigned irq_level; |
dd40781e | 994 | struct delayed_work selftest_work; |
8ceee660 | 995 | |
76884835 BH |
996 | #ifdef CONFIG_SFC_MTD |
997 | struct list_head mtd_list; | |
998 | #endif | |
4a5b504d | 999 | |
8880f4ec | 1000 | void *nic_data; |
f3ad5003 | 1001 | struct efx_mcdi_data *mcdi; |
8ceee660 BH |
1002 | |
1003 | struct mutex mac_lock; | |
766ca0fa | 1004 | struct work_struct mac_work; |
dc8cfa55 | 1005 | bool port_enabled; |
8ceee660 | 1006 | |
74cd60a4 | 1007 | bool mc_bist_for_other_fn; |
dc8cfa55 | 1008 | bool port_initialized; |
8ceee660 | 1009 | struct net_device *net_dev; |
8ceee660 | 1010 | |
ebfcd0fd AR |
1011 | netdev_features_t fixed_features; |
1012 | ||
8ceee660 | 1013 | struct efx_buffer stats_buffer; |
f8f3b5ae JC |
1014 | u64 rx_nodesc_drops_total; |
1015 | u64 rx_nodesc_drops_while_down; | |
1016 | bool rx_nodesc_drops_prev_state; | |
8ceee660 | 1017 | |
c1c4f453 | 1018 | unsigned int phy_type; |
6c8c2513 | 1019 | const struct efx_phy_operations *phy_op; |
8ceee660 | 1020 | void *phy_data; |
68e7f45e | 1021 | struct mdio_if_info mdio; |
8880f4ec | 1022 | unsigned int mdio_bus; |
f8b87c17 | 1023 | enum efx_phy_mode phy_mode; |
8ceee660 | 1024 | |
d3245b28 | 1025 | u32 link_advertising; |
eb50c0d6 | 1026 | struct efx_link_state link_state; |
8ceee660 BH |
1027 | unsigned int n_link_state_changes; |
1028 | ||
964e6135 | 1029 | bool unicast_filter; |
8ceee660 | 1030 | union efx_multicast_hash multicast_hash; |
b5626946 | 1031 | u8 wanted_fc; |
a606f432 | 1032 | unsigned fc_disable; |
8ceee660 BH |
1033 | |
1034 | atomic_t rx_reset; | |
3273c2e8 | 1035 | enum efx_loopback_mode loopback_mode; |
e58f69f4 | 1036 | u64 loopback_modes; |
3273c2e8 BH |
1037 | |
1038 | void *loopback_selftest; | |
64eebcfd | 1039 | |
0d322413 | 1040 | struct rw_semaphore filter_sem; |
6d661cec BH |
1041 | spinlock_t filter_lock; |
1042 | void *filter_state; | |
1043 | #ifdef CONFIG_RFS_ACCEL | |
faf8dcc1 | 1044 | unsigned int rps_expire_channel; |
6d661cec BH |
1045 | unsigned int rps_expire_index; |
1046 | #endif | |
ab28c12a | 1047 | |
3881d8ab | 1048 | atomic_t active_queues; |
9f2cb71c BH |
1049 | atomic_t rxq_flush_pending; |
1050 | atomic_t rxq_flush_outstanding; | |
1051 | wait_queue_head_t flush_wq; | |
1052 | ||
cd2d5b52 | 1053 | #ifdef CONFIG_SFC_SRIOV |
cd2d5b52 BH |
1054 | unsigned vf_count; |
1055 | unsigned vf_init_count; | |
1056 | unsigned vi_scale; | |
cd2d5b52 BH |
1057 | #endif |
1058 | ||
7c236c43 | 1059 | struct efx_ptp_data *ptp_data; |
7c236c43 | 1060 | |
ef215e64 BH |
1061 | char *vpd_sn; |
1062 | ||
ab28c12a BH |
1063 | /* The following fields may be written more often */ |
1064 | ||
1065 | struct delayed_work monitor_work ____cacheline_aligned_in_smp; | |
1066 | spinlock_t biu_lock; | |
1646a6f3 | 1067 | int last_irq_cpu; |
ab28c12a | 1068 | spinlock_t stats_lock; |
e4d112e4 | 1069 | atomic_t n_rx_noskb_drops; |
8ceee660 BH |
1070 | }; |
1071 | ||
55668611 BH |
1072 | static inline int efx_dev_registered(struct efx_nic *efx) |
1073 | { | |
1074 | return efx->net_dev->reg_state == NETREG_REGISTERED; | |
1075 | } | |
1076 | ||
8880f4ec BH |
1077 | static inline unsigned int efx_port_num(struct efx_nic *efx) |
1078 | { | |
6602041b | 1079 | return efx->port_num; |
8880f4ec BH |
1080 | } |
1081 | ||
45a3fd55 BH |
1082 | struct efx_mtd_partition { |
1083 | struct list_head node; | |
1084 | struct mtd_info mtd; | |
1085 | const char *dev_type_name; | |
1086 | const char *type_name; | |
1087 | char name[IFNAMSIZ + 20]; | |
1088 | }; | |
1089 | ||
8ceee660 BH |
1090 | /** |
1091 | * struct efx_nic_type - Efx device type definition | |
02246a7f | 1092 | * @mem_bar: Get the memory BAR |
b105798f | 1093 | * @mem_map_size: Get memory BAR mapped size |
ef2b90ee BH |
1094 | * @probe: Probe the controller |
1095 | * @remove: Free resources allocated by probe() | |
1096 | * @init: Initialise the controller | |
28e47c49 BH |
1097 | * @dimension_resources: Dimension controller resources (buffer table, |
1098 | * and VIs once the available interrupt resources are clear) | |
ef2b90ee BH |
1099 | * @fini: Shut down the controller |
1100 | * @monitor: Periodic function for polling link state and hardware monitor | |
0e2a9c7c BH |
1101 | * @map_reset_reason: Map ethtool reset reason to a reset method |
1102 | * @map_reset_flags: Map ethtool reset flags to a reset method, if possible | |
ef2b90ee BH |
1103 | * @reset: Reset the controller hardware and possibly the PHY. This will |
1104 | * be called while the controller is uninitialised. | |
1105 | * @probe_port: Probe the MAC and PHY | |
1106 | * @remove_port: Free resources allocated by probe_port() | |
40641ed9 | 1107 | * @handle_global_event: Handle a "global" event (may be %NULL) |
e42c3d85 | 1108 | * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues) |
ef2b90ee | 1109 | * @prepare_flush: Prepare the hardware for flushing the DMA queues |
e42c3d85 BH |
1110 | * (for Falcon architecture) |
1111 | * @finish_flush: Clean up after flushing the DMA queues (for Falcon | |
1112 | * architecture) | |
e283546c EC |
1113 | * @prepare_flr: Prepare for an FLR |
1114 | * @finish_flr: Clean up after an FLR | |
cd0ecc9a BH |
1115 | * @describe_stats: Describe statistics for ethtool |
1116 | * @update_stats: Update statistics not provided by event handling. | |
1117 | * Either argument may be %NULL. | |
ef2b90ee | 1118 | * @start_stats: Start the regular fetching of statistics |
f8f3b5ae | 1119 | * @pull_stats: Pull stats from the NIC and wait until they arrive. |
ef2b90ee | 1120 | * @stop_stats: Stop the regular fetching of statistics |
06629f07 | 1121 | * @set_id_led: Set state of identifying LED or revert to automatic function |
ef2b90ee | 1122 | * @push_irq_moderation: Apply interrupt moderation value |
d3245b28 | 1123 | * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY |
9dd3a13b | 1124 | * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL) |
30b81cda BH |
1125 | * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings |
1126 | * to the hardware. Serialised by the mac_lock. | |
710b208d | 1127 | * @check_mac_fault: Check MAC fault state. True if fault present. |
89c758fa BH |
1128 | * @get_wol: Get WoL configuration from driver state |
1129 | * @set_wol: Push WoL configuration to the NIC | |
1130 | * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) | |
86094f7f | 1131 | * @test_chip: Test registers. May use efx_farch_test_registers(), and is |
d4f2cecc | 1132 | * expected to reset the NIC. |
0aa3fbaa | 1133 | * @test_nvram: Test validity of NVRAM contents |
f3ad5003 BH |
1134 | * @mcdi_request: Send an MCDI request with the given header and SDU. |
1135 | * The SDU length may be any value from 0 up to the protocol- | |
1136 | * defined maximum, but its buffer will be padded to a multiple | |
1137 | * of 4 bytes. | |
1138 | * @mcdi_poll_response: Test whether an MCDI response is available. | |
1139 | * @mcdi_read_response: Read the MCDI response PDU. The offset will | |
1140 | * be a multiple of 4. The length may not be, but the buffer | |
1141 | * will be padded so it is safe to round up. | |
1142 | * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so, | |
1143 | * return an appropriate error code for aborting any current | |
1144 | * request; otherwise return 0. | |
86094f7f BH |
1145 | * @irq_enable_master: Enable IRQs on the NIC. Each event queue must |
1146 | * be separately enabled after this. | |
1147 | * @irq_test_generate: Generate a test IRQ | |
1148 | * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event | |
1149 | * queue must be separately disabled before this. | |
1150 | * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is | |
1151 | * a pointer to the &struct efx_msi_context for the channel. | |
1152 | * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument | |
1153 | * is a pointer to the &struct efx_nic. | |
1154 | * @tx_probe: Allocate resources for TX queue | |
1155 | * @tx_init: Initialise TX queue on the NIC | |
1156 | * @tx_remove: Free resources for TX queue | |
1157 | * @tx_write: Write TX descriptors and doorbell | |
d43050c0 | 1158 | * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC |
86094f7f BH |
1159 | * @rx_probe: Allocate resources for RX queue |
1160 | * @rx_init: Initialise RX queue on the NIC | |
1161 | * @rx_remove: Free resources for RX queue | |
1162 | * @rx_write: Write RX descriptors and doorbell | |
1163 | * @rx_defer_refill: Generate a refill reminder event | |
1164 | * @ev_probe: Allocate resources for event queue | |
1165 | * @ev_init: Initialise event queue on the NIC | |
1166 | * @ev_fini: Deinitialise event queue on the NIC | |
1167 | * @ev_remove: Free resources for event queue | |
1168 | * @ev_process: Process events for a queue, up to the given NAPI quota | |
1169 | * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ | |
1170 | * @ev_test_generate: Generate a test event | |
add72477 BH |
1171 | * @filter_table_probe: Probe filter capabilities and set up filter software state |
1172 | * @filter_table_restore: Restore filters removed from hardware | |
1173 | * @filter_table_remove: Remove filters from hardware and tear down software state | |
1174 | * @filter_update_rx_scatter: Update filters after change to rx scatter setting | |
1175 | * @filter_insert: add or replace a filter | |
1176 | * @filter_remove_safe: remove a filter by ID, carefully | |
1177 | * @filter_get_safe: retrieve a filter by ID, carefully | |
fbd79120 BH |
1178 | * @filter_clear_rx: Remove all RX filters whose priority is less than or |
1179 | * equal to the given priority and is not %EFX_FILTER_PRI_AUTO | |
add72477 BH |
1180 | * @filter_count_rx_used: Get the number of filters in use at a given priority |
1181 | * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1 | |
1182 | * @filter_get_rx_ids: Get list of RX filters at a given priority | |
1183 | * @filter_rfs_insert: Add or replace a filter for RFS. This must be | |
1184 | * atomic. The hardware change may be asynchronous but should | |
1185 | * not be delayed for long. It may fail if this can't be done | |
1186 | * atomically. | |
1187 | * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS. | |
1188 | * This must check whether the specified table entry is used by RFS | |
1189 | * and that rps_may_expire_flow() returns true for it. | |
45a3fd55 BH |
1190 | * @mtd_probe: Probe and add MTD partitions associated with this net device, |
1191 | * using efx_mtd_add() | |
1192 | * @mtd_rename: Set an MTD partition name using the net device name | |
1193 | * @mtd_read: Read from an MTD partition | |
1194 | * @mtd_erase: Erase part of an MTD partition | |
1195 | * @mtd_write: Write to an MTD partition | |
1196 | * @mtd_sync: Wait for write-back to complete on MTD partition. This | |
1197 | * also notifies the driver that a writer has finished using this | |
1198 | * partition. | |
9ec06595 | 1199 | * @ptp_write_host_time: Send host time to MC as part of sync protocol |
bd9a265d JC |
1200 | * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX |
1201 | * timestamping, possibly only temporarily for the purposes of a reset. | |
9ec06595 DP |
1202 | * @ptp_set_ts_config: Set hardware timestamp configuration. The flags |
1203 | * and tx_type will already have been validated but this operation | |
1204 | * must validate and update rx_filter. | |
910c8789 | 1205 | * @set_mac_address: Set the MAC address of the device |
daeda630 | 1206 | * @revision: Hardware architecture revision |
8ceee660 BH |
1207 | * @txd_ptr_tbl_base: TX descriptor ring base address |
1208 | * @rxd_ptr_tbl_base: RX descriptor ring base address | |
1209 | * @buf_tbl_base: Buffer table base address | |
1210 | * @evq_ptr_tbl_base: Event queue pointer table base address | |
1211 | * @evq_rptr_tbl_base: Event queue read-pointer table base address | |
8ceee660 | 1212 | * @max_dma_mask: Maximum possible DMA mask |
43a3739d JC |
1213 | * @rx_prefix_size: Size of RX prefix before packet data |
1214 | * @rx_hash_offset: Offset of RX flow hash within prefix | |
bd9a265d | 1215 | * @rx_ts_offset: Offset of timestamp within prefix |
85740cdf | 1216 | * @rx_buffer_padding: Size of padding at end of RX packet |
e8c68c0a JC |
1217 | * @can_rx_scatter: NIC is able to scatter packets to multiple buffers |
1218 | * @always_rx_scatter: NIC will always scatter packets to multiple buffers | |
8ceee660 BH |
1219 | * @max_interrupt_mode: Highest capability interrupt mode supported |
1220 | * from &enum efx_init_mode. | |
cc180b69 | 1221 | * @timer_period_max: Maximum period of interrupt timer (in ticks) |
c383b537 BH |
1222 | * @offload_features: net_device feature flags for protocol offload |
1223 | * features implemented in hardware | |
df2cd8af | 1224 | * @mcdi_max_ver: Maximum MCDI version supported |
9ec06595 | 1225 | * @hwtstamp_filters: Mask of hardware timestamp filter types supported |
8ceee660 BH |
1226 | */ |
1227 | struct efx_nic_type { | |
6f7f8aa6 | 1228 | bool is_vf; |
02246a7f | 1229 | unsigned int mem_bar; |
b105798f | 1230 | unsigned int (*mem_map_size)(struct efx_nic *efx); |
ef2b90ee BH |
1231 | int (*probe)(struct efx_nic *efx); |
1232 | void (*remove)(struct efx_nic *efx); | |
1233 | int (*init)(struct efx_nic *efx); | |
c15eed22 | 1234 | int (*dimension_resources)(struct efx_nic *efx); |
ef2b90ee BH |
1235 | void (*fini)(struct efx_nic *efx); |
1236 | void (*monitor)(struct efx_nic *efx); | |
0e2a9c7c BH |
1237 | enum reset_type (*map_reset_reason)(enum reset_type reason); |
1238 | int (*map_reset_flags)(u32 *flags); | |
ef2b90ee BH |
1239 | int (*reset)(struct efx_nic *efx, enum reset_type method); |
1240 | int (*probe_port)(struct efx_nic *efx); | |
1241 | void (*remove_port)(struct efx_nic *efx); | |
40641ed9 | 1242 | bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); |
e42c3d85 | 1243 | int (*fini_dmaq)(struct efx_nic *efx); |
ef2b90ee | 1244 | void (*prepare_flush)(struct efx_nic *efx); |
d5e8cc6c | 1245 | void (*finish_flush)(struct efx_nic *efx); |
e283546c EC |
1246 | void (*prepare_flr)(struct efx_nic *efx); |
1247 | void (*finish_flr)(struct efx_nic *efx); | |
cd0ecc9a BH |
1248 | size_t (*describe_stats)(struct efx_nic *efx, u8 *names); |
1249 | size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats, | |
1250 | struct rtnl_link_stats64 *core_stats); | |
ef2b90ee | 1251 | void (*start_stats)(struct efx_nic *efx); |
f8f3b5ae | 1252 | void (*pull_stats)(struct efx_nic *efx); |
ef2b90ee | 1253 | void (*stop_stats)(struct efx_nic *efx); |
06629f07 | 1254 | void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); |
ef2b90ee | 1255 | void (*push_irq_moderation)(struct efx_channel *channel); |
d3245b28 | 1256 | int (*reconfigure_port)(struct efx_nic *efx); |
9dd3a13b | 1257 | void (*prepare_enable_fc_tx)(struct efx_nic *efx); |
710b208d BH |
1258 | int (*reconfigure_mac)(struct efx_nic *efx); |
1259 | bool (*check_mac_fault)(struct efx_nic *efx); | |
89c758fa BH |
1260 | void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); |
1261 | int (*set_wol)(struct efx_nic *efx, u32 type); | |
1262 | void (*resume_wol)(struct efx_nic *efx); | |
d4f2cecc | 1263 | int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); |
0aa3fbaa | 1264 | int (*test_nvram)(struct efx_nic *efx); |
f3ad5003 BH |
1265 | void (*mcdi_request)(struct efx_nic *efx, |
1266 | const efx_dword_t *hdr, size_t hdr_len, | |
1267 | const efx_dword_t *sdu, size_t sdu_len); | |
1268 | bool (*mcdi_poll_response)(struct efx_nic *efx); | |
1269 | void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu, | |
1270 | size_t pdu_offset, size_t pdu_len); | |
1271 | int (*mcdi_poll_reboot)(struct efx_nic *efx); | |
c577e59e | 1272 | void (*mcdi_reboot_detected)(struct efx_nic *efx); |
86094f7f BH |
1273 | void (*irq_enable_master)(struct efx_nic *efx); |
1274 | void (*irq_test_generate)(struct efx_nic *efx); | |
1275 | void (*irq_disable_non_ev)(struct efx_nic *efx); | |
1276 | irqreturn_t (*irq_handle_msi)(int irq, void *dev_id); | |
1277 | irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id); | |
1278 | int (*tx_probe)(struct efx_tx_queue *tx_queue); | |
1279 | void (*tx_init)(struct efx_tx_queue *tx_queue); | |
1280 | void (*tx_remove)(struct efx_tx_queue *tx_queue); | |
1281 | void (*tx_write)(struct efx_tx_queue *tx_queue); | |
267c0157 JC |
1282 | int (*rx_push_rss_config)(struct efx_nic *efx, bool user, |
1283 | const u32 *rx_indir_table); | |
86094f7f BH |
1284 | int (*rx_probe)(struct efx_rx_queue *rx_queue); |
1285 | void (*rx_init)(struct efx_rx_queue *rx_queue); | |
1286 | void (*rx_remove)(struct efx_rx_queue *rx_queue); | |
1287 | void (*rx_write)(struct efx_rx_queue *rx_queue); | |
1288 | void (*rx_defer_refill)(struct efx_rx_queue *rx_queue); | |
1289 | int (*ev_probe)(struct efx_channel *channel); | |
261e4d96 | 1290 | int (*ev_init)(struct efx_channel *channel); |
86094f7f BH |
1291 | void (*ev_fini)(struct efx_channel *channel); |
1292 | void (*ev_remove)(struct efx_channel *channel); | |
1293 | int (*ev_process)(struct efx_channel *channel, int quota); | |
1294 | void (*ev_read_ack)(struct efx_channel *channel); | |
1295 | void (*ev_test_generate)(struct efx_channel *channel); | |
add72477 BH |
1296 | int (*filter_table_probe)(struct efx_nic *efx); |
1297 | void (*filter_table_restore)(struct efx_nic *efx); | |
1298 | void (*filter_table_remove)(struct efx_nic *efx); | |
1299 | void (*filter_update_rx_scatter)(struct efx_nic *efx); | |
1300 | s32 (*filter_insert)(struct efx_nic *efx, | |
1301 | struct efx_filter_spec *spec, bool replace); | |
1302 | int (*filter_remove_safe)(struct efx_nic *efx, | |
1303 | enum efx_filter_priority priority, | |
1304 | u32 filter_id); | |
1305 | int (*filter_get_safe)(struct efx_nic *efx, | |
1306 | enum efx_filter_priority priority, | |
1307 | u32 filter_id, struct efx_filter_spec *); | |
fbd79120 BH |
1308 | int (*filter_clear_rx)(struct efx_nic *efx, |
1309 | enum efx_filter_priority priority); | |
add72477 BH |
1310 | u32 (*filter_count_rx_used)(struct efx_nic *efx, |
1311 | enum efx_filter_priority priority); | |
1312 | u32 (*filter_get_rx_id_limit)(struct efx_nic *efx); | |
1313 | s32 (*filter_get_rx_ids)(struct efx_nic *efx, | |
1314 | enum efx_filter_priority priority, | |
1315 | u32 *buf, u32 size); | |
1316 | #ifdef CONFIG_RFS_ACCEL | |
1317 | s32 (*filter_rfs_insert)(struct efx_nic *efx, | |
1318 | struct efx_filter_spec *spec); | |
1319 | bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id, | |
1320 | unsigned int index); | |
1321 | #endif | |
45a3fd55 BH |
1322 | #ifdef CONFIG_SFC_MTD |
1323 | int (*mtd_probe)(struct efx_nic *efx); | |
1324 | void (*mtd_rename)(struct efx_mtd_partition *part); | |
1325 | int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len, | |
1326 | size_t *retlen, u8 *buffer); | |
1327 | int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len); | |
1328 | int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len, | |
1329 | size_t *retlen, const u8 *buffer); | |
1330 | int (*mtd_sync)(struct mtd_info *mtd); | |
1331 | #endif | |
977a5d5d | 1332 | void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time); |
bd9a265d | 1333 | int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp); |
9ec06595 DP |
1334 | int (*ptp_set_ts_config)(struct efx_nic *efx, |
1335 | struct hwtstamp_config *init); | |
834e23dd | 1336 | int (*sriov_configure)(struct efx_nic *efx, int num_vfs); |
4a53ea8a AR |
1337 | int (*vlan_rx_add_vid)(struct efx_nic *efx, __be16 proto, u16 vid); |
1338 | int (*vlan_rx_kill_vid)(struct efx_nic *efx, __be16 proto, u16 vid); | |
d98a4ffe SS |
1339 | int (*sriov_init)(struct efx_nic *efx); |
1340 | void (*sriov_fini)(struct efx_nic *efx); | |
d98a4ffe SS |
1341 | bool (*sriov_wanted)(struct efx_nic *efx); |
1342 | void (*sriov_reset)(struct efx_nic *efx); | |
7fa8d547 SS |
1343 | void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i); |
1344 | int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, u8 *mac); | |
1345 | int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan, | |
1346 | u8 qos); | |
1347 | int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i, | |
1348 | bool spoofchk); | |
1349 | int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i, | |
1350 | struct ifla_vf_info *ivi); | |
4392dc69 EC |
1351 | int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i, |
1352 | int link_state); | |
1d051e00 SS |
1353 | int (*sriov_get_phys_port_id)(struct efx_nic *efx, |
1354 | struct netdev_phys_item_id *ppid); | |
6d8aaaf6 DP |
1355 | int (*vswitching_probe)(struct efx_nic *efx); |
1356 | int (*vswitching_restore)(struct efx_nic *efx); | |
1357 | void (*vswitching_remove)(struct efx_nic *efx); | |
0d5e0fbb | 1358 | int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr); |
910c8789 | 1359 | int (*set_mac_address)(struct efx_nic *efx); |
b895d73e | 1360 | |
daeda630 | 1361 | int revision; |
8ceee660 BH |
1362 | unsigned int txd_ptr_tbl_base; |
1363 | unsigned int rxd_ptr_tbl_base; | |
1364 | unsigned int buf_tbl_base; | |
1365 | unsigned int evq_ptr_tbl_base; | |
1366 | unsigned int evq_rptr_tbl_base; | |
9bbd7d9a | 1367 | u64 max_dma_mask; |
43a3739d JC |
1368 | unsigned int rx_prefix_size; |
1369 | unsigned int rx_hash_offset; | |
bd9a265d | 1370 | unsigned int rx_ts_offset; |
8ceee660 | 1371 | unsigned int rx_buffer_padding; |
85740cdf | 1372 | bool can_rx_scatter; |
e8c68c0a | 1373 | bool always_rx_scatter; |
8ceee660 | 1374 | unsigned int max_interrupt_mode; |
cc180b69 | 1375 | unsigned int timer_period_max; |
c8f44aff | 1376 | netdev_features_t offload_features; |
df2cd8af | 1377 | int mcdi_max_ver; |
add72477 | 1378 | unsigned int max_rx_ip_filters; |
9ec06595 | 1379 | u32 hwtstamp_filters; |
8ceee660 BH |
1380 | }; |
1381 | ||
1382 | /************************************************************************** | |
1383 | * | |
1384 | * Prototypes and inline functions | |
1385 | * | |
1386 | *************************************************************************/ | |
1387 | ||
f7d12cdc BH |
1388 | static inline struct efx_channel * |
1389 | efx_get_channel(struct efx_nic *efx, unsigned index) | |
1390 | { | |
1391 | EFX_BUG_ON_PARANOID(index >= efx->n_channels); | |
8313aca3 | 1392 | return efx->channel[index]; |
f7d12cdc BH |
1393 | } |
1394 | ||
8ceee660 BH |
1395 | /* Iterate over all used channels */ |
1396 | #define efx_for_each_channel(_channel, _efx) \ | |
8313aca3 BH |
1397 | for (_channel = (_efx)->channel[0]; \ |
1398 | _channel; \ | |
1399 | _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ | |
1400 | (_efx)->channel[_channel->channel + 1] : NULL) | |
8ceee660 | 1401 | |
7f967c01 BH |
1402 | /* Iterate over all used channels in reverse */ |
1403 | #define efx_for_each_channel_rev(_channel, _efx) \ | |
1404 | for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ | |
1405 | _channel; \ | |
1406 | _channel = _channel->channel ? \ | |
1407 | (_efx)->channel[_channel->channel - 1] : NULL) | |
1408 | ||
97653431 BH |
1409 | static inline struct efx_tx_queue * |
1410 | efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) | |
1411 | { | |
1412 | EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || | |
1413 | type >= EFX_TXQ_TYPES); | |
1414 | return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; | |
1415 | } | |
f7d12cdc | 1416 | |
525da907 BH |
1417 | static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) |
1418 | { | |
1419 | return channel->channel - channel->efx->tx_channel_offset < | |
1420 | channel->efx->n_tx_channels; | |
1421 | } | |
1422 | ||
f7d12cdc BH |
1423 | static inline struct efx_tx_queue * |
1424 | efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) | |
1425 | { | |
525da907 BH |
1426 | EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || |
1427 | type >= EFX_TXQ_TYPES); | |
1428 | return &channel->tx_queue[type]; | |
f7d12cdc | 1429 | } |
8ceee660 | 1430 | |
94b274bf BH |
1431 | static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) |
1432 | { | |
1433 | return !(tx_queue->efx->net_dev->num_tc < 2 && | |
1434 | tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); | |
1435 | } | |
1436 | ||
8ceee660 BH |
1437 | /* Iterate over all TX queues belonging to a channel */ |
1438 | #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ | |
525da907 BH |
1439 | if (!efx_channel_has_tx_queues(_channel)) \ |
1440 | ; \ | |
1441 | else \ | |
1442 | for (_tx_queue = (_channel)->tx_queue; \ | |
94b274bf BH |
1443 | _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ |
1444 | efx_tx_queue_used(_tx_queue); \ | |
525da907 | 1445 | _tx_queue++) |
8ceee660 | 1446 | |
94b274bf BH |
1447 | /* Iterate over all possible TX queues belonging to a channel */ |
1448 | #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ | |
73e0026f BH |
1449 | if (!efx_channel_has_tx_queues(_channel)) \ |
1450 | ; \ | |
1451 | else \ | |
1452 | for (_tx_queue = (_channel)->tx_queue; \ | |
1453 | _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ | |
1454 | _tx_queue++) | |
94b274bf | 1455 | |
525da907 BH |
1456 | static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) |
1457 | { | |
79d68b37 | 1458 | return channel->rx_queue.core_index >= 0; |
525da907 BH |
1459 | } |
1460 | ||
f7d12cdc BH |
1461 | static inline struct efx_rx_queue * |
1462 | efx_channel_get_rx_queue(struct efx_channel *channel) | |
1463 | { | |
525da907 BH |
1464 | EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); |
1465 | return &channel->rx_queue; | |
f7d12cdc BH |
1466 | } |
1467 | ||
8ceee660 BH |
1468 | /* Iterate over all RX queues belonging to a channel */ |
1469 | #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ | |
525da907 BH |
1470 | if (!efx_channel_has_rx_queue(_channel)) \ |
1471 | ; \ | |
1472 | else \ | |
1473 | for (_rx_queue = &(_channel)->rx_queue; \ | |
1474 | _rx_queue; \ | |
1475 | _rx_queue = NULL) | |
8ceee660 | 1476 | |
ba1e8a35 BH |
1477 | static inline struct efx_channel * |
1478 | efx_rx_queue_channel(struct efx_rx_queue *rx_queue) | |
1479 | { | |
8313aca3 | 1480 | return container_of(rx_queue, struct efx_channel, rx_queue); |
ba1e8a35 BH |
1481 | } |
1482 | ||
1483 | static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) | |
1484 | { | |
8313aca3 | 1485 | return efx_rx_queue_channel(rx_queue)->channel; |
ba1e8a35 BH |
1486 | } |
1487 | ||
8ceee660 BH |
1488 | /* Returns a pointer to the specified receive buffer in the RX |
1489 | * descriptor queue. | |
1490 | */ | |
1491 | static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, | |
1492 | unsigned int index) | |
1493 | { | |
807540ba | 1494 | return &rx_queue->buffer[index]; |
8ceee660 BH |
1495 | } |
1496 | ||
8ceee660 BH |
1497 | /** |
1498 | * EFX_MAX_FRAME_LEN - calculate maximum frame length | |
1499 | * | |
1500 | * This calculates the maximum frame length that will be used for a | |
1501 | * given MTU. The frame length will be equal to the MTU plus a | |
1502 | * constant amount of header space and padding. This is the quantity | |
1503 | * that the net driver will program into the MAC as the maximum frame | |
1504 | * length. | |
1505 | * | |
754c653a | 1506 | * The 10G MAC requires 8-byte alignment on the frame |
8ceee660 | 1507 | * length, so we round up to the nearest 8. |
cc11763b BH |
1508 | * |
1509 | * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an | |
1510 | * XGMII cycle). If the frame length reaches the maximum value in the | |
1511 | * same cycle, the XMAC can miss the IPG altogether. We work around | |
1512 | * this by adding a further 16 bytes. | |
8ceee660 | 1513 | */ |
6f24e5d5 | 1514 | #define EFX_FRAME_PAD 16 |
8ceee660 | 1515 | #define EFX_MAX_FRAME_LEN(mtu) \ |
6f24e5d5 | 1516 | (ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8)) |
8ceee660 | 1517 | |
7c236c43 SH |
1518 | static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb) |
1519 | { | |
1520 | return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; | |
1521 | } | |
1522 | static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb) | |
1523 | { | |
1524 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
1525 | } | |
8ceee660 | 1526 | |
e4478ad1 MH |
1527 | /* Get all supported features. |
1528 | * If a feature is not fixed, it is present in hw_features. | |
1529 | * If a feature is fixed, it does not present in hw_features, but | |
1530 | * always in features. | |
1531 | */ | |
1532 | static inline netdev_features_t efx_supported_features(const struct efx_nic *efx) | |
1533 | { | |
1534 | const struct net_device *net_dev = efx->net_dev; | |
1535 | ||
1536 | return net_dev->features | net_dev->hw_features; | |
1537 | } | |
1538 | ||
8ceee660 | 1539 | #endif /* EFX_NET_DRIVER_H */ |