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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | /* Common definitions for all Efx net driver code */ | |
12 | ||
13 | #ifndef EFX_NET_DRIVER_H | |
14 | #define EFX_NET_DRIVER_H | |
15 | ||
8ceee660 BH |
16 | #include <linux/netdevice.h> |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/ethtool.h> | |
19 | #include <linux/if_vlan.h> | |
90d683af | 20 | #include <linux/timer.h> |
68e7f45e | 21 | #include <linux/mdio.h> |
8ceee660 BH |
22 | #include <linux/list.h> |
23 | #include <linux/pci.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/highmem.h> | |
26 | #include <linux/workqueue.h> | |
cd2d5b52 | 27 | #include <linux/mutex.h> |
10ed61c4 | 28 | #include <linux/vmalloc.h> |
37b5a603 | 29 | #include <linux/i2c.h> |
8ceee660 BH |
30 | |
31 | #include "enum.h" | |
32 | #include "bitfield.h" | |
8ceee660 | 33 | |
8ceee660 BH |
34 | /************************************************************************** |
35 | * | |
36 | * Build definitions | |
37 | * | |
38 | **************************************************************************/ | |
c5d5f5fd | 39 | |
6d84b986 | 40 | #define EFX_DRIVER_VERSION "3.1" |
8ceee660 | 41 | |
5f3f9d6c | 42 | #ifdef DEBUG |
8ceee660 BH |
43 | #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) |
44 | #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) | |
45 | #else | |
46 | #define EFX_BUG_ON_PARANOID(x) do {} while (0) | |
47 | #define EFX_WARN_ON_PARANOID(x) do {} while (0) | |
48 | #endif | |
49 | ||
8ceee660 BH |
50 | /************************************************************************** |
51 | * | |
52 | * Efx data structures | |
53 | * | |
54 | **************************************************************************/ | |
55 | ||
a16e5b24 | 56 | #define EFX_MAX_CHANNELS 32U |
8ceee660 | 57 | #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS |
cd2d5b52 BH |
58 | #define EFX_EXTRA_CHANNEL_IOV 0 |
59 | #define EFX_MAX_EXTRA_CHANNELS 1U | |
8ceee660 | 60 | |
a4900ac9 BH |
61 | /* Checksum generation is a per-queue option in hardware, so each |
62 | * queue visible to the networking core is backed by two hardware TX | |
63 | * queues. */ | |
94b274bf BH |
64 | #define EFX_MAX_TX_TC 2 |
65 | #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) | |
66 | #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ | |
67 | #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ | |
68 | #define EFX_TXQ_TYPES 4 | |
69 | #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) | |
60ac1065 | 70 | |
d4f2cecc BH |
71 | struct efx_self_tests; |
72 | ||
8ceee660 BH |
73 | /** |
74 | * struct efx_special_buffer - An Efx special buffer | |
75 | * @addr: CPU base address of the buffer | |
76 | * @dma_addr: DMA base address of the buffer | |
77 | * @len: Buffer length, in bytes | |
78 | * @index: Buffer index within controller;s buffer table | |
79 | * @entries: Number of buffer table entries | |
80 | * | |
81 | * Special buffers are used for the event queues and the TX and RX | |
82 | * descriptor queues for each channel. They are *not* used for the | |
83 | * actual transmit and receive buffers. | |
8ceee660 BH |
84 | */ |
85 | struct efx_special_buffer { | |
86 | void *addr; | |
87 | dma_addr_t dma_addr; | |
88 | unsigned int len; | |
5bbe2f4f BH |
89 | unsigned int index; |
90 | unsigned int entries; | |
8ceee660 BH |
91 | }; |
92 | ||
93 | /** | |
94 | * struct efx_tx_buffer - An Efx TX buffer | |
95 | * @skb: The associated socket buffer. | |
96 | * Set only on the final fragment of a packet; %NULL for all other | |
97 | * fragments. When this fragment completes, then we can free this | |
98 | * skb. | |
b9b39b62 BH |
99 | * @tsoh: The associated TSO header structure, or %NULL if this |
100 | * buffer is not a TSO header. | |
8ceee660 BH |
101 | * @dma_addr: DMA address of the fragment. |
102 | * @len: Length of this fragment. | |
103 | * This field is zero when the queue slot is empty. | |
104 | * @continuation: True if this fragment is not the end of a packet. | |
0e33d870 | 105 | * @unmap_single: True if dma_unmap_single should be used. |
8ceee660 BH |
106 | * @unmap_len: Length of this fragment to unmap |
107 | */ | |
108 | struct efx_tx_buffer { | |
109 | const struct sk_buff *skb; | |
b9b39b62 | 110 | struct efx_tso_header *tsoh; |
8ceee660 BH |
111 | dma_addr_t dma_addr; |
112 | unsigned short len; | |
dc8cfa55 BH |
113 | bool continuation; |
114 | bool unmap_single; | |
8ceee660 BH |
115 | unsigned short unmap_len; |
116 | }; | |
117 | ||
118 | /** | |
119 | * struct efx_tx_queue - An Efx TX queue | |
120 | * | |
121 | * This is a ring buffer of TX fragments. | |
122 | * Since the TX completion path always executes on the same | |
123 | * CPU and the xmit path can operate on different CPUs, | |
124 | * performance is increased by ensuring that the completion | |
125 | * path and the xmit path operate on different cache lines. | |
126 | * This is particularly important if the xmit path is always | |
127 | * executing on one CPU which is different from the completion | |
128 | * path. There is also a cache line for members which are | |
129 | * read but not written on the fast path. | |
130 | * | |
131 | * @efx: The associated Efx NIC | |
132 | * @queue: DMA queue number | |
8ceee660 | 133 | * @channel: The associated channel |
c04bfc6b | 134 | * @core_txq: The networking core TX queue structure |
8ceee660 BH |
135 | * @buffer: The software buffer ring |
136 | * @txd: The hardware descriptor ring | |
ecc910f5 | 137 | * @ptr_mask: The size of the ring minus 1. |
94b274bf | 138 | * @initialised: Has hardware queue been initialised? |
8ceee660 BH |
139 | * @read_count: Current read pointer. |
140 | * This is the number of buffers that have been removed from both rings. | |
cd38557d BH |
141 | * @old_write_count: The value of @write_count when last checked. |
142 | * This is here for performance reasons. The xmit path will | |
143 | * only get the up-to-date value of @write_count if this | |
144 | * variable indicates that the queue is empty. This is to | |
145 | * avoid cache-line ping-pong between the xmit path and the | |
146 | * completion path. | |
8ceee660 BH |
147 | * @insert_count: Current insert pointer |
148 | * This is the number of buffers that have been added to the | |
149 | * software ring. | |
150 | * @write_count: Current write pointer | |
151 | * This is the number of buffers that have been added to the | |
152 | * hardware ring. | |
153 | * @old_read_count: The value of read_count when last checked. | |
154 | * This is here for performance reasons. The xmit path will | |
155 | * only get the up-to-date value of read_count if this | |
156 | * variable indicates that the queue is full. This is to | |
157 | * avoid cache-line ping-pong between the xmit path and the | |
158 | * completion path. | |
b9b39b62 BH |
159 | * @tso_headers_free: A list of TSO headers allocated for this TX queue |
160 | * that are not in use, and so available for new TSO sends. The list | |
161 | * is protected by the TX queue lock. | |
162 | * @tso_bursts: Number of times TSO xmit invoked by kernel | |
163 | * @tso_long_headers: Number of packets with headers too long for standard | |
164 | * blocks | |
165 | * @tso_packets: Number of packets via the TSO xmit path | |
cd38557d BH |
166 | * @pushes: Number of times the TX push feature has been used |
167 | * @empty_read_count: If the completion path has seen the queue as empty | |
168 | * and the transmission path has not yet checked this, the value of | |
169 | * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. | |
8ceee660 BH |
170 | */ |
171 | struct efx_tx_queue { | |
172 | /* Members which don't change on the fast path */ | |
173 | struct efx_nic *efx ____cacheline_aligned_in_smp; | |
a4900ac9 | 174 | unsigned queue; |
8ceee660 | 175 | struct efx_channel *channel; |
c04bfc6b | 176 | struct netdev_queue *core_txq; |
8ceee660 BH |
177 | struct efx_tx_buffer *buffer; |
178 | struct efx_special_buffer txd; | |
ecc910f5 | 179 | unsigned int ptr_mask; |
94b274bf | 180 | bool initialised; |
8ceee660 BH |
181 | |
182 | /* Members used mainly on the completion path */ | |
183 | unsigned int read_count ____cacheline_aligned_in_smp; | |
cd38557d | 184 | unsigned int old_write_count; |
8ceee660 BH |
185 | |
186 | /* Members used only on the xmit path */ | |
187 | unsigned int insert_count ____cacheline_aligned_in_smp; | |
188 | unsigned int write_count; | |
189 | unsigned int old_read_count; | |
b9b39b62 BH |
190 | struct efx_tso_header *tso_headers_free; |
191 | unsigned int tso_bursts; | |
192 | unsigned int tso_long_headers; | |
193 | unsigned int tso_packets; | |
cd38557d BH |
194 | unsigned int pushes; |
195 | ||
196 | /* Members shared between paths and sometimes updated */ | |
197 | unsigned int empty_read_count ____cacheline_aligned_in_smp; | |
198 | #define EFX_EMPTY_COUNT_VALID 0x80000000 | |
8ceee660 BH |
199 | }; |
200 | ||
201 | /** | |
202 | * struct efx_rx_buffer - An Efx RX data buffer | |
203 | * @dma_addr: DMA base address of the buffer | |
db339569 BH |
204 | * @skb: The associated socket buffer. Valid iff !(@flags & %EFX_RX_BUF_PAGE). |
205 | * Will be %NULL if the buffer slot is currently free. | |
206 | * @page: The associated page buffer. Valif iff @flags & %EFX_RX_BUF_PAGE. | |
207 | * Will be %NULL if the buffer slot is currently free. | |
8ceee660 | 208 | * @len: Buffer length, in bytes. |
db339569 | 209 | * @flags: Flags for buffer and packet state. |
8ceee660 BH |
210 | */ |
211 | struct efx_rx_buffer { | |
212 | dma_addr_t dma_addr; | |
8ba5366a SH |
213 | union { |
214 | struct sk_buff *skb; | |
215 | struct page *page; | |
216 | } u; | |
8ceee660 | 217 | unsigned int len; |
db339569 | 218 | u16 flags; |
8ceee660 | 219 | }; |
db339569 BH |
220 | #define EFX_RX_BUF_PAGE 0x0001 |
221 | #define EFX_RX_PKT_CSUMMED 0x0002 | |
222 | #define EFX_RX_PKT_DISCARD 0x0004 | |
8ceee660 | 223 | |
62b330ba SH |
224 | /** |
225 | * struct efx_rx_page_state - Page-based rx buffer state | |
226 | * | |
227 | * Inserted at the start of every page allocated for receive buffers. | |
228 | * Used to facilitate sharing dma mappings between recycled rx buffers | |
229 | * and those passed up to the kernel. | |
230 | * | |
231 | * @refcnt: Number of struct efx_rx_buffer's referencing this page. | |
232 | * When refcnt falls to zero, the page is unmapped for dma | |
233 | * @dma_addr: The dma address of this page. | |
234 | */ | |
235 | struct efx_rx_page_state { | |
236 | unsigned refcnt; | |
237 | dma_addr_t dma_addr; | |
238 | ||
239 | unsigned int __pad[0] ____cacheline_aligned; | |
240 | }; | |
241 | ||
8ceee660 BH |
242 | /** |
243 | * struct efx_rx_queue - An Efx RX queue | |
244 | * @efx: The associated Efx NIC | |
8ceee660 BH |
245 | * @buffer: The software buffer ring |
246 | * @rxd: The hardware descriptor ring | |
ecc910f5 | 247 | * @ptr_mask: The size of the ring minus 1. |
9f2cb71c BH |
248 | * @enabled: Receive queue enabled indicator. |
249 | * @flush_pending: Set when a RX flush is pending. Has the same lifetime as | |
250 | * @rxq_flush_pending. | |
8ceee660 BH |
251 | * @added_count: Number of buffers added to the receive queue. |
252 | * @notified_count: Number of buffers given to NIC (<= @added_count). | |
253 | * @removed_count: Number of buffers removed from the receive queue. | |
8ceee660 BH |
254 | * @max_fill: RX descriptor maximum fill level (<= ring size) |
255 | * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill | |
256 | * (<= @max_fill) | |
8ceee660 BH |
257 | * @min_fill: RX descriptor minimum non-zero fill level. |
258 | * This records the minimum fill level observed when a ring | |
259 | * refill was triggered. | |
8ceee660 BH |
260 | * @alloc_page_count: RX allocation strategy counter. |
261 | * @alloc_skb_count: RX allocation strategy counter. | |
90d683af | 262 | * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). |
8ceee660 BH |
263 | */ |
264 | struct efx_rx_queue { | |
265 | struct efx_nic *efx; | |
8ceee660 BH |
266 | struct efx_rx_buffer *buffer; |
267 | struct efx_special_buffer rxd; | |
ecc910f5 | 268 | unsigned int ptr_mask; |
9f2cb71c BH |
269 | bool enabled; |
270 | bool flush_pending; | |
8ceee660 BH |
271 | |
272 | int added_count; | |
273 | int notified_count; | |
274 | int removed_count; | |
8ceee660 BH |
275 | unsigned int max_fill; |
276 | unsigned int fast_fill_trigger; | |
8ceee660 BH |
277 | unsigned int min_fill; |
278 | unsigned int min_overfill; | |
279 | unsigned int alloc_page_count; | |
280 | unsigned int alloc_skb_count; | |
90d683af | 281 | struct timer_list slow_fill; |
8ceee660 | 282 | unsigned int slow_fill_count; |
8ceee660 BH |
283 | }; |
284 | ||
285 | /** | |
286 | * struct efx_buffer - An Efx general-purpose buffer | |
287 | * @addr: host base address of the buffer | |
288 | * @dma_addr: DMA base address of the buffer | |
289 | * @len: Buffer length, in bytes | |
290 | * | |
754c653a | 291 | * The NIC uses these buffers for its interrupt status registers and |
8ceee660 BH |
292 | * MAC stats dumps. |
293 | */ | |
294 | struct efx_buffer { | |
295 | void *addr; | |
296 | dma_addr_t dma_addr; | |
297 | unsigned int len; | |
298 | }; | |
299 | ||
300 | ||
8ceee660 BH |
301 | enum efx_rx_alloc_method { |
302 | RX_ALLOC_METHOD_AUTO = 0, | |
303 | RX_ALLOC_METHOD_SKB = 1, | |
304 | RX_ALLOC_METHOD_PAGE = 2, | |
305 | }; | |
306 | ||
307 | /** | |
308 | * struct efx_channel - An Efx channel | |
309 | * | |
310 | * A channel comprises an event queue, at least one TX queue, at least | |
311 | * one RX queue, and an associated tasklet for processing the event | |
312 | * queue. | |
313 | * | |
314 | * @efx: Associated Efx NIC | |
8ceee660 | 315 | * @channel: Channel instance number |
7f967c01 | 316 | * @type: Channel type definition |
8ceee660 BH |
317 | * @enabled: Channel enabled indicator |
318 | * @irq: IRQ number (MSI and MSI-X only) | |
0d86ebd8 | 319 | * @irq_moderation: IRQ moderation value (in hardware ticks) |
8ceee660 BH |
320 | * @napi_dev: Net device used with NAPI |
321 | * @napi_str: NAPI control structure | |
8ceee660 BH |
322 | * @work_pending: Is work pending via NAPI? |
323 | * @eventq: Event queue buffer | |
ecc910f5 | 324 | * @eventq_mask: Event queue pointer mask |
8ceee660 | 325 | * @eventq_read_ptr: Event queue read pointer |
dd40781e | 326 | * @event_test_cpu: Last CPU to handle interrupt or test event for this channel |
6fb70fd1 BH |
327 | * @irq_count: Number of IRQs since last adaptive moderation decision |
328 | * @irq_mod_score: IRQ moderation score | |
8ceee660 BH |
329 | * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors |
330 | * and diagnostic counters | |
331 | * @rx_alloc_push_pages: RX allocation method currently in use for pushing | |
332 | * descriptors | |
8ceee660 | 333 | * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors |
8ceee660 BH |
334 | * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors |
335 | * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors | |
c1ac403b | 336 | * @n_rx_mcast_mismatch: Count of unmatched multicast frames |
8ceee660 BH |
337 | * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors |
338 | * @n_rx_overlength: Count of RX_OVERLENGTH errors | |
339 | * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun | |
8313aca3 | 340 | * @rx_queue: RX queue for this channel |
8313aca3 | 341 | * @tx_queue: TX queues for this channel |
8ceee660 BH |
342 | */ |
343 | struct efx_channel { | |
344 | struct efx_nic *efx; | |
8ceee660 | 345 | int channel; |
7f967c01 | 346 | const struct efx_channel_type *type; |
dc8cfa55 | 347 | bool enabled; |
8ceee660 | 348 | int irq; |
8ceee660 BH |
349 | unsigned int irq_moderation; |
350 | struct net_device *napi_dev; | |
351 | struct napi_struct napi_str; | |
dc8cfa55 | 352 | bool work_pending; |
8ceee660 | 353 | struct efx_special_buffer eventq; |
ecc910f5 | 354 | unsigned int eventq_mask; |
8ceee660 | 355 | unsigned int eventq_read_ptr; |
dd40781e | 356 | int event_test_cpu; |
8ceee660 | 357 | |
6fb70fd1 BH |
358 | unsigned int irq_count; |
359 | unsigned int irq_mod_score; | |
64d8ad6d BH |
360 | #ifdef CONFIG_RFS_ACCEL |
361 | unsigned int rfs_filters_added; | |
362 | #endif | |
6fb70fd1 | 363 | |
8ceee660 BH |
364 | int rx_alloc_level; |
365 | int rx_alloc_push_pages; | |
8ceee660 BH |
366 | |
367 | unsigned n_rx_tobe_disc; | |
8ceee660 BH |
368 | unsigned n_rx_ip_hdr_chksum_err; |
369 | unsigned n_rx_tcp_udp_chksum_err; | |
c1ac403b | 370 | unsigned n_rx_mcast_mismatch; |
8ceee660 BH |
371 | unsigned n_rx_frm_trunc; |
372 | unsigned n_rx_overlength; | |
373 | unsigned n_skbuff_leaks; | |
374 | ||
375 | /* Used to pipeline received packets in order to optimise memory | |
376 | * access with prefetches. | |
377 | */ | |
378 | struct efx_rx_buffer *rx_pkt; | |
8ceee660 | 379 | |
8313aca3 | 380 | struct efx_rx_queue rx_queue; |
94b274bf | 381 | struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; |
8ceee660 BH |
382 | }; |
383 | ||
7f967c01 BH |
384 | /** |
385 | * struct efx_channel_type - distinguishes traffic and extra channels | |
386 | * @handle_no_channel: Handle failure to allocate an extra channel | |
387 | * @pre_probe: Set up extra state prior to initialisation | |
388 | * @post_remove: Tear down extra state after finalisation, if allocated. | |
389 | * May be called on channels that have not been probed. | |
390 | * @get_name: Generate the channel's name (used for its IRQ handler) | |
391 | * @copy: Copy the channel state prior to reallocation. May be %NULL if | |
392 | * reallocation is not supported. | |
393 | * @keep_eventq: Flag for whether event queue should be kept initialised | |
394 | * while the device is stopped | |
395 | */ | |
396 | struct efx_channel_type { | |
397 | void (*handle_no_channel)(struct efx_nic *); | |
398 | int (*pre_probe)(struct efx_channel *); | |
399 | void (*get_name)(struct efx_channel *, char *buf, size_t len); | |
400 | struct efx_channel *(*copy)(const struct efx_channel *); | |
401 | bool keep_eventq; | |
402 | }; | |
403 | ||
398468ed BH |
404 | enum efx_led_mode { |
405 | EFX_LED_OFF = 0, | |
406 | EFX_LED_ON = 1, | |
407 | EFX_LED_DEFAULT = 2 | |
408 | }; | |
409 | ||
c459302d BH |
410 | #define STRING_TABLE_LOOKUP(val, member) \ |
411 | ((val) < member ## _max) ? member ## _names[val] : "(invalid)" | |
412 | ||
18e83e4c | 413 | extern const char *const efx_loopback_mode_names[]; |
c459302d BH |
414 | extern const unsigned int efx_loopback_mode_max; |
415 | #define LOOPBACK_MODE(efx) \ | |
416 | STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) | |
417 | ||
18e83e4c | 418 | extern const char *const efx_reset_type_names[]; |
c459302d BH |
419 | extern const unsigned int efx_reset_type_max; |
420 | #define RESET_TYPE(type) \ | |
421 | STRING_TABLE_LOOKUP(type, efx_reset_type) | |
3273c2e8 | 422 | |
8ceee660 BH |
423 | enum efx_int_mode { |
424 | /* Be careful if altering to correct macro below */ | |
425 | EFX_INT_MODE_MSIX = 0, | |
426 | EFX_INT_MODE_MSI = 1, | |
427 | EFX_INT_MODE_LEGACY = 2, | |
428 | EFX_INT_MODE_MAX /* Insert any new items before this */ | |
429 | }; | |
430 | #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) | |
431 | ||
8ceee660 BH |
432 | enum nic_state { |
433 | STATE_INIT = 0, | |
434 | STATE_RUNNING = 1, | |
435 | STATE_FINI = 2, | |
3c78708f | 436 | STATE_DISABLED = 3, |
8ceee660 BH |
437 | STATE_MAX, |
438 | }; | |
439 | ||
440 | /* | |
441 | * Alignment of page-allocated RX buffers | |
442 | * | |
443 | * Controls the number of bytes inserted at the start of an RX buffer. | |
444 | * This is the equivalent of NET_IP_ALIGN [which controls the alignment | |
445 | * of the skb->head for hardware DMA]. | |
446 | */ | |
13e9ab11 | 447 | #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
8ceee660 BH |
448 | #define EFX_PAGE_IP_ALIGN 0 |
449 | #else | |
450 | #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN | |
451 | #endif | |
452 | ||
453 | /* | |
454 | * Alignment of the skb->head which wraps a page-allocated RX buffer | |
455 | * | |
456 | * The skb allocated to wrap an rx_buffer can have this alignment. Since | |
457 | * the data is memcpy'd from the rx_buf, it does not need to be equal to | |
458 | * EFX_PAGE_IP_ALIGN. | |
459 | */ | |
460 | #define EFX_PAGE_SKB_ALIGN 2 | |
461 | ||
462 | /* Forward declaration */ | |
463 | struct efx_nic; | |
464 | ||
465 | /* Pseudo bit-mask flow control field */ | |
b5626946 DM |
466 | #define EFX_FC_RX FLOW_CTRL_RX |
467 | #define EFX_FC_TX FLOW_CTRL_TX | |
468 | #define EFX_FC_AUTO 4 | |
8ceee660 | 469 | |
eb50c0d6 BH |
470 | /** |
471 | * struct efx_link_state - Current state of the link | |
472 | * @up: Link is up | |
473 | * @fd: Link is full-duplex | |
474 | * @fc: Actual flow control flags | |
475 | * @speed: Link speed (Mbps) | |
476 | */ | |
477 | struct efx_link_state { | |
478 | bool up; | |
479 | bool fd; | |
b5626946 | 480 | u8 fc; |
eb50c0d6 BH |
481 | unsigned int speed; |
482 | }; | |
483 | ||
fdaa9aed SH |
484 | static inline bool efx_link_state_equal(const struct efx_link_state *left, |
485 | const struct efx_link_state *right) | |
486 | { | |
487 | return left->up == right->up && left->fd == right->fd && | |
488 | left->fc == right->fc && left->speed == right->speed; | |
489 | } | |
490 | ||
8ceee660 BH |
491 | /** |
492 | * struct efx_phy_operations - Efx PHY operations table | |
c1c4f453 BH |
493 | * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, |
494 | * efx->loopback_modes. | |
8ceee660 BH |
495 | * @init: Initialise PHY |
496 | * @fini: Shut down PHY | |
497 | * @reconfigure: Reconfigure PHY (e.g. for new link parameters) | |
fdaa9aed SH |
498 | * @poll: Update @link_state and report whether it changed. |
499 | * Serialised by the mac_lock. | |
177dfcd8 BH |
500 | * @get_settings: Get ethtool settings. Serialised by the mac_lock. |
501 | * @set_settings: Set ethtool settings. Serialised by the mac_lock. | |
af4ad9bc | 502 | * @set_npage_adv: Set abilities advertised in (Extended) Next Page |
04cc8cac | 503 | * (only needed where AN bit is set in mmds) |
4f16c073 | 504 | * @test_alive: Test that PHY is 'alive' (online) |
c1c4f453 | 505 | * @test_name: Get the name of a PHY-specific test/result |
4f16c073 | 506 | * @run_tests: Run tests and record results as appropriate (offline). |
1796721a | 507 | * Flags are the ethtool tests flags. |
8ceee660 BH |
508 | */ |
509 | struct efx_phy_operations { | |
c1c4f453 | 510 | int (*probe) (struct efx_nic *efx); |
8ceee660 BH |
511 | int (*init) (struct efx_nic *efx); |
512 | void (*fini) (struct efx_nic *efx); | |
ff3b00a0 | 513 | void (*remove) (struct efx_nic *efx); |
d3245b28 | 514 | int (*reconfigure) (struct efx_nic *efx); |
fdaa9aed | 515 | bool (*poll) (struct efx_nic *efx); |
177dfcd8 BH |
516 | void (*get_settings) (struct efx_nic *efx, |
517 | struct ethtool_cmd *ecmd); | |
518 | int (*set_settings) (struct efx_nic *efx, | |
519 | struct ethtool_cmd *ecmd); | |
af4ad9bc | 520 | void (*set_npage_adv) (struct efx_nic *efx, u32); |
4f16c073 | 521 | int (*test_alive) (struct efx_nic *efx); |
c1c4f453 | 522 | const char *(*test_name) (struct efx_nic *efx, unsigned int index); |
1796721a | 523 | int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); |
c087bd2c SH |
524 | int (*get_module_eeprom) (struct efx_nic *efx, |
525 | struct ethtool_eeprom *ee, | |
526 | u8 *data); | |
527 | int (*get_module_info) (struct efx_nic *efx, | |
528 | struct ethtool_modinfo *modinfo); | |
8ceee660 BH |
529 | }; |
530 | ||
f8b87c17 | 531 | /** |
49ce9c2c | 532 | * enum efx_phy_mode - PHY operating mode flags |
f8b87c17 BH |
533 | * @PHY_MODE_NORMAL: on and should pass traffic |
534 | * @PHY_MODE_TX_DISABLED: on with TX disabled | |
3e133c44 BH |
535 | * @PHY_MODE_LOW_POWER: set to low power through MDIO |
536 | * @PHY_MODE_OFF: switched off through external control | |
f8b87c17 BH |
537 | * @PHY_MODE_SPECIAL: on but will not pass traffic |
538 | */ | |
539 | enum efx_phy_mode { | |
540 | PHY_MODE_NORMAL = 0, | |
541 | PHY_MODE_TX_DISABLED = 1, | |
3e133c44 BH |
542 | PHY_MODE_LOW_POWER = 2, |
543 | PHY_MODE_OFF = 4, | |
f8b87c17 BH |
544 | PHY_MODE_SPECIAL = 8, |
545 | }; | |
546 | ||
547 | static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) | |
548 | { | |
8c8661e4 | 549 | return !!(mode & ~PHY_MODE_TX_DISABLED); |
f8b87c17 BH |
550 | } |
551 | ||
8ceee660 BH |
552 | /* |
553 | * Efx extended statistics | |
554 | * | |
555 | * Not all statistics are provided by all supported MACs. The purpose | |
556 | * is this structure is to contain the raw statistics provided by each | |
557 | * MAC. | |
558 | */ | |
559 | struct efx_mac_stats { | |
560 | u64 tx_bytes; | |
561 | u64 tx_good_bytes; | |
562 | u64 tx_bad_bytes; | |
f9c76250 BH |
563 | u64 tx_packets; |
564 | u64 tx_bad; | |
565 | u64 tx_pause; | |
566 | u64 tx_control; | |
567 | u64 tx_unicast; | |
568 | u64 tx_multicast; | |
569 | u64 tx_broadcast; | |
570 | u64 tx_lt64; | |
571 | u64 tx_64; | |
572 | u64 tx_65_to_127; | |
573 | u64 tx_128_to_255; | |
574 | u64 tx_256_to_511; | |
575 | u64 tx_512_to_1023; | |
576 | u64 tx_1024_to_15xx; | |
577 | u64 tx_15xx_to_jumbo; | |
578 | u64 tx_gtjumbo; | |
579 | u64 tx_collision; | |
580 | u64 tx_single_collision; | |
581 | u64 tx_multiple_collision; | |
582 | u64 tx_excessive_collision; | |
583 | u64 tx_deferred; | |
584 | u64 tx_late_collision; | |
585 | u64 tx_excessive_deferred; | |
586 | u64 tx_non_tcpudp; | |
587 | u64 tx_mac_src_error; | |
588 | u64 tx_ip_src_error; | |
8ceee660 BH |
589 | u64 rx_bytes; |
590 | u64 rx_good_bytes; | |
591 | u64 rx_bad_bytes; | |
f9c76250 BH |
592 | u64 rx_packets; |
593 | u64 rx_good; | |
594 | u64 rx_bad; | |
595 | u64 rx_pause; | |
596 | u64 rx_control; | |
597 | u64 rx_unicast; | |
598 | u64 rx_multicast; | |
599 | u64 rx_broadcast; | |
600 | u64 rx_lt64; | |
601 | u64 rx_64; | |
602 | u64 rx_65_to_127; | |
603 | u64 rx_128_to_255; | |
604 | u64 rx_256_to_511; | |
605 | u64 rx_512_to_1023; | |
606 | u64 rx_1024_to_15xx; | |
607 | u64 rx_15xx_to_jumbo; | |
608 | u64 rx_gtjumbo; | |
609 | u64 rx_bad_lt64; | |
610 | u64 rx_bad_64_to_15xx; | |
611 | u64 rx_bad_15xx_to_jumbo; | |
612 | u64 rx_bad_gtjumbo; | |
613 | u64 rx_overflow; | |
614 | u64 rx_missed; | |
615 | u64 rx_false_carrier; | |
616 | u64 rx_symbol_error; | |
617 | u64 rx_align_error; | |
618 | u64 rx_length_error; | |
619 | u64 rx_internal_error; | |
620 | u64 rx_good_lt64; | |
8ceee660 BH |
621 | }; |
622 | ||
623 | /* Number of bits used in a multicast filter hash address */ | |
624 | #define EFX_MCAST_HASH_BITS 8 | |
625 | ||
626 | /* Number of (single-bit) entries in a multicast filter hash */ | |
627 | #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) | |
628 | ||
629 | /* An Efx multicast filter hash */ | |
630 | union efx_multicast_hash { | |
631 | u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; | |
632 | efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; | |
633 | }; | |
634 | ||
64eebcfd | 635 | struct efx_filter_state; |
cd2d5b52 BH |
636 | struct efx_vf; |
637 | struct vfdi_status; | |
64eebcfd | 638 | |
8ceee660 BH |
639 | /** |
640 | * struct efx_nic - an Efx NIC | |
641 | * @name: Device name (net device name or bus id before net device registered) | |
642 | * @pci_dev: The PCI device | |
643 | * @type: Controller type attributes | |
644 | * @legacy_irq: IRQ number | |
94dec6a2 | 645 | * @legacy_irq_enabled: Are IRQs enabled on NIC (INT_EN_KER register)? |
8d9853d9 BH |
646 | * @workqueue: Workqueue for port reconfigures and the HW monitor. |
647 | * Work items do not hold and must not acquire RTNL. | |
6977dc63 | 648 | * @workqueue_name: Name of workqueue |
8ceee660 | 649 | * @reset_work: Scheduled reset workitem |
8ceee660 BH |
650 | * @membase_phys: Memory BAR value as physical address |
651 | * @membase: Memory BAR value | |
8ceee660 | 652 | * @interrupt_mode: Interrupt mode |
cc180b69 | 653 | * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds |
6fb70fd1 BH |
654 | * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues |
655 | * @irq_rx_moderation: IRQ moderation time for RX event queues | |
62776d03 | 656 | * @msg_enable: Log message enable flags |
8ceee660 | 657 | * @state: Device state flag. Serialised by the rtnl_lock. |
a7d529ae | 658 | * @reset_pending: Bitmask for pending resets |
8ceee660 BH |
659 | * @tx_queue: TX DMA queues |
660 | * @rx_queue: RX DMA queues | |
661 | * @channel: Channels | |
4642610c | 662 | * @channel_name: Names for channels and their IRQs |
7f967c01 BH |
663 | * @extra_channel_types: Types of extra (non-traffic) channels that |
664 | * should be allocated for this NIC | |
ecc910f5 SH |
665 | * @rxq_entries: Size of receive queues requested by user. |
666 | * @txq_entries: Size of transmit queues requested by user. | |
28e47c49 BH |
667 | * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches |
668 | * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches | |
669 | * @sram_lim_qw: Qword address limit of SRAM | |
0484e0db | 670 | * @next_buffer_table: First available buffer table id |
28b581ab | 671 | * @n_channels: Number of channels in use |
a4900ac9 BH |
672 | * @n_rx_channels: Number of channels used for RX (= number of RX queues) |
673 | * @n_tx_channels: Number of channels used for TX | |
8ceee660 BH |
674 | * @rx_buffer_len: RX buffer length |
675 | * @rx_buffer_order: Order (log2) of number of pages for each RX buffer | |
78d4189d | 676 | * @rx_hash_key: Toeplitz hash key for RSS |
765c9f46 | 677 | * @rx_indir_table: Indirection table for RSS |
0484e0db BH |
678 | * @int_error_count: Number of internal errors seen recently |
679 | * @int_error_expire: Time at which error count will be expired | |
8ceee660 | 680 | * @irq_status: Interrupt status buffer |
c28884c5 | 681 | * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 |
1646a6f3 | 682 | * @irq_level: IRQ level/index for IRQs not triggered by an event queue |
dd40781e | 683 | * @selftest_work: Work item for asynchronous self-test |
76884835 | 684 | * @mtd_list: List of MTDs attached to the NIC |
25985edc | 685 | * @nic_data: Hardware dependent state |
8c8661e4 | 686 | * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, |
e4abce85 | 687 | * efx_monitor() and efx_reconfigure_port() |
8ceee660 | 688 | * @port_enabled: Port enabled indicator. |
fdaa9aed SH |
689 | * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and |
690 | * efx_mac_work() with kernel interfaces. Safe to read under any | |
691 | * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must | |
692 | * be held to modify it. | |
8ceee660 BH |
693 | * @port_initialized: Port initialized? |
694 | * @net_dev: Operating system network device. Consider holding the rtnl lock | |
8ceee660 | 695 | * @stats_buffer: DMA buffer for statistics |
8ceee660 | 696 | * @phy_type: PHY type |
8ceee660 BH |
697 | * @phy_op: PHY interface |
698 | * @phy_data: PHY private data (including PHY-specific stats) | |
68e7f45e | 699 | * @mdio: PHY MDIO interface |
8880f4ec | 700 | * @mdio_bus: PHY MDIO bus ID (only used by Siena) |
8c8661e4 | 701 | * @phy_mode: PHY operating mode. Serialised by @mac_lock. |
d3245b28 | 702 | * @link_advertising: Autonegotiation advertising flags |
eb50c0d6 | 703 | * @link_state: Current state of the link |
8ceee660 BH |
704 | * @n_link_state_changes: Number of times the link has changed state |
705 | * @promiscuous: Promiscuous flag. Protected by netif_tx_lock. | |
706 | * @multicast_hash: Multicast hash table | |
04cc8cac | 707 | * @wanted_fc: Wanted flow control flags |
a606f432 SH |
708 | * @fc_disable: When non-zero flow control is disabled. Typically used to |
709 | * ensure that network back pressure doesn't delay dma queue flushes. | |
710 | * Serialised by the rtnl lock. | |
8be4f3e6 | 711 | * @mac_work: Work item for changing MAC promiscuity and multicast hash |
3273c2e8 BH |
712 | * @loopback_mode: Loopback status |
713 | * @loopback_modes: Supported loopback mode bitmask | |
714 | * @loopback_selftest: Offline self-test private state | |
9f2cb71c BH |
715 | * @drain_pending: Count of RX and TX queues that haven't been flushed and drained. |
716 | * @rxq_flush_pending: Count of number of receive queues that need to be flushed. | |
717 | * Decremented when the efx_flush_rx_queue() is called. | |
718 | * @rxq_flush_outstanding: Count of number of RX flushes started but not yet | |
719 | * completed (either success or failure). Not used when MCDI is used to | |
720 | * flush receive queues. | |
721 | * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. | |
cd2d5b52 BH |
722 | * @vf: Array of &struct efx_vf objects. |
723 | * @vf_count: Number of VFs intended to be enabled. | |
724 | * @vf_init_count: Number of VFs that have been fully initialised. | |
725 | * @vi_scale: log2 number of vnics per VF. | |
726 | * @vf_buftbl_base: The zeroth buffer table index used to back VF queues. | |
727 | * @vfdi_status: Common VFDI status page to be dmad to VF address space. | |
728 | * @local_addr_list: List of local addresses. Protected by %local_lock. | |
729 | * @local_page_list: List of DMA addressable pages used to broadcast | |
730 | * %local_addr_list. Protected by %local_lock. | |
731 | * @local_lock: Mutex protecting %local_addr_list and %local_page_list. | |
732 | * @peer_work: Work item to broadcast peer addresses to VMs. | |
ab28c12a BH |
733 | * @monitor_work: Hardware monitor workitem |
734 | * @biu_lock: BIU (bus interface unit) lock | |
1646a6f3 BH |
735 | * @last_irq_cpu: Last CPU to handle a possible test interrupt. This |
736 | * field is used by efx_test_interrupts() to verify that an | |
737 | * interrupt has occurred. | |
ab28c12a BH |
738 | * @n_rx_nodesc_drop_cnt: RX no descriptor drop count |
739 | * @mac_stats: MAC statistics. These include all statistics the MACs | |
740 | * can provide. Generic code converts these into a standard | |
741 | * &struct net_device_stats. | |
742 | * @stats_lock: Statistics update lock. Serialises statistics fetches | |
1cb34522 | 743 | * and access to @mac_stats. |
8ceee660 | 744 | * |
754c653a | 745 | * This is stored in the private area of the &struct net_device. |
8ceee660 BH |
746 | */ |
747 | struct efx_nic { | |
ab28c12a BH |
748 | /* The following fields should be written very rarely */ |
749 | ||
8ceee660 BH |
750 | char name[IFNAMSIZ]; |
751 | struct pci_dev *pci_dev; | |
752 | const struct efx_nic_type *type; | |
753 | int legacy_irq; | |
94dec6a2 | 754 | bool legacy_irq_enabled; |
8ceee660 | 755 | struct workqueue_struct *workqueue; |
6977dc63 | 756 | char workqueue_name[16]; |
8ceee660 | 757 | struct work_struct reset_work; |
086ea356 | 758 | resource_size_t membase_phys; |
8ceee660 | 759 | void __iomem *membase; |
ab28c12a | 760 | |
8ceee660 | 761 | enum efx_int_mode interrupt_mode; |
cc180b69 | 762 | unsigned int timer_quantum_ns; |
6fb70fd1 BH |
763 | bool irq_rx_adaptive; |
764 | unsigned int irq_rx_moderation; | |
62776d03 | 765 | u32 msg_enable; |
8ceee660 | 766 | |
8ceee660 | 767 | enum nic_state state; |
a7d529ae | 768 | unsigned long reset_pending; |
8ceee660 | 769 | |
8313aca3 | 770 | struct efx_channel *channel[EFX_MAX_CHANNELS]; |
efbc2d7c | 771 | char channel_name[EFX_MAX_CHANNELS][IFNAMSIZ + 6]; |
7f967c01 BH |
772 | const struct efx_channel_type * |
773 | extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; | |
8ceee660 | 774 | |
ecc910f5 SH |
775 | unsigned rxq_entries; |
776 | unsigned txq_entries; | |
28e47c49 BH |
777 | unsigned tx_dc_base; |
778 | unsigned rx_dc_base; | |
779 | unsigned sram_lim_qw; | |
0484e0db | 780 | unsigned next_buffer_table; |
a4900ac9 BH |
781 | unsigned n_channels; |
782 | unsigned n_rx_channels; | |
cd2d5b52 | 783 | unsigned rss_spread; |
97653431 | 784 | unsigned tx_channel_offset; |
a4900ac9 | 785 | unsigned n_tx_channels; |
8ceee660 BH |
786 | unsigned int rx_buffer_len; |
787 | unsigned int rx_buffer_order; | |
5d3a6fca | 788 | u8 rx_hash_key[40]; |
765c9f46 | 789 | u32 rx_indir_table[128]; |
8ceee660 | 790 | |
0484e0db BH |
791 | unsigned int_error_count; |
792 | unsigned long int_error_expire; | |
793 | ||
8ceee660 | 794 | struct efx_buffer irq_status; |
c28884c5 | 795 | unsigned irq_zero_count; |
1646a6f3 | 796 | unsigned irq_level; |
dd40781e | 797 | struct delayed_work selftest_work; |
8ceee660 | 798 | |
76884835 BH |
799 | #ifdef CONFIG_SFC_MTD |
800 | struct list_head mtd_list; | |
801 | #endif | |
4a5b504d | 802 | |
8880f4ec | 803 | void *nic_data; |
8ceee660 BH |
804 | |
805 | struct mutex mac_lock; | |
766ca0fa | 806 | struct work_struct mac_work; |
dc8cfa55 | 807 | bool port_enabled; |
8ceee660 | 808 | |
dc8cfa55 | 809 | bool port_initialized; |
8ceee660 | 810 | struct net_device *net_dev; |
8ceee660 | 811 | |
8ceee660 | 812 | struct efx_buffer stats_buffer; |
8ceee660 | 813 | |
c1c4f453 | 814 | unsigned int phy_type; |
6c8c2513 | 815 | const struct efx_phy_operations *phy_op; |
8ceee660 | 816 | void *phy_data; |
68e7f45e | 817 | struct mdio_if_info mdio; |
8880f4ec | 818 | unsigned int mdio_bus; |
f8b87c17 | 819 | enum efx_phy_mode phy_mode; |
8ceee660 | 820 | |
d3245b28 | 821 | u32 link_advertising; |
eb50c0d6 | 822 | struct efx_link_state link_state; |
8ceee660 BH |
823 | unsigned int n_link_state_changes; |
824 | ||
dc8cfa55 | 825 | bool promiscuous; |
8ceee660 | 826 | union efx_multicast_hash multicast_hash; |
b5626946 | 827 | u8 wanted_fc; |
a606f432 | 828 | unsigned fc_disable; |
8ceee660 BH |
829 | |
830 | atomic_t rx_reset; | |
3273c2e8 | 831 | enum efx_loopback_mode loopback_mode; |
e58f69f4 | 832 | u64 loopback_modes; |
3273c2e8 BH |
833 | |
834 | void *loopback_selftest; | |
64eebcfd BH |
835 | |
836 | struct efx_filter_state *filter_state; | |
ab28c12a | 837 | |
9f2cb71c BH |
838 | atomic_t drain_pending; |
839 | atomic_t rxq_flush_pending; | |
840 | atomic_t rxq_flush_outstanding; | |
841 | wait_queue_head_t flush_wq; | |
842 | ||
cd2d5b52 BH |
843 | #ifdef CONFIG_SFC_SRIOV |
844 | struct efx_channel *vfdi_channel; | |
845 | struct efx_vf *vf; | |
846 | unsigned vf_count; | |
847 | unsigned vf_init_count; | |
848 | unsigned vi_scale; | |
849 | unsigned vf_buftbl_base; | |
850 | struct efx_buffer vfdi_status; | |
851 | struct list_head local_addr_list; | |
852 | struct list_head local_page_list; | |
853 | struct mutex local_lock; | |
854 | struct work_struct peer_work; | |
855 | #endif | |
856 | ||
ab28c12a BH |
857 | /* The following fields may be written more often */ |
858 | ||
859 | struct delayed_work monitor_work ____cacheline_aligned_in_smp; | |
860 | spinlock_t biu_lock; | |
1646a6f3 | 861 | int last_irq_cpu; |
ab28c12a BH |
862 | unsigned n_rx_nodesc_drop_cnt; |
863 | struct efx_mac_stats mac_stats; | |
864 | spinlock_t stats_lock; | |
8ceee660 BH |
865 | }; |
866 | ||
55668611 BH |
867 | static inline int efx_dev_registered(struct efx_nic *efx) |
868 | { | |
869 | return efx->net_dev->reg_state == NETREG_REGISTERED; | |
870 | } | |
871 | ||
8880f4ec BH |
872 | static inline unsigned int efx_port_num(struct efx_nic *efx) |
873 | { | |
3df95ce9 | 874 | return efx->net_dev->dev_id; |
8880f4ec BH |
875 | } |
876 | ||
8ceee660 BH |
877 | /** |
878 | * struct efx_nic_type - Efx device type definition | |
ef2b90ee BH |
879 | * @probe: Probe the controller |
880 | * @remove: Free resources allocated by probe() | |
881 | * @init: Initialise the controller | |
28e47c49 BH |
882 | * @dimension_resources: Dimension controller resources (buffer table, |
883 | * and VIs once the available interrupt resources are clear) | |
ef2b90ee BH |
884 | * @fini: Shut down the controller |
885 | * @monitor: Periodic function for polling link state and hardware monitor | |
0e2a9c7c BH |
886 | * @map_reset_reason: Map ethtool reset reason to a reset method |
887 | * @map_reset_flags: Map ethtool reset flags to a reset method, if possible | |
ef2b90ee BH |
888 | * @reset: Reset the controller hardware and possibly the PHY. This will |
889 | * be called while the controller is uninitialised. | |
890 | * @probe_port: Probe the MAC and PHY | |
891 | * @remove_port: Free resources allocated by probe_port() | |
40641ed9 | 892 | * @handle_global_event: Handle a "global" event (may be %NULL) |
ef2b90ee BH |
893 | * @prepare_flush: Prepare the hardware for flushing the DMA queues |
894 | * @update_stats: Update statistics not provided by event handling | |
895 | * @start_stats: Start the regular fetching of statistics | |
896 | * @stop_stats: Stop the regular fetching of statistics | |
06629f07 | 897 | * @set_id_led: Set state of identifying LED or revert to automatic function |
ef2b90ee | 898 | * @push_irq_moderation: Apply interrupt moderation value |
d3245b28 | 899 | * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY |
30b81cda BH |
900 | * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings |
901 | * to the hardware. Serialised by the mac_lock. | |
710b208d | 902 | * @check_mac_fault: Check MAC fault state. True if fault present. |
89c758fa BH |
903 | * @get_wol: Get WoL configuration from driver state |
904 | * @set_wol: Push WoL configuration to the NIC | |
905 | * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) | |
d4f2cecc BH |
906 | * @test_chip: Test registers. Should use efx_nic_test_registers(), and is |
907 | * expected to reset the NIC. | |
0aa3fbaa | 908 | * @test_nvram: Test validity of NVRAM contents |
daeda630 | 909 | * @revision: Hardware architecture revision |
8ceee660 BH |
910 | * @mem_map_size: Memory BAR mapped size |
911 | * @txd_ptr_tbl_base: TX descriptor ring base address | |
912 | * @rxd_ptr_tbl_base: RX descriptor ring base address | |
913 | * @buf_tbl_base: Buffer table base address | |
914 | * @evq_ptr_tbl_base: Event queue pointer table base address | |
915 | * @evq_rptr_tbl_base: Event queue read-pointer table base address | |
8ceee660 | 916 | * @max_dma_mask: Maximum possible DMA mask |
39c9cf07 BH |
917 | * @rx_buffer_hash_size: Size of hash at start of RX buffer |
918 | * @rx_buffer_padding: Size of padding at end of RX buffer | |
8ceee660 BH |
919 | * @max_interrupt_mode: Highest capability interrupt mode supported |
920 | * from &enum efx_init_mode. | |
921 | * @phys_addr_channels: Number of channels with physically addressed | |
922 | * descriptors | |
cc180b69 | 923 | * @timer_period_max: Maximum period of interrupt timer (in ticks) |
c383b537 BH |
924 | * @offload_features: net_device feature flags for protocol offload |
925 | * features implemented in hardware | |
8ceee660 BH |
926 | */ |
927 | struct efx_nic_type { | |
ef2b90ee BH |
928 | int (*probe)(struct efx_nic *efx); |
929 | void (*remove)(struct efx_nic *efx); | |
930 | int (*init)(struct efx_nic *efx); | |
28e47c49 | 931 | void (*dimension_resources)(struct efx_nic *efx); |
ef2b90ee BH |
932 | void (*fini)(struct efx_nic *efx); |
933 | void (*monitor)(struct efx_nic *efx); | |
0e2a9c7c BH |
934 | enum reset_type (*map_reset_reason)(enum reset_type reason); |
935 | int (*map_reset_flags)(u32 *flags); | |
ef2b90ee BH |
936 | int (*reset)(struct efx_nic *efx, enum reset_type method); |
937 | int (*probe_port)(struct efx_nic *efx); | |
938 | void (*remove_port)(struct efx_nic *efx); | |
40641ed9 | 939 | bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); |
ef2b90ee BH |
940 | void (*prepare_flush)(struct efx_nic *efx); |
941 | void (*update_stats)(struct efx_nic *efx); | |
942 | void (*start_stats)(struct efx_nic *efx); | |
943 | void (*stop_stats)(struct efx_nic *efx); | |
06629f07 | 944 | void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); |
ef2b90ee | 945 | void (*push_irq_moderation)(struct efx_channel *channel); |
d3245b28 | 946 | int (*reconfigure_port)(struct efx_nic *efx); |
710b208d BH |
947 | int (*reconfigure_mac)(struct efx_nic *efx); |
948 | bool (*check_mac_fault)(struct efx_nic *efx); | |
89c758fa BH |
949 | void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); |
950 | int (*set_wol)(struct efx_nic *efx, u32 type); | |
951 | void (*resume_wol)(struct efx_nic *efx); | |
d4f2cecc | 952 | int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); |
0aa3fbaa | 953 | int (*test_nvram)(struct efx_nic *efx); |
b895d73e | 954 | |
daeda630 | 955 | int revision; |
8ceee660 BH |
956 | unsigned int mem_map_size; |
957 | unsigned int txd_ptr_tbl_base; | |
958 | unsigned int rxd_ptr_tbl_base; | |
959 | unsigned int buf_tbl_base; | |
960 | unsigned int evq_ptr_tbl_base; | |
961 | unsigned int evq_rptr_tbl_base; | |
9bbd7d9a | 962 | u64 max_dma_mask; |
39c9cf07 | 963 | unsigned int rx_buffer_hash_size; |
8ceee660 BH |
964 | unsigned int rx_buffer_padding; |
965 | unsigned int max_interrupt_mode; | |
966 | unsigned int phys_addr_channels; | |
cc180b69 | 967 | unsigned int timer_period_max; |
c8f44aff | 968 | netdev_features_t offload_features; |
8ceee660 BH |
969 | }; |
970 | ||
971 | /************************************************************************** | |
972 | * | |
973 | * Prototypes and inline functions | |
974 | * | |
975 | *************************************************************************/ | |
976 | ||
f7d12cdc BH |
977 | static inline struct efx_channel * |
978 | efx_get_channel(struct efx_nic *efx, unsigned index) | |
979 | { | |
980 | EFX_BUG_ON_PARANOID(index >= efx->n_channels); | |
8313aca3 | 981 | return efx->channel[index]; |
f7d12cdc BH |
982 | } |
983 | ||
8ceee660 BH |
984 | /* Iterate over all used channels */ |
985 | #define efx_for_each_channel(_channel, _efx) \ | |
8313aca3 BH |
986 | for (_channel = (_efx)->channel[0]; \ |
987 | _channel; \ | |
988 | _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ | |
989 | (_efx)->channel[_channel->channel + 1] : NULL) | |
8ceee660 | 990 | |
7f967c01 BH |
991 | /* Iterate over all used channels in reverse */ |
992 | #define efx_for_each_channel_rev(_channel, _efx) \ | |
993 | for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ | |
994 | _channel; \ | |
995 | _channel = _channel->channel ? \ | |
996 | (_efx)->channel[_channel->channel - 1] : NULL) | |
997 | ||
97653431 BH |
998 | static inline struct efx_tx_queue * |
999 | efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) | |
1000 | { | |
1001 | EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || | |
1002 | type >= EFX_TXQ_TYPES); | |
1003 | return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; | |
1004 | } | |
f7d12cdc | 1005 | |
525da907 BH |
1006 | static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) |
1007 | { | |
1008 | return channel->channel - channel->efx->tx_channel_offset < | |
1009 | channel->efx->n_tx_channels; | |
1010 | } | |
1011 | ||
f7d12cdc BH |
1012 | static inline struct efx_tx_queue * |
1013 | efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) | |
1014 | { | |
525da907 BH |
1015 | EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || |
1016 | type >= EFX_TXQ_TYPES); | |
1017 | return &channel->tx_queue[type]; | |
f7d12cdc | 1018 | } |
8ceee660 | 1019 | |
94b274bf BH |
1020 | static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) |
1021 | { | |
1022 | return !(tx_queue->efx->net_dev->num_tc < 2 && | |
1023 | tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); | |
1024 | } | |
1025 | ||
8ceee660 BH |
1026 | /* Iterate over all TX queues belonging to a channel */ |
1027 | #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ | |
525da907 BH |
1028 | if (!efx_channel_has_tx_queues(_channel)) \ |
1029 | ; \ | |
1030 | else \ | |
1031 | for (_tx_queue = (_channel)->tx_queue; \ | |
94b274bf BH |
1032 | _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ |
1033 | efx_tx_queue_used(_tx_queue); \ | |
525da907 | 1034 | _tx_queue++) |
8ceee660 | 1035 | |
94b274bf BH |
1036 | /* Iterate over all possible TX queues belonging to a channel */ |
1037 | #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ | |
73e0026f BH |
1038 | if (!efx_channel_has_tx_queues(_channel)) \ |
1039 | ; \ | |
1040 | else \ | |
1041 | for (_tx_queue = (_channel)->tx_queue; \ | |
1042 | _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ | |
1043 | _tx_queue++) | |
94b274bf | 1044 | |
525da907 BH |
1045 | static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) |
1046 | { | |
1047 | return channel->channel < channel->efx->n_rx_channels; | |
1048 | } | |
1049 | ||
f7d12cdc BH |
1050 | static inline struct efx_rx_queue * |
1051 | efx_channel_get_rx_queue(struct efx_channel *channel) | |
1052 | { | |
525da907 BH |
1053 | EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); |
1054 | return &channel->rx_queue; | |
f7d12cdc BH |
1055 | } |
1056 | ||
8ceee660 BH |
1057 | /* Iterate over all RX queues belonging to a channel */ |
1058 | #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ | |
525da907 BH |
1059 | if (!efx_channel_has_rx_queue(_channel)) \ |
1060 | ; \ | |
1061 | else \ | |
1062 | for (_rx_queue = &(_channel)->rx_queue; \ | |
1063 | _rx_queue; \ | |
1064 | _rx_queue = NULL) | |
8ceee660 | 1065 | |
ba1e8a35 BH |
1066 | static inline struct efx_channel * |
1067 | efx_rx_queue_channel(struct efx_rx_queue *rx_queue) | |
1068 | { | |
8313aca3 | 1069 | return container_of(rx_queue, struct efx_channel, rx_queue); |
ba1e8a35 BH |
1070 | } |
1071 | ||
1072 | static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) | |
1073 | { | |
8313aca3 | 1074 | return efx_rx_queue_channel(rx_queue)->channel; |
ba1e8a35 BH |
1075 | } |
1076 | ||
8ceee660 BH |
1077 | /* Returns a pointer to the specified receive buffer in the RX |
1078 | * descriptor queue. | |
1079 | */ | |
1080 | static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, | |
1081 | unsigned int index) | |
1082 | { | |
807540ba | 1083 | return &rx_queue->buffer[index]; |
8ceee660 BH |
1084 | } |
1085 | ||
1086 | /* Set bit in a little-endian bitfield */ | |
18c2fc04 | 1087 | static inline void set_bit_le(unsigned nr, unsigned char *addr) |
8ceee660 BH |
1088 | { |
1089 | addr[nr / 8] |= (1 << (nr % 8)); | |
1090 | } | |
1091 | ||
1092 | /* Clear bit in a little-endian bitfield */ | |
18c2fc04 | 1093 | static inline void clear_bit_le(unsigned nr, unsigned char *addr) |
8ceee660 BH |
1094 | { |
1095 | addr[nr / 8] &= ~(1 << (nr % 8)); | |
1096 | } | |
1097 | ||
1098 | ||
1099 | /** | |
1100 | * EFX_MAX_FRAME_LEN - calculate maximum frame length | |
1101 | * | |
1102 | * This calculates the maximum frame length that will be used for a | |
1103 | * given MTU. The frame length will be equal to the MTU plus a | |
1104 | * constant amount of header space and padding. This is the quantity | |
1105 | * that the net driver will program into the MAC as the maximum frame | |
1106 | * length. | |
1107 | * | |
754c653a | 1108 | * The 10G MAC requires 8-byte alignment on the frame |
8ceee660 | 1109 | * length, so we round up to the nearest 8. |
cc11763b BH |
1110 | * |
1111 | * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an | |
1112 | * XGMII cycle). If the frame length reaches the maximum value in the | |
1113 | * same cycle, the XMAC can miss the IPG altogether. We work around | |
1114 | * this by adding a further 16 bytes. | |
8ceee660 BH |
1115 | */ |
1116 | #define EFX_MAX_FRAME_LEN(mtu) \ | |
cc11763b | 1117 | ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) |
8ceee660 BH |
1118 | |
1119 | ||
1120 | #endif /* EFX_NET_DRIVER_H */ |