[deliverable/linux.git] / drivers / net / ethernet / sfc / nic.c

/****************************************************************************
 * Driver for Solarflare Solarstorm network controllers and boards
 * Copyright 2005-2006 Fen Systems Ltd.
 * Copyright 2006-2011 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/cpu_rmap.h>
#include "net_driver.h"
#include "bitfield.h"
#include "efx.h"
#include "nic.h"
#include "farch_regs.h"
#include "io.h"
#include "workarounds.h"

/**************************************************************************
 *
 * Generic buffer handling
 * These buffers are used for interrupt status, MAC stats, etc.
 *
 **************************************************************************/

int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
			 unsigned int len, gfp_t gfp_flags)
{
	buffer->addr = dma_zalloc_coherent(&efx->pci_dev->dev, len,
					   &buffer->dma_addr, gfp_flags);
	if (!buffer->addr)
		return -ENOMEM;
	buffer->len = len;
	return 0;
}

void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
{
	if (buffer->addr) {
		dma_free_coherent(&efx->pci_dev->dev, buffer->len,
				  buffer->addr, buffer->dma_addr);
		buffer->addr = NULL;
	}
}

/* Check whether an event is present in the eventq at the current
 * read pointer.  Only useful for self-test.
 */
bool efx_nic_event_present(struct efx_channel *channel)
{
	return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
}

void efx_nic_event_test_start(struct efx_channel *channel)
{
	channel->event_test_cpu = -1;
	smp_wmb();
	channel->efx->type->ev_test_generate(channel);
}

void efx_nic_irq_test_start(struct efx_nic *efx)
{
	efx->last_irq_cpu = -1;
	smp_wmb();
	efx->type->irq_test_generate(efx);
}

/* Hook interrupt handler(s)
 * Try MSI and then legacy interrupts.
 */
int efx_nic_init_interrupt(struct efx_nic *efx)
{
	struct efx_channel *channel;
	unsigned int n_irqs;
	int rc;

	if (!EFX_INT_MODE_USE_MSI(efx)) {
		rc = request_irq(efx->legacy_irq,
				 efx->type->irq_handle_legacy, IRQF_SHARED,
				 efx->name, efx);
		if (rc) {
			netif_err(efx, drv, efx->net_dev,
				  "failed to hook legacy IRQ %d\n",
				  efx->pci_dev->irq);
			goto fail1;
		}
		return 0;
	}

#ifdef CONFIG_RFS_ACCEL
	if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
		efx->net_dev->rx_cpu_rmap =
			alloc_irq_cpu_rmap(efx->n_rx_channels);
		if (!efx->net_dev->rx_cpu_rmap) {
			rc = -ENOMEM;
			goto fail1;
		}
	}
#endif

	/* Hook MSI or MSI-X interrupt */
	n_irqs = 0;
	efx_for_each_channel(channel, efx) {
		rc = request_irq(channel->irq, efx->type->irq_handle_msi,
				 IRQF_PROBE_SHARED, /* Not shared */
				 efx->msi_context[channel->channel].name,
				 &efx->msi_context[channel->channel]);
		if (rc) {
			netif_err(efx, drv, efx->net_dev,
				  "failed to hook IRQ %d\n", channel->irq);
			goto fail2;
		}
		++n_irqs;

#ifdef CONFIG_RFS_ACCEL
		if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&
		    channel->channel < efx->n_rx_channels) {
			rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
					      channel->irq);
			if (rc)
				goto fail2;
		}
#endif
	}

	return 0;

 fail2:
#ifdef CONFIG_RFS_ACCEL
	free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
	efx->net_dev->rx_cpu_rmap = NULL;
#endif
	efx_for_each_channel(channel, efx) {
		if (n_irqs-- == 0)
			break;
		free_irq(channel->irq, &efx->msi_context[channel->channel]);
	}
 fail1:
	return rc;
}

void efx_nic_fini_interrupt(struct efx_nic *efx)
{
	struct efx_channel *channel;

#ifdef CONFIG_RFS_ACCEL
	free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
	efx->net_dev->rx_cpu_rmap = NULL;
#endif

	/* Disable MSI/MSI-X interrupts */
	efx_for_each_channel(channel, efx)
		free_irq(channel->irq, &efx->msi_context[channel->channel]);

	/* Disable legacy interrupt */
	if (efx->legacy_irq)
		free_irq(efx->legacy_irq, efx);
}

/* Register dump */

#define REGISTER_REVISION_A	1
#define REGISTER_REVISION_B	2
#define REGISTER_REVISION_C	3
#define REGISTER_REVISION_Z	3	/* latest revision */

struct efx_nic_reg {
	u32 offset:24;
	u32 min_revision:2, max_revision:2;
};

#define REGISTER(name, min_rev, max_rev) {				\
	FR_ ## min_rev ## max_rev ## _ ## name,				\
	REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev	\
}
#define REGISTER_AA(name) REGISTER(name, A, A)
#define REGISTER_AB(name) REGISTER(name, A, B)
#define REGISTER_AZ(name) REGISTER(name, A, Z)
#define REGISTER_BB(name) REGISTER(name, B, B)
#define REGISTER_BZ(name) REGISTER(name, B, Z)
#define REGISTER_CZ(name) REGISTER(name, C, Z)

static const struct efx_nic_reg efx_nic_regs[] = {
	REGISTER_AZ(ADR_REGION),
	REGISTER_AZ(INT_EN_KER),
	REGISTER_BZ(INT_EN_CHAR),
	REGISTER_AZ(INT_ADR_KER),
	REGISTER_BZ(INT_ADR_CHAR),
	/* INT_ACK_KER is WO */
	/* INT_ISR0 is RC */
	REGISTER_AZ(HW_INIT),
	REGISTER_CZ(USR_EV_CFG),
	REGISTER_AB(EE_SPI_HCMD),
	REGISTER_AB(EE_SPI_HADR),
	REGISTER_AB(EE_SPI_HDATA),
	REGISTER_AB(EE_BASE_PAGE),
	REGISTER_AB(EE_VPD_CFG0),
	/* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
	/* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
	/* PCIE_CORE_INDIRECT is indirect */
	REGISTER_AB(NIC_STAT),
	REGISTER_AB(GPIO_CTL),
	REGISTER_AB(GLB_CTL),
	/* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
	REGISTER_BZ(DP_CTRL),
	REGISTER_AZ(MEM_STAT),
	REGISTER_AZ(CS_DEBUG),
	REGISTER_AZ(ALTERA_BUILD),
	REGISTER_AZ(CSR_SPARE),
	REGISTER_AB(PCIE_SD_CTL0123),
	REGISTER_AB(PCIE_SD_CTL45),
	REGISTER_AB(PCIE_PCS_CTL_STAT),
	/* DEBUG_DATA_OUT is not used */
	/* DRV_EV is WO */
	REGISTER_AZ(EVQ_CTL),
	REGISTER_AZ(EVQ_CNT1),
	REGISTER_AZ(EVQ_CNT2),
	REGISTER_AZ(BUF_TBL_CFG),
	REGISTER_AZ(SRM_RX_DC_CFG),
	REGISTER_AZ(SRM_TX_DC_CFG),
	REGISTER_AZ(SRM_CFG),
	/* BUF_TBL_UPD is WO */
	REGISTER_AZ(SRM_UPD_EVQ),
	REGISTER_AZ(SRAM_PARITY),
	REGISTER_AZ(RX_CFG),
	REGISTER_BZ(RX_FILTER_CTL),
	/* RX_FLUSH_DESCQ is WO */
	REGISTER_AZ(RX_DC_CFG),
	REGISTER_AZ(RX_DC_PF_WM),
	REGISTER_BZ(RX_RSS_TKEY),
	/* RX_NODESC_DROP is RC */
	REGISTER_AA(RX_SELF_RST),
	/* RX_DEBUG, RX_PUSH_DROP are not used */
	REGISTER_CZ(RX_RSS_IPV6_REG1),
	REGISTER_CZ(RX_RSS_IPV6_REG2),
	REGISTER_CZ(RX_RSS_IPV6_REG3),
	/* TX_FLUSH_DESCQ is WO */
	REGISTER_AZ(TX_DC_CFG),
	REGISTER_AA(TX_CHKSM_CFG),
	REGISTER_AZ(TX_CFG),
	/* TX_PUSH_DROP is not used */
	REGISTER_AZ(TX_RESERVED),
	REGISTER_BZ(TX_PACE),
	/* TX_PACE_DROP_QID is RC */
	REGISTER_BB(TX_VLAN),
	REGISTER_BZ(TX_IPFIL_PORTEN),
	REGISTER_AB(MD_TXD),
	REGISTER_AB(MD_RXD),
	REGISTER_AB(MD_CS),
	REGISTER_AB(MD_PHY_ADR),
	REGISTER_AB(MD_ID),
	/* MD_STAT is RC */
	REGISTER_AB(MAC_STAT_DMA),
	REGISTER_AB(MAC_CTRL),
	REGISTER_BB(GEN_MODE),
	REGISTER_AB(MAC_MC_HASH_REG0),
	REGISTER_AB(MAC_MC_HASH_REG1),
	REGISTER_AB(GM_CFG1),
	REGISTER_AB(GM_CFG2),
	/* GM_IPG and GM_HD are not used */
	REGISTER_AB(GM_MAX_FLEN),
	/* GM_TEST is not used */
	REGISTER_AB(GM_ADR1),
	REGISTER_AB(GM_ADR2),
	REGISTER_AB(GMF_CFG0),
	REGISTER_AB(GMF_CFG1),
	REGISTER_AB(GMF_CFG2),
	REGISTER_AB(GMF_CFG3),
	REGISTER_AB(GMF_CFG4),
	REGISTER_AB(GMF_CFG5),
	REGISTER_BB(TX_SRC_MAC_CTL),
	REGISTER_AB(XM_ADR_LO),
	REGISTER_AB(XM_ADR_HI),
	REGISTER_AB(XM_GLB_CFG),
	REGISTER_AB(XM_TX_CFG),
	REGISTER_AB(XM_RX_CFG),
	REGISTER_AB(XM_MGT_INT_MASK),
	REGISTER_AB(XM_FC),
	REGISTER_AB(XM_PAUSE_TIME),
	REGISTER_AB(XM_TX_PARAM),
	REGISTER_AB(XM_RX_PARAM),
	/* XM_MGT_INT_MSK (note no 'A') is RC */
	REGISTER_AB(XX_PWR_RST),
	REGISTER_AB(XX_SD_CTL),
	REGISTER_AB(XX_TXDRV_CTL),
	/* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
	/* XX_CORE_STAT is partly RC */
};

struct efx_nic_reg_table {
	u32 offset:24;
	u32 min_revision:2, max_revision:2;
	u32 step:6, rows:21;
};

#define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \
	offset,								\
	REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev,	\
	step, rows							\
}
#define REGISTER_TABLE(name, min_rev, max_rev)				\
	REGISTER_TABLE_DIMENSIONS(					\
		name, FR_ ## min_rev ## max_rev ## _ ## name,		\
		min_rev, max_rev,					\
		FR_ ## min_rev ## max_rev ## _ ## name ## _STEP,	\
		FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
#define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A)
#define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z)
#define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B)
#define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z)
#define REGISTER_TABLE_BB_CZ(name)					\
	REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B,		\
				  FR_BZ_ ## name ## _STEP,		\
				  FR_BB_ ## name ## _ROWS),		\
	REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z,		\
				  FR_BZ_ ## name ## _STEP,		\
				  FR_CZ_ ## name ## _ROWS)
#define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z)

static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
	/* DRIVER is not used */
	/* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
	REGISTER_TABLE_BB(TX_IPFIL_TBL),
	REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
	REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
	REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
	REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
	REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
	REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
	REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
	/* We can't reasonably read all of the buffer table (up to 8MB!).
	 * However this driver will only use a few entries.  Reading
	 * 1K entries allows for some expansion of queue count and
	 * size before we need to change the version. */
	REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
				  A, A, 8, 1024),
	REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
				  B, Z, 8, 1024),
	REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
	REGISTER_TABLE_BB_CZ(TIMER_TBL),
	REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
	REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
	/* TX_FILTER_TBL0 is huge and not used by this driver */
	REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
	REGISTER_TABLE_CZ(MC_TREG_SMEM),
	/* MSIX_PBA_TABLE is not mapped */
	/* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
	REGISTER_TABLE_BZ(RX_FILTER_TBL0),
};

size_t efx_nic_get_regs_len(struct efx_nic *efx)
{
	const struct efx_nic_reg *reg;
	const struct efx_nic_reg_table *table;
	size_t len = 0;

	for (reg = efx_nic_regs;
	     reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
	     reg++)
		if (efx->type->revision >= reg->min_revision &&
		    efx->type->revision <= reg->max_revision)
			len += sizeof(efx_oword_t);

	for (table = efx_nic_reg_tables;
	     table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
	     table++)
		if (efx->type->revision >= table->min_revision &&
		    efx->type->revision <= table->max_revision)
			len += table->rows * min_t(size_t, table->step, 16);

	return len;
}

void efx_nic_get_regs(struct efx_nic *efx, void *buf)
{
	const struct efx_nic_reg *reg;
	const struct efx_nic_reg_table *table;

	for (reg = efx_nic_regs;
	     reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
	     reg++) {
		if (efx->type->revision >= reg->min_revision &&
		    efx->type->revision <= reg->max_revision) {
			efx_reado(efx, (efx_oword_t *)buf, reg->offset);
			buf += sizeof(efx_oword_t);
		}
	}

	for (table = efx_nic_reg_tables;
	     table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
	     table++) {
		size_t size, i;

		if (!(efx->type->revision >= table->min_revision &&
		      efx->type->revision <= table->max_revision))
			continue;

		size = min_t(size_t, table->step, 16);

		for (i = 0; i < table->rows; i++) {
			switch (table->step) {
			case 4: /* 32-bit SRAM */
				efx_readd(efx, buf, table->offset + 4 * i);
				break;
			case 8: /* 64-bit SRAM */
				efx_sram_readq(efx,
					       efx->membase + table->offset,
					       buf, i);
				break;
			case 16: /* 128-bit-readable register */
				efx_reado_table(efx, buf, table->offset, i);
				break;
			case 32: /* 128-bit register, interleaved */
				efx_reado_table(efx, buf, table->offset, 2 * i);
				break;
			default:
				WARN_ON(1);
				return;
			}
			buf += size;
		}
	}
}

/**
 * efx_nic_describe_stats - Describe supported statistics for ethtool
 * @desc: Array of &struct efx_hw_stat_desc describing the statistics
 * @count: Length of the @desc array
 * @mask: Bitmask of which elements of @desc are enabled
 * @names: Buffer to copy names to, or %NULL.  The names are copied
 *	starting at intervals of %ETH_GSTRING_LEN bytes.
 *
 * Returns the number of visible statistics, i.e. the number of set
 * bits in the first @count bits of @mask for which a name is defined.
 */
size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
			      const unsigned long *mask, u8 *names)
{
	size_t visible = 0;
	size_t index;

	for_each_set_bit(index, mask, count) {
		if (desc[index].name) {
			if (names) {
				strlcpy(names, desc[index].name,
					ETH_GSTRING_LEN);
				names += ETH_GSTRING_LEN;
			}
			++visible;
		}
	}

	return visible;
}

/**
 * efx_nic_update_stats - Convert statistics DMA buffer to array of u64
 * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer
 *	layout.  DMA widths of 0, 16, 32 and 64 are supported; where
 *	the width is specified as 0 the corresponding element of
 *	@stats is not updated.
 * @count: Length of the @desc array
 * @mask: Bitmask of which elements of @desc are enabled
 * @stats: Buffer to update with the converted statistics.  The length
 *	of this array must be at least the number of set bits in the
 *	first @count bits of @mask.
 * @dma_buf: DMA buffer containing hardware statistics
 * @accumulate: If set, the converted values will be added rather than
 *	directly stored to the corresponding elements of @stats
 */
void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
			  const unsigned long *mask,
			  u64 *stats, const void *dma_buf, bool accumulate)
{
	size_t index;

	for_each_set_bit(index, mask, count) {
		if (desc[index].dma_width) {
			const void *addr = dma_buf + desc[index].offset;
			u64 val;

			switch (desc[index].dma_width) {
			case 16:
				val = le16_to_cpup((__le16 *)addr);
				break;
			case 32:
				val = le32_to_cpup((__le32 *)addr);
				break;
			case 64:
				val = le64_to_cpup((__le64 *)addr);
				break;
			default:
				WARN_ON(1);
				val = 0;
				break;
			}

			if (accumulate)
				*stats += val;
			else
				*stats = val;
		}

		++stats;
	}
}
Commit	Line	Data
8e730c15 BH	1	/****************************************************************************
	2	* Driver for Solarflare Solarstorm network controllers and boards
	3	* Copyright 2005-2006 Fen Systems Ltd.
0a6f40c6	4	* Copyright 2006-2011 Solarflare Communications Inc.
8e730c15 BH	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation, incorporated herein by reference.
	9	*/
	10
	11	#include <linux/bitops.h>
	12	#include <linux/delay.h>
a6b7a407	13	#include <linux/interrupt.h>
8e730c15 BH	14	#include <linux/pci.h>
	15	#include <linux/module.h>
	16	#include <linux/seq_file.h>
1899c111	17	#include <linux/cpu_rmap.h>
8e730c15 BH	18	#include "net_driver.h"
	19	#include "bitfield.h"
	20	#include "efx.h"
	21	#include "nic.h"
8b8a95a1	22	#include "farch_regs.h"
8e730c15 BH	23	#include "io.h"
	24	#include "workarounds.h"
	25
8e730c15 BH	26	/**************************************************************************
	27	*
	28	* Generic buffer handling
f7251a9c	29	* These buffers are used for interrupt status, MAC stats, etc.
8e730c15 BH	30	*
	31	**************************************************************************/
	32
	33	int efx_nic_alloc_buffer(struct efx_nic efx, struct efx_buffer buffer,
0d19a540	34	unsigned int len, gfp_t gfp_flags)
8e730c15	35	{
ede23fa8 JP	36	buffer->addr = dma_zalloc_coherent(&efx->pci_dev->dev, len,
ede23fa8 JP	37	&buffer->dma_addr, gfp_flags);
8e730c15 BH	38	if (!buffer->addr)
	39	return -ENOMEM;
	40	buffer->len = len;
8e730c15 BH	41	return 0;
	42	}
	43
	44	void efx_nic_free_buffer(struct efx_nic efx, struct efx_buffer buffer)
	45	{
	46	if (buffer->addr) {
0e33d870 BH	47	dma_free_coherent(&efx->pci_dev->dev, buffer->len,
0e33d870 BH	48	buffer->addr, buffer->dma_addr);
8e730c15 BH	49	buffer->addr = NULL;
	50	}
	51	}
	52
d4fabcc8 BH	53	/* Check whether an event is present in the eventq at the current
	54	* read pointer. Only useful for self-test.
	55	*/
	56	bool efx_nic_event_present(struct efx_channel *channel)
	57	{
	58	return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
	59	}
8e730c15	60
eee6f6a9	61	void efx_nic_event_test_start(struct efx_channel *channel)
8e730c15	62	{
dd40781e	63	channel->event_test_cpu = -1;
eee6f6a9	64	smp_wmb();
86094f7f	65	channel->efx->type->ev_test_generate(channel);
8e730c15 BH	66	}
8e730c15 BH	67
eee6f6a9	68	void efx_nic_irq_test_start(struct efx_nic *efx)
8e730c15	69	{
eee6f6a9 BH	70	efx->last_irq_cpu = -1;
eee6f6a9 BH	71	smp_wmb();
86094f7f	72	efx->type->irq_test_generate(efx);
8e730c15 BH	73	}
	74
	75	/* Hook interrupt handler(s)
	76	* Try MSI and then legacy interrupts.
	77	*/
	78	int efx_nic_init_interrupt(struct efx_nic *efx)
	79	{
	80	struct efx_channel *channel;
1899c111	81	unsigned int n_irqs;
8e730c15 BH	82	int rc;
	83
	84	if (!EFX_INT_MODE_USE_MSI(efx)) {
86094f7f BH	85	rc = request_irq(efx->legacy_irq,
86094f7f BH	86	efx->type->irq_handle_legacy, IRQF_SHARED,
8e730c15 BH	87	efx->name, efx);
8e730c15 BH	88	if (rc) {
62776d03 BH	89	netif_err(efx, drv, efx->net_dev,
	90	"failed to hook legacy IRQ %d\n",
	91	efx->pci_dev->irq);
8e730c15 BH	92	goto fail1;
	93	}
	94	return 0;
	95	}
	96
1899c111 BH	97	#ifdef CONFIG_RFS_ACCEL
	98	if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
	99	efx->net_dev->rx_cpu_rmap =
	100	alloc_irq_cpu_rmap(efx->n_rx_channels);
	101	if (!efx->net_dev->rx_cpu_rmap) {
	102	rc = -ENOMEM;
	103	goto fail1;
	104	}
	105	}
	106	#endif
	107
8e730c15	108	/* Hook MSI or MSI-X interrupt */
1899c111	109	n_irqs = 0;
8e730c15	110	efx_for_each_channel(channel, efx) {
86094f7f	111	rc = request_irq(channel->irq, efx->type->irq_handle_msi,
8e730c15	112	IRQF_PROBE_SHARED, /* Not shared */
d8291187 BH	113	efx->msi_context[channel->channel].name,
d8291187 BH	114	&efx->msi_context[channel->channel]);
8e730c15	115	if (rc) {
62776d03 BH	116	netif_err(efx, drv, efx->net_dev,
62776d03 BH	117	"failed to hook IRQ %d\n", channel->irq);
8e730c15 BH	118	goto fail2;
8e730c15 BH	119	}
1899c111 BH	120	++n_irqs;
	121
	122	#ifdef CONFIG_RFS_ACCEL
	123	if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&
	124	channel->channel < efx->n_rx_channels) {
	125	rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
	126	channel->irq);
	127	if (rc)
	128	goto fail2;
	129	}
	130	#endif
8e730c15 BH	131	}
	132
	133	return 0;
	134
	135	fail2:
1899c111 BH	136	#ifdef CONFIG_RFS_ACCEL
	137	free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
	138	efx->net_dev->rx_cpu_rmap = NULL;
	139	#endif
	140	efx_for_each_channel(channel, efx) {
	141	if (n_irqs-- == 0)
	142	break;
d8291187	143	free_irq(channel->irq, &efx->msi_context[channel->channel]);
1899c111	144	}
8e730c15 BH	145	fail1:
	146	return rc;
	147	}
	148
	149	void efx_nic_fini_interrupt(struct efx_nic *efx)
	150	{
	151	struct efx_channel *channel;
8e730c15	152
1899c111 BH	153	#ifdef CONFIG_RFS_ACCEL
	154	free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
	155	efx->net_dev->rx_cpu_rmap = NULL;
	156	#endif
	157
8e730c15	158	/* Disable MSI/MSI-X interrupts */
1899c111	159	efx_for_each_channel(channel, efx)
d8291187	160	free_irq(channel->irq, &efx->msi_context[channel->channel]);
8e730c15	161
8e730c15 BH	162	/* Disable legacy interrupt */
	163	if (efx->legacy_irq)
	164	free_irq(efx->legacy_irq, efx);
	165	}
	166
5b98c1bf BH	167	/* Register dump */
	168
	169	#define REGISTER_REVISION_A 1
	170	#define REGISTER_REVISION_B 2
	171	#define REGISTER_REVISION_C 3
	172	#define REGISTER_REVISION_Z 3 /* latest revision */
	173
	174	struct efx_nic_reg {
	175	u32 offset:24;
	176	u32 min_revision:2, max_revision:2;
	177	};
	178
	179	#define REGISTER(name, min_rev, max_rev) { \
	180	FR_ ## min_rev ## max_rev ## _ ## name, \
	181	REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev \
	182	}
	183	#define REGISTER_AA(name) REGISTER(name, A, A)
	184	#define REGISTER_AB(name) REGISTER(name, A, B)
	185	#define REGISTER_AZ(name) REGISTER(name, A, Z)
	186	#define REGISTER_BB(name) REGISTER(name, B, B)
	187	#define REGISTER_BZ(name) REGISTER(name, B, Z)
	188	#define REGISTER_CZ(name) REGISTER(name, C, Z)
	189
	190	static const struct efx_nic_reg efx_nic_regs[] = {
	191	REGISTER_AZ(ADR_REGION),
	192	REGISTER_AZ(INT_EN_KER),
	193	REGISTER_BZ(INT_EN_CHAR),
	194	REGISTER_AZ(INT_ADR_KER),
	195	REGISTER_BZ(INT_ADR_CHAR),
	196	/* INT_ACK_KER is WO */
	197	/* INT_ISR0 is RC */
	198	REGISTER_AZ(HW_INIT),
	199	REGISTER_CZ(USR_EV_CFG),
	200	REGISTER_AB(EE_SPI_HCMD),
	201	REGISTER_AB(EE_SPI_HADR),
	202	REGISTER_AB(EE_SPI_HDATA),
	203	REGISTER_AB(EE_BASE_PAGE),
	204	REGISTER_AB(EE_VPD_CFG0),
	205	/* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
	206	/* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
	207	/* PCIE_CORE_INDIRECT is indirect */
	208	REGISTER_AB(NIC_STAT),
	209	REGISTER_AB(GPIO_CTL),
	210	REGISTER_AB(GLB_CTL),
	211	/* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
	212	REGISTER_BZ(DP_CTRL),
	213	REGISTER_AZ(MEM_STAT),
	214	REGISTER_AZ(CS_DEBUG),
	215	REGISTER_AZ(ALTERA_BUILD),
	216	REGISTER_AZ(CSR_SPARE),
	217	REGISTER_AB(PCIE_SD_CTL0123),
	218	REGISTER_AB(PCIE_SD_CTL45),
	219	REGISTER_AB(PCIE_PCS_CTL_STAT),
	220	/* DEBUG_DATA_OUT is not used */
	221	/* DRV_EV is WO */
	222	REGISTER_AZ(EVQ_CTL),
	223	REGISTER_AZ(EVQ_CNT1),
	224	REGISTER_AZ(EVQ_CNT2),
	225	REGISTER_AZ(BUF_TBL_CFG),
	226	REGISTER_AZ(SRM_RX_DC_CFG),
	227	REGISTER_AZ(SRM_TX_DC_CFG),
	228	REGISTER_AZ(SRM_CFG),
	229	/* BUF_TBL_UPD is WO */
	230	REGISTER_AZ(SRM_UPD_EVQ),
231	REGISTER_AZ(SRAM_PARITY),
232	REGISTER_AZ(RX_CFG),
233	REGISTER_BZ(RX_FILTER_CTL),
234	/* RX_FLUSH_DESCQ is WO */
235	REGISTER_AZ(RX_DC_CFG),
236	REGISTER_AZ(RX_DC_PF_WM),
237	REGISTER_BZ(RX_RSS_TKEY),
238	/* RX_NODESC_DROP is RC */
239	REGISTER_AA(RX_SELF_RST),
240	/* RX_DEBUG, RX_PUSH_DROP are not used */
241	REGISTER_CZ(RX_RSS_IPV6_REG1),
242	REGISTER_CZ(RX_RSS_IPV6_REG2),
243	REGISTER_CZ(RX_RSS_IPV6_REG3),
244	/* TX_FLUSH_DESCQ is WO */
245	REGISTER_AZ(TX_DC_CFG),
246	REGISTER_AA(TX_CHKSM_CFG),
247	REGISTER_AZ(TX_CFG),
248	/* TX_PUSH_DROP is not used */
249	REGISTER_AZ(TX_RESERVED),
250	REGISTER_BZ(TX_PACE),
251	/* TX_PACE_DROP_QID is RC */
252	REGISTER_BB(TX_VLAN),
253	REGISTER_BZ(TX_IPFIL_PORTEN),
254	REGISTER_AB(MD_TXD),
255	REGISTER_AB(MD_RXD),
256	REGISTER_AB(MD_CS),
257	REGISTER_AB(MD_PHY_ADR),
258	REGISTER_AB(MD_ID),
259	/* MD_STAT is RC */
260	REGISTER_AB(MAC_STAT_DMA),
261	REGISTER_AB(MAC_CTRL),
262	REGISTER_BB(GEN_MODE),
263	REGISTER_AB(MAC_MC_HASH_REG0),
264	REGISTER_AB(MAC_MC_HASH_REG1),
265	REGISTER_AB(GM_CFG1),
266	REGISTER_AB(GM_CFG2),
267	/* GM_IPG and GM_HD are not used */
268	REGISTER_AB(GM_MAX_FLEN),
269	/* GM_TEST is not used */
270	REGISTER_AB(GM_ADR1),
271	REGISTER_AB(GM_ADR2),
272	REGISTER_AB(GMF_CFG0),
273	REGISTER_AB(GMF_CFG1),
274	REGISTER_AB(GMF_CFG2),
275	REGISTER_AB(GMF_CFG3),
276	REGISTER_AB(GMF_CFG4),
277	REGISTER_AB(GMF_CFG5),
278	REGISTER_BB(TX_SRC_MAC_CTL),
279	REGISTER_AB(XM_ADR_LO),
280	REGISTER_AB(XM_ADR_HI),
281	REGISTER_AB(XM_GLB_CFG),
282	REGISTER_AB(XM_TX_CFG),
283	REGISTER_AB(XM_RX_CFG),
284	REGISTER_AB(XM_MGT_INT_MASK),
285	REGISTER_AB(XM_FC),
286	REGISTER_AB(XM_PAUSE_TIME),
287	REGISTER_AB(XM_TX_PARAM),
288	REGISTER_AB(XM_RX_PARAM),
289	/* XM_MGT_INT_MSK (note no 'A') is RC */
290	REGISTER_AB(XX_PWR_RST),
291	REGISTER_AB(XX_SD_CTL),
292	REGISTER_AB(XX_TXDRV_CTL),
293	/* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
294	/* XX_CORE_STAT is partly RC */
295	};
296
297	struct efx_nic_reg_table {
298	u32 offset:24;
299	u32 min_revision:2, max_revision:2;
300	u32 step:6, rows:21;
301	};
302
303	#define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \
304	offset, \
305	REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev, \
306	step, rows \
307	}
9c636baf	308	#define REGISTER_TABLE(name, min_rev, max_rev) \
5b98c1bf BH	309	REGISTER_TABLE_DIMENSIONS( \
	310	name, FR_ ## min_rev ## max_rev ## _ ## name, \
	311	min_rev, max_rev, \
	312	FR_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
	313	FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
	314	#define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A)
	315	#define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z)
	316	#define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B)
	317	#define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z)
	318	#define REGISTER_TABLE_BB_CZ(name) \
	319	REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B, \
	320	FR_BZ_ ## name ## _STEP, \
	321	FR_BB_ ## name ## _ROWS), \
	322	REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z, \
	323	FR_BZ_ ## name ## _STEP, \
	324	FR_CZ_ ## name ## _ROWS)
	325	#define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z)
	326
	327	static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
	328	/* DRIVER is not used */
	329	/* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
	330	REGISTER_TABLE_BB(TX_IPFIL_TBL),
	331	REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
	332	REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
	333	REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
	334	REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
	335	REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
	336	REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
	337	REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
75abc51c	338	/* We can't reasonably read all of the buffer table (up to 8MB!).
5b98c1bf BH	339	* However this driver will only use a few entries. Reading
	340	* 1K entries allows for some expansion of queue count and
	341	* size before we need to change the version. */
	342	REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
	343	A, A, 8, 1024),
	344	REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
	345	B, Z, 8, 1024),
5b98c1bf BH	346	REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
	347	REGISTER_TABLE_BB_CZ(TIMER_TBL),
	348	REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
	349	REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
	350	/* TX_FILTER_TBL0 is huge and not used by this driver */
	351	REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
	352	REGISTER_TABLE_CZ(MC_TREG_SMEM),
	353	/* MSIX_PBA_TABLE is not mapped */
	354	/* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
75abc51c	355	REGISTER_TABLE_BZ(RX_FILTER_TBL0),
5b98c1bf BH	356	};
	357
	358	size_t efx_nic_get_regs_len(struct efx_nic *efx)
	359	{
	360	const struct efx_nic_reg *reg;
	361	const struct efx_nic_reg_table *table;
	362	size_t len = 0;
	363
	364	for (reg = efx_nic_regs;
	365	reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
	366	reg++)
	367	if (efx->type->revision >= reg->min_revision &&
	368	efx->type->revision <= reg->max_revision)
	369	len += sizeof(efx_oword_t);
	370
	371	for (table = efx_nic_reg_tables;
	372	table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
	373	table++)
	374	if (efx->type->revision >= table->min_revision &&
	375	efx->type->revision <= table->max_revision)
	376	len += table->rows * min_t(size_t, table->step, 16);
	377
	378	return len;
	379	}
	380
	381	void efx_nic_get_regs(struct efx_nic efx, void buf)
	382	{
	383	const struct efx_nic_reg *reg;
	384	const struct efx_nic_reg_table *table;
	385
	386	for (reg = efx_nic_regs;
	387	reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
	388	reg++) {
	389	if (efx->type->revision >= reg->min_revision &&
	390	efx->type->revision <= reg->max_revision) {
	391	efx_reado(efx, (efx_oword_t *)buf, reg->offset);
	392	buf += sizeof(efx_oword_t);
	393	}
	394	}
	395
	396	for (table = efx_nic_reg_tables;
	397	table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
	398	table++) {
	399	size_t size, i;
	400
	401	if (!(efx->type->revision >= table->min_revision &&
	402	efx->type->revision <= table->max_revision))
	403	continue;
	404
	405	size = min_t(size_t, table->step, 16);
	406
	407	for (i = 0; i < table->rows; i++) {
	408	switch (table->step) {
778cdaf6 BH	409	case 4: /* 32-bit SRAM */
778cdaf6 BH	410	efx_readd(efx, buf, table->offset + 4 * i);
5b98c1bf BH	411	break;
	412	case 8: /* 64-bit SRAM */
	413	efx_sram_readq(efx,
	414	efx->membase + table->offset,
	415	buf, i);
	416	break;
778cdaf6	417	case 16: /* 128-bit-readable register */
5b98c1bf BH	418	efx_reado_table(efx, buf, table->offset, i);
	419	break;
	420	case 32: /* 128-bit register, interleaved */
	421	efx_reado_table(efx, buf, table->offset, 2 * i);
	422	break;
	423	default:
	424	WARN_ON(1);
	425	return;
	426	}
	427	buf += size;
	428	}
	429	}
	430	}
cd0ecc9a BH	431
	432	/**
	433	* efx_nic_describe_stats - Describe supported statistics for ethtool
	434	* @desc: Array of &struct efx_hw_stat_desc describing the statistics
	435	* @count: Length of the @desc array
	436	* @mask: Bitmask of which elements of @desc are enabled
	437	* @names: Buffer to copy names to, or %NULL. The names are copied
	438	* starting at intervals of %ETH_GSTRING_LEN bytes.
	439	*
	440	* Returns the number of visible statistics, i.e. the number of set
	441	* bits in the first @count bits of @mask for which a name is defined.
	442	*/
	443	size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
	444	const unsigned long mask, u8 names)
	445	{
	446	size_t visible = 0;
	447	size_t index;
	448
	449	for_each_set_bit(index, mask, count) {
	450	if (desc[index].name) {
	451	if (names) {
	452	strlcpy(names, desc[index].name,
	453	ETH_GSTRING_LEN);
	454	names += ETH_GSTRING_LEN;
	455	}
	456	++visible;
	457	}
	458	}
	459
	460	return visible;
	461	}
	462
	463	/**
	464	* efx_nic_update_stats - Convert statistics DMA buffer to array of u64
	465	* @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer
	466	* layout. DMA widths of 0, 16, 32 and 64 are supported; where
	467	* the width is specified as 0 the corresponding element of
	468	* @stats is not updated.
	469	* @count: Length of the @desc array
	470	* @mask: Bitmask of which elements of @desc are enabled
	471	* @stats: Buffer to update with the converted statistics. The length
	472	* of this array must be at least the number of set bits in the
	473	* first @count bits of @mask.
	474	* @dma_buf: DMA buffer containing hardware statistics
	475	* @accumulate: If set, the converted values will be added rather than
	476	* directly stored to the corresponding elements of @stats
	477	*/
	478	void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
	479	const unsigned long *mask,
	480	u64 stats, const void dma_buf, bool accumulate)
	481	{
	482	size_t index;
	483
	484	for_each_set_bit(index, mask, count) {
	485	if (desc[index].dma_width) {
	486	const void *addr = dma_buf + desc[index].offset;
	487	u64 val;
	488
	489	switch (desc[index].dma_width) {
	490	case 16:
	491	val = le16_to_cpup((__le16 *)addr);
	492	break;
	493	case 32:
	494	val = le32_to_cpup((__le32 *)addr);
495	break;
496	case 64:
497	val = le64_to_cpup((__le64 *)addr);
498	break;
499	default:
500	WARN_ON(1);
501	val = 0;
502	break;
503	}
504
505	if (accumulate)
506	*stats += val;
507	else
508	*stats = val;
509	}
510
511	++stats;
512	}
513	}