Commit | Line | Data |
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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2005-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/socket.h> | |
12 | #include <linux/in.h> | |
5a0e3ad6 | 13 | #include <linux/slab.h> |
8ceee660 | 14 | #include <linux/ip.h> |
c47b2d9d | 15 | #include <linux/ipv6.h> |
8ceee660 BH |
16 | #include <linux/tcp.h> |
17 | #include <linux/udp.h> | |
70c71606 | 18 | #include <linux/prefetch.h> |
6eb07caf | 19 | #include <linux/moduleparam.h> |
2768935a | 20 | #include <linux/iommu.h> |
8ceee660 BH |
21 | #include <net/ip.h> |
22 | #include <net/checksum.h> | |
23 | #include "net_driver.h" | |
8ceee660 | 24 | #include "efx.h" |
add72477 | 25 | #include "filter.h" |
744093c9 | 26 | #include "nic.h" |
3273c2e8 | 27 | #include "selftest.h" |
8ceee660 BH |
28 | #include "workarounds.h" |
29 | ||
1648a23f DP |
30 | /* Preferred number of descriptors to fill at once */ |
31 | #define EFX_RX_PREFERRED_BATCH 8U | |
8ceee660 | 32 | |
2768935a DP |
33 | /* Number of RX buffers to recycle pages for. When creating the RX page recycle |
34 | * ring, this number is divided by the number of buffers per page to calculate | |
35 | * the number of pages to store in the RX page recycle ring. | |
36 | */ | |
37 | #define EFX_RECYCLE_RING_SIZE_IOMMU 4096 | |
1648a23f | 38 | #define EFX_RECYCLE_RING_SIZE_NOIOMMU (2 * EFX_RX_PREFERRED_BATCH) |
62b330ba | 39 | |
8ceee660 | 40 | /* Size of buffer allocated for skb header area. */ |
d4ef5b6f | 41 | #define EFX_SKB_HEADERS 128u |
8ceee660 | 42 | |
8ceee660 BH |
43 | /* This is the percentage fill level below which new RX descriptors |
44 | * will be added to the RX descriptor ring. | |
45 | */ | |
64235187 | 46 | static unsigned int rx_refill_threshold; |
8ceee660 | 47 | |
85740cdf BH |
48 | /* Each packet can consume up to ceil(max_frame_len / buffer_size) buffers */ |
49 | #define EFX_RX_MAX_FRAGS DIV_ROUND_UP(EFX_MAX_FRAME_LEN(EFX_MAX_MTU), \ | |
50 | EFX_RX_USR_BUF_SIZE) | |
51 | ||
8ceee660 BH |
52 | /* |
53 | * RX maximum head room required. | |
54 | * | |
85740cdf BH |
55 | * This must be at least 1 to prevent overflow, plus one packet-worth |
56 | * to allow pipelined receives. | |
8ceee660 | 57 | */ |
85740cdf | 58 | #define EFX_RXD_HEAD_ROOM (1 + EFX_RX_MAX_FRAGS) |
8ceee660 | 59 | |
b184f16b | 60 | static inline u8 *efx_rx_buf_va(struct efx_rx_buffer *buf) |
39c9cf07 | 61 | { |
b184f16b | 62 | return page_address(buf->page) + buf->page_offset; |
a526f140 SH |
63 | } |
64 | ||
43a3739d | 65 | static inline u32 efx_rx_buf_hash(struct efx_nic *efx, const u8 *eh) |
a526f140 | 66 | { |
43a3739d JC |
67 | #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) |
68 | return __le32_to_cpup((const __le32 *)(eh + efx->rx_packet_hash_offset)); | |
39c9cf07 | 69 | #else |
43a3739d | 70 | const u8 *data = eh + efx->rx_packet_hash_offset; |
0beaca2c BH |
71 | return (u32)data[0] | |
72 | (u32)data[1] << 8 | | |
73 | (u32)data[2] << 16 | | |
74 | (u32)data[3] << 24; | |
39c9cf07 BH |
75 | #endif |
76 | } | |
77 | ||
85740cdf BH |
78 | static inline struct efx_rx_buffer * |
79 | efx_rx_buf_next(struct efx_rx_queue *rx_queue, struct efx_rx_buffer *rx_buf) | |
80 | { | |
81 | if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask))) | |
82 | return efx_rx_buffer(rx_queue, 0); | |
83 | else | |
84 | return rx_buf + 1; | |
85 | } | |
86 | ||
2768935a DP |
87 | static inline void efx_sync_rx_buffer(struct efx_nic *efx, |
88 | struct efx_rx_buffer *rx_buf, | |
89 | unsigned int len) | |
90 | { | |
91 | dma_sync_single_for_cpu(&efx->pci_dev->dev, rx_buf->dma_addr, len, | |
92 | DMA_FROM_DEVICE); | |
93 | } | |
94 | ||
1648a23f DP |
95 | void efx_rx_config_page_split(struct efx_nic *efx) |
96 | { | |
2ec03014 | 97 | efx->rx_page_buf_step = ALIGN(efx->rx_dma_len + efx->rx_ip_align, |
950c54df | 98 | EFX_RX_BUF_ALIGNMENT); |
1648a23f DP |
99 | efx->rx_bufs_per_page = efx->rx_buffer_order ? 1 : |
100 | ((PAGE_SIZE - sizeof(struct efx_rx_page_state)) / | |
101 | efx->rx_page_buf_step); | |
102 | efx->rx_buffer_truesize = (PAGE_SIZE << efx->rx_buffer_order) / | |
103 | efx->rx_bufs_per_page; | |
104 | efx->rx_pages_per_batch = DIV_ROUND_UP(EFX_RX_PREFERRED_BATCH, | |
105 | efx->rx_bufs_per_page); | |
106 | } | |
107 | ||
2768935a DP |
108 | /* Check the RX page recycle ring for a page that can be reused. */ |
109 | static struct page *efx_reuse_page(struct efx_rx_queue *rx_queue) | |
110 | { | |
111 | struct efx_nic *efx = rx_queue->efx; | |
112 | struct page *page; | |
113 | struct efx_rx_page_state *state; | |
114 | unsigned index; | |
115 | ||
116 | index = rx_queue->page_remove & rx_queue->page_ptr_mask; | |
117 | page = rx_queue->page_ring[index]; | |
118 | if (page == NULL) | |
119 | return NULL; | |
120 | ||
121 | rx_queue->page_ring[index] = NULL; | |
122 | /* page_remove cannot exceed page_add. */ | |
123 | if (rx_queue->page_remove != rx_queue->page_add) | |
124 | ++rx_queue->page_remove; | |
125 | ||
126 | /* If page_count is 1 then we hold the only reference to this page. */ | |
127 | if (page_count(page) == 1) { | |
128 | ++rx_queue->page_recycle_count; | |
129 | return page; | |
130 | } else { | |
131 | state = page_address(page); | |
132 | dma_unmap_page(&efx->pci_dev->dev, state->dma_addr, | |
133 | PAGE_SIZE << efx->rx_buffer_order, | |
134 | DMA_FROM_DEVICE); | |
135 | put_page(page); | |
136 | ++rx_queue->page_recycle_failed; | |
137 | } | |
138 | ||
139 | return NULL; | |
140 | } | |
141 | ||
8ceee660 | 142 | /** |
97d48a10 | 143 | * efx_init_rx_buffers - create EFX_RX_BATCH page-based RX buffers |
8ceee660 BH |
144 | * |
145 | * @rx_queue: Efx RX queue | |
8ceee660 | 146 | * |
1648a23f DP |
147 | * This allocates a batch of pages, maps them for DMA, and populates |
148 | * struct efx_rx_buffers for each one. Return a negative error code or | |
149 | * 0 on success. If a single page can be used for multiple buffers, | |
150 | * then the page will either be inserted fully, or not at all. | |
8ceee660 | 151 | */ |
cce28794 | 152 | static int efx_init_rx_buffers(struct efx_rx_queue *rx_queue, bool atomic) |
8ceee660 BH |
153 | { |
154 | struct efx_nic *efx = rx_queue->efx; | |
f7d6f379 SH |
155 | struct efx_rx_buffer *rx_buf; |
156 | struct page *page; | |
b590ace0 | 157 | unsigned int page_offset; |
62b330ba | 158 | struct efx_rx_page_state *state; |
f7d6f379 SH |
159 | dma_addr_t dma_addr; |
160 | unsigned index, count; | |
161 | ||
1648a23f DP |
162 | count = 0; |
163 | do { | |
2768935a DP |
164 | page = efx_reuse_page(rx_queue); |
165 | if (page == NULL) { | |
cce28794 JC |
166 | page = alloc_pages(__GFP_COLD | __GFP_COMP | |
167 | (atomic ? GFP_ATOMIC : GFP_KERNEL), | |
2768935a DP |
168 | efx->rx_buffer_order); |
169 | if (unlikely(page == NULL)) | |
170 | return -ENOMEM; | |
171 | dma_addr = | |
172 | dma_map_page(&efx->pci_dev->dev, page, 0, | |
173 | PAGE_SIZE << efx->rx_buffer_order, | |
174 | DMA_FROM_DEVICE); | |
175 | if (unlikely(dma_mapping_error(&efx->pci_dev->dev, | |
176 | dma_addr))) { | |
177 | __free_pages(page, efx->rx_buffer_order); | |
178 | return -EIO; | |
179 | } | |
180 | state = page_address(page); | |
181 | state->dma_addr = dma_addr; | |
182 | } else { | |
183 | state = page_address(page); | |
184 | dma_addr = state->dma_addr; | |
8ceee660 | 185 | } |
62b330ba | 186 | |
62b330ba | 187 | dma_addr += sizeof(struct efx_rx_page_state); |
b590ace0 | 188 | page_offset = sizeof(struct efx_rx_page_state); |
f7d6f379 | 189 | |
1648a23f DP |
190 | do { |
191 | index = rx_queue->added_count & rx_queue->ptr_mask; | |
192 | rx_buf = efx_rx_buffer(rx_queue, index); | |
2ec03014 | 193 | rx_buf->dma_addr = dma_addr + efx->rx_ip_align; |
1648a23f | 194 | rx_buf->page = page; |
2ec03014 | 195 | rx_buf->page_offset = page_offset + efx->rx_ip_align; |
1648a23f | 196 | rx_buf->len = efx->rx_dma_len; |
179ea7f0 | 197 | rx_buf->flags = 0; |
1648a23f DP |
198 | ++rx_queue->added_count; |
199 | get_page(page); | |
200 | dma_addr += efx->rx_page_buf_step; | |
201 | page_offset += efx->rx_page_buf_step; | |
202 | } while (page_offset + efx->rx_page_buf_step <= PAGE_SIZE); | |
179ea7f0 BH |
203 | |
204 | rx_buf->flags = EFX_RX_BUF_LAST_IN_PAGE; | |
1648a23f | 205 | } while (++count < efx->rx_pages_per_batch); |
8ceee660 | 206 | |
8ceee660 BH |
207 | return 0; |
208 | } | |
209 | ||
2768935a DP |
210 | /* Unmap a DMA-mapped page. This function is only called for the final RX |
211 | * buffer in a page. | |
212 | */ | |
4d566063 | 213 | static void efx_unmap_rx_buffer(struct efx_nic *efx, |
2768935a | 214 | struct efx_rx_buffer *rx_buf) |
8ceee660 | 215 | { |
2768935a DP |
216 | struct page *page = rx_buf->page; |
217 | ||
218 | if (page) { | |
219 | struct efx_rx_page_state *state = page_address(page); | |
220 | dma_unmap_page(&efx->pci_dev->dev, | |
221 | state->dma_addr, | |
222 | PAGE_SIZE << efx->rx_buffer_order, | |
223 | DMA_FROM_DEVICE); | |
8ceee660 BH |
224 | } |
225 | } | |
226 | ||
9eb0a5d1 DP |
227 | static void efx_free_rx_buffers(struct efx_rx_queue *rx_queue, |
228 | struct efx_rx_buffer *rx_buf, | |
229 | unsigned int num_bufs) | |
8ceee660 | 230 | { |
9eb0a5d1 DP |
231 | do { |
232 | if (rx_buf->page) { | |
233 | put_page(rx_buf->page); | |
234 | rx_buf->page = NULL; | |
235 | } | |
236 | rx_buf = efx_rx_buf_next(rx_queue, rx_buf); | |
237 | } while (--num_bufs); | |
8ceee660 BH |
238 | } |
239 | ||
2768935a DP |
240 | /* Attempt to recycle the page if there is an RX recycle ring; the page can |
241 | * only be added if this is the final RX buffer, to prevent pages being used in | |
242 | * the descriptor ring and appearing in the recycle ring simultaneously. | |
243 | */ | |
244 | static void efx_recycle_rx_page(struct efx_channel *channel, | |
245 | struct efx_rx_buffer *rx_buf) | |
8ceee660 | 246 | { |
2768935a DP |
247 | struct page *page = rx_buf->page; |
248 | struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel); | |
249 | struct efx_nic *efx = rx_queue->efx; | |
250 | unsigned index; | |
8ceee660 | 251 | |
2768935a | 252 | /* Only recycle the page after processing the final buffer. */ |
179ea7f0 | 253 | if (!(rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE)) |
62b330ba | 254 | return; |
24455800 | 255 | |
2768935a DP |
256 | index = rx_queue->page_add & rx_queue->page_ptr_mask; |
257 | if (rx_queue->page_ring[index] == NULL) { | |
258 | unsigned read_index = rx_queue->page_remove & | |
259 | rx_queue->page_ptr_mask; | |
24455800 | 260 | |
2768935a DP |
261 | /* The next slot in the recycle ring is available, but |
262 | * increment page_remove if the read pointer currently | |
263 | * points here. | |
264 | */ | |
265 | if (read_index == index) | |
266 | ++rx_queue->page_remove; | |
267 | rx_queue->page_ring[index] = page; | |
268 | ++rx_queue->page_add; | |
269 | return; | |
270 | } | |
271 | ++rx_queue->page_recycle_full; | |
272 | efx_unmap_rx_buffer(efx, rx_buf); | |
273 | put_page(rx_buf->page); | |
24455800 SH |
274 | } |
275 | ||
2768935a DP |
276 | static void efx_fini_rx_buffer(struct efx_rx_queue *rx_queue, |
277 | struct efx_rx_buffer *rx_buf) | |
278 | { | |
279 | /* Release the page reference we hold for the buffer. */ | |
280 | if (rx_buf->page) | |
281 | put_page(rx_buf->page); | |
282 | ||
283 | /* If this is the last buffer in a page, unmap and free it. */ | |
179ea7f0 | 284 | if (rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE) { |
2768935a | 285 | efx_unmap_rx_buffer(rx_queue->efx, rx_buf); |
9eb0a5d1 | 286 | efx_free_rx_buffers(rx_queue, rx_buf, 1); |
2768935a DP |
287 | } |
288 | rx_buf->page = NULL; | |
289 | } | |
290 | ||
291 | /* Recycle the pages that are used by buffers that have just been received. */ | |
734d4e15 BH |
292 | static void efx_recycle_rx_pages(struct efx_channel *channel, |
293 | struct efx_rx_buffer *rx_buf, | |
294 | unsigned int n_frags) | |
24455800 | 295 | { |
f7d12cdc | 296 | struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel); |
24455800 | 297 | |
85740cdf | 298 | do { |
2768935a | 299 | efx_recycle_rx_page(channel, rx_buf); |
85740cdf BH |
300 | rx_buf = efx_rx_buf_next(rx_queue, rx_buf); |
301 | } while (--n_frags); | |
24455800 SH |
302 | } |
303 | ||
734d4e15 BH |
304 | static void efx_discard_rx_packet(struct efx_channel *channel, |
305 | struct efx_rx_buffer *rx_buf, | |
306 | unsigned int n_frags) | |
307 | { | |
308 | struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel); | |
309 | ||
310 | efx_recycle_rx_pages(channel, rx_buf, n_frags); | |
311 | ||
9eb0a5d1 | 312 | efx_free_rx_buffers(rx_queue, rx_buf, n_frags); |
734d4e15 BH |
313 | } |
314 | ||
8ceee660 BH |
315 | /** |
316 | * efx_fast_push_rx_descriptors - push new RX descriptors quickly | |
317 | * @rx_queue: RX descriptor queue | |
49ce9c2c | 318 | * |
8ceee660 | 319 | * This will aim to fill the RX descriptor queue up to |
da9ca505 | 320 | * @rx_queue->@max_fill. If there is insufficient atomic |
90d683af SH |
321 | * memory to do so, a slow fill will be scheduled. |
322 | * | |
323 | * The caller must provide serialisation (none is used here). In practise, | |
324 | * this means this function must run from the NAPI handler, or be called | |
325 | * when NAPI is disabled. | |
8ceee660 | 326 | */ |
cce28794 | 327 | void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue, bool atomic) |
8ceee660 | 328 | { |
1648a23f DP |
329 | struct efx_nic *efx = rx_queue->efx; |
330 | unsigned int fill_level, batch_size; | |
f7d6f379 | 331 | int space, rc = 0; |
8ceee660 | 332 | |
d8aec745 BH |
333 | if (!rx_queue->refill_enabled) |
334 | return; | |
335 | ||
90d683af | 336 | /* Calculate current fill level, and exit if we don't need to fill */ |
8ceee660 | 337 | fill_level = (rx_queue->added_count - rx_queue->removed_count); |
ecc910f5 | 338 | EFX_BUG_ON_PARANOID(fill_level > rx_queue->efx->rxq_entries); |
8ceee660 | 339 | if (fill_level >= rx_queue->fast_fill_trigger) |
24455800 | 340 | goto out; |
8ceee660 BH |
341 | |
342 | /* Record minimum fill level */ | |
b3475645 | 343 | if (unlikely(fill_level < rx_queue->min_fill)) { |
8ceee660 BH |
344 | if (fill_level) |
345 | rx_queue->min_fill = fill_level; | |
b3475645 | 346 | } |
8ceee660 | 347 | |
1648a23f | 348 | batch_size = efx->rx_pages_per_batch * efx->rx_bufs_per_page; |
da9ca505 | 349 | space = rx_queue->max_fill - fill_level; |
1648a23f | 350 | EFX_BUG_ON_PARANOID(space < batch_size); |
8ceee660 | 351 | |
62776d03 BH |
352 | netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev, |
353 | "RX queue %d fast-filling descriptor ring from" | |
97d48a10 | 354 | " level %d to level %d\n", |
ba1e8a35 | 355 | efx_rx_queue_index(rx_queue), fill_level, |
97d48a10 AR |
356 | rx_queue->max_fill); |
357 | ||
8ceee660 BH |
358 | |
359 | do { | |
cce28794 | 360 | rc = efx_init_rx_buffers(rx_queue, atomic); |
f7d6f379 SH |
361 | if (unlikely(rc)) { |
362 | /* Ensure that we don't leave the rx queue empty */ | |
363 | if (rx_queue->added_count == rx_queue->removed_count) | |
364 | efx_schedule_slow_fill(rx_queue); | |
365 | goto out; | |
8ceee660 | 366 | } |
1648a23f | 367 | } while ((space -= batch_size) >= batch_size); |
8ceee660 | 368 | |
62776d03 BH |
369 | netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev, |
370 | "RX queue %d fast-filled descriptor ring " | |
ba1e8a35 | 371 | "to level %d\n", efx_rx_queue_index(rx_queue), |
62776d03 | 372 | rx_queue->added_count - rx_queue->removed_count); |
8ceee660 BH |
373 | |
374 | out: | |
24455800 SH |
375 | if (rx_queue->notified_count != rx_queue->added_count) |
376 | efx_nic_notify_rx_desc(rx_queue); | |
8ceee660 BH |
377 | } |
378 | ||
90d683af | 379 | void efx_rx_slow_fill(unsigned long context) |
8ceee660 | 380 | { |
90d683af | 381 | struct efx_rx_queue *rx_queue = (struct efx_rx_queue *)context; |
8ceee660 | 382 | |
90d683af | 383 | /* Post an event to cause NAPI to run and refill the queue */ |
2ae75dac | 384 | efx_nic_generate_fill_event(rx_queue); |
8ceee660 | 385 | ++rx_queue->slow_fill_count; |
8ceee660 BH |
386 | } |
387 | ||
4d566063 BH |
388 | static void efx_rx_packet__check_len(struct efx_rx_queue *rx_queue, |
389 | struct efx_rx_buffer *rx_buf, | |
97d48a10 | 390 | int len) |
8ceee660 BH |
391 | { |
392 | struct efx_nic *efx = rx_queue->efx; | |
393 | unsigned max_len = rx_buf->len - efx->type->rx_buffer_padding; | |
394 | ||
395 | if (likely(len <= max_len)) | |
396 | return; | |
397 | ||
398 | /* The packet must be discarded, but this is only a fatal error | |
399 | * if the caller indicated it was | |
400 | */ | |
db339569 | 401 | rx_buf->flags |= EFX_RX_PKT_DISCARD; |
8ceee660 BH |
402 | |
403 | if ((len > rx_buf->len) && EFX_WORKAROUND_8071(efx)) { | |
62776d03 BH |
404 | if (net_ratelimit()) |
405 | netif_err(efx, rx_err, efx->net_dev, | |
406 | " RX queue %d seriously overlength " | |
407 | "RX event (0x%x > 0x%x+0x%x). Leaking\n", | |
ba1e8a35 | 408 | efx_rx_queue_index(rx_queue), len, max_len, |
62776d03 | 409 | efx->type->rx_buffer_padding); |
8ceee660 BH |
410 | efx_schedule_reset(efx, RESET_TYPE_RX_RECOVERY); |
411 | } else { | |
62776d03 BH |
412 | if (net_ratelimit()) |
413 | netif_err(efx, rx_err, efx->net_dev, | |
414 | " RX queue %d overlength RX event " | |
415 | "(0x%x > 0x%x)\n", | |
ba1e8a35 | 416 | efx_rx_queue_index(rx_queue), len, max_len); |
8ceee660 BH |
417 | } |
418 | ||
ba1e8a35 | 419 | efx_rx_queue_channel(rx_queue)->n_rx_overlength++; |
8ceee660 BH |
420 | } |
421 | ||
61321d92 BH |
422 | /* Pass a received packet up through GRO. GRO can handle pages |
423 | * regardless of checksum state and skbs with a good checksum. | |
8ceee660 | 424 | */ |
85740cdf BH |
425 | static void |
426 | efx_rx_packet_gro(struct efx_channel *channel, struct efx_rx_buffer *rx_buf, | |
427 | unsigned int n_frags, u8 *eh) | |
8ceee660 | 428 | { |
da3bc071 | 429 | struct napi_struct *napi = &channel->napi_str; |
18e1d2be | 430 | gro_result_t gro_result; |
97d48a10 | 431 | struct efx_nic *efx = channel->efx; |
97d48a10 | 432 | struct sk_buff *skb; |
8ceee660 | 433 | |
97d48a10 | 434 | skb = napi_get_frags(napi); |
85740cdf | 435 | if (unlikely(!skb)) { |
9eb0a5d1 DP |
436 | struct efx_rx_queue *rx_queue; |
437 | ||
438 | rx_queue = efx_channel_get_rx_queue(channel); | |
439 | efx_free_rx_buffers(rx_queue, rx_buf, n_frags); | |
97d48a10 AR |
440 | return; |
441 | } | |
76620aaf | 442 | |
97d48a10 | 443 | if (efx->net_dev->features & NETIF_F_RXHASH) |
c7cb38af TH |
444 | skb_set_hash(skb, efx_rx_buf_hash(efx, eh), |
445 | PKT_HASH_TYPE_L3); | |
97d48a10 AR |
446 | skb->ip_summed = ((rx_buf->flags & EFX_RX_PKT_CSUMMED) ? |
447 | CHECKSUM_UNNECESSARY : CHECKSUM_NONE); | |
8ceee660 | 448 | |
85740cdf BH |
449 | for (;;) { |
450 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
451 | rx_buf->page, rx_buf->page_offset, | |
452 | rx_buf->len); | |
453 | rx_buf->page = NULL; | |
454 | skb->len += rx_buf->len; | |
455 | if (skb_shinfo(skb)->nr_frags == n_frags) | |
456 | break; | |
3eadb7b0 | 457 | |
85740cdf BH |
458 | rx_buf = efx_rx_buf_next(&channel->rx_queue, rx_buf); |
459 | } | |
460 | ||
461 | skb->data_len = skb->len; | |
462 | skb->truesize += n_frags * efx->rx_buffer_truesize; | |
463 | ||
464 | skb_record_rx_queue(skb, channel->rx_queue.core_index); | |
8ceee660 | 465 | |
36763266 | 466 | skb_mark_napi_id(skb, &channel->napi_str); |
85740cdf | 467 | gro_result = napi_gro_frags(napi); |
97d48a10 AR |
468 | if (gro_result != GRO_DROP) |
469 | channel->irq_mod_score += 2; | |
470 | } | |
1241e951 | 471 | |
85740cdf | 472 | /* Allocate and construct an SKB around page fragments */ |
97d48a10 AR |
473 | static struct sk_buff *efx_rx_mk_skb(struct efx_channel *channel, |
474 | struct efx_rx_buffer *rx_buf, | |
85740cdf | 475 | unsigned int n_frags, |
97d48a10 AR |
476 | u8 *eh, int hdr_len) |
477 | { | |
478 | struct efx_nic *efx = channel->efx; | |
479 | struct sk_buff *skb; | |
18e1d2be | 480 | |
97d48a10 | 481 | /* Allocate an SKB to store the headers */ |
2ccd0b19 BH |
482 | skb = netdev_alloc_skb(efx->net_dev, |
483 | efx->rx_ip_align + efx->rx_prefix_size + | |
484 | hdr_len); | |
e4d112e4 EC |
485 | if (unlikely(skb == NULL)) { |
486 | atomic_inc(&efx->n_rx_noskb_drops); | |
97d48a10 | 487 | return NULL; |
e4d112e4 | 488 | } |
97d48a10 AR |
489 | |
490 | EFX_BUG_ON_PARANOID(rx_buf->len < hdr_len); | |
491 | ||
2ccd0b19 BH |
492 | memcpy(skb->data + efx->rx_ip_align, eh - efx->rx_prefix_size, |
493 | efx->rx_prefix_size + hdr_len); | |
494 | skb_reserve(skb, efx->rx_ip_align + efx->rx_prefix_size); | |
495 | __skb_put(skb, hdr_len); | |
97d48a10 | 496 | |
85740cdf | 497 | /* Append the remaining page(s) onto the frag list */ |
97d48a10 | 498 | if (rx_buf->len > hdr_len) { |
85740cdf BH |
499 | rx_buf->page_offset += hdr_len; |
500 | rx_buf->len -= hdr_len; | |
501 | ||
502 | for (;;) { | |
503 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
504 | rx_buf->page, rx_buf->page_offset, | |
505 | rx_buf->len); | |
506 | rx_buf->page = NULL; | |
507 | skb->len += rx_buf->len; | |
508 | skb->data_len += rx_buf->len; | |
509 | if (skb_shinfo(skb)->nr_frags == n_frags) | |
510 | break; | |
511 | ||
512 | rx_buf = efx_rx_buf_next(&channel->rx_queue, rx_buf); | |
513 | } | |
97d48a10 AR |
514 | } else { |
515 | __free_pages(rx_buf->page, efx->rx_buffer_order); | |
85740cdf BH |
516 | rx_buf->page = NULL; |
517 | n_frags = 0; | |
18e1d2be | 518 | } |
97d48a10 | 519 | |
85740cdf | 520 | skb->truesize += n_frags * efx->rx_buffer_truesize; |
97d48a10 AR |
521 | |
522 | /* Move past the ethernet header */ | |
523 | skb->protocol = eth_type_trans(skb, efx->net_dev); | |
524 | ||
36763266 AR |
525 | skb_mark_napi_id(skb, &channel->napi_str); |
526 | ||
97d48a10 | 527 | return skb; |
8ceee660 BH |
528 | } |
529 | ||
8ceee660 | 530 | void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index, |
85740cdf | 531 | unsigned int n_frags, unsigned int len, u16 flags) |
8ceee660 BH |
532 | { |
533 | struct efx_nic *efx = rx_queue->efx; | |
ba1e8a35 | 534 | struct efx_channel *channel = efx_rx_queue_channel(rx_queue); |
8ceee660 | 535 | struct efx_rx_buffer *rx_buf; |
8ceee660 | 536 | |
8ccf3800 AR |
537 | rx_queue->rx_packets++; |
538 | ||
8ceee660 | 539 | rx_buf = efx_rx_buffer(rx_queue, index); |
179ea7f0 | 540 | rx_buf->flags |= flags; |
8ceee660 | 541 | |
85740cdf BH |
542 | /* Validate the number of fragments and completed length */ |
543 | if (n_frags == 1) { | |
3dced740 BH |
544 | if (!(flags & EFX_RX_PKT_PREFIX_LEN)) |
545 | efx_rx_packet__check_len(rx_queue, rx_buf, len); | |
85740cdf | 546 | } else if (unlikely(n_frags > EFX_RX_MAX_FRAGS) || |
e8c68c0a JC |
547 | unlikely(len <= (n_frags - 1) * efx->rx_dma_len) || |
548 | unlikely(len > n_frags * efx->rx_dma_len) || | |
85740cdf BH |
549 | unlikely(!efx->rx_scatter)) { |
550 | /* If this isn't an explicit discard request, either | |
551 | * the hardware or the driver is broken. | |
552 | */ | |
553 | WARN_ON(!(len == 0 && rx_buf->flags & EFX_RX_PKT_DISCARD)); | |
554 | rx_buf->flags |= EFX_RX_PKT_DISCARD; | |
555 | } | |
8ceee660 | 556 | |
62776d03 | 557 | netif_vdbg(efx, rx_status, efx->net_dev, |
85740cdf | 558 | "RX queue %d received ids %x-%x len %d %s%s\n", |
ba1e8a35 | 559 | efx_rx_queue_index(rx_queue), index, |
85740cdf | 560 | (index + n_frags - 1) & rx_queue->ptr_mask, len, |
db339569 BH |
561 | (rx_buf->flags & EFX_RX_PKT_CSUMMED) ? " [SUMMED]" : "", |
562 | (rx_buf->flags & EFX_RX_PKT_DISCARD) ? " [DISCARD]" : ""); | |
8ceee660 | 563 | |
85740cdf BH |
564 | /* Discard packet, if instructed to do so. Process the |
565 | * previous receive first. | |
566 | */ | |
db339569 | 567 | if (unlikely(rx_buf->flags & EFX_RX_PKT_DISCARD)) { |
85740cdf | 568 | efx_rx_flush_packet(channel); |
734d4e15 | 569 | efx_discard_rx_packet(channel, rx_buf, n_frags); |
85740cdf | 570 | return; |
8ceee660 BH |
571 | } |
572 | ||
3dced740 | 573 | if (n_frags == 1 && !(flags & EFX_RX_PKT_PREFIX_LEN)) |
85740cdf BH |
574 | rx_buf->len = len; |
575 | ||
2768935a DP |
576 | /* Release and/or sync the DMA mapping - assumes all RX buffers |
577 | * consumed in-order per RX queue. | |
8ceee660 | 578 | */ |
2768935a | 579 | efx_sync_rx_buffer(efx, rx_buf, rx_buf->len); |
8ceee660 BH |
580 | |
581 | /* Prefetch nice and early so data will (hopefully) be in cache by | |
582 | * the time we look at it. | |
583 | */ | |
5036b7c7 | 584 | prefetch(efx_rx_buf_va(rx_buf)); |
8ceee660 | 585 | |
43a3739d JC |
586 | rx_buf->page_offset += efx->rx_prefix_size; |
587 | rx_buf->len -= efx->rx_prefix_size; | |
85740cdf BH |
588 | |
589 | if (n_frags > 1) { | |
590 | /* Release/sync DMA mapping for additional fragments. | |
591 | * Fix length for last fragment. | |
592 | */ | |
593 | unsigned int tail_frags = n_frags - 1; | |
594 | ||
595 | for (;;) { | |
596 | rx_buf = efx_rx_buf_next(rx_queue, rx_buf); | |
597 | if (--tail_frags == 0) | |
598 | break; | |
e8c68c0a | 599 | efx_sync_rx_buffer(efx, rx_buf, efx->rx_dma_len); |
85740cdf | 600 | } |
e8c68c0a | 601 | rx_buf->len = len - (n_frags - 1) * efx->rx_dma_len; |
2768935a | 602 | efx_sync_rx_buffer(efx, rx_buf, rx_buf->len); |
85740cdf | 603 | } |
b74e3e8c | 604 | |
734d4e15 | 605 | /* All fragments have been DMA-synced, so recycle pages. */ |
2768935a | 606 | rx_buf = efx_rx_buffer(rx_queue, index); |
734d4e15 | 607 | efx_recycle_rx_pages(channel, rx_buf, n_frags); |
2768935a | 608 | |
8ceee660 BH |
609 | /* Pipeline receives so that we give time for packet headers to be |
610 | * prefetched into cache. | |
611 | */ | |
ff734ef4 | 612 | efx_rx_flush_packet(channel); |
85740cdf BH |
613 | channel->rx_pkt_n_frags = n_frags; |
614 | channel->rx_pkt_index = index; | |
8ceee660 BH |
615 | } |
616 | ||
97d48a10 | 617 | static void efx_rx_deliver(struct efx_channel *channel, u8 *eh, |
85740cdf BH |
618 | struct efx_rx_buffer *rx_buf, |
619 | unsigned int n_frags) | |
1ddceb4c BH |
620 | { |
621 | struct sk_buff *skb; | |
97d48a10 | 622 | u16 hdr_len = min_t(u16, rx_buf->len, EFX_SKB_HEADERS); |
1ddceb4c | 623 | |
85740cdf | 624 | skb = efx_rx_mk_skb(channel, rx_buf, n_frags, eh, hdr_len); |
97d48a10 | 625 | if (unlikely(skb == NULL)) { |
9eb0a5d1 DP |
626 | struct efx_rx_queue *rx_queue; |
627 | ||
628 | rx_queue = efx_channel_get_rx_queue(channel); | |
629 | efx_free_rx_buffers(rx_queue, rx_buf, n_frags); | |
97d48a10 AR |
630 | return; |
631 | } | |
632 | skb_record_rx_queue(skb, channel->rx_queue.core_index); | |
1ddceb4c BH |
633 | |
634 | /* Set the SKB flags */ | |
635 | skb_checksum_none_assert(skb); | |
c99dffc4 JC |
636 | if (likely(rx_buf->flags & EFX_RX_PKT_CSUMMED)) |
637 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1ddceb4c | 638 | |
bd9a265d JC |
639 | efx_rx_skb_attach_timestamp(channel, skb); |
640 | ||
c31e5f9f | 641 | if (channel->type->receive_skb) |
4a74dc65 | 642 | if (channel->type->receive_skb(channel, skb)) |
97d48a10 | 643 | return; |
4a74dc65 BH |
644 | |
645 | /* Pass the packet up */ | |
646 | netif_receive_skb(skb); | |
1ddceb4c BH |
647 | } |
648 | ||
8ceee660 | 649 | /* Handle a received packet. Second half: Touches packet payload. */ |
85740cdf | 650 | void __efx_rx_packet(struct efx_channel *channel) |
8ceee660 BH |
651 | { |
652 | struct efx_nic *efx = channel->efx; | |
85740cdf BH |
653 | struct efx_rx_buffer *rx_buf = |
654 | efx_rx_buffer(&channel->rx_queue, channel->rx_pkt_index); | |
b74e3e8c | 655 | u8 *eh = efx_rx_buf_va(rx_buf); |
604f6049 | 656 | |
3dced740 BH |
657 | /* Read length from the prefix if necessary. This already |
658 | * excludes the length of the prefix itself. | |
659 | */ | |
660 | if (rx_buf->flags & EFX_RX_PKT_PREFIX_LEN) | |
661 | rx_buf->len = le16_to_cpup((__le16 *) | |
662 | (eh + efx->rx_packet_len_offset)); | |
663 | ||
3273c2e8 BH |
664 | /* If we're in loopback test, then pass the packet directly to the |
665 | * loopback layer, and free the rx_buf here | |
666 | */ | |
667 | if (unlikely(efx->loopback_selftest)) { | |
9eb0a5d1 DP |
668 | struct efx_rx_queue *rx_queue; |
669 | ||
a526f140 | 670 | efx_loopback_rx_packet(efx, eh, rx_buf->len); |
9eb0a5d1 DP |
671 | rx_queue = efx_channel_get_rx_queue(channel); |
672 | efx_free_rx_buffers(rx_queue, rx_buf, | |
673 | channel->rx_pkt_n_frags); | |
85740cdf | 674 | goto out; |
3273c2e8 BH |
675 | } |
676 | ||
abfe9039 | 677 | if (unlikely(!(efx->net_dev->features & NETIF_F_RXCSUM))) |
db339569 | 678 | rx_buf->flags &= ~EFX_RX_PKT_CSUMMED; |
ab3cf6d0 | 679 | |
36763266 AR |
680 | if ((rx_buf->flags & EFX_RX_PKT_TCP) && !channel->type->receive_skb && |
681 | !efx_channel_busy_polling(channel)) | |
85740cdf | 682 | efx_rx_packet_gro(channel, rx_buf, channel->rx_pkt_n_frags, eh); |
1ddceb4c | 683 | else |
85740cdf BH |
684 | efx_rx_deliver(channel, eh, rx_buf, channel->rx_pkt_n_frags); |
685 | out: | |
686 | channel->rx_pkt_n_frags = 0; | |
8ceee660 BH |
687 | } |
688 | ||
689 | int efx_probe_rx_queue(struct efx_rx_queue *rx_queue) | |
690 | { | |
691 | struct efx_nic *efx = rx_queue->efx; | |
ecc910f5 | 692 | unsigned int entries; |
8ceee660 BH |
693 | int rc; |
694 | ||
ecc910f5 SH |
695 | /* Create the smallest power-of-two aligned ring */ |
696 | entries = max(roundup_pow_of_two(efx->rxq_entries), EFX_MIN_DMAQ_SIZE); | |
697 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE); | |
698 | rx_queue->ptr_mask = entries - 1; | |
699 | ||
62776d03 | 700 | netif_dbg(efx, probe, efx->net_dev, |
ecc910f5 SH |
701 | "creating RX queue %d size %#x mask %#x\n", |
702 | efx_rx_queue_index(rx_queue), efx->rxq_entries, | |
703 | rx_queue->ptr_mask); | |
8ceee660 BH |
704 | |
705 | /* Allocate RX buffers */ | |
c2e4e25a | 706 | rx_queue->buffer = kcalloc(entries, sizeof(*rx_queue->buffer), |
ecc910f5 | 707 | GFP_KERNEL); |
8831da7b BH |
708 | if (!rx_queue->buffer) |
709 | return -ENOMEM; | |
8ceee660 | 710 | |
152b6a62 | 711 | rc = efx_nic_probe_rx(rx_queue); |
8831da7b BH |
712 | if (rc) { |
713 | kfree(rx_queue->buffer); | |
714 | rx_queue->buffer = NULL; | |
715 | } | |
2768935a | 716 | |
8ceee660 BH |
717 | return rc; |
718 | } | |
719 | ||
debd0034 | 720 | static void efx_init_rx_recycle_ring(struct efx_nic *efx, |
721 | struct efx_rx_queue *rx_queue) | |
2768935a DP |
722 | { |
723 | unsigned int bufs_in_recycle_ring, page_ring_size; | |
724 | ||
725 | /* Set the RX recycle ring size */ | |
726 | #ifdef CONFIG_PPC64 | |
727 | bufs_in_recycle_ring = EFX_RECYCLE_RING_SIZE_IOMMU; | |
728 | #else | |
636d73da | 729 | if (iommu_present(&pci_bus_type)) |
2768935a DP |
730 | bufs_in_recycle_ring = EFX_RECYCLE_RING_SIZE_IOMMU; |
731 | else | |
732 | bufs_in_recycle_ring = EFX_RECYCLE_RING_SIZE_NOIOMMU; | |
733 | #endif /* CONFIG_PPC64 */ | |
734 | ||
735 | page_ring_size = roundup_pow_of_two(bufs_in_recycle_ring / | |
736 | efx->rx_bufs_per_page); | |
737 | rx_queue->page_ring = kcalloc(page_ring_size, | |
738 | sizeof(*rx_queue->page_ring), GFP_KERNEL); | |
739 | rx_queue->page_ptr_mask = page_ring_size - 1; | |
740 | } | |
741 | ||
bc3c90a2 | 742 | void efx_init_rx_queue(struct efx_rx_queue *rx_queue) |
8ceee660 | 743 | { |
ecc910f5 | 744 | struct efx_nic *efx = rx_queue->efx; |
64235187 | 745 | unsigned int max_fill, trigger, max_trigger; |
8ceee660 | 746 | |
62776d03 | 747 | netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev, |
ba1e8a35 | 748 | "initialising RX queue %d\n", efx_rx_queue_index(rx_queue)); |
8ceee660 BH |
749 | |
750 | /* Initialise ptr fields */ | |
751 | rx_queue->added_count = 0; | |
752 | rx_queue->notified_count = 0; | |
753 | rx_queue->removed_count = 0; | |
754 | rx_queue->min_fill = -1U; | |
2768935a DP |
755 | efx_init_rx_recycle_ring(efx, rx_queue); |
756 | ||
757 | rx_queue->page_remove = 0; | |
758 | rx_queue->page_add = rx_queue->page_ptr_mask + 1; | |
759 | rx_queue->page_recycle_count = 0; | |
760 | rx_queue->page_recycle_failed = 0; | |
761 | rx_queue->page_recycle_full = 0; | |
8ceee660 BH |
762 | |
763 | /* Initialise limit fields */ | |
ecc910f5 | 764 | max_fill = efx->rxq_entries - EFX_RXD_HEAD_ROOM; |
1648a23f DP |
765 | max_trigger = |
766 | max_fill - efx->rx_pages_per_batch * efx->rx_bufs_per_page; | |
64235187 DR |
767 | if (rx_refill_threshold != 0) { |
768 | trigger = max_fill * min(rx_refill_threshold, 100U) / 100U; | |
769 | if (trigger > max_trigger) | |
770 | trigger = max_trigger; | |
771 | } else { | |
772 | trigger = max_trigger; | |
773 | } | |
8ceee660 BH |
774 | |
775 | rx_queue->max_fill = max_fill; | |
776 | rx_queue->fast_fill_trigger = trigger; | |
d8aec745 | 777 | rx_queue->refill_enabled = true; |
8ceee660 BH |
778 | |
779 | /* Set up RX descriptor ring */ | |
152b6a62 | 780 | efx_nic_init_rx(rx_queue); |
8ceee660 BH |
781 | } |
782 | ||
783 | void efx_fini_rx_queue(struct efx_rx_queue *rx_queue) | |
784 | { | |
785 | int i; | |
2768935a | 786 | struct efx_nic *efx = rx_queue->efx; |
8ceee660 BH |
787 | struct efx_rx_buffer *rx_buf; |
788 | ||
62776d03 | 789 | netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev, |
ba1e8a35 | 790 | "shutting down RX queue %d\n", efx_rx_queue_index(rx_queue)); |
8ceee660 | 791 | |
90d683af | 792 | del_timer_sync(&rx_queue->slow_fill); |
8ceee660 | 793 | |
2768935a | 794 | /* Release RX buffers from the current read ptr to the write ptr */ |
8ceee660 | 795 | if (rx_queue->buffer) { |
2768935a DP |
796 | for (i = rx_queue->removed_count; i < rx_queue->added_count; |
797 | i++) { | |
798 | unsigned index = i & rx_queue->ptr_mask; | |
799 | rx_buf = efx_rx_buffer(rx_queue, index); | |
8ceee660 BH |
800 | efx_fini_rx_buffer(rx_queue, rx_buf); |
801 | } | |
802 | } | |
2768935a DP |
803 | |
804 | /* Unmap and release the pages in the recycle ring. Remove the ring. */ | |
805 | for (i = 0; i <= rx_queue->page_ptr_mask; i++) { | |
806 | struct page *page = rx_queue->page_ring[i]; | |
807 | struct efx_rx_page_state *state; | |
808 | ||
809 | if (page == NULL) | |
810 | continue; | |
811 | ||
812 | state = page_address(page); | |
813 | dma_unmap_page(&efx->pci_dev->dev, state->dma_addr, | |
814 | PAGE_SIZE << efx->rx_buffer_order, | |
815 | DMA_FROM_DEVICE); | |
816 | put_page(page); | |
817 | } | |
818 | kfree(rx_queue->page_ring); | |
819 | rx_queue->page_ring = NULL; | |
8ceee660 BH |
820 | } |
821 | ||
822 | void efx_remove_rx_queue(struct efx_rx_queue *rx_queue) | |
823 | { | |
62776d03 | 824 | netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev, |
ba1e8a35 | 825 | "destroying RX queue %d\n", efx_rx_queue_index(rx_queue)); |
8ceee660 | 826 | |
152b6a62 | 827 | efx_nic_remove_rx(rx_queue); |
8ceee660 BH |
828 | |
829 | kfree(rx_queue->buffer); | |
830 | rx_queue->buffer = NULL; | |
8ceee660 BH |
831 | } |
832 | ||
8ceee660 | 833 | |
8ceee660 BH |
834 | module_param(rx_refill_threshold, uint, 0444); |
835 | MODULE_PARM_DESC(rx_refill_threshold, | |
64235187 | 836 | "RX descriptor ring refill threshold (%)"); |
8ceee660 | 837 | |
add72477 BH |
838 | #ifdef CONFIG_RFS_ACCEL |
839 | ||
840 | int efx_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb, | |
841 | u16 rxq_index, u32 flow_id) | |
842 | { | |
843 | struct efx_nic *efx = netdev_priv(net_dev); | |
844 | struct efx_channel *channel; | |
845 | struct efx_filter_spec spec; | |
add72477 | 846 | const __be16 *ports; |
c47b2d9d | 847 | __be16 ether_type; |
add72477 BH |
848 | int nhoff; |
849 | int rc; | |
850 | ||
c47b2d9d BH |
851 | /* The core RPS/RFS code has already parsed and validated |
852 | * VLAN, IP and transport headers. We assume they are in the | |
853 | * header area. | |
854 | */ | |
add72477 BH |
855 | |
856 | if (skb->protocol == htons(ETH_P_8021Q)) { | |
c47b2d9d BH |
857 | const struct vlan_hdr *vh = |
858 | (const struct vlan_hdr *)skb->data; | |
add72477 | 859 | |
c47b2d9d BH |
860 | /* We can't filter on the IP 5-tuple and the vlan |
861 | * together, so just strip the vlan header and filter | |
862 | * on the IP part. | |
add72477 | 863 | */ |
c47b2d9d BH |
864 | EFX_BUG_ON_PARANOID(skb_headlen(skb) < sizeof(*vh)); |
865 | ether_type = vh->h_vlan_encapsulated_proto; | |
866 | nhoff = sizeof(struct vlan_hdr); | |
867 | } else { | |
868 | ether_type = skb->protocol; | |
869 | nhoff = 0; | |
add72477 BH |
870 | } |
871 | ||
c47b2d9d | 872 | if (ether_type != htons(ETH_P_IP) && ether_type != htons(ETH_P_IPV6)) |
add72477 | 873 | return -EPROTONOSUPPORT; |
add72477 BH |
874 | |
875 | efx_filter_init_rx(&spec, EFX_FILTER_PRI_HINT, | |
876 | efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0, | |
877 | rxq_index); | |
c47b2d9d BH |
878 | spec.match_flags = |
879 | EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO | | |
880 | EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT | | |
881 | EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT; | |
882 | spec.ether_type = ether_type; | |
883 | ||
884 | if (ether_type == htons(ETH_P_IP)) { | |
885 | const struct iphdr *ip = | |
886 | (const struct iphdr *)(skb->data + nhoff); | |
887 | ||
888 | EFX_BUG_ON_PARANOID(skb_headlen(skb) < nhoff + sizeof(*ip)); | |
889 | if (ip_is_fragment(ip)) | |
890 | return -EPROTONOSUPPORT; | |
891 | spec.ip_proto = ip->protocol; | |
892 | spec.rem_host[0] = ip->saddr; | |
893 | spec.loc_host[0] = ip->daddr; | |
894 | EFX_BUG_ON_PARANOID(skb_headlen(skb) < nhoff + 4 * ip->ihl + 4); | |
895 | ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl); | |
896 | } else { | |
897 | const struct ipv6hdr *ip6 = | |
898 | (const struct ipv6hdr *)(skb->data + nhoff); | |
899 | ||
900 | EFX_BUG_ON_PARANOID(skb_headlen(skb) < | |
901 | nhoff + sizeof(*ip6) + 4); | |
902 | spec.ip_proto = ip6->nexthdr; | |
903 | memcpy(spec.rem_host, &ip6->saddr, sizeof(ip6->saddr)); | |
904 | memcpy(spec.loc_host, &ip6->daddr, sizeof(ip6->daddr)); | |
905 | ports = (const __be16 *)(ip6 + 1); | |
906 | } | |
907 | ||
908 | spec.rem_port = ports[0]; | |
909 | spec.loc_port = ports[1]; | |
add72477 BH |
910 | |
911 | rc = efx->type->filter_rfs_insert(efx, &spec); | |
912 | if (rc < 0) | |
913 | return rc; | |
914 | ||
915 | /* Remember this so we can check whether to expire the filter later */ | |
916 | efx->rps_flow_id[rc] = flow_id; | |
917 | channel = efx_get_channel(efx, skb_get_rx_queue(skb)); | |
918 | ++channel->rfs_filters_added; | |
919 | ||
c47b2d9d BH |
920 | if (ether_type == htons(ETH_P_IP)) |
921 | netif_info(efx, rx_status, efx->net_dev, | |
922 | "steering %s %pI4:%u:%pI4:%u to queue %u [flow %u filter %d]\n", | |
923 | (spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP", | |
924 | spec.rem_host, ntohs(ports[0]), spec.loc_host, | |
925 | ntohs(ports[1]), rxq_index, flow_id, rc); | |
926 | else | |
927 | netif_info(efx, rx_status, efx->net_dev, | |
928 | "steering %s [%pI6]:%u:[%pI6]:%u to queue %u [flow %u filter %d]\n", | |
929 | (spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP", | |
930 | spec.rem_host, ntohs(ports[0]), spec.loc_host, | |
931 | ntohs(ports[1]), rxq_index, flow_id, rc); | |
add72477 BH |
932 | |
933 | return rc; | |
934 | } | |
935 | ||
936 | bool __efx_filter_rfs_expire(struct efx_nic *efx, unsigned int quota) | |
937 | { | |
938 | bool (*expire_one)(struct efx_nic *efx, u32 flow_id, unsigned int index); | |
939 | unsigned int index, size; | |
940 | u32 flow_id; | |
941 | ||
942 | if (!spin_trylock_bh(&efx->filter_lock)) | |
943 | return false; | |
944 | ||
945 | expire_one = efx->type->filter_rfs_expire_one; | |
946 | index = efx->rps_expire_index; | |
947 | size = efx->type->max_rx_ip_filters; | |
948 | while (quota--) { | |
949 | flow_id = efx->rps_flow_id[index]; | |
950 | if (expire_one(efx, flow_id, index)) | |
951 | netif_info(efx, rx_status, efx->net_dev, | |
952 | "expired filter %d [flow %u]\n", | |
953 | index, flow_id); | |
954 | if (++index == size) | |
955 | index = 0; | |
956 | } | |
957 | efx->rps_expire_index = index; | |
958 | ||
959 | spin_unlock_bh(&efx->filter_lock); | |
960 | return true; | |
961 | } | |
962 | ||
963 | #endif /* CONFIG_RFS_ACCEL */ | |
b883d0bd BH |
964 | |
965 | /** | |
966 | * efx_filter_is_mc_recipient - test whether spec is a multicast recipient | |
967 | * @spec: Specification to test | |
968 | * | |
969 | * Return: %true if the specification is a non-drop RX filter that | |
970 | * matches a local MAC address I/G bit value of 1 or matches a local | |
971 | * IPv4 or IPv6 address value in the respective multicast address | |
972 | * range. Otherwise %false. | |
973 | */ | |
974 | bool efx_filter_is_mc_recipient(const struct efx_filter_spec *spec) | |
975 | { | |
976 | if (!(spec->flags & EFX_FILTER_FLAG_RX) || | |
977 | spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP) | |
978 | return false; | |
979 | ||
980 | if (spec->match_flags & | |
981 | (EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_LOC_MAC_IG) && | |
982 | is_multicast_ether_addr(spec->loc_mac)) | |
983 | return true; | |
984 | ||
985 | if ((spec->match_flags & | |
986 | (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) == | |
987 | (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) { | |
988 | if (spec->ether_type == htons(ETH_P_IP) && | |
989 | ipv4_is_multicast(spec->loc_host[0])) | |
990 | return true; | |
991 | if (spec->ether_type == htons(ETH_P_IPV6) && | |
992 | ((const u8 *)spec->loc_host)[0] == 0xff) | |
993 | return true; | |
994 | } | |
995 | ||
996 | return false; | |
997 | } |