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sfc: Remove efx_nic_type::push_multicast_hash operation
[deliverable/linux.git] / drivers / net / ethernet / sfc / siena.c
CommitLineData
afd4aea0
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
0a6f40c6 4 * Copyright 2006-2010 Solarflare Communications Inc.
afd4aea0
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
5a0e3ad6 15#include <linux/slab.h>
d614cfbc 16#include <linux/random.h>
afd4aea0
BH		 17#include "net_driver.h"
18#include "bitfield.h"
19#include "efx.h"
20#include "nic.h"
afd4aea0
BH		 21#include "spi.h"
22#include "regs.h"
23#include "io.h"
24#include "phy.h"
25#include "workarounds.h"
26#include "mcdi.h"
27#include "mcdi_pcol.h"
28
29/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
30
31static void siena_init_wol(struct efx_nic *efx);
32
33
34static void siena_push_irq_moderation(struct efx_channel *channel)
35{
36 efx_dword_t timer_cmd;
37
9e393b30
BH		 38 BUILD_BUG_ON(EFX_IRQ_MOD_MAX > (1 << FRF_CZ_TC_TIMER_VAL_WIDTH));
39
afd4aea0
BH		 40 if (channel->irq_moderation)
41 EFX_POPULATE_DWORD_2(timer_cmd,
42 FRF_CZ_TC_TIMER_MODE,
43 FFE_CZ_TIMER_MODE_INT_HLDOFF,
44 FRF_CZ_TC_TIMER_VAL,
45 channel->irq_moderation - 1);
46 else
47 EFX_POPULATE_DWORD_2(timer_cmd,
48 FRF_CZ_TC_TIMER_MODE,
49 FFE_CZ_TIMER_MODE_DIS,
50 FRF_CZ_TC_TIMER_VAL, 0);
51 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
52 channel->channel);
53}
54
afd4aea0
BH		 55static int siena_mdio_write(struct net_device *net_dev,
56 int prtad, int devad, u16 addr, u16 value)
57{
58 struct efx_nic *efx = netdev_priv(net_dev);
59 uint32_t status;
60 int rc;
61
62 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
63 addr, value, &status);
64 if (rc)
65 return rc;
66 if (status != MC_CMD_MDIO_STATUS_GOOD)
67 return -EIO;
68
69 return 0;
70}
71
72static int siena_mdio_read(struct net_device *net_dev,
73 int prtad, int devad, u16 addr)
74{
75 struct efx_nic *efx = netdev_priv(net_dev);
76 uint16_t value;
77 uint32_t status;
78 int rc;
79
80 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
81 addr, &value, &status);
82 if (rc)
83 return rc;
84 if (status != MC_CMD_MDIO_STATUS_GOOD)
85 return -EIO;
86
87 return (int)value;
88}
89
90/* This call is responsible for hooking in the MAC and PHY operations */
91static int siena_probe_port(struct efx_nic *efx)
92{
93 int rc;
94
95 /* Hook in PHY operations table */
96 efx->phy_op = &efx_mcdi_phy_ops;
97
98 /* Set up MDIO structure for PHY */
99 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
100 efx->mdio.mdio_read = siena_mdio_read;
101 efx->mdio.mdio_write = siena_mdio_write;
102
7a6b8f6f 103 /* Fill out MDIO structure, loopback modes, and initial link state */
afd4aea0
BH		 104 rc = efx->phy_op->probe(efx);
105 if (rc != 0)
106 return rc;
107
afd4aea0
BH		 108 /* Allocate buffer for stats */
109 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
110 MC_CMD_MAC_NSTATS * sizeof(u64));
111 if (rc)
112 return rc;
62776d03
BH		 113 netif_dbg(efx, probe, efx->net_dev,
114 "stats buffer at %llx (virt %p phys %llx)\n",
115 (u64)efx->stats_buffer.dma_addr,
116 efx->stats_buffer.addr,
117 (u64)virt_to_phys(efx->stats_buffer.addr));
afd4aea0
BH		 118
119 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
120
121 return 0;
122}
123
d215697f 124static void siena_remove_port(struct efx_nic *efx)
afd4aea0 125{
ff3b00a0 126 efx->phy_op->remove(efx);
afd4aea0
BH		 127 efx_nic_free_buffer(efx, &efx->stats_buffer);
128}
129
130static const struct efx_nic_register_test siena_register_tests[] = {
131 { FR_AZ_ADR_REGION,
4cddca54 132 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
afd4aea0
BH		 133 { FR_CZ_USR_EV_CFG,
134 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
135 { FR_AZ_RX_CFG,
136 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
137 { FR_AZ_TX_CFG,
138 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
139 { FR_AZ_TX_RESERVED,
140 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
141 { FR_AZ_SRM_TX_DC_CFG,
142 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
143 { FR_AZ_RX_DC_CFG,
144 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
145 { FR_AZ_RX_DC_PF_WM,
146 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
147 { FR_BZ_DP_CTRL,
148 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
149 { FR_BZ_RX_RSS_TKEY,
150 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
151 { FR_CZ_RX_RSS_IPV6_REG1,
152 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
153 { FR_CZ_RX_RSS_IPV6_REG2,
154 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
155 { FR_CZ_RX_RSS_IPV6_REG3,
156 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
157};
158
159static int siena_test_registers(struct efx_nic *efx)
160{
161 return efx_nic_test_registers(efx, siena_register_tests,
162 ARRAY_SIZE(siena_register_tests));
163}
164
165/**************************************************************************
166 *
167 * Device reset
168 *
169 **************************************************************************
170 */
171
0e2a9c7c
BH		 172static enum reset_type siena_map_reset_reason(enum reset_type reason)
173{
174 return RESET_TYPE_ALL;
175}
176
177static int siena_map_reset_flags(u32 *flags)
178{
179 enum {
180 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
181 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
182 ETH_RESET_PHY),
183 SIENA_RESET_MC = (SIENA_RESET_PORT |
184 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
185 };
186
187 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
188 *flags &= ~SIENA_RESET_MC;
189 return RESET_TYPE_WORLD;
190 }
191
192 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
193 *flags &= ~SIENA_RESET_PORT;
194 return RESET_TYPE_ALL;
195 }
196
197 /* no invisible reset implemented */
198
199 return -EINVAL;
200}
201
afd4aea0
BH		 202static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
203{
8b2103ad
SH		 204 int rc;
205
206 /* Recover from a failed assertion pre-reset */
207 rc = efx_mcdi_handle_assertion(efx);
208 if (rc)
209 return rc;
afd4aea0
BH		 210
211 if (method == RESET_TYPE_WORLD)
212 return efx_mcdi_reset_mc(efx);
213 else
214 return efx_mcdi_reset_port(efx);
215}
216
217static int siena_probe_nvconfig(struct efx_nic *efx)
218{
7e300bc8 219 return efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL);
afd4aea0
BH		 220}
221
222static int siena_probe_nic(struct efx_nic *efx)
223{
224 struct siena_nic_data *nic_data;
3db1cd5c 225 bool already_attached = false;
d42a8f46 226 efx_oword_t reg;
afd4aea0
BH		 227 int rc;
228
229 /* Allocate storage for hardware specific data */
230 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
231 if (!nic_data)
232 return -ENOMEM;
233 efx->nic_data = nic_data;
234
235 if (efx_nic_fpga_ver(efx) != 0) {
62776d03
BH		 236 netif_err(efx, probe, efx->net_dev,
237 "Siena FPGA not supported\n");
afd4aea0
BH		 238 rc = -ENODEV;
239 goto fail1;
240 }
241
d42a8f46 242 efx_reado(efx, &reg, FR_AZ_CS_DEBUG);
3df95ce9 243 efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
d42a8f46 244
afd4aea0
BH		 245 efx_mcdi_init(efx);
246
247 /* Recover from a failed assertion before probing */
248 rc = efx_mcdi_handle_assertion(efx);
249 if (rc)
86c432ca 250 goto fail1;
afd4aea0 251
afd4aea0
BH		 252 /* Let the BMC know that the driver is now in charge of link and
253 * filter settings. We must do this before we reset the NIC */
254 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
255 if (rc) {
62776d03
BH		 256 netif_err(efx, probe, efx->net_dev,
257 "Unable to register driver with MCPU\n");
afd4aea0
BH		 258 goto fail2;
259 }
260 if (already_attached)
261 /* Not a fatal error */
62776d03
BH		 262 netif_err(efx, probe, efx->net_dev,
263 "Host already registered with MCPU\n");
afd4aea0
BH		 264
265 /* Now we can reset the NIC */
266 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
267 if (rc) {
62776d03 268 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
afd4aea0
BH		 269 goto fail3;
270 }
271
272 siena_init_wol(efx);
273
274 /* Allocate memory for INT_KER */
275 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
276 if (rc)
277 goto fail4;
278 BUG_ON(efx->irq_status.dma_addr & 0x0f);
279
62776d03
BH		 280 netif_dbg(efx, probe, efx->net_dev,
281 "INT_KER at %llx (virt %p phys %llx)\n",
282 (unsigned long long)efx->irq_status.dma_addr,
283 efx->irq_status.addr,
284 (unsigned long long)virt_to_phys(efx->irq_status.addr));
afd4aea0
BH		 285
286 /* Read in the non-volatile configuration */
287 rc = siena_probe_nvconfig(efx);
288 if (rc == -EINVAL) {
62776d03
BH		 289 netif_err(efx, probe, efx->net_dev,
290 "NVRAM is invalid therefore using defaults\n");
afd4aea0
BH		 291 efx->phy_type = PHY_TYPE_NONE;
292 efx->mdio.prtad = MDIO_PRTAD_NONE;
293 } else if (rc) {
294 goto fail5;
295 }
296
297 return 0;
298
299fail5:
300 efx_nic_free_buffer(efx, &efx->irq_status);
301fail4:
302fail3:
303 efx_mcdi_drv_attach(efx, false, NULL);
304fail2:
305fail1:
306 kfree(efx->nic_data);
307 return rc;
308}
309
310/* This call performs hardware-specific global initialisation, such as
311 * defining the descriptor cache sizes and number of RSS channels.
312 * It does not set up any buffers, descriptor rings or event queues.
313 */
314static int siena_init_nic(struct efx_nic *efx)
315{
316 efx_oword_t temp;
317 int rc;
318
319 /* Recover from a failed assertion post-reset */
320 rc = efx_mcdi_handle_assertion(efx);
321 if (rc)
322 return rc;
323
324 /* Squash TX of packets of 16 bytes or less */
325 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
326 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
327 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
328
329 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
330 * descriptors (which is bad).
331 */
332 efx_reado(efx, &temp, FR_AZ_TX_CFG);
333 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
334 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
335 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
336
337 efx_reado(efx, &temp, FR_AZ_RX_CFG);
338 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
339 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
477e54eb
BH		 340 /* Enable hash insertion. This is broken for the 'Falcon' hash
341 * if IPv6 hashing is also enabled, so also select Toeplitz
342 * TCP/IPv4 and IPv4 hashes. */
343 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
344 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
345 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
afd4aea0
BH		 346 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
347
477e54eb
BH		 348 /* Set hash key for IPv4 */
349 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
350 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
351
d614cfbc 352 /* Enable IPv6 RSS */
5d3a6fca 353 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
d614cfbc
BH		 354 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
355 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
5d3a6fca 356 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
d614cfbc 357 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
5d3a6fca 358 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
d614cfbc
BH		 359 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
360 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
361 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
5d3a6fca 362 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
d614cfbc
BH		 363 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
364 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
365
afd4aea0
BH		 366 /* Enable event logging */
367 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
368 if (rc)
369 return rc;
370
371 /* Set destination of both TX and RX Flush events */
372 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
373 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
374
375 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
376 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
377
378 efx_nic_init_common(efx);
379 return 0;
380}
381
382static void siena_remove_nic(struct efx_nic *efx)
383{
384 efx_nic_free_buffer(efx, &efx->irq_status);
385
386 siena_reset_hw(efx, RESET_TYPE_ALL);
387
388 /* Relinquish the device back to the BMC */
389 if (efx_nic_has_mc(efx))
390 efx_mcdi_drv_attach(efx, false, NULL);
391
392 /* Tear down the private nic state */
86c432ca 393 kfree(efx->nic_data);
afd4aea0
BH		 394 efx->nic_data = NULL;
395}
396
a659b2a9 397#define STATS_GENERATION_INVALID ((__force __le64)(-1))
afd4aea0
BH		 398
399static int siena_try_update_nic_stats(struct efx_nic *efx)
400{
a659b2a9 401 __le64 *dma_stats;
afd4aea0 402 struct efx_mac_stats *mac_stats;
a659b2a9 403 __le64 generation_start, generation_end;
afd4aea0
BH		 404
405 mac_stats = &efx->mac_stats;
43d620c8 406 dma_stats = efx->stats_buffer.addr;
afd4aea0
BH		 407
408 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
409 if (generation_end == STATS_GENERATION_INVALID)
410 return 0;
411 rmb();
412
413#define MAC_STAT(M, D) \
a659b2a9 414 mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D])
afd4aea0
BH		 415
416 MAC_STAT(tx_bytes, TX_BYTES);
417 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
418 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
419 mac_stats->tx_bad_bytes);
420 MAC_STAT(tx_packets, TX_PKTS);
421 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
422 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
423 MAC_STAT(tx_control, TX_CONTROL_PKTS);
424 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
425 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
426 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
427 MAC_STAT(tx_lt64, TX_LT64_PKTS);
428 MAC_STAT(tx_64, TX_64_PKTS);
429 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
430 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
431 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
432 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
433 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
434 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
435 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
436 mac_stats->tx_collision = 0;
437 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
438 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
439 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
440 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
441 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
442 mac_stats->tx_collision = (mac_stats->tx_single_collision +
443 mac_stats->tx_multiple_collision +
444 mac_stats->tx_excessive_collision +
445 mac_stats->tx_late_collision);
446 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
447 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
448 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
449 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
450 MAC_STAT(rx_bytes, RX_BYTES);
451 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
452 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
453 mac_stats->rx_bad_bytes);
454 MAC_STAT(rx_packets, RX_PKTS);
455 MAC_STAT(rx_good, RX_GOOD_PKTS);
1cdc2cfc 456 MAC_STAT(rx_bad, RX_BAD_FCS_PKTS);
afd4aea0
BH		 457 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
458 MAC_STAT(rx_control, RX_CONTROL_PKTS);
459 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
460 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
461 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
462 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
463 MAC_STAT(rx_64, RX_64_PKTS);
464 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
465 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
466 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
467 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
468 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
469 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
470 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
471 mac_stats->rx_bad_lt64 = 0;
472 mac_stats->rx_bad_64_to_15xx = 0;
473 mac_stats->rx_bad_15xx_to_jumbo = 0;
474 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
475 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
476 mac_stats->rx_missed = 0;
477 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
478 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
479 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
480 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
481 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
482 mac_stats->rx_good_lt64 = 0;
483
a659b2a9
SH		 484 efx->n_rx_nodesc_drop_cnt =
485 le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]);
afd4aea0
BH		 486
487#undef MAC_STAT
488
489 rmb();
490 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
491 if (generation_end != generation_start)
492 return -EAGAIN;
493
494 return 0;
495}
496
497static void siena_update_nic_stats(struct efx_nic *efx)
498{
aabc5649
BH		 499 int retry;
500
501 /* If we're unlucky enough to read statistics wduring the DMA, wait
502 * up to 10ms for it to finish (typically takes <500us) */
503 for (retry = 0; retry < 100; ++retry) {
504 if (siena_try_update_nic_stats(efx) == 0)
505 return;
506 udelay(100);
507 }
508
509 /* Use the old values instead */
afd4aea0
BH		 510}
511
512static void siena_start_nic_stats(struct efx_nic *efx)
513{
a659b2a9 514 __le64 *dma_stats = efx->stats_buffer.addr;
afd4aea0
BH		 515
516 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
517
518 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
519 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
520}
521
522static void siena_stop_nic_stats(struct efx_nic *efx)
523{
524 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
525}
526
afd4aea0
BH		 527/**************************************************************************
528 *
529 * Wake on LAN
530 *
531 **************************************************************************
532 */
533
534static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
535{
536 struct siena_nic_data *nic_data = efx->nic_data;
537
538 wol->supported = WAKE_MAGIC;
539 if (nic_data->wol_filter_id != -1)
540 wol->wolopts = WAKE_MAGIC;
541 else
542 wol->wolopts = 0;
543 memset(&wol->sopass, 0, sizeof(wol->sopass));
544}
545
546
547static int siena_set_wol(struct efx_nic *efx, u32 type)
548{
549 struct siena_nic_data *nic_data = efx->nic_data;
550 int rc;
551
552 if (type & ~WAKE_MAGIC)
553 return -EINVAL;
554
555 if (type & WAKE_MAGIC) {
556 if (nic_data->wol_filter_id != -1)
557 efx_mcdi_wol_filter_remove(efx,
558 nic_data->wol_filter_id);
02ebc268 559 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
afd4aea0
BH		 560 &nic_data->wol_filter_id);
561 if (rc)
562 goto fail;
563
564 pci_wake_from_d3(efx->pci_dev, true);
565 } else {
566 rc = efx_mcdi_wol_filter_reset(efx);
567 nic_data->wol_filter_id = -1;
568 pci_wake_from_d3(efx->pci_dev, false);
569 if (rc)
570 goto fail;
571 }
572
573 return 0;
574 fail:
62776d03
BH		 575 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
576 __func__, type, rc);
afd4aea0
BH		 577 return rc;
578}
579
580
581static void siena_init_wol(struct efx_nic *efx)
582{
583 struct siena_nic_data *nic_data = efx->nic_data;
584 int rc;
585
586 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
587
588 if (rc != 0) {
589 /* If it failed, attempt to get into a synchronised
590 * state with MC by resetting any set WoL filters */
591 efx_mcdi_wol_filter_reset(efx);
592 nic_data->wol_filter_id = -1;
593 } else if (nic_data->wol_filter_id != -1) {
594 pci_wake_from_d3(efx->pci_dev, true);
595 }
596}
597
598
599/**************************************************************************
600 *
601 * Revision-dependent attributes used by efx.c and nic.c
602 *
603 **************************************************************************
604 */
605
6c8c2513 606const struct efx_nic_type siena_a0_nic_type = {
afd4aea0
BH		 607 .probe = siena_probe_nic,
608 .remove = siena_remove_nic,
609 .init = siena_init_nic,
610 .fini = efx_port_dummy_op_void,
611 .monitor = NULL,
0e2a9c7c
BH		 612 .map_reset_reason = siena_map_reset_reason,
613 .map_reset_flags = siena_map_reset_flags,
afd4aea0
BH		 614 .reset = siena_reset_hw,
615 .probe_port = siena_probe_port,
616 .remove_port = siena_remove_port,
617 .prepare_flush = efx_port_dummy_op_void,
618 .update_stats = siena_update_nic_stats,
619 .start_stats = siena_start_nic_stats,
620 .stop_stats = siena_stop_nic_stats,
621 .set_id_led = efx_mcdi_set_id_led,
622 .push_irq_moderation = siena_push_irq_moderation,
710b208d
BH		 623 .reconfigure_mac = efx_mcdi_mac_reconfigure,
624 .check_mac_fault = efx_mcdi_mac_check_fault,
afd4aea0
BH		 625 .reconfigure_port = efx_mcdi_phy_reconfigure,
626 .get_wol = siena_get_wol,
627 .set_wol = siena_set_wol,
628 .resume_wol = siena_init_wol,
629 .test_registers = siena_test_registers,
2e803407 630 .test_nvram = efx_mcdi_nvram_test_all,
afd4aea0
BH		 631
632 .revision = EFX_REV_SIENA_A0,
86c432ca
BH		 633 .mem_map_size = (FR_CZ_MC_TREG_SMEM +
634 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
afd4aea0
BH		 635 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
636 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
637 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
638 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
639 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
640 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
39c9cf07 641 .rx_buffer_hash_size = 0x10,
afd4aea0
BH		 642 .rx_buffer_padding = 0,
643 .max_interrupt_mode = EFX_INT_MODE_MSIX,
644 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
645 * interrupt handler only supports 32
646 * channels */
647 .tx_dc_base = 0x88000,
648 .rx_dc_base = 0x68000,
39c9cf07 649 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b4187e42 650 NETIF_F_RXHASH | NETIF_F_NTUPLE),
afd4aea0 651};
Linux kernel - Deliverables
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