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Merge branch 'drm-armada-devel' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into...
[deliverable/linux.git] / drivers / net / ethernet / sfc / siena.c
CommitLineData
afd4aea0 1/****************************************************************************
f7a6d2c4 2 * Driver for Solarflare network controllers and boards
afd4aea0 3 * Copyright 2005-2006 Fen Systems Ltd.
f7a6d2c4 4 * Copyright 2006-2013 Solarflare Communications Inc.
afd4aea0
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
5a0e3ad6 15#include <linux/slab.h>
d614cfbc 16#include <linux/random.h>
afd4aea0
BH		 17#include "net_driver.h"
18#include "bitfield.h"
19#include "efx.h"
20#include "nic.h"
8b8a95a1 21#include "farch_regs.h"
afd4aea0
BH		 22#include "io.h"
23#include "phy.h"
24#include "workarounds.h"
25#include "mcdi.h"
26#include "mcdi_pcol.h"
d4f2cecc 27#include "selftest.h"
7fa8d547 28#include "siena_sriov.h"
afd4aea0
BH		 29
30/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
31
32static void siena_init_wol(struct efx_nic *efx);
33
34
35static void siena_push_irq_moderation(struct efx_channel *channel)
36{
37 efx_dword_t timer_cmd;
38
39 if (channel->irq_moderation)
40 EFX_POPULATE_DWORD_2(timer_cmd,
41 FRF_CZ_TC_TIMER_MODE,
42 FFE_CZ_TIMER_MODE_INT_HLDOFF,
43 FRF_CZ_TC_TIMER_VAL,
44 channel->irq_moderation - 1);
45 else
46 EFX_POPULATE_DWORD_2(timer_cmd,
47 FRF_CZ_TC_TIMER_MODE,
48 FFE_CZ_TIMER_MODE_DIS,
49 FRF_CZ_TC_TIMER_VAL, 0);
50 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
51 channel->channel);
52}
53
d5e8cc6c
BH		 54void siena_prepare_flush(struct efx_nic *efx)
55{
56 if (efx->fc_disable++ == 0)
57 efx_mcdi_set_mac(efx);
58}
59
60void siena_finish_flush(struct efx_nic *efx)
61{
62 if (--efx->fc_disable == 0)
63 efx_mcdi_set_mac(efx);
64}
65
86094f7f 66static const struct efx_farch_register_test siena_register_tests[] = {
afd4aea0 67 { FR_AZ_ADR_REGION,
4cddca54 68 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
afd4aea0
BH		 69 { FR_CZ_USR_EV_CFG,
70 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
71 { FR_AZ_RX_CFG,
72 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
73 { FR_AZ_TX_CFG,
74 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
75 { FR_AZ_TX_RESERVED,
76 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
77 { FR_AZ_SRM_TX_DC_CFG,
78 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
79 { FR_AZ_RX_DC_CFG,
80 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
81 { FR_AZ_RX_DC_PF_WM,
82 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
83 { FR_BZ_DP_CTRL,
84 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
85 { FR_BZ_RX_RSS_TKEY,
86 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
87 { FR_CZ_RX_RSS_IPV6_REG1,
88 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
89 { FR_CZ_RX_RSS_IPV6_REG2,
90 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
91 { FR_CZ_RX_RSS_IPV6_REG3,
92 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
93};
94
d4f2cecc 95static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
afd4aea0 96{
ef492f11 97 enum reset_type reset_method = RESET_TYPE_ALL;
d4f2cecc
BH		 98 int rc, rc2;
99
100 efx_reset_down(efx, reset_method);
101
102 /* Reset the chip immediately so that it is completely
103 * quiescent regardless of what any VF driver does.
104 */
6bff861d 105 rc = efx_mcdi_reset(efx, reset_method);
d4f2cecc
BH		 106 if (rc)
107 goto out;
108
109 tests->registers =
86094f7f
BH		 110 efx_farch_test_registers(efx, siena_register_tests,
111 ARRAY_SIZE(siena_register_tests))
d4f2cecc
BH		 112 ? -1 : 1;
113
6bff861d 114 rc = efx_mcdi_reset(efx, reset_method);
d4f2cecc
BH		 115out:
116 rc2 = efx_reset_up(efx, reset_method, rc == 0);
117 return rc ? rc : rc2;
afd4aea0
BH		 118}
119
9ec06595
DP		 120/**************************************************************************
121 *
122 * PTP
123 *
124 **************************************************************************
125 */
126
127static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
128{
129 _efx_writed(efx, cpu_to_le32(host_time),
130 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
131}
132
133static int siena_ptp_set_ts_config(struct efx_nic *efx,
134 struct hwtstamp_config *init)
135{
136 int rc;
137
138 switch (init->rx_filter) {
139 case HWTSTAMP_FILTER_NONE:
140 /* if TX timestamping is still requested then leave PTP on */
141 return efx_ptp_change_mode(efx,
142 init->tx_type != HWTSTAMP_TX_OFF,
143 efx_ptp_get_mode(efx));
144 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
145 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
146 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
147 init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
148 return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1);
149 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
150 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
151 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
152 init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
153 rc = efx_ptp_change_mode(efx, true,
154 MC_CMD_PTP_MODE_V2_ENHANCED);
155 /* bug 33070 - old versions of the firmware do not support the
156 * improved UUID filtering option. Similarly old versions of the
157 * application do not expect it to be enabled. If the firmware
158 * does not accept the enhanced mode, fall back to the standard
159 * PTP v2 UUID filtering. */
160 if (rc != 0)
161 rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2);
162 return rc;
163 default:
164 return -ERANGE;
165 }
166}
167
afd4aea0
BH		 168/**************************************************************************
169 *
170 * Device reset
171 *
172 **************************************************************************
173 */
174
0e2a9c7c
BH		 175static int siena_map_reset_flags(u32 *flags)
176{
177 enum {
178 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
179 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
180 ETH_RESET_PHY),
181 SIENA_RESET_MC = (SIENA_RESET_PORT |
182 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
183 };
184
185 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
186 *flags &= ~SIENA_RESET_MC;
187 return RESET_TYPE_WORLD;
188 }
189
190 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
191 *flags &= ~SIENA_RESET_PORT;
192 return RESET_TYPE_ALL;
193 }
194
195 /* no invisible reset implemented */
196
197 return -EINVAL;
198}
199
626950db
AR		 200#ifdef CONFIG_EEH
201/* When a PCI device is isolated from the bus, a subsequent MMIO read is
202 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
203 * was written to minimise MMIO read (for latency) then a periodic call to check
204 * the EEH status of the device is required so that device recovery can happen
205 * in a timely fashion.
206 */
207static void siena_monitor(struct efx_nic *efx)
208{
12a89dba 209 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
626950db
AR		 210
211 eeh_dev_check_failure(eehdev);
212}
213#endif
214
afd4aea0
BH		 215static int siena_probe_nvconfig(struct efx_nic *efx)
216{
cc180b69
BH		 217 u32 caps = 0;
218 int rc;
219
220 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
221
222 efx->timer_quantum_ns =
223 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
224 3072 : 6144; /* 768 cycles */
225 return rc;
afd4aea0
BH		 226}
227
c15eed22 228static int siena_dimension_resources(struct efx_nic *efx)
28e47c49
BH		 229{
230 /* Each port has a small block of internal SRAM dedicated to
231 * the buffer table and descriptor caches. In theory we can
232 * map both blocks to one port, but we don't.
233 */
86094f7f 234 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
c15eed22 235 return 0;
28e47c49
BH		 236}
237
b105798f
BH		 238static unsigned int siena_mem_map_size(struct efx_nic *efx)
239{
240 return FR_CZ_MC_TREG_SMEM +
241 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
242}
243
afd4aea0
BH		 244static int siena_probe_nic(struct efx_nic *efx)
245{
246 struct siena_nic_data *nic_data;
d42a8f46 247 efx_oword_t reg;
afd4aea0
BH		 248 int rc;
249
250 /* Allocate storage for hardware specific data */
251 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
252 if (!nic_data)
253 return -ENOMEM;
2dc313ec 254 nic_data->efx = efx;
afd4aea0
BH		 255 efx->nic_data = nic_data;
256
86094f7f 257 if (efx_farch_fpga_ver(efx) != 0) {
62776d03
BH		 258 netif_err(efx, probe, efx->net_dev,
259 "Siena FPGA not supported\n");
afd4aea0
BH		 260 rc = -ENODEV;
261 goto fail1;
262 }
263
b105798f 264 efx->max_channels = EFX_MAX_CHANNELS;
b0fbdae1 265 efx->max_tx_channels = EFX_MAX_CHANNELS;
b105798f 266
d42a8f46 267 efx_reado(efx, &reg, FR_AZ_CS_DEBUG);
6602041b 268 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
d42a8f46 269
f073dde0 270 rc = efx_mcdi_init(efx);
afd4aea0 271 if (rc)
86c432ca 272 goto fail1;
afd4aea0 273
afd4aea0 274 /* Now we can reset the NIC */
6bff861d 275 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
afd4aea0 276 if (rc) {
62776d03 277 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
afd4aea0
BH		 278 goto fail3;
279 }
280
281 siena_init_wol(efx);
282
283 /* Allocate memory for INT_KER */
0d19a540
BH		 284 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
285 GFP_KERNEL);
afd4aea0
BH		 286 if (rc)
287 goto fail4;
288 BUG_ON(efx->irq_status.dma_addr & 0x0f);
289
62776d03
BH		 290 netif_dbg(efx, probe, efx->net_dev,
291 "INT_KER at %llx (virt %p phys %llx)\n",
292 (unsigned long long)efx->irq_status.dma_addr,
293 efx->irq_status.addr,
294 (unsigned long long)virt_to_phys(efx->irq_status.addr));
afd4aea0
BH		 295
296 /* Read in the non-volatile configuration */
297 rc = siena_probe_nvconfig(efx);
298 if (rc == -EINVAL) {
62776d03
BH		 299 netif_err(efx, probe, efx->net_dev,
300 "NVRAM is invalid therefore using defaults\n");
afd4aea0
BH		 301 efx->phy_type = PHY_TYPE_NONE;
302 efx->mdio.prtad = MDIO_PRTAD_NONE;
303 } else if (rc) {
304 goto fail5;
305 }
306
55c5e0f8
BH		 307 rc = efx_mcdi_mon_probe(efx);
308 if (rc)
309 goto fail5;
310
7fa8d547 311#ifdef CONFIG_SFC_SRIOV
327c685e 312 efx_siena_sriov_probe(efx);
7fa8d547 313#endif
ac36baf8 314 efx_ptp_defer_probe_with_channel(efx);
cd2d5b52 315
afd4aea0
BH		 316 return 0;
317
318fail5:
319 efx_nic_free_buffer(efx, &efx->irq_status);
320fail4:
321fail3:
f3ad5003 322 efx_mcdi_fini(efx);
afd4aea0
BH		 323fail1:
324 kfree(efx->nic_data);
325 return rc;
326}
327
267c0157
JC		 328static int siena_rx_push_rss_config(struct efx_nic *efx, bool user,
329 const u32 *rx_indir_table)
d43050c0
AR		 330{
331 efx_oword_t temp;
332
333 /* Set hash key for IPv4 */
334 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
335 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
336
337 /* Enable IPv6 RSS */
338 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
339 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
340 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
341 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
342 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
343 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
344 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
345 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
346 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
347 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
348 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
349 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
350
267c0157
JC		 351 memcpy(efx->rx_indir_table, rx_indir_table,
352 sizeof(efx->rx_indir_table));
d43050c0 353 efx_farch_rx_push_indir_table(efx);
267c0157
JC		 354
355 return 0;
d43050c0
AR		 356}
357
afd4aea0
BH		 358/* This call performs hardware-specific global initialisation, such as
359 * defining the descriptor cache sizes and number of RSS channels.
360 * It does not set up any buffers, descriptor rings or event queues.
361 */
362static int siena_init_nic(struct efx_nic *efx)
363{
364 efx_oword_t temp;
365 int rc;
366
367 /* Recover from a failed assertion post-reset */
368 rc = efx_mcdi_handle_assertion(efx);
369 if (rc)
370 return rc;
371
372 /* Squash TX of packets of 16 bytes or less */
373 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
374 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
375 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
376
377 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
378 * descriptors (which is bad).
379 */
380 efx_reado(efx, &temp, FR_AZ_TX_CFG);
381 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
382 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
383 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
384
385 efx_reado(efx, &temp, FR_AZ_RX_CFG);
386 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
387 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
477e54eb
BH		 388 /* Enable hash insertion. This is broken for the 'Falcon' hash
389 * if IPv6 hashing is also enabled, so also select Toeplitz
390 * TCP/IPv4 and IPv4 hashes. */
391 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
392 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
393 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
85740cdf
BH		 394 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
395 EFX_RX_USR_BUF_SIZE >> 5);
afd4aea0
BH		 396 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
397
267c0157 398 siena_rx_push_rss_config(efx, false, efx->rx_indir_table);
d614cfbc 399
afd4aea0
BH		 400 /* Enable event logging */
401 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
402 if (rc)
403 return rc;
404
405 /* Set destination of both TX and RX Flush events */
406 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
407 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
408
409 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
410 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
411
86094f7f 412 efx_farch_init_common(efx);
afd4aea0
BH		 413 return 0;
414}
415
416static void siena_remove_nic(struct efx_nic *efx)
417{
55c5e0f8
BH		 418 efx_mcdi_mon_remove(efx);
419
afd4aea0
BH		 420 efx_nic_free_buffer(efx, &efx->irq_status);
421
6bff861d 422 efx_mcdi_reset(efx, RESET_TYPE_ALL);
afd4aea0 423
4c75b43a 424 efx_mcdi_fini(efx);
afd4aea0
BH		 425
426 /* Tear down the private nic state */
86c432ca 427 kfree(efx->nic_data);
afd4aea0
BH		 428 efx->nic_data = NULL;
429}
430
cd0ecc9a
BH		 431#define SIENA_DMA_STAT(ext_name, mcdi_name) \
432 [SIENA_STAT_ ## ext_name] = \
433 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
434#define SIENA_OTHER_STAT(ext_name) \
435 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 436#define GENERIC_SW_STAT(ext_name) \
437 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
cd0ecc9a
BH		 438
439static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
440 SIENA_DMA_STAT(tx_bytes, TX_BYTES),
441 SIENA_OTHER_STAT(tx_good_bytes),
442 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
443 SIENA_DMA_STAT(tx_packets, TX_PKTS),
444 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
445 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
446 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
447 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
448 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
449 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
450 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
451 SIENA_DMA_STAT(tx_64, TX_64_PKTS),
452 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
453 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
454 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
455 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
456 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
457 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
458 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
459 SIENA_OTHER_STAT(tx_collision),
460 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
461 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
462 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
463 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
464 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
465 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
466 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
467 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
468 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
469 SIENA_DMA_STAT(rx_bytes, RX_BYTES),
470 SIENA_OTHER_STAT(rx_good_bytes),
471 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
472 SIENA_DMA_STAT(rx_packets, RX_PKTS),
473 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
474 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
475 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
476 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
477 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
478 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
479 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
480 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
481 SIENA_DMA_STAT(rx_64, RX_64_PKTS),
482 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
483 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
484 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
485 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
486 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
487 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
488 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
489 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
490 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
491 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
492 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
493 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
494 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
495 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
496 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
e4d112e4
EC		 497 GENERIC_SW_STAT(rx_nodesc_trunc),
498 GENERIC_SW_STAT(rx_noskb_drops),
cd0ecc9a
BH		 499};
500static const unsigned long siena_stat_mask[] = {
501 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
502};
503
504static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
505{
506 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
507 siena_stat_mask, names);
508}
509
afd4aea0
BH		 510static int siena_try_update_nic_stats(struct efx_nic *efx)
511{
cd0ecc9a
BH		 512 struct siena_nic_data *nic_data = efx->nic_data;
513 u64 *stats = nic_data->stats;
a659b2a9 514 __le64 *dma_stats;
a659b2a9 515 __le64 generation_start, generation_end;
afd4aea0 516
43d620c8 517 dma_stats = efx->stats_buffer.addr;
afd4aea0
BH		 518
519 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
43f775b2 520 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
afd4aea0
BH		 521 return 0;
522 rmb();
cd0ecc9a
BH		 523 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
524 stats, efx->stats_buffer.addr, false);
afd4aea0
BH		 525 rmb();
526 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
527 if (generation_end != generation_start)
528 return -EAGAIN;
529
cd0ecc9a 530 /* Update derived statistics */
f8f3b5ae
JC		 531 efx_nic_fix_nodesc_drop_stat(efx,
532 &stats[SIENA_STAT_rx_nodesc_drop_cnt]);
cd0ecc9a
BH		 533 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
534 stats[SIENA_STAT_tx_bytes] -
535 stats[SIENA_STAT_tx_bad_bytes]);
536 stats[SIENA_STAT_tx_collision] =
537 stats[SIENA_STAT_tx_single_collision] +
538 stats[SIENA_STAT_tx_multiple_collision] +
539 stats[SIENA_STAT_tx_excessive_collision] +
540 stats[SIENA_STAT_tx_late_collision];
541 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
542 stats[SIENA_STAT_rx_bytes] -
543 stats[SIENA_STAT_rx_bad_bytes]);
e4d112e4 544 efx_update_sw_stats(efx, stats);
afd4aea0
BH		 545 return 0;
546}
547
cd0ecc9a
BH		 548static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
549 struct rtnl_link_stats64 *core_stats)
afd4aea0 550{
cd0ecc9a
BH		 551 struct siena_nic_data *nic_data = efx->nic_data;
552 u64 *stats = nic_data->stats;
aabc5649
BH		 553 int retry;
554
555 /* If we're unlucky enough to read statistics wduring the DMA, wait
556 * up to 10ms for it to finish (typically takes <500us) */
557 for (retry = 0; retry < 100; ++retry) {
558 if (siena_try_update_nic_stats(efx) == 0)
cd0ecc9a 559 break;
aabc5649
BH		 560 udelay(100);
561 }
562
cd0ecc9a
BH		 563 if (full_stats)
564 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
565
566 if (core_stats) {
567 core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
568 core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
569 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
570 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
e4d112e4
EC		 571 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] +
572 stats[GENERIC_STAT_rx_nodesc_trunc] +
573 stats[GENERIC_STAT_rx_noskb_drops];
cd0ecc9a
BH		 574 core_stats->multicast = stats[SIENA_STAT_rx_multicast];
575 core_stats->collisions = stats[SIENA_STAT_tx_collision];
576 core_stats->rx_length_errors =
577 stats[SIENA_STAT_rx_gtjumbo] +
578 stats[SIENA_STAT_rx_length_error];
579 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
580 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
581 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
582 core_stats->tx_window_errors =
583 stats[SIENA_STAT_tx_late_collision];
584
585 core_stats->rx_errors = (core_stats->rx_length_errors +
586 core_stats->rx_crc_errors +
587 core_stats->rx_frame_errors +
588 stats[SIENA_STAT_rx_symbol_error]);
589 core_stats->tx_errors = (core_stats->tx_window_errors +
590 stats[SIENA_STAT_tx_bad]);
591 }
592
593 return SIENA_STAT_COUNT;
afd4aea0
BH		 594}
595
319ec644
BH		 596static int siena_mac_reconfigure(struct efx_nic *efx)
597{
598 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
599 int rc;
600
601 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
602 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
603 sizeof(efx->multicast_hash));
604
964e6135
BH		 605 efx_farch_filter_sync_rx_mode(efx);
606
319ec644
BH		 607 WARN_ON(!mutex_is_locked(&efx->mac_lock));
608
609 rc = efx_mcdi_set_mac(efx);
610 if (rc != 0)
611 return rc;
612
613 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
614 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
615 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
616 inbuf, sizeof(inbuf), NULL, 0, NULL);
617}
618
afd4aea0
BH		 619/**************************************************************************
620 *
621 * Wake on LAN
622 *
623 **************************************************************************
624 */
625
626static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
627{
628 struct siena_nic_data *nic_data = efx->nic_data;
629
630 wol->supported = WAKE_MAGIC;
631 if (nic_data->wol_filter_id != -1)
632 wol->wolopts = WAKE_MAGIC;
633 else
634 wol->wolopts = 0;
635 memset(&wol->sopass, 0, sizeof(wol->sopass));
636}
637
638
639static int siena_set_wol(struct efx_nic *efx, u32 type)
640{
641 struct siena_nic_data *nic_data = efx->nic_data;
642 int rc;
643
644 if (type & ~WAKE_MAGIC)
645 return -EINVAL;
646
647 if (type & WAKE_MAGIC) {
648 if (nic_data->wol_filter_id != -1)
649 efx_mcdi_wol_filter_remove(efx,
650 nic_data->wol_filter_id);
02ebc268 651 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
afd4aea0
BH		 652 &nic_data->wol_filter_id);
653 if (rc)
654 goto fail;
655
656 pci_wake_from_d3(efx->pci_dev, true);
657 } else {
658 rc = efx_mcdi_wol_filter_reset(efx);
659 nic_data->wol_filter_id = -1;
660 pci_wake_from_d3(efx->pci_dev, false);
661 if (rc)
662 goto fail;
663 }
664
665 return 0;
666 fail:
62776d03
BH		 667 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
668 __func__, type, rc);
afd4aea0
BH		 669 return rc;
670}
671
672
673static void siena_init_wol(struct efx_nic *efx)
674{
675 struct siena_nic_data *nic_data = efx->nic_data;
676 int rc;
677
678 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
679
680 if (rc != 0) {
681 /* If it failed, attempt to get into a synchronised
682 * state with MC by resetting any set WoL filters */
683 efx_mcdi_wol_filter_reset(efx);
684 nic_data->wol_filter_id = -1;
685 } else if (nic_data->wol_filter_id != -1) {
686 pci_wake_from_d3(efx->pci_dev, true);
687 }
688}
689
f3ad5003
BH		 690/**************************************************************************
691 *
692 * MCDI
693 *
694 **************************************************************************
695 */
696
697#define MCDI_PDU(efx) \
698 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
699#define MCDI_DOORBELL(efx) \
700 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
701#define MCDI_STATUS(efx) \
702 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
703
704static void siena_mcdi_request(struct efx_nic *efx,
705 const efx_dword_t *hdr, size_t hdr_len,
706 const efx_dword_t *sdu, size_t sdu_len)
707{
708 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
709 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
710 unsigned int i;
711 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
712
713 EFX_BUG_ON_PARANOID(hdr_len != 4);
714
715 efx_writed(efx, hdr, pdu);
716
717 for (i = 0; i < inlen_dw; i++)
718 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
719
720 /* Ensure the request is written out before the doorbell */
721 wmb();
722
723 /* ring the doorbell with a distinctive value */
724 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
725}
726
727static bool siena_mcdi_poll_response(struct efx_nic *efx)
728{
729 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
730 efx_dword_t hdr;
731
732 efx_readd(efx, &hdr, pdu);
733
734 /* All 1's indicates that shared memory is in reset (and is
735 * not a valid hdr). Wait for it to come out reset before
736 * completing the command
737 */
738 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
739 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
740}
741
742static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
743 size_t offset, size_t outlen)
744{
745 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
746 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
747 int i;
748
749 for (i = 0; i < outlen_dw; i++)
750 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
751}
752
753static int siena_mcdi_poll_reboot(struct efx_nic *efx)
754{
cd0ecc9a 755 struct siena_nic_data *nic_data = efx->nic_data;
f3ad5003
BH		 756 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
757 efx_dword_t reg;
758 u32 value;
759
760 efx_readd(efx, &reg, addr);
761 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
762
763 if (value == 0)
764 return 0;
765
766 EFX_ZERO_DWORD(reg);
767 efx_writed(efx, &reg, addr);
768
cd0ecc9a
BH		 769 /* MAC statistics have been cleared on the NIC; clear the local
770 * copies that we update with efx_update_diff_stat().
771 */
772 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
773 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
774
f3ad5003
BH		 775 if (value == MC_STATUS_DWORD_ASSERT)
776 return -EINTR;
777 else
778 return -EIO;
779}
afd4aea0 780
45a3fd55
BH		 781/**************************************************************************
782 *
783 * MTD
784 *
785 **************************************************************************
786 */
787
788#ifdef CONFIG_SFC_MTD
789
790struct siena_nvram_type_info {
791 int port;
792 const char *name;
793};
794
795static const struct siena_nvram_type_info siena_nvram_types[] = {
796 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
797 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
798 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
799 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
800 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
801 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
802 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
803 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
804 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
805 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
806 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
807 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
808 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
809};
810
811static int siena_mtd_probe_partition(struct efx_nic *efx,
812 struct efx_mcdi_mtd_partition *part,
813 unsigned int type)
814{
815 const struct siena_nvram_type_info *info;
816 size_t size, erase_size;
817 bool protected;
818 int rc;
819
820 if (type >= ARRAY_SIZE(siena_nvram_types) ||
821 siena_nvram_types[type].name == NULL)
822 return -ENODEV;
823
824 info = &siena_nvram_types[type];
825
826 if (info->port != efx_port_num(efx))
827 return -ENODEV;
828
829 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
830 if (rc)
831 return rc;
832 if (protected)
833 return -ENODEV; /* hide it */
834
835 part->nvram_type = type;
836 part->common.dev_type_name = "Siena NVRAM manager";
837 part->common.type_name = info->name;
838
839 part->common.mtd.type = MTD_NORFLASH;
840 part->common.mtd.flags = MTD_CAP_NORFLASH;
841 part->common.mtd.size = size;
842 part->common.mtd.erasesize = erase_size;
843
844 return 0;
845}
846
847static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
848 struct efx_mcdi_mtd_partition *parts,
849 size_t n_parts)
850{
851 uint16_t fw_subtype_list[
852 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
853 size_t i;
854 int rc;
855
856 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
857 if (rc)
858 return rc;
859
860 for (i = 0; i < n_parts; i++)
861 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
862
863 return 0;
864}
865
866static int siena_mtd_probe(struct efx_nic *efx)
867{
868 struct efx_mcdi_mtd_partition *parts;
869 u32 nvram_types;
870 unsigned int type;
871 size_t n_parts;
872 int rc;
873
874 ASSERT_RTNL();
875
876 rc = efx_mcdi_nvram_types(efx, &nvram_types);
877 if (rc)
878 return rc;
879
880 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
881 if (!parts)
882 return -ENOMEM;
883
884 type = 0;
885 n_parts = 0;
886
887 while (nvram_types != 0) {
888 if (nvram_types & 1) {
889 rc = siena_mtd_probe_partition(efx, &parts[n_parts],
890 type);
891 if (rc == 0)
892 n_parts++;
893 else if (rc != -ENODEV)
894 goto fail;
895 }
896 type++;
897 nvram_types >>= 1;
898 }
899
900 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
901 if (rc)
902 goto fail;
903
904 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
905fail:
906 if (rc)
907 kfree(parts);
908 return rc;
909}
910
911#endif /* CONFIG_SFC_MTD */
912
afd4aea0
BH		 913/**************************************************************************
914 *
915 * Revision-dependent attributes used by efx.c and nic.c
916 *
917 **************************************************************************
918 */
919
6c8c2513 920const struct efx_nic_type siena_a0_nic_type = {
6f7f8aa6 921 .is_vf = false,
02246a7f 922 .mem_bar = EFX_MEM_BAR,
b105798f 923 .mem_map_size = siena_mem_map_size,
afd4aea0
BH		 924 .probe = siena_probe_nic,
925 .remove = siena_remove_nic,
926 .init = siena_init_nic,
28e47c49 927 .dimension_resources = siena_dimension_resources,
afd4aea0 928 .fini = efx_port_dummy_op_void,
626950db
AR		 929#ifdef CONFIG_EEH
930 .monitor = siena_monitor,
931#else
afd4aea0 932 .monitor = NULL,
626950db 933#endif
6bff861d 934 .map_reset_reason = efx_mcdi_map_reset_reason,
0e2a9c7c 935 .map_reset_flags = siena_map_reset_flags,
6bff861d 936 .reset = efx_mcdi_reset,
43f775b2
BH		 937 .probe_port = efx_mcdi_port_probe,
938 .remove_port = efx_mcdi_port_remove,
e42c3d85 939 .fini_dmaq = efx_farch_fini_dmaq,
d5e8cc6c
BH		 940 .prepare_flush = siena_prepare_flush,
941 .finish_flush = siena_finish_flush,
e283546c
EC		 942 .prepare_flr = efx_port_dummy_op_void,
943 .finish_flr = efx_farch_finish_flr,
cd0ecc9a 944 .describe_stats = siena_describe_nic_stats,
afd4aea0 945 .update_stats = siena_update_nic_stats,
43f775b2 946 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 947 .pull_stats = efx_mcdi_mac_pull_stats,
43f775b2 948 .stop_stats = efx_mcdi_mac_stop_stats,
afd4aea0
BH		 949 .set_id_led = efx_mcdi_set_id_led,
950 .push_irq_moderation = siena_push_irq_moderation,
319ec644 951 .reconfigure_mac = siena_mac_reconfigure,
710b208d 952 .check_mac_fault = efx_mcdi_mac_check_fault,
43f775b2 953 .reconfigure_port = efx_mcdi_port_reconfigure,
afd4aea0
BH		 954 .get_wol = siena_get_wol,
955 .set_wol = siena_set_wol,
956 .resume_wol = siena_init_wol,
d4f2cecc 957 .test_chip = siena_test_chip,
2e803407 958 .test_nvram = efx_mcdi_nvram_test_all,
f3ad5003
BH		 959 .mcdi_request = siena_mcdi_request,
960 .mcdi_poll_response = siena_mcdi_poll_response,
961 .mcdi_read_response = siena_mcdi_read_response,
962 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
86094f7f
BH		 963 .irq_enable_master = efx_farch_irq_enable_master,
964 .irq_test_generate = efx_farch_irq_test_generate,
965 .irq_disable_non_ev = efx_farch_irq_disable_master,
966 .irq_handle_msi = efx_farch_msi_interrupt,
967 .irq_handle_legacy = efx_farch_legacy_interrupt,
968 .tx_probe = efx_farch_tx_probe,
969 .tx_init = efx_farch_tx_init,
970 .tx_remove = efx_farch_tx_remove,
971 .tx_write = efx_farch_tx_write,
d43050c0 972 .rx_push_rss_config = siena_rx_push_rss_config,
86094f7f
BH		 973 .rx_probe = efx_farch_rx_probe,
974 .rx_init = efx_farch_rx_init,
975 .rx_remove = efx_farch_rx_remove,
976 .rx_write = efx_farch_rx_write,
977 .rx_defer_refill = efx_farch_rx_defer_refill,
978 .ev_probe = efx_farch_ev_probe,
979 .ev_init = efx_farch_ev_init,
980 .ev_fini = efx_farch_ev_fini,
981 .ev_remove = efx_farch_ev_remove,
982 .ev_process = efx_farch_ev_process,
983 .ev_read_ack = efx_farch_ev_read_ack,
984 .ev_test_generate = efx_farch_ev_test_generate,
add72477
BH		 985 .filter_table_probe = efx_farch_filter_table_probe,
986 .filter_table_restore = efx_farch_filter_table_restore,
987 .filter_table_remove = efx_farch_filter_table_remove,
988 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
989 .filter_insert = efx_farch_filter_insert,
990 .filter_remove_safe = efx_farch_filter_remove_safe,
991 .filter_get_safe = efx_farch_filter_get_safe,
992 .filter_clear_rx = efx_farch_filter_clear_rx,
993 .filter_count_rx_used = efx_farch_filter_count_rx_used,
994 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
995 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
996#ifdef CONFIG_RFS_ACCEL
997 .filter_rfs_insert = efx_farch_filter_rfs_insert,
998 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
999#endif
45a3fd55
BH		 1000#ifdef CONFIG_SFC_MTD
1001 .mtd_probe = siena_mtd_probe,
1002 .mtd_rename = efx_mcdi_mtd_rename,
1003 .mtd_read = efx_mcdi_mtd_read,
1004 .mtd_erase = efx_mcdi_mtd_erase,
1005 .mtd_write = efx_mcdi_mtd_write,
1006 .mtd_sync = efx_mcdi_mtd_sync,
1007#endif
977a5d5d 1008 .ptp_write_host_time = siena_ptp_write_host_time,
9ec06595 1009 .ptp_set_ts_config = siena_ptp_set_ts_config,
7fa8d547 1010#ifdef CONFIG_SFC_SRIOV
834e23dd 1011 .sriov_configure = efx_siena_sriov_configure,
d98a4ffe
SS		 1012 .sriov_init = efx_siena_sriov_init,
1013 .sriov_fini = efx_siena_sriov_fini,
d98a4ffe
SS		 1014 .sriov_wanted = efx_siena_sriov_wanted,
1015 .sriov_reset = efx_siena_sriov_reset,
7fa8d547
SS		 1016 .sriov_flr = efx_siena_sriov_flr,
1017 .sriov_set_vf_mac = efx_siena_sriov_set_vf_mac,
1018 .sriov_set_vf_vlan = efx_siena_sriov_set_vf_vlan,
1019 .sriov_set_vf_spoofchk = efx_siena_sriov_set_vf_spoofchk,
1020 .sriov_get_vf_config = efx_siena_sriov_get_vf_config,
6d8aaaf6
DP		 1021 .vswitching_probe = efx_port_dummy_op_int,
1022 .vswitching_restore = efx_port_dummy_op_int,
1023 .vswitching_remove = efx_port_dummy_op_void,
910c8789 1024 .set_mac_address = efx_siena_sriov_mac_address_changed,
7fa8d547 1025#endif
afd4aea0
BH		 1026
1027 .revision = EFX_REV_SIENA_A0,
afd4aea0
BH		 1028 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1029 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1030 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1031 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1032 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1033 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
43a3739d
JC		 1034 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
1035 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
afd4aea0 1036 .rx_buffer_padding = 0,
85740cdf 1037 .can_rx_scatter = true,
afd4aea0 1038 .max_interrupt_mode = EFX_INT_MODE_MSIX,
cc180b69 1039 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
39c9cf07 1040 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b4187e42 1041 NETIF_F_RXHASH | NETIF_F_NTUPLE),
df2cd8af 1042 .mcdi_max_ver = 1,
add72477 1043 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
9ec06595
DP		 1044 .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE |
1045 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT |
7415991e 1046 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT),
afd4aea0 1047};
Linux kernel - Deliverables
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