[deliverable/linux.git] / drivers / net / ethernet / sfc / tenxpress.c

/****************************************************************************
 * Driver for Solarflare network controllers and boards
 * Copyright 2007-2011 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#include <linux/delay.h>
#include <linux/rtnetlink.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include "efx.h"
#include "mdio_10g.h"
#include "nic.h"
#include "phy.h"
#include "workarounds.h"

/* We expect these MMDs to be in the package. */
#define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD	| \
				 MDIO_DEVS_PCS		| \
				 MDIO_DEVS_PHYXS	| \
				 MDIO_DEVS_AN)

#define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) |	\
			   (1 << LOOPBACK_PCS) |	\
			   (1 << LOOPBACK_PMAPMD) |	\
			   (1 << LOOPBACK_PHYXS_WS))

/* We complain if we fail to see the link partner as 10G capable this many
 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
 */
#define MAX_BAD_LP_TRIES	(5)

/* Extended control register */
#define PMA_PMD_XCONTROL_REG	49152
#define PMA_PMD_EXT_GMII_EN_LBN	1
#define PMA_PMD_EXT_GMII_EN_WIDTH 1
#define PMA_PMD_EXT_CLK_OUT_LBN	2
#define PMA_PMD_EXT_CLK_OUT_WIDTH 1
#define PMA_PMD_LNPGA_POWERDOWN_LBN 8
#define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
#define PMA_PMD_EXT_CLK312_WIDTH 1
#define PMA_PMD_EXT_LPOWER_LBN  12
#define PMA_PMD_EXT_LPOWER_WIDTH 1
#define PMA_PMD_EXT_ROBUST_LBN	14
#define PMA_PMD_EXT_ROBUST_WIDTH 1
#define PMA_PMD_EXT_SSR_LBN	15
#define PMA_PMD_EXT_SSR_WIDTH	1

/* extended status register */
#define PMA_PMD_XSTATUS_REG	49153
#define PMA_PMD_XSTAT_MDIX_LBN	14
#define PMA_PMD_XSTAT_FLP_LBN   (12)

/* LED control register */
#define PMA_PMD_LED_CTRL_REG	49159
#define PMA_PMA_LED_ACTIVITY_LBN	(3)

/* LED function override register */
#define PMA_PMD_LED_OVERR_REG	49161
/* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
#define PMA_PMD_LED_LINK_LBN	(0)
#define PMA_PMD_LED_SPEED_LBN	(2)
#define PMA_PMD_LED_TX_LBN	(4)
#define PMA_PMD_LED_RX_LBN	(6)
/* Override settings */
#define	PMA_PMD_LED_AUTO	(0)	/* H/W control */
#define	PMA_PMD_LED_ON		(1)
#define	PMA_PMD_LED_OFF		(2)
#define PMA_PMD_LED_FLASH	(3)
#define PMA_PMD_LED_MASK	3
/* All LEDs under hardware control */
/* Green and Amber under hardware control, Red off */
#define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)

#define PMA_PMD_SPEED_ENABLE_REG 49192
#define PMA_PMD_100TX_ADV_LBN    1
#define PMA_PMD_100TX_ADV_WIDTH  1
#define PMA_PMD_1000T_ADV_LBN    2
#define PMA_PMD_1000T_ADV_WIDTH  1
#define PMA_PMD_10000T_ADV_LBN   3
#define PMA_PMD_10000T_ADV_WIDTH 1
#define PMA_PMD_SPEED_LBN        4
#define PMA_PMD_SPEED_WIDTH      4

/* Misc register defines */
#define PCS_CLOCK_CTRL_REG	55297
#define PLL312_RST_N_LBN 2

#define PCS_SOFT_RST2_REG	55302
#define SERDES_RST_N_LBN 13
#define XGXS_RST_N_LBN 12

#define	PCS_TEST_SELECT_REG	55303	/* PRM 10.5.8 */
#define	CLK312_EN_LBN 3

/* PHYXS registers */
#define PHYXS_XCONTROL_REG	49152
#define PHYXS_RESET_LBN		15
#define PHYXS_RESET_WIDTH	1

#define PHYXS_TEST1         (49162)
#define LOOPBACK_NEAR_LBN   (8)
#define LOOPBACK_NEAR_WIDTH (1)

/* Boot status register */
#define PCS_BOOT_STATUS_REG		53248
#define PCS_BOOT_FATAL_ERROR_LBN	0
#define PCS_BOOT_PROGRESS_LBN		1
#define PCS_BOOT_PROGRESS_WIDTH		2
#define PCS_BOOT_PROGRESS_INIT		0
#define PCS_BOOT_PROGRESS_WAIT_MDIO	1
#define PCS_BOOT_PROGRESS_CHECKSUM	2
#define PCS_BOOT_PROGRESS_JUMP		3
#define PCS_BOOT_DOWNLOAD_WAIT_LBN	3
#define PCS_BOOT_CODE_STARTED_LBN	4

/* 100M/1G PHY registers */
#define GPHY_XCONTROL_REG	49152
#define GPHY_ISOLATE_LBN	10
#define GPHY_ISOLATE_WIDTH	1
#define GPHY_DUPLEX_LBN		8
#define GPHY_DUPLEX_WIDTH	1
#define GPHY_LOOPBACK_NEAR_LBN	14
#define GPHY_LOOPBACK_NEAR_WIDTH 1

#define C22EXT_STATUS_REG       49153
#define C22EXT_STATUS_LINK_LBN  2
#define C22EXT_STATUS_LINK_WIDTH 1

#define C22EXT_MSTSLV_CTRL			49161
#define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN	8
#define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN	9

#define C22EXT_MSTSLV_STATUS			49162
#define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN	10
#define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN	11

/* Time to wait between powering down the LNPGA and turning off the power
 * rails */
#define LNPGA_PDOWN_WAIT	(HZ / 5)

struct tenxpress_phy_data {
	enum efx_loopback_mode loopback_mode;
	enum efx_phy_mode phy_mode;
	int bad_lp_tries;
};

static int tenxpress_init(struct efx_nic *efx)
{
	/* Enable 312.5 MHz clock */
	efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
		       1 << CLK312_EN_LBN);

	/* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
	efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG,
			  1 << PMA_PMA_LED_ACTIVITY_LBN, true);
	efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG,
		       SFX7101_PMA_PMD_LED_DEFAULT);

	return 0;
}

static int tenxpress_phy_probe(struct efx_nic *efx)
{
	struct tenxpress_phy_data *phy_data;

	/* Allocate phy private storage */
	phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
	if (!phy_data)
		return -ENOMEM;
	efx->phy_data = phy_data;
	phy_data->phy_mode = efx->phy_mode;

	efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS;
	efx->mdio.mode_support = MDIO_SUPPORTS_C45;

	efx->loopback_modes = SFX7101_LOOPBACKS | FALCON_XMAC_LOOPBACKS;

	efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg |
				 ADVERTISED_10000baseT_Full);

	return 0;
}

static int tenxpress_phy_init(struct efx_nic *efx)
{
	int rc;

	falcon_board(efx)->type->init_phy(efx);

	if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
		rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
		if (rc < 0)
			return rc;

		rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS);
		if (rc < 0)
			return rc;
	}

	rc = tenxpress_init(efx);
	if (rc < 0)
		return rc;

	/* Reinitialise flow control settings */
	efx_link_set_wanted_fc(efx, efx->wanted_fc);
	efx_mdio_an_reconfigure(efx);

	schedule_timeout_uninterruptible(HZ / 5); /* 200ms */

	/* Let XGXS and SerDes out of reset */
	falcon_reset_xaui(efx);

	return 0;
}

/* Perform a "special software reset" on the PHY. The caller is
 * responsible for saving and restoring the PHY hardware registers
 * properly, and masking/unmasking LASI */
static int tenxpress_special_reset(struct efx_nic *efx)
{
	int rc, reg;

	/* The XGMAC clock is driven from the SFX7101 312MHz clock, so
	 * a special software reset can glitch the XGMAC sufficiently for stats
	 * requests to fail. */
	falcon_stop_nic_stats(efx);

	/* Initiate reset */
	reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
	reg |= (1 << PMA_PMD_EXT_SSR_LBN);
	efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);

	mdelay(200);

	/* Wait for the blocks to come out of reset */
	rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
	if (rc < 0)
		goto out;

	/* Try and reconfigure the device */
	rc = tenxpress_init(efx);
	if (rc < 0)
		goto out;

	/* Wait for the XGXS state machine to churn */
	mdelay(10);
out:
	falcon_start_nic_stats(efx);
	return rc;
}

static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
{
	struct tenxpress_phy_data *pd = efx->phy_data;
	bool bad_lp;
	int reg;

	if (link_ok) {
		bad_lp = false;
	} else {
		/* Check that AN has started but not completed. */
		reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
		if (!(reg & MDIO_AN_STAT1_LPABLE))
			return; /* LP status is unknown */
		bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE);
		if (bad_lp)
			pd->bad_lp_tries++;
	}

	/* Nothing to do if all is well and was previously so. */
	if (!pd->bad_lp_tries)
		return;

	/* Use the RX (red) LED as an error indicator once we've seen AN
	 * failure several times in a row, and also log a message. */
	if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
		reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
				    PMA_PMD_LED_OVERR_REG);
		reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
		if (!bad_lp) {
			reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
		} else {
			reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
			netif_err(efx, link, efx->net_dev,
				  "appears to be plugged into a port"
				  " that is not 10GBASE-T capable. The PHY"
				  " supports 10GBASE-T ONLY, so no link can"
				  " be established\n");
		}
		efx_mdio_write(efx, MDIO_MMD_PMAPMD,
			       PMA_PMD_LED_OVERR_REG, reg);
		pd->bad_lp_tries = bad_lp;
	}
}

static bool sfx7101_link_ok(struct efx_nic *efx)
{
	return efx_mdio_links_ok(efx,
				 MDIO_DEVS_PMAPMD |
				 MDIO_DEVS_PCS |
				 MDIO_DEVS_PHYXS);
}

static void tenxpress_ext_loopback(struct efx_nic *efx)
{
	efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1,
			  1 << LOOPBACK_NEAR_LBN,
			  efx->loopback_mode == LOOPBACK_PHYXS);
}

static void tenxpress_low_power(struct efx_nic *efx)
{
	efx_mdio_set_mmds_lpower(
		efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
		TENXPRESS_REQUIRED_DEVS);
}

static int tenxpress_phy_reconfigure(struct efx_nic *efx)
{
	struct tenxpress_phy_data *phy_data = efx->phy_data;
	bool phy_mode_change, loop_reset;

	if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
		phy_data->phy_mode = efx->phy_mode;
		return 0;
	}

	phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
			   phy_data->phy_mode != PHY_MODE_NORMAL);
	loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, LOOPBACKS_EXTERNAL(efx)) ||
		      LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));

	if (loop_reset || phy_mode_change) {
		tenxpress_special_reset(efx);
		falcon_reset_xaui(efx);
	}

	tenxpress_low_power(efx);
	efx_mdio_transmit_disable(efx);
	efx_mdio_phy_reconfigure(efx);
	tenxpress_ext_loopback(efx);
	efx_mdio_an_reconfigure(efx);

	phy_data->loopback_mode = efx->loopback_mode;
	phy_data->phy_mode = efx->phy_mode;

	return 0;
}

static void
tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd);

/* Poll for link state changes */
static bool tenxpress_phy_poll(struct efx_nic *efx)
{
	struct efx_link_state old_state = efx->link_state;

	efx->link_state.up = sfx7101_link_ok(efx);
	efx->link_state.speed = 10000;
	efx->link_state.fd = true;
	efx->link_state.fc = efx_mdio_get_pause(efx);

	sfx7101_check_bad_lp(efx, efx->link_state.up);

	return !efx_link_state_equal(&efx->link_state, &old_state);
}

static void sfx7101_phy_fini(struct efx_nic *efx)
{
	int reg;

	/* Power down the LNPGA */
	reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
	efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);

	/* Waiting here ensures that the board fini, which can turn
	 * off the power to the PHY, won't get run until the LNPGA
	 * powerdown has been given long enough to complete. */
	schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
}

static void tenxpress_phy_remove(struct efx_nic *efx)
{
	kfree(efx->phy_data);
	efx->phy_data = NULL;
}


/* Override the RX, TX and link LEDs */
void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
{
	int reg;

	switch (mode) {
	case EFX_LED_OFF:
		reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) |
			(PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) |
			(PMA_PMD_LED_OFF << PMA_PMD_LED_LINK_LBN);
		break;
	case EFX_LED_ON:
		reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) |
			(PMA_PMD_LED_ON << PMA_PMD_LED_RX_LBN) |
			(PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN);
		break;
	default:
		reg = SFX7101_PMA_PMD_LED_DEFAULT;
		break;
	}

	efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg);
}

static const char *const sfx7101_test_names[] = {
	"bist"
};

static const char *sfx7101_test_name(struct efx_nic *efx, unsigned int index)
{
	if (index < ARRAY_SIZE(sfx7101_test_names))
		return sfx7101_test_names[index];
	return NULL;
}

static int
sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags)
{
	int rc;

	if (!(flags & ETH_TEST_FL_OFFLINE))
		return 0;

	/* BIST is automatically run after a special software reset */
	rc = tenxpress_special_reset(efx);
	results[0] = rc ? -1 : 1;

	efx_mdio_an_reconfigure(efx);

	return rc;
}

static void
tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
{
	u32 adv = 0, lpa = 0;
	int reg;

	reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
	if (reg & MDIO_AN_10GBT_CTRL_ADV10G)
		adv |= ADVERTISED_10000baseT_Full;
	reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
	if (reg & MDIO_AN_10GBT_STAT_LP10G)
		lpa |= ADVERTISED_10000baseT_Full;

	mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa);

	/* In loopback, the PHY automatically brings up the correct interface,
	 * but doesn't advertise the correct speed. So override it */
	if (LOOPBACK_EXTERNAL(efx))
		ethtool_cmd_speed_set(ecmd, SPEED_10000);
}

static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
{
	if (!ecmd->autoneg)
		return -EINVAL;

	return efx_mdio_set_settings(efx, ecmd);
}

static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising)
{
	efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
			  MDIO_AN_10GBT_CTRL_ADV10G,
			  advertising & ADVERTISED_10000baseT_Full);
}

const struct efx_phy_operations falcon_sfx7101_phy_ops = {
	.probe		  = tenxpress_phy_probe,
	.init             = tenxpress_phy_init,
	.reconfigure      = tenxpress_phy_reconfigure,
	.poll             = tenxpress_phy_poll,
	.fini             = sfx7101_phy_fini,
	.remove		  = tenxpress_phy_remove,
	.get_settings	  = tenxpress_get_settings,
	.set_settings	  = tenxpress_set_settings,
	.set_npage_adv    = sfx7101_set_npage_adv,
	.test_alive	  = efx_mdio_test_alive,
	.test_name	  = sfx7101_test_name,
	.run_tests	  = sfx7101_run_tests,
};
Commit	Line	Data
8ceee660	1	/****************************************************************************
f7a6d2c4	2	* Driver for Solarflare network controllers and boards
0a6f40c6	3	* Copyright 2007-2011 Solarflare Communications Inc.
8ceee660 BH	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published
	7	* by the Free Software Foundation, incorporated herein by reference.
	8	*/
	9
	10	#include <linux/delay.h>
da3bc071	11	#include <linux/rtnetlink.h>
8ceee660	12	#include <linux/seq_file.h>
5a0e3ad6	13	#include <linux/slab.h>
8ceee660	14	#include "efx.h"
8ceee660	15	#include "mdio_10g.h"
744093c9	16	#include "nic.h"
8ceee660	17	#include "phy.h"
e6fa2eb7	18	#include "workarounds.h"
8ceee660	19
8fbca791	20	/* We expect these MMDs to be in the package. */
68e7f45e BH	21	#define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD \| \
	22	MDIO_DEVS_PCS \| \
	23	MDIO_DEVS_PHYXS \| \
	24	MDIO_DEVS_AN)
8ceee660	25
e6fa2eb7 BH	26	#define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) \| \
	27	(1 << LOOPBACK_PCS) \| \
	28	(1 << LOOPBACK_PMAPMD) \| \
e58f69f4	29	(1 << LOOPBACK_PHYXS_WS))
e6fa2eb7	30
8ceee660 BH	31	/* We complain if we fail to see the link partner as 10G capable this many
	32	* times in a row (must be > 1 as sampling the autoneg. registers is racy)
	33	*/
	34	#define MAX_BAD_LP_TRIES (5)
	35
	36	/* Extended control register */
e6fa2eb7 BH	37	#define PMA_PMD_XCONTROL_REG 49152
	38	#define PMA_PMD_EXT_GMII_EN_LBN 1
	39	#define PMA_PMD_EXT_GMII_EN_WIDTH 1
	40	#define PMA_PMD_EXT_CLK_OUT_LBN 2
	41	#define PMA_PMD_EXT_CLK_OUT_WIDTH 1
8fbca791	42	#define PMA_PMD_LNPGA_POWERDOWN_LBN 8
e6fa2eb7	43	#define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
e6fa2eb7 BH	44	#define PMA_PMD_EXT_CLK312_WIDTH 1
	45	#define PMA_PMD_EXT_LPOWER_LBN 12
	46	#define PMA_PMD_EXT_LPOWER_WIDTH 1
869b5b38 SH	47	#define PMA_PMD_EXT_ROBUST_LBN 14
869b5b38 SH	48	#define PMA_PMD_EXT_ROBUST_WIDTH 1
e6fa2eb7 BH	49	#define PMA_PMD_EXT_SSR_LBN 15
e6fa2eb7 BH	50	#define PMA_PMD_EXT_SSR_WIDTH 1
8ceee660 BH	51
8ceee660 BH	52	/* extended status register */
e6fa2eb7	53	#define PMA_PMD_XSTATUS_REG 49153
e762cd70	54	#define PMA_PMD_XSTAT_MDIX_LBN 14
8ceee660 BH	55	#define PMA_PMD_XSTAT_FLP_LBN (12)
	56
	57	/* LED control register */
e6fa2eb7	58	#define PMA_PMD_LED_CTRL_REG 49159
8ceee660 BH	59	#define PMA_PMA_LED_ACTIVITY_LBN (3)
	60
	61	/* LED function override register */
e6fa2eb7	62	#define PMA_PMD_LED_OVERR_REG 49161
8ceee660 BH	63	/* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
	64	#define PMA_PMD_LED_LINK_LBN (0)
	65	#define PMA_PMD_LED_SPEED_LBN (2)
	66	#define PMA_PMD_LED_TX_LBN (4)
	67	#define PMA_PMD_LED_RX_LBN (6)
	68	/* Override settings */
	69	#define PMA_PMD_LED_AUTO (0) /* H/W control */
	70	#define PMA_PMD_LED_ON (1)
	71	#define PMA_PMD_LED_OFF (2)
	72	#define PMA_PMD_LED_FLASH (3)
04cc8cac	73	#define PMA_PMD_LED_MASK 3
8ceee660	74	/* All LEDs under hardware control */
8ceee660	75	/* Green and Amber under hardware control, Red off */
dcf477b2	76	#define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
8ceee660	77
e6fa2eb7 BH	78	#define PMA_PMD_SPEED_ENABLE_REG 49192
	79	#define PMA_PMD_100TX_ADV_LBN 1
	80	#define PMA_PMD_100TX_ADV_WIDTH 1
	81	#define PMA_PMD_1000T_ADV_LBN 2
	82	#define PMA_PMD_1000T_ADV_WIDTH 1
	83	#define PMA_PMD_10000T_ADV_LBN 3
	84	#define PMA_PMD_10000T_ADV_WIDTH 1
	85	#define PMA_PMD_SPEED_LBN 4
	86	#define PMA_PMD_SPEED_WIDTH 4
	87
8fbca791	88	/* Misc register defines */
e6fa2eb7	89	#define PCS_CLOCK_CTRL_REG 55297
8ceee660 BH	90	#define PLL312_RST_N_LBN 2
8ceee660 BH	91
e6fa2eb7	92	#define PCS_SOFT_RST2_REG 55302
8ceee660 BH	93	#define SERDES_RST_N_LBN 13
	94	#define XGXS_RST_N_LBN 12
	95
e6fa2eb7	96	#define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
8ceee660 BH	97	#define CLK312_EN_LBN 3
8ceee660 BH	98
3273c2e8	99	/* PHYXS registers */
e6fa2eb7 BH	100	#define PHYXS_XCONTROL_REG 49152
	101	#define PHYXS_RESET_LBN 15
	102	#define PHYXS_RESET_WIDTH 1
	103
3273c2e8 BH	104	#define PHYXS_TEST1 (49162)
	105	#define LOOPBACK_NEAR_LBN (8)
	106	#define LOOPBACK_NEAR_WIDTH (1)
	107
8ceee660	108	/* Boot status register */
190dbcfd BH	109	#define PCS_BOOT_STATUS_REG 53248
	110	#define PCS_BOOT_FATAL_ERROR_LBN 0
	111	#define PCS_BOOT_PROGRESS_LBN 1
	112	#define PCS_BOOT_PROGRESS_WIDTH 2
	113	#define PCS_BOOT_PROGRESS_INIT 0
	114	#define PCS_BOOT_PROGRESS_WAIT_MDIO 1
	115	#define PCS_BOOT_PROGRESS_CHECKSUM 2
	116	#define PCS_BOOT_PROGRESS_JUMP 3
	117	#define PCS_BOOT_DOWNLOAD_WAIT_LBN 3
	118	#define PCS_BOOT_CODE_STARTED_LBN 4
8ceee660	119
e6fa2eb7 BH	120	/* 100M/1G PHY registers */
	121	#define GPHY_XCONTROL_REG 49152
	122	#define GPHY_ISOLATE_LBN 10
	123	#define GPHY_ISOLATE_WIDTH 1
9c636baf	124	#define GPHY_DUPLEX_LBN 8
e6fa2eb7 BH	125	#define GPHY_DUPLEX_WIDTH 1
	126	#define GPHY_LOOPBACK_NEAR_LBN 14
	127	#define GPHY_LOOPBACK_NEAR_WIDTH 1
	128
	129	#define C22EXT_STATUS_REG 49153
	130	#define C22EXT_STATUS_LINK_LBN 2
	131	#define C22EXT_STATUS_LINK_WIDTH 1
	132
af4ad9bc BH	133	#define C22EXT_MSTSLV_CTRL 49161
	134	#define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8
	135	#define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9
	136
	137	#define C22EXT_MSTSLV_STATUS 49162
	138	#define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10
	139	#define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11
e6fa2eb7	140
8ceee660 BH	141	/* Time to wait between powering down the LNPGA and turning off the power
	142	* rails */
	143	#define LNPGA_PDOWN_WAIT (HZ / 5)
	144
8ceee660	145	struct tenxpress_phy_data {
3273c2e8	146	enum efx_loopback_mode loopback_mode;
f8b87c17	147	enum efx_phy_mode phy_mode;
8ceee660 BH	148	int bad_lp_tries;
	149	};
	150
8ceee660 BH	151	static int tenxpress_init(struct efx_nic *efx)
8ceee660 BH	152	{
8fbca791 BH	153	/* Enable 312.5 MHz clock */
	154	efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
	155	1 << CLK312_EN_LBN);
8ceee660	156
8ceee660	157	/* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
8fbca791 BH	158	efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG,
	159	1 << PMA_PMA_LED_ACTIVITY_LBN, true);
	160	efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG,
	161	SFX7101_PMA_PMD_LED_DEFAULT);
8ceee660	162
190dbcfd	163	return 0;
8ceee660 BH	164	}
8ceee660 BH	165
ff3b00a0	166	static int tenxpress_phy_probe(struct efx_nic *efx)
c1c4f453	167	{
ff3b00a0	168	struct tenxpress_phy_data *phy_data;
ff3b00a0 SH	169
	170	/* Allocate phy private storage */
	171	phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
	172	if (!phy_data)
	173	return -ENOMEM;
	174	efx->phy_data = phy_data;
	175	phy_data->phy_mode = efx->phy_mode;
	176
8fbca791 BH	177	efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS;
8fbca791 BH	178	efx->mdio.mode_support = MDIO_SUPPORTS_C45;
ff3b00a0	179
8fbca791	180	efx->loopback_modes = SFX7101_LOOPBACKS \| FALCON_XMAC_LOOPBACKS;
ff3b00a0	181
8fbca791 BH	182	efx->link_advertising = (ADVERTISED_TP \| ADVERTISED_Autoneg \|
8fbca791 BH	183	ADVERTISED_10000baseT_Full);
c1c4f453	184
c1c4f453 BH	185	return 0;
	186	}
	187
8ceee660 BH	188	static int tenxpress_phy_init(struct efx_nic *efx)
8ceee660 BH	189	{
ff3b00a0	190	int rc;
8ceee660	191
44838a44	192	falcon_board(efx)->type->init_phy(efx);
981fc1b4	193
e6fa2eb7	194	if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
68e7f45e	195	rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
e6fa2eb7	196	if (rc < 0)
ff3b00a0	197	return rc;
e6fa2eb7	198
a461103b	199	rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS);
e6fa2eb7	200	if (rc < 0)
ff3b00a0	201	return rc;
e6fa2eb7	202	}
8ceee660 BH	203
	204	rc = tenxpress_init(efx);
	205	if (rc < 0)
ff3b00a0	206	return rc;
8ceee660	207
ff3b00a0	208	/* Reinitialise flow control settings */
d3245b28 BH	209	efx_link_set_wanted_fc(efx, efx->wanted_fc);
d3245b28 BH	210	efx_mdio_an_reconfigure(efx);
c634263d	211
8ceee660 BH	212	schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
8ceee660 BH	213
e6fa2eb7	214	/* Let XGXS and SerDes out of reset */
8ceee660 BH	215	falcon_reset_xaui(efx);
	216
	217	return 0;
8ceee660 BH	218	}
8ceee660 BH	219
e6fa2eb7 BH	220	/* Perform a "special software reset" on the PHY. The caller is
	221	* responsible for saving and restoring the PHY hardware registers
	222	* properly, and masking/unmasking LASI */
3273c2e8 BH	223	static int tenxpress_special_reset(struct efx_nic *efx)
	224	{
	225	int rc, reg;
	226
8fbca791	227	/* The XGMAC clock is driven from the SFX7101 312MHz clock, so
c8fcc49c	228	* a special software reset can glitch the XGMAC sufficiently for stats
1974cc20	229	* requests to fail. */
55edc6e6	230	falcon_stop_nic_stats(efx);
3273c2e8 BH	231
3273c2e8 BH	232	/* Initiate reset */
68e7f45e	233	reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
3273c2e8	234	reg \|= (1 << PMA_PMD_EXT_SSR_LBN);
68e7f45e	235	efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
3273c2e8	236
c8fcc49c	237	mdelay(200);
3273c2e8 BH	238
3273c2e8 BH	239	/* Wait for the blocks to come out of reset */
68e7f45e	240	rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
3273c2e8	241	if (rc < 0)
1974cc20	242	goto out;
3273c2e8 BH	243
	244	/* Try and reconfigure the device */
	245	rc = tenxpress_init(efx);
	246	if (rc < 0)
1974cc20	247	goto out;
3273c2e8	248
e6fa2eb7 BH	249	/* Wait for the XGXS state machine to churn */
e6fa2eb7 BH	250	mdelay(10);
1974cc20	251	out:
55edc6e6	252	falcon_start_nic_stats(efx);
c8fcc49c	253	return rc;
3273c2e8 BH	254	}
3273c2e8 BH	255
e6fa2eb7	256	static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
8ceee660 BH	257	{
8ceee660 BH	258	struct tenxpress_phy_data *pd = efx->phy_data;
04cc8cac	259	bool bad_lp;
8ceee660 BH	260	int reg;
8ceee660 BH	261
04cc8cac BH	262	if (link_ok) {
	263	bad_lp = false;
	264	} else {
	265	/* Check that AN has started but not completed. */
68e7f45e BH	266	reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
68e7f45e BH	267	if (!(reg & MDIO_AN_STAT1_LPABLE))
04cc8cac	268	return; /* LP status is unknown */
68e7f45e	269	bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE);
04cc8cac BH	270	if (bad_lp)
	271	pd->bad_lp_tries++;
	272	}
	273
8ceee660	274	/* Nothing to do if all is well and was previously so. */
04cc8cac	275	if (!pd->bad_lp_tries)
8ceee660 BH	276	return;
8ceee660 BH	277
04cc8cac BH	278	/* Use the RX (red) LED as an error indicator once we've seen AN
	279	* failure several times in a row, and also log a message. */
	280	if (!bad_lp \|\| pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
68e7f45e BH	281	reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
68e7f45e BH	282	PMA_PMD_LED_OVERR_REG);
04cc8cac BH	283	reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
	284	if (!bad_lp) {
	285	reg \|= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
	286	} else {
	287	reg \|= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
62776d03 BH	288	netif_err(efx, link, efx->net_dev,
	289	"appears to be plugged into a port"
	290	" that is not 10GBASE-T capable. The PHY"
	291	" supports 10GBASE-T ONLY, so no link can"
	292	" be established\n");
04cc8cac	293	}
68e7f45e BH	294	efx_mdio_write(efx, MDIO_MMD_PMAPMD,
68e7f45e BH	295	PMA_PMD_LED_OVERR_REG, reg);
04cc8cac	296	pd->bad_lp_tries = bad_lp;
8ceee660	297	}
8ceee660 BH	298	}
8ceee660 BH	299
e6fa2eb7	300	static bool sfx7101_link_ok(struct efx_nic *efx)
8ceee660	301	{
68e7f45e BH	302	return efx_mdio_links_ok(efx,
	303	MDIO_DEVS_PMAPMD \|
	304	MDIO_DEVS_PCS \|
	305	MDIO_DEVS_PHYXS);
e6fa2eb7 BH	306	}
e6fa2eb7 BH	307
e6fa2eb7	308	static void tenxpress_ext_loopback(struct efx_nic *efx)
3273c2e8	309	{
68e7f45e BH	310	efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1,
	311	1 << LOOPBACK_NEAR_LBN,
	312	efx->loopback_mode == LOOPBACK_PHYXS);
e6fa2eb7 BH	313	}
	314
	315	static void tenxpress_low_power(struct efx_nic *efx)
	316	{
8fbca791 BH	317	efx_mdio_set_mmds_lpower(
	318	efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
	319	TENXPRESS_REQUIRED_DEVS);
3273c2e8 BH	320	}
3273c2e8 BH	321
d3245b28	322	static int tenxpress_phy_reconfigure(struct efx_nic *efx)
8ceee660	323	{
3273c2e8	324	struct tenxpress_phy_data *phy_data = efx->phy_data;
8b9dc8dd	325	bool phy_mode_change, loop_reset;
3273c2e8	326
e6fa2eb7	327	if (efx->phy_mode & (PHY_MODE_OFF \| PHY_MODE_SPECIAL)) {
f8b87c17	328	phy_data->phy_mode = efx->phy_mode;
d3245b28	329	return 0;
f8b87c17	330	}
8ceee660	331
e6fa2eb7 BH	332	phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
e6fa2eb7 BH	333	phy_data->phy_mode != PHY_MODE_NORMAL);
c1c4f453	334	loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, LOOPBACKS_EXTERNAL(efx)) \|\|
e6fa2eb7 BH	335	LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
e6fa2eb7 BH	336
8b9dc8dd	337	if (loop_reset \|\| phy_mode_change) {
d3245b28	338	tenxpress_special_reset(efx);
8fbca791	339	falcon_reset_xaui(efx);
3273c2e8 BH	340	}
3273c2e8 BH	341
d3245b28	342	tenxpress_low_power(efx);
68e7f45e BH	343	efx_mdio_transmit_disable(efx);
68e7f45e BH	344	efx_mdio_phy_reconfigure(efx);
e6fa2eb7	345	tenxpress_ext_loopback(efx);
d3245b28	346	efx_mdio_an_reconfigure(efx);
3273c2e8	347
3273c2e8	348	phy_data->loopback_mode = efx->loopback_mode;
f8b87c17	349	phy_data->phy_mode = efx->phy_mode;
d3245b28 BH	350
d3245b28 BH	351	return 0;
8ceee660 BH	352	}
8ceee660 BH	353
fdaa9aed SH	354	static void
	355	tenxpress_get_settings(struct efx_nic efx, struct ethtool_cmd ecmd);
	356
	357	/* Poll for link state changes */
	358	static bool tenxpress_phy_poll(struct efx_nic *efx)
8ceee660	359	{
fdaa9aed	360	struct efx_link_state old_state = efx->link_state;
8ceee660	361
8fbca791 BH	362	efx->link_state.up = sfx7101_link_ok(efx);
	363	efx->link_state.speed = 10000;
	364	efx->link_state.fd = true;
	365	efx->link_state.fc = efx_mdio_get_pause(efx);
8ceee660	366
8fbca791	367	sfx7101_check_bad_lp(efx, efx->link_state.up);
fdaa9aed SH	368
fdaa9aed SH	369	return !efx_link_state_equal(&efx->link_state, &old_state);
8ceee660 BH	370	}
8ceee660 BH	371
ff3b00a0	372	static void sfx7101_phy_fini(struct efx_nic *efx)
8ceee660 BH	373	{
	374	int reg;
	375
ff3b00a0 SH	376	/* Power down the LNPGA */
	377	reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
	378	efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
	379
	380	/* Waiting here ensures that the board fini, which can turn
	381	* off the power to the PHY, won't get run until the LNPGA
	382	* powerdown has been given long enough to complete. */
	383	schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
	384	}
	385
	386	static void tenxpress_phy_remove(struct efx_nic *efx)
	387	{
8ceee660 BH	388	kfree(efx->phy_data);
	389	efx->phy_data = NULL;
	390	}
	391
	392
398468ed BH	393	/* Override the RX, TX and link LEDs */
398468ed BH	394	void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
8ceee660 BH	395	{
	396	int reg;
	397
398468ed BH	398	switch (mode) {
	399	case EFX_LED_OFF:
	400	reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) \|
	401	(PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) \|
	402	(PMA_PMD_LED_OFF << PMA_PMD_LED_LINK_LBN);
	403	break;
	404	case EFX_LED_ON:
	405	reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) \|
	406	(PMA_PMD_LED_ON << PMA_PMD_LED_RX_LBN) \|
	407	(PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN);
	408	break;
	409	default:
8fbca791	410	reg = SFX7101_PMA_PMD_LED_DEFAULT;
398468ed BH	411	break;
398468ed BH	412	}
8ceee660	413
68e7f45e	414	efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg);
8ceee660 BH	415	}
8ceee660 BH	416
307505e9	417	static const char *const sfx7101_test_names[] = {
1796721a BH	418	"bist"
	419	};
	420
c1c4f453 BH	421	static const char sfx7101_test_name(struct efx_nic efx, unsigned int index)
	422	{
	423	if (index < ARRAY_SIZE(sfx7101_test_names))
	424	return sfx7101_test_names[index];
	425	return NULL;
	426	}
	427
1796721a	428	static int
307505e9	429	sfx7101_run_tests(struct efx_nic efx, int results, unsigned flags)
8c8661e4	430	{
1796721a BH	431	int rc;
	432
	433	if (!(flags & ETH_TEST_FL_OFFLINE))
	434	return 0;
	435
8c8661e4	436	/* BIST is automatically run after a special software reset */
1796721a BH	437	rc = tenxpress_special_reset(efx);
1796721a BH	438	results[0] = rc ? -1 : 1;
d3245b28 BH	439
	440	efx_mdio_an_reconfigure(efx);
	441
1796721a	442	return rc;
8c8661e4 BH	443	}
8c8661e4 BH	444
af4ad9bc BH	445	static void
af4ad9bc BH	446	tenxpress_get_settings(struct efx_nic efx, struct ethtool_cmd ecmd)
04cc8cac	447	{
af4ad9bc	448	u32 adv = 0, lpa = 0;
04cc8cac BH	449	int reg;
04cc8cac BH	450
68e7f45e BH	451	reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
68e7f45e BH	452	if (reg & MDIO_AN_10GBT_CTRL_ADV10G)
af4ad9bc	453	adv \|= ADVERTISED_10000baseT_Full;
68e7f45e BH	454	reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
68e7f45e BH	455	if (reg & MDIO_AN_10GBT_STAT_LP10G)
04cc8cac	456	lpa \|= ADVERTISED_10000baseT_Full;
04cc8cac	457
68e7f45e	458	mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa);
e6fa2eb7	459
8b9dc8dd SH	460	/* In loopback, the PHY automatically brings up the correct interface,
8b9dc8dd SH	461	* but doesn't advertise the correct speed. So override it */
8fbca791	462	if (LOOPBACK_EXTERNAL(efx))
70739497	463	ethtool_cmd_speed_set(ecmd, SPEED_10000);
04cc8cac BH	464	}
04cc8cac BH	465
af4ad9bc	466	static int tenxpress_set_settings(struct efx_nic efx, struct ethtool_cmd ecmd)
e6fa2eb7	467	{
af4ad9bc BH	468	if (!ecmd->autoneg)
af4ad9bc BH	469	return -EINVAL;
e6fa2eb7	470
68e7f45e	471	return efx_mdio_set_settings(efx, ecmd);
e6fa2eb7 BH	472	}
e6fa2eb7 BH	473
af4ad9bc	474	static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising)
e6fa2eb7	475	{
68e7f45e BH	476	efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
	477	MDIO_AN_10GBT_CTRL_ADV10G,
	478	advertising & ADVERTISED_10000baseT_Full);
e6fa2eb7 BH	479	}
e6fa2eb7 BH	480
6c8c2513	481	const struct efx_phy_operations falcon_sfx7101_phy_ops = {
ff3b00a0	482	.probe = tenxpress_phy_probe,
8ceee660 BH	483	.init = tenxpress_phy_init,
8ceee660 BH	484	.reconfigure = tenxpress_phy_reconfigure,
766ca0fa	485	.poll = tenxpress_phy_poll,
ff3b00a0 SH	486	.fini = sfx7101_phy_fini,
ff3b00a0 SH	487	.remove = tenxpress_phy_remove,
af4ad9bc BH	488	.get_settings = tenxpress_get_settings,
	489	.set_settings = tenxpress_set_settings,
	490	.set_npage_adv = sfx7101_set_npage_adv,
4f16c073	491	.test_alive = efx_mdio_test_alive,
c1c4f453	492	.test_name = sfx7101_test_name,
307505e9	493	.run_tests = sfx7101_run_tests,
e6fa2eb7	494	};