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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2010 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/pci.h> | |
12 | #include <linux/tcp.h> | |
13 | #include <linux/ip.h> | |
14 | #include <linux/in.h> | |
738a8f4b | 15 | #include <linux/ipv6.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
738a8f4b | 17 | #include <net/ipv6.h> |
8ceee660 BH |
18 | #include <linux/if_ether.h> |
19 | #include <linux/highmem.h> | |
20 | #include "net_driver.h" | |
8ceee660 | 21 | #include "efx.h" |
744093c9 | 22 | #include "nic.h" |
8ceee660 BH |
23 | #include "workarounds.h" |
24 | ||
25 | /* | |
26 | * TX descriptor ring full threshold | |
27 | * | |
28 | * The tx_queue descriptor ring fill-level must fall below this value | |
29 | * before we restart the netif queue | |
30 | */ | |
ecc910f5 | 31 | #define EFX_TXQ_THRESHOLD(_efx) ((_efx)->txq_entries / 2u) |
8ceee660 | 32 | |
4d566063 | 33 | static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue, |
c3940999 TH |
34 | struct efx_tx_buffer *buffer, |
35 | unsigned int *pkts_compl, | |
36 | unsigned int *bytes_compl) | |
8ceee660 BH |
37 | { |
38 | if (buffer->unmap_len) { | |
39 | struct pci_dev *pci_dev = tx_queue->efx->pci_dev; | |
cc12dac2 BH |
40 | dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len - |
41 | buffer->unmap_len); | |
8ceee660 | 42 | if (buffer->unmap_single) |
cc12dac2 BH |
43 | pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len, |
44 | PCI_DMA_TODEVICE); | |
8ceee660 | 45 | else |
cc12dac2 BH |
46 | pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len, |
47 | PCI_DMA_TODEVICE); | |
8ceee660 | 48 | buffer->unmap_len = 0; |
dc8cfa55 | 49 | buffer->unmap_single = false; |
8ceee660 BH |
50 | } |
51 | ||
52 | if (buffer->skb) { | |
c3940999 TH |
53 | (*pkts_compl)++; |
54 | (*bytes_compl) += buffer->skb->len; | |
8ceee660 BH |
55 | dev_kfree_skb_any((struct sk_buff *) buffer->skb); |
56 | buffer->skb = NULL; | |
62776d03 BH |
57 | netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev, |
58 | "TX queue %d transmission id %x complete\n", | |
59 | tx_queue->queue, tx_queue->read_count); | |
8ceee660 BH |
60 | } |
61 | } | |
62 | ||
b9b39b62 BH |
63 | /** |
64 | * struct efx_tso_header - a DMA mapped buffer for packet headers | |
65 | * @next: Linked list of free ones. | |
66 | * The list is protected by the TX queue lock. | |
67 | * @dma_unmap_len: Length to unmap for an oversize buffer, or 0. | |
68 | * @dma_addr: The DMA address of the header below. | |
69 | * | |
70 | * This controls the memory used for a TSO header. Use TSOH_DATA() | |
71 | * to find the packet header data. Use TSOH_SIZE() to calculate the | |
72 | * total size required for a given packet header length. TSO headers | |
73 | * in the free list are exactly %TSOH_STD_SIZE bytes in size. | |
74 | */ | |
75 | struct efx_tso_header { | |
76 | union { | |
77 | struct efx_tso_header *next; | |
78 | size_t unmap_len; | |
79 | }; | |
80 | dma_addr_t dma_addr; | |
81 | }; | |
82 | ||
83 | static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, | |
740847da | 84 | struct sk_buff *skb); |
b9b39b62 BH |
85 | static void efx_fini_tso(struct efx_tx_queue *tx_queue); |
86 | static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, | |
87 | struct efx_tso_header *tsoh); | |
88 | ||
4d566063 BH |
89 | static void efx_tsoh_free(struct efx_tx_queue *tx_queue, |
90 | struct efx_tx_buffer *buffer) | |
b9b39b62 BH |
91 | { |
92 | if (buffer->tsoh) { | |
93 | if (likely(!buffer->tsoh->unmap_len)) { | |
94 | buffer->tsoh->next = tx_queue->tso_headers_free; | |
95 | tx_queue->tso_headers_free = buffer->tsoh; | |
96 | } else { | |
97 | efx_tsoh_heap_free(tx_queue, buffer->tsoh); | |
98 | } | |
99 | buffer->tsoh = NULL; | |
100 | } | |
101 | } | |
102 | ||
8ceee660 | 103 | |
63f19884 BH |
104 | static inline unsigned |
105 | efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr) | |
106 | { | |
107 | /* Depending on the NIC revision, we can use descriptor | |
108 | * lengths up to 8K or 8K-1. However, since PCI Express | |
109 | * devices must split read requests at 4K boundaries, there is | |
110 | * little benefit from using descriptors that cross those | |
111 | * boundaries and we keep things simple by not doing so. | |
112 | */ | |
113 | unsigned len = (~dma_addr & 0xfff) + 1; | |
114 | ||
115 | /* Work around hardware bug for unaligned buffers. */ | |
116 | if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf)) | |
117 | len = min_t(unsigned, len, 512 - (dma_addr & 0xf)); | |
118 | ||
119 | return len; | |
120 | } | |
121 | ||
8ceee660 BH |
122 | /* |
123 | * Add a socket buffer to a TX queue | |
124 | * | |
125 | * This maps all fragments of a socket buffer for DMA and adds them to | |
126 | * the TX queue. The queue's insert pointer will be incremented by | |
127 | * the number of fragments in the socket buffer. | |
128 | * | |
129 | * If any DMA mapping fails, any mapped fragments will be unmapped, | |
130 | * the queue's insert pointer will be restored to its original value. | |
131 | * | |
497f5ba3 BH |
132 | * This function is split out from efx_hard_start_xmit to allow the |
133 | * loopback test to direct packets via specific TX queues. | |
134 | * | |
8ceee660 BH |
135 | * Returns NETDEV_TX_OK or NETDEV_TX_BUSY |
136 | * You must hold netif_tx_lock() to call this function. | |
137 | */ | |
497f5ba3 | 138 | netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb) |
8ceee660 BH |
139 | { |
140 | struct efx_nic *efx = tx_queue->efx; | |
141 | struct pci_dev *pci_dev = efx->pci_dev; | |
142 | struct efx_tx_buffer *buffer; | |
143 | skb_frag_t *fragment; | |
63f19884 | 144 | unsigned int len, unmap_len = 0, fill_level, insert_ptr; |
8ceee660 BH |
145 | dma_addr_t dma_addr, unmap_addr = 0; |
146 | unsigned int dma_len; | |
dc8cfa55 | 147 | bool unmap_single; |
8ceee660 | 148 | int q_space, i = 0; |
61357325 | 149 | netdev_tx_t rc = NETDEV_TX_OK; |
8ceee660 BH |
150 | |
151 | EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count); | |
152 | ||
9bc183d7 | 153 | if (skb_shinfo(skb)->gso_size) |
b9b39b62 BH |
154 | return efx_enqueue_skb_tso(tx_queue, skb); |
155 | ||
8ceee660 BH |
156 | /* Get size of the initial fragment */ |
157 | len = skb_headlen(skb); | |
158 | ||
bb145a9e BH |
159 | /* Pad if necessary */ |
160 | if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) { | |
161 | EFX_BUG_ON_PARANOID(skb->data_len); | |
162 | len = 32 + 1; | |
163 | if (skb_pad(skb, len - skb->len)) | |
164 | return NETDEV_TX_OK; | |
165 | } | |
166 | ||
8ceee660 | 167 | fill_level = tx_queue->insert_count - tx_queue->old_read_count; |
ecc910f5 | 168 | q_space = efx->txq_entries - 1 - fill_level; |
8ceee660 BH |
169 | |
170 | /* Map for DMA. Use pci_map_single rather than pci_map_page | |
171 | * since this is more efficient on machines with sparse | |
172 | * memory. | |
173 | */ | |
dc8cfa55 | 174 | unmap_single = true; |
8ceee660 BH |
175 | dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE); |
176 | ||
177 | /* Process all fragments */ | |
178 | while (1) { | |
8d8bb39b | 179 | if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr))) |
8ceee660 BH |
180 | goto pci_err; |
181 | ||
182 | /* Store fields for marking in the per-fragment final | |
183 | * descriptor */ | |
184 | unmap_len = len; | |
185 | unmap_addr = dma_addr; | |
186 | ||
187 | /* Add to TX queue, splitting across DMA boundaries */ | |
188 | do { | |
189 | if (unlikely(q_space-- <= 0)) { | |
190 | /* It might be that completions have | |
191 | * happened since the xmit path last | |
192 | * checked. Update the xmit path's | |
193 | * copy of read_count. | |
194 | */ | |
c04bfc6b | 195 | netif_tx_stop_queue(tx_queue->core_txq); |
8ceee660 | 196 | /* This memory barrier protects the |
c04bfc6b | 197 | * change of queue state from the access |
8ceee660 BH |
198 | * of read_count. */ |
199 | smp_mb(); | |
200 | tx_queue->old_read_count = | |
51c56f40 | 201 | ACCESS_ONCE(tx_queue->read_count); |
8ceee660 BH |
202 | fill_level = (tx_queue->insert_count |
203 | - tx_queue->old_read_count); | |
ecc910f5 | 204 | q_space = efx->txq_entries - 1 - fill_level; |
c04bfc6b BH |
205 | if (unlikely(q_space-- <= 0)) { |
206 | rc = NETDEV_TX_BUSY; | |
207 | goto unwind; | |
208 | } | |
8ceee660 | 209 | smp_mb(); |
e4abce85 BH |
210 | if (likely(!efx->loopback_selftest)) |
211 | netif_tx_start_queue( | |
212 | tx_queue->core_txq); | |
8ceee660 BH |
213 | } |
214 | ||
ecc910f5 | 215 | insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask; |
8ceee660 | 216 | buffer = &tx_queue->buffer[insert_ptr]; |
b9b39b62 BH |
217 | efx_tsoh_free(tx_queue, buffer); |
218 | EFX_BUG_ON_PARANOID(buffer->tsoh); | |
8ceee660 BH |
219 | EFX_BUG_ON_PARANOID(buffer->skb); |
220 | EFX_BUG_ON_PARANOID(buffer->len); | |
dc8cfa55 | 221 | EFX_BUG_ON_PARANOID(!buffer->continuation); |
8ceee660 BH |
222 | EFX_BUG_ON_PARANOID(buffer->unmap_len); |
223 | ||
63f19884 BH |
224 | dma_len = efx_max_tx_len(efx, dma_addr); |
225 | if (likely(dma_len >= len)) | |
8ceee660 BH |
226 | dma_len = len; |
227 | ||
8ceee660 BH |
228 | /* Fill out per descriptor fields */ |
229 | buffer->len = dma_len; | |
230 | buffer->dma_addr = dma_addr; | |
231 | len -= dma_len; | |
232 | dma_addr += dma_len; | |
233 | ++tx_queue->insert_count; | |
234 | } while (len); | |
235 | ||
236 | /* Transfer ownership of the unmapping to the final buffer */ | |
8ceee660 BH |
237 | buffer->unmap_single = unmap_single; |
238 | buffer->unmap_len = unmap_len; | |
239 | unmap_len = 0; | |
240 | ||
241 | /* Get address and size of next fragment */ | |
242 | if (i >= skb_shinfo(skb)->nr_frags) | |
243 | break; | |
244 | fragment = &skb_shinfo(skb)->frags[i]; | |
9e903e08 | 245 | len = skb_frag_size(fragment); |
8ceee660 BH |
246 | i++; |
247 | /* Map for DMA */ | |
dc8cfa55 | 248 | unmap_single = false; |
4a22c4c9 | 249 | dma_addr = skb_frag_dma_map(&pci_dev->dev, fragment, 0, len, |
5d6bcdfe | 250 | DMA_TO_DEVICE); |
8ceee660 BH |
251 | } |
252 | ||
253 | /* Transfer ownership of the skb to the final buffer */ | |
254 | buffer->skb = skb; | |
dc8cfa55 | 255 | buffer->continuation = false; |
8ceee660 | 256 | |
c3940999 TH |
257 | netdev_tx_sent_queue(tx_queue->core_txq, skb->len); |
258 | ||
8ceee660 | 259 | /* Pass off to hardware */ |
152b6a62 | 260 | efx_nic_push_buffers(tx_queue); |
8ceee660 BH |
261 | |
262 | return NETDEV_TX_OK; | |
263 | ||
264 | pci_err: | |
62776d03 BH |
265 | netif_err(efx, tx_err, efx->net_dev, |
266 | " TX queue %d could not map skb with %d bytes %d " | |
267 | "fragments for DMA\n", tx_queue->queue, skb->len, | |
268 | skb_shinfo(skb)->nr_frags + 1); | |
8ceee660 BH |
269 | |
270 | /* Mark the packet as transmitted, and free the SKB ourselves */ | |
9bc183d7 | 271 | dev_kfree_skb_any(skb); |
8ceee660 BH |
272 | |
273 | unwind: | |
274 | /* Work backwards until we hit the original insert pointer value */ | |
275 | while (tx_queue->insert_count != tx_queue->write_count) { | |
c3940999 | 276 | unsigned int pkts_compl = 0, bytes_compl = 0; |
8ceee660 | 277 | --tx_queue->insert_count; |
ecc910f5 | 278 | insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask; |
8ceee660 | 279 | buffer = &tx_queue->buffer[insert_ptr]; |
c3940999 | 280 | efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); |
8ceee660 BH |
281 | buffer->len = 0; |
282 | } | |
283 | ||
284 | /* Free the fragment we were mid-way through pushing */ | |
ecbd95c1 BH |
285 | if (unmap_len) { |
286 | if (unmap_single) | |
287 | pci_unmap_single(pci_dev, unmap_addr, unmap_len, | |
288 | PCI_DMA_TODEVICE); | |
289 | else | |
290 | pci_unmap_page(pci_dev, unmap_addr, unmap_len, | |
291 | PCI_DMA_TODEVICE); | |
292 | } | |
8ceee660 BH |
293 | |
294 | return rc; | |
295 | } | |
296 | ||
297 | /* Remove packets from the TX queue | |
298 | * | |
299 | * This removes packets from the TX queue, up to and including the | |
300 | * specified index. | |
301 | */ | |
4d566063 | 302 | static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue, |
c3940999 TH |
303 | unsigned int index, |
304 | unsigned int *pkts_compl, | |
305 | unsigned int *bytes_compl) | |
8ceee660 BH |
306 | { |
307 | struct efx_nic *efx = tx_queue->efx; | |
308 | unsigned int stop_index, read_ptr; | |
8ceee660 | 309 | |
ecc910f5 SH |
310 | stop_index = (index + 1) & tx_queue->ptr_mask; |
311 | read_ptr = tx_queue->read_count & tx_queue->ptr_mask; | |
8ceee660 BH |
312 | |
313 | while (read_ptr != stop_index) { | |
314 | struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr]; | |
315 | if (unlikely(buffer->len == 0)) { | |
62776d03 BH |
316 | netif_err(efx, tx_err, efx->net_dev, |
317 | "TX queue %d spurious TX completion id %x\n", | |
318 | tx_queue->queue, read_ptr); | |
8ceee660 BH |
319 | efx_schedule_reset(efx, RESET_TYPE_TX_SKIP); |
320 | return; | |
321 | } | |
322 | ||
c3940999 | 323 | efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl); |
dc8cfa55 | 324 | buffer->continuation = true; |
8ceee660 BH |
325 | buffer->len = 0; |
326 | ||
327 | ++tx_queue->read_count; | |
ecc910f5 | 328 | read_ptr = tx_queue->read_count & tx_queue->ptr_mask; |
8ceee660 BH |
329 | } |
330 | } | |
331 | ||
8ceee660 BH |
332 | /* Initiate a packet transmission. We use one channel per CPU |
333 | * (sharing when we have more CPUs than channels). On Falcon, the TX | |
334 | * completion events will be directed back to the CPU that transmitted | |
335 | * the packet, which should be cache-efficient. | |
336 | * | |
337 | * Context: non-blocking. | |
338 | * Note that returning anything other than NETDEV_TX_OK will cause the | |
339 | * OS to free the skb. | |
340 | */ | |
61357325 SH |
341 | netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb, |
342 | struct net_device *net_dev) | |
8ceee660 | 343 | { |
767e468c | 344 | struct efx_nic *efx = netdev_priv(net_dev); |
60ac1065 | 345 | struct efx_tx_queue *tx_queue; |
94b274bf | 346 | unsigned index, type; |
60ac1065 | 347 | |
e4abce85 | 348 | EFX_WARN_ON_PARANOID(!netif_device_present(net_dev)); |
a7ef5933 | 349 | |
94b274bf BH |
350 | index = skb_get_queue_mapping(skb); |
351 | type = skb->ip_summed == CHECKSUM_PARTIAL ? EFX_TXQ_TYPE_OFFLOAD : 0; | |
352 | if (index >= efx->n_tx_channels) { | |
353 | index -= efx->n_tx_channels; | |
354 | type |= EFX_TXQ_TYPE_HIGHPRI; | |
355 | } | |
356 | tx_queue = efx_get_tx_queue(efx, index, type); | |
60ac1065 | 357 | |
497f5ba3 | 358 | return efx_enqueue_skb(tx_queue, skb); |
8ceee660 BH |
359 | } |
360 | ||
60031fcc BH |
361 | void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue) |
362 | { | |
94b274bf BH |
363 | struct efx_nic *efx = tx_queue->efx; |
364 | ||
60031fcc | 365 | /* Must be inverse of queue lookup in efx_hard_start_xmit() */ |
94b274bf BH |
366 | tx_queue->core_txq = |
367 | netdev_get_tx_queue(efx->net_dev, | |
368 | tx_queue->queue / EFX_TXQ_TYPES + | |
369 | ((tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ? | |
370 | efx->n_tx_channels : 0)); | |
371 | } | |
372 | ||
373 | int efx_setup_tc(struct net_device *net_dev, u8 num_tc) | |
374 | { | |
375 | struct efx_nic *efx = netdev_priv(net_dev); | |
376 | struct efx_channel *channel; | |
377 | struct efx_tx_queue *tx_queue; | |
378 | unsigned tc; | |
379 | int rc; | |
380 | ||
381 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0 || num_tc > EFX_MAX_TX_TC) | |
382 | return -EINVAL; | |
383 | ||
384 | if (num_tc == net_dev->num_tc) | |
385 | return 0; | |
386 | ||
387 | for (tc = 0; tc < num_tc; tc++) { | |
388 | net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels; | |
389 | net_dev->tc_to_txq[tc].count = efx->n_tx_channels; | |
390 | } | |
391 | ||
392 | if (num_tc > net_dev->num_tc) { | |
393 | /* Initialise high-priority queues as necessary */ | |
394 | efx_for_each_channel(channel, efx) { | |
395 | efx_for_each_possible_channel_tx_queue(tx_queue, | |
396 | channel) { | |
397 | if (!(tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI)) | |
398 | continue; | |
399 | if (!tx_queue->buffer) { | |
400 | rc = efx_probe_tx_queue(tx_queue); | |
401 | if (rc) | |
402 | return rc; | |
403 | } | |
404 | if (!tx_queue->initialised) | |
405 | efx_init_tx_queue(tx_queue); | |
406 | efx_init_tx_queue_core_txq(tx_queue); | |
407 | } | |
408 | } | |
409 | } else { | |
410 | /* Reduce number of classes before number of queues */ | |
411 | net_dev->num_tc = num_tc; | |
412 | } | |
413 | ||
414 | rc = netif_set_real_num_tx_queues(net_dev, | |
415 | max_t(int, num_tc, 1) * | |
416 | efx->n_tx_channels); | |
417 | if (rc) | |
418 | return rc; | |
419 | ||
420 | /* Do not destroy high-priority queues when they become | |
421 | * unused. We would have to flush them first, and it is | |
422 | * fairly difficult to flush a subset of TX queues. Leave | |
423 | * it to efx_fini_channels(). | |
424 | */ | |
425 | ||
426 | net_dev->num_tc = num_tc; | |
427 | return 0; | |
60031fcc BH |
428 | } |
429 | ||
8ceee660 BH |
430 | void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index) |
431 | { | |
432 | unsigned fill_level; | |
433 | struct efx_nic *efx = tx_queue->efx; | |
c3940999 | 434 | unsigned int pkts_compl = 0, bytes_compl = 0; |
8ceee660 | 435 | |
ecc910f5 | 436 | EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask); |
8ceee660 | 437 | |
c3940999 TH |
438 | efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl); |
439 | netdev_tx_completed_queue(tx_queue->core_txq, pkts_compl, bytes_compl); | |
8ceee660 BH |
440 | |
441 | /* See if we need to restart the netif queue. This barrier | |
c04bfc6b BH |
442 | * separates the update of read_count from the test of the |
443 | * queue state. */ | |
8ceee660 | 444 | smp_mb(); |
c04bfc6b | 445 | if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) && |
9d1aea62 | 446 | likely(efx->port_enabled) && |
e4abce85 | 447 | likely(netif_device_present(efx->net_dev))) { |
8ceee660 | 448 | fill_level = tx_queue->insert_count - tx_queue->read_count; |
ecc910f5 | 449 | if (fill_level < EFX_TXQ_THRESHOLD(efx)) { |
55668611 | 450 | EFX_BUG_ON_PARANOID(!efx_dev_registered(efx)); |
c04bfc6b | 451 | netif_tx_wake_queue(tx_queue->core_txq); |
8ceee660 BH |
452 | } |
453 | } | |
cd38557d BH |
454 | |
455 | /* Check whether the hardware queue is now empty */ | |
456 | if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) { | |
457 | tx_queue->old_write_count = ACCESS_ONCE(tx_queue->write_count); | |
458 | if (tx_queue->read_count == tx_queue->old_write_count) { | |
459 | smp_mb(); | |
460 | tx_queue->empty_read_count = | |
461 | tx_queue->read_count | EFX_EMPTY_COUNT_VALID; | |
462 | } | |
463 | } | |
8ceee660 BH |
464 | } |
465 | ||
466 | int efx_probe_tx_queue(struct efx_tx_queue *tx_queue) | |
467 | { | |
468 | struct efx_nic *efx = tx_queue->efx; | |
ecc910f5 | 469 | unsigned int entries; |
8ceee660 BH |
470 | int i, rc; |
471 | ||
ecc910f5 SH |
472 | /* Create the smallest power-of-two aligned ring */ |
473 | entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE); | |
474 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE); | |
475 | tx_queue->ptr_mask = entries - 1; | |
476 | ||
477 | netif_dbg(efx, probe, efx->net_dev, | |
478 | "creating TX queue %d size %#x mask %#x\n", | |
479 | tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask); | |
8ceee660 BH |
480 | |
481 | /* Allocate software ring */ | |
ecc910f5 SH |
482 | tx_queue->buffer = kzalloc(entries * sizeof(*tx_queue->buffer), |
483 | GFP_KERNEL); | |
60ac1065 BH |
484 | if (!tx_queue->buffer) |
485 | return -ENOMEM; | |
ecc910f5 | 486 | for (i = 0; i <= tx_queue->ptr_mask; ++i) |
dc8cfa55 | 487 | tx_queue->buffer[i].continuation = true; |
8ceee660 BH |
488 | |
489 | /* Allocate hardware ring */ | |
152b6a62 | 490 | rc = efx_nic_probe_tx(tx_queue); |
8ceee660 | 491 | if (rc) |
60ac1065 | 492 | goto fail; |
8ceee660 BH |
493 | |
494 | return 0; | |
495 | ||
60ac1065 | 496 | fail: |
8ceee660 BH |
497 | kfree(tx_queue->buffer); |
498 | tx_queue->buffer = NULL; | |
8ceee660 BH |
499 | return rc; |
500 | } | |
501 | ||
bc3c90a2 | 502 | void efx_init_tx_queue(struct efx_tx_queue *tx_queue) |
8ceee660 | 503 | { |
62776d03 BH |
504 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
505 | "initialising TX queue %d\n", tx_queue->queue); | |
8ceee660 BH |
506 | |
507 | tx_queue->insert_count = 0; | |
508 | tx_queue->write_count = 0; | |
cd38557d | 509 | tx_queue->old_write_count = 0; |
8ceee660 BH |
510 | tx_queue->read_count = 0; |
511 | tx_queue->old_read_count = 0; | |
cd38557d | 512 | tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID; |
8ceee660 BH |
513 | |
514 | /* Set up TX descriptor ring */ | |
152b6a62 | 515 | efx_nic_init_tx(tx_queue); |
94b274bf BH |
516 | |
517 | tx_queue->initialised = true; | |
8ceee660 BH |
518 | } |
519 | ||
520 | void efx_release_tx_buffers(struct efx_tx_queue *tx_queue) | |
521 | { | |
522 | struct efx_tx_buffer *buffer; | |
523 | ||
524 | if (!tx_queue->buffer) | |
525 | return; | |
526 | ||
527 | /* Free any buffers left in the ring */ | |
528 | while (tx_queue->read_count != tx_queue->write_count) { | |
c3940999 | 529 | unsigned int pkts_compl = 0, bytes_compl = 0; |
ecc910f5 | 530 | buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask]; |
c3940999 | 531 | efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); |
dc8cfa55 | 532 | buffer->continuation = true; |
8ceee660 BH |
533 | buffer->len = 0; |
534 | ||
535 | ++tx_queue->read_count; | |
536 | } | |
c3940999 | 537 | netdev_tx_reset_queue(tx_queue->core_txq); |
8ceee660 BH |
538 | } |
539 | ||
540 | void efx_fini_tx_queue(struct efx_tx_queue *tx_queue) | |
541 | { | |
94b274bf BH |
542 | if (!tx_queue->initialised) |
543 | return; | |
544 | ||
62776d03 BH |
545 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
546 | "shutting down TX queue %d\n", tx_queue->queue); | |
8ceee660 | 547 | |
94b274bf BH |
548 | tx_queue->initialised = false; |
549 | ||
8ceee660 | 550 | /* Flush TX queue, remove descriptor ring */ |
152b6a62 | 551 | efx_nic_fini_tx(tx_queue); |
8ceee660 BH |
552 | |
553 | efx_release_tx_buffers(tx_queue); | |
554 | ||
b9b39b62 BH |
555 | /* Free up TSO header cache */ |
556 | efx_fini_tso(tx_queue); | |
8ceee660 BH |
557 | } |
558 | ||
559 | void efx_remove_tx_queue(struct efx_tx_queue *tx_queue) | |
560 | { | |
94b274bf BH |
561 | if (!tx_queue->buffer) |
562 | return; | |
563 | ||
62776d03 BH |
564 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
565 | "destroying TX queue %d\n", tx_queue->queue); | |
152b6a62 | 566 | efx_nic_remove_tx(tx_queue); |
8ceee660 BH |
567 | |
568 | kfree(tx_queue->buffer); | |
569 | tx_queue->buffer = NULL; | |
8ceee660 BH |
570 | } |
571 | ||
572 | ||
b9b39b62 BH |
573 | /* Efx TCP segmentation acceleration. |
574 | * | |
575 | * Why? Because by doing it here in the driver we can go significantly | |
576 | * faster than the GSO. | |
577 | * | |
578 | * Requires TX checksum offload support. | |
579 | */ | |
580 | ||
581 | /* Number of bytes inserted at the start of a TSO header buffer, | |
582 | * similar to NET_IP_ALIGN. | |
583 | */ | |
13e9ab11 | 584 | #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
b9b39b62 BH |
585 | #define TSOH_OFFSET 0 |
586 | #else | |
587 | #define TSOH_OFFSET NET_IP_ALIGN | |
588 | #endif | |
589 | ||
590 | #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET) | |
591 | ||
592 | /* Total size of struct efx_tso_header, buffer and padding */ | |
593 | #define TSOH_SIZE(hdr_len) \ | |
594 | (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len) | |
595 | ||
596 | /* Size of blocks on free list. Larger blocks must be allocated from | |
597 | * the heap. | |
598 | */ | |
599 | #define TSOH_STD_SIZE 128 | |
600 | ||
601 | #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2)) | |
602 | #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data) | |
603 | #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data) | |
604 | #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data) | |
738a8f4b | 605 | #define SKB_IPV6_OFF(skb) PTR_DIFF(ipv6_hdr(skb), (skb)->data) |
b9b39b62 BH |
606 | |
607 | /** | |
608 | * struct tso_state - TSO state for an SKB | |
23d9e60b | 609 | * @out_len: Remaining length in current segment |
b9b39b62 | 610 | * @seqnum: Current sequence number |
23d9e60b | 611 | * @ipv4_id: Current IPv4 ID, host endian |
b9b39b62 | 612 | * @packet_space: Remaining space in current packet |
23d9e60b BH |
613 | * @dma_addr: DMA address of current position |
614 | * @in_len: Remaining length in current SKB fragment | |
615 | * @unmap_len: Length of SKB fragment | |
616 | * @unmap_addr: DMA address of SKB fragment | |
617 | * @unmap_single: DMA single vs page mapping flag | |
738a8f4b | 618 | * @protocol: Network protocol (after any VLAN header) |
23d9e60b BH |
619 | * @header_len: Number of bytes of header |
620 | * @full_packet_size: Number of bytes to put in each outgoing segment | |
b9b39b62 BH |
621 | * |
622 | * The state used during segmentation. It is put into this data structure | |
623 | * just to make it easy to pass into inline functions. | |
624 | */ | |
625 | struct tso_state { | |
23d9e60b BH |
626 | /* Output position */ |
627 | unsigned out_len; | |
b9b39b62 | 628 | unsigned seqnum; |
23d9e60b | 629 | unsigned ipv4_id; |
b9b39b62 BH |
630 | unsigned packet_space; |
631 | ||
23d9e60b BH |
632 | /* Input position */ |
633 | dma_addr_t dma_addr; | |
634 | unsigned in_len; | |
635 | unsigned unmap_len; | |
636 | dma_addr_t unmap_addr; | |
637 | bool unmap_single; | |
638 | ||
738a8f4b | 639 | __be16 protocol; |
23d9e60b BH |
640 | unsigned header_len; |
641 | int full_packet_size; | |
b9b39b62 BH |
642 | }; |
643 | ||
644 | ||
645 | /* | |
646 | * Verify that our various assumptions about sk_buffs and the conditions | |
738a8f4b | 647 | * under which TSO will be attempted hold true. Return the protocol number. |
b9b39b62 | 648 | */ |
738a8f4b | 649 | static __be16 efx_tso_check_protocol(struct sk_buff *skb) |
b9b39b62 | 650 | { |
740847da BH |
651 | __be16 protocol = skb->protocol; |
652 | ||
b9b39b62 | 653 | EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto != |
740847da BH |
654 | protocol); |
655 | if (protocol == htons(ETH_P_8021Q)) { | |
656 | /* Find the encapsulated protocol; reset network header | |
657 | * and transport header based on that. */ | |
658 | struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data; | |
659 | protocol = veh->h_vlan_encapsulated_proto; | |
660 | skb_set_network_header(skb, sizeof(*veh)); | |
661 | if (protocol == htons(ETH_P_IP)) | |
662 | skb_set_transport_header(skb, sizeof(*veh) + | |
663 | 4 * ip_hdr(skb)->ihl); | |
738a8f4b BH |
664 | else if (protocol == htons(ETH_P_IPV6)) |
665 | skb_set_transport_header(skb, sizeof(*veh) + | |
666 | sizeof(struct ipv6hdr)); | |
740847da BH |
667 | } |
668 | ||
738a8f4b BH |
669 | if (protocol == htons(ETH_P_IP)) { |
670 | EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP); | |
671 | } else { | |
672 | EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6)); | |
673 | EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP); | |
674 | } | |
b9b39b62 BH |
675 | EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data) |
676 | + (tcp_hdr(skb)->doff << 2u)) > | |
677 | skb_headlen(skb)); | |
738a8f4b BH |
678 | |
679 | return protocol; | |
b9b39b62 BH |
680 | } |
681 | ||
682 | ||
683 | /* | |
684 | * Allocate a page worth of efx_tso_header structures, and string them | |
685 | * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM. | |
686 | */ | |
687 | static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue) | |
688 | { | |
689 | ||
690 | struct pci_dev *pci_dev = tx_queue->efx->pci_dev; | |
691 | struct efx_tso_header *tsoh; | |
692 | dma_addr_t dma_addr; | |
693 | u8 *base_kva, *kva; | |
694 | ||
695 | base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr); | |
696 | if (base_kva == NULL) { | |
62776d03 BH |
697 | netif_err(tx_queue->efx, tx_err, tx_queue->efx->net_dev, |
698 | "Unable to allocate page for TSO headers\n"); | |
b9b39b62 BH |
699 | return -ENOMEM; |
700 | } | |
701 | ||
702 | /* pci_alloc_consistent() allocates pages. */ | |
703 | EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u)); | |
704 | ||
705 | for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) { | |
706 | tsoh = (struct efx_tso_header *)kva; | |
707 | tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva); | |
708 | tsoh->next = tx_queue->tso_headers_free; | |
709 | tx_queue->tso_headers_free = tsoh; | |
710 | } | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
715 | ||
716 | /* Free up a TSO header, and all others in the same page. */ | |
717 | static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue, | |
718 | struct efx_tso_header *tsoh, | |
719 | struct pci_dev *pci_dev) | |
720 | { | |
721 | struct efx_tso_header **p; | |
722 | unsigned long base_kva; | |
723 | dma_addr_t base_dma; | |
724 | ||
725 | base_kva = (unsigned long)tsoh & PAGE_MASK; | |
726 | base_dma = tsoh->dma_addr & PAGE_MASK; | |
727 | ||
728 | p = &tx_queue->tso_headers_free; | |
b3475645 | 729 | while (*p != NULL) { |
b9b39b62 BH |
730 | if (((unsigned long)*p & PAGE_MASK) == base_kva) |
731 | *p = (*p)->next; | |
732 | else | |
733 | p = &(*p)->next; | |
b3475645 | 734 | } |
b9b39b62 BH |
735 | |
736 | pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma); | |
737 | } | |
738 | ||
739 | static struct efx_tso_header * | |
740 | efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len) | |
741 | { | |
742 | struct efx_tso_header *tsoh; | |
743 | ||
744 | tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA); | |
745 | if (unlikely(!tsoh)) | |
746 | return NULL; | |
747 | ||
748 | tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev, | |
749 | TSOH_BUFFER(tsoh), header_len, | |
750 | PCI_DMA_TODEVICE); | |
8d8bb39b FT |
751 | if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev, |
752 | tsoh->dma_addr))) { | |
b9b39b62 BH |
753 | kfree(tsoh); |
754 | return NULL; | |
755 | } | |
756 | ||
757 | tsoh->unmap_len = header_len; | |
758 | return tsoh; | |
759 | } | |
760 | ||
761 | static void | |
762 | efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh) | |
763 | { | |
764 | pci_unmap_single(tx_queue->efx->pci_dev, | |
765 | tsoh->dma_addr, tsoh->unmap_len, | |
766 | PCI_DMA_TODEVICE); | |
767 | kfree(tsoh); | |
768 | } | |
769 | ||
770 | /** | |
771 | * efx_tx_queue_insert - push descriptors onto the TX queue | |
772 | * @tx_queue: Efx TX queue | |
773 | * @dma_addr: DMA address of fragment | |
774 | * @len: Length of fragment | |
ecbd95c1 | 775 | * @final_buffer: The final buffer inserted into the queue |
b9b39b62 BH |
776 | * |
777 | * Push descriptors onto the TX queue. Return 0 on success or 1 if | |
778 | * @tx_queue full. | |
779 | */ | |
780 | static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue, | |
781 | dma_addr_t dma_addr, unsigned len, | |
ecbd95c1 | 782 | struct efx_tx_buffer **final_buffer) |
b9b39b62 BH |
783 | { |
784 | struct efx_tx_buffer *buffer; | |
785 | struct efx_nic *efx = tx_queue->efx; | |
63f19884 | 786 | unsigned dma_len, fill_level, insert_ptr; |
b9b39b62 BH |
787 | int q_space; |
788 | ||
789 | EFX_BUG_ON_PARANOID(len <= 0); | |
790 | ||
791 | fill_level = tx_queue->insert_count - tx_queue->old_read_count; | |
792 | /* -1 as there is no way to represent all descriptors used */ | |
ecc910f5 | 793 | q_space = efx->txq_entries - 1 - fill_level; |
b9b39b62 BH |
794 | |
795 | while (1) { | |
796 | if (unlikely(q_space-- <= 0)) { | |
797 | /* It might be that completions have happened | |
798 | * since the xmit path last checked. Update | |
799 | * the xmit path's copy of read_count. | |
800 | */ | |
c04bfc6b | 801 | netif_tx_stop_queue(tx_queue->core_txq); |
b9b39b62 | 802 | /* This memory barrier protects the change of |
c04bfc6b | 803 | * queue state from the access of read_count. */ |
b9b39b62 BH |
804 | smp_mb(); |
805 | tx_queue->old_read_count = | |
51c56f40 | 806 | ACCESS_ONCE(tx_queue->read_count); |
b9b39b62 BH |
807 | fill_level = (tx_queue->insert_count |
808 | - tx_queue->old_read_count); | |
ecc910f5 | 809 | q_space = efx->txq_entries - 1 - fill_level; |
ecbd95c1 BH |
810 | if (unlikely(q_space-- <= 0)) { |
811 | *final_buffer = NULL; | |
b9b39b62 | 812 | return 1; |
ecbd95c1 | 813 | } |
b9b39b62 | 814 | smp_mb(); |
c04bfc6b | 815 | netif_tx_start_queue(tx_queue->core_txq); |
b9b39b62 BH |
816 | } |
817 | ||
ecc910f5 | 818 | insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask; |
b9b39b62 BH |
819 | buffer = &tx_queue->buffer[insert_ptr]; |
820 | ++tx_queue->insert_count; | |
821 | ||
822 | EFX_BUG_ON_PARANOID(tx_queue->insert_count - | |
ecc910f5 SH |
823 | tx_queue->read_count >= |
824 | efx->txq_entries); | |
b9b39b62 BH |
825 | |
826 | efx_tsoh_free(tx_queue, buffer); | |
827 | EFX_BUG_ON_PARANOID(buffer->len); | |
828 | EFX_BUG_ON_PARANOID(buffer->unmap_len); | |
829 | EFX_BUG_ON_PARANOID(buffer->skb); | |
dc8cfa55 | 830 | EFX_BUG_ON_PARANOID(!buffer->continuation); |
b9b39b62 BH |
831 | EFX_BUG_ON_PARANOID(buffer->tsoh); |
832 | ||
833 | buffer->dma_addr = dma_addr; | |
834 | ||
63f19884 | 835 | dma_len = efx_max_tx_len(efx, dma_addr); |
b9b39b62 BH |
836 | |
837 | /* If there is enough space to send then do so */ | |
838 | if (dma_len >= len) | |
839 | break; | |
840 | ||
841 | buffer->len = dma_len; /* Don't set the other members */ | |
842 | dma_addr += dma_len; | |
843 | len -= dma_len; | |
844 | } | |
845 | ||
846 | EFX_BUG_ON_PARANOID(!len); | |
847 | buffer->len = len; | |
ecbd95c1 | 848 | *final_buffer = buffer; |
b9b39b62 BH |
849 | return 0; |
850 | } | |
851 | ||
852 | ||
853 | /* | |
854 | * Put a TSO header into the TX queue. | |
855 | * | |
856 | * This is special-cased because we know that it is small enough to fit in | |
857 | * a single fragment, and we know it doesn't cross a page boundary. It | |
858 | * also allows us to not worry about end-of-packet etc. | |
859 | */ | |
4d566063 BH |
860 | static void efx_tso_put_header(struct efx_tx_queue *tx_queue, |
861 | struct efx_tso_header *tsoh, unsigned len) | |
b9b39b62 BH |
862 | { |
863 | struct efx_tx_buffer *buffer; | |
864 | ||
ecc910f5 | 865 | buffer = &tx_queue->buffer[tx_queue->insert_count & tx_queue->ptr_mask]; |
b9b39b62 BH |
866 | efx_tsoh_free(tx_queue, buffer); |
867 | EFX_BUG_ON_PARANOID(buffer->len); | |
868 | EFX_BUG_ON_PARANOID(buffer->unmap_len); | |
869 | EFX_BUG_ON_PARANOID(buffer->skb); | |
dc8cfa55 | 870 | EFX_BUG_ON_PARANOID(!buffer->continuation); |
b9b39b62 BH |
871 | EFX_BUG_ON_PARANOID(buffer->tsoh); |
872 | buffer->len = len; | |
873 | buffer->dma_addr = tsoh->dma_addr; | |
874 | buffer->tsoh = tsoh; | |
875 | ||
876 | ++tx_queue->insert_count; | |
877 | } | |
878 | ||
879 | ||
880 | /* Remove descriptors put into a tx_queue. */ | |
881 | static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue) | |
882 | { | |
883 | struct efx_tx_buffer *buffer; | |
cc12dac2 | 884 | dma_addr_t unmap_addr; |
b9b39b62 BH |
885 | |
886 | /* Work backwards until we hit the original insert pointer value */ | |
887 | while (tx_queue->insert_count != tx_queue->write_count) { | |
888 | --tx_queue->insert_count; | |
889 | buffer = &tx_queue->buffer[tx_queue->insert_count & | |
ecc910f5 | 890 | tx_queue->ptr_mask]; |
b9b39b62 BH |
891 | efx_tsoh_free(tx_queue, buffer); |
892 | EFX_BUG_ON_PARANOID(buffer->skb); | |
b9b39b62 | 893 | if (buffer->unmap_len) { |
cc12dac2 BH |
894 | unmap_addr = (buffer->dma_addr + buffer->len - |
895 | buffer->unmap_len); | |
ecbd95c1 BH |
896 | if (buffer->unmap_single) |
897 | pci_unmap_single(tx_queue->efx->pci_dev, | |
cc12dac2 | 898 | unmap_addr, buffer->unmap_len, |
ecbd95c1 BH |
899 | PCI_DMA_TODEVICE); |
900 | else | |
901 | pci_unmap_page(tx_queue->efx->pci_dev, | |
cc12dac2 | 902 | unmap_addr, buffer->unmap_len, |
ecbd95c1 | 903 | PCI_DMA_TODEVICE); |
b9b39b62 BH |
904 | buffer->unmap_len = 0; |
905 | } | |
a7ebd27a NT |
906 | buffer->len = 0; |
907 | buffer->continuation = true; | |
b9b39b62 BH |
908 | } |
909 | } | |
910 | ||
911 | ||
912 | /* Parse the SKB header and initialise state. */ | |
4d566063 | 913 | static void tso_start(struct tso_state *st, const struct sk_buff *skb) |
b9b39b62 BH |
914 | { |
915 | /* All ethernet/IP/TCP headers combined size is TCP header size | |
916 | * plus offset of TCP header relative to start of packet. | |
917 | */ | |
23d9e60b BH |
918 | st->header_len = ((tcp_hdr(skb)->doff << 2u) |
919 | + PTR_DIFF(tcp_hdr(skb), skb->data)); | |
920 | st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size; | |
b9b39b62 | 921 | |
738a8f4b BH |
922 | if (st->protocol == htons(ETH_P_IP)) |
923 | st->ipv4_id = ntohs(ip_hdr(skb)->id); | |
924 | else | |
925 | st->ipv4_id = 0; | |
b9b39b62 BH |
926 | st->seqnum = ntohl(tcp_hdr(skb)->seq); |
927 | ||
928 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg); | |
929 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn); | |
930 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst); | |
931 | ||
23d9e60b BH |
932 | st->packet_space = st->full_packet_size; |
933 | st->out_len = skb->len - st->header_len; | |
934 | st->unmap_len = 0; | |
935 | st->unmap_single = false; | |
b9b39b62 BH |
936 | } |
937 | ||
4d566063 BH |
938 | static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx, |
939 | skb_frag_t *frag) | |
b9b39b62 | 940 | { |
4a22c4c9 | 941 | st->unmap_addr = skb_frag_dma_map(&efx->pci_dev->dev, frag, 0, |
9e903e08 | 942 | skb_frag_size(frag), DMA_TO_DEVICE); |
5d6bcdfe | 943 | if (likely(!dma_mapping_error(&efx->pci_dev->dev, st->unmap_addr))) { |
23d9e60b | 944 | st->unmap_single = false; |
9e903e08 ED |
945 | st->unmap_len = skb_frag_size(frag); |
946 | st->in_len = skb_frag_size(frag); | |
23d9e60b | 947 | st->dma_addr = st->unmap_addr; |
ecbd95c1 BH |
948 | return 0; |
949 | } | |
950 | return -ENOMEM; | |
951 | } | |
952 | ||
4d566063 BH |
953 | static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx, |
954 | const struct sk_buff *skb) | |
ecbd95c1 | 955 | { |
23d9e60b | 956 | int hl = st->header_len; |
ecbd95c1 | 957 | int len = skb_headlen(skb) - hl; |
b9b39b62 | 958 | |
23d9e60b BH |
959 | st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl, |
960 | len, PCI_DMA_TODEVICE); | |
961 | if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) { | |
962 | st->unmap_single = true; | |
963 | st->unmap_len = len; | |
964 | st->in_len = len; | |
965 | st->dma_addr = st->unmap_addr; | |
b9b39b62 BH |
966 | return 0; |
967 | } | |
968 | return -ENOMEM; | |
969 | } | |
970 | ||
971 | ||
972 | /** | |
973 | * tso_fill_packet_with_fragment - form descriptors for the current fragment | |
974 | * @tx_queue: Efx TX queue | |
975 | * @skb: Socket buffer | |
976 | * @st: TSO state | |
977 | * | |
978 | * Form descriptors for the current fragment, until we reach the end | |
979 | * of fragment or end-of-packet. Return 0 on success, 1 if not enough | |
980 | * space in @tx_queue. | |
981 | */ | |
4d566063 BH |
982 | static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue, |
983 | const struct sk_buff *skb, | |
984 | struct tso_state *st) | |
b9b39b62 | 985 | { |
ecbd95c1 | 986 | struct efx_tx_buffer *buffer; |
b9b39b62 BH |
987 | int n, end_of_packet, rc; |
988 | ||
23d9e60b | 989 | if (st->in_len == 0) |
b9b39b62 BH |
990 | return 0; |
991 | if (st->packet_space == 0) | |
992 | return 0; | |
993 | ||
23d9e60b | 994 | EFX_BUG_ON_PARANOID(st->in_len <= 0); |
b9b39b62 BH |
995 | EFX_BUG_ON_PARANOID(st->packet_space <= 0); |
996 | ||
23d9e60b | 997 | n = min(st->in_len, st->packet_space); |
b9b39b62 BH |
998 | |
999 | st->packet_space -= n; | |
23d9e60b BH |
1000 | st->out_len -= n; |
1001 | st->in_len -= n; | |
b9b39b62 | 1002 | |
23d9e60b | 1003 | rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer); |
ecbd95c1 | 1004 | if (likely(rc == 0)) { |
23d9e60b | 1005 | if (st->out_len == 0) |
ecbd95c1 BH |
1006 | /* Transfer ownership of the skb */ |
1007 | buffer->skb = skb; | |
b9b39b62 | 1008 | |
23d9e60b | 1009 | end_of_packet = st->out_len == 0 || st->packet_space == 0; |
ecbd95c1 | 1010 | buffer->continuation = !end_of_packet; |
b9b39b62 | 1011 | |
23d9e60b | 1012 | if (st->in_len == 0) { |
ecbd95c1 | 1013 | /* Transfer ownership of the pci mapping */ |
23d9e60b BH |
1014 | buffer->unmap_len = st->unmap_len; |
1015 | buffer->unmap_single = st->unmap_single; | |
1016 | st->unmap_len = 0; | |
ecbd95c1 BH |
1017 | } |
1018 | } | |
1019 | ||
23d9e60b | 1020 | st->dma_addr += n; |
b9b39b62 BH |
1021 | return rc; |
1022 | } | |
1023 | ||
1024 | ||
1025 | /** | |
1026 | * tso_start_new_packet - generate a new header and prepare for the new packet | |
1027 | * @tx_queue: Efx TX queue | |
1028 | * @skb: Socket buffer | |
1029 | * @st: TSO state | |
1030 | * | |
1031 | * Generate a new header and prepare for the new packet. Return 0 on | |
1032 | * success, or -1 if failed to alloc header. | |
1033 | */ | |
4d566063 BH |
1034 | static int tso_start_new_packet(struct efx_tx_queue *tx_queue, |
1035 | const struct sk_buff *skb, | |
1036 | struct tso_state *st) | |
b9b39b62 BH |
1037 | { |
1038 | struct efx_tso_header *tsoh; | |
b9b39b62 BH |
1039 | struct tcphdr *tsoh_th; |
1040 | unsigned ip_length; | |
1041 | u8 *header; | |
1042 | ||
1043 | /* Allocate a DMA-mapped header buffer. */ | |
23d9e60b | 1044 | if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) { |
b3475645 | 1045 | if (tx_queue->tso_headers_free == NULL) { |
b9b39b62 BH |
1046 | if (efx_tsoh_block_alloc(tx_queue)) |
1047 | return -1; | |
b3475645 | 1048 | } |
b9b39b62 BH |
1049 | EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free); |
1050 | tsoh = tx_queue->tso_headers_free; | |
1051 | tx_queue->tso_headers_free = tsoh->next; | |
1052 | tsoh->unmap_len = 0; | |
1053 | } else { | |
1054 | tx_queue->tso_long_headers++; | |
23d9e60b | 1055 | tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len); |
b9b39b62 BH |
1056 | if (unlikely(!tsoh)) |
1057 | return -1; | |
1058 | } | |
1059 | ||
1060 | header = TSOH_BUFFER(tsoh); | |
1061 | tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb)); | |
b9b39b62 BH |
1062 | |
1063 | /* Copy and update the headers. */ | |
23d9e60b | 1064 | memcpy(header, skb->data, st->header_len); |
b9b39b62 BH |
1065 | |
1066 | tsoh_th->seq = htonl(st->seqnum); | |
1067 | st->seqnum += skb_shinfo(skb)->gso_size; | |
23d9e60b | 1068 | if (st->out_len > skb_shinfo(skb)->gso_size) { |
b9b39b62 | 1069 | /* This packet will not finish the TSO burst. */ |
23d9e60b | 1070 | ip_length = st->full_packet_size - ETH_HDR_LEN(skb); |
b9b39b62 BH |
1071 | tsoh_th->fin = 0; |
1072 | tsoh_th->psh = 0; | |
1073 | } else { | |
1074 | /* This packet will be the last in the TSO burst. */ | |
23d9e60b | 1075 | ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len; |
b9b39b62 BH |
1076 | tsoh_th->fin = tcp_hdr(skb)->fin; |
1077 | tsoh_th->psh = tcp_hdr(skb)->psh; | |
1078 | } | |
b9b39b62 | 1079 | |
738a8f4b BH |
1080 | if (st->protocol == htons(ETH_P_IP)) { |
1081 | struct iphdr *tsoh_iph = | |
1082 | (struct iphdr *)(header + SKB_IPV4_OFF(skb)); | |
1083 | ||
1084 | tsoh_iph->tot_len = htons(ip_length); | |
1085 | ||
1086 | /* Linux leaves suitable gaps in the IP ID space for us to fill. */ | |
1087 | tsoh_iph->id = htons(st->ipv4_id); | |
1088 | st->ipv4_id++; | |
1089 | } else { | |
1090 | struct ipv6hdr *tsoh_iph = | |
1091 | (struct ipv6hdr *)(header + SKB_IPV6_OFF(skb)); | |
1092 | ||
1093 | tsoh_iph->payload_len = htons(ip_length - sizeof(*tsoh_iph)); | |
1094 | } | |
b9b39b62 BH |
1095 | |
1096 | st->packet_space = skb_shinfo(skb)->gso_size; | |
1097 | ++tx_queue->tso_packets; | |
1098 | ||
1099 | /* Form a descriptor for this header. */ | |
23d9e60b | 1100 | efx_tso_put_header(tx_queue, tsoh, st->header_len); |
b9b39b62 BH |
1101 | |
1102 | return 0; | |
1103 | } | |
1104 | ||
1105 | ||
1106 | /** | |
1107 | * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer | |
1108 | * @tx_queue: Efx TX queue | |
1109 | * @skb: Socket buffer | |
1110 | * | |
1111 | * Context: You must hold netif_tx_lock() to call this function. | |
1112 | * | |
1113 | * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if | |
1114 | * @skb was not enqueued. In all cases @skb is consumed. Return | |
1115 | * %NETDEV_TX_OK or %NETDEV_TX_BUSY. | |
1116 | */ | |
1117 | static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, | |
740847da | 1118 | struct sk_buff *skb) |
b9b39b62 | 1119 | { |
ecbd95c1 | 1120 | struct efx_nic *efx = tx_queue->efx; |
b9b39b62 BH |
1121 | int frag_i, rc, rc2 = NETDEV_TX_OK; |
1122 | struct tso_state state; | |
b9b39b62 | 1123 | |
738a8f4b BH |
1124 | /* Find the packet protocol and sanity-check it */ |
1125 | state.protocol = efx_tso_check_protocol(skb); | |
b9b39b62 BH |
1126 | |
1127 | EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count); | |
1128 | ||
1129 | tso_start(&state, skb); | |
1130 | ||
1131 | /* Assume that skb header area contains exactly the headers, and | |
1132 | * all payload is in the frag list. | |
1133 | */ | |
23d9e60b | 1134 | if (skb_headlen(skb) == state.header_len) { |
b9b39b62 BH |
1135 | /* Grab the first payload fragment. */ |
1136 | EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1); | |
1137 | frag_i = 0; | |
ecbd95c1 BH |
1138 | rc = tso_get_fragment(&state, efx, |
1139 | skb_shinfo(skb)->frags + frag_i); | |
b9b39b62 BH |
1140 | if (rc) |
1141 | goto mem_err; | |
1142 | } else { | |
ecbd95c1 | 1143 | rc = tso_get_head_fragment(&state, efx, skb); |
b9b39b62 BH |
1144 | if (rc) |
1145 | goto mem_err; | |
1146 | frag_i = -1; | |
1147 | } | |
1148 | ||
1149 | if (tso_start_new_packet(tx_queue, skb, &state) < 0) | |
1150 | goto mem_err; | |
1151 | ||
1152 | while (1) { | |
1153 | rc = tso_fill_packet_with_fragment(tx_queue, skb, &state); | |
c04bfc6b BH |
1154 | if (unlikely(rc)) { |
1155 | rc2 = NETDEV_TX_BUSY; | |
1156 | goto unwind; | |
1157 | } | |
b9b39b62 BH |
1158 | |
1159 | /* Move onto the next fragment? */ | |
23d9e60b | 1160 | if (state.in_len == 0) { |
b9b39b62 BH |
1161 | if (++frag_i >= skb_shinfo(skb)->nr_frags) |
1162 | /* End of payload reached. */ | |
1163 | break; | |
ecbd95c1 BH |
1164 | rc = tso_get_fragment(&state, efx, |
1165 | skb_shinfo(skb)->frags + frag_i); | |
b9b39b62 BH |
1166 | if (rc) |
1167 | goto mem_err; | |
1168 | } | |
1169 | ||
1170 | /* Start at new packet? */ | |
1171 | if (state.packet_space == 0 && | |
1172 | tso_start_new_packet(tx_queue, skb, &state) < 0) | |
1173 | goto mem_err; | |
1174 | } | |
1175 | ||
449fa023 ED |
1176 | netdev_tx_sent_queue(tx_queue->core_txq, skb->len); |
1177 | ||
b9b39b62 | 1178 | /* Pass off to hardware */ |
152b6a62 | 1179 | efx_nic_push_buffers(tx_queue); |
b9b39b62 BH |
1180 | |
1181 | tx_queue->tso_bursts++; | |
1182 | return NETDEV_TX_OK; | |
1183 | ||
1184 | mem_err: | |
62776d03 BH |
1185 | netif_err(efx, tx_err, efx->net_dev, |
1186 | "Out of memory for TSO headers, or PCI mapping error\n"); | |
9bc183d7 | 1187 | dev_kfree_skb_any(skb); |
b9b39b62 BH |
1188 | |
1189 | unwind: | |
5988b63a | 1190 | /* Free the DMA mapping we were in the process of writing out */ |
23d9e60b BH |
1191 | if (state.unmap_len) { |
1192 | if (state.unmap_single) | |
1193 | pci_unmap_single(efx->pci_dev, state.unmap_addr, | |
1194 | state.unmap_len, PCI_DMA_TODEVICE); | |
ecbd95c1 | 1195 | else |
23d9e60b BH |
1196 | pci_unmap_page(efx->pci_dev, state.unmap_addr, |
1197 | state.unmap_len, PCI_DMA_TODEVICE); | |
ecbd95c1 | 1198 | } |
5988b63a | 1199 | |
b9b39b62 BH |
1200 | efx_enqueue_unwind(tx_queue); |
1201 | return rc2; | |
1202 | } | |
1203 | ||
1204 | ||
1205 | /* | |
1206 | * Free up all TSO datastructures associated with tx_queue. This | |
1207 | * routine should be called only once the tx_queue is both empty and | |
1208 | * will no longer be used. | |
1209 | */ | |
1210 | static void efx_fini_tso(struct efx_tx_queue *tx_queue) | |
1211 | { | |
1212 | unsigned i; | |
1213 | ||
b3475645 | 1214 | if (tx_queue->buffer) { |
ecc910f5 | 1215 | for (i = 0; i <= tx_queue->ptr_mask; ++i) |
b9b39b62 | 1216 | efx_tsoh_free(tx_queue, &tx_queue->buffer[i]); |
b3475645 | 1217 | } |
b9b39b62 BH |
1218 | |
1219 | while (tx_queue->tso_headers_free != NULL) | |
1220 | efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free, | |
1221 | tx_queue->efx->pci_dev); | |
1222 | } |