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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2005-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/pci.h> | |
12 | #include <linux/tcp.h> | |
13 | #include <linux/ip.h> | |
14 | #include <linux/in.h> | |
738a8f4b | 15 | #include <linux/ipv6.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
738a8f4b | 17 | #include <net/ipv6.h> |
8ceee660 BH |
18 | #include <linux/if_ether.h> |
19 | #include <linux/highmem.h> | |
183233be | 20 | #include <linux/cache.h> |
8ceee660 | 21 | #include "net_driver.h" |
8ceee660 | 22 | #include "efx.h" |
183233be | 23 | #include "io.h" |
744093c9 | 24 | #include "nic.h" |
8ceee660 | 25 | #include "workarounds.h" |
dfa50be9 | 26 | #include "ef10_regs.h" |
8ceee660 | 27 | |
183233be BH |
28 | #ifdef EFX_USE_PIO |
29 | ||
30 | #define EFX_PIOBUF_SIZE_MAX ER_DZ_TX_PIOBUF_SIZE | |
31 | #define EFX_PIOBUF_SIZE_DEF ALIGN(256, L1_CACHE_BYTES) | |
32 | unsigned int efx_piobuf_size __read_mostly = EFX_PIOBUF_SIZE_DEF; | |
33 | ||
34 | #endif /* EFX_USE_PIO */ | |
35 | ||
0fe5565b BH |
36 | static inline unsigned int |
37 | efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue) | |
38 | { | |
39 | return tx_queue->insert_count & tx_queue->ptr_mask; | |
40 | } | |
41 | ||
42 | static inline struct efx_tx_buffer * | |
43 | __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue) | |
44 | { | |
45 | return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)]; | |
46 | } | |
47 | ||
48 | static inline struct efx_tx_buffer * | |
49 | efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue) | |
50 | { | |
51 | struct efx_tx_buffer *buffer = | |
52 | __efx_tx_queue_get_insert_buffer(tx_queue); | |
53 | ||
54 | EFX_BUG_ON_PARANOID(buffer->len); | |
55 | EFX_BUG_ON_PARANOID(buffer->flags); | |
56 | EFX_BUG_ON_PARANOID(buffer->unmap_len); | |
57 | ||
58 | return buffer; | |
59 | } | |
60 | ||
4d566063 | 61 | static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue, |
c3940999 TH |
62 | struct efx_tx_buffer *buffer, |
63 | unsigned int *pkts_compl, | |
64 | unsigned int *bytes_compl) | |
8ceee660 BH |
65 | { |
66 | if (buffer->unmap_len) { | |
0e33d870 | 67 | struct device *dma_dev = &tx_queue->efx->pci_dev->dev; |
2acdb92e | 68 | dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset; |
7668ff9c | 69 | if (buffer->flags & EFX_TX_BUF_MAP_SINGLE) |
0e33d870 BH |
70 | dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len, |
71 | DMA_TO_DEVICE); | |
8ceee660 | 72 | else |
0e33d870 BH |
73 | dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len, |
74 | DMA_TO_DEVICE); | |
8ceee660 | 75 | buffer->unmap_len = 0; |
8ceee660 BH |
76 | } |
77 | ||
7668ff9c | 78 | if (buffer->flags & EFX_TX_BUF_SKB) { |
c3940999 TH |
79 | (*pkts_compl)++; |
80 | (*bytes_compl) += buffer->skb->len; | |
4ef6dae4 | 81 | dev_consume_skb_any((struct sk_buff *)buffer->skb); |
62776d03 BH |
82 | netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev, |
83 | "TX queue %d transmission id %x complete\n", | |
84 | tx_queue->queue, tx_queue->read_count); | |
f7251a9c BH |
85 | } else if (buffer->flags & EFX_TX_BUF_HEAP) { |
86 | kfree(buffer->heap_buf); | |
8ceee660 | 87 | } |
7668ff9c | 88 | |
f7251a9c BH |
89 | buffer->len = 0; |
90 | buffer->flags = 0; | |
8ceee660 BH |
91 | } |
92 | ||
b9b39b62 | 93 | static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, |
740847da | 94 | struct sk_buff *skb); |
8ceee660 | 95 | |
63f19884 BH |
96 | static inline unsigned |
97 | efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr) | |
98 | { | |
99 | /* Depending on the NIC revision, we can use descriptor | |
100 | * lengths up to 8K or 8K-1. However, since PCI Express | |
101 | * devices must split read requests at 4K boundaries, there is | |
102 | * little benefit from using descriptors that cross those | |
103 | * boundaries and we keep things simple by not doing so. | |
104 | */ | |
5b6262d0 | 105 | unsigned len = (~dma_addr & (EFX_PAGE_SIZE - 1)) + 1; |
63f19884 BH |
106 | |
107 | /* Work around hardware bug for unaligned buffers. */ | |
108 | if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf)) | |
109 | len = min_t(unsigned, len, 512 - (dma_addr & 0xf)); | |
110 | ||
111 | return len; | |
112 | } | |
113 | ||
7e6d06f0 BH |
114 | unsigned int efx_tx_max_skb_descs(struct efx_nic *efx) |
115 | { | |
116 | /* Header and payload descriptor for each output segment, plus | |
117 | * one for every input fragment boundary within a segment | |
118 | */ | |
119 | unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS; | |
120 | ||
dfa50be9 BH |
121 | /* Possibly one more per segment for the alignment workaround, |
122 | * or for option descriptors | |
123 | */ | |
124 | if (EFX_WORKAROUND_5391(efx) || efx_nic_rev(efx) >= EFX_REV_HUNT_A0) | |
7e6d06f0 BH |
125 | max_descs += EFX_TSO_MAX_SEGS; |
126 | ||
127 | /* Possibly more for PCIe page boundaries within input fragments */ | |
128 | if (PAGE_SIZE > EFX_PAGE_SIZE) | |
129 | max_descs += max_t(unsigned int, MAX_SKB_FRAGS, | |
130 | DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE)); | |
131 | ||
132 | return max_descs; | |
133 | } | |
134 | ||
14bf718f BH |
135 | static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1) |
136 | { | |
137 | /* We need to consider both queues that the net core sees as one */ | |
138 | struct efx_tx_queue *txq2 = efx_tx_queue_partner(txq1); | |
139 | struct efx_nic *efx = txq1->efx; | |
140 | unsigned int fill_level; | |
141 | ||
142 | fill_level = max(txq1->insert_count - txq1->old_read_count, | |
143 | txq2->insert_count - txq2->old_read_count); | |
144 | if (likely(fill_level < efx->txq_stop_thresh)) | |
145 | return; | |
146 | ||
147 | /* We used the stale old_read_count above, which gives us a | |
148 | * pessimistic estimate of the fill level (which may even | |
149 | * validly be >= efx->txq_entries). Now try again using | |
150 | * read_count (more likely to be a cache miss). | |
151 | * | |
152 | * If we read read_count and then conditionally stop the | |
153 | * queue, it is possible for the completion path to race with | |
154 | * us and complete all outstanding descriptors in the middle, | |
155 | * after which there will be no more completions to wake it. | |
156 | * Therefore we stop the queue first, then read read_count | |
157 | * (with a memory barrier to ensure the ordering), then | |
158 | * restart the queue if the fill level turns out to be low | |
159 | * enough. | |
160 | */ | |
161 | netif_tx_stop_queue(txq1->core_txq); | |
162 | smp_mb(); | |
163 | txq1->old_read_count = ACCESS_ONCE(txq1->read_count); | |
164 | txq2->old_read_count = ACCESS_ONCE(txq2->read_count); | |
165 | ||
166 | fill_level = max(txq1->insert_count - txq1->old_read_count, | |
167 | txq2->insert_count - txq2->old_read_count); | |
168 | EFX_BUG_ON_PARANOID(fill_level >= efx->txq_entries); | |
169 | if (likely(fill_level < efx->txq_stop_thresh)) { | |
170 | smp_mb(); | |
171 | if (likely(!efx->loopback_selftest)) | |
172 | netif_tx_start_queue(txq1->core_txq); | |
173 | } | |
174 | } | |
175 | ||
ee45fd92 JC |
176 | #ifdef EFX_USE_PIO |
177 | ||
178 | struct efx_short_copy_buffer { | |
179 | int used; | |
180 | u8 buf[L1_CACHE_BYTES]; | |
181 | }; | |
182 | ||
183 | /* Copy to PIO, respecting that writes to PIO buffers must be dword aligned. | |
184 | * Advances piobuf pointer. Leaves additional data in the copy buffer. | |
185 | */ | |
186 | static void efx_memcpy_toio_aligned(struct efx_nic *efx, u8 __iomem **piobuf, | |
187 | u8 *data, int len, | |
188 | struct efx_short_copy_buffer *copy_buf) | |
189 | { | |
190 | int block_len = len & ~(sizeof(copy_buf->buf) - 1); | |
191 | ||
4984c237 | 192 | __iowrite64_copy(*piobuf, data, block_len >> 3); |
ee45fd92 JC |
193 | *piobuf += block_len; |
194 | len -= block_len; | |
195 | ||
196 | if (len) { | |
197 | data += block_len; | |
198 | BUG_ON(copy_buf->used); | |
199 | BUG_ON(len > sizeof(copy_buf->buf)); | |
200 | memcpy(copy_buf->buf, data, len); | |
201 | copy_buf->used = len; | |
202 | } | |
203 | } | |
204 | ||
205 | /* Copy to PIO, respecting dword alignment, popping data from copy buffer first. | |
206 | * Advances piobuf pointer. Leaves additional data in the copy buffer. | |
207 | */ | |
208 | static void efx_memcpy_toio_aligned_cb(struct efx_nic *efx, u8 __iomem **piobuf, | |
209 | u8 *data, int len, | |
210 | struct efx_short_copy_buffer *copy_buf) | |
211 | { | |
212 | if (copy_buf->used) { | |
213 | /* if the copy buffer is partially full, fill it up and write */ | |
214 | int copy_to_buf = | |
215 | min_t(int, sizeof(copy_buf->buf) - copy_buf->used, len); | |
216 | ||
217 | memcpy(copy_buf->buf + copy_buf->used, data, copy_to_buf); | |
218 | copy_buf->used += copy_to_buf; | |
219 | ||
220 | /* if we didn't fill it up then we're done for now */ | |
221 | if (copy_buf->used < sizeof(copy_buf->buf)) | |
222 | return; | |
223 | ||
4984c237 BH |
224 | __iowrite64_copy(*piobuf, copy_buf->buf, |
225 | sizeof(copy_buf->buf) >> 3); | |
ee45fd92 JC |
226 | *piobuf += sizeof(copy_buf->buf); |
227 | data += copy_to_buf; | |
228 | len -= copy_to_buf; | |
229 | copy_buf->used = 0; | |
230 | } | |
231 | ||
232 | efx_memcpy_toio_aligned(efx, piobuf, data, len, copy_buf); | |
233 | } | |
234 | ||
235 | static void efx_flush_copy_buffer(struct efx_nic *efx, u8 __iomem *piobuf, | |
236 | struct efx_short_copy_buffer *copy_buf) | |
237 | { | |
238 | /* if there's anything in it, write the whole buffer, including junk */ | |
239 | if (copy_buf->used) | |
4984c237 BH |
240 | __iowrite64_copy(piobuf, copy_buf->buf, |
241 | sizeof(copy_buf->buf) >> 3); | |
ee45fd92 JC |
242 | } |
243 | ||
244 | /* Traverse skb structure and copy fragments in to PIO buffer. | |
245 | * Advances piobuf pointer. | |
246 | */ | |
247 | static void efx_skb_copy_bits_to_pio(struct efx_nic *efx, struct sk_buff *skb, | |
248 | u8 __iomem **piobuf, | |
249 | struct efx_short_copy_buffer *copy_buf) | |
250 | { | |
251 | int i; | |
252 | ||
253 | efx_memcpy_toio_aligned(efx, piobuf, skb->data, skb_headlen(skb), | |
254 | copy_buf); | |
255 | ||
256 | for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) { | |
257 | skb_frag_t *f = &skb_shinfo(skb)->frags[i]; | |
258 | u8 *vaddr; | |
259 | ||
260 | vaddr = kmap_atomic(skb_frag_page(f)); | |
261 | ||
262 | efx_memcpy_toio_aligned_cb(efx, piobuf, vaddr + f->page_offset, | |
263 | skb_frag_size(f), copy_buf); | |
264 | kunmap_atomic(vaddr); | |
265 | } | |
266 | ||
267 | EFX_BUG_ON_PARANOID(skb_shinfo(skb)->frag_list); | |
268 | } | |
269 | ||
270 | static struct efx_tx_buffer * | |
271 | efx_enqueue_skb_pio(struct efx_tx_queue *tx_queue, struct sk_buff *skb) | |
272 | { | |
273 | struct efx_tx_buffer *buffer = | |
274 | efx_tx_queue_get_insert_buffer(tx_queue); | |
275 | u8 __iomem *piobuf = tx_queue->piobuf; | |
276 | ||
277 | /* Copy to PIO buffer. Ensure the writes are padded to the end | |
278 | * of a cache line, as this is required for write-combining to be | |
279 | * effective on at least x86. | |
280 | */ | |
281 | ||
282 | if (skb_shinfo(skb)->nr_frags) { | |
283 | /* The size of the copy buffer will ensure all writes | |
284 | * are the size of a cache line. | |
285 | */ | |
286 | struct efx_short_copy_buffer copy_buf; | |
287 | ||
288 | copy_buf.used = 0; | |
289 | ||
290 | efx_skb_copy_bits_to_pio(tx_queue->efx, skb, | |
291 | &piobuf, ©_buf); | |
292 | efx_flush_copy_buffer(tx_queue->efx, piobuf, ©_buf); | |
293 | } else { | |
294 | /* Pad the write to the size of a cache line. | |
295 | * We can do this because we know the skb_shared_info sruct is | |
296 | * after the source, and the destination buffer is big enough. | |
297 | */ | |
298 | BUILD_BUG_ON(L1_CACHE_BYTES > | |
299 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); | |
4984c237 BH |
300 | __iowrite64_copy(tx_queue->piobuf, skb->data, |
301 | ALIGN(skb->len, L1_CACHE_BYTES) >> 3); | |
ee45fd92 JC |
302 | } |
303 | ||
304 | EFX_POPULATE_QWORD_5(buffer->option, | |
305 | ESF_DZ_TX_DESC_IS_OPT, 1, | |
306 | ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_PIO, | |
307 | ESF_DZ_TX_PIO_CONT, 0, | |
308 | ESF_DZ_TX_PIO_BYTE_CNT, skb->len, | |
309 | ESF_DZ_TX_PIO_BUF_ADDR, | |
310 | tx_queue->piobuf_offset); | |
311 | ++tx_queue->pio_packets; | |
312 | ++tx_queue->insert_count; | |
313 | return buffer; | |
314 | } | |
315 | #endif /* EFX_USE_PIO */ | |
316 | ||
8ceee660 BH |
317 | /* |
318 | * Add a socket buffer to a TX queue | |
319 | * | |
320 | * This maps all fragments of a socket buffer for DMA and adds them to | |
321 | * the TX queue. The queue's insert pointer will be incremented by | |
322 | * the number of fragments in the socket buffer. | |
323 | * | |
324 | * If any DMA mapping fails, any mapped fragments will be unmapped, | |
325 | * the queue's insert pointer will be restored to its original value. | |
326 | * | |
497f5ba3 BH |
327 | * This function is split out from efx_hard_start_xmit to allow the |
328 | * loopback test to direct packets via specific TX queues. | |
329 | * | |
14bf718f | 330 | * Returns NETDEV_TX_OK. |
8ceee660 BH |
331 | * You must hold netif_tx_lock() to call this function. |
332 | */ | |
497f5ba3 | 333 | netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb) |
8ceee660 BH |
334 | { |
335 | struct efx_nic *efx = tx_queue->efx; | |
0e33d870 | 336 | struct device *dma_dev = &efx->pci_dev->dev; |
8ceee660 | 337 | struct efx_tx_buffer *buffer; |
70b33fb0 | 338 | unsigned int old_insert_count = tx_queue->insert_count; |
8ceee660 | 339 | skb_frag_t *fragment; |
0fe5565b | 340 | unsigned int len, unmap_len = 0; |
8ceee660 BH |
341 | dma_addr_t dma_addr, unmap_addr = 0; |
342 | unsigned int dma_len; | |
7668ff9c | 343 | unsigned short dma_flags; |
14bf718f | 344 | int i = 0; |
8ceee660 | 345 | |
9bc183d7 | 346 | if (skb_shinfo(skb)->gso_size) |
b9b39b62 BH |
347 | return efx_enqueue_skb_tso(tx_queue, skb); |
348 | ||
8ceee660 BH |
349 | /* Get size of the initial fragment */ |
350 | len = skb_headlen(skb); | |
351 | ||
bb145a9e BH |
352 | /* Pad if necessary */ |
353 | if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) { | |
354 | EFX_BUG_ON_PARANOID(skb->data_len); | |
355 | len = 32 + 1; | |
356 | if (skb_pad(skb, len - skb->len)) | |
357 | return NETDEV_TX_OK; | |
358 | } | |
359 | ||
ee45fd92 JC |
360 | /* Consider using PIO for short packets */ |
361 | #ifdef EFX_USE_PIO | |
70b33fb0 EC |
362 | if (skb->len <= efx_piobuf_size && !skb->xmit_more && |
363 | efx_nic_may_tx_pio(tx_queue)) { | |
ee45fd92 JC |
364 | buffer = efx_enqueue_skb_pio(tx_queue, skb); |
365 | dma_flags = EFX_TX_BUF_OPTION; | |
366 | goto finish_packet; | |
367 | } | |
368 | #endif | |
369 | ||
0e33d870 | 370 | /* Map for DMA. Use dma_map_single rather than dma_map_page |
8ceee660 BH |
371 | * since this is more efficient on machines with sparse |
372 | * memory. | |
373 | */ | |
7668ff9c | 374 | dma_flags = EFX_TX_BUF_MAP_SINGLE; |
0e33d870 | 375 | dma_addr = dma_map_single(dma_dev, skb->data, len, PCI_DMA_TODEVICE); |
8ceee660 BH |
376 | |
377 | /* Process all fragments */ | |
378 | while (1) { | |
0e33d870 BH |
379 | if (unlikely(dma_mapping_error(dma_dev, dma_addr))) |
380 | goto dma_err; | |
8ceee660 BH |
381 | |
382 | /* Store fields for marking in the per-fragment final | |
383 | * descriptor */ | |
384 | unmap_len = len; | |
385 | unmap_addr = dma_addr; | |
386 | ||
387 | /* Add to TX queue, splitting across DMA boundaries */ | |
388 | do { | |
0fe5565b | 389 | buffer = efx_tx_queue_get_insert_buffer(tx_queue); |
8ceee660 | 390 | |
63f19884 BH |
391 | dma_len = efx_max_tx_len(efx, dma_addr); |
392 | if (likely(dma_len >= len)) | |
8ceee660 BH |
393 | dma_len = len; |
394 | ||
8ceee660 BH |
395 | /* Fill out per descriptor fields */ |
396 | buffer->len = dma_len; | |
397 | buffer->dma_addr = dma_addr; | |
7668ff9c | 398 | buffer->flags = EFX_TX_BUF_CONT; |
8ceee660 BH |
399 | len -= dma_len; |
400 | dma_addr += dma_len; | |
401 | ++tx_queue->insert_count; | |
402 | } while (len); | |
403 | ||
404 | /* Transfer ownership of the unmapping to the final buffer */ | |
7668ff9c | 405 | buffer->flags = EFX_TX_BUF_CONT | dma_flags; |
8ceee660 | 406 | buffer->unmap_len = unmap_len; |
2acdb92e | 407 | buffer->dma_offset = buffer->dma_addr - unmap_addr; |
8ceee660 BH |
408 | unmap_len = 0; |
409 | ||
410 | /* Get address and size of next fragment */ | |
411 | if (i >= skb_shinfo(skb)->nr_frags) | |
412 | break; | |
413 | fragment = &skb_shinfo(skb)->frags[i]; | |
9e903e08 | 414 | len = skb_frag_size(fragment); |
8ceee660 BH |
415 | i++; |
416 | /* Map for DMA */ | |
7668ff9c | 417 | dma_flags = 0; |
0e33d870 | 418 | dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len, |
5d6bcdfe | 419 | DMA_TO_DEVICE); |
8ceee660 BH |
420 | } |
421 | ||
422 | /* Transfer ownership of the skb to the final buffer */ | |
440b87ea | 423 | #ifdef EFX_USE_PIO |
ee45fd92 | 424 | finish_packet: |
440b87ea | 425 | #endif |
8ceee660 | 426 | buffer->skb = skb; |
7668ff9c | 427 | buffer->flags = EFX_TX_BUF_SKB | dma_flags; |
8ceee660 | 428 | |
c3940999 TH |
429 | netdev_tx_sent_queue(tx_queue->core_txq, skb->len); |
430 | ||
70b33fb0 EC |
431 | efx_tx_maybe_stop_queue(tx_queue); |
432 | ||
8ceee660 | 433 | /* Pass off to hardware */ |
70b33fb0 EC |
434 | if (!skb->xmit_more || netif_xmit_stopped(tx_queue->core_txq)) |
435 | efx_nic_push_buffers(tx_queue); | |
8ceee660 | 436 | |
8ccf3800 AR |
437 | tx_queue->tx_packets++; |
438 | ||
8ceee660 BH |
439 | return NETDEV_TX_OK; |
440 | ||
0e33d870 | 441 | dma_err: |
62776d03 BH |
442 | netif_err(efx, tx_err, efx->net_dev, |
443 | " TX queue %d could not map skb with %d bytes %d " | |
444 | "fragments for DMA\n", tx_queue->queue, skb->len, | |
445 | skb_shinfo(skb)->nr_frags + 1); | |
8ceee660 BH |
446 | |
447 | /* Mark the packet as transmitted, and free the SKB ourselves */ | |
9bc183d7 | 448 | dev_kfree_skb_any(skb); |
8ceee660 | 449 | |
8ceee660 | 450 | /* Work backwards until we hit the original insert pointer value */ |
70b33fb0 | 451 | while (tx_queue->insert_count != old_insert_count) { |
c3940999 | 452 | unsigned int pkts_compl = 0, bytes_compl = 0; |
8ceee660 | 453 | --tx_queue->insert_count; |
0fe5565b | 454 | buffer = __efx_tx_queue_get_insert_buffer(tx_queue); |
c3940999 | 455 | efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); |
8ceee660 BH |
456 | } |
457 | ||
458 | /* Free the fragment we were mid-way through pushing */ | |
ecbd95c1 | 459 | if (unmap_len) { |
7668ff9c | 460 | if (dma_flags & EFX_TX_BUF_MAP_SINGLE) |
0e33d870 BH |
461 | dma_unmap_single(dma_dev, unmap_addr, unmap_len, |
462 | DMA_TO_DEVICE); | |
ecbd95c1 | 463 | else |
0e33d870 BH |
464 | dma_unmap_page(dma_dev, unmap_addr, unmap_len, |
465 | DMA_TO_DEVICE); | |
ecbd95c1 | 466 | } |
8ceee660 | 467 | |
14bf718f | 468 | return NETDEV_TX_OK; |
8ceee660 BH |
469 | } |
470 | ||
471 | /* Remove packets from the TX queue | |
472 | * | |
473 | * This removes packets from the TX queue, up to and including the | |
474 | * specified index. | |
475 | */ | |
4d566063 | 476 | static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue, |
c3940999 TH |
477 | unsigned int index, |
478 | unsigned int *pkts_compl, | |
479 | unsigned int *bytes_compl) | |
8ceee660 BH |
480 | { |
481 | struct efx_nic *efx = tx_queue->efx; | |
482 | unsigned int stop_index, read_ptr; | |
8ceee660 | 483 | |
ecc910f5 SH |
484 | stop_index = (index + 1) & tx_queue->ptr_mask; |
485 | read_ptr = tx_queue->read_count & tx_queue->ptr_mask; | |
8ceee660 BH |
486 | |
487 | while (read_ptr != stop_index) { | |
488 | struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr]; | |
ba8977bd BH |
489 | |
490 | if (!(buffer->flags & EFX_TX_BUF_OPTION) && | |
491 | unlikely(buffer->len == 0)) { | |
62776d03 BH |
492 | netif_err(efx, tx_err, efx->net_dev, |
493 | "TX queue %d spurious TX completion id %x\n", | |
494 | tx_queue->queue, read_ptr); | |
8ceee660 BH |
495 | efx_schedule_reset(efx, RESET_TYPE_TX_SKIP); |
496 | return; | |
497 | } | |
498 | ||
c3940999 | 499 | efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl); |
8ceee660 BH |
500 | |
501 | ++tx_queue->read_count; | |
ecc910f5 | 502 | read_ptr = tx_queue->read_count & tx_queue->ptr_mask; |
8ceee660 BH |
503 | } |
504 | } | |
505 | ||
8ceee660 BH |
506 | /* Initiate a packet transmission. We use one channel per CPU |
507 | * (sharing when we have more CPUs than channels). On Falcon, the TX | |
508 | * completion events will be directed back to the CPU that transmitted | |
509 | * the packet, which should be cache-efficient. | |
510 | * | |
511 | * Context: non-blocking. | |
512 | * Note that returning anything other than NETDEV_TX_OK will cause the | |
513 | * OS to free the skb. | |
514 | */ | |
61357325 | 515 | netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb, |
2d0cc56d | 516 | struct net_device *net_dev) |
8ceee660 | 517 | { |
767e468c | 518 | struct efx_nic *efx = netdev_priv(net_dev); |
60ac1065 | 519 | struct efx_tx_queue *tx_queue; |
94b274bf | 520 | unsigned index, type; |
60ac1065 | 521 | |
e4abce85 | 522 | EFX_WARN_ON_PARANOID(!netif_device_present(net_dev)); |
a7ef5933 | 523 | |
7c236c43 SH |
524 | /* PTP "event" packet */ |
525 | if (unlikely(efx_xmit_with_hwtstamp(skb)) && | |
526 | unlikely(efx_ptp_is_ptp_tx(efx, skb))) { | |
527 | return efx_ptp_tx(efx, skb); | |
528 | } | |
529 | ||
94b274bf BH |
530 | index = skb_get_queue_mapping(skb); |
531 | type = skb->ip_summed == CHECKSUM_PARTIAL ? EFX_TXQ_TYPE_OFFLOAD : 0; | |
532 | if (index >= efx->n_tx_channels) { | |
533 | index -= efx->n_tx_channels; | |
534 | type |= EFX_TXQ_TYPE_HIGHPRI; | |
535 | } | |
536 | tx_queue = efx_get_tx_queue(efx, index, type); | |
60ac1065 | 537 | |
497f5ba3 | 538 | return efx_enqueue_skb(tx_queue, skb); |
8ceee660 BH |
539 | } |
540 | ||
60031fcc BH |
541 | void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue) |
542 | { | |
94b274bf BH |
543 | struct efx_nic *efx = tx_queue->efx; |
544 | ||
60031fcc | 545 | /* Must be inverse of queue lookup in efx_hard_start_xmit() */ |
94b274bf BH |
546 | tx_queue->core_txq = |
547 | netdev_get_tx_queue(efx->net_dev, | |
548 | tx_queue->queue / EFX_TXQ_TYPES + | |
549 | ((tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ? | |
550 | efx->n_tx_channels : 0)); | |
551 | } | |
552 | ||
553 | int efx_setup_tc(struct net_device *net_dev, u8 num_tc) | |
554 | { | |
555 | struct efx_nic *efx = netdev_priv(net_dev); | |
556 | struct efx_channel *channel; | |
557 | struct efx_tx_queue *tx_queue; | |
558 | unsigned tc; | |
559 | int rc; | |
560 | ||
561 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0 || num_tc > EFX_MAX_TX_TC) | |
562 | return -EINVAL; | |
563 | ||
564 | if (num_tc == net_dev->num_tc) | |
565 | return 0; | |
566 | ||
567 | for (tc = 0; tc < num_tc; tc++) { | |
568 | net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels; | |
569 | net_dev->tc_to_txq[tc].count = efx->n_tx_channels; | |
570 | } | |
571 | ||
572 | if (num_tc > net_dev->num_tc) { | |
573 | /* Initialise high-priority queues as necessary */ | |
574 | efx_for_each_channel(channel, efx) { | |
575 | efx_for_each_possible_channel_tx_queue(tx_queue, | |
576 | channel) { | |
577 | if (!(tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI)) | |
578 | continue; | |
579 | if (!tx_queue->buffer) { | |
580 | rc = efx_probe_tx_queue(tx_queue); | |
581 | if (rc) | |
582 | return rc; | |
583 | } | |
584 | if (!tx_queue->initialised) | |
585 | efx_init_tx_queue(tx_queue); | |
586 | efx_init_tx_queue_core_txq(tx_queue); | |
587 | } | |
588 | } | |
589 | } else { | |
590 | /* Reduce number of classes before number of queues */ | |
591 | net_dev->num_tc = num_tc; | |
592 | } | |
593 | ||
594 | rc = netif_set_real_num_tx_queues(net_dev, | |
595 | max_t(int, num_tc, 1) * | |
596 | efx->n_tx_channels); | |
597 | if (rc) | |
598 | return rc; | |
599 | ||
600 | /* Do not destroy high-priority queues when they become | |
601 | * unused. We would have to flush them first, and it is | |
602 | * fairly difficult to flush a subset of TX queues. Leave | |
603 | * it to efx_fini_channels(). | |
604 | */ | |
605 | ||
606 | net_dev->num_tc = num_tc; | |
607 | return 0; | |
60031fcc BH |
608 | } |
609 | ||
8ceee660 BH |
610 | void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index) |
611 | { | |
612 | unsigned fill_level; | |
613 | struct efx_nic *efx = tx_queue->efx; | |
14bf718f | 614 | struct efx_tx_queue *txq2; |
c3940999 | 615 | unsigned int pkts_compl = 0, bytes_compl = 0; |
8ceee660 | 616 | |
ecc910f5 | 617 | EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask); |
8ceee660 | 618 | |
c3940999 | 619 | efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl); |
c936835c PD |
620 | tx_queue->pkts_compl += pkts_compl; |
621 | tx_queue->bytes_compl += bytes_compl; | |
8ceee660 | 622 | |
02e12165 BH |
623 | if (pkts_compl > 1) |
624 | ++tx_queue->merge_events; | |
625 | ||
14bf718f BH |
626 | /* See if we need to restart the netif queue. This memory |
627 | * barrier ensures that we write read_count (inside | |
628 | * efx_dequeue_buffers()) before reading the queue status. | |
629 | */ | |
8ceee660 | 630 | smp_mb(); |
c04bfc6b | 631 | if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) && |
9d1aea62 | 632 | likely(efx->port_enabled) && |
e4abce85 | 633 | likely(netif_device_present(efx->net_dev))) { |
14bf718f BH |
634 | txq2 = efx_tx_queue_partner(tx_queue); |
635 | fill_level = max(tx_queue->insert_count - tx_queue->read_count, | |
636 | txq2->insert_count - txq2->read_count); | |
637 | if (fill_level <= efx->txq_wake_thresh) | |
c04bfc6b | 638 | netif_tx_wake_queue(tx_queue->core_txq); |
8ceee660 | 639 | } |
cd38557d BH |
640 | |
641 | /* Check whether the hardware queue is now empty */ | |
642 | if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) { | |
643 | tx_queue->old_write_count = ACCESS_ONCE(tx_queue->write_count); | |
644 | if (tx_queue->read_count == tx_queue->old_write_count) { | |
645 | smp_mb(); | |
646 | tx_queue->empty_read_count = | |
647 | tx_queue->read_count | EFX_EMPTY_COUNT_VALID; | |
648 | } | |
649 | } | |
8ceee660 BH |
650 | } |
651 | ||
f7251a9c BH |
652 | /* Size of page-based TSO header buffers. Larger blocks must be |
653 | * allocated from the heap. | |
654 | */ | |
655 | #define TSOH_STD_SIZE 128 | |
656 | #define TSOH_PER_PAGE (PAGE_SIZE / TSOH_STD_SIZE) | |
657 | ||
658 | /* At most half the descriptors in the queue at any time will refer to | |
659 | * a TSO header buffer, since they must always be followed by a | |
660 | * payload descriptor referring to an skb. | |
661 | */ | |
662 | static unsigned int efx_tsoh_page_count(struct efx_tx_queue *tx_queue) | |
663 | { | |
664 | return DIV_ROUND_UP(tx_queue->ptr_mask + 1, 2 * TSOH_PER_PAGE); | |
665 | } | |
666 | ||
8ceee660 BH |
667 | int efx_probe_tx_queue(struct efx_tx_queue *tx_queue) |
668 | { | |
669 | struct efx_nic *efx = tx_queue->efx; | |
ecc910f5 | 670 | unsigned int entries; |
7668ff9c | 671 | int rc; |
8ceee660 | 672 | |
ecc910f5 SH |
673 | /* Create the smallest power-of-two aligned ring */ |
674 | entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE); | |
675 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE); | |
676 | tx_queue->ptr_mask = entries - 1; | |
677 | ||
678 | netif_dbg(efx, probe, efx->net_dev, | |
679 | "creating TX queue %d size %#x mask %#x\n", | |
680 | tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask); | |
8ceee660 BH |
681 | |
682 | /* Allocate software ring */ | |
c2e4e25a | 683 | tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer), |
ecc910f5 | 684 | GFP_KERNEL); |
60ac1065 BH |
685 | if (!tx_queue->buffer) |
686 | return -ENOMEM; | |
8ceee660 | 687 | |
f7251a9c BH |
688 | if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) { |
689 | tx_queue->tsoh_page = | |
690 | kcalloc(efx_tsoh_page_count(tx_queue), | |
691 | sizeof(tx_queue->tsoh_page[0]), GFP_KERNEL); | |
692 | if (!tx_queue->tsoh_page) { | |
693 | rc = -ENOMEM; | |
694 | goto fail1; | |
695 | } | |
696 | } | |
697 | ||
8ceee660 | 698 | /* Allocate hardware ring */ |
152b6a62 | 699 | rc = efx_nic_probe_tx(tx_queue); |
8ceee660 | 700 | if (rc) |
f7251a9c | 701 | goto fail2; |
8ceee660 BH |
702 | |
703 | return 0; | |
704 | ||
f7251a9c BH |
705 | fail2: |
706 | kfree(tx_queue->tsoh_page); | |
707 | tx_queue->tsoh_page = NULL; | |
708 | fail1: | |
8ceee660 BH |
709 | kfree(tx_queue->buffer); |
710 | tx_queue->buffer = NULL; | |
8ceee660 BH |
711 | return rc; |
712 | } | |
713 | ||
bc3c90a2 | 714 | void efx_init_tx_queue(struct efx_tx_queue *tx_queue) |
8ceee660 | 715 | { |
62776d03 BH |
716 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
717 | "initialising TX queue %d\n", tx_queue->queue); | |
8ceee660 BH |
718 | |
719 | tx_queue->insert_count = 0; | |
720 | tx_queue->write_count = 0; | |
cd38557d | 721 | tx_queue->old_write_count = 0; |
8ceee660 BH |
722 | tx_queue->read_count = 0; |
723 | tx_queue->old_read_count = 0; | |
cd38557d | 724 | tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID; |
8ceee660 BH |
725 | |
726 | /* Set up TX descriptor ring */ | |
152b6a62 | 727 | efx_nic_init_tx(tx_queue); |
94b274bf BH |
728 | |
729 | tx_queue->initialised = true; | |
8ceee660 BH |
730 | } |
731 | ||
e42c3d85 | 732 | void efx_fini_tx_queue(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
733 | { |
734 | struct efx_tx_buffer *buffer; | |
735 | ||
e42c3d85 BH |
736 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
737 | "shutting down TX queue %d\n", tx_queue->queue); | |
738 | ||
8ceee660 BH |
739 | if (!tx_queue->buffer) |
740 | return; | |
741 | ||
742 | /* Free any buffers left in the ring */ | |
743 | while (tx_queue->read_count != tx_queue->write_count) { | |
c3940999 | 744 | unsigned int pkts_compl = 0, bytes_compl = 0; |
ecc910f5 | 745 | buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask]; |
c3940999 | 746 | efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); |
8ceee660 BH |
747 | |
748 | ++tx_queue->read_count; | |
749 | } | |
c3940999 | 750 | netdev_tx_reset_queue(tx_queue->core_txq); |
8ceee660 BH |
751 | } |
752 | ||
8ceee660 BH |
753 | void efx_remove_tx_queue(struct efx_tx_queue *tx_queue) |
754 | { | |
f7251a9c BH |
755 | int i; |
756 | ||
94b274bf BH |
757 | if (!tx_queue->buffer) |
758 | return; | |
759 | ||
62776d03 BH |
760 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
761 | "destroying TX queue %d\n", tx_queue->queue); | |
152b6a62 | 762 | efx_nic_remove_tx(tx_queue); |
8ceee660 | 763 | |
f7251a9c BH |
764 | if (tx_queue->tsoh_page) { |
765 | for (i = 0; i < efx_tsoh_page_count(tx_queue); i++) | |
766 | efx_nic_free_buffer(tx_queue->efx, | |
767 | &tx_queue->tsoh_page[i]); | |
768 | kfree(tx_queue->tsoh_page); | |
769 | tx_queue->tsoh_page = NULL; | |
770 | } | |
771 | ||
8ceee660 BH |
772 | kfree(tx_queue->buffer); |
773 | tx_queue->buffer = NULL; | |
8ceee660 BH |
774 | } |
775 | ||
776 | ||
b9b39b62 BH |
777 | /* Efx TCP segmentation acceleration. |
778 | * | |
779 | * Why? Because by doing it here in the driver we can go significantly | |
780 | * faster than the GSO. | |
781 | * | |
782 | * Requires TX checksum offload support. | |
783 | */ | |
784 | ||
b9b39b62 | 785 | #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2)) |
b9b39b62 BH |
786 | |
787 | /** | |
788 | * struct tso_state - TSO state for an SKB | |
23d9e60b | 789 | * @out_len: Remaining length in current segment |
b9b39b62 | 790 | * @seqnum: Current sequence number |
23d9e60b | 791 | * @ipv4_id: Current IPv4 ID, host endian |
b9b39b62 | 792 | * @packet_space: Remaining space in current packet |
23d9e60b BH |
793 | * @dma_addr: DMA address of current position |
794 | * @in_len: Remaining length in current SKB fragment | |
795 | * @unmap_len: Length of SKB fragment | |
796 | * @unmap_addr: DMA address of SKB fragment | |
7668ff9c | 797 | * @dma_flags: TX buffer flags for DMA mapping - %EFX_TX_BUF_MAP_SINGLE or 0 |
738a8f4b | 798 | * @protocol: Network protocol (after any VLAN header) |
9714284f BH |
799 | * @ip_off: Offset of IP header |
800 | * @tcp_off: Offset of TCP header | |
23d9e60b | 801 | * @header_len: Number of bytes of header |
53cb13c6 | 802 | * @ip_base_len: IPv4 tot_len or IPv6 payload_len, before TCP payload |
dfa50be9 BH |
803 | * @header_dma_addr: Header DMA address, when using option descriptors |
804 | * @header_unmap_len: Header DMA mapped length, or 0 if not using option | |
805 | * descriptors | |
b9b39b62 BH |
806 | * |
807 | * The state used during segmentation. It is put into this data structure | |
808 | * just to make it easy to pass into inline functions. | |
809 | */ | |
810 | struct tso_state { | |
23d9e60b BH |
811 | /* Output position */ |
812 | unsigned out_len; | |
b9b39b62 | 813 | unsigned seqnum; |
dfa50be9 | 814 | u16 ipv4_id; |
b9b39b62 BH |
815 | unsigned packet_space; |
816 | ||
23d9e60b BH |
817 | /* Input position */ |
818 | dma_addr_t dma_addr; | |
819 | unsigned in_len; | |
820 | unsigned unmap_len; | |
821 | dma_addr_t unmap_addr; | |
7668ff9c | 822 | unsigned short dma_flags; |
23d9e60b | 823 | |
738a8f4b | 824 | __be16 protocol; |
9714284f BH |
825 | unsigned int ip_off; |
826 | unsigned int tcp_off; | |
23d9e60b | 827 | unsigned header_len; |
53cb13c6 | 828 | unsigned int ip_base_len; |
dfa50be9 BH |
829 | dma_addr_t header_dma_addr; |
830 | unsigned int header_unmap_len; | |
b9b39b62 BH |
831 | }; |
832 | ||
833 | ||
834 | /* | |
835 | * Verify that our various assumptions about sk_buffs and the conditions | |
738a8f4b | 836 | * under which TSO will be attempted hold true. Return the protocol number. |
b9b39b62 | 837 | */ |
738a8f4b | 838 | static __be16 efx_tso_check_protocol(struct sk_buff *skb) |
b9b39b62 | 839 | { |
740847da BH |
840 | __be16 protocol = skb->protocol; |
841 | ||
b9b39b62 | 842 | EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto != |
740847da BH |
843 | protocol); |
844 | if (protocol == htons(ETH_P_8021Q)) { | |
740847da BH |
845 | struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data; |
846 | protocol = veh->h_vlan_encapsulated_proto; | |
740847da BH |
847 | } |
848 | ||
738a8f4b BH |
849 | if (protocol == htons(ETH_P_IP)) { |
850 | EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP); | |
851 | } else { | |
852 | EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6)); | |
853 | EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP); | |
854 | } | |
b9b39b62 BH |
855 | EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data) |
856 | + (tcp_hdr(skb)->doff << 2u)) > | |
857 | skb_headlen(skb)); | |
738a8f4b BH |
858 | |
859 | return protocol; | |
b9b39b62 BH |
860 | } |
861 | ||
f7251a9c BH |
862 | static u8 *efx_tsoh_get_buffer(struct efx_tx_queue *tx_queue, |
863 | struct efx_tx_buffer *buffer, unsigned int len) | |
b9b39b62 | 864 | { |
f7251a9c | 865 | u8 *result; |
b9b39b62 | 866 | |
f7251a9c BH |
867 | EFX_BUG_ON_PARANOID(buffer->len); |
868 | EFX_BUG_ON_PARANOID(buffer->flags); | |
869 | EFX_BUG_ON_PARANOID(buffer->unmap_len); | |
b9b39b62 | 870 | |
0bdadad1 | 871 | if (likely(len <= TSOH_STD_SIZE - NET_IP_ALIGN)) { |
f7251a9c BH |
872 | unsigned index = |
873 | (tx_queue->insert_count & tx_queue->ptr_mask) / 2; | |
874 | struct efx_buffer *page_buf = | |
875 | &tx_queue->tsoh_page[index / TSOH_PER_PAGE]; | |
876 | unsigned offset = | |
0bdadad1 | 877 | TSOH_STD_SIZE * (index % TSOH_PER_PAGE) + NET_IP_ALIGN; |
b9b39b62 | 878 | |
f7251a9c | 879 | if (unlikely(!page_buf->addr) && |
0d19a540 BH |
880 | efx_nic_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE, |
881 | GFP_ATOMIC)) | |
f7251a9c | 882 | return NULL; |
b9b39b62 | 883 | |
f7251a9c BH |
884 | result = (u8 *)page_buf->addr + offset; |
885 | buffer->dma_addr = page_buf->dma_addr + offset; | |
886 | buffer->flags = EFX_TX_BUF_CONT; | |
887 | } else { | |
888 | tx_queue->tso_long_headers++; | |
b9b39b62 | 889 | |
0bdadad1 | 890 | buffer->heap_buf = kmalloc(NET_IP_ALIGN + len, GFP_ATOMIC); |
f7251a9c BH |
891 | if (unlikely(!buffer->heap_buf)) |
892 | return NULL; | |
0bdadad1 | 893 | result = (u8 *)buffer->heap_buf + NET_IP_ALIGN; |
f7251a9c | 894 | buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_HEAP; |
b9b39b62 BH |
895 | } |
896 | ||
f7251a9c | 897 | buffer->len = len; |
b9b39b62 | 898 | |
f7251a9c | 899 | return result; |
b9b39b62 BH |
900 | } |
901 | ||
902 | /** | |
903 | * efx_tx_queue_insert - push descriptors onto the TX queue | |
904 | * @tx_queue: Efx TX queue | |
905 | * @dma_addr: DMA address of fragment | |
906 | * @len: Length of fragment | |
ecbd95c1 | 907 | * @final_buffer: The final buffer inserted into the queue |
b9b39b62 | 908 | * |
14bf718f | 909 | * Push descriptors onto the TX queue. |
b9b39b62 | 910 | */ |
14bf718f BH |
911 | static void efx_tx_queue_insert(struct efx_tx_queue *tx_queue, |
912 | dma_addr_t dma_addr, unsigned len, | |
913 | struct efx_tx_buffer **final_buffer) | |
b9b39b62 BH |
914 | { |
915 | struct efx_tx_buffer *buffer; | |
916 | struct efx_nic *efx = tx_queue->efx; | |
0fe5565b | 917 | unsigned dma_len; |
b9b39b62 BH |
918 | |
919 | EFX_BUG_ON_PARANOID(len <= 0); | |
920 | ||
b9b39b62 | 921 | while (1) { |
0fe5565b | 922 | buffer = efx_tx_queue_get_insert_buffer(tx_queue); |
b9b39b62 BH |
923 | ++tx_queue->insert_count; |
924 | ||
925 | EFX_BUG_ON_PARANOID(tx_queue->insert_count - | |
ecc910f5 SH |
926 | tx_queue->read_count >= |
927 | efx->txq_entries); | |
b9b39b62 | 928 | |
b9b39b62 BH |
929 | buffer->dma_addr = dma_addr; |
930 | ||
63f19884 | 931 | dma_len = efx_max_tx_len(efx, dma_addr); |
b9b39b62 BH |
932 | |
933 | /* If there is enough space to send then do so */ | |
934 | if (dma_len >= len) | |
935 | break; | |
936 | ||
7668ff9c BH |
937 | buffer->len = dma_len; |
938 | buffer->flags = EFX_TX_BUF_CONT; | |
b9b39b62 BH |
939 | dma_addr += dma_len; |
940 | len -= dma_len; | |
941 | } | |
942 | ||
943 | EFX_BUG_ON_PARANOID(!len); | |
944 | buffer->len = len; | |
ecbd95c1 | 945 | *final_buffer = buffer; |
b9b39b62 BH |
946 | } |
947 | ||
948 | ||
949 | /* | |
950 | * Put a TSO header into the TX queue. | |
951 | * | |
952 | * This is special-cased because we know that it is small enough to fit in | |
953 | * a single fragment, and we know it doesn't cross a page boundary. It | |
954 | * also allows us to not worry about end-of-packet etc. | |
955 | */ | |
f7251a9c BH |
956 | static int efx_tso_put_header(struct efx_tx_queue *tx_queue, |
957 | struct efx_tx_buffer *buffer, u8 *header) | |
b9b39b62 | 958 | { |
f7251a9c BH |
959 | if (unlikely(buffer->flags & EFX_TX_BUF_HEAP)) { |
960 | buffer->dma_addr = dma_map_single(&tx_queue->efx->pci_dev->dev, | |
961 | header, buffer->len, | |
962 | DMA_TO_DEVICE); | |
963 | if (unlikely(dma_mapping_error(&tx_queue->efx->pci_dev->dev, | |
964 | buffer->dma_addr))) { | |
965 | kfree(buffer->heap_buf); | |
966 | buffer->len = 0; | |
967 | buffer->flags = 0; | |
968 | return -ENOMEM; | |
969 | } | |
970 | buffer->unmap_len = buffer->len; | |
2acdb92e | 971 | buffer->dma_offset = 0; |
f7251a9c BH |
972 | buffer->flags |= EFX_TX_BUF_MAP_SINGLE; |
973 | } | |
b9b39b62 BH |
974 | |
975 | ++tx_queue->insert_count; | |
f7251a9c | 976 | return 0; |
b9b39b62 BH |
977 | } |
978 | ||
979 | ||
f7251a9c BH |
980 | /* Remove buffers put into a tx_queue. None of the buffers must have |
981 | * an skb attached. | |
982 | */ | |
70b33fb0 EC |
983 | static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue, |
984 | unsigned int insert_count) | |
b9b39b62 BH |
985 | { |
986 | struct efx_tx_buffer *buffer; | |
987 | ||
988 | /* Work backwards until we hit the original insert pointer value */ | |
70b33fb0 | 989 | while (tx_queue->insert_count != insert_count) { |
b9b39b62 | 990 | --tx_queue->insert_count; |
0fe5565b | 991 | buffer = __efx_tx_queue_get_insert_buffer(tx_queue); |
f7251a9c | 992 | efx_dequeue_buffer(tx_queue, buffer, NULL, NULL); |
b9b39b62 BH |
993 | } |
994 | } | |
995 | ||
996 | ||
997 | /* Parse the SKB header and initialise state. */ | |
c78c39e6 BH |
998 | static int tso_start(struct tso_state *st, struct efx_nic *efx, |
999 | const struct sk_buff *skb) | |
b9b39b62 | 1000 | { |
93413f50 | 1001 | bool use_opt_desc = efx_nic_rev(efx) >= EFX_REV_HUNT_A0; |
dfa50be9 | 1002 | struct device *dma_dev = &efx->pci_dev->dev; |
c78c39e6 | 1003 | unsigned int header_len, in_len; |
dfa50be9 | 1004 | dma_addr_t dma_addr; |
c78c39e6 | 1005 | |
9714284f BH |
1006 | st->ip_off = skb_network_header(skb) - skb->data; |
1007 | st->tcp_off = skb_transport_header(skb) - skb->data; | |
c78c39e6 BH |
1008 | header_len = st->tcp_off + (tcp_hdr(skb)->doff << 2u); |
1009 | in_len = skb_headlen(skb) - header_len; | |
1010 | st->header_len = header_len; | |
1011 | st->in_len = in_len; | |
53cb13c6 | 1012 | if (st->protocol == htons(ETH_P_IP)) { |
9714284f | 1013 | st->ip_base_len = st->header_len - st->ip_off; |
738a8f4b | 1014 | st->ipv4_id = ntohs(ip_hdr(skb)->id); |
53cb13c6 | 1015 | } else { |
9714284f | 1016 | st->ip_base_len = st->header_len - st->tcp_off; |
738a8f4b | 1017 | st->ipv4_id = 0; |
53cb13c6 | 1018 | } |
b9b39b62 BH |
1019 | st->seqnum = ntohl(tcp_hdr(skb)->seq); |
1020 | ||
1021 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg); | |
1022 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn); | |
1023 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst); | |
1024 | ||
c78c39e6 BH |
1025 | st->out_len = skb->len - header_len; |
1026 | ||
93413f50 | 1027 | if (!use_opt_desc) { |
dfa50be9 BH |
1028 | st->header_unmap_len = 0; |
1029 | ||
1030 | if (likely(in_len == 0)) { | |
1031 | st->dma_flags = 0; | |
1032 | st->unmap_len = 0; | |
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | dma_addr = dma_map_single(dma_dev, skb->data + header_len, | |
1037 | in_len, DMA_TO_DEVICE); | |
1038 | st->dma_flags = EFX_TX_BUF_MAP_SINGLE; | |
1039 | st->dma_addr = dma_addr; | |
1040 | st->unmap_addr = dma_addr; | |
1041 | st->unmap_len = in_len; | |
1042 | } else { | |
1043 | dma_addr = dma_map_single(dma_dev, skb->data, | |
1044 | skb_headlen(skb), DMA_TO_DEVICE); | |
1045 | st->header_dma_addr = dma_addr; | |
1046 | st->header_unmap_len = skb_headlen(skb); | |
c78c39e6 | 1047 | st->dma_flags = 0; |
dfa50be9 BH |
1048 | st->dma_addr = dma_addr + header_len; |
1049 | st->unmap_len = 0; | |
c78c39e6 BH |
1050 | } |
1051 | ||
dfa50be9 | 1052 | return unlikely(dma_mapping_error(dma_dev, dma_addr)) ? -ENOMEM : 0; |
b9b39b62 BH |
1053 | } |
1054 | ||
4d566063 BH |
1055 | static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx, |
1056 | skb_frag_t *frag) | |
b9b39b62 | 1057 | { |
4a22c4c9 | 1058 | st->unmap_addr = skb_frag_dma_map(&efx->pci_dev->dev, frag, 0, |
9e903e08 | 1059 | skb_frag_size(frag), DMA_TO_DEVICE); |
5d6bcdfe | 1060 | if (likely(!dma_mapping_error(&efx->pci_dev->dev, st->unmap_addr))) { |
7668ff9c | 1061 | st->dma_flags = 0; |
9e903e08 ED |
1062 | st->unmap_len = skb_frag_size(frag); |
1063 | st->in_len = skb_frag_size(frag); | |
23d9e60b | 1064 | st->dma_addr = st->unmap_addr; |
ecbd95c1 BH |
1065 | return 0; |
1066 | } | |
1067 | return -ENOMEM; | |
1068 | } | |
1069 | ||
b9b39b62 BH |
1070 | |
1071 | /** | |
1072 | * tso_fill_packet_with_fragment - form descriptors for the current fragment | |
1073 | * @tx_queue: Efx TX queue | |
1074 | * @skb: Socket buffer | |
1075 | * @st: TSO state | |
1076 | * | |
1077 | * Form descriptors for the current fragment, until we reach the end | |
14bf718f | 1078 | * of fragment or end-of-packet. |
b9b39b62 | 1079 | */ |
14bf718f BH |
1080 | static void tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue, |
1081 | const struct sk_buff *skb, | |
1082 | struct tso_state *st) | |
b9b39b62 | 1083 | { |
ecbd95c1 | 1084 | struct efx_tx_buffer *buffer; |
14bf718f | 1085 | int n; |
b9b39b62 | 1086 | |
23d9e60b | 1087 | if (st->in_len == 0) |
14bf718f | 1088 | return; |
b9b39b62 | 1089 | if (st->packet_space == 0) |
14bf718f | 1090 | return; |
b9b39b62 | 1091 | |
23d9e60b | 1092 | EFX_BUG_ON_PARANOID(st->in_len <= 0); |
b9b39b62 BH |
1093 | EFX_BUG_ON_PARANOID(st->packet_space <= 0); |
1094 | ||
23d9e60b | 1095 | n = min(st->in_len, st->packet_space); |
b9b39b62 BH |
1096 | |
1097 | st->packet_space -= n; | |
23d9e60b BH |
1098 | st->out_len -= n; |
1099 | st->in_len -= n; | |
b9b39b62 | 1100 | |
14bf718f | 1101 | efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer); |
b9b39b62 | 1102 | |
14bf718f BH |
1103 | if (st->out_len == 0) { |
1104 | /* Transfer ownership of the skb */ | |
1105 | buffer->skb = skb; | |
1106 | buffer->flags = EFX_TX_BUF_SKB; | |
1107 | } else if (st->packet_space != 0) { | |
1108 | buffer->flags = EFX_TX_BUF_CONT; | |
1109 | } | |
1110 | ||
1111 | if (st->in_len == 0) { | |
1112 | /* Transfer ownership of the DMA mapping */ | |
1113 | buffer->unmap_len = st->unmap_len; | |
2acdb92e | 1114 | buffer->dma_offset = buffer->unmap_len - buffer->len; |
14bf718f BH |
1115 | buffer->flags |= st->dma_flags; |
1116 | st->unmap_len = 0; | |
ecbd95c1 BH |
1117 | } |
1118 | ||
23d9e60b | 1119 | st->dma_addr += n; |
b9b39b62 BH |
1120 | } |
1121 | ||
1122 | ||
1123 | /** | |
1124 | * tso_start_new_packet - generate a new header and prepare for the new packet | |
1125 | * @tx_queue: Efx TX queue | |
1126 | * @skb: Socket buffer | |
1127 | * @st: TSO state | |
1128 | * | |
1129 | * Generate a new header and prepare for the new packet. Return 0 on | |
f7251a9c | 1130 | * success, or -%ENOMEM if failed to alloc header. |
b9b39b62 | 1131 | */ |
4d566063 BH |
1132 | static int tso_start_new_packet(struct efx_tx_queue *tx_queue, |
1133 | const struct sk_buff *skb, | |
1134 | struct tso_state *st) | |
b9b39b62 | 1135 | { |
f7251a9c | 1136 | struct efx_tx_buffer *buffer = |
0fe5565b | 1137 | efx_tx_queue_get_insert_buffer(tx_queue); |
dfa50be9 BH |
1138 | bool is_last = st->out_len <= skb_shinfo(skb)->gso_size; |
1139 | u8 tcp_flags_clear; | |
b9b39b62 | 1140 | |
dfa50be9 | 1141 | if (!is_last) { |
53cb13c6 | 1142 | st->packet_space = skb_shinfo(skb)->gso_size; |
dfa50be9 | 1143 | tcp_flags_clear = 0x09; /* mask out FIN and PSH */ |
b9b39b62 | 1144 | } else { |
53cb13c6 | 1145 | st->packet_space = st->out_len; |
dfa50be9 | 1146 | tcp_flags_clear = 0x00; |
b9b39b62 | 1147 | } |
b9b39b62 | 1148 | |
dfa50be9 BH |
1149 | if (!st->header_unmap_len) { |
1150 | /* Allocate and insert a DMA-mapped header buffer. */ | |
1151 | struct tcphdr *tsoh_th; | |
1152 | unsigned ip_length; | |
1153 | u8 *header; | |
1154 | int rc; | |
738a8f4b | 1155 | |
dfa50be9 BH |
1156 | header = efx_tsoh_get_buffer(tx_queue, buffer, st->header_len); |
1157 | if (!header) | |
1158 | return -ENOMEM; | |
738a8f4b | 1159 | |
dfa50be9 BH |
1160 | tsoh_th = (struct tcphdr *)(header + st->tcp_off); |
1161 | ||
1162 | /* Copy and update the headers. */ | |
1163 | memcpy(header, skb->data, st->header_len); | |
1164 | ||
1165 | tsoh_th->seq = htonl(st->seqnum); | |
1166 | ((u8 *)tsoh_th)[13] &= ~tcp_flags_clear; | |
1167 | ||
1168 | ip_length = st->ip_base_len + st->packet_space; | |
1169 | ||
1170 | if (st->protocol == htons(ETH_P_IP)) { | |
1171 | struct iphdr *tsoh_iph = | |
1172 | (struct iphdr *)(header + st->ip_off); | |
1173 | ||
1174 | tsoh_iph->tot_len = htons(ip_length); | |
1175 | tsoh_iph->id = htons(st->ipv4_id); | |
1176 | } else { | |
1177 | struct ipv6hdr *tsoh_iph = | |
1178 | (struct ipv6hdr *)(header + st->ip_off); | |
1179 | ||
1180 | tsoh_iph->payload_len = htons(ip_length); | |
1181 | } | |
1182 | ||
1183 | rc = efx_tso_put_header(tx_queue, buffer, header); | |
1184 | if (unlikely(rc)) | |
1185 | return rc; | |
738a8f4b | 1186 | } else { |
dfa50be9 BH |
1187 | /* Send the original headers with a TSO option descriptor |
1188 | * in front | |
1189 | */ | |
1190 | u8 tcp_flags = ((u8 *)tcp_hdr(skb))[13] & ~tcp_flags_clear; | |
1191 | ||
1192 | buffer->flags = EFX_TX_BUF_OPTION; | |
1193 | buffer->len = 0; | |
1194 | buffer->unmap_len = 0; | |
1195 | EFX_POPULATE_QWORD_5(buffer->option, | |
1196 | ESF_DZ_TX_DESC_IS_OPT, 1, | |
1197 | ESF_DZ_TX_OPTION_TYPE, | |
1198 | ESE_DZ_TX_OPTION_DESC_TSO, | |
1199 | ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags, | |
1200 | ESF_DZ_TX_TSO_IP_ID, st->ipv4_id, | |
1201 | ESF_DZ_TX_TSO_TCP_SEQNO, st->seqnum); | |
1202 | ++tx_queue->insert_count; | |
738a8f4b | 1203 | |
dfa50be9 BH |
1204 | /* We mapped the headers in tso_start(). Unmap them |
1205 | * when the last segment is completed. | |
1206 | */ | |
0fe5565b | 1207 | buffer = efx_tx_queue_get_insert_buffer(tx_queue); |
dfa50be9 BH |
1208 | buffer->dma_addr = st->header_dma_addr; |
1209 | buffer->len = st->header_len; | |
1210 | if (is_last) { | |
1211 | buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_MAP_SINGLE; | |
1212 | buffer->unmap_len = st->header_unmap_len; | |
2acdb92e | 1213 | buffer->dma_offset = 0; |
dfa50be9 BH |
1214 | /* Ensure we only unmap them once in case of a |
1215 | * later DMA mapping error and rollback | |
1216 | */ | |
1217 | st->header_unmap_len = 0; | |
1218 | } else { | |
1219 | buffer->flags = EFX_TX_BUF_CONT; | |
1220 | buffer->unmap_len = 0; | |
1221 | } | |
1222 | ++tx_queue->insert_count; | |
738a8f4b | 1223 | } |
b9b39b62 | 1224 | |
dfa50be9 BH |
1225 | st->seqnum += skb_shinfo(skb)->gso_size; |
1226 | ||
1227 | /* Linux leaves suitable gaps in the IP ID space for us to fill. */ | |
1228 | ++st->ipv4_id; | |
f7251a9c | 1229 | |
b9b39b62 BH |
1230 | ++tx_queue->tso_packets; |
1231 | ||
8ccf3800 AR |
1232 | ++tx_queue->tx_packets; |
1233 | ||
b9b39b62 BH |
1234 | return 0; |
1235 | } | |
1236 | ||
1237 | ||
1238 | /** | |
1239 | * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer | |
1240 | * @tx_queue: Efx TX queue | |
1241 | * @skb: Socket buffer | |
1242 | * | |
1243 | * Context: You must hold netif_tx_lock() to call this function. | |
1244 | * | |
1245 | * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if | |
1246 | * @skb was not enqueued. In all cases @skb is consumed. Return | |
14bf718f | 1247 | * %NETDEV_TX_OK. |
b9b39b62 BH |
1248 | */ |
1249 | static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, | |
740847da | 1250 | struct sk_buff *skb) |
b9b39b62 | 1251 | { |
ecbd95c1 | 1252 | struct efx_nic *efx = tx_queue->efx; |
70b33fb0 | 1253 | unsigned int old_insert_count = tx_queue->insert_count; |
14bf718f | 1254 | int frag_i, rc; |
b9b39b62 | 1255 | struct tso_state state; |
b9b39b62 | 1256 | |
738a8f4b BH |
1257 | /* Find the packet protocol and sanity-check it */ |
1258 | state.protocol = efx_tso_check_protocol(skb); | |
b9b39b62 | 1259 | |
c78c39e6 BH |
1260 | rc = tso_start(&state, efx, skb); |
1261 | if (rc) | |
1262 | goto mem_err; | |
b9b39b62 | 1263 | |
c78c39e6 | 1264 | if (likely(state.in_len == 0)) { |
b9b39b62 BH |
1265 | /* Grab the first payload fragment. */ |
1266 | EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1); | |
1267 | frag_i = 0; | |
ecbd95c1 BH |
1268 | rc = tso_get_fragment(&state, efx, |
1269 | skb_shinfo(skb)->frags + frag_i); | |
b9b39b62 BH |
1270 | if (rc) |
1271 | goto mem_err; | |
1272 | } else { | |
c78c39e6 | 1273 | /* Payload starts in the header area. */ |
b9b39b62 BH |
1274 | frag_i = -1; |
1275 | } | |
1276 | ||
1277 | if (tso_start_new_packet(tx_queue, skb, &state) < 0) | |
1278 | goto mem_err; | |
1279 | ||
1280 | while (1) { | |
14bf718f | 1281 | tso_fill_packet_with_fragment(tx_queue, skb, &state); |
b9b39b62 BH |
1282 | |
1283 | /* Move onto the next fragment? */ | |
23d9e60b | 1284 | if (state.in_len == 0) { |
b9b39b62 BH |
1285 | if (++frag_i >= skb_shinfo(skb)->nr_frags) |
1286 | /* End of payload reached. */ | |
1287 | break; | |
ecbd95c1 BH |
1288 | rc = tso_get_fragment(&state, efx, |
1289 | skb_shinfo(skb)->frags + frag_i); | |
b9b39b62 BH |
1290 | if (rc) |
1291 | goto mem_err; | |
1292 | } | |
1293 | ||
1294 | /* Start at new packet? */ | |
1295 | if (state.packet_space == 0 && | |
1296 | tso_start_new_packet(tx_queue, skb, &state) < 0) | |
1297 | goto mem_err; | |
1298 | } | |
1299 | ||
449fa023 ED |
1300 | netdev_tx_sent_queue(tx_queue->core_txq, skb->len); |
1301 | ||
14bf718f BH |
1302 | efx_tx_maybe_stop_queue(tx_queue); |
1303 | ||
70b33fb0 EC |
1304 | /* Pass off to hardware */ |
1305 | if (!skb->xmit_more || netif_xmit_stopped(tx_queue->core_txq)) | |
1306 | efx_nic_push_buffers(tx_queue); | |
1307 | ||
b9b39b62 BH |
1308 | tx_queue->tso_bursts++; |
1309 | return NETDEV_TX_OK; | |
1310 | ||
1311 | mem_err: | |
62776d03 | 1312 | netif_err(efx, tx_err, efx->net_dev, |
0e33d870 | 1313 | "Out of memory for TSO headers, or DMA mapping error\n"); |
9bc183d7 | 1314 | dev_kfree_skb_any(skb); |
b9b39b62 | 1315 | |
5988b63a | 1316 | /* Free the DMA mapping we were in the process of writing out */ |
23d9e60b | 1317 | if (state.unmap_len) { |
7668ff9c | 1318 | if (state.dma_flags & EFX_TX_BUF_MAP_SINGLE) |
0e33d870 BH |
1319 | dma_unmap_single(&efx->pci_dev->dev, state.unmap_addr, |
1320 | state.unmap_len, DMA_TO_DEVICE); | |
ecbd95c1 | 1321 | else |
0e33d870 BH |
1322 | dma_unmap_page(&efx->pci_dev->dev, state.unmap_addr, |
1323 | state.unmap_len, DMA_TO_DEVICE); | |
ecbd95c1 | 1324 | } |
5988b63a | 1325 | |
dfa50be9 BH |
1326 | /* Free the header DMA mapping, if using option descriptors */ |
1327 | if (state.header_unmap_len) | |
1328 | dma_unmap_single(&efx->pci_dev->dev, state.header_dma_addr, | |
1329 | state.header_unmap_len, DMA_TO_DEVICE); | |
1330 | ||
70b33fb0 | 1331 | efx_enqueue_unwind(tx_queue, old_insert_count); |
14bf718f | 1332 | return NETDEV_TX_OK; |
b9b39b62 | 1333 | } |