Merge branch 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / net / ethernet / sis / sis900.c
CommitLineData
1da177e4 1/* sis900.c: A SiS 900/7016 PCI Fast Ethernet driver for Linux.
6aa20a22 2 Copyright 1999 Silicon Integrated System Corporation
d269a69f 3 Revision: 1.08.10 Apr. 2 2006
6aa20a22 4
1da177e4 5 Modified from the driver which is originally written by Donald Becker.
6aa20a22 6
1da177e4
LT
7 This software may be used and distributed according to the terms
8 of the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on this skeleton fall under the GPL and must retain
10 the authorship (implicit copyright) notice.
6aa20a22 11
1da177e4
LT
12 References:
13 SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
14 preliminary Rev. 1.0 Jan. 14, 1998
15 SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support,
16 preliminary Rev. 1.0 Nov. 10, 1998
17 SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
18 preliminary Rev. 1.0 Jan. 18, 1998
19
d269a69f 20 Rev 1.08.10 Apr. 2 2006 Daniele Venzano add vlan (jumbo packets) support
ea37ccea 21 Rev 1.08.09 Sep. 19 2005 Daniele Venzano add Wake on LAN support
1da177e4 22 Rev 1.08.08 Jan. 22 2005 Daniele Venzano use netif_msg for debugging messages
d269a69f 23 Rev 1.08.07 Nov. 2 2003 Daniele Venzano <venza@brownhat.org> add suspend/resume support
1da177e4
LT
24 Rev 1.08.06 Sep. 24 2002 Mufasa Yang bug fix for Tx timeout & add SiS963 support
25 Rev 1.08.05 Jun. 6 2002 Mufasa Yang bug fix for read_eeprom & Tx descriptor over-boundary
26 Rev 1.08.04 Apr. 25 2002 Mufasa Yang <mufasa@sis.com.tw> added SiS962 support
27 Rev 1.08.03 Feb. 1 2002 Matt Domsch <Matt_Domsch@dell.com> update to use library crc32 function
28 Rev 1.08.02 Nov. 30 2001 Hui-Fen Hsu workaround for EDB & bug fix for dhcp problem
29 Rev 1.08.01 Aug. 25 2001 Hui-Fen Hsu update for 630ET & workaround for ICS1893 PHY
30 Rev 1.08.00 Jun. 11 2001 Hui-Fen Hsu workaround for RTL8201 PHY and some bug fix
31 Rev 1.07.11 Apr. 2 2001 Hui-Fen Hsu updates PCI drivers to use the new pci_set_dma_mask for kernel 2.4.3
6aa20a22 32 Rev 1.07.10 Mar. 1 2001 Hui-Fen Hsu <hfhsu@sis.com.tw> some bug fix & 635M/B support
1da177e4
LT
33 Rev 1.07.09 Feb. 9 2001 Dave Jones <davej@suse.de> PCI enable cleanup
34 Rev 1.07.08 Jan. 8 2001 Lei-Chun Chang added RTL8201 PHY support
35 Rev 1.07.07 Nov. 29 2000 Lei-Chun Chang added kernel-doc extractable documentation and 630 workaround fix
36 Rev 1.07.06 Nov. 7 2000 Jeff Garzik <jgarzik@pobox.com> some bug fix and cleaning
37 Rev 1.07.05 Nov. 6 2000 metapirat<metapirat@gmx.de> contribute media type select by ifconfig
38 Rev 1.07.04 Sep. 6 2000 Lei-Chun Chang added ICS1893 PHY support
b595076a 39 Rev 1.07.03 Aug. 24 2000 Lei-Chun Chang (lcchang@sis.com.tw) modified 630E equalizer workaround rule
1da177e4
LT
40 Rev 1.07.01 Aug. 08 2000 Ollie Lho minor update for SiS 630E and SiS 630E A1
41 Rev 1.07 Mar. 07 2000 Ollie Lho bug fix in Rx buffer ring
42 Rev 1.06.04 Feb. 11 2000 Jeff Garzik <jgarzik@pobox.com> softnet and init for kernel 2.4
43 Rev 1.06.03 Dec. 23 1999 Ollie Lho Third release
44 Rev 1.06.02 Nov. 23 1999 Ollie Lho bug in mac probing fixed
45 Rev 1.06.01 Nov. 16 1999 Ollie Lho CRC calculation provide by Joseph Zbiciak (im14u2c@primenet.com)
46 Rev 1.06 Nov. 4 1999 Ollie Lho (ollie@sis.com.tw) Second release
47 Rev 1.05.05 Oct. 29 1999 Ollie Lho (ollie@sis.com.tw) Single buffer Tx/Rx
48 Chin-Shan Li (lcs@sis.com.tw) Added AMD Am79c901 HomePNA PHY support
49 Rev 1.05 Aug. 7 1999 Jim Huang (cmhuang@sis.com.tw) Initial release
50*/
51
52#include <linux/module.h>
53#include <linux/moduleparam.h>
54#include <linux/kernel.h>
d43c36dc 55#include <linux/sched.h>
1da177e4
LT
56#include <linux/string.h>
57#include <linux/timer.h>
58#include <linux/errno.h>
59#include <linux/ioport.h>
60#include <linux/slab.h>
61#include <linux/interrupt.h>
62#include <linux/pci.h>
63#include <linux/netdevice.h>
64#include <linux/init.h>
65#include <linux/mii.h>
66#include <linux/etherdevice.h>
67#include <linux/skbuff.h>
68#include <linux/delay.h>
69#include <linux/ethtool.h>
70#include <linux/crc32.h>
71#include <linux/bitops.h>
12b279f9 72#include <linux/dma-mapping.h>
1da177e4
LT
73
74#include <asm/processor.h> /* Processor type for cache alignment. */
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/uaccess.h> /* User space memory access functions */
78
79#include "sis900.h"
80
81#define SIS900_MODULE_NAME "sis900"
d269a69f 82#define SIS900_DRV_VERSION "v1.08.10 Apr. 2 2006"
1da177e4 83
369e1231 84static const char version[] =
9a3c3de7 85 KERN_INFO "sis900.c: " SIS900_DRV_VERSION "\n";
1da177e4
LT
86
87static int max_interrupt_work = 40;
88static int multicast_filter_limit = 128;
89
90static int sis900_debug = -1; /* Use SIS900_DEF_MSG as value */
91
92#define SIS900_DEF_MSG \
93 (NETIF_MSG_DRV | \
94 NETIF_MSG_LINK | \
95 NETIF_MSG_RX_ERR | \
96 NETIF_MSG_TX_ERR)
97
98/* Time in jiffies before concluding the transmitter is hung. */
99#define TX_TIMEOUT (4*HZ)
1da177e4
LT
100
101enum {
102 SIS_900 = 0,
103 SIS_7016
104};
f71e1309 105static const char * card_names[] = {
1da177e4
LT
106 "SiS 900 PCI Fast Ethernet",
107 "SiS 7016 PCI Fast Ethernet"
108};
9baa3c34
BT
109
110static const struct pci_device_id sis900_pci_tbl[] = {
1da177e4
LT
111 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_900,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_900},
113 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_7016,
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_7016},
115 {0,}
116};
117MODULE_DEVICE_TABLE (pci, sis900_pci_tbl);
118
119static void sis900_read_mode(struct net_device *net_dev, int *speed, int *duplex);
120
f71e1309 121static const struct mii_chip_info {
1da177e4
LT
122 const char * name;
123 u16 phy_id0;
124 u16 phy_id1;
125 u8 phy_types;
126#define HOME 0x0001
127#define LAN 0x0002
128#define MIX 0x0003
129#define UNKNOWN 0x0
130} mii_chip_table[] = {
131 { "SiS 900 Internal MII PHY", 0x001d, 0x8000, LAN },
132 { "SiS 7014 Physical Layer Solution", 0x0016, 0xf830, LAN },
d8e95e52 133 { "SiS 900 on Foxconn 661 7MI", 0x0143, 0xBC70, LAN },
1da177e4 134 { "Altimata AC101LF PHY", 0x0022, 0x5520, LAN },
494aced2 135 { "ADM 7001 LAN PHY", 0x002e, 0xcc60, LAN },
1da177e4
LT
136 { "AMD 79C901 10BASE-T PHY", 0x0000, 0x6B70, LAN },
137 { "AMD 79C901 HomePNA PHY", 0x0000, 0x6B90, HOME},
138 { "ICS LAN PHY", 0x0015, 0xF440, LAN },
80a8003f 139 { "ICS LAN PHY", 0x0143, 0xBC70, LAN },
1da177e4
LT
140 { "NS 83851 PHY", 0x2000, 0x5C20, MIX },
141 { "NS 83847 PHY", 0x2000, 0x5C30, MIX },
142 { "Realtek RTL8201 PHY", 0x0000, 0x8200, LAN },
143 { "VIA 6103 PHY", 0x0101, 0x8f20, LAN },
144 {NULL,},
145};
146
147struct mii_phy {
148 struct mii_phy * next;
149 int phy_addr;
150 u16 phy_id0;
151 u16 phy_id1;
152 u16 status;
153 u8 phy_types;
154};
155
156typedef struct _BufferDesc {
157 u32 link;
158 u32 cmdsts;
159 u32 bufptr;
160} BufferDesc;
161
162struct sis900_private {
1da177e4
LT
163 struct pci_dev * pci_dev;
164
165 spinlock_t lock;
166
167 struct mii_phy * mii;
168 struct mii_phy * first_mii; /* record the first mii structure */
169 unsigned int cur_phy;
da369b01 170 struct mii_if_info mii_info;
1da177e4 171
57d6d456
FR
172 void __iomem *ioaddr;
173
1da177e4
LT
174 struct timer_list timer; /* Link status detection timer. */
175 u8 autong_complete; /* 1: auto-negotiate complete */
176
177 u32 msg_enable;
178
179 unsigned int cur_rx, dirty_rx; /* producer/comsumer pointers for Tx/Rx ring */
180 unsigned int cur_tx, dirty_tx;
181
182 /* The saved address of a sent/receive-in-place packet buffer */
183 struct sk_buff *tx_skbuff[NUM_TX_DESC];
184 struct sk_buff *rx_skbuff[NUM_RX_DESC];
185 BufferDesc *tx_ring;
186 BufferDesc *rx_ring;
187
188 dma_addr_t tx_ring_dma;
189 dma_addr_t rx_ring_dma;
190
191 unsigned int tx_full; /* The Tx queue is full. */
192 u8 host_bridge_rev;
193 u8 chipset_rev;
194};
195
196MODULE_AUTHOR("Jim Huang <cmhuang@sis.com.tw>, Ollie Lho <ollie@sis.com.tw>");
197MODULE_DESCRIPTION("SiS 900 PCI Fast Ethernet driver");
198MODULE_LICENSE("GPL");
199
200module_param(multicast_filter_limit, int, 0444);
201module_param(max_interrupt_work, int, 0444);
202module_param(sis900_debug, int, 0444);
203MODULE_PARM_DESC(multicast_filter_limit, "SiS 900/7016 maximum number of filtered multicast addresses");
204MODULE_PARM_DESC(max_interrupt_work, "SiS 900/7016 maximum events handled per interrupt");
205MODULE_PARM_DESC(sis900_debug, "SiS 900/7016 bitmapped debugging message level");
206
57d6d456
FR
207#define sw32(reg, val) iowrite32(val, ioaddr + (reg))
208#define sw8(reg, val) iowrite8(val, ioaddr + (reg))
209#define sr32(reg) ioread32(ioaddr + (reg))
210#define sr16(reg) ioread16(ioaddr + (reg))
211
1da177e4
LT
212#ifdef CONFIG_NET_POLL_CONTROLLER
213static void sis900_poll(struct net_device *dev);
214#endif
215static int sis900_open(struct net_device *net_dev);
216static int sis900_mii_probe (struct net_device * net_dev);
217static void sis900_init_rxfilter (struct net_device * net_dev);
57d6d456 218static u16 read_eeprom(void __iomem *ioaddr, int location);
da369b01 219static int mdio_read(struct net_device *net_dev, int phy_id, int location);
1da177e4
LT
220static void mdio_write(struct net_device *net_dev, int phy_id, int location, int val);
221static void sis900_timer(unsigned long data);
222static void sis900_check_mode (struct net_device *net_dev, struct mii_phy *mii_phy);
223static void sis900_tx_timeout(struct net_device *net_dev);
224static void sis900_init_tx_ring(struct net_device *net_dev);
225static void sis900_init_rx_ring(struct net_device *net_dev);
61357325
SH
226static netdev_tx_t sis900_start_xmit(struct sk_buff *skb,
227 struct net_device *net_dev);
1da177e4
LT
228static int sis900_rx(struct net_device *net_dev);
229static void sis900_finish_xmit (struct net_device *net_dev);
7d12e780 230static irqreturn_t sis900_interrupt(int irq, void *dev_instance);
1da177e4
LT
231static int sis900_close(struct net_device *net_dev);
232static int mii_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd);
1da177e4
LT
233static u16 sis900_mcast_bitnr(u8 *addr, u8 revision);
234static void set_rx_mode(struct net_device *net_dev);
235static void sis900_reset(struct net_device *net_dev);
236static void sis630_set_eq(struct net_device *net_dev, u8 revision);
237static int sis900_set_config(struct net_device *dev, struct ifmap *map);
238static u16 sis900_default_phy(struct net_device * net_dev);
239static void sis900_set_capability( struct net_device *net_dev ,struct mii_phy *phy);
240static u16 sis900_reset_phy(struct net_device *net_dev, int phy_addr);
241static void sis900_auto_negotiate(struct net_device *net_dev, int phy_addr);
57d6d456 242static void sis900_set_mode(struct sis900_private *, int speed, int duplex);
7282d491 243static const struct ethtool_ops sis900_ethtool_ops;
1da177e4
LT
244
245/**
246 * sis900_get_mac_addr - Get MAC address for stand alone SiS900 model
247 * @pci_dev: the sis900 pci device
6aa20a22 248 * @net_dev: the net device to get address for
1da177e4
LT
249 *
250 * Older SiS900 and friends, use EEPROM to store MAC address.
aaeb6cdf 251 * MAC address is read from read_eeprom() into @net_dev->dev_addr.
1da177e4
LT
252 */
253
369e1231
BP
254static int sis900_get_mac_addr(struct pci_dev *pci_dev,
255 struct net_device *net_dev)
1da177e4 256{
57d6d456
FR
257 struct sis900_private *sis_priv = netdev_priv(net_dev);
258 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
259 u16 signature;
260 int i;
261
262 /* check to see if we have sane EEPROM */
6aa20a22 263 signature = (u16) read_eeprom(ioaddr, EEPROMSignature);
1da177e4 264 if (signature == 0xffff || signature == 0x0000) {
6aa20a22 265 printk (KERN_WARNING "%s: Error EERPOM read %x\n",
1da177e4
LT
266 pci_name(pci_dev), signature);
267 return 0;
268 }
269
270 /* get MAC address from EEPROM */
271 for (i = 0; i < 3; i++)
272 ((u16 *)(net_dev->dev_addr))[i] = read_eeprom(ioaddr, i+EEPROMMACAddr);
273
274 return 1;
275}
276
277/**
278 * sis630e_get_mac_addr - Get MAC address for SiS630E model
279 * @pci_dev: the sis900 pci device
6aa20a22 280 * @net_dev: the net device to get address for
1da177e4
LT
281 *
282 * SiS630E model, use APC CMOS RAM to store MAC address.
283 * APC CMOS RAM is accessed through ISA bridge.
aaeb6cdf 284 * MAC address is read into @net_dev->dev_addr.
1da177e4
LT
285 */
286
369e1231
BP
287static int sis630e_get_mac_addr(struct pci_dev *pci_dev,
288 struct net_device *net_dev)
1da177e4
LT
289{
290 struct pci_dev *isa_bridge = NULL;
291 u8 reg;
292 int i;
293
294 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0008, isa_bridge);
295 if (!isa_bridge)
296 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0018, isa_bridge);
297 if (!isa_bridge) {
298 printk(KERN_WARNING "%s: Can not find ISA bridge\n",
299 pci_name(pci_dev));
300 return 0;
301 }
302 pci_read_config_byte(isa_bridge, 0x48, &reg);
303 pci_write_config_byte(isa_bridge, 0x48, reg | 0x40);
304
305 for (i = 0; i < 6; i++) {
306 outb(0x09 + i, 0x70);
6aa20a22 307 ((u8 *)(net_dev->dev_addr))[i] = inb(0x71);
1da177e4 308 }
efa2ad89 309
1da177e4
LT
310 pci_write_config_byte(isa_bridge, 0x48, reg & ~0x40);
311 pci_dev_put(isa_bridge);
312
313 return 1;
314}
315
316
317/**
318 * sis635_get_mac_addr - Get MAC address for SIS635 model
319 * @pci_dev: the sis900 pci device
6aa20a22 320 * @net_dev: the net device to get address for
1da177e4
LT
321 *
322 * SiS635 model, set MAC Reload Bit to load Mac address from APC
6aa20a22 323 * to rfdr. rfdr is accessed through rfcr. MAC address is read into
aaeb6cdf 324 * @net_dev->dev_addr.
1da177e4
LT
325 */
326
369e1231
BP
327static int sis635_get_mac_addr(struct pci_dev *pci_dev,
328 struct net_device *net_dev)
1da177e4 329{
57d6d456
FR
330 struct sis900_private *sis_priv = netdev_priv(net_dev);
331 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
332 u32 rfcrSave;
333 u32 i;
334
57d6d456 335 rfcrSave = sr32(rfcr);
1da177e4 336
57d6d456
FR
337 sw32(cr, rfcrSave | RELOAD);
338 sw32(cr, 0);
1da177e4
LT
339
340 /* disable packet filtering before setting filter */
57d6d456 341 sw32(rfcr, rfcrSave & ~RFEN);
1da177e4
LT
342
343 /* load MAC addr to filter data register */
344 for (i = 0 ; i < 3 ; i++) {
57d6d456
FR
345 sw32(rfcr, (i << RFADDR_shift));
346 *( ((u16 *)net_dev->dev_addr) + i) = sr16(rfdr);
1da177e4
LT
347 }
348
349 /* enable packet filtering */
57d6d456 350 sw32(rfcr, rfcrSave | RFEN);
1da177e4
LT
351
352 return 1;
353}
354
355/**
356 * sis96x_get_mac_addr - Get MAC address for SiS962 or SiS963 model
357 * @pci_dev: the sis900 pci device
6aa20a22 358 * @net_dev: the net device to get address for
1da177e4 359 *
6aa20a22 360 * SiS962 or SiS963 model, use EEPROM to store MAC address. And EEPROM
1da177e4 361 * is shared by
6aa20a22
JG
362 * LAN and 1394. When access EEPROM, send EEREQ signal to hardware first
363 * and wait for EEGNT. If EEGNT is ON, EEPROM is permitted to be access
1da177e4 364 * by LAN, otherwise is not. After MAC address is read from EEPROM, send
6aa20a22
JG
365 * EEDONE signal to refuse EEPROM access by LAN.
366 * The EEPROM map of SiS962 or SiS963 is different to SiS900.
367 * The signature field in SiS962 or SiS963 spec is meaningless.
aaeb6cdf 368 * MAC address is read into @net_dev->dev_addr.
1da177e4
LT
369 */
370
369e1231
BP
371static int sis96x_get_mac_addr(struct pci_dev *pci_dev,
372 struct net_device *net_dev)
1da177e4 373{
57d6d456
FR
374 struct sis900_private *sis_priv = netdev_priv(net_dev);
375 void __iomem *ioaddr = sis_priv->ioaddr;
376 int wait, rc = 0;
6aa20a22 377
57d6d456
FR
378 sw32(mear, EEREQ);
379 for (wait = 0; wait < 2000; wait++) {
380 if (sr32(mear) & EEGNT) {
381 u16 *mac = (u16 *)net_dev->dev_addr;
382 int i;
1da177e4
LT
383
384 /* get MAC address from EEPROM */
385 for (i = 0; i < 3; i++)
57d6d456 386 mac[i] = read_eeprom(ioaddr, i + EEPROMMACAddr);
1da177e4 387
57d6d456
FR
388 rc = 1;
389 break;
1da177e4 390 }
57d6d456 391 udelay(1);
1da177e4 392 }
57d6d456
FR
393 sw32(mear, EEDONE);
394 return rc;
1da177e4
LT
395}
396
09ab9e7c
SH
397static const struct net_device_ops sis900_netdev_ops = {
398 .ndo_open = sis900_open,
399 .ndo_stop = sis900_close,
400 .ndo_start_xmit = sis900_start_xmit,
401 .ndo_set_config = sis900_set_config,
afc4b13d 402 .ndo_set_rx_mode = set_rx_mode,
09ab9e7c
SH
403 .ndo_change_mtu = eth_change_mtu,
404 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 405 .ndo_set_mac_address = eth_mac_addr,
09ab9e7c
SH
406 .ndo_do_ioctl = mii_ioctl,
407 .ndo_tx_timeout = sis900_tx_timeout,
408#ifdef CONFIG_NET_POLL_CONTROLLER
409 .ndo_poll_controller = sis900_poll,
410#endif
411};
412
1da177e4
LT
413/**
414 * sis900_probe - Probe for sis900 device
415 * @pci_dev: the sis900 pci device
416 * @pci_id: the pci device ID
417 *
418 * Check and probe sis900 net device for @pci_dev.
6aa20a22 419 * Get mac address according to the chip revision,
1da177e4
LT
420 * and assign SiS900-specific entries in the device structure.
421 * ie: sis900_open(), sis900_start_xmit(), sis900_close(), etc.
422 */
423
369e1231 424static int sis900_probe(struct pci_dev *pci_dev,
1dd06ae8 425 const struct pci_device_id *pci_id)
1da177e4
LT
426{
427 struct sis900_private *sis_priv;
428 struct net_device *net_dev;
429 struct pci_dev *dev;
430 dma_addr_t ring_dma;
431 void *ring_space;
57d6d456 432 void __iomem *ioaddr;
1da177e4 433 int i, ret;
f71e1309 434 const char *card_name = card_names[pci_id->driver_data];
1da177e4
LT
435 const char *dev_name = pci_name(pci_dev);
436
437/* when built into the kernel, we only print version if device is found */
438#ifndef MODULE
439 static int printed_version;
440 if (!printed_version++)
441 printk(version);
442#endif
443
444 /* setup various bits in PCI command register */
445 ret = pci_enable_device(pci_dev);
446 if(ret) return ret;
6aa20a22 447
284901a9 448 i = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
1da177e4 449 if(i){
2450022a 450 printk(KERN_ERR "sis900.c: architecture does not support "
1da177e4
LT
451 "32bit PCI busmaster DMA\n");
452 return i;
453 }
6aa20a22 454
1da177e4 455 pci_set_master(pci_dev);
6aa20a22 456
1da177e4
LT
457 net_dev = alloc_etherdev(sizeof(struct sis900_private));
458 if (!net_dev)
459 return -ENOMEM;
1da177e4
LT
460 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
461
462 /* We do a request_region() to register /proc/ioports info. */
1da177e4
LT
463 ret = pci_request_regions(pci_dev, "sis900");
464 if (ret)
465 goto err_out;
466
57d6d456
FR
467 /* IO region. */
468 ioaddr = pci_iomap(pci_dev, 0, 0);
0968a9d1
PST
469 if (!ioaddr) {
470 ret = -ENOMEM;
57d6d456 471 goto err_out_cleardev;
0968a9d1 472 }
57d6d456 473
8f15ea42 474 sis_priv = netdev_priv(net_dev);
57d6d456 475 sis_priv->ioaddr = ioaddr;
1da177e4
LT
476 sis_priv->pci_dev = pci_dev;
477 spin_lock_init(&sis_priv->lock);
478
479 pci_set_drvdata(pci_dev, net_dev);
480
481 ring_space = pci_alloc_consistent(pci_dev, TX_TOTAL_SIZE, &ring_dma);
482 if (!ring_space) {
483 ret = -ENOMEM;
57d6d456 484 goto err_out_unmap;
1da177e4 485 }
43d620c8 486 sis_priv->tx_ring = ring_space;
1da177e4
LT
487 sis_priv->tx_ring_dma = ring_dma;
488
489 ring_space = pci_alloc_consistent(pci_dev, RX_TOTAL_SIZE, &ring_dma);
490 if (!ring_space) {
491 ret = -ENOMEM;
492 goto err_unmap_tx;
493 }
43d620c8 494 sis_priv->rx_ring = ring_space;
1da177e4 495 sis_priv->rx_ring_dma = ring_dma;
6aa20a22 496
1da177e4 497 /* The SiS900-specific entries in the device structure. */
09ab9e7c 498 net_dev->netdev_ops = &sis900_netdev_ops;
1da177e4
LT
499 net_dev->watchdog_timeo = TX_TIMEOUT;
500 net_dev->ethtool_ops = &sis900_ethtool_ops;
501
1da177e4
LT
502 if (sis900_debug > 0)
503 sis_priv->msg_enable = sis900_debug;
504 else
505 sis_priv->msg_enable = SIS900_DEF_MSG;
da369b01
DV
506
507 sis_priv->mii_info.dev = net_dev;
508 sis_priv->mii_info.mdio_read = mdio_read;
509 sis_priv->mii_info.mdio_write = mdio_write;
510 sis_priv->mii_info.phy_id_mask = 0x1f;
511 sis_priv->mii_info.reg_num_mask = 0x1f;
512
1da177e4 513 /* Get Mac address according to the chip revision */
eaaa3a7c 514 sis_priv->chipset_rev = pci_dev->revision;
1da177e4
LT
515 if(netif_msg_probe(sis_priv))
516 printk(KERN_DEBUG "%s: detected revision %2.2x, "
517 "trying to get MAC address...\n",
518 dev_name, sis_priv->chipset_rev);
6aa20a22 519
1da177e4
LT
520 ret = 0;
521 if (sis_priv->chipset_rev == SIS630E_900_REV)
522 ret = sis630e_get_mac_addr(pci_dev, net_dev);
523 else if ((sis_priv->chipset_rev > 0x81) && (sis_priv->chipset_rev <= 0x90) )
524 ret = sis635_get_mac_addr(pci_dev, net_dev);
525 else if (sis_priv->chipset_rev == SIS96x_900_REV)
526 ret = sis96x_get_mac_addr(pci_dev, net_dev);
527 else
528 ret = sis900_get_mac_addr(pci_dev, net_dev);
529
d1d5e6b1 530 if (!ret || !is_valid_ether_addr(net_dev->dev_addr)) {
f2cedb63 531 eth_hw_addr_random(net_dev);
d1d5e6b1
DV
532 printk(KERN_WARNING "%s: Unreadable or invalid MAC address,"
533 "using random generated one\n", dev_name);
1da177e4 534 }
6aa20a22 535
1da177e4
LT
536 /* 630ET : set the mii access mode as software-mode */
537 if (sis_priv->chipset_rev == SIS630ET_900_REV)
57d6d456 538 sw32(cr, ACCESSMODE | sr32(cr));
1da177e4
LT
539
540 /* probe for mii transceiver */
541 if (sis900_mii_probe(net_dev) == 0) {
542 printk(KERN_WARNING "%s: Error probing MII device.\n",
543 dev_name);
544 ret = -ENODEV;
545 goto err_unmap_rx;
546 }
547
548 /* save our host bridge revision */
549 dev = pci_get_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_630, NULL);
550 if (dev) {
eaaa3a7c 551 sis_priv->host_bridge_rev = dev->revision;
1da177e4
LT
552 pci_dev_put(dev);
553 }
554
555 ret = register_netdev(net_dev);
556 if (ret)
557 goto err_unmap_rx;
558
559 /* print some information about our NIC */
57d6d456
FR
560 printk(KERN_INFO "%s: %s at 0x%p, IRQ %d, %pM\n",
561 net_dev->name, card_name, ioaddr, pci_dev->irq,
e174961c 562 net_dev->dev_addr);
1da177e4 563
ea37ccea 564 /* Detect Wake on Lan support */
57d6d456 565 ret = (sr32(CFGPMC) & PMESP) >> 27;
ea37ccea
DV
566 if (netif_msg_probe(sis_priv) && (ret & PME_D3C) == 0)
567 printk(KERN_INFO "%s: Wake on LAN only available from suspend to RAM.", net_dev->name);
568
1da177e4
LT
569 return 0;
570
57d6d456 571err_unmap_rx:
1da177e4
LT
572 pci_free_consistent(pci_dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
573 sis_priv->rx_ring_dma);
57d6d456 574err_unmap_tx:
1da177e4
LT
575 pci_free_consistent(pci_dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
576 sis_priv->tx_ring_dma);
57d6d456
FR
577err_out_unmap:
578 pci_iounmap(pci_dev, ioaddr);
579err_out_cleardev:
1da177e4
LT
580 pci_release_regions(pci_dev);
581 err_out:
582 free_netdev(net_dev);
583 return ret;
584}
585
586/**
587 * sis900_mii_probe - Probe MII PHY for sis900
588 * @net_dev: the net device to probe for
6aa20a22 589 *
1da177e4
LT
590 * Search for total of 32 possible mii phy addresses.
591 * Identify and set current phy if found one,
592 * return error if it failed to found.
593 */
594
369e1231 595static int sis900_mii_probe(struct net_device *net_dev)
1da177e4 596{
8f15ea42 597 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
598 const char *dev_name = pci_name(sis_priv->pci_dev);
599 u16 poll_bit = MII_STAT_LINK, status = 0;
600 unsigned long timeout = jiffies + 5 * HZ;
601 int phy_addr;
602
603 sis_priv->mii = NULL;
604
605 /* search for total of 32 possible mii phy addresses */
6aa20a22 606 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
1da177e4
LT
607 struct mii_phy * mii_phy = NULL;
608 u16 mii_status;
609 int i;
610
611 mii_phy = NULL;
612 for(i = 0; i < 2; i++)
613 mii_status = mdio_read(net_dev, phy_addr, MII_STATUS);
614
615 if (mii_status == 0xffff || mii_status == 0x0000) {
616 if (netif_msg_probe(sis_priv))
617 printk(KERN_DEBUG "%s: MII at address %d"
618 " not accessible\n",
619 dev_name, phy_addr);
620 continue;
621 }
6aa20a22 622
1da177e4 623 if ((mii_phy = kmalloc(sizeof(struct mii_phy), GFP_KERNEL)) == NULL) {
1da177e4
LT
624 mii_phy = sis_priv->first_mii;
625 while (mii_phy) {
626 struct mii_phy *phy;
627 phy = mii_phy;
628 mii_phy = mii_phy->next;
629 kfree(phy);
630 }
631 return 0;
632 }
6aa20a22 633
1da177e4 634 mii_phy->phy_id0 = mdio_read(net_dev, phy_addr, MII_PHY_ID0);
6aa20a22 635 mii_phy->phy_id1 = mdio_read(net_dev, phy_addr, MII_PHY_ID1);
1da177e4
LT
636 mii_phy->phy_addr = phy_addr;
637 mii_phy->status = mii_status;
638 mii_phy->next = sis_priv->mii;
639 sis_priv->mii = mii_phy;
640 sis_priv->first_mii = mii_phy;
641
642 for (i = 0; mii_chip_table[i].phy_id1; i++)
643 if ((mii_phy->phy_id0 == mii_chip_table[i].phy_id0 ) &&
644 ((mii_phy->phy_id1 & 0xFFF0) == mii_chip_table[i].phy_id1)){
645 mii_phy->phy_types = mii_chip_table[i].phy_types;
646 if (mii_chip_table[i].phy_types == MIX)
647 mii_phy->phy_types =
648 (mii_status & (MII_STAT_CAN_TX_FDX | MII_STAT_CAN_TX)) ? LAN : HOME;
649 printk(KERN_INFO "%s: %s transceiver found "
650 "at address %d.\n",
651 dev_name,
652 mii_chip_table[i].name,
653 phy_addr);
654 break;
655 }
6aa20a22 656
1da177e4
LT
657 if( !mii_chip_table[i].phy_id1 ) {
658 printk(KERN_INFO "%s: Unknown PHY transceiver found at address %d.\n",
659 dev_name, phy_addr);
660 mii_phy->phy_types = UNKNOWN;
661 }
662 }
6aa20a22 663
1da177e4
LT
664 if (sis_priv->mii == NULL) {
665 printk(KERN_INFO "%s: No MII transceivers found!\n", dev_name);
666 return 0;
667 }
668
669 /* select default PHY for mac */
670 sis_priv->mii = NULL;
671 sis900_default_phy( net_dev );
672
673 /* Reset phy if default phy is internal sis900 */
674 if ((sis_priv->mii->phy_id0 == 0x001D) &&
675 ((sis_priv->mii->phy_id1&0xFFF0) == 0x8000))
676 status = sis900_reset_phy(net_dev, sis_priv->cur_phy);
6aa20a22 677
1da177e4
LT
678 /* workaround for ICS1893 PHY */
679 if ((sis_priv->mii->phy_id0 == 0x0015) &&
680 ((sis_priv->mii->phy_id1&0xFFF0) == 0xF440))
681 mdio_write(net_dev, sis_priv->cur_phy, 0x0018, 0xD200);
682
683 if(status & MII_STAT_LINK){
684 while (poll_bit) {
685 yield();
686
687 poll_bit ^= (mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS) & poll_bit);
688 if (time_after_eq(jiffies, timeout)) {
689 printk(KERN_WARNING "%s: reset phy and link down now\n",
690 dev_name);
691 return -ETIME;
692 }
693 }
694 }
695
696 if (sis_priv->chipset_rev == SIS630E_900_REV) {
697 /* SiS 630E has some bugs on default value of PHY registers */
698 mdio_write(net_dev, sis_priv->cur_phy, MII_ANADV, 0x05e1);
699 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG1, 0x22);
700 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG2, 0xff00);
701 mdio_write(net_dev, sis_priv->cur_phy, MII_MASK, 0xffc0);
6aa20a22 702 //mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, 0x1000);
1da177e4
LT
703 }
704
705 if (sis_priv->mii->status & MII_STAT_LINK)
706 netif_carrier_on(net_dev);
707 else
708 netif_carrier_off(net_dev);
709
710 return 1;
711}
712
713/**
714 * sis900_default_phy - Select default PHY for sis900 mac.
715 * @net_dev: the net device to probe for
716 *
717 * Select first detected PHY with link as default.
718 * If no one is link on, select PHY whose types is HOME as default.
719 * If HOME doesn't exist, select LAN.
720 */
721
722static u16 sis900_default_phy(struct net_device * net_dev)
723{
8f15ea42 724 struct sis900_private *sis_priv = netdev_priv(net_dev);
6aa20a22 725 struct mii_phy *phy = NULL, *phy_home = NULL,
1da177e4
LT
726 *default_phy = NULL, *phy_lan = NULL;
727 u16 status;
728
729 for (phy=sis_priv->first_mii; phy; phy=phy->next) {
730 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
731 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
732
733 /* Link ON & Not select default PHY & not ghost PHY */
734 if ((status & MII_STAT_LINK) && !default_phy &&
735 (phy->phy_types != UNKNOWN))
736 default_phy = phy;
737 else {
738 status = mdio_read(net_dev, phy->phy_addr, MII_CONTROL);
739 mdio_write(net_dev, phy->phy_addr, MII_CONTROL,
740 status | MII_CNTL_AUTO | MII_CNTL_ISOLATE);
741 if (phy->phy_types == HOME)
742 phy_home = phy;
743 else if(phy->phy_types == LAN)
744 phy_lan = phy;
745 }
746 }
747
748 if (!default_phy && phy_home)
749 default_phy = phy_home;
750 else if (!default_phy && phy_lan)
751 default_phy = phy_lan;
752 else if (!default_phy)
753 default_phy = sis_priv->first_mii;
754
755 if (sis_priv->mii != default_phy) {
756 sis_priv->mii = default_phy;
757 sis_priv->cur_phy = default_phy->phy_addr;
758 printk(KERN_INFO "%s: Using transceiver found at address %d as default\n",
759 pci_name(sis_priv->pci_dev), sis_priv->cur_phy);
760 }
6aa20a22 761
da369b01
DV
762 sis_priv->mii_info.phy_id = sis_priv->cur_phy;
763
1da177e4
LT
764 status = mdio_read(net_dev, sis_priv->cur_phy, MII_CONTROL);
765 status &= (~MII_CNTL_ISOLATE);
766
6aa20a22 767 mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, status);
1da177e4
LT
768 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
769 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
770
6aa20a22 771 return status;
1da177e4
LT
772}
773
774
775/**
776 * sis900_set_capability - set the media capability of network adapter.
777 * @net_dev : the net device to probe for
778 * @phy : default PHY
779 *
780 * Set the media capability of network adapter according to
781 * mii status register. It's necessary before auto-negotiate.
782 */
6aa20a22 783
1da177e4
LT
784static void sis900_set_capability(struct net_device *net_dev, struct mii_phy *phy)
785{
786 u16 cap;
787 u16 status;
6aa20a22 788
1da177e4
LT
789 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
790 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
6aa20a22 791
1da177e4
LT
792 cap = MII_NWAY_CSMA_CD |
793 ((phy->status & MII_STAT_CAN_TX_FDX)? MII_NWAY_TX_FDX:0) |
794 ((phy->status & MII_STAT_CAN_TX) ? MII_NWAY_TX:0) |
795 ((phy->status & MII_STAT_CAN_T_FDX) ? MII_NWAY_T_FDX:0)|
796 ((phy->status & MII_STAT_CAN_T) ? MII_NWAY_T:0);
797
798 mdio_write(net_dev, phy->phy_addr, MII_ANADV, cap);
799}
800
801
802/* Delay between EEPROM clock transitions. */
57d6d456 803#define eeprom_delay() sr32(mear)
1da177e4
LT
804
805/**
806 * read_eeprom - Read Serial EEPROM
807 * @ioaddr: base i/o address
808 * @location: the EEPROM location to read
809 *
810 * Read Serial EEPROM through EEPROM Access Register.
811 * Note that location is in word (16 bits) unit
812 */
813
369e1231 814static u16 read_eeprom(void __iomem *ioaddr, int location)
1da177e4 815{
57d6d456 816 u32 read_cmd = location | EEread;
1da177e4
LT
817 int i;
818 u16 retval = 0;
1da177e4 819
57d6d456 820 sw32(mear, 0);
1da177e4 821 eeprom_delay();
57d6d456 822 sw32(mear, EECS);
1da177e4
LT
823 eeprom_delay();
824
825 /* Shift the read command (9) bits out. */
826 for (i = 8; i >= 0; i--) {
827 u32 dataval = (read_cmd & (1 << i)) ? EEDI | EECS : EECS;
57d6d456
FR
828
829 sw32(mear, dataval);
1da177e4 830 eeprom_delay();
57d6d456 831 sw32(mear, dataval | EECLK);
1da177e4
LT
832 eeprom_delay();
833 }
57d6d456 834 sw32(mear, EECS);
1da177e4
LT
835 eeprom_delay();
836
837 /* read the 16-bits data in */
838 for (i = 16; i > 0; i--) {
57d6d456 839 sw32(mear, EECS);
1da177e4 840 eeprom_delay();
57d6d456 841 sw32(mear, EECS | EECLK);
1da177e4 842 eeprom_delay();
57d6d456 843 retval = (retval << 1) | ((sr32(mear) & EEDO) ? 1 : 0);
1da177e4
LT
844 eeprom_delay();
845 }
846
847 /* Terminate the EEPROM access. */
57d6d456 848 sw32(mear, 0);
1da177e4
LT
849 eeprom_delay();
850
807540ba 851 return retval;
1da177e4
LT
852}
853
854/* Read and write the MII management registers using software-generated
855 serial MDIO protocol. Note that the command bits and data bits are
856 send out separately */
57d6d456 857#define mdio_delay() sr32(mear)
1da177e4 858
57d6d456 859static void mdio_idle(struct sis900_private *sp)
1da177e4 860{
57d6d456
FR
861 void __iomem *ioaddr = sp->ioaddr;
862
863 sw32(mear, MDIO | MDDIR);
1da177e4 864 mdio_delay();
57d6d456 865 sw32(mear, MDIO | MDDIR | MDC);
1da177e4
LT
866}
867
57d6d456
FR
868/* Synchronize the MII management interface by shifting 32 one bits out. */
869static void mdio_reset(struct sis900_private *sp)
1da177e4 870{
57d6d456 871 void __iomem *ioaddr = sp->ioaddr;
1da177e4
LT
872 int i;
873
874 for (i = 31; i >= 0; i--) {
57d6d456 875 sw32(mear, MDDIR | MDIO);
1da177e4 876 mdio_delay();
57d6d456 877 sw32(mear, MDDIR | MDIO | MDC);
1da177e4
LT
878 mdio_delay();
879 }
1da177e4
LT
880}
881
882/**
883 * mdio_read - read MII PHY register
884 * @net_dev: the net device to read
885 * @phy_id: the phy address to read
886 * @location: the phy regiester id to read
887 *
888 * Read MII registers through MDIO and MDC
889 * using MDIO management frame structure and protocol(defined by ISO/IEC).
890 * Please see SiS7014 or ICS spec
891 */
892
da369b01 893static int mdio_read(struct net_device *net_dev, int phy_id, int location)
1da177e4 894{
1da177e4 895 int mii_cmd = MIIread|(phy_id<<MIIpmdShift)|(location<<MIIregShift);
57d6d456
FR
896 struct sis900_private *sp = netdev_priv(net_dev);
897 void __iomem *ioaddr = sp->ioaddr;
1da177e4
LT
898 u16 retval = 0;
899 int i;
900
57d6d456
FR
901 mdio_reset(sp);
902 mdio_idle(sp);
1da177e4
LT
903
904 for (i = 15; i >= 0; i--) {
905 int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR;
57d6d456
FR
906
907 sw32(mear, dataval);
1da177e4 908 mdio_delay();
57d6d456 909 sw32(mear, dataval | MDC);
1da177e4
LT
910 mdio_delay();
911 }
912
913 /* Read the 16 data bits. */
914 for (i = 16; i > 0; i--) {
57d6d456 915 sw32(mear, 0);
1da177e4 916 mdio_delay();
57d6d456
FR
917 retval = (retval << 1) | ((sr32(mear) & MDIO) ? 1 : 0);
918 sw32(mear, MDC);
1da177e4
LT
919 mdio_delay();
920 }
57d6d456 921 sw32(mear, 0x00);
1da177e4
LT
922
923 return retval;
924}
925
926/**
927 * mdio_write - write MII PHY register
928 * @net_dev: the net device to write
929 * @phy_id: the phy address to write
930 * @location: the phy regiester id to write
931 * @value: the register value to write with
932 *
933 * Write MII registers with @value through MDIO and MDC
934 * using MDIO management frame structure and protocol(defined by ISO/IEC)
935 * please see SiS7014 or ICS spec
936 */
937
938static void mdio_write(struct net_device *net_dev, int phy_id, int location,
939 int value)
940{
1da177e4 941 int mii_cmd = MIIwrite|(phy_id<<MIIpmdShift)|(location<<MIIregShift);
57d6d456
FR
942 struct sis900_private *sp = netdev_priv(net_dev);
943 void __iomem *ioaddr = sp->ioaddr;
1da177e4
LT
944 int i;
945
57d6d456
FR
946 mdio_reset(sp);
947 mdio_idle(sp);
1da177e4
LT
948
949 /* Shift the command bits out. */
950 for (i = 15; i >= 0; i--) {
951 int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR;
57d6d456
FR
952
953 sw8(mear, dataval);
1da177e4 954 mdio_delay();
57d6d456 955 sw8(mear, dataval | MDC);
1da177e4
LT
956 mdio_delay();
957 }
958 mdio_delay();
959
960 /* Shift the value bits out. */
961 for (i = 15; i >= 0; i--) {
962 int dataval = (value & (1 << i)) ? MDDIR | MDIO : MDDIR;
57d6d456
FR
963
964 sw32(mear, dataval);
1da177e4 965 mdio_delay();
57d6d456 966 sw32(mear, dataval | MDC);
1da177e4
LT
967 mdio_delay();
968 }
969 mdio_delay();
970
971 /* Clear out extra bits. */
972 for (i = 2; i > 0; i--) {
57d6d456 973 sw8(mear, 0);
1da177e4 974 mdio_delay();
57d6d456 975 sw8(mear, MDC);
1da177e4
LT
976 mdio_delay();
977 }
57d6d456 978 sw32(mear, 0x00);
1da177e4
LT
979}
980
981
982/**
983 * sis900_reset_phy - reset sis900 mii phy.
984 * @net_dev: the net device to write
985 * @phy_addr: default phy address
986 *
987 * Some specific phy can't work properly without reset.
988 * This function will be called during initialization and
989 * link status change from ON to DOWN.
990 */
991
992static u16 sis900_reset_phy(struct net_device *net_dev, int phy_addr)
993{
f3be9742 994 int i;
1da177e4
LT
995 u16 status;
996
f3be9742 997 for (i = 0; i < 2; i++)
1da177e4
LT
998 status = mdio_read(net_dev, phy_addr, MII_STATUS);
999
1000 mdio_write( net_dev, phy_addr, MII_CONTROL, MII_CNTL_RESET );
6aa20a22 1001
1da177e4
LT
1002 return status;
1003}
1004
1005#ifdef CONFIG_NET_POLL_CONTROLLER
1006/*
1007 * Polling 'interrupt' - used by things like netconsole to send skbs
1008 * without having to re-enable interrupts. It's not called while
1009 * the interrupt routine is executing.
1010*/
1011static void sis900_poll(struct net_device *dev)
1012{
57d6d456
FR
1013 struct sis900_private *sp = netdev_priv(dev);
1014 const int irq = sp->pci_dev->irq;
1015
1016 disable_irq(irq);
1017 sis900_interrupt(irq, dev);
1018 enable_irq(irq);
1da177e4
LT
1019}
1020#endif
1021
1022/**
1023 * sis900_open - open sis900 device
1024 * @net_dev: the net device to open
1025 *
1026 * Do some initialization and start net interface.
1027 * enable interrupts and set sis900 timer.
1028 */
1029
1030static int
1031sis900_open(struct net_device *net_dev)
1032{
8f15ea42 1033 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456 1034 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
1035 int ret;
1036
1037 /* Soft reset the chip. */
1038 sis900_reset(net_dev);
1039
1040 /* Equalizer workaround Rule */
1041 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1042
57d6d456
FR
1043 ret = request_irq(sis_priv->pci_dev->irq, sis900_interrupt, IRQF_SHARED,
1044 net_dev->name, net_dev);
1da177e4
LT
1045 if (ret)
1046 return ret;
1047
1048 sis900_init_rxfilter(net_dev);
1049
1050 sis900_init_tx_ring(net_dev);
1051 sis900_init_rx_ring(net_dev);
1052
1053 set_rx_mode(net_dev);
1054
1055 netif_start_queue(net_dev);
1056
1057 /* Workaround for EDB */
57d6d456 1058 sis900_set_mode(sis_priv, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
1da177e4
LT
1059
1060 /* Enable all known interrupts by setting the interrupt mask. */
57d6d456
FR
1061 sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxIDLE);
1062 sw32(cr, RxENA | sr32(cr));
1063 sw32(ier, IE);
1da177e4
LT
1064
1065 sis900_check_mode(net_dev, sis_priv->mii);
1066
1067 /* Set the timer to switch to check for link beat and perhaps switch
1068 to an alternate media type. */
1069 init_timer(&sis_priv->timer);
1070 sis_priv->timer.expires = jiffies + HZ;
1071 sis_priv->timer.data = (unsigned long)net_dev;
c061b18d 1072 sis_priv->timer.function = sis900_timer;
1da177e4
LT
1073 add_timer(&sis_priv->timer);
1074
1075 return 0;
1076}
1077
1078/**
1079 * sis900_init_rxfilter - Initialize the Rx filter
1080 * @net_dev: the net device to initialize for
1081 *
1082 * Set receive filter address to our MAC address
1083 * and enable packet filtering.
1084 */
1085
1086static void
1087sis900_init_rxfilter (struct net_device * net_dev)
1088{
8f15ea42 1089 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456 1090 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
1091 u32 rfcrSave;
1092 u32 i;
1093
57d6d456 1094 rfcrSave = sr32(rfcr);
1da177e4
LT
1095
1096 /* disable packet filtering before setting filter */
57d6d456 1097 sw32(rfcr, rfcrSave & ~RFEN);
1da177e4
LT
1098
1099 /* load MAC addr to filter data register */
1100 for (i = 0 ; i < 3 ; i++) {
57d6d456 1101 u32 w = (u32) *((u16 *)(net_dev->dev_addr)+i);
1da177e4 1102
57d6d456
FR
1103 sw32(rfcr, i << RFADDR_shift);
1104 sw32(rfdr, w);
1da177e4
LT
1105
1106 if (netif_msg_hw(sis_priv)) {
1107 printk(KERN_DEBUG "%s: Receive Filter Addrss[%d]=%x\n",
57d6d456 1108 net_dev->name, i, sr32(rfdr));
1da177e4
LT
1109 }
1110 }
1111
1112 /* enable packet filtering */
57d6d456 1113 sw32(rfcr, rfcrSave | RFEN);
1da177e4
LT
1114}
1115
1116/**
1117 * sis900_init_tx_ring - Initialize the Tx descriptor ring
1118 * @net_dev: the net device to initialize for
1119 *
6aa20a22 1120 * Initialize the Tx descriptor ring,
1da177e4
LT
1121 */
1122
1123static void
1124sis900_init_tx_ring(struct net_device *net_dev)
1125{
8f15ea42 1126 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456 1127 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
1128 int i;
1129
1130 sis_priv->tx_full = 0;
1131 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1132
1133 for (i = 0; i < NUM_TX_DESC; i++) {
1134 sis_priv->tx_skbuff[i] = NULL;
1135
1136 sis_priv->tx_ring[i].link = sis_priv->tx_ring_dma +
1137 ((i+1)%NUM_TX_DESC)*sizeof(BufferDesc);
1138 sis_priv->tx_ring[i].cmdsts = 0;
1139 sis_priv->tx_ring[i].bufptr = 0;
1140 }
1141
1142 /* load Transmit Descriptor Register */
57d6d456 1143 sw32(txdp, sis_priv->tx_ring_dma);
1da177e4
LT
1144 if (netif_msg_hw(sis_priv))
1145 printk(KERN_DEBUG "%s: TX descriptor register loaded with: %8.8x\n",
57d6d456 1146 net_dev->name, sr32(txdp));
1da177e4
LT
1147}
1148
1149/**
1150 * sis900_init_rx_ring - Initialize the Rx descriptor ring
1151 * @net_dev: the net device to initialize for
1152 *
6aa20a22 1153 * Initialize the Rx descriptor ring,
1da177e4
LT
1154 * and pre-allocate recevie buffers (socket buffer)
1155 */
1156
6aa20a22 1157static void
1da177e4
LT
1158sis900_init_rx_ring(struct net_device *net_dev)
1159{
8f15ea42 1160 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456 1161 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
1162 int i;
1163
1164 sis_priv->cur_rx = 0;
1165 sis_priv->dirty_rx = 0;
1166
1167 /* init RX descriptor */
1168 for (i = 0; i < NUM_RX_DESC; i++) {
1169 sis_priv->rx_skbuff[i] = NULL;
1170
1171 sis_priv->rx_ring[i].link = sis_priv->rx_ring_dma +
1172 ((i+1)%NUM_RX_DESC)*sizeof(BufferDesc);
1173 sis_priv->rx_ring[i].cmdsts = 0;
1174 sis_priv->rx_ring[i].bufptr = 0;
1175 }
1176
1177 /* allocate sock buffers */
1178 for (i = 0; i < NUM_RX_DESC; i++) {
1179 struct sk_buff *skb;
1180
dae2e9f4 1181 if ((skb = netdev_alloc_skb(net_dev, RX_BUF_SIZE)) == NULL) {
1da177e4
LT
1182 /* not enough memory for skbuff, this makes a "hole"
1183 on the buffer ring, it is not clear how the
1184 hardware will react to this kind of degenerated
1185 buffer */
1186 break;
1187 }
1da177e4
LT
1188 sis_priv->rx_skbuff[i] = skb;
1189 sis_priv->rx_ring[i].cmdsts = RX_BUF_SIZE;
1e8edc2a
DK
1190 sis_priv->rx_ring[i].bufptr = pci_map_single(sis_priv->pci_dev,
1191 skb->data, RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1192 if (unlikely(pci_dma_mapping_error(sis_priv->pci_dev,
1193 sis_priv->rx_ring[i].bufptr))) {
1194 dev_kfree_skb(skb);
1195 sis_priv->rx_skbuff[i] = NULL;
1196 break;
1197 }
1da177e4
LT
1198 }
1199 sis_priv->dirty_rx = (unsigned int) (i - NUM_RX_DESC);
1200
1201 /* load Receive Descriptor Register */
57d6d456 1202 sw32(rxdp, sis_priv->rx_ring_dma);
1da177e4
LT
1203 if (netif_msg_hw(sis_priv))
1204 printk(KERN_DEBUG "%s: RX descriptor register loaded with: %8.8x\n",
57d6d456 1205 net_dev->name, sr32(rxdp));
1da177e4
LT
1206}
1207
1208/**
1209 * sis630_set_eq - set phy equalizer value for 630 LAN
1210 * @net_dev: the net device to set equalizer value
1211 * @revision: 630 LAN revision number
1212 *
1213 * 630E equalizer workaround rule(Cyrus Huang 08/15)
1214 * PHY register 14h(Test)
25985edc 1215 * Bit 14: 0 -- Automatically detect (default)
1da177e4
LT
1216 * 1 -- Manually set Equalizer filter
1217 * Bit 13: 0 -- (Default)
1218 * 1 -- Speed up convergence of equalizer setting
1219 * Bit 9 : 0 -- (Default)
1220 * 1 -- Disable Baseline Wander
1221 * Bit 3~7 -- Equalizer filter setting
1222 * Link ON: Set Bit 9, 13 to 1, Bit 14 to 0
1223 * Then calculate equalizer value
1224 * Then set equalizer value, and set Bit 14 to 1, Bit 9 to 0
1225 * Link Off:Set Bit 13 to 1, Bit 14 to 0
1226 * Calculate Equalizer value:
25985edc 1227 * When Link is ON and Bit 14 is 0, SIS900PHY will auto-detect proper equalizer value.
1da177e4
LT
1228 * When the equalizer is stable, this value is not a fixed value. It will be within
1229 * a small range(eg. 7~9). Then we get a minimum and a maximum value(eg. min=7, max=9)
1230 * 0 <= max <= 4 --> set equalizer to max
1231 * 5 <= max <= 14 --> set equalizer to max+1 or set equalizer to max+2 if max == min
1232 * max >= 15 --> set equalizer to max+5 or set equalizer to max+6 if max == min
1233 */
1234
1235static void sis630_set_eq(struct net_device *net_dev, u8 revision)
1236{
8f15ea42 1237 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1238 u16 reg14h, eq_value=0, max_value=0, min_value=0;
1239 int i, maxcount=10;
1240
1241 if ( !(revision == SIS630E_900_REV || revision == SIS630EA1_900_REV ||
1242 revision == SIS630A_900_REV || revision == SIS630ET_900_REV) )
1243 return;
1244
1245 if (netif_carrier_ok(net_dev)) {
1246 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1247 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1248 (0x2200 | reg14h) & 0xBFFF);
1249 for (i=0; i < maxcount; i++) {
1250 eq_value = (0x00F8 & mdio_read(net_dev,
1251 sis_priv->cur_phy, MII_RESV)) >> 3;
1252 if (i == 0)
1253 max_value=min_value=eq_value;
1254 max_value = (eq_value > max_value) ?
1255 eq_value : max_value;
1256 min_value = (eq_value < min_value) ?
1257 eq_value : min_value;
1258 }
1259 /* 630E rule to determine the equalizer value */
1260 if (revision == SIS630E_900_REV || revision == SIS630EA1_900_REV ||
1261 revision == SIS630ET_900_REV) {
1262 if (max_value < 5)
1263 eq_value = max_value;
1264 else if (max_value >= 5 && max_value < 15)
1265 eq_value = (max_value == min_value) ?
1266 max_value+2 : max_value+1;
1267 else if (max_value >= 15)
1268 eq_value=(max_value == min_value) ?
1269 max_value+6 : max_value+5;
1270 }
1271 /* 630B0&B1 rule to determine the equalizer value */
6aa20a22
JG
1272 if (revision == SIS630A_900_REV &&
1273 (sis_priv->host_bridge_rev == SIS630B0 ||
1da177e4
LT
1274 sis_priv->host_bridge_rev == SIS630B1)) {
1275 if (max_value == 0)
1276 eq_value = 3;
1277 else
1278 eq_value = (max_value + min_value + 1)/2;
1279 }
1280 /* write equalizer value and setting */
1281 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1282 reg14h = (reg14h & 0xFF07) | ((eq_value << 3) & 0x00F8);
1283 reg14h = (reg14h | 0x6000) & 0xFDFF;
1284 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV, reg14h);
1285 } else {
1286 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
6aa20a22
JG
1287 if (revision == SIS630A_900_REV &&
1288 (sis_priv->host_bridge_rev == SIS630B0 ||
1289 sis_priv->host_bridge_rev == SIS630B1))
1da177e4
LT
1290 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1291 (reg14h | 0x2200) & 0xBFFF);
1292 else
1293 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1294 (reg14h | 0x2000) & 0xBFFF);
1295 }
1da177e4
LT
1296}
1297
1298/**
1299 * sis900_timer - sis900 timer routine
1300 * @data: pointer to sis900 net device
1301 *
6aa20a22 1302 * On each timer ticks we check two things,
1da177e4
LT
1303 * link status (ON/OFF) and link mode (10/100/Full/Half)
1304 */
1305
1306static void sis900_timer(unsigned long data)
1307{
1308 struct net_device *net_dev = (struct net_device *)data;
8f15ea42 1309 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4 1310 struct mii_phy *mii_phy = sis_priv->mii;
f71e1309 1311 static const int next_tick = 5*HZ;
78f1ccc4 1312 int speed = 0, duplex = 0;
1da177e4
LT
1313 u16 status;
1314
1da177e4
LT
1315 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1316 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1317
1318 /* Link OFF -> ON */
1319 if (!netif_carrier_ok(net_dev)) {
1320 LookForLink:
1321 /* Search for new PHY */
1322 status = sis900_default_phy(net_dev);
1323 mii_phy = sis_priv->mii;
1324
78f1ccc4
DK
1325 if (status & MII_STAT_LINK) {
1326 WARN_ON(!(status & MII_STAT_AUTO_DONE));
1327
1328 sis900_read_mode(net_dev, &speed, &duplex);
1329 if (duplex) {
1330 sis900_set_mode(sis_priv, speed, duplex);
1331 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1332 netif_carrier_on(net_dev);
1333 }
1334 }
1da177e4
LT
1335 } else {
1336 /* Link ON -> OFF */
1337 if (!(status & MII_STAT_LINK)){
1338 netif_carrier_off(net_dev);
1339 if(netif_msg_link(sis_priv))
1340 printk(KERN_INFO "%s: Media Link Off\n", net_dev->name);
1341
1342 /* Change mode issue */
6aa20a22 1343 if ((mii_phy->phy_id0 == 0x001D) &&
1da177e4
LT
1344 ((mii_phy->phy_id1 & 0xFFF0) == 0x8000))
1345 sis900_reset_phy(net_dev, sis_priv->cur_phy);
6aa20a22 1346
1da177e4 1347 sis630_set_eq(net_dev, sis_priv->chipset_rev);
6aa20a22 1348
1da177e4
LT
1349 goto LookForLink;
1350 }
1351 }
1352
1353 sis_priv->timer.expires = jiffies + next_tick;
1354 add_timer(&sis_priv->timer);
1355}
1356
1357/**
1358 * sis900_check_mode - check the media mode for sis900
1359 * @net_dev: the net device to be checked
1360 * @mii_phy: the mii phy
1361 *
1362 * Older driver gets the media mode from mii status output
1363 * register. Now we set our media capability and auto-negotiate
1364 * to get the upper bound of speed and duplex between two ends.
1365 * If the types of mii phy is HOME, it doesn't need to auto-negotiate
1366 * and autong_complete should be set to 1.
1367 */
1368
1369static void sis900_check_mode(struct net_device *net_dev, struct mii_phy *mii_phy)
1370{
8f15ea42 1371 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456 1372 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
1373 int speed, duplex;
1374
1375 if (mii_phy->phy_types == LAN) {
57d6d456 1376 sw32(cfg, ~EXD & sr32(cfg));
1da177e4
LT
1377 sis900_set_capability(net_dev , mii_phy);
1378 sis900_auto_negotiate(net_dev, sis_priv->cur_phy);
1379 } else {
57d6d456 1380 sw32(cfg, EXD | sr32(cfg));
1da177e4
LT
1381 speed = HW_SPEED_HOME;
1382 duplex = FDX_CAPABLE_HALF_SELECTED;
57d6d456 1383 sis900_set_mode(sis_priv, speed, duplex);
1da177e4
LT
1384 sis_priv->autong_complete = 1;
1385 }
1386}
1387
1388/**
1389 * sis900_set_mode - Set the media mode of mac register.
57d6d456 1390 * @sp: the device private data
1da177e4
LT
1391 * @speed : the transmit speed to be determined
1392 * @duplex: the duplex mode to be determined
1393 *
1394 * Set the media mode of mac register txcfg/rxcfg according to
1395 * speed and duplex of phy. Bit EDB_MASTER_EN indicates the EDB
1396 * bus is used instead of PCI bus. When this bit is set 1, the
1397 * Max DMA Burst Size for TX/RX DMA should be no larger than 16
1398 * double words.
1399 */
1400
57d6d456 1401static void sis900_set_mode(struct sis900_private *sp, int speed, int duplex)
1da177e4 1402{
57d6d456 1403 void __iomem *ioaddr = sp->ioaddr;
1da177e4
LT
1404 u32 tx_flags = 0, rx_flags = 0;
1405
57d6d456 1406 if (sr32( cfg) & EDB_MASTER_EN) {
1da177e4
LT
1407 tx_flags = TxATP | (DMA_BURST_64 << TxMXDMA_shift) |
1408 (TX_FILL_THRESH << TxFILLT_shift);
1409 rx_flags = DMA_BURST_64 << RxMXDMA_shift;
1410 } else {
1411 tx_flags = TxATP | (DMA_BURST_512 << TxMXDMA_shift) |
1412 (TX_FILL_THRESH << TxFILLT_shift);
1413 rx_flags = DMA_BURST_512 << RxMXDMA_shift;
1414 }
1415
1416 if (speed == HW_SPEED_HOME || speed == HW_SPEED_10_MBPS) {
1417 rx_flags |= (RxDRNT_10 << RxDRNT_shift);
1418 tx_flags |= (TxDRNT_10 << TxDRNT_shift);
1419 } else {
1420 rx_flags |= (RxDRNT_100 << RxDRNT_shift);
1421 tx_flags |= (TxDRNT_100 << TxDRNT_shift);
1422 }
1423
1424 if (duplex == FDX_CAPABLE_FULL_SELECTED) {
1425 tx_flags |= (TxCSI | TxHBI);
1426 rx_flags |= RxATX;
1427 }
1428
d269a69f
DV
1429#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
1430 /* Can accept Jumbo packet */
1431 rx_flags |= RxAJAB;
1432#endif
1433
57d6d456
FR
1434 sw32(txcfg, tx_flags);
1435 sw32(rxcfg, rx_flags);
1da177e4
LT
1436}
1437
1438/**
1439 * sis900_auto_negotiate - Set the Auto-Negotiation Enable/Reset bit.
1440 * @net_dev: the net device to read mode for
1441 * @phy_addr: mii phy address
1442 *
1443 * If the adapter is link-on, set the auto-negotiate enable/reset bit.
1444 * autong_complete should be set to 0 when starting auto-negotiation.
1445 * autong_complete should be set to 1 if we didn't start auto-negotiation.
1446 * sis900_timer will wait for link on again if autong_complete = 0.
1447 */
1448
1449static void sis900_auto_negotiate(struct net_device *net_dev, int phy_addr)
1450{
8f15ea42 1451 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1452 int i = 0;
1453 u32 status;
6aa20a22 1454
f3be9742 1455 for (i = 0; i < 2; i++)
1da177e4
LT
1456 status = mdio_read(net_dev, phy_addr, MII_STATUS);
1457
1458 if (!(status & MII_STAT_LINK)){
1459 if(netif_msg_link(sis_priv))
1460 printk(KERN_INFO "%s: Media Link Off\n", net_dev->name);
1461 sis_priv->autong_complete = 1;
1462 netif_carrier_off(net_dev);
1463 return;
1464 }
1465
1466 /* (Re)start AutoNegotiate */
1467 mdio_write(net_dev, phy_addr, MII_CONTROL,
1468 MII_CNTL_AUTO | MII_CNTL_RST_AUTO);
1469 sis_priv->autong_complete = 0;
1470}
1471
1472
1473/**
1474 * sis900_read_mode - read media mode for sis900 internal phy
1475 * @net_dev: the net device to read mode for
1476 * @speed : the transmit speed to be determined
1477 * @duplex : the duplex mode to be determined
1478 *
1479 * The capability of remote end will be put in mii register autorec
1480 * after auto-negotiation. Use AND operation to get the upper bound
1481 * of speed and duplex between two ends.
1482 */
1483
1484static void sis900_read_mode(struct net_device *net_dev, int *speed, int *duplex)
1485{
8f15ea42 1486 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1487 struct mii_phy *phy = sis_priv->mii;
1488 int phy_addr = sis_priv->cur_phy;
1489 u32 status;
1490 u16 autoadv, autorec;
f3be9742 1491 int i;
1da177e4 1492
f3be9742 1493 for (i = 0; i < 2; i++)
1da177e4
LT
1494 status = mdio_read(net_dev, phy_addr, MII_STATUS);
1495
1496 if (!(status & MII_STAT_LINK))
1497 return;
1498
1499 /* AutoNegotiate completed */
1500 autoadv = mdio_read(net_dev, phy_addr, MII_ANADV);
1501 autorec = mdio_read(net_dev, phy_addr, MII_ANLPAR);
1502 status = autoadv & autorec;
6aa20a22 1503
1da177e4
LT
1504 *speed = HW_SPEED_10_MBPS;
1505 *duplex = FDX_CAPABLE_HALF_SELECTED;
1506
1507 if (status & (MII_NWAY_TX | MII_NWAY_TX_FDX))
1508 *speed = HW_SPEED_100_MBPS;
1509 if (status & ( MII_NWAY_TX_FDX | MII_NWAY_T_FDX))
1510 *duplex = FDX_CAPABLE_FULL_SELECTED;
6aa20a22 1511
1da177e4
LT
1512 sis_priv->autong_complete = 1;
1513
1514 /* Workaround for Realtek RTL8201 PHY issue */
1515 if ((phy->phy_id0 == 0x0000) && ((phy->phy_id1 & 0xFFF0) == 0x8200)) {
1516 if (mdio_read(net_dev, phy_addr, MII_CONTROL) & MII_CNTL_FDX)
1517 *duplex = FDX_CAPABLE_FULL_SELECTED;
1518 if (mdio_read(net_dev, phy_addr, 0x0019) & 0x01)
1519 *speed = HW_SPEED_100_MBPS;
1520 }
1521
1522 if(netif_msg_link(sis_priv))
2381a55c 1523 printk(KERN_INFO "%s: Media Link On %s %s-duplex\n",
1da177e4
LT
1524 net_dev->name,
1525 *speed == HW_SPEED_100_MBPS ?
1526 "100mbps" : "10mbps",
1527 *duplex == FDX_CAPABLE_FULL_SELECTED ?
1528 "full" : "half");
1529}
1530
1531/**
1532 * sis900_tx_timeout - sis900 transmit timeout routine
1533 * @net_dev: the net device to transmit
1534 *
1535 * print transmit timeout status
1536 * disable interrupts and do some tasks
1537 */
1538
1539static void sis900_tx_timeout(struct net_device *net_dev)
1540{
8f15ea42 1541 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456 1542 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
1543 unsigned long flags;
1544 int i;
1545
57d6d456 1546 if (netif_msg_tx_err(sis_priv)) {
2381a55c 1547 printk(KERN_INFO "%s: Transmit timeout, status %8.8x %8.8x\n",
57d6d456
FR
1548 net_dev->name, sr32(cr), sr32(isr));
1549 }
1da177e4
LT
1550
1551 /* Disable interrupts by clearing the interrupt mask. */
57d6d456 1552 sw32(imr, 0x0000);
1da177e4
LT
1553
1554 /* use spinlock to prevent interrupt handler accessing buffer ring */
1555 spin_lock_irqsave(&sis_priv->lock, flags);
1556
1557 /* discard unsent packets */
1558 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1559 for (i = 0; i < NUM_TX_DESC; i++) {
1560 struct sk_buff *skb = sis_priv->tx_skbuff[i];
1561
1562 if (skb) {
6aa20a22 1563 pci_unmap_single(sis_priv->pci_dev,
1da177e4
LT
1564 sis_priv->tx_ring[i].bufptr, skb->len,
1565 PCI_DMA_TODEVICE);
1566 dev_kfree_skb_irq(skb);
1567 sis_priv->tx_skbuff[i] = NULL;
1568 sis_priv->tx_ring[i].cmdsts = 0;
1569 sis_priv->tx_ring[i].bufptr = 0;
09f75cd7 1570 net_dev->stats.tx_dropped++;
1da177e4
LT
1571 }
1572 }
1573 sis_priv->tx_full = 0;
1574 netif_wake_queue(net_dev);
1575
1576 spin_unlock_irqrestore(&sis_priv->lock, flags);
1577
860e9538 1578 netif_trans_update(net_dev); /* prevent tx timeout */
1da177e4
LT
1579
1580 /* load Transmit Descriptor Register */
57d6d456 1581 sw32(txdp, sis_priv->tx_ring_dma);
1da177e4
LT
1582
1583 /* Enable all known interrupts by setting the interrupt mask. */
57d6d456 1584 sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxIDLE);
1da177e4
LT
1585}
1586
1587/**
1588 * sis900_start_xmit - sis900 start transmit routine
1589 * @skb: socket buffer pointer to put the data being transmitted
1590 * @net_dev: the net device to transmit with
1591 *
6aa20a22 1592 * Set the transmit buffer descriptor,
1da177e4
LT
1593 * and write TxENA to enable transmit state machine.
1594 * tell upper layer if the buffer is full
1595 */
1596
61357325 1597static netdev_tx_t
1da177e4
LT
1598sis900_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
1599{
8f15ea42 1600 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456 1601 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
1602 unsigned int entry;
1603 unsigned long flags;
1604 unsigned int index_cur_tx, index_dirty_tx;
1605 unsigned int count_dirty_tx;
1606
1da177e4
LT
1607 spin_lock_irqsave(&sis_priv->lock, flags);
1608
1609 /* Calculate the next Tx descriptor entry. */
1610 entry = sis_priv->cur_tx % NUM_TX_DESC;
1611 sis_priv->tx_skbuff[entry] = skb;
1612
1613 /* set the transmit buffer descriptor and enable Transmit State Machine */
1614 sis_priv->tx_ring[entry].bufptr = pci_map_single(sis_priv->pci_dev,
1615 skb->data, skb->len, PCI_DMA_TODEVICE);
1e8edc2a
DK
1616 if (unlikely(pci_dma_mapping_error(sis_priv->pci_dev,
1617 sis_priv->tx_ring[entry].bufptr))) {
828f56f6 1618 dev_kfree_skb_any(skb);
1e8edc2a
DK
1619 sis_priv->tx_skbuff[entry] = NULL;
1620 net_dev->stats.tx_dropped++;
1621 spin_unlock_irqrestore(&sis_priv->lock, flags);
1622 return NETDEV_TX_OK;
1623 }
1da177e4 1624 sis_priv->tx_ring[entry].cmdsts = (OWN | skb->len);
57d6d456 1625 sw32(cr, TxENA | sr32(cr));
1da177e4
LT
1626
1627 sis_priv->cur_tx ++;
1628 index_cur_tx = sis_priv->cur_tx;
1629 index_dirty_tx = sis_priv->dirty_tx;
1630
1631 for (count_dirty_tx = 0; index_cur_tx != index_dirty_tx; index_dirty_tx++)
1632 count_dirty_tx ++;
1633
1634 if (index_cur_tx == index_dirty_tx) {
1635 /* dirty_tx is met in the cycle of cur_tx, buffer full */
1636 sis_priv->tx_full = 1;
1637 netif_stop_queue(net_dev);
6aa20a22 1638 } else if (count_dirty_tx < NUM_TX_DESC) {
1da177e4
LT
1639 /* Typical path, tell upper layer that more transmission is possible */
1640 netif_start_queue(net_dev);
1641 } else {
1642 /* buffer full, tell upper layer no more transmission */
1643 sis_priv->tx_full = 1;
1644 netif_stop_queue(net_dev);
1645 }
1646
1647 spin_unlock_irqrestore(&sis_priv->lock, flags);
1648
1da177e4
LT
1649 if (netif_msg_tx_queued(sis_priv))
1650 printk(KERN_DEBUG "%s: Queued Tx packet at %p size %d "
1651 "to slot %d.\n",
1652 net_dev->name, skb->data, (int)skb->len, entry);
1653
6ed10654 1654 return NETDEV_TX_OK;
1da177e4
LT
1655}
1656
1657/**
1658 * sis900_interrupt - sis900 interrupt handler
1659 * @irq: the irq number
1660 * @dev_instance: the client data object
1da177e4 1661 *
6aa20a22 1662 * The interrupt handler does all of the Rx thread work,
1da177e4
LT
1663 * and cleans up after the Tx thread
1664 */
1665
7d12e780 1666static irqreturn_t sis900_interrupt(int irq, void *dev_instance)
1da177e4
LT
1667{
1668 struct net_device *net_dev = dev_instance;
8f15ea42 1669 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4 1670 int boguscnt = max_interrupt_work;
57d6d456 1671 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
1672 u32 status;
1673 unsigned int handled = 0;
1674
1675 spin_lock (&sis_priv->lock);
1676
1677 do {
57d6d456 1678 status = sr32(isr);
1da177e4
LT
1679
1680 if ((status & (HIBERR|TxURN|TxERR|TxIDLE|RxORN|RxERR|RxOK)) == 0)
1681 /* nothing intresting happened */
1682 break;
1683 handled = 1;
1684
1685 /* why dow't we break after Tx/Rx case ?? keyword: full-duplex */
1686 if (status & (RxORN | RxERR | RxOK))
1687 /* Rx interrupt */
1688 sis900_rx(net_dev);
1689
1690 if (status & (TxURN | TxERR | TxIDLE))
1691 /* Tx interrupt */
1692 sis900_finish_xmit(net_dev);
1693
1694 /* something strange happened !!! */
1695 if (status & HIBERR) {
1696 if(netif_msg_intr(sis_priv))
2450022a 1697 printk(KERN_INFO "%s: Abnormal interrupt, "
1da177e4
LT
1698 "status %#8.8x.\n", net_dev->name, status);
1699 break;
1700 }
1701 if (--boguscnt < 0) {
1702 if(netif_msg_intr(sis_priv))
1703 printk(KERN_INFO "%s: Too much work at interrupt, "
1704 "interrupt status = %#8.8x.\n",
1705 net_dev->name, status);
1706 break;
1707 }
1708 } while (1);
1709
1710 if(netif_msg_intr(sis_priv))
1711 printk(KERN_DEBUG "%s: exiting interrupt, "
8e33a52f 1712 "interrupt status = %#8.8x\n",
57d6d456 1713 net_dev->name, sr32(isr));
6aa20a22 1714
1da177e4
LT
1715 spin_unlock (&sis_priv->lock);
1716 return IRQ_RETVAL(handled);
1717}
1718
1719/**
1720 * sis900_rx - sis900 receive routine
1721 * @net_dev: the net device which receives data
1722 *
6aa20a22 1723 * Process receive interrupt events,
1da177e4 1724 * put buffer to higher layer and refill buffer pool
0b28002f 1725 * Note: This function is called by interrupt handler,
1da177e4
LT
1726 * don't do "too much" work here
1727 */
1728
1729static int sis900_rx(struct net_device *net_dev)
1730{
8f15ea42 1731 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456 1732 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
1733 unsigned int entry = sis_priv->cur_rx % NUM_RX_DESC;
1734 u32 rx_status = sis_priv->rx_ring[entry].cmdsts;
7380a78a 1735 int rx_work_limit;
1da177e4
LT
1736
1737 if (netif_msg_rx_status(sis_priv))
1738 printk(KERN_DEBUG "sis900_rx, cur_rx:%4.4d, dirty_rx:%4.4d "
1739 "status:0x%8.8x\n",
1740 sis_priv->cur_rx, sis_priv->dirty_rx, rx_status);
7380a78a 1741 rx_work_limit = sis_priv->dirty_rx + NUM_RX_DESC - sis_priv->cur_rx;
1da177e4
LT
1742
1743 while (rx_status & OWN) {
1744 unsigned int rx_size;
d269a69f 1745 unsigned int data_size;
1da177e4 1746
7380a78a
VA
1747 if (--rx_work_limit < 0)
1748 break;
1749
d269a69f
DV
1750 data_size = rx_status & DSIZE;
1751 rx_size = data_size - CRC_SIZE;
1752
1753#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
25985edc 1754 /* ``TOOLONG'' flag means jumbo packet received. */
d269a69f
DV
1755 if ((rx_status & TOOLONG) && data_size <= MAX_FRAME_SIZE)
1756 rx_status &= (~ ((unsigned int)TOOLONG));
1757#endif
1da177e4
LT
1758
1759 if (rx_status & (ABORT|OVERRUN|TOOLONG|RUNT|RXISERR|CRCERR|FAERR)) {
1760 /* corrupted packet received */
1761 if (netif_msg_rx_err(sis_priv))
1762 printk(KERN_DEBUG "%s: Corrupted packet "
d269a69f
DV
1763 "received, buffer status = 0x%8.8x/%d.\n",
1764 net_dev->name, rx_status, data_size);
09f75cd7 1765 net_dev->stats.rx_errors++;
1da177e4 1766 if (rx_status & OVERRUN)
09f75cd7 1767 net_dev->stats.rx_over_errors++;
1da177e4 1768 if (rx_status & (TOOLONG|RUNT))
09f75cd7 1769 net_dev->stats.rx_length_errors++;
1da177e4 1770 if (rx_status & (RXISERR | FAERR))
09f75cd7 1771 net_dev->stats.rx_frame_errors++;
6aa20a22 1772 if (rx_status & CRCERR)
09f75cd7 1773 net_dev->stats.rx_crc_errors++;
1da177e4
LT
1774 /* reset buffer descriptor state */
1775 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1776 } else {
1777 struct sk_buff * skb;
dc5a1449 1778 struct sk_buff * rx_skb;
1da177e4 1779
b748d9e3
NH
1780 pci_unmap_single(sis_priv->pci_dev,
1781 sis_priv->rx_ring[entry].bufptr, RX_BUF_SIZE,
1782 PCI_DMA_FROMDEVICE);
1783
af901ca1 1784 /* refill the Rx buffer, what if there is not enough
b748d9e3 1785 * memory for new socket buffer ?? */
dae2e9f4 1786 if ((skb = netdev_alloc_skb(net_dev, RX_BUF_SIZE)) == NULL) {
b748d9e3
NH
1787 /*
1788 * Not enough memory to refill the buffer
1789 * so we need to recycle the old one so
1790 * as to avoid creating a memory hole
1791 * in the rx ring
1792 */
1793 skb = sis_priv->rx_skbuff[entry];
09f75cd7 1794 net_dev->stats.rx_dropped++;
b748d9e3 1795 goto refill_rx_ring;
7d2e3cb7 1796 }
b748d9e3 1797
1da177e4 1798 /* This situation should never happen, but due to
af901ca1 1799 some unknown bugs, it is possible that
1da177e4
LT
1800 we are working on NULL sk_buff :-( */
1801 if (sis_priv->rx_skbuff[entry] == NULL) {
1802 if (netif_msg_rx_err(sis_priv))
6aa20a22 1803 printk(KERN_WARNING "%s: NULL pointer "
7380a78a
VA
1804 "encountered in Rx ring\n"
1805 "cur_rx:%4.4d, dirty_rx:%4.4d\n",
1806 net_dev->name, sis_priv->cur_rx,
1807 sis_priv->dirty_rx);
bf1f9ae0 1808 dev_kfree_skb(skb);
1da177e4
LT
1809 break;
1810 }
1811
1da177e4 1812 /* give the socket buffer to upper layers */
dc5a1449
NH
1813 rx_skb = sis_priv->rx_skbuff[entry];
1814 skb_put(rx_skb, rx_size);
1815 rx_skb->protocol = eth_type_trans(rx_skb, net_dev);
1816 netif_rx(rx_skb);
1da177e4
LT
1817
1818 /* some network statistics */
1819 if ((rx_status & BCAST) == MCAST)
09f75cd7 1820 net_dev->stats.multicast++;
09f75cd7
JG
1821 net_dev->stats.rx_bytes += rx_size;
1822 net_dev->stats.rx_packets++;
b748d9e3
NH
1823 sis_priv->dirty_rx++;
1824refill_rx_ring:
1da177e4
LT
1825 sis_priv->rx_skbuff[entry] = skb;
1826 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1e8edc2a 1827 sis_priv->rx_ring[entry].bufptr =
6aa20a22 1828 pci_map_single(sis_priv->pci_dev, skb->data,
1da177e4 1829 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1e8edc2a
DK
1830 if (unlikely(pci_dma_mapping_error(sis_priv->pci_dev,
1831 sis_priv->rx_ring[entry].bufptr))) {
1832 dev_kfree_skb_irq(skb);
1833 sis_priv->rx_skbuff[entry] = NULL;
1834 break;
1835 }
1da177e4
LT
1836 }
1837 sis_priv->cur_rx++;
1838 entry = sis_priv->cur_rx % NUM_RX_DESC;
1839 rx_status = sis_priv->rx_ring[entry].cmdsts;
1840 } // while
1841
1842 /* refill the Rx buffer, what if the rate of refilling is slower
1843 * than consuming ?? */
7380a78a 1844 for (; sis_priv->cur_rx != sis_priv->dirty_rx; sis_priv->dirty_rx++) {
1da177e4
LT
1845 struct sk_buff *skb;
1846
1847 entry = sis_priv->dirty_rx % NUM_RX_DESC;
1848
1849 if (sis_priv->rx_skbuff[entry] == NULL) {
720a43ef
JP
1850 skb = netdev_alloc_skb(net_dev, RX_BUF_SIZE);
1851 if (skb == NULL) {
1da177e4
LT
1852 /* not enough memory for skbuff, this makes a
1853 * "hole" on the buffer ring, it is not clear
1854 * how the hardware will react to this kind
1855 * of degenerated buffer */
09f75cd7 1856 net_dev->stats.rx_dropped++;
1da177e4
LT
1857 break;
1858 }
1da177e4
LT
1859 sis_priv->rx_skbuff[entry] = skb;
1860 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1e8edc2a 1861 sis_priv->rx_ring[entry].bufptr =
689be439 1862 pci_map_single(sis_priv->pci_dev, skb->data,
1da177e4 1863 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1e8edc2a
DK
1864 if (unlikely(pci_dma_mapping_error(sis_priv->pci_dev,
1865 sis_priv->rx_ring[entry].bufptr))) {
1866 dev_kfree_skb_irq(skb);
1867 sis_priv->rx_skbuff[entry] = NULL;
1868 break;
1869 }
1da177e4
LT
1870 }
1871 }
1872 /* re-enable the potentially idle receive state matchine */
57d6d456 1873 sw32(cr , RxENA | sr32(cr));
1da177e4
LT
1874
1875 return 0;
1876}
1877
1878/**
1879 * sis900_finish_xmit - finish up transmission of packets
1880 * @net_dev: the net device to be transmitted on
1881 *
6aa20a22 1882 * Check for error condition and free socket buffer etc
1da177e4 1883 * schedule for more transmission as needed
0b28002f 1884 * Note: This function is called by interrupt handler,
1da177e4
LT
1885 * don't do "too much" work here
1886 */
1887
1888static void sis900_finish_xmit (struct net_device *net_dev)
1889{
8f15ea42 1890 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1891
1892 for (; sis_priv->dirty_tx != sis_priv->cur_tx; sis_priv->dirty_tx++) {
1893 struct sk_buff *skb;
1894 unsigned int entry;
1895 u32 tx_status;
1896
1897 entry = sis_priv->dirty_tx % NUM_TX_DESC;
1898 tx_status = sis_priv->tx_ring[entry].cmdsts;
1899
1900 if (tx_status & OWN) {
1901 /* The packet is not transmitted yet (owned by hardware) !
1902 * Note: the interrupt is generated only when Tx Machine
1903 * is idle, so this is an almost impossible case */
1904 break;
1905 }
1906
1907 if (tx_status & (ABORT | UNDERRUN | OWCOLL)) {
1908 /* packet unsuccessfully transmitted */
1909 if (netif_msg_tx_err(sis_priv))
1910 printk(KERN_DEBUG "%s: Transmit "
1911 "error, Tx status %8.8x.\n",
1912 net_dev->name, tx_status);
09f75cd7 1913 net_dev->stats.tx_errors++;
1da177e4 1914 if (tx_status & UNDERRUN)
09f75cd7 1915 net_dev->stats.tx_fifo_errors++;
1da177e4 1916 if (tx_status & ABORT)
09f75cd7 1917 net_dev->stats.tx_aborted_errors++;
1da177e4 1918 if (tx_status & NOCARRIER)
09f75cd7 1919 net_dev->stats.tx_carrier_errors++;
1da177e4 1920 if (tx_status & OWCOLL)
09f75cd7 1921 net_dev->stats.tx_window_errors++;
1da177e4
LT
1922 } else {
1923 /* packet successfully transmitted */
09f75cd7
JG
1924 net_dev->stats.collisions += (tx_status & COLCNT) >> 16;
1925 net_dev->stats.tx_bytes += tx_status & DSIZE;
1926 net_dev->stats.tx_packets++;
1da177e4
LT
1927 }
1928 /* Free the original skb. */
1929 skb = sis_priv->tx_skbuff[entry];
6aa20a22 1930 pci_unmap_single(sis_priv->pci_dev,
1da177e4
LT
1931 sis_priv->tx_ring[entry].bufptr, skb->len,
1932 PCI_DMA_TODEVICE);
1933 dev_kfree_skb_irq(skb);
1934 sis_priv->tx_skbuff[entry] = NULL;
1935 sis_priv->tx_ring[entry].bufptr = 0;
1936 sis_priv->tx_ring[entry].cmdsts = 0;
1937 }
1938
1939 if (sis_priv->tx_full && netif_queue_stopped(net_dev) &&
1940 sis_priv->cur_tx - sis_priv->dirty_tx < NUM_TX_DESC - 4) {
1941 /* The ring is no longer full, clear tx_full and schedule
1942 * more transmission by netif_wake_queue(net_dev) */
1943 sis_priv->tx_full = 0;
1944 netif_wake_queue (net_dev);
1945 }
1946}
1947
1948/**
6aa20a22 1949 * sis900_close - close sis900 device
1da177e4
LT
1950 * @net_dev: the net device to be closed
1951 *
6aa20a22 1952 * Disable interrupts, stop the Tx and Rx Status Machine
1da177e4
LT
1953 * free Tx and RX socket buffer
1954 */
1955
1956static int sis900_close(struct net_device *net_dev)
1957{
8f15ea42 1958 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456
FR
1959 struct pci_dev *pdev = sis_priv->pci_dev;
1960 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
1961 struct sk_buff *skb;
1962 int i;
1963
1964 netif_stop_queue(net_dev);
1965
1966 /* Disable interrupts by clearing the interrupt mask. */
57d6d456
FR
1967 sw32(imr, 0x0000);
1968 sw32(ier, 0x0000);
1da177e4
LT
1969
1970 /* Stop the chip's Tx and Rx Status Machine */
57d6d456 1971 sw32(cr, RxDIS | TxDIS | sr32(cr));
1da177e4
LT
1972
1973 del_timer(&sis_priv->timer);
1974
57d6d456 1975 free_irq(pdev->irq, net_dev);
1da177e4
LT
1976
1977 /* Free Tx and RX skbuff */
1978 for (i = 0; i < NUM_RX_DESC; i++) {
1979 skb = sis_priv->rx_skbuff[i];
1980 if (skb) {
57d6d456
FR
1981 pci_unmap_single(pdev, sis_priv->rx_ring[i].bufptr,
1982 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1da177e4
LT
1983 dev_kfree_skb(skb);
1984 sis_priv->rx_skbuff[i] = NULL;
1985 }
1986 }
1987 for (i = 0; i < NUM_TX_DESC; i++) {
1988 skb = sis_priv->tx_skbuff[i];
1989 if (skb) {
57d6d456
FR
1990 pci_unmap_single(pdev, sis_priv->tx_ring[i].bufptr,
1991 skb->len, PCI_DMA_TODEVICE);
1da177e4
LT
1992 dev_kfree_skb(skb);
1993 sis_priv->tx_skbuff[i] = NULL;
1994 }
1995 }
1996
1997 /* Green! Put the chip in low-power mode. */
1998
1999 return 0;
2000}
2001
2002/**
2003 * sis900_get_drvinfo - Return information about driver
2004 * @net_dev: the net device to probe
2005 * @info: container for info returned
2006 *
2007 * Process ethtool command such as "ehtool -i" to show information
2008 */
6aa20a22 2009
1da177e4
LT
2010static void sis900_get_drvinfo(struct net_device *net_dev,
2011 struct ethtool_drvinfo *info)
2012{
8f15ea42 2013 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4 2014
23020ab3
RJ
2015 strlcpy(info->driver, SIS900_MODULE_NAME, sizeof(info->driver));
2016 strlcpy(info->version, SIS900_DRV_VERSION, sizeof(info->version));
2017 strlcpy(info->bus_info, pci_name(sis_priv->pci_dev),
2018 sizeof(info->bus_info));
1da177e4
LT
2019}
2020
2021static u32 sis900_get_msglevel(struct net_device *net_dev)
2022{
8f15ea42 2023 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
2024 return sis_priv->msg_enable;
2025}
6aa20a22 2026
1da177e4
LT
2027static void sis900_set_msglevel(struct net_device *net_dev, u32 value)
2028{
8f15ea42 2029 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
2030 sis_priv->msg_enable = value;
2031}
2032
da369b01
DV
2033static u32 sis900_get_link(struct net_device *net_dev)
2034{
8f15ea42 2035 struct sis900_private *sis_priv = netdev_priv(net_dev);
da369b01
DV
2036 return mii_link_ok(&sis_priv->mii_info);
2037}
2038
2039static int sis900_get_settings(struct net_device *net_dev,
2040 struct ethtool_cmd *cmd)
2041{
8f15ea42 2042 struct sis900_private *sis_priv = netdev_priv(net_dev);
da369b01
DV
2043 spin_lock_irq(&sis_priv->lock);
2044 mii_ethtool_gset(&sis_priv->mii_info, cmd);
2045 spin_unlock_irq(&sis_priv->lock);
2046 return 0;
2047}
2048
2049static int sis900_set_settings(struct net_device *net_dev,
2050 struct ethtool_cmd *cmd)
2051{
8f15ea42 2052 struct sis900_private *sis_priv = netdev_priv(net_dev);
da369b01
DV
2053 int rt;
2054 spin_lock_irq(&sis_priv->lock);
2055 rt = mii_ethtool_sset(&sis_priv->mii_info, cmd);
2056 spin_unlock_irq(&sis_priv->lock);
2057 return rt;
2058}
2059
2060static int sis900_nway_reset(struct net_device *net_dev)
2061{
8f15ea42 2062 struct sis900_private *sis_priv = netdev_priv(net_dev);
da369b01
DV
2063 return mii_nway_restart(&sis_priv->mii_info);
2064}
2065
ea37ccea
DV
2066/**
2067 * sis900_set_wol - Set up Wake on Lan registers
2068 * @net_dev: the net device to probe
2069 * @wol: container for info passed to the driver
2070 *
2071 * Process ethtool command "wol" to setup wake on lan features.
2072 * SiS900 supports sending WoL events if a correct packet is received,
2073 * but there is no simple way to filter them to only a subset (broadcast,
2074 * multicast, unicast or arp).
2075 */
6aa20a22 2076
ea37ccea
DV
2077static int sis900_set_wol(struct net_device *net_dev, struct ethtool_wolinfo *wol)
2078{
8f15ea42 2079 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456 2080 void __iomem *ioaddr = sis_priv->ioaddr;
ea37ccea
DV
2081 u32 cfgpmcsr = 0, pmctrl_bits = 0;
2082
2083 if (wol->wolopts == 0) {
2084 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
7bef4b39 2085 cfgpmcsr &= ~PME_EN;
ea37ccea 2086 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
57d6d456 2087 sw32(pmctrl, pmctrl_bits);
ea37ccea
DV
2088 if (netif_msg_wol(sis_priv))
2089 printk(KERN_DEBUG "%s: Wake on LAN disabled\n", net_dev->name);
2090 return 0;
2091 }
2092
2093 if (wol->wolopts & (WAKE_MAGICSECURE | WAKE_UCAST | WAKE_MCAST
2094 | WAKE_BCAST | WAKE_ARP))
2095 return -EINVAL;
2096
2097 if (wol->wolopts & WAKE_MAGIC)
2098 pmctrl_bits |= MAGICPKT;
2099 if (wol->wolopts & WAKE_PHY)
2100 pmctrl_bits |= LINKON;
6aa20a22 2101
57d6d456 2102 sw32(pmctrl, pmctrl_bits);
ea37ccea
DV
2103
2104 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
2105 cfgpmcsr |= PME_EN;
2106 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
2107 if (netif_msg_wol(sis_priv))
2108 printk(KERN_DEBUG "%s: Wake on LAN enabled\n", net_dev->name);
2109
2110 return 0;
2111}
2112
2113static void sis900_get_wol(struct net_device *net_dev, struct ethtool_wolinfo *wol)
2114{
57d6d456
FR
2115 struct sis900_private *sp = netdev_priv(net_dev);
2116 void __iomem *ioaddr = sp->ioaddr;
ea37ccea
DV
2117 u32 pmctrl_bits;
2118
57d6d456 2119 pmctrl_bits = sr32(pmctrl);
ea37ccea
DV
2120 if (pmctrl_bits & MAGICPKT)
2121 wol->wolopts |= WAKE_MAGIC;
2122 if (pmctrl_bits & LINKON)
2123 wol->wolopts |= WAKE_PHY;
2124
2125 wol->supported = (WAKE_PHY | WAKE_MAGIC);
2126}
2127
7282d491 2128static const struct ethtool_ops sis900_ethtool_ops = {
1da177e4
LT
2129 .get_drvinfo = sis900_get_drvinfo,
2130 .get_msglevel = sis900_get_msglevel,
2131 .set_msglevel = sis900_set_msglevel,
da369b01
DV
2132 .get_link = sis900_get_link,
2133 .get_settings = sis900_get_settings,
2134 .set_settings = sis900_set_settings,
2135 .nway_reset = sis900_nway_reset,
ea37ccea
DV
2136 .get_wol = sis900_get_wol,
2137 .set_wol = sis900_set_wol
1da177e4
LT
2138};
2139
2140/**
6aa20a22 2141 * mii_ioctl - process MII i/o control command
1da177e4
LT
2142 * @net_dev: the net device to command for
2143 * @rq: parameter for command
2144 * @cmd: the i/o command
2145 *
2146 * Process MII command like read/write MII register
2147 */
2148
2149static int mii_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
2150{
8f15ea42 2151 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
2152 struct mii_ioctl_data *data = if_mii(rq);
2153
2154 switch(cmd) {
2155 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2156 data->phy_id = sis_priv->mii->phy_addr;
2157 /* Fall Through */
2158
2159 case SIOCGMIIREG: /* Read MII PHY register. */
2160 data->val_out = mdio_read(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
2161 return 0;
2162
2163 case SIOCSMIIREG: /* Write MII PHY register. */
1da177e4
LT
2164 mdio_write(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
2165 return 0;
2166 default:
2167 return -EOPNOTSUPP;
2168 }
2169}
2170
1da177e4 2171/**
6aa20a22 2172 * sis900_set_config - Set media type by net_device.set_config
1da177e4
LT
2173 * @dev: the net device for media type change
2174 * @map: ifmap passed by ifconfig
2175 *
2176 * Set media type to 10baseT, 100baseT or 0(for auto) by ifconfig
2177 * we support only port changes. All other runtime configuration
2178 * changes will be ignored
2179 */
2180
2181static int sis900_set_config(struct net_device *dev, struct ifmap *map)
6aa20a22 2182{
8f15ea42 2183 struct sis900_private *sis_priv = netdev_priv(dev);
1da177e4 2184 struct mii_phy *mii_phy = sis_priv->mii;
6aa20a22 2185
1da177e4
LT
2186 u16 status;
2187
2188 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
2189 /* we switch on the ifmap->port field. I couldn't find anything
2190 * like a definition or standard for the values of that field.
2191 * I think the meaning of those values is device specific. But
2192 * since I would like to change the media type via the ifconfig
6aa20a22 2193 * command I use the definition from linux/netdevice.h
1da177e4
LT
2194 * (which seems to be different from the ifport(pcmcia) definition) */
2195 switch(map->port){
6aa20a22 2196 case IF_PORT_UNKNOWN: /* use auto here */
1da177e4
LT
2197 dev->if_port = map->port;
2198 /* we are going to change the media type, so the Link
2199 * will be temporary down and we need to reflect that
2200 * here. When the Link comes up again, it will be
2201 * sensed by the sis_timer procedure, which also does
2202 * all the rest for us */
2203 netif_carrier_off(dev);
6aa20a22 2204
1da177e4
LT
2205 /* read current state */
2206 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
6aa20a22 2207
1da177e4
LT
2208 /* enable auto negotiation and reset the negotioation
2209 * (I don't really know what the auto negatiotiation
2210 * reset really means, but it sounds for me right to
2211 * do one here) */
2212 mdio_write(dev, mii_phy->phy_addr,
2213 MII_CONTROL, status | MII_CNTL_AUTO | MII_CNTL_RST_AUTO);
2214
2215 break;
6aa20a22
JG
2216
2217 case IF_PORT_10BASET: /* 10BaseT */
1da177e4 2218 dev->if_port = map->port;
6aa20a22 2219
1da177e4
LT
2220 /* we are going to change the media type, so the Link
2221 * will be temporary down and we need to reflect that
2222 * here. When the Link comes up again, it will be
2223 * sensed by the sis_timer procedure, which also does
2224 * all the rest for us */
2225 netif_carrier_off(dev);
6aa20a22 2226
1da177e4
LT
2227 /* set Speed to 10Mbps */
2228 /* read current state */
2229 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
6aa20a22 2230
1da177e4
LT
2231 /* disable auto negotiation and force 10MBit mode*/
2232 mdio_write(dev, mii_phy->phy_addr,
2233 MII_CONTROL, status & ~(MII_CNTL_SPEED |
2234 MII_CNTL_AUTO));
2235 break;
6aa20a22 2236
1da177e4 2237 case IF_PORT_100BASET: /* 100BaseT */
6aa20a22 2238 case IF_PORT_100BASETX: /* 100BaseTx */
1da177e4 2239 dev->if_port = map->port;
6aa20a22 2240
1da177e4
LT
2241 /* we are going to change the media type, so the Link
2242 * will be temporary down and we need to reflect that
2243 * here. When the Link comes up again, it will be
2244 * sensed by the sis_timer procedure, which also does
2245 * all the rest for us */
2246 netif_carrier_off(dev);
6aa20a22 2247
1da177e4
LT
2248 /* set Speed to 100Mbps */
2249 /* disable auto negotiation and enable 100MBit Mode */
2250 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
2251 mdio_write(dev, mii_phy->phy_addr,
2252 MII_CONTROL, (status & ~MII_CNTL_SPEED) |
2253 MII_CNTL_SPEED);
6aa20a22 2254
1da177e4 2255 break;
6aa20a22 2256
1da177e4
LT
2257 case IF_PORT_10BASE2: /* 10Base2 */
2258 case IF_PORT_AUI: /* AUI */
2259 case IF_PORT_100BASEFX: /* 100BaseFx */
2260 /* These Modes are not supported (are they?)*/
2261 return -EOPNOTSUPP;
6aa20a22 2262
1da177e4
LT
2263 default:
2264 return -EINVAL;
2265 }
2266 }
2267 return 0;
2268}
2269
2270/**
6aa20a22 2271 * sis900_mcast_bitnr - compute hashtable index
1da177e4
LT
2272 * @addr: multicast address
2273 * @revision: revision id of chip
2274 *
2275 * SiS 900 uses the most sigificant 7 bits to index a 128 bits multicast
2276 * hash table, which makes this function a little bit different from other drivers
2277 * SiS 900 B0 & 635 M/B uses the most significat 8 bits to index 256 bits
6aa20a22 2278 * multicast hash table.
1da177e4
LT
2279 */
2280
2281static inline u16 sis900_mcast_bitnr(u8 *addr, u8 revision)
2282{
2283
2284 u32 crc = ether_crc(6, addr);
2285
2286 /* leave 8 or 7 most siginifant bits */
2287 if ((revision >= SIS635A_900_REV) || (revision == SIS900B_900_REV))
807540ba 2288 return (int)(crc >> 24);
1da177e4 2289 else
807540ba 2290 return (int)(crc >> 25);
1da177e4
LT
2291}
2292
2293/**
6aa20a22 2294 * set_rx_mode - Set SiS900 receive mode
1da177e4
LT
2295 * @net_dev: the net device to be set
2296 *
2297 * Set SiS900 receive mode for promiscuous, multicast, or broadcast mode.
2298 * And set the appropriate multicast filter.
2299 * Multicast hash table changes from 128 to 256 bits for 635M/B & 900B0.
2300 */
2301
2302static void set_rx_mode(struct net_device *net_dev)
2303{
8f15ea42 2304 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456 2305 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
2306 u16 mc_filter[16] = {0}; /* 256/128 bits multicast hash table */
2307 int i, table_entries;
2308 u32 rx_mode;
2309
7f927fcc 2310 /* 635 Hash Table entries = 256(2^16) */
1da177e4
LT
2311 if((sis_priv->chipset_rev >= SIS635A_900_REV) ||
2312 (sis_priv->chipset_rev == SIS900B_900_REV))
2313 table_entries = 16;
2314 else
2315 table_entries = 8;
2316
2317 if (net_dev->flags & IFF_PROMISC) {
2318 /* Accept any kinds of packets */
2319 rx_mode = RFPromiscuous;
2320 for (i = 0; i < table_entries; i++)
2321 mc_filter[i] = 0xffff;
4cd24eaf 2322 } else if ((netdev_mc_count(net_dev) > multicast_filter_limit) ||
1da177e4
LT
2323 (net_dev->flags & IFF_ALLMULTI)) {
2324 /* too many multicast addresses or accept all multicast packet */
2325 rx_mode = RFAAB | RFAAM;
2326 for (i = 0; i < table_entries; i++)
2327 mc_filter[i] = 0xffff;
2328 } else {
2329 /* Accept Broadcast packet, destination address matchs our
2330 * MAC address, use Receive Filter to reject unwanted MCAST
2331 * packets */
22bedad3 2332 struct netdev_hw_addr *ha;
1da177e4 2333 rx_mode = RFAAB;
5508590c 2334
22bedad3
JP
2335 netdev_for_each_mc_addr(ha, net_dev) {
2336 unsigned int bit_nr;
2337
2338 bit_nr = sis900_mcast_bitnr(ha->addr,
2339 sis_priv->chipset_rev);
1da177e4
LT
2340 mc_filter[bit_nr >> 4] |= (1 << (bit_nr & 0xf));
2341 }
2342 }
2343
2344 /* update Multicast Hash Table in Receive Filter */
2345 for (i = 0; i < table_entries; i++) {
2346 /* why plus 0x04 ??, That makes the correct value for hash table. */
57d6d456
FR
2347 sw32(rfcr, (u32)(0x00000004 + i) << RFADDR_shift);
2348 sw32(rfdr, mc_filter[i]);
1da177e4
LT
2349 }
2350
57d6d456 2351 sw32(rfcr, RFEN | rx_mode);
1da177e4
LT
2352
2353 /* sis900 is capable of looping back packets at MAC level for
2354 * debugging purpose */
2355 if (net_dev->flags & IFF_LOOPBACK) {
2356 u32 cr_saved;
2357 /* We must disable Tx/Rx before setting loopback mode */
57d6d456
FR
2358 cr_saved = sr32(cr);
2359 sw32(cr, cr_saved | TxDIS | RxDIS);
1da177e4 2360 /* enable loopback */
57d6d456
FR
2361 sw32(txcfg, sr32(txcfg) | TxMLB);
2362 sw32(rxcfg, sr32(rxcfg) | RxATX);
1da177e4 2363 /* restore cr */
57d6d456 2364 sw32(cr, cr_saved);
1da177e4 2365 }
1da177e4
LT
2366}
2367
2368/**
6aa20a22 2369 * sis900_reset - Reset sis900 MAC
1da177e4
LT
2370 * @net_dev: the net device to reset
2371 *
2372 * reset sis900 MAC and wait until finished
2373 * reset through command register
2374 * change backoff algorithm for 900B0 & 635 M/B
2375 */
2376
2377static void sis900_reset(struct net_device *net_dev)
2378{
8f15ea42 2379 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456 2380 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4 2381 u32 status = TxRCMP | RxRCMP;
57d6d456 2382 int i;
1da177e4 2383
57d6d456
FR
2384 sw32(ier, 0);
2385 sw32(imr, 0);
2386 sw32(rfcr, 0);
1da177e4 2387
57d6d456 2388 sw32(cr, RxRESET | TxRESET | RESET | sr32(cr));
6aa20a22 2389
1da177e4 2390 /* Check that the chip has finished the reset. */
57d6d456
FR
2391 for (i = 0; status && (i < 1000); i++)
2392 status ^= sr32(isr) & status;
1da177e4 2393
57d6d456
FR
2394 if (sis_priv->chipset_rev >= SIS635A_900_REV ||
2395 sis_priv->chipset_rev == SIS900B_900_REV)
2396 sw32(cfg, PESEL | RND_CNT);
1da177e4 2397 else
57d6d456 2398 sw32(cfg, PESEL);
1da177e4
LT
2399}
2400
2401/**
6aa20a22 2402 * sis900_remove - Remove sis900 device
1da177e4
LT
2403 * @pci_dev: the pci device to be removed
2404 *
2405 * remove and release SiS900 net device
2406 */
2407
369e1231 2408static void sis900_remove(struct pci_dev *pci_dev)
1da177e4
LT
2409{
2410 struct net_device *net_dev = pci_get_drvdata(pci_dev);
8f15ea42 2411 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456
FR
2412
2413 unregister_netdev(net_dev);
1da177e4
LT
2414
2415 while (sis_priv->first_mii) {
57d6d456
FR
2416 struct mii_phy *phy = sis_priv->first_mii;
2417
1da177e4
LT
2418 sis_priv->first_mii = phy->next;
2419 kfree(phy);
2420 }
2421
2422 pci_free_consistent(pci_dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
2423 sis_priv->rx_ring_dma);
2424 pci_free_consistent(pci_dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
2425 sis_priv->tx_ring_dma);
57d6d456 2426 pci_iounmap(pci_dev, sis_priv->ioaddr);
1da177e4
LT
2427 free_netdev(net_dev);
2428 pci_release_regions(pci_dev);
1da177e4
LT
2429}
2430
2431#ifdef CONFIG_PM
2432
2433static int sis900_suspend(struct pci_dev *pci_dev, pm_message_t state)
2434{
2435 struct net_device *net_dev = pci_get_drvdata(pci_dev);
57d6d456
FR
2436 struct sis900_private *sis_priv = netdev_priv(net_dev);
2437 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
2438
2439 if(!netif_running(net_dev))
2440 return 0;
2441
2442 netif_stop_queue(net_dev);
2443 netif_device_detach(net_dev);
2444
2445 /* Stop the chip's Tx and Rx Status Machine */
57d6d456 2446 sw32(cr, RxDIS | TxDIS | sr32(cr));
1da177e4
LT
2447
2448 pci_set_power_state(pci_dev, PCI_D3hot);
2449 pci_save_state(pci_dev);
2450
2451 return 0;
2452}
2453
2454static int sis900_resume(struct pci_dev *pci_dev)
2455{
2456 struct net_device *net_dev = pci_get_drvdata(pci_dev);
8f15ea42 2457 struct sis900_private *sis_priv = netdev_priv(net_dev);
57d6d456 2458 void __iomem *ioaddr = sis_priv->ioaddr;
1da177e4
LT
2459
2460 if(!netif_running(net_dev))
2461 return 0;
2462 pci_restore_state(pci_dev);
2463 pci_set_power_state(pci_dev, PCI_D0);
2464
2465 sis900_init_rxfilter(net_dev);
2466
2467 sis900_init_tx_ring(net_dev);
2468 sis900_init_rx_ring(net_dev);
2469
2470 set_rx_mode(net_dev);
2471
2472 netif_device_attach(net_dev);
2473 netif_start_queue(net_dev);
2474
2475 /* Workaround for EDB */
8495c0da 2476 sis900_set_mode(sis_priv, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
1da177e4
LT
2477
2478 /* Enable all known interrupts by setting the interrupt mask. */
57d6d456
FR
2479 sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxIDLE);
2480 sw32(cr, RxENA | sr32(cr));
2481 sw32(ier, IE);
1da177e4
LT
2482
2483 sis900_check_mode(net_dev, sis_priv->mii);
2484
2485 return 0;
2486}
2487#endif /* CONFIG_PM */
2488
2489static struct pci_driver sis900_pci_driver = {
2490 .name = SIS900_MODULE_NAME,
2491 .id_table = sis900_pci_tbl,
2492 .probe = sis900_probe,
369e1231 2493 .remove = sis900_remove,
1da177e4
LT
2494#ifdef CONFIG_PM
2495 .suspend = sis900_suspend,
2496 .resume = sis900_resume,
2497#endif /* CONFIG_PM */
2498};
2499
2500static int __init sis900_init_module(void)
2501{
2502/* when a module, this is printed whether or not devices are found in probe */
2503#ifdef MODULE
2504 printk(version);
2505#endif
2506
29917620 2507 return pci_register_driver(&sis900_pci_driver);
1da177e4
LT
2508}
2509
2510static void __exit sis900_cleanup_module(void)
2511{
2512 pci_unregister_driver(&sis900_pci_driver);
2513}
2514
2515module_init(sis900_init_module);
2516module_exit(sis900_cleanup_module);
2517
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