projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 47dd7a54 GC |
1 | config STMMAC_ETH |
| 2 | tristate "STMicroelectronics 10/100/1000 Ethernet driver" | |
| 7ac6653a | 3 | depends on HAS_IOMEM |
| aaba215c | 4 | select NET_CORE |
| 47dd7a54 GC |
5 | select MII |
| 6 | select PHYLIB | |
| 7ba8a9b4 | 7 | select CRC32 |
| 7ac6653a | 8 | ---help--- |
| 7187c1ad | 9 | This is the driver for the Ethernet IPs are built around a |
| ac75791a | 10 | Synopsys IP Core and only tested on the STMicroelectronics |
| 7187c1ad | 11 | platforms. |
| 47dd7a54 GC |
12 | |
| 13 | if STMMAC_ETH | |
| 14 | ||
| 7ac29055 GC |
15 | config STMMAC_DEBUG_FS |
| 16 | bool "Enable monitoring via sysFS " | |
| 17 | default n | |
| 18 | depends on STMMAC_ETH && DEBUG_FS | |
| 19 | -- help | |
| e7434821 GC |
20 | The stmmac entry in /sys reports DMA TX/RX rings |
| 21 | or (if supported) the HW cap register. | |
| 7ac29055 | 22 | |
| 47dd7a54 GC |
23 | config STMMAC_DA |
| 24 | bool "STMMAC DMA arbitration scheme" | |
| 25 | default n | |
| 7ac6653a | 26 | ---help--- |
| 47dd7a54 GC |
27 | Selecting this option, rx has priority over Tx (only for Giga |
| 28 | Ethernet device). | |
| 29 | By default, the DMA arbitration scheme is based on Round-robin | |
| 30 | (rx:tx priority is 1:1). | |
| 31 | ||
| 32 | config STMMAC_DUAL_MAC | |
| 33 | bool "STMMAC: dual mac support (EXPERIMENTAL)" | |
| 34 | default n | |
| 35 | depends on EXPERIMENTAL && STMMAC_ETH && !STMMAC_TIMER | |
| 7ac6653a | 36 | ---help--- |
| 47dd7a54 GC |
37 | Some ST SoCs (for example the stx7141 and stx7200c2) have two |
| 38 | Ethernet Controllers. This option turns on the second Ethernet | |
| 39 | device on this kind of platforms. | |
| 40 | ||
| 41 | config STMMAC_TIMER | |
| 42 | bool "STMMAC Timer optimisation" | |
| 43 | default n | |
| 250ad8f5 | 44 | depends on RTC_HCTOSYS_DEVICE |
| 7ac6653a | 45 | ---help--- |
| 47dd7a54 | 46 | Use an external timer for mitigating the number of network |
| 7187c1ad GC |
47 | interrupts. Currently, for SH architectures, it is possible |
| 48 | to use the TMU channel 2 and the SH-RTC device. | |
| 47dd7a54 GC |
49 | |
| 50 | choice | |
| 51 | prompt "Select Timer device" | |
| 52 | depends on STMMAC_TIMER | |
| 53 | ||
| 54 | config STMMAC_TMU_TIMER | |
| 55 | bool "TMU channel 2" | |
| 56 | depends on CPU_SH4 | |
| 7ac6653a | 57 | ---help--- |
| 47dd7a54 GC |
58 | |
| 59 | config STMMAC_RTC_TIMER | |
| 60 | bool "Real time clock" | |
| 61 | depends on RTC_CLASS | |
| 7ac6653a | 62 | ---help--- |
| 47dd7a54 GC |
63 | |
| 64 | endchoice | |
| 65 | ||
| 286a8372 GC |
66 | choice |
| 67 | prompt "Select the DMA TX/RX descriptor operating modes" | |
| 68 | depends on STMMAC_ETH | |
| 69 | ---help--- | |
| 70 | This driver supports DMA descriptor to operate both in dual buffer | |
| 71 | (RING) and linked-list(CHAINED) mode. In RING mode each descriptor | |
| 72 | points to two data buffer pointers whereas in CHAINED mode they | |
| 73 | points to only one data buffer pointer. | |
| 74 | ||
| 75 | config STMMAC_RING | |
| 76 | bool "Enable Descriptor Ring Mode" | |
| 77 | ||
| 78 | config STMMAC_CHAINED | |
| 79 | bool "Enable Descriptor Chained Mode" | |
| 80 | ||
| 81 | endchoice | |
| 82 | ||
| 83 | ||
| 47dd7a54 | 84 | endif |