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stmmac: add CHAINED descriptor mode support (V4)
[deliverable/linux.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
286a8372 5 Copyright(C) 2007-2011 STMicroelectronics Ltd
47dd7a54
GC		 6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/kernel.h>
34#include <linux/interrupt.h>
47dd7a54
GC		 35#include <linux/etherdevice.h>
36#include <linux/platform_device.h>
37#include <linux/ip.h>
38#include <linux/tcp.h>
39#include <linux/skbuff.h>
40#include <linux/ethtool.h>
41#include <linux/if_ether.h>
42#include <linux/crc32.h>
43#include <linux/mii.h>
01789349 44#include <linux/if.h>
47dd7a54
GC		 45#include <linux/if_vlan.h>
46#include <linux/dma-mapping.h>
5a0e3ad6 47#include <linux/slab.h>
70c71606 48#include <linux/prefetch.h>
7ac29055
GC		 49#ifdef CONFIG_STMMAC_DEBUG_FS
50#include <linux/debugfs.h>
51#include <linux/seq_file.h>
52#endif
286a8372 53#include "stmmac.h"
47dd7a54
GC		 54
55#define STMMAC_RESOURCE_NAME "stmmaceth"
47dd7a54
GC		 56
57#undef STMMAC_DEBUG
58/*#define STMMAC_DEBUG*/
59#ifdef STMMAC_DEBUG
60#define DBG(nlevel, klevel, fmt, args...) \
61 ((void)(netif_msg_##nlevel(priv) && \
62 printk(KERN_##klevel fmt, ## args)))
63#else
64#define DBG(nlevel, klevel, fmt, args...) do { } while (0)
65#endif
66
67#undef STMMAC_RX_DEBUG
68/*#define STMMAC_RX_DEBUG*/
69#ifdef STMMAC_RX_DEBUG
70#define RX_DBG(fmt, args...) printk(fmt, ## args)
71#else
72#define RX_DBG(fmt, args...) do { } while (0)
73#endif
74
75#undef STMMAC_XMIT_DEBUG
76/*#define STMMAC_XMIT_DEBUG*/
77#ifdef STMMAC_TX_DEBUG
78#define TX_DBG(fmt, args...) printk(fmt, ## args)
79#else
80#define TX_DBG(fmt, args...) do { } while (0)
81#endif
82
83#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
84#define JUMBO_LEN 9000
85
86/* Module parameters */
87#define TX_TIMEO 5000 /* default 5 seconds */
88static int watchdog = TX_TIMEO;
89module_param(watchdog, int, S_IRUGO | S_IWUSR);
90MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
91
92static int debug = -1; /* -1: default, 0: no output, 16: all */
93module_param(debug, int, S_IRUGO | S_IWUSR);
94MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
95
96static int phyaddr = -1;
97module_param(phyaddr, int, S_IRUGO);
98MODULE_PARM_DESC(phyaddr, "Physical device address");
99
100#define DMA_TX_SIZE 256
101static int dma_txsize = DMA_TX_SIZE;
102module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
103MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
104
105#define DMA_RX_SIZE 256
106static int dma_rxsize = DMA_RX_SIZE;
107module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
108MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
109
110static int flow_ctrl = FLOW_OFF;
111module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
112MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
113
114static int pause = PAUSE_TIME;
115module_param(pause, int, S_IRUGO | S_IWUSR);
116MODULE_PARM_DESC(pause, "Flow Control Pause Time");
117
118#define TC_DEFAULT 64
119static int tc = TC_DEFAULT;
120module_param(tc, int, S_IRUGO | S_IWUSR);
121MODULE_PARM_DESC(tc, "DMA threshold control value");
122
47dd7a54
GC		 123/* Pay attention to tune this parameter; take care of both
124 * hardware capability and network stabitily/performance impact.
125 * Many tests showed that ~4ms latency seems to be good enough. */
126#ifdef CONFIG_STMMAC_TIMER
127#define DEFAULT_PERIODIC_RATE 256
128static int tmrate = DEFAULT_PERIODIC_RATE;
129module_param(tmrate, int, S_IRUGO | S_IWUSR);
130MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
131#endif
132
133#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
134static int buf_sz = DMA_BUFFER_SIZE;
135module_param(buf_sz, int, S_IRUGO | S_IWUSR);
136MODULE_PARM_DESC(buf_sz, "DMA buffer size");
137
47dd7a54
GC		 138static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
139 NETIF_MSG_LINK | NETIF_MSG_IFUP |
140 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
141
142static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
47dd7a54
GC		 143
144/**
145 * stmmac_verify_args - verify the driver parameters.
146 * Description: it verifies if some wrong parameter is passed to the driver.
147 * Note that wrong parameters are replaced with the default values.
148 */
149static void stmmac_verify_args(void)
150{
151 if (unlikely(watchdog < 0))
152 watchdog = TX_TIMEO;
153 if (unlikely(dma_rxsize < 0))
154 dma_rxsize = DMA_RX_SIZE;
155 if (unlikely(dma_txsize < 0))
156 dma_txsize = DMA_TX_SIZE;
157 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
158 buf_sz = DMA_BUFFER_SIZE;
159 if (unlikely(flow_ctrl > 1))
160 flow_ctrl = FLOW_AUTO;
161 else if (likely(flow_ctrl < 0))
162 flow_ctrl = FLOW_OFF;
163 if (unlikely((pause < 0) || (pause > 0xffff)))
164 pause = PAUSE_TIME;
47dd7a54
GC		 165}
166
167#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
168static void print_pkt(unsigned char *buf, int len)
169{
170 int j;
171 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
172 for (j = 0; j < len; j++) {
173 if ((j % 16) == 0)
174 pr_info("\n %03x:", j);
175 pr_info(" %02x", buf[j]);
176 }
177 pr_info("\n");
47dd7a54
GC		 178}
179#endif
180
181/* minimum number of free TX descriptors required to wake up TX process */
182#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
183
184static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
185{
186 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
187}
188
9dfeb4d9
GC		 189/* On some ST platforms, some HW system configuraton registers have to be
190 * set according to the link speed negotiated.
191 */
192static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
193{
194 struct phy_device *phydev = priv->phydev;
195
196 if (likely(priv->plat->fix_mac_speed))
197 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
198 phydev->speed);
199}
200
47dd7a54
GC		 201/**
202 * stmmac_adjust_link
203 * @dev: net device structure
204 * Description: it adjusts the link parameters.
205 */
206static void stmmac_adjust_link(struct net_device *dev)
207{
208 struct stmmac_priv *priv = netdev_priv(dev);
209 struct phy_device *phydev = priv->phydev;
47dd7a54
GC		 210 unsigned long flags;
211 int new_state = 0;
212 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
213
214 if (phydev == NULL)
215 return;
216
217 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
218 phydev->addr, phydev->link);
219
220 spin_lock_irqsave(&priv->lock, flags);
221 if (phydev->link) {
ad01b7d4 222 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 223
224 /* Now we make sure that we can be in full duplex mode.
225 * If not, we operate in half-duplex mode. */
226 if (phydev->duplex != priv->oldduplex) {
227 new_state = 1;
228 if (!(phydev->duplex))
db98a0b0 229 ctrl &= ~priv->hw->link.duplex;
47dd7a54 230 else
db98a0b0 231 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 232 priv->oldduplex = phydev->duplex;
233 }
234 /* Flow Control operation */
235 if (phydev->pause)
ad01b7d4 236 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
db98a0b0 237 fc, pause_time);
47dd7a54
GC		 238
239 if (phydev->speed != priv->speed) {
240 new_state = 1;
241 switch (phydev->speed) {
242 case 1000:
9dfeb4d9 243 if (likely(priv->plat->has_gmac))
db98a0b0 244 ctrl &= ~priv->hw->link.port;
9dfeb4d9 245 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 246 break;
247 case 100:
248 case 10:
9dfeb4d9 249 if (priv->plat->has_gmac) {
db98a0b0 250 ctrl |= priv->hw->link.port;
47dd7a54 251 if (phydev->speed == SPEED_100) {
db98a0b0 252 ctrl |= priv->hw->link.speed;
47dd7a54 253 } else {
db98a0b0 254 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 255 }
256 } else {
db98a0b0 257 ctrl &= ~priv->hw->link.port;
47dd7a54 258 }
9dfeb4d9 259 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 260 break;
261 default:
262 if (netif_msg_link(priv))
263 pr_warning("%s: Speed (%d) is not 10"
264 " or 100!\n", dev->name, phydev->speed);
265 break;
266 }
267
268 priv->speed = phydev->speed;
269 }
270
ad01b7d4 271 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 272
273 if (!priv->oldlink) {
274 new_state = 1;
275 priv->oldlink = 1;
276 }
277 } else if (priv->oldlink) {
278 new_state = 1;
279 priv->oldlink = 0;
280 priv->speed = 0;
281 priv->oldduplex = -1;
282 }
283
284 if (new_state && netif_msg_link(priv))
285 phy_print_status(phydev);
286
287 spin_unlock_irqrestore(&priv->lock, flags);
288
289 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
290}
291
292/**
293 * stmmac_init_phy - PHY initialization
294 * @dev: net device structure
295 * Description: it initializes the driver's PHY state, and attaches the PHY
296 * to the mac driver.
297 * Return value:
298 * 0 on success
299 */
300static int stmmac_init_phy(struct net_device *dev)
301{
302 struct stmmac_priv *priv = netdev_priv(dev);
303 struct phy_device *phydev;
109cdd66
GC		 304 char phy_id[MII_BUS_ID_SIZE + 3];
305 char bus_id[MII_BUS_ID_SIZE];
79ee1dc3 306 int interface = priv->plat->interface;
47dd7a54
GC		 307 priv->oldlink = 0;
308 priv->speed = 0;
309 priv->oldduplex = -1;
310
9dfeb4d9 311 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
109cdd66 312 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
36bcfe7d 313 priv->plat->phy_addr);
47dd7a54
GC		 314 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
315
79ee1dc3 316 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface);
47dd7a54
GC		 317
318 if (IS_ERR(phydev)) {
319 pr_err("%s: Could not attach to PHY\n", dev->name);
320 return PTR_ERR(phydev);
321 }
322
79ee1dc3
SK		 323 /* Stop Advertising 1000BASE Capability if interface is not GMII */
324 if ((interface) && ((interface == PHY_INTERFACE_MODE_MII) ||
325 (interface == PHY_INTERFACE_MODE_RMII))) {
326 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
327 SUPPORTED_Asym_Pause);
328 priv->phydev->advertising = priv->phydev->supported;
329 }
330
47dd7a54
GC		 331 /*
332 * Broken HW is sometimes missing the pull-up resistor on the
333 * MDIO line, which results in reads to non-existent devices returning
334 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
335 * device as well.
336 * Note: phydev->phy_id is the result of reading the UID PHY registers.
337 */
338 if (phydev->phy_id == 0) {
339 phy_disconnect(phydev);
340 return -ENODEV;
341 }
342 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
36bcfe7d 343 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
47dd7a54
GC		 344
345 priv->phydev = phydev;
346
347 return 0;
348}
349
19449bfc 350static inline void stmmac_enable_mac(void __iomem *ioaddr)
47dd7a54
GC		 351{
352 u32 value = readl(ioaddr + MAC_CTRL_REG);
47dd7a54 353
19449bfc 354 value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
47dd7a54
GC		 355 writel(value, ioaddr + MAC_CTRL_REG);
356}
357
19449bfc 358static inline void stmmac_disable_mac(void __iomem *ioaddr)
47dd7a54
GC		 359{
360 u32 value = readl(ioaddr + MAC_CTRL_REG);
47dd7a54 361
19449bfc 362 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
47dd7a54
GC		 363 writel(value, ioaddr + MAC_CTRL_REG);
364}
365
366/**
367 * display_ring
368 * @p: pointer to the ring.
369 * @size: size of the ring.
370 * Description: display all the descriptors within the ring.
371 */
372static void display_ring(struct dma_desc *p, int size)
373{
374 struct tmp_s {
375 u64 a;
376 unsigned int b;
377 unsigned int c;
378 };
379 int i;
380 for (i = 0; i < size; i++) {
381 struct tmp_s *x = (struct tmp_s *)(p + i);
382 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
383 i, (unsigned int)virt_to_phys(&p[i]),
384 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
385 x->b, x->c);
386 pr_info("\n");
387 }
388}
389
286a8372
GC		 390static int stmmac_set_bfsize(int mtu, int bufsize)
391{
392 int ret = bufsize;
393
394 if (mtu >= BUF_SIZE_4KiB)
395 ret = BUF_SIZE_8KiB;
396 else if (mtu >= BUF_SIZE_2KiB)
397 ret = BUF_SIZE_4KiB;
398 else if (mtu >= DMA_BUFFER_SIZE)
399 ret = BUF_SIZE_2KiB;
400 else
401 ret = DMA_BUFFER_SIZE;
402
403 return ret;
404}
405
47dd7a54
GC		 406/**
407 * init_dma_desc_rings - init the RX/TX descriptor rings
408 * @dev: net device structure
409 * Description: this function initializes the DMA RX/TX descriptors
286a8372
GC		 410 * and allocates the socket buffers. It suppors the chained and ring
411 * modes.
47dd7a54
GC		 412 */
413static void init_dma_desc_rings(struct net_device *dev)
414{
415 int i;
416 struct stmmac_priv *priv = netdev_priv(dev);
417 struct sk_buff *skb;
418 unsigned int txsize = priv->dma_tx_size;
419 unsigned int rxsize = priv->dma_rx_size;
286a8372
GC		 420 unsigned int bfsize;
421 int dis_ic = 0;
422 int des3_as_data_buf = 0;
47dd7a54 423
286a8372
GC		 424 /* Set the max buffer size according to the DESC mode
425 * and the MTU. Note that RING mode allows 16KiB bsize. */
426 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
427
428 if (bfsize == BUF_SIZE_16KiB)
429 des3_as_data_buf = 1;
47dd7a54 430 else
286a8372 431 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
47dd7a54 432
73cfe264
GC		 433#ifdef CONFIG_STMMAC_TIMER
434 /* Disable interrupts on completion for the reception if timer is on */
435 if (likely(priv->tm->enable))
436 dis_ic = 1;
437#endif
47dd7a54
GC		 438
439 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
440 txsize, rxsize, bfsize);
441
442 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
443 priv->rx_skbuff =
444 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
445 priv->dma_rx =
446 (struct dma_desc *)dma_alloc_coherent(priv->device,
447 rxsize *
448 sizeof(struct dma_desc),
449 &priv->dma_rx_phy,
450 GFP_KERNEL);
451 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
452 GFP_KERNEL);
453 priv->dma_tx =
454 (struct dma_desc *)dma_alloc_coherent(priv->device,
455 txsize *
456 sizeof(struct dma_desc),
457 &priv->dma_tx_phy,
458 GFP_KERNEL);
459
460 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
461 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
462 return;
463 }
464
286a8372 465 DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
47dd7a54
GC		 466 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
467 dev->name, priv->dma_rx, priv->dma_tx,
468 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
469
470 /* RX INITIALIZATION */
471 DBG(probe, INFO, "stmmac: SKB addresses:\n"
472 "skb\t\tskb data\tdma data\n");
473
474 for (i = 0; i < rxsize; i++) {
475 struct dma_desc *p = priv->dma_rx + i;
476
477 skb = netdev_alloc_skb_ip_align(dev, bfsize);
478 if (unlikely(skb == NULL)) {
479 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
480 break;
481 }
482 priv->rx_skbuff[i] = skb;
483 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
484 bfsize, DMA_FROM_DEVICE);
485
486 p->des2 = priv->rx_skbuff_dma[i];
286a8372
GC		 487
488 priv->hw->ring->init_desc3(des3_as_data_buf, p);
489
47dd7a54
GC		 490 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
491 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
492 }
493 priv->cur_rx = 0;
494 priv->dirty_rx = (unsigned int)(i - rxsize);
495 priv->dma_buf_sz = bfsize;
496 buf_sz = bfsize;
497
498 /* TX INITIALIZATION */
499 for (i = 0; i < txsize; i++) {
500 priv->tx_skbuff[i] = NULL;
501 priv->dma_tx[i].des2 = 0;
502 }
286a8372
GC		 503
504 /* In case of Chained mode this sets the des3 to the next
505 * element in the chain */
506 priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize);
507 priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize);
508
47dd7a54
GC		 509 priv->dirty_tx = 0;
510 priv->cur_tx = 0;
511
512 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 513 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
514 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
47dd7a54
GC		 515
516 if (netif_msg_hw(priv)) {
517 pr_info("RX descriptor ring:\n");
518 display_ring(priv->dma_rx, rxsize);
519 pr_info("TX descriptor ring:\n");
520 display_ring(priv->dma_tx, txsize);
521 }
47dd7a54
GC		 522}
523
524static void dma_free_rx_skbufs(struct stmmac_priv *priv)
525{
526 int i;
527
528 for (i = 0; i < priv->dma_rx_size; i++) {
529 if (priv->rx_skbuff[i]) {
530 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
531 priv->dma_buf_sz, DMA_FROM_DEVICE);
532 dev_kfree_skb_any(priv->rx_skbuff[i]);
533 }
534 priv->rx_skbuff[i] = NULL;
535 }
47dd7a54
GC		 536}
537
538static void dma_free_tx_skbufs(struct stmmac_priv *priv)
539{
540 int i;
541
542 for (i = 0; i < priv->dma_tx_size; i++) {
543 if (priv->tx_skbuff[i] != NULL) {
544 struct dma_desc *p = priv->dma_tx + i;
545 if (p->des2)
546 dma_unmap_single(priv->device, p->des2,
db98a0b0
GC		 547 priv->hw->desc->get_tx_len(p),
548 DMA_TO_DEVICE);
47dd7a54
GC		 549 dev_kfree_skb_any(priv->tx_skbuff[i]);
550 priv->tx_skbuff[i] = NULL;
551 }
552 }
47dd7a54
GC		 553}
554
555static void free_dma_desc_resources(struct stmmac_priv *priv)
556{
557 /* Release the DMA TX/RX socket buffers */
558 dma_free_rx_skbufs(priv);
559 dma_free_tx_skbufs(priv);
560
561 /* Free the region of consistent memory previously allocated for
562 * the DMA */
563 dma_free_coherent(priv->device,
564 priv->dma_tx_size * sizeof(struct dma_desc),
565 priv->dma_tx, priv->dma_tx_phy);
566 dma_free_coherent(priv->device,
567 priv->dma_rx_size * sizeof(struct dma_desc),
568 priv->dma_rx, priv->dma_rx_phy);
569 kfree(priv->rx_skbuff_dma);
570 kfree(priv->rx_skbuff);
571 kfree(priv->tx_skbuff);
47dd7a54
GC		 572}
573
47dd7a54
GC		 574/**
575 * stmmac_dma_operation_mode - HW DMA operation mode
576 * @priv : pointer to the private device structure.
577 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
ebbb293f 578 * or Store-And-Forward capability.
47dd7a54
GC		 579 */
580static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
581{
61b8013a
SK		 582 if (likely(priv->plat->force_sf_dma_mode ||
583 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
584 /*
585 * In case of GMAC, SF mode can be enabled
586 * to perform the TX COE in HW. This depends on:
ebbb293f
GC		 587 * 1) TX COE if actually supported
588 * 2) There is no bugged Jumbo frame support
589 * that needs to not insert csum in the TDES.
590 */
591 priv->hw->dma->dma_mode(priv->ioaddr,
592 SF_DMA_MODE, SF_DMA_MODE);
593 tc = SF_DMA_MODE;
594 } else
595 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
47dd7a54
GC		 596}
597
47dd7a54
GC		 598/**
599 * stmmac_tx:
600 * @priv: private driver structure
601 * Description: it reclaims resources after transmission completes.
602 */
603static void stmmac_tx(struct stmmac_priv *priv)
604{
605 unsigned int txsize = priv->dma_tx_size;
47dd7a54 606
a9097a96
GC		 607 spin_lock(&priv->tx_lock);
608
47dd7a54
GC		 609 while (priv->dirty_tx != priv->cur_tx) {
610 int last;
611 unsigned int entry = priv->dirty_tx % txsize;
612 struct sk_buff *skb = priv->tx_skbuff[entry];
613 struct dma_desc *p = priv->dma_tx + entry;
614
615 /* Check if the descriptor is owned by the DMA. */
db98a0b0 616 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 617 break;
618
619 /* Verify tx error by looking at the last segment */
db98a0b0 620 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 621 if (likely(last)) {
622 int tx_error =
db98a0b0
GC		 623 priv->hw->desc->tx_status(&priv->dev->stats,
624 &priv->xstats, p,
ad01b7d4 625 priv->ioaddr);
47dd7a54
GC		 626 if (likely(tx_error == 0)) {
627 priv->dev->stats.tx_packets++;
628 priv->xstats.tx_pkt_n++;
629 } else
630 priv->dev->stats.tx_errors++;
631 }
632 TX_DBG("%s: curr %d, dirty %d\n", __func__,
633 priv->cur_tx, priv->dirty_tx);
634
635 if (likely(p->des2))
636 dma_unmap_single(priv->device, p->des2,
db98a0b0 637 priv->hw->desc->get_tx_len(p),
47dd7a54 638 DMA_TO_DEVICE);
286a8372 639 priv->hw->ring->clean_desc3(p);
47dd7a54
GC		 640
641 if (likely(skb != NULL)) {
642 /*
643 * If there's room in the queue (limit it to size)
644 * we add this skb back into the pool,
645 * if it's the right size.
646 */
647 if ((skb_queue_len(&priv->rx_recycle) <
648 priv->dma_rx_size) &&
649 skb_recycle_check(skb, priv->dma_buf_sz))
650 __skb_queue_head(&priv->rx_recycle, skb);
651 else
652 dev_kfree_skb(skb);
653
654 priv->tx_skbuff[entry] = NULL;
655 }
656
db98a0b0 657 priv->hw->desc->release_tx_desc(p);
47dd7a54
GC		 658
659 entry = (++priv->dirty_tx) % txsize;
660 }
661 if (unlikely(netif_queue_stopped(priv->dev) &&
662 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
663 netif_tx_lock(priv->dev);
664 if (netif_queue_stopped(priv->dev) &&
665 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
666 TX_DBG("%s: restart transmit\n", __func__);
667 netif_wake_queue(priv->dev);
668 }
669 netif_tx_unlock(priv->dev);
670 }
a9097a96 671 spin_unlock(&priv->tx_lock);
47dd7a54
GC		 672}
673
674static inline void stmmac_enable_irq(struct stmmac_priv *priv)
675{
73cfe264
GC		 676#ifdef CONFIG_STMMAC_TIMER
677 if (likely(priv->tm->enable))
678 priv->tm->timer_start(tmrate);
679 else
47dd7a54 680#endif
ad01b7d4 681 priv->hw->dma->enable_dma_irq(priv->ioaddr);
47dd7a54
GC		 682}
683
684static inline void stmmac_disable_irq(struct stmmac_priv *priv)
685{
73cfe264
GC		 686#ifdef CONFIG_STMMAC_TIMER
687 if (likely(priv->tm->enable))
688 priv->tm->timer_stop();
689 else
47dd7a54 690#endif
ad01b7d4 691 priv->hw->dma->disable_dma_irq(priv->ioaddr);
47dd7a54
GC		 692}
693
694static int stmmac_has_work(struct stmmac_priv *priv)
695{
696 unsigned int has_work = 0;
697 int rxret, tx_work = 0;
698
db98a0b0 699 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
47dd7a54
GC		 700 (priv->cur_rx % priv->dma_rx_size));
701
702 if (priv->dirty_tx != priv->cur_tx)
703 tx_work = 1;
704
705 if (likely(!rxret || tx_work))
706 has_work = 1;
707
708 return has_work;
709}
710
711static inline void _stmmac_schedule(struct stmmac_priv *priv)
712{
713 if (likely(stmmac_has_work(priv))) {
714 stmmac_disable_irq(priv);
715 napi_schedule(&priv->napi);
716 }
717}
718
719#ifdef CONFIG_STMMAC_TIMER
720void stmmac_schedule(struct net_device *dev)
721{
722 struct stmmac_priv *priv = netdev_priv(dev);
723
724 priv->xstats.sched_timer_n++;
725
726 _stmmac_schedule(priv);
47dd7a54
GC		 727}
728
729static void stmmac_no_timer_started(unsigned int x)
730{;
731};
732
733static void stmmac_no_timer_stopped(void)
734{;
735};
736#endif
737
738/**
739 * stmmac_tx_err:
740 * @priv: pointer to the private device structure
741 * Description: it cleans the descriptors and restarts the transmission
742 * in case of errors.
743 */
744static void stmmac_tx_err(struct stmmac_priv *priv)
745{
746 netif_stop_queue(priv->dev);
747
ad01b7d4 748 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 749 dma_free_tx_skbufs(priv);
db98a0b0 750 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 751 priv->dirty_tx = 0;
752 priv->cur_tx = 0;
ad01b7d4 753 priv->hw->dma->start_tx(priv->ioaddr);
47dd7a54
GC		 754
755 priv->dev->stats.tx_errors++;
756 netif_wake_queue(priv->dev);
47dd7a54
GC		 757}
758
47dd7a54 759
aec7ff27
GC		 760static void stmmac_dma_interrupt(struct stmmac_priv *priv)
761{
aec7ff27
GC		 762 int status;
763
ad01b7d4 764 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
aec7ff27
GC		 765 if (likely(status == handle_tx_rx))
766 _stmmac_schedule(priv);
767
768 else if (unlikely(status == tx_hard_error_bump_tc)) {
769 /* Try to bump up the dma threshold on this failure */
770 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
771 tc += 64;
ad01b7d4 772 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
aec7ff27 773 priv->xstats.threshold = tc;
47dd7a54 774 }
aec7ff27
GC		 775 } else if (unlikely(status == tx_hard_error))
776 stmmac_tx_err(priv);
47dd7a54
GC		 777}
778
1c901a46
GC		 779static void stmmac_mmc_setup(struct stmmac_priv *priv)
780{
781 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
782 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
783
784 /* Do not manage MMC IRQ (FIXME) */
785 dwmac_mmc_intr_all_mask(priv->ioaddr);
786 dwmac_mmc_ctrl(priv->ioaddr, mode);
787 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
788}
789
f0b9d786
GC		 790static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
791{
792 u32 hwid = priv->hw->synopsys_uid;
793
794 /* Only check valid Synopsys Id because old MAC chips
795 * have no HW registers where get the ID */
796 if (likely(hwid)) {
797 u32 uid = ((hwid & 0x0000ff00) >> 8);
798 u32 synid = (hwid & 0x000000ff);
799
800 pr_info("STMMAC - user ID: 0x%x, Synopsys ID: 0x%x\n",
801 uid, synid);
802
803 return synid;
804 }
805 return 0;
806}
e7434821
GC		 807
808/* New GMAC chips support a new register to indicate the
809 * presence of the optional feature/functions.
810 */
811static int stmmac_get_hw_features(struct stmmac_priv *priv)
812{
813 u32 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
814
815 if (likely(hw_cap)) {
1db123fb
RK		 816 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
817 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
818 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
819 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
820 priv->dma_cap.multi_addr =
821 (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
822 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
823 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
824 priv->dma_cap.pmt_remote_wake_up =
825 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
826 priv->dma_cap.pmt_magic_frame =
827 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
828 /*MMC*/
829 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
e7434821 830 /* IEEE 1588-2002*/
1db123fb
RK		 831 priv->dma_cap.time_stamp =
832 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
e7434821 833 /* IEEE 1588-2008*/
1db123fb
RK		 834 priv->dma_cap.atime_stamp =
835 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
e7434821 836 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1db123fb
RK		 837 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
838 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
e7434821 839 /* TX and RX csum */
1db123fb
RK		 840 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
841 priv->dma_cap.rx_coe_type1 =
842 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
843 priv->dma_cap.rx_coe_type2 =
844 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
845 priv->dma_cap.rxfifo_over_2048 =
846 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
e7434821 847 /* TX and RX number of channels */
1db123fb
RK		 848 priv->dma_cap.number_rx_channel =
849 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
850 priv->dma_cap.number_tx_channel =
851 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
e7434821 852 /* Alternate (enhanced) DESC mode*/
1db123fb
RK		 853 priv->dma_cap.enh_desc =
854 (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
e7434821
GC		 855
856 } else
857 pr_debug("\tNo HW DMA feature register supported");
858
859 return hw_cap;
860}
861
47dd7a54
GC		 862/**
863 * stmmac_open - open entry point of the driver
864 * @dev : pointer to the device structure.
865 * Description:
866 * This function is the open entry point of the driver.
867 * Return value:
868 * 0 on success and an appropriate (-)ve integer as defined in errno.h
869 * file on failure.
870 */
871static int stmmac_open(struct net_device *dev)
872{
873 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 874 int ret;
875
876 /* Check that the MAC address is valid. If its not, refuse
877 * to bring the device up. The user must specify an
878 * address using the following linux command:
879 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
880 if (!is_valid_ether_addr(dev->dev_addr)) {
881 random_ether_addr(dev->dev_addr);
882 pr_warning("%s: generated random MAC address %pM\n", dev->name,
883 dev->dev_addr);
884 }
885
886 stmmac_verify_args();
887
47dd7a54 888#ifdef CONFIG_STMMAC_TIMER
73cfe264 889 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
47dd7a54 890 if (unlikely(priv->tm == NULL)) {
2381a55c 891 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
47dd7a54
GC		 892 return -ENOMEM;
893 }
894 priv->tm->freq = tmrate;
895
73cfe264
GC		 896 /* Test if the external timer can be actually used.
897 * In case of failure continue without timer. */
47dd7a54 898 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
73cfe264 899 pr_warning("stmmaceth: cannot attach the external timer.\n");
47dd7a54
GC		 900 priv->tm->freq = 0;
901 priv->tm->timer_start = stmmac_no_timer_started;
902 priv->tm->timer_stop = stmmac_no_timer_stopped;
73cfe264
GC		 903 } else
904 priv->tm->enable = 1;
47dd7a54 905#endif
f66ffe28
GC		 906 ret = stmmac_init_phy(dev);
907 if (unlikely(ret)) {
908 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
909 goto open_error;
910 }
47dd7a54
GC		 911
912 /* Create and initialize the TX/RX descriptors chains. */
913 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
914 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
915 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
916 init_dma_desc_rings(dev);
917
918 /* DMA initialization and SW reset */
f66ffe28
GC		 919 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
920 priv->dma_tx_phy, priv->dma_rx_phy);
921 if (ret < 0) {
47dd7a54 922 pr_err("%s: DMA initialization failed\n", __func__);
f66ffe28 923 goto open_error;
47dd7a54
GC		 924 }
925
926 /* Copy the MAC addr into the HW */
ad01b7d4 927 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
ca5f12c1 928 /* If required, perform hw setup of the bus. */
9dfeb4d9
GC		 929 if (priv->plat->bus_setup)
930 priv->plat->bus_setup(priv->ioaddr);
47dd7a54 931 /* Initialize the MAC Core */
ad01b7d4 932 priv->hw->mac->core_init(priv->ioaddr);
47dd7a54 933
f0b9d786
GC		 934 stmmac_get_synopsys_id(priv);
935
e7434821
GC		 936 stmmac_get_hw_features(priv);
937
ebbb293f
GC		 938 if (priv->rx_coe)
939 pr_info("stmmac: Rx Checksum Offload Engine supported\n");
9dfeb4d9 940 if (priv->plat->tx_coe)
ebbb293f 941 pr_info("\tTX Checksum insertion supported\n");
5e982f3b 942 netdev_update_features(dev);
ebbb293f 943
f66ffe28
GC		 944 /* Request the IRQ lines */
945 ret = request_irq(dev->irq, stmmac_interrupt,
946 IRQF_SHARED, dev->name, dev);
947 if (unlikely(ret < 0)) {
948 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
949 __func__, dev->irq, ret);
950 goto open_error;
951 }
952
47dd7a54 953 /* Enable the MAC Rx/Tx */
19449bfc 954 stmmac_enable_mac(priv->ioaddr);
47dd7a54
GC		 955
956 /* Set the HW DMA mode and the COE */
957 stmmac_dma_operation_mode(priv);
958
959 /* Extra statistics */
960 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
961 priv->xstats.threshold = tc;
962
38fe7a93
GC		 963 if (priv->dma_cap.rmon)
964 stmmac_mmc_setup(priv);
1c901a46 965
47dd7a54
GC		 966 /* Start the ball rolling... */
967 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
ad01b7d4
GC		 968 priv->hw->dma->start_tx(priv->ioaddr);
969 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 970
971#ifdef CONFIG_STMMAC_TIMER
972 priv->tm->timer_start(tmrate);
973#endif
974 /* Dump DMA/MAC registers */
975 if (netif_msg_hw(priv)) {
ad01b7d4
GC		 976 priv->hw->mac->dump_regs(priv->ioaddr);
977 priv->hw->dma->dump_regs(priv->ioaddr);
47dd7a54
GC		 978 }
979
980 if (priv->phydev)
981 phy_start(priv->phydev);
982
983 napi_enable(&priv->napi);
984 skb_queue_head_init(&priv->rx_recycle);
985 netif_start_queue(dev);
f66ffe28 986
47dd7a54 987 return 0;
f66ffe28
GC		 988
989open_error:
990#ifdef CONFIG_STMMAC_TIMER
991 kfree(priv->tm);
992#endif
993 if (priv->phydev)
994 phy_disconnect(priv->phydev);
995
996 return ret;
47dd7a54
GC		 997}
998
999/**
1000 * stmmac_release - close entry point of the driver
1001 * @dev : device pointer.
1002 * Description:
1003 * This is the stop entry point of the driver.
1004 */
1005static int stmmac_release(struct net_device *dev)
1006{
1007 struct stmmac_priv *priv = netdev_priv(dev);
1008
1009 /* Stop and disconnect the PHY */
1010 if (priv->phydev) {
1011 phy_stop(priv->phydev);
1012 phy_disconnect(priv->phydev);
1013 priv->phydev = NULL;
1014 }
1015
1016 netif_stop_queue(dev);
1017
1018#ifdef CONFIG_STMMAC_TIMER
1019 /* Stop and release the timer */
1020 stmmac_close_ext_timer();
1021 if (priv->tm != NULL)
1022 kfree(priv->tm);
1023#endif
1024 napi_disable(&priv->napi);
1025 skb_queue_purge(&priv->rx_recycle);
1026
1027 /* Free the IRQ lines */
1028 free_irq(dev->irq, dev);
1029
1030 /* Stop TX/RX DMA and clear the descriptors */
ad01b7d4
GC		 1031 priv->hw->dma->stop_tx(priv->ioaddr);
1032 priv->hw->dma->stop_rx(priv->ioaddr);
47dd7a54
GC		 1033
1034 /* Release and free the Rx/Tx resources */
1035 free_dma_desc_resources(priv);
1036
19449bfc 1037 /* Disable the MAC Rx/Tx */
1038 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 1039
1040 netif_carrier_off(dev);
1041
1042 return 0;
1043}
1044
47dd7a54
GC		 1045/**
1046 * stmmac_xmit:
1047 * @skb : the socket buffer
1048 * @dev : device pointer
1049 * Description : Tx entry point of the driver.
1050 */
1051static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1052{
1053 struct stmmac_priv *priv = netdev_priv(dev);
1054 unsigned int txsize = priv->dma_tx_size;
1055 unsigned int entry;
1056 int i, csum_insertion = 0;
1057 int nfrags = skb_shinfo(skb)->nr_frags;
1058 struct dma_desc *desc, *first;
286a8372 1059 unsigned int nopaged_len = skb_headlen(skb);
47dd7a54
GC		 1060
1061 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1062 if (!netif_queue_stopped(dev)) {
1063 netif_stop_queue(dev);
1064 /* This is a hard error, log it. */
1065 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1066 __func__);
1067 }
1068 return NETDEV_TX_BUSY;
1069 }
1070
a9097a96
GC		 1071 spin_lock(&priv->tx_lock);
1072
47dd7a54
GC		 1073 entry = priv->cur_tx % txsize;
1074
1075#ifdef STMMAC_XMIT_DEBUG
1076 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1077 pr_info("stmmac xmit:\n"
1078 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1079 "\tn_frags: %d - ip_summed: %d - %s gso\n",
286a8372 1080 skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
47dd7a54
GC		 1081 !skb_is_gso(skb) ? "isn't" : "is");
1082#endif
1083
5e982f3b 1084 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
47dd7a54
GC		 1085
1086 desc = priv->dma_tx + entry;
1087 first = desc;
1088
1089#ifdef STMMAC_XMIT_DEBUG
1090 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1091 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1092 "\t\tn_frags: %d, ip_summed: %d\n",
286a8372 1093 skb->len, nopaged_len, nfrags, skb->ip_summed);
47dd7a54
GC		 1094#endif
1095 priv->tx_skbuff[entry] = skb;
286a8372
GC		 1096
1097 if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) {
1098 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion);
47dd7a54
GC		 1099 desc = priv->dma_tx + entry;
1100 } else {
47dd7a54
GC		 1101 desc->des2 = dma_map_single(priv->device, skb->data,
1102 nopaged_len, DMA_TO_DEVICE);
db98a0b0
GC		 1103 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1104 csum_insertion);
47dd7a54
GC		 1105 }
1106
1107 for (i = 0; i < nfrags; i++) {
9e903e08
ED		 1108 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1109 int len = skb_frag_size(frag);
47dd7a54
GC		 1110
1111 entry = (++priv->cur_tx) % txsize;
1112 desc = priv->dma_tx + entry;
1113
1114 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
f722380d
IC		 1115 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1116 DMA_TO_DEVICE);
47dd7a54 1117 priv->tx_skbuff[entry] = NULL;
db98a0b0 1118 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
eb0dc4bb 1119 wmb();
db98a0b0 1120 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1121 }
1122
1123 /* Interrupt on completition only for the latest segment */
db98a0b0 1124 priv->hw->desc->close_tx_desc(desc);
73cfe264 1125
47dd7a54 1126#ifdef CONFIG_STMMAC_TIMER
73cfe264
GC		 1127 /* Clean IC while using timer */
1128 if (likely(priv->tm->enable))
db98a0b0 1129 priv->hw->desc->clear_tx_ic(desc);
47dd7a54 1130#endif
eb0dc4bb
SH		 1131
1132 wmb();
1133
47dd7a54 1134 /* To avoid raise condition */
db98a0b0 1135 priv->hw->desc->set_tx_owner(first);
47dd7a54
GC		 1136
1137 priv->cur_tx++;
1138
1139#ifdef STMMAC_XMIT_DEBUG
1140 if (netif_msg_pktdata(priv)) {
1141 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1142 "first=%p, nfrags=%d\n",
1143 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1144 entry, first, nfrags);
1145 display_ring(priv->dma_tx, txsize);
1146 pr_info(">>> frame to be transmitted: ");
1147 print_pkt(skb->data, skb->len);
1148 }
1149#endif
1150 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1151 TX_DBG("%s: stop transmitted packets\n", __func__);
1152 netif_stop_queue(dev);
1153 }
1154
1155 dev->stats.tx_bytes += skb->len;
1156
3e82ce12
RC		 1157 skb_tx_timestamp(skb);
1158
52f64fae
RC		 1159 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1160
a9097a96
GC		 1161 spin_unlock(&priv->tx_lock);
1162
47dd7a54
GC		 1163 return NETDEV_TX_OK;
1164}
1165
1166static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1167{
1168 unsigned int rxsize = priv->dma_rx_size;
1169 int bfsize = priv->dma_buf_sz;
1170 struct dma_desc *p = priv->dma_rx;
1171
1172 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1173 unsigned int entry = priv->dirty_rx % rxsize;
1174 if (likely(priv->rx_skbuff[entry] == NULL)) {
1175 struct sk_buff *skb;
1176
1177 skb = __skb_dequeue(&priv->rx_recycle);
1178 if (skb == NULL)
1179 skb = netdev_alloc_skb_ip_align(priv->dev,
1180 bfsize);
1181
1182 if (unlikely(skb == NULL))
1183 break;
1184
1185 priv->rx_skbuff[entry] = skb;
1186 priv->rx_skbuff_dma[entry] =
1187 dma_map_single(priv->device, skb->data, bfsize,
1188 DMA_FROM_DEVICE);
1189
1190 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
286a8372
GC		 1191
1192 if (unlikely(priv->plat->has_gmac))
1193 priv->hw->ring->refill_desc3(bfsize, p + entry);
1194
47dd7a54
GC		 1195 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1196 }
eb0dc4bb 1197 wmb();
db98a0b0 1198 priv->hw->desc->set_rx_owner(p + entry);
47dd7a54 1199 }
47dd7a54
GC		 1200}
1201
1202static int stmmac_rx(struct stmmac_priv *priv, int limit)
1203{
1204 unsigned int rxsize = priv->dma_rx_size;
1205 unsigned int entry = priv->cur_rx % rxsize;
1206 unsigned int next_entry;
1207 unsigned int count = 0;
1208 struct dma_desc *p = priv->dma_rx + entry;
1209 struct dma_desc *p_next;
1210
1211#ifdef STMMAC_RX_DEBUG
1212 if (netif_msg_hw(priv)) {
1213 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1214 display_ring(priv->dma_rx, rxsize);
1215 }
1216#endif
1217 count = 0;
db98a0b0 1218 while (!priv->hw->desc->get_rx_owner(p)) {
47dd7a54
GC		 1219 int status;
1220
1221 if (count >= limit)
1222 break;
1223
1224 count++;
1225
1226 next_entry = (++priv->cur_rx) % rxsize;
1227 p_next = priv->dma_rx + next_entry;
1228 prefetch(p_next);
1229
1230 /* read the status of the incoming frame */
db98a0b0
GC		 1231 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1232 &priv->xstats, p));
47dd7a54
GC		 1233 if (unlikely(status == discard_frame))
1234 priv->dev->stats.rx_errors++;
1235 else {
1236 struct sk_buff *skb;
3eeb2997 1237 int frame_len;
47dd7a54 1238
3eeb2997
GC		 1239 frame_len = priv->hw->desc->get_rx_frame_len(p);
1240 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1241 * Type frames (LLC/LLC-SNAP) */
1242 if (unlikely(status != llc_snap))
1243 frame_len -= ETH_FCS_LEN;
47dd7a54
GC		 1244#ifdef STMMAC_RX_DEBUG
1245 if (frame_len > ETH_FRAME_LEN)
1246 pr_debug("\tRX frame size %d, COE status: %d\n",
1247 frame_len, status);
1248
1249 if (netif_msg_hw(priv))
1250 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1251 p, entry, p->des2);
1252#endif
1253 skb = priv->rx_skbuff[entry];
1254 if (unlikely(!skb)) {
1255 pr_err("%s: Inconsistent Rx descriptor chain\n",
1256 priv->dev->name);
1257 priv->dev->stats.rx_dropped++;
1258 break;
1259 }
1260 prefetch(skb->data - NET_IP_ALIGN);
1261 priv->rx_skbuff[entry] = NULL;
1262
1263 skb_put(skb, frame_len);
1264 dma_unmap_single(priv->device,
1265 priv->rx_skbuff_dma[entry],
1266 priv->dma_buf_sz, DMA_FROM_DEVICE);
1267#ifdef STMMAC_RX_DEBUG
1268 if (netif_msg_pktdata(priv)) {
1269 pr_info(" frame received (%dbytes)", frame_len);
1270 print_pkt(skb->data, frame_len);
1271 }
1272#endif
1273 skb->protocol = eth_type_trans(skb, priv->dev);
1274
1275 if (unlikely(status == csum_none)) {
1276 /* always for the old mac 10/100 */
bc8acf2c 1277 skb_checksum_none_assert(skb);
47dd7a54
GC		 1278 netif_receive_skb(skb);
1279 } else {
1280 skb->ip_summed = CHECKSUM_UNNECESSARY;
1281 napi_gro_receive(&priv->napi, skb);
1282 }
1283
1284 priv->dev->stats.rx_packets++;
1285 priv->dev->stats.rx_bytes += frame_len;
47dd7a54
GC		 1286 }
1287 entry = next_entry;
1288 p = p_next; /* use prefetched values */
1289 }
1290
1291 stmmac_rx_refill(priv);
1292
1293 priv->xstats.rx_pkt_n += count;
1294
1295 return count;
1296}
1297
1298/**
1299 * stmmac_poll - stmmac poll method (NAPI)
1300 * @napi : pointer to the napi structure.
1301 * @budget : maximum number of packets that the current CPU can receive from
1302 * all interfaces.
1303 * Description :
1304 * This function implements the the reception process.
1305 * Also it runs the TX completion thread
1306 */
1307static int stmmac_poll(struct napi_struct *napi, int budget)
1308{
1309 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1310 int work_done = 0;
1311
1312 priv->xstats.poll_n++;
1313 stmmac_tx(priv);
1314 work_done = stmmac_rx(priv, budget);
1315
1316 if (work_done < budget) {
1317 napi_complete(napi);
1318 stmmac_enable_irq(priv);
1319 }
1320 return work_done;
1321}
1322
1323/**
1324 * stmmac_tx_timeout
1325 * @dev : Pointer to net device structure
1326 * Description: this function is called when a packet transmission fails to
1327 * complete within a reasonable tmrate. The driver will mark the error in the
1328 * netdev structure and arrange for the device to be reset to a sane state
1329 * in order to transmit a new packet.
1330 */
1331static void stmmac_tx_timeout(struct net_device *dev)
1332{
1333 struct stmmac_priv *priv = netdev_priv(dev);
1334
1335 /* Clear Tx resources and restart transmitting again */
1336 stmmac_tx_err(priv);
47dd7a54
GC		 1337}
1338
1339/* Configuration changes (passed on by ifconfig) */
1340static int stmmac_config(struct net_device *dev, struct ifmap *map)
1341{
1342 if (dev->flags & IFF_UP) /* can't act on a running interface */
1343 return -EBUSY;
1344
1345 /* Don't allow changing the I/O address */
1346 if (map->base_addr != dev->base_addr) {
1347 pr_warning("%s: can't change I/O address\n", dev->name);
1348 return -EOPNOTSUPP;
1349 }
1350
1351 /* Don't allow changing the IRQ */
1352 if (map->irq != dev->irq) {
1353 pr_warning("%s: can't change IRQ number %d\n",
1354 dev->name, dev->irq);
1355 return -EOPNOTSUPP;
1356 }
1357
1358 /* ignore other fields */
1359 return 0;
1360}
1361
1362/**
01789349 1363 * stmmac_set_rx_mode - entry point for multicast addressing
47dd7a54
GC		 1364 * @dev : pointer to the device structure
1365 * Description:
1366 * This function is a driver entry point which gets called by the kernel
1367 * whenever multicast addresses must be enabled/disabled.
1368 * Return value:
1369 * void.
1370 */
01789349 1371static void stmmac_set_rx_mode(struct net_device *dev)
47dd7a54
GC		 1372{
1373 struct stmmac_priv *priv = netdev_priv(dev);
1374
1375 spin_lock(&priv->lock);
db98a0b0 1376 priv->hw->mac->set_filter(dev);
47dd7a54 1377 spin_unlock(&priv->lock);
47dd7a54
GC		 1378}
1379
1380/**
1381 * stmmac_change_mtu - entry point to change MTU size for the device.
1382 * @dev : device pointer.
1383 * @new_mtu : the new MTU size for the device.
1384 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1385 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1386 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1387 * Return value:
1388 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1389 * file on failure.
1390 */
1391static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1392{
1393 struct stmmac_priv *priv = netdev_priv(dev);
1394 int max_mtu;
1395
1396 if (netif_running(dev)) {
1397 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1398 return -EBUSY;
1399 }
1400
48febf7e 1401 if (priv->plat->enh_desc)
47dd7a54
GC		 1402 max_mtu = JUMBO_LEN;
1403 else
48febf7e 1404 max_mtu = BUF_SIZE_4KiB;
47dd7a54
GC		 1405
1406 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1407 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1408 return -EINVAL;
1409 }
1410
5e982f3b
MM		 1411 dev->mtu = new_mtu;
1412 netdev_update_features(dev);
1413
1414 return 0;
1415}
1416
1417static u32 stmmac_fix_features(struct net_device *dev, u32 features)
1418{
1419 struct stmmac_priv *priv = netdev_priv(dev);
1420
1421 if (!priv->rx_coe)
1422 features &= ~NETIF_F_RXCSUM;
1423 if (!priv->plat->tx_coe)
1424 features &= ~NETIF_F_ALL_CSUM;
1425
ebbb293f
GC		 1426 /* Some GMAC devices have a bugged Jumbo frame support that
1427 * needs to have the Tx COE disabled for oversized frames
1428 * (due to limited buffer sizes). In this case we disable
1429 * the TX csum insertionin the TDES and not use SF. */
5e982f3b
MM		 1430 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1431 features &= ~NETIF_F_ALL_CSUM;
ebbb293f 1432
5e982f3b 1433 return features;
47dd7a54
GC		 1434}
1435
1436static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1437{
1438 struct net_device *dev = (struct net_device *)dev_id;
1439 struct stmmac_priv *priv = netdev_priv(dev);
1440
1441 if (unlikely(!dev)) {
1442 pr_err("%s: invalid dev pointer\n", __func__);
1443 return IRQ_NONE;
1444 }
1445
9dfeb4d9 1446 if (priv->plat->has_gmac)
47dd7a54 1447 /* To handle GMAC own interrupts */
ad01b7d4 1448 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
aec7ff27
GC		 1449
1450 stmmac_dma_interrupt(priv);
47dd7a54
GC		 1451
1452 return IRQ_HANDLED;
1453}
1454
1455#ifdef CONFIG_NET_POLL_CONTROLLER
1456/* Polling receive - used by NETCONSOLE and other diagnostic tools
1457 * to allow network I/O with interrupts disabled. */
1458static void stmmac_poll_controller(struct net_device *dev)
1459{
1460 disable_irq(dev->irq);
1461 stmmac_interrupt(dev->irq, dev);
1462 enable_irq(dev->irq);
1463}
1464#endif
1465
1466/**
1467 * stmmac_ioctl - Entry point for the Ioctl
1468 * @dev: Device pointer.
1469 * @rq: An IOCTL specefic structure, that can contain a pointer to
1470 * a proprietary structure used to pass information to the driver.
1471 * @cmd: IOCTL command
1472 * Description:
1473 * Currently there are no special functionality supported in IOCTL, just the
1474 * phy_mii_ioctl(...) can be invoked.
1475 */
1476static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1477{
1478 struct stmmac_priv *priv = netdev_priv(dev);
28b04113 1479 int ret;
47dd7a54
GC		 1480
1481 if (!netif_running(dev))
1482 return -EINVAL;
1483
28b04113
RC		 1484 if (!priv->phydev)
1485 return -EINVAL;
1486
1487 spin_lock(&priv->lock);
1488 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1489 spin_unlock(&priv->lock);
1490
47dd7a54
GC		 1491 return ret;
1492}
1493
7ac29055
GC		 1494#ifdef CONFIG_STMMAC_DEBUG_FS
1495static struct dentry *stmmac_fs_dir;
1496static struct dentry *stmmac_rings_status;
e7434821 1497static struct dentry *stmmac_dma_cap;
7ac29055
GC		 1498
1499static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1500{
1501 struct tmp_s {
1502 u64 a;
1503 unsigned int b;
1504 unsigned int c;
1505 };
1506 int i;
1507 struct net_device *dev = seq->private;
1508 struct stmmac_priv *priv = netdev_priv(dev);
1509
1510 seq_printf(seq, "=======================\n");
1511 seq_printf(seq, " RX descriptor ring\n");
1512 seq_printf(seq, "=======================\n");
1513
1514 for (i = 0; i < priv->dma_rx_size; i++) {
1515 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1516 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1517 i, (unsigned int)(x->a),
1518 (unsigned int)((x->a) >> 32), x->b, x->c);
1519 seq_printf(seq, "\n");
1520 }
1521
1522 seq_printf(seq, "\n");
1523 seq_printf(seq, "=======================\n");
1524 seq_printf(seq, " TX descriptor ring\n");
1525 seq_printf(seq, "=======================\n");
1526
1527 for (i = 0; i < priv->dma_tx_size; i++) {
1528 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1529 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1530 i, (unsigned int)(x->a),
1531 (unsigned int)((x->a) >> 32), x->b, x->c);
1532 seq_printf(seq, "\n");
1533 }
1534
1535 return 0;
1536}
1537
1538static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1539{
1540 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1541}
1542
1543static const struct file_operations stmmac_rings_status_fops = {
1544 .owner = THIS_MODULE,
1545 .open = stmmac_sysfs_ring_open,
1546 .read = seq_read,
1547 .llseek = seq_lseek,
1548 .release = seq_release,
1549};
1550
e7434821
GC		 1551static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1552{
1553 struct net_device *dev = seq->private;
1554 struct stmmac_priv *priv = netdev_priv(dev);
1555
1556 if (!stmmac_get_hw_features(priv)) {
1557 seq_printf(seq, "DMA HW features not supported\n");
1558 return 0;
1559 }
1560
1561 seq_printf(seq, "==============================\n");
1562 seq_printf(seq, "\tDMA HW features\n");
1563 seq_printf(seq, "==============================\n");
1564
1565 seq_printf(seq, "\t10/100 Mbps %s\n",
1566 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1567 seq_printf(seq, "\t1000 Mbps %s\n",
1568 (priv->dma_cap.mbps_1000) ? "Y" : "N");
1569 seq_printf(seq, "\tHalf duple %s\n",
1570 (priv->dma_cap.half_duplex) ? "Y" : "N");
1571 seq_printf(seq, "\tHash Filter: %s\n",
1572 (priv->dma_cap.hash_filter) ? "Y" : "N");
1573 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1574 (priv->dma_cap.multi_addr) ? "Y" : "N");
1575 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1576 (priv->dma_cap.pcs) ? "Y" : "N");
1577 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1578 (priv->dma_cap.sma_mdio) ? "Y" : "N");
1579 seq_printf(seq, "\tPMT Remote wake up: %s\n",
1580 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1581 seq_printf(seq, "\tPMT Magic Frame: %s\n",
1582 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1583 seq_printf(seq, "\tRMON module: %s\n",
1584 (priv->dma_cap.rmon) ? "Y" : "N");
1585 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1586 (priv->dma_cap.time_stamp) ? "Y" : "N");
1587 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1588 (priv->dma_cap.atime_stamp) ? "Y" : "N");
1589 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1590 (priv->dma_cap.eee) ? "Y" : "N");
1591 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1592 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1593 (priv->dma_cap.tx_coe) ? "Y" : "N");
1594 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1595 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1596 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1597 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1598 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1599 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1600 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1601 priv->dma_cap.number_rx_channel);
1602 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1603 priv->dma_cap.number_tx_channel);
1604 seq_printf(seq, "\tEnhanced descriptors: %s\n",
1605 (priv->dma_cap.enh_desc) ? "Y" : "N");
1606
1607 return 0;
1608}
1609
1610static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1611{
1612 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1613}
1614
1615static const struct file_operations stmmac_dma_cap_fops = {
1616 .owner = THIS_MODULE,
1617 .open = stmmac_sysfs_dma_cap_open,
1618 .read = seq_read,
1619 .llseek = seq_lseek,
1620 .release = seq_release,
1621};
1622
7ac29055
GC		 1623static int stmmac_init_fs(struct net_device *dev)
1624{
1625 /* Create debugfs entries */
1626 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1627
1628 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1629 pr_err("ERROR %s, debugfs create directory failed\n",
1630 STMMAC_RESOURCE_NAME);
1631
1632 return -ENOMEM;
1633 }
1634
1635 /* Entry to report DMA RX/TX rings */
1636 stmmac_rings_status = debugfs_create_file("descriptors_status",
1637 S_IRUGO, stmmac_fs_dir, dev,
1638 &stmmac_rings_status_fops);
1639
1640 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1641 pr_info("ERROR creating stmmac ring debugfs file\n");
1642 debugfs_remove(stmmac_fs_dir);
1643
1644 return -ENOMEM;
1645 }
1646
e7434821
GC		 1647 /* Entry to report the DMA HW features */
1648 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1649 dev, &stmmac_dma_cap_fops);
1650
1651 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1652 pr_info("ERROR creating stmmac MMC debugfs file\n");
1653 debugfs_remove(stmmac_rings_status);
1654 debugfs_remove(stmmac_fs_dir);
1655
1656 return -ENOMEM;
1657 }
1658
7ac29055
GC		 1659 return 0;
1660}
1661
1662static void stmmac_exit_fs(void)
1663{
1664 debugfs_remove(stmmac_rings_status);
e7434821 1665 debugfs_remove(stmmac_dma_cap);
7ac29055
GC		 1666 debugfs_remove(stmmac_fs_dir);
1667}
1668#endif /* CONFIG_STMMAC_DEBUG_FS */
1669
47dd7a54
GC		 1670static const struct net_device_ops stmmac_netdev_ops = {
1671 .ndo_open = stmmac_open,
1672 .ndo_start_xmit = stmmac_xmit,
1673 .ndo_stop = stmmac_release,
1674 .ndo_change_mtu = stmmac_change_mtu,
5e982f3b 1675 .ndo_fix_features = stmmac_fix_features,
01789349 1676 .ndo_set_rx_mode = stmmac_set_rx_mode,
47dd7a54
GC		 1677 .ndo_tx_timeout = stmmac_tx_timeout,
1678 .ndo_do_ioctl = stmmac_ioctl,
1679 .ndo_set_config = stmmac_config,
47dd7a54
GC		 1680#ifdef CONFIG_NET_POLL_CONTROLLER
1681 .ndo_poll_controller = stmmac_poll_controller,
1682#endif
1683 .ndo_set_mac_address = eth_mac_addr,
1684};
1685
1686/**
1687 * stmmac_probe - Initialization of the adapter .
1688 * @dev : device pointer
1689 * Description: The function initializes the network device structure for
1690 * the STMMAC driver. It also calls the low level routines
1691 * in order to init the HW (i.e. the DMA engine)
1692 */
1693static int stmmac_probe(struct net_device *dev)
1694{
1695 int ret = 0;
1696 struct stmmac_priv *priv = netdev_priv(dev);
1697
1698 ether_setup(dev);
1699
1700 dev->netdev_ops = &stmmac_netdev_ops;
1701 stmmac_set_ethtool_ops(dev);
1702
5e982f3b
MM		 1703 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1704 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
47dd7a54
GC		 1705 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1706#ifdef STMMAC_VLAN_TAG_USED
1707 /* Both mac100 and gmac support receive VLAN tag detection */
1708 dev->features |= NETIF_F_HW_VLAN_RX;
1709#endif
1710 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1711
47dd7a54
GC		 1712 if (flow_ctrl)
1713 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1714
1715 priv->pause = pause;
1716 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1717
1718 /* Get the MAC address */
ad01b7d4
GC		 1719 priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr,
1720 dev->dev_addr, 0);
47dd7a54
GC		 1721
1722 if (!is_valid_ether_addr(dev->dev_addr))
1723 pr_warning("\tno valid MAC address;"
1724 "please, use ifconfig or nwhwconfig!\n");
1725
f8e96161 1726 spin_lock_init(&priv->lock);
a9097a96 1727 spin_lock_init(&priv->tx_lock);
f8e96161 1728
47dd7a54
GC		 1729 ret = register_netdev(dev);
1730 if (ret) {
1731 pr_err("%s: ERROR %i registering the device\n",
1732 __func__, ret);
1733 return -ENODEV;
1734 }
1735
1736 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1737 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
79032644 1738 (dev->features & NETIF_F_IP_CSUM) ? "on" : "off");
47dd7a54 1739
47dd7a54
GC		 1740 return ret;
1741}
1742
1743/**
1744 * stmmac_mac_device_setup
1745 * @dev : device pointer
1746 * Description: select and initialise the mac device (mac100 or Gmac).
1747 */
1748static int stmmac_mac_device_setup(struct net_device *dev)
1749{
1750 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 1751
1752 struct mac_device_info *device;
1753
01789349
JP		 1754 if (priv->plat->has_gmac) {
1755 dev->priv_flags |= IFF_UNICAST_FLT;
ad01b7d4 1756 device = dwmac1000_setup(priv->ioaddr);
01789349 1757 } else {
ad01b7d4 1758 device = dwmac100_setup(priv->ioaddr);
01789349 1759 }
3d90c508 1760
1ff21906
DC		 1761 if (!device)
1762 return -ENOMEM;
1763
9dfeb4d9 1764 if (priv->plat->enh_desc) {
3d90c508
GC		 1765 device->desc = &enh_desc_ops;
1766 pr_info("\tEnhanced descriptor structure\n");
1767 } else
56b106ae 1768 device->desc = &ndesc_ops;
47dd7a54 1769
db98a0b0 1770 priv->hw = device;
286a8372 1771 priv->hw->ring = &ring_mode_ops;
47dd7a54 1772
539c9aa5 1773 if (device_can_wakeup(priv->device)) {
543876c9 1774 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
3172d3af 1775 enable_irq_wake(priv->wol_irq);
539c9aa5 1776 }
47dd7a54
GC		 1777
1778 return 0;
1779}
1780
47dd7a54
GC		 1781/**
1782 * stmmac_dvr_probe
1783 * @pdev: platform device pointer
1784 * Description: the driver is initialized through platform_device.
1785 */
1786static int stmmac_dvr_probe(struct platform_device *pdev)
1787{
1788 int ret = 0;
1789 struct resource *res;
ad01b7d4 1790 void __iomem *addr = NULL;
47dd7a54 1791 struct net_device *ndev = NULL;
293bb1c4 1792 struct stmmac_priv *priv = NULL;
47dd7a54
GC		 1793 struct plat_stmmacenet_data *plat_dat;
1794
1795 pr_info("STMMAC driver:\n\tplatform registration... ");
1796 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
34a52f36
DC		 1797 if (!res)
1798 return -ENODEV;
ebbb293f 1799 pr_info("\tdone!\n");
47dd7a54 1800
b6222682 1801 if (!request_mem_region(res->start, resource_size(res),
47dd7a54
GC		 1802 pdev->name)) {
1803 pr_err("%s: ERROR: memory allocation failed"
1804 "cannot get the I/O addr 0x%x\n",
1805 __func__, (unsigned int)res->start);
34a52f36 1806 return -EBUSY;
47dd7a54
GC		 1807 }
1808
7c5365bc 1809 addr = ioremap(res->start, resource_size(res));
47dd7a54 1810 if (!addr) {
7c5365bc 1811 pr_err("%s: ERROR: memory mapping failed\n", __func__);
47dd7a54 1812 ret = -ENOMEM;
34a52f36 1813 goto out_release_region;
47dd7a54
GC		 1814 }
1815
1816 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1817 if (!ndev) {
1818 pr_err("%s: ERROR: allocating the device\n", __func__);
1819 ret = -ENOMEM;
34a52f36 1820 goto out_unmap;
47dd7a54
GC		 1821 }
1822
1823 SET_NETDEV_DEV(ndev, &pdev->dev);
1824
1825 /* Get the MAC information */
1826 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1827 if (ndev->irq == -ENXIO) {
1828 pr_err("%s: ERROR: MAC IRQ configuration "
1829 "information not found\n", __func__);
34a52f36
DC		 1830 ret = -ENXIO;
1831 goto out_free_ndev;
47dd7a54
GC		 1832 }
1833
1834 priv = netdev_priv(ndev);
1835 priv->device = &(pdev->dev);
1836 priv->dev = ndev;
ee7946a7 1837 plat_dat = pdev->dev.platform_data;
9dfeb4d9
GC		 1838
1839 priv->plat = plat_dat;
1840
ad01b7d4 1841 priv->ioaddr = addr;
47dd7a54 1842
543876c9
GC		 1843 /* PMT module is not integrated in all the MAC devices. */
1844 if (plat_dat->pmt) {
1845 pr_info("\tPMT module supported\n");
1846 device_set_wakeup_capable(&pdev->dev, 1);
1847 }
3172d3af
DS		 1848 /*
1849 * On some platforms e.g. SPEAr the wake up irq differs from the mac irq
1850 * The external wake up irq can be passed through the platform code
1851 * named as "eth_wake_irq"
1852 *
1853 * In case the wake up interrupt is not passed from the platform
1854 * so the driver will continue to use the mac irq (ndev->irq)
1855 */
1856 priv->wol_irq = platform_get_irq_byname(pdev, "eth_wake_irq");
1857 if (priv->wol_irq == -ENXIO)
1858 priv->wol_irq = ndev->irq;
1859
543876c9 1860
47dd7a54
GC		 1861 platform_set_drvdata(pdev, ndev);
1862
1863 /* Set the I/O base addr */
1864 ndev->base_addr = (unsigned long)addr;
1865
293bb1c4
GC		 1866 /* Custom initialisation */
1867 if (priv->plat->init) {
1868 ret = priv->plat->init(pdev);
1869 if (unlikely(ret))
34a52f36 1870 goto out_free_ndev;
293bb1c4 1871 }
ee7946a7 1872
47dd7a54
GC		 1873 /* MAC HW revice detection */
1874 ret = stmmac_mac_device_setup(ndev);
1875 if (ret < 0)
34a52f36 1876 goto out_plat_exit;
47dd7a54
GC		 1877
1878 /* Network Device Registration */
1879 ret = stmmac_probe(ndev);
1880 if (ret < 0)
34a52f36 1881 goto out_plat_exit;
47dd7a54 1882
36bcfe7d
GC		 1883 /* Override with kernel parameters if supplied XXX CRS XXX
1884 * this needs to have multiple instances */
1885 if ((phyaddr >= 0) && (phyaddr <= 31))
1886 priv->plat->phy_addr = phyaddr;
47dd7a54 1887
47dd7a54 1888 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1f0f6388
DM		 1889 "\tIO base addr: 0x%p)\n", ndev->name, pdev->name,
1890 pdev->id, ndev->irq, addr);
47dd7a54
GC		 1891
1892 /* MDIO bus Registration */
9dfeb4d9 1893 pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id);
47dd7a54
GC		 1894 ret = stmmac_mdio_register(ndev);
1895 if (ret < 0)
34a52f36 1896 goto out_unregister;
47dd7a54 1897 pr_debug("registered!\n");
7ac29055
GC		 1898
1899#ifdef CONFIG_STMMAC_DEBUG_FS
1900 ret = stmmac_init_fs(ndev);
1901 if (ret < 0)
1902 pr_warning("\tFailed debugFS registration");
1903#endif
1904
34a52f36 1905 return 0;
47dd7a54 1906
34a52f36
DC		 1907out_unregister:
1908 unregister_netdev(ndev);
1909out_plat_exit:
1910 if (priv->plat->exit)
1911 priv->plat->exit(pdev);
1912out_free_ndev:
1913 free_netdev(ndev);
1914 platform_set_drvdata(pdev, NULL);
1915out_unmap:
1916 iounmap(addr);
1917out_release_region:
1918 release_mem_region(res->start, resource_size(res));
47dd7a54
GC		 1919
1920 return ret;
1921}
1922
1923/**
1924 * stmmac_dvr_remove
1925 * @pdev: platform device pointer
1926 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1927 * changes the link status, releases the DMA descriptor rings,
1928 * unregisters the MDIO bus and unmaps the allocated memory.
1929 */
1930static int stmmac_dvr_remove(struct platform_device *pdev)
1931{
1932 struct net_device *ndev = platform_get_drvdata(pdev);
aec7ff27 1933 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1934 struct resource *res;
1935
1936 pr_info("%s:\n\tremoving driver", __func__);
1937
ad01b7d4
GC		 1938 priv->hw->dma->stop_rx(priv->ioaddr);
1939 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 1940
19449bfc 1941 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 1942
1943 netif_carrier_off(ndev);
1944
1945 stmmac_mdio_unregister(ndev);
1946
293bb1c4
GC		 1947 if (priv->plat->exit)
1948 priv->plat->exit(pdev);
1949
47dd7a54
GC		 1950 platform_set_drvdata(pdev, NULL);
1951 unregister_netdev(ndev);
1952
ad01b7d4 1953 iounmap((void *)priv->ioaddr);
47dd7a54 1954 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7c5365bc 1955 release_mem_region(res->start, resource_size(res));
47dd7a54 1956
7ac29055
GC		 1957#ifdef CONFIG_STMMAC_DEBUG_FS
1958 stmmac_exit_fs();
1959#endif
1960
47dd7a54
GC		 1961 free_netdev(ndev);
1962
1963 return 0;
1964}
1965
1966#ifdef CONFIG_PM
874bd42d 1967static int stmmac_suspend(struct device *dev)
47dd7a54 1968{
874bd42d
GC		 1969 struct net_device *ndev = dev_get_drvdata(dev);
1970 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1971 int dis_ic = 0;
1972
874bd42d 1973 if (!ndev || !netif_running(ndev))
47dd7a54
GC		 1974 return 0;
1975
1976 spin_lock(&priv->lock);
1977
874bd42d
GC		 1978 netif_device_detach(ndev);
1979 netif_stop_queue(ndev);
1980 if (priv->phydev)
1981 phy_stop(priv->phydev);
47dd7a54
GC		 1982
1983#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 1984 priv->tm->timer_stop();
1985 if (likely(priv->tm->enable))
1986 dis_ic = 1;
47dd7a54 1987#endif
874bd42d
GC		 1988 napi_disable(&priv->napi);
1989
1990 /* Stop TX/RX DMA */
1991 priv->hw->dma->stop_tx(priv->ioaddr);
1992 priv->hw->dma->stop_rx(priv->ioaddr);
1993 /* Clear the Rx/Tx descriptors */
1994 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1995 dis_ic);
1996 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
1997
1998 /* Enable Power down mode by programming the PMT regs */
1999 if (device_may_wakeup(priv->device))
2000 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2001 else
2002 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 2003
2004 spin_unlock(&priv->lock);
2005 return 0;
2006}
2007
874bd42d 2008static int stmmac_resume(struct device *dev)
47dd7a54 2009{
874bd42d
GC		 2010 struct net_device *ndev = dev_get_drvdata(dev);
2011 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54 2012
874bd42d 2013 if (!netif_running(ndev))
47dd7a54
GC		 2014 return 0;
2015
c4433be6
GC		 2016 spin_lock(&priv->lock);
2017
47dd7a54
GC		 2018 /* Power Down bit, into the PM register, is cleared
2019 * automatically as soon as a magic packet or a Wake-up frame
2020 * is received. Anyway, it's better to manually clear
2021 * this bit because it can generate problems while resuming
2022 * from another devices (e.g. serial console). */
874bd42d 2023 if (device_may_wakeup(priv->device))
543876c9 2024 priv->hw->mac->pmt(priv->ioaddr, 0);
47dd7a54 2025
874bd42d 2026 netif_device_attach(ndev);
47dd7a54
GC		 2027
2028 /* Enable the MAC and DMA */
19449bfc 2029 stmmac_enable_mac(priv->ioaddr);
ad01b7d4
GC		 2030 priv->hw->dma->start_tx(priv->ioaddr);
2031 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 2032
2033#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 2034 if (likely(priv->tm->enable))
2035 priv->tm->timer_start(tmrate);
47dd7a54
GC		 2036#endif
2037 napi_enable(&priv->napi);
2038
2039 if (priv->phydev)
2040 phy_start(priv->phydev);
2041
874bd42d 2042 netif_start_queue(ndev);
47dd7a54 2043
47dd7a54
GC		 2044 spin_unlock(&priv->lock);
2045 return 0;
2046}
47dd7a54 2047
874bd42d
GC		 2048static int stmmac_freeze(struct device *dev)
2049{
2050 struct net_device *ndev = dev_get_drvdata(dev);
2051
2052 if (!ndev || !netif_running(ndev))
2053 return 0;
2054
2055 return stmmac_release(ndev);
2056}
2057
2058static int stmmac_restore(struct device *dev)
2059{
2060 struct net_device *ndev = dev_get_drvdata(dev);
2061
2062 if (!ndev || !netif_running(ndev))
2063 return 0;
2064
2065 return stmmac_open(ndev);
2066}
2067
2068static const struct dev_pm_ops stmmac_pm_ops = {
47dd7a54
GC		 2069 .suspend = stmmac_suspend,
2070 .resume = stmmac_resume,
874bd42d
GC		 2071 .freeze = stmmac_freeze,
2072 .thaw = stmmac_restore,
2073 .restore = stmmac_restore,
2074};
2075#else
2076static const struct dev_pm_ops stmmac_pm_ops;
2077#endif /* CONFIG_PM */
47dd7a54 2078
874bd42d
GC		 2079static struct platform_driver stmmac_driver = {
2080 .probe = stmmac_dvr_probe,
2081 .remove = stmmac_dvr_remove,
2082 .driver = {
2083 .name = STMMAC_RESOURCE_NAME,
2084 .owner = THIS_MODULE,
2085 .pm = &stmmac_pm_ops,
2086 },
47dd7a54
GC		 2087};
2088
2089/**
2090 * stmmac_init_module - Entry point for the driver
2091 * Description: This function is the entry point for the driver.
2092 */
2093static int __init stmmac_init_module(void)
2094{
2095 int ret;
2096
47dd7a54
GC		 2097 ret = platform_driver_register(&stmmac_driver);
2098 return ret;
2099}
2100
2101/**
2102 * stmmac_cleanup_module - Cleanup routine for the driver
2103 * Description: This function is the cleanup routine for the driver.
2104 */
2105static void __exit stmmac_cleanup_module(void)
2106{
47dd7a54
GC		 2107 platform_driver_unregister(&stmmac_driver);
2108}
2109
2110#ifndef MODULE
2111static int __init stmmac_cmdline_opt(char *str)
2112{
2113 char *opt;
2114
2115 if (!str || !*str)
2116 return -EINVAL;
2117 while ((opt = strsep(&str, ",")) != NULL) {
f3240e28
GC		 2118 if (!strncmp(opt, "debug:", 6)) {
2119 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug))
2120 goto err;
2121 } else if (!strncmp(opt, "phyaddr:", 8)) {
2122 if (strict_strtoul(opt + 8, 0,
2123 (unsigned long *)&phyaddr))
2124 goto err;
2125 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2126 if (strict_strtoul(opt + 11, 0,
2127 (unsigned long *)&dma_txsize))
2128 goto err;
2129 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2130 if (strict_strtoul(opt + 11, 0,
2131 (unsigned long *)&dma_rxsize))
2132 goto err;
2133 } else if (!strncmp(opt, "buf_sz:", 7)) {
2134 if (strict_strtoul(opt + 7, 0,
2135 (unsigned long *)&buf_sz))
2136 goto err;
2137 } else if (!strncmp(opt, "tc:", 3)) {
2138 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc))
2139 goto err;
2140 } else if (!strncmp(opt, "watchdog:", 9)) {
2141 if (strict_strtoul(opt + 9, 0,
2142 (unsigned long *)&watchdog))
2143 goto err;
2144 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2145 if (strict_strtoul(opt + 10, 0,
2146 (unsigned long *)&flow_ctrl))
2147 goto err;
2148 } else if (!strncmp(opt, "pause:", 6)) {
2149 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause))
2150 goto err;
47dd7a54 2151#ifdef CONFIG_STMMAC_TIMER
f3240e28
GC		 2152 } else if (!strncmp(opt, "tmrate:", 7)) {
2153 if (strict_strtoul(opt + 7, 0,
2154 (unsigned long *)&tmrate))
2155 goto err;
47dd7a54 2156#endif
f3240e28 2157 }
47dd7a54
GC		 2158 }
2159 return 0;
f3240e28
GC		 2160
2161err:
2162 pr_err("%s: ERROR broken module parameter conversion", __func__);
2163 return -EINVAL;
47dd7a54
GC		 2164}
2165
2166__setup("stmmaceth=", stmmac_cmdline_opt);
2167#endif
2168
2169module_init(stmmac_init_module);
2170module_exit(stmmac_cleanup_module);
2171
2172MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
2173MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2174MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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