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47dd7a54 GC |
1 | /******************************************************************************* |
2 | STMMAC Ethernet Driver -- MDIO bus implementation | |
3 | Provides Bus interface for MII registers | |
4 | ||
5 | Copyright (C) 2007-2009 STMicroelectronics Ltd | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Carl Shaw <carl.shaw@st.com> | |
24 | Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
25 | *******************************************************************************/ | |
26 | ||
47dd7a54 GC |
27 | #include <linux/mii.h> |
28 | #include <linux/phy.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
0e076471 SK |
30 | #include <linux/of.h> |
31 | #include <linux/of_gpio.h> | |
e34d6569 | 32 | #include <linux/of_mdio.h> |
b7f080cf | 33 | #include <asm/io.h> |
47dd7a54 GC |
34 | |
35 | #include "stmmac.h" | |
36 | ||
37 | #define MII_BUSY 0x00000001 | |
38 | #define MII_WRITE 0x00000002 | |
39 | ||
39b401db DS |
40 | static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr) |
41 | { | |
42 | unsigned long curr; | |
43 | unsigned long finish = jiffies + 3 * HZ; | |
44 | ||
45 | do { | |
46 | curr = jiffies; | |
47 | if (readl(ioaddr + mii_addr) & MII_BUSY) | |
48 | cpu_relax(); | |
49 | else | |
50 | return 0; | |
51 | } while (!time_after_eq(curr, finish)); | |
52 | ||
53 | return -EBUSY; | |
54 | } | |
55 | ||
47dd7a54 GC |
56 | /** |
57 | * stmmac_mdio_read | |
58 | * @bus: points to the mii_bus structure | |
59 | * @phyaddr: MII addr reg bits 15-11 | |
60 | * @phyreg: MII addr reg bits 10-6 | |
61 | * Description: it reads data from the MII register from within the phy device. | |
62 | * For the 7111 GMAC, we must set the bit 0 in the MII address register while | |
63 | * accessing the PHY registers. | |
64 | * Fortunately, it seems this has no drawback for the 7109 MAC. | |
65 | */ | |
66 | static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) | |
67 | { | |
68 | struct net_device *ndev = bus->priv; | |
69 | struct stmmac_priv *priv = netdev_priv(ndev); | |
db98a0b0 GC |
70 | unsigned int mii_address = priv->hw->mii.addr; |
71 | unsigned int mii_data = priv->hw->mii.data; | |
47dd7a54 GC |
72 | |
73 | int data; | |
74 | u16 regValue = (((phyaddr << 11) & (0x0000F800)) | | |
75 | ((phyreg << 6) & (0x000007C0))); | |
cd7201f4 | 76 | regValue |= MII_BUSY | ((priv->clk_csr & 0xF) << 2); |
47dd7a54 | 77 | |
39b401db DS |
78 | if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) |
79 | return -EBUSY; | |
80 | ||
ad01b7d4 | 81 | writel(regValue, priv->ioaddr + mii_address); |
39b401db DS |
82 | |
83 | if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) | |
84 | return -EBUSY; | |
47dd7a54 GC |
85 | |
86 | /* Read the data from the MII data register */ | |
ad01b7d4 | 87 | data = (int)readl(priv->ioaddr + mii_data); |
47dd7a54 GC |
88 | |
89 | return data; | |
90 | } | |
91 | ||
92 | /** | |
93 | * stmmac_mdio_write | |
94 | * @bus: points to the mii_bus structure | |
95 | * @phyaddr: MII addr reg bits 15-11 | |
96 | * @phyreg: MII addr reg bits 10-6 | |
97 | * @phydata: phy data | |
98 | * Description: it writes the data into the MII register from within the device. | |
99 | */ | |
100 | static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, | |
101 | u16 phydata) | |
102 | { | |
103 | struct net_device *ndev = bus->priv; | |
104 | struct stmmac_priv *priv = netdev_priv(ndev); | |
db98a0b0 GC |
105 | unsigned int mii_address = priv->hw->mii.addr; |
106 | unsigned int mii_data = priv->hw->mii.data; | |
47dd7a54 GC |
107 | |
108 | u16 value = | |
109 | (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))) | |
110 | | MII_WRITE; | |
111 | ||
cd7201f4 | 112 | value |= MII_BUSY | ((priv->clk_csr & 0xF) << 2); |
dfb8fb96 | 113 | |
47dd7a54 | 114 | /* Wait until any existing MII operation is complete */ |
39b401db DS |
115 | if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) |
116 | return -EBUSY; | |
47dd7a54 GC |
117 | |
118 | /* Set the MII address register to write */ | |
ad01b7d4 GC |
119 | writel(phydata, priv->ioaddr + mii_data); |
120 | writel(value, priv->ioaddr + mii_address); | |
47dd7a54 GC |
121 | |
122 | /* Wait until any existing MII operation is complete */ | |
39b401db | 123 | return stmmac_mdio_busy_wait(priv->ioaddr, mii_address); |
47dd7a54 GC |
124 | } |
125 | ||
126 | /** | |
127 | * stmmac_mdio_reset | |
128 | * @bus: points to the mii_bus structure | |
129 | * Description: reset the MII bus | |
130 | */ | |
073752aa | 131 | int stmmac_mdio_reset(struct mii_bus *bus) |
47dd7a54 | 132 | { |
bfab27a1 | 133 | #if defined(CONFIG_STMMAC_PLATFORM) |
47dd7a54 GC |
134 | struct net_device *ndev = bus->priv; |
135 | struct stmmac_priv *priv = netdev_priv(ndev); | |
db98a0b0 | 136 | unsigned int mii_address = priv->hw->mii.addr; |
0e076471 SK |
137 | struct stmmac_mdio_bus_data *data = priv->plat->mdio_bus_data; |
138 | ||
139 | #ifdef CONFIG_OF | |
140 | if (priv->device->of_node) { | |
0e076471 SK |
141 | |
142 | if (data->reset_gpio < 0) { | |
143 | struct device_node *np = priv->device->of_node; | |
144 | if (!np) | |
145 | return 0; | |
146 | ||
147 | data->reset_gpio = of_get_named_gpio(np, | |
148 | "snps,reset-gpio", 0); | |
149 | if (data->reset_gpio < 0) | |
150 | return 0; | |
151 | ||
152 | data->active_low = of_property_read_bool(np, | |
153 | "snps,reset-active-low"); | |
154 | of_property_read_u32_array(np, | |
155 | "snps,reset-delays-us", data->delays, 3); | |
0e076471 | 156 | |
ae26c1c6 GC |
157 | if (gpio_request(data->reset_gpio, "mdio-reset")) |
158 | return 0; | |
159 | } | |
0e076471 | 160 | |
ae26c1c6 GC |
161 | gpio_direction_output(data->reset_gpio, |
162 | data->active_low ? 1 : 0); | |
163 | if (data->delays[0]) | |
164 | msleep(DIV_ROUND_UP(data->delays[0], 1000)); | |
892aa01d | 165 | |
ae26c1c6 GC |
166 | gpio_set_value(data->reset_gpio, data->active_low ? 0 : 1); |
167 | if (data->delays[1]) | |
168 | msleep(DIV_ROUND_UP(data->delays[1], 1000)); | |
892aa01d | 169 | |
ae26c1c6 GC |
170 | gpio_set_value(data->reset_gpio, data->active_low ? 1 : 0); |
171 | if (data->delays[2]) | |
172 | msleep(DIV_ROUND_UP(data->delays[2], 1000)); | |
0e076471 SK |
173 | } |
174 | #endif | |
47dd7a54 | 175 | |
0e076471 | 176 | if (data->phy_reset) { |
47dd7a54 | 177 | pr_debug("stmmac_mdio_reset: calling phy_reset\n"); |
0e076471 | 178 | data->phy_reset(priv->plat->bsp_priv); |
47dd7a54 GC |
179 | } |
180 | ||
181 | /* This is a workaround for problems with the STE101P PHY. | |
182 | * It doesn't complete its reset until at least one clock cycle | |
183 | * on MDC, so perform a dummy mdio read. | |
184 | */ | |
ad01b7d4 | 185 | writel(0, priv->ioaddr + mii_address); |
bfab27a1 | 186 | #endif |
47dd7a54 GC |
187 | return 0; |
188 | } | |
189 | ||
190 | /** | |
191 | * stmmac_mdio_register | |
192 | * @ndev: net device structure | |
193 | * Description: it registers the MII bus | |
194 | */ | |
195 | int stmmac_mdio_register(struct net_device *ndev) | |
196 | { | |
197 | int err = 0; | |
198 | struct mii_bus *new_bus; | |
199 | int *irqlist; | |
200 | struct stmmac_priv *priv = netdev_priv(ndev); | |
36bcfe7d | 201 | struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; |
47dd7a54 | 202 | int addr, found; |
e34d6569 PR |
203 | struct device_node *mdio_node = NULL; |
204 | struct device_node *child_node = NULL; | |
47dd7a54 | 205 | |
36bcfe7d GC |
206 | if (!mdio_bus_data) |
207 | return 0; | |
208 | ||
e34d6569 PR |
209 | if (IS_ENABLED(CONFIG_OF)) { |
210 | for_each_child_of_node(priv->device->of_node, child_node) { | |
211 | if (of_device_is_compatible(child_node, | |
212 | "snps,dwmac-mdio")) { | |
213 | mdio_node = child_node; | |
214 | break; | |
215 | } | |
216 | } | |
217 | ||
218 | if (mdio_node) { | |
219 | netdev_dbg(ndev, "FOUND MDIO subnode\n"); | |
220 | } else { | |
221 | netdev_err(ndev, "NO MDIO subnode\n"); | |
222 | return 0; | |
223 | } | |
224 | } | |
225 | ||
47dd7a54 GC |
226 | new_bus = mdiobus_alloc(); |
227 | if (new_bus == NULL) | |
228 | return -ENOMEM; | |
229 | ||
cc80ee13 | 230 | if (mdio_bus_data->irqs) { |
36bcfe7d | 231 | irqlist = mdio_bus_data->irqs; |
cc80ee13 DN |
232 | } else { |
233 | for (addr = 0; addr < PHY_MAX_ADDR; addr++) | |
234 | priv->mii_irq[addr] = PHY_POLL; | |
36bcfe7d | 235 | irqlist = priv->mii_irq; |
cc80ee13 | 236 | } |
47dd7a54 | 237 | |
0e076471 SK |
238 | #ifdef CONFIG_OF |
239 | if (priv->device->of_node) | |
240 | mdio_bus_data->reset_gpio = -1; | |
241 | #endif | |
242 | ||
90b9a545 | 243 | new_bus->name = "stmmac"; |
47dd7a54 GC |
244 | new_bus->read = &stmmac_mdio_read; |
245 | new_bus->write = &stmmac_mdio_write; | |
246 | new_bus->reset = &stmmac_mdio_reset; | |
db8857bf | 247 | snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
ceb69499 | 248 | new_bus->name, priv->plat->bus_id); |
47dd7a54 GC |
249 | new_bus->priv = ndev; |
250 | new_bus->irq = irqlist; | |
36bcfe7d | 251 | new_bus->phy_mask = mdio_bus_data->phy_mask; |
47dd7a54 | 252 | new_bus->parent = priv->device; |
e34d6569 PR |
253 | |
254 | err = of_mdiobus_register(new_bus, mdio_node); | |
47dd7a54 GC |
255 | if (err != 0) { |
256 | pr_err("%s: Cannot register as MDIO bus\n", new_bus->name); | |
257 | goto bus_register_fail; | |
258 | } | |
259 | ||
47dd7a54 | 260 | found = 0; |
36bcfe7d | 261 | for (addr = 0; addr < PHY_MAX_ADDR; addr++) { |
47dd7a54 GC |
262 | struct phy_device *phydev = new_bus->phy_map[addr]; |
263 | if (phydev) { | |
36bcfe7d GC |
264 | int act = 0; |
265 | char irq_num[4]; | |
266 | char *irq_str; | |
267 | ||
268 | /* | |
269 | * If an IRQ was provided to be assigned after | |
270 | * the bus probe, do it here. | |
271 | */ | |
272 | if ((mdio_bus_data->irqs == NULL) && | |
273 | (mdio_bus_data->probed_phy_irq > 0)) { | |
274 | irqlist[addr] = mdio_bus_data->probed_phy_irq; | |
275 | phydev->irq = mdio_bus_data->probed_phy_irq; | |
47dd7a54 | 276 | } |
36bcfe7d GC |
277 | |
278 | /* | |
a77e4acc | 279 | * If we're going to bind the MAC to this PHY bus, |
36bcfe7d GC |
280 | * and no PHY number was provided to the MAC, |
281 | * use the one probed here. | |
282 | */ | |
d56631a6 | 283 | if (priv->plat->phy_addr == -1) |
36bcfe7d GC |
284 | priv->plat->phy_addr = addr; |
285 | ||
d56631a6 | 286 | act = (priv->plat->phy_addr == addr); |
36bcfe7d GC |
287 | switch (phydev->irq) { |
288 | case PHY_POLL: | |
289 | irq_str = "POLL"; | |
290 | break; | |
291 | case PHY_IGNORE_INTERRUPT: | |
292 | irq_str = "IGNORE"; | |
293 | break; | |
294 | default: | |
295 | sprintf(irq_num, "%d", phydev->irq); | |
296 | irq_str = irq_num; | |
297 | break; | |
298 | } | |
299 | pr_info("%s: PHY ID %08x at %d IRQ %s (%s)%s\n", | |
300 | ndev->name, phydev->phy_id, addr, | |
84eff6d1 | 301 | irq_str, phydev_name(phydev), |
36bcfe7d | 302 | act ? " active" : ""); |
47dd7a54 GC |
303 | found = 1; |
304 | } | |
305 | } | |
306 | ||
e34d6569 | 307 | if (!found && !mdio_node) { |
fe3881cf | 308 | pr_warn("%s: No PHY found\n", ndev->name); |
3955b22b GC |
309 | mdiobus_unregister(new_bus); |
310 | mdiobus_free(new_bus); | |
311 | return -ENODEV; | |
312 | } | |
313 | ||
314 | priv->mii = new_bus; | |
47dd7a54 GC |
315 | |
316 | return 0; | |
36bcfe7d | 317 | |
47dd7a54 | 318 | bus_register_fail: |
36bcfe7d | 319 | mdiobus_free(new_bus); |
47dd7a54 GC |
320 | return err; |
321 | } | |
322 | ||
323 | /** | |
324 | * stmmac_mdio_unregister | |
325 | * @ndev: net device structure | |
326 | * Description: it unregisters the MII bus | |
327 | */ | |
328 | int stmmac_mdio_unregister(struct net_device *ndev) | |
329 | { | |
330 | struct stmmac_priv *priv = netdev_priv(ndev); | |
331 | ||
a5cf5ce9 SK |
332 | if (!priv->mii) |
333 | return 0; | |
334 | ||
47dd7a54 GC |
335 | mdiobus_unregister(priv->mii); |
336 | priv->mii->priv = NULL; | |
36bcfe7d GC |
337 | mdiobus_free(priv->mii); |
338 | priv->mii = NULL; | |
47dd7a54 GC |
339 | |
340 | return 0; | |
341 | } |