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amd/7990: Remove extern from function prototypes
[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
2e5b38ab 27#include <linux/net_tstamp.h>
df828598
M		 28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
f150bd7f 31#include <linux/pm_runtime.h>
2eb32b0a
M		 32#include <linux/of.h>
33#include <linux/of_net.h>
34#include <linux/of_device.h>
3b72c2fe 35#include <linux/if_vlan.h>
df828598 36
739683b4 37#include <linux/pinctrl/consumer.h>
df828598 38
dbe34724 39#include "cpsw.h"
df828598 40#include "cpsw_ale.h"
2e5b38ab 41#include "cpts.h"
df828598
M		 42#include "davinci_cpdma.h"
43
44#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
45 NETIF_MSG_DRV | NETIF_MSG_LINK | \
46 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
47 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
48 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
49 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
50 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
51 NETIF_MSG_RX_STATUS)
52
53#define cpsw_info(priv, type, format, ...) \
54do { \
55 if (netif_msg_##type(priv) && net_ratelimit()) \
56 dev_info(priv->dev, format, ## __VA_ARGS__); \
57} while (0)
58
59#define cpsw_err(priv, type, format, ...) \
60do { \
61 if (netif_msg_##type(priv) && net_ratelimit()) \
62 dev_err(priv->dev, format, ## __VA_ARGS__); \
63} while (0)
64
65#define cpsw_dbg(priv, type, format, ...) \
66do { \
67 if (netif_msg_##type(priv) && net_ratelimit()) \
68 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
69} while (0)
70
71#define cpsw_notice(priv, type, format, ...) \
72do { \
73 if (netif_msg_##type(priv) && net_ratelimit()) \
74 dev_notice(priv->dev, format, ## __VA_ARGS__); \
75} while (0)
76
5c50a856
M		 77#define ALE_ALL_PORTS 0x7
78
df828598
M		 79#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
80#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
81#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
82
e90cfac6
RC		 83#define CPSW_VERSION_1 0x19010a
84#define CPSW_VERSION_2 0x19010c
c193f365 85#define CPSW_VERSION_3 0x19010f
926489be 86#define CPSW_VERSION_4 0x190112
549985ee
RC		 87
88#define HOST_PORT_NUM 0
89#define SLIVER_SIZE 0x40
90
91#define CPSW1_HOST_PORT_OFFSET 0x028
92#define CPSW1_SLAVE_OFFSET 0x050
93#define CPSW1_SLAVE_SIZE 0x040
94#define CPSW1_CPDMA_OFFSET 0x100
95#define CPSW1_STATERAM_OFFSET 0x200
d9718546 96#define CPSW1_HW_STATS 0x400
549985ee
RC		 97#define CPSW1_CPTS_OFFSET 0x500
98#define CPSW1_ALE_OFFSET 0x600
99#define CPSW1_SLIVER_OFFSET 0x700
100
101#define CPSW2_HOST_PORT_OFFSET 0x108
102#define CPSW2_SLAVE_OFFSET 0x200
103#define CPSW2_SLAVE_SIZE 0x100
104#define CPSW2_CPDMA_OFFSET 0x800
d9718546 105#define CPSW2_HW_STATS 0x900
549985ee
RC		 106#define CPSW2_STATERAM_OFFSET 0xa00
107#define CPSW2_CPTS_OFFSET 0xc00
108#define CPSW2_ALE_OFFSET 0xd00
109#define CPSW2_SLIVER_OFFSET 0xd80
110#define CPSW2_BD_OFFSET 0x2000
111
df828598
M		 112#define CPDMA_RXTHRESH 0x0c0
113#define CPDMA_RXFREE 0x0e0
114#define CPDMA_TXHDP 0x00
115#define CPDMA_RXHDP 0x20
116#define CPDMA_TXCP 0x40
117#define CPDMA_RXCP 0x60
118
df828598
M		 119#define CPSW_POLL_WEIGHT 64
120#define CPSW_MIN_PACKET_SIZE 60
121#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
122
123#define RX_PRIORITY_MAPPING 0x76543210
124#define TX_PRIORITY_MAPPING 0x33221100
125#define CPDMA_TX_PRIORITY_MAP 0x76543210
126
3b72c2fe
M		 127#define CPSW_VLAN_AWARE BIT(1)
128#define CPSW_ALE_VLAN_AWARE 1
129
d9ba8f9e
M		 130#define CPSW_FIFO_NORMAL_MODE (0 << 15)
131#define CPSW_FIFO_DUAL_MAC_MODE (1 << 15)
132#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15)
133
ff5b8ef2
M		 134#define CPSW_INTPACEEN (0x3f << 16)
135#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
136#define CPSW_CMINTMAX_CNT 63
137#define CPSW_CMINTMIN_CNT 2
138#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
139#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
140
df828598
M		 141#define cpsw_enable_irq(priv) \
142 do { \
143 u32 i; \
144 for (i = 0; i < priv->num_irqs; i++) \
145 enable_irq(priv->irqs_table[i]); \
146 } while (0);
147#define cpsw_disable_irq(priv) \
148 do { \
149 u32 i; \
150 for (i = 0; i < priv->num_irqs; i++) \
151 disable_irq_nosync(priv->irqs_table[i]); \
152 } while (0);
153
d3bb9c58
M		 154#define cpsw_slave_index(priv) \
155 ((priv->data.dual_emac) ? priv->emac_port : \
156 priv->data.active_slave)
157
df828598
M		 158static int debug_level;
159module_param(debug_level, int, 0);
160MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
161
162static int ale_ageout = 10;
163module_param(ale_ageout, int, 0);
164MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
165
166static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
167module_param(rx_packet_max, int, 0);
168MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
169
996a5c27 170struct cpsw_wr_regs {
df828598
M		 171 u32 id_ver;
172 u32 soft_reset;
173 u32 control;
174 u32 int_control;
175 u32 rx_thresh_en;
176 u32 rx_en;
177 u32 tx_en;
178 u32 misc_en;
ff5b8ef2
M		 179 u32 mem_allign1[8];
180 u32 rx_thresh_stat;
181 u32 rx_stat;
182 u32 tx_stat;
183 u32 misc_stat;
184 u32 mem_allign2[8];
185 u32 rx_imax;
186 u32 tx_imax;
187
df828598
M		 188};
189
996a5c27 190struct cpsw_ss_regs {
df828598
M		 191 u32 id_ver;
192 u32 control;
193 u32 soft_reset;
194 u32 stat_port_en;
195 u32 ptype;
bd357af2
RC		 196 u32 soft_idle;
197 u32 thru_rate;
198 u32 gap_thresh;
199 u32 tx_start_wds;
200 u32 flow_control;
201 u32 vlan_ltype;
202 u32 ts_ltype;
203 u32 dlr_ltype;
df828598
M		 204};
205
9750a3ad
RC		 206/* CPSW_PORT_V1 */
207#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
208#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
209#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
210#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
211#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
212#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
213#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
214#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
215
216/* CPSW_PORT_V2 */
217#define CPSW2_CONTROL 0x00 /* Control Register */
218#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
219#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
220#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
221#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
222#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
223#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
224
225/* CPSW_PORT_V1 and V2 */
226#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
227#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
228#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
229
230/* CPSW_PORT_V2 only */
231#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
232#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
233#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
234#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
235#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
236#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
237#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
238#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
239
240/* Bit definitions for the CPSW2_CONTROL register */
241#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
242#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
243#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
244#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
245#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
246#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
247#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
248#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
249#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
250#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
251#define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */
252#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
253#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
254#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
255#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
256#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
257
258#define CTRL_TS_BITS \
259 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
260 TS_ANNEX_D_EN | TS_LTYPE1_EN)
261
262#define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
263#define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN)
264#define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN)
265
266/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268#define TS_SEQ_ID_OFFSET_MASK (0x3f)
269#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270#define TS_MSG_TYPE_EN_MASK (0xffff)
271
272/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598 274
2e5b38ab
RC		 275/* Bit definitions for the CPSW1_TS_CTL register */
276#define CPSW_V1_TS_RX_EN BIT(0)
277#define CPSW_V1_TS_TX_EN BIT(4)
278#define CPSW_V1_MSG_TYPE_OFS 16
279
280/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
282
df828598
M		 283struct cpsw_host_regs {
284 u32 max_blks;
285 u32 blk_cnt;
d9ba8f9e 286 u32 tx_in_ctl;
df828598
M		 287 u32 port_vlan;
288 u32 tx_pri_map;
289 u32 cpdma_tx_pri_map;
290 u32 cpdma_rx_chan_map;
291};
292
293struct cpsw_sliver_regs {
294 u32 id_ver;
295 u32 mac_control;
296 u32 mac_status;
297 u32 soft_reset;
298 u32 rx_maxlen;
299 u32 __reserved_0;
300 u32 rx_pause;
301 u32 tx_pause;
302 u32 __reserved_1;
303 u32 rx_pri_map;
304};
305
d9718546
M		 306struct cpsw_hw_stats {
307 u32 rxgoodframes;
308 u32 rxbroadcastframes;
309 u32 rxmulticastframes;
310 u32 rxpauseframes;
311 u32 rxcrcerrors;
312 u32 rxaligncodeerrors;
313 u32 rxoversizedframes;
314 u32 rxjabberframes;
315 u32 rxundersizedframes;
316 u32 rxfragments;
317 u32 __pad_0[2];
318 u32 rxoctets;
319 u32 txgoodframes;
320 u32 txbroadcastframes;
321 u32 txmulticastframes;
322 u32 txpauseframes;
323 u32 txdeferredframes;
324 u32 txcollisionframes;
325 u32 txsinglecollframes;
326 u32 txmultcollframes;
327 u32 txexcessivecollisions;
328 u32 txlatecollisions;
329 u32 txunderrun;
330 u32 txcarriersenseerrors;
331 u32 txoctets;
332 u32 octetframes64;
333 u32 octetframes65t127;
334 u32 octetframes128t255;
335 u32 octetframes256t511;
336 u32 octetframes512t1023;
337 u32 octetframes1024tup;
338 u32 netoctets;
339 u32 rxsofoverruns;
340 u32 rxmofoverruns;
341 u32 rxdmaoverruns;
342};
343
df828598 344struct cpsw_slave {
9750a3ad 345 void __iomem *regs;
df828598
M		 346 struct cpsw_sliver_regs __iomem *sliver;
347 int slave_num;
348 u32 mac_control;
349 struct cpsw_slave_data *data;
350 struct phy_device *phy;
d9ba8f9e
M		 351 struct net_device *ndev;
352 u32 port_vlan;
353 u32 open_stat;
df828598
M		 354};
355
9750a3ad
RC		 356static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
357{
358 return __raw_readl(slave->regs + offset);
359}
360
361static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
362{
363 __raw_writel(val, slave->regs + offset);
364}
365
df828598
M		 366struct cpsw_priv {
367 spinlock_t lock;
368 struct platform_device *pdev;
369 struct net_device *ndev;
370 struct resource *cpsw_res;
a65dd5b2 371 struct resource *cpsw_wr_res;
df828598
M		 372 struct napi_struct napi;
373 struct device *dev;
374 struct cpsw_platform_data data;
996a5c27
RC		 375 struct cpsw_ss_regs __iomem *regs;
376 struct cpsw_wr_regs __iomem *wr_regs;
d9718546 377 u8 __iomem *hw_stats;
df828598
M		 378 struct cpsw_host_regs __iomem *host_port_regs;
379 u32 msg_enable;
e90cfac6 380 u32 version;
ff5b8ef2
M		 381 u32 coal_intvl;
382 u32 bus_freq_mhz;
df828598
M		 383 struct net_device_stats stats;
384 int rx_packet_max;
385 int host_port;
386 struct clk *clk;
387 u8 mac_addr[ETH_ALEN];
388 struct cpsw_slave *slaves;
389 struct cpdma_ctlr *dma;
390 struct cpdma_chan *txch, *rxch;
391 struct cpsw_ale *ale;
392 /* snapshot of IRQ numbers */
393 u32 irqs_table[4];
394 u32 num_irqs;
a11fbba9 395 bool irq_enabled;
9232b16d 396 struct cpts *cpts;
d9ba8f9e 397 u32 emac_port;
df828598
M		 398};
399
d9718546
M		 400struct cpsw_stats {
401 char stat_string[ETH_GSTRING_LEN];
402 int type;
403 int sizeof_stat;
404 int stat_offset;
405};
406
407enum {
408 CPSW_STATS,
409 CPDMA_RX_STATS,
410 CPDMA_TX_STATS,
411};
412
413#define CPSW_STAT(m) CPSW_STATS, \
414 sizeof(((struct cpsw_hw_stats *)0)->m), \
415 offsetof(struct cpsw_hw_stats, m)
416#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
417 sizeof(((struct cpdma_chan_stats *)0)->m), \
418 offsetof(struct cpdma_chan_stats, m)
419#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
420 sizeof(((struct cpdma_chan_stats *)0)->m), \
421 offsetof(struct cpdma_chan_stats, m)
422
423static const struct cpsw_stats cpsw_gstrings_stats[] = {
424 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
425 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
426 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
427 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
428 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
429 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
430 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
431 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
432 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
433 { "Rx Fragments", CPSW_STAT(rxfragments) },
434 { "Rx Octets", CPSW_STAT(rxoctets) },
435 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
436 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
437 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
438 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
439 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
440 { "Collisions", CPSW_STAT(txcollisionframes) },
441 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
442 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
443 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
444 { "Late Collisions", CPSW_STAT(txlatecollisions) },
445 { "Tx Underrun", CPSW_STAT(txunderrun) },
446 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
447 { "Tx Octets", CPSW_STAT(txoctets) },
448 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
449 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
450 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
451 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
452 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
453 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
454 { "Net Octets", CPSW_STAT(netoctets) },
455 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
456 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
457 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
458 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
459 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
460 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
461 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
462 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
463 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
464 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
465 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
466 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
467 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
468 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
469 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
470 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
471 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
472 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
473 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
474 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
475 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
476 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
477 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
478 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
479 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
480 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
481 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
482 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
483 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
484};
485
486#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
487
df828598 488#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
d9ba8f9e
M		 489#define for_each_slave(priv, func, arg...) \
490 do { \
6e6ceaed
SS		 491 struct cpsw_slave *slave; \
492 int n; \
d9ba8f9e
M		 493 if (priv->data.dual_emac) \
494 (func)((priv)->slaves + priv->emac_port, ##arg);\
495 else \
6e6ceaed
SS		 496 for (n = (priv)->data.slaves, \
497 slave = (priv)->slaves; \
498 n; n--) \
499 (func)(slave++, ##arg); \
d9ba8f9e
M		 500 } while (0)
501#define cpsw_get_slave_ndev(priv, __slave_no__) \
502 (priv->slaves[__slave_no__].ndev)
503#define cpsw_get_slave_priv(priv, __slave_no__) \
504 ((priv->slaves[__slave_no__].ndev) ? \
505 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
506
507#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
508 do { \
509 if (!priv->data.dual_emac) \
510 break; \
511 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
512 ndev = cpsw_get_slave_ndev(priv, 0); \
513 priv = netdev_priv(ndev); \
514 skb->dev = ndev; \
515 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
516 ndev = cpsw_get_slave_ndev(priv, 1); \
517 priv = netdev_priv(ndev); \
518 skb->dev = ndev; \
519 } \
df828598 520 } while (0)
d9ba8f9e
M		 521#define cpsw_add_mcast(priv, addr) \
522 do { \
523 if (priv->data.dual_emac) { \
524 struct cpsw_slave *slave = priv->slaves + \
525 priv->emac_port; \
526 int slave_port = cpsw_get_slave_port(priv, \
527 slave->slave_num); \
528 cpsw_ale_add_mcast(priv->ale, addr, \
529 1 << slave_port | 1 << priv->host_port, \
530 ALE_VLAN, slave->port_vlan, 0); \
531 } else { \
532 cpsw_ale_add_mcast(priv->ale, addr, \
533 ALE_ALL_PORTS << priv->host_port, \
534 0, 0, 0); \
535 } \
536 } while (0)
537
538static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
539{
540 if (priv->host_port == 0)
541 return slave_num + 1;
542 else
543 return slave_num;
544}
df828598 545
5c50a856
M		 546static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
547{
548 struct cpsw_priv *priv = netdev_priv(ndev);
549
550 if (ndev->flags & IFF_PROMISC) {
551 /* Enable promiscuous mode */
552 dev_err(priv->dev, "Ignoring Promiscuous mode\n");
553 return;
554 }
555
556 /* Clear all mcast from ALE */
557 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
558
559 if (!netdev_mc_empty(ndev)) {
560 struct netdev_hw_addr *ha;
561
562 /* program multicast address list into ALE register */
563 netdev_for_each_mc_addr(ha, ndev) {
d9ba8f9e 564 cpsw_add_mcast(priv, (u8 *)ha->addr);
5c50a856
M		 565 }
566 }
567}
568
df828598
M		 569static void cpsw_intr_enable(struct cpsw_priv *priv)
570{
996a5c27
RC		 571 __raw_writel(0xFF, &priv->wr_regs->tx_en);
572 __raw_writel(0xFF, &priv->wr_regs->rx_en);
df828598
M		 573
574 cpdma_ctlr_int_ctrl(priv->dma, true);
575 return;
576}
577
578static void cpsw_intr_disable(struct cpsw_priv *priv)
579{
996a5c27
RC		 580 __raw_writel(0, &priv->wr_regs->tx_en);
581 __raw_writel(0, &priv->wr_regs->rx_en);
df828598
M		 582
583 cpdma_ctlr_int_ctrl(priv->dma, false);
584 return;
585}
586
587void cpsw_tx_handler(void *token, int len, int status)
588{
589 struct sk_buff *skb = token;
590 struct net_device *ndev = skb->dev;
591 struct cpsw_priv *priv = netdev_priv(ndev);
592
fae50823
M		 593 /* Check whether the queue is stopped due to stalled tx dma, if the
594 * queue is stopped then start the queue as we have free desc for tx
595 */
df828598 596 if (unlikely(netif_queue_stopped(ndev)))
b56d6b3f 597 netif_wake_queue(ndev);
9232b16d 598 cpts_tx_timestamp(priv->cpts, skb);
df828598
M		 599 priv->stats.tx_packets++;
600 priv->stats.tx_bytes += len;
601 dev_kfree_skb_any(skb);
602}
603
604void cpsw_rx_handler(void *token, int len, int status)
605{
606 struct sk_buff *skb = token;
b4727e69 607 struct sk_buff *new_skb;
df828598
M		 608 struct net_device *ndev = skb->dev;
609 struct cpsw_priv *priv = netdev_priv(ndev);
610 int ret = 0;
611
d9ba8f9e
M		 612 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
613
b4727e69
SS		 614 if (unlikely(status < 0)) {
615 /* the interface is going down, skbs are purged */
df828598
M		 616 dev_kfree_skb_any(skb);
617 return;
618 }
b4727e69
SS		 619
620 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
621 if (new_skb) {
df828598 622 skb_put(skb, len);
9232b16d 623 cpts_rx_timestamp(priv->cpts, skb);
df828598
M		 624 skb->protocol = eth_type_trans(skb, ndev);
625 netif_receive_skb(skb);
626 priv->stats.rx_bytes += len;
627 priv->stats.rx_packets++;
b4727e69
SS		 628 } else {
629 priv->stats.rx_dropped++;
630 new_skb = skb;
df828598
M		 631 }
632
b4727e69
SS		 633 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
634 skb_tailroom(new_skb), 0);
635 if (WARN_ON(ret < 0))
636 dev_kfree_skb_any(new_skb);
df828598
M		 637}
638
639static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
640{
641 struct cpsw_priv *priv = dev_id;
fd51cf19 642 u32 rx, tx, rx_thresh;
df828598 643
fd51cf19
SS		 644 rx_thresh = __raw_readl(&priv->wr_regs->rx_thresh_stat);
645 rx = __raw_readl(&priv->wr_regs->rx_stat);
646 tx = __raw_readl(&priv->wr_regs->tx_stat);
647 if (!rx_thresh && !rx && !tx)
648 return IRQ_NONE;
649
650 cpsw_intr_disable(priv);
a11fbba9
SS		 651 if (priv->irq_enabled == true) {
652 cpsw_disable_irq(priv);
653 priv->irq_enabled = false;
654 }
fd51cf19
SS		 655
656 if (netif_running(priv->ndev)) {
df828598 657 napi_schedule(&priv->napi);
fd51cf19
SS		 658 return IRQ_HANDLED;
659 }
660
661 priv = cpsw_get_slave_priv(priv, 1);
662 if (!priv)
663 return IRQ_NONE;
664
665 if (netif_running(priv->ndev)) {
666 napi_schedule(&priv->napi);
667 return IRQ_HANDLED;
df828598 668 }
fd51cf19 669 return IRQ_NONE;
df828598
M		 670}
671
df828598
M		 672static int cpsw_poll(struct napi_struct *napi, int budget)
673{
674 struct cpsw_priv *priv = napi_to_priv(napi);
675 int num_tx, num_rx;
676
677 num_tx = cpdma_chan_process(priv->txch, 128);
510a1e72
M		 678 if (num_tx)
679 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
df828598 680
510a1e72 681 num_rx = cpdma_chan_process(priv->rxch, budget);
df828598 682 if (num_rx < budget) {
a11fbba9
SS		 683 struct cpsw_priv *prim_cpsw;
684
df828598
M		 685 napi_complete(napi);
686 cpsw_intr_enable(priv);
510a1e72 687 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
a11fbba9
SS		 688 prim_cpsw = cpsw_get_slave_priv(priv, 0);
689 if (prim_cpsw->irq_enabled == false) {
a11fbba9 690 prim_cpsw->irq_enabled = true;
af5c6df7 691 cpsw_enable_irq(priv);
a11fbba9 692 }
df828598
M		 693 }
694
510a1e72
M		 695 if (num_rx || num_tx)
696 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
697 num_rx, num_tx);
698
df828598
M		 699 return num_rx;
700}
701
702static inline void soft_reset(const char *module, void __iomem *reg)
703{
704 unsigned long timeout = jiffies + HZ;
705
706 __raw_writel(1, reg);
707 do {
708 cpu_relax();
709 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
710
711 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
712}
713
714#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
715 ((mac)[2] << 16) | ((mac)[3] << 24))
716#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
717
718static void cpsw_set_slave_mac(struct cpsw_slave *slave,
719 struct cpsw_priv *priv)
720{
9750a3ad
RC		 721 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
722 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 723}
724
725static void _cpsw_adjust_link(struct cpsw_slave *slave,
726 struct cpsw_priv *priv, bool *link)
727{
728 struct phy_device *phy = slave->phy;
729 u32 mac_control = 0;
730 u32 slave_port;
731
732 if (!phy)
733 return;
734
735 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
736
737 if (phy->link) {
738 mac_control = priv->data.mac_control;
739
740 /* enable forwarding */
741 cpsw_ale_control_set(priv->ale, slave_port,
742 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
743
744 if (phy->speed == 1000)
745 mac_control |= BIT(7); /* GIGABITEN */
746 if (phy->duplex)
747 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 748
749 /* set speed_in input in case RMII mode is used in 100Mbps */
750 if (phy->speed == 100)
751 mac_control |= BIT(15);
752
df828598
M		 753 *link = true;
754 } else {
755 mac_control = 0;
756 /* disable forwarding */
757 cpsw_ale_control_set(priv->ale, slave_port,
758 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
759 }
760
761 if (mac_control != slave->mac_control) {
762 phy_print_status(phy);
763 __raw_writel(mac_control, &slave->sliver->mac_control);
764 }
765
766 slave->mac_control = mac_control;
767}
768
769static void cpsw_adjust_link(struct net_device *ndev)
770{
771 struct cpsw_priv *priv = netdev_priv(ndev);
772 bool link = false;
773
774 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
775
776 if (link) {
777 netif_carrier_on(ndev);
778 if (netif_running(ndev))
779 netif_wake_queue(ndev);
780 } else {
781 netif_carrier_off(ndev);
782 netif_stop_queue(ndev);
783 }
784}
785
ff5b8ef2
M		 786static int cpsw_get_coalesce(struct net_device *ndev,
787 struct ethtool_coalesce *coal)
788{
789 struct cpsw_priv *priv = netdev_priv(ndev);
790
791 coal->rx_coalesce_usecs = priv->coal_intvl;
792 return 0;
793}
794
795static int cpsw_set_coalesce(struct net_device *ndev,
796 struct ethtool_coalesce *coal)
797{
798 struct cpsw_priv *priv = netdev_priv(ndev);
799 u32 int_ctrl;
800 u32 num_interrupts = 0;
801 u32 prescale = 0;
802 u32 addnl_dvdr = 1;
803 u32 coal_intvl = 0;
804
805 if (!coal->rx_coalesce_usecs)
806 return -EINVAL;
807
808 coal_intvl = coal->rx_coalesce_usecs;
809
810 int_ctrl = readl(&priv->wr_regs->int_control);
811 prescale = priv->bus_freq_mhz * 4;
812
813 if (coal_intvl < CPSW_CMINTMIN_INTVL)
814 coal_intvl = CPSW_CMINTMIN_INTVL;
815
816 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
817 /* Interrupt pacer works with 4us Pulse, we can
818 * throttle further by dilating the 4us pulse.
819 */
820 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
821
822 if (addnl_dvdr > 1) {
823 prescale *= addnl_dvdr;
824 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
825 coal_intvl = (CPSW_CMINTMAX_INTVL
826 * addnl_dvdr);
827 } else {
828 addnl_dvdr = 1;
829 coal_intvl = CPSW_CMINTMAX_INTVL;
830 }
831 }
832
833 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
834 writel(num_interrupts, &priv->wr_regs->rx_imax);
835 writel(num_interrupts, &priv->wr_regs->tx_imax);
836
837 int_ctrl |= CPSW_INTPACEEN;
838 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
839 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
840 writel(int_ctrl, &priv->wr_regs->int_control);
841
842 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
843 if (priv->data.dual_emac) {
844 int i;
845
846 for (i = 0; i < priv->data.slaves; i++) {
847 priv = netdev_priv(priv->slaves[i].ndev);
848 priv->coal_intvl = coal_intvl;
849 }
850 } else {
851 priv->coal_intvl = coal_intvl;
852 }
853
854 return 0;
855}
856
d9718546
M		 857static int cpsw_get_sset_count(struct net_device *ndev, int sset)
858{
859 switch (sset) {
860 case ETH_SS_STATS:
861 return CPSW_STATS_LEN;
862 default:
863 return -EOPNOTSUPP;
864 }
865}
866
867static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
868{
869 u8 *p = data;
870 int i;
871
872 switch (stringset) {
873 case ETH_SS_STATS:
874 for (i = 0; i < CPSW_STATS_LEN; i++) {
875 memcpy(p, cpsw_gstrings_stats[i].stat_string,
876 ETH_GSTRING_LEN);
877 p += ETH_GSTRING_LEN;
878 }
879 break;
880 }
881}
882
883static void cpsw_get_ethtool_stats(struct net_device *ndev,
884 struct ethtool_stats *stats, u64 *data)
885{
886 struct cpsw_priv *priv = netdev_priv(ndev);
887 struct cpdma_chan_stats rx_stats;
888 struct cpdma_chan_stats tx_stats;
889 u32 val;
890 u8 *p;
891 int i;
892
893 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
894 cpdma_chan_get_stats(priv->rxch, &rx_stats);
895 cpdma_chan_get_stats(priv->txch, &tx_stats);
896
897 for (i = 0; i < CPSW_STATS_LEN; i++) {
898 switch (cpsw_gstrings_stats[i].type) {
899 case CPSW_STATS:
900 val = readl(priv->hw_stats +
901 cpsw_gstrings_stats[i].stat_offset);
902 data[i] = val;
903 break;
904
905 case CPDMA_RX_STATS:
906 p = (u8 *)&rx_stats +
907 cpsw_gstrings_stats[i].stat_offset;
908 data[i] = *(u32 *)p;
909 break;
910
911 case CPDMA_TX_STATS:
912 p = (u8 *)&tx_stats +
913 cpsw_gstrings_stats[i].stat_offset;
914 data[i] = *(u32 *)p;
915 break;
916 }
917 }
918}
919
df828598
M		 920static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
921{
922 static char *leader = "........................................";
923
924 if (!val)
925 return 0;
926 else
927 return snprintf(buf, maxlen, "%s %s %10d\n", name,
928 leader + strlen(name), val);
929}
930
d9ba8f9e
M		 931static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
932{
933 u32 i;
934 u32 usage_count = 0;
935
936 if (!priv->data.dual_emac)
937 return 0;
938
939 for (i = 0; i < priv->data.slaves; i++)
940 if (priv->slaves[i].open_stat)
941 usage_count++;
942
943 return usage_count;
944}
945
946static inline int cpsw_tx_packet_submit(struct net_device *ndev,
947 struct cpsw_priv *priv, struct sk_buff *skb)
948{
949 if (!priv->data.dual_emac)
950 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 951 skb->len, 0);
d9ba8f9e
M		 952
953 if (ndev == cpsw_get_slave_ndev(priv, 0))
954 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 955 skb->len, 1);
d9ba8f9e
M		 956 else
957 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 958 skb->len, 2);
d9ba8f9e
M		 959}
960
961static inline void cpsw_add_dual_emac_def_ale_entries(
962 struct cpsw_priv *priv, struct cpsw_slave *slave,
963 u32 slave_port)
964{
965 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
966
967 if (priv->version == CPSW_VERSION_1)
968 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
969 else
970 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
971 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
972 port_mask, port_mask, 0);
973 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
974 port_mask, ALE_VLAN, slave->port_vlan, 0);
975 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
976 priv->host_port, ALE_VLAN, slave->port_vlan);
977}
978
df828598
M		 979static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
980{
981 char name[32];
982 u32 slave_port;
983
984 sprintf(name, "slave-%d", slave->slave_num);
985
986 soft_reset(name, &slave->sliver->soft_reset);
987
988 /* setup priority mapping */
989 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad
RC		 990
991 switch (priv->version) {
992 case CPSW_VERSION_1:
993 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
994 break;
995 case CPSW_VERSION_2:
c193f365 996 case CPSW_VERSION_3:
926489be 997 case CPSW_VERSION_4:
9750a3ad
RC		 998 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
999 break;
1000 }
df828598
M		 1001
1002 /* setup max packet size, and mac address */
1003 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1004 cpsw_set_slave_mac(slave, priv);
1005
1006 slave->mac_control = 0; /* no link yet */
1007
1008 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1009
d9ba8f9e
M		 1010 if (priv->data.dual_emac)
1011 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1012 else
1013 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1014 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
df828598
M		 1015
1016 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
f9a8f83b 1017 &cpsw_adjust_link, slave->data->phy_if);
df828598
M		 1018 if (IS_ERR(slave->phy)) {
1019 dev_err(priv->dev, "phy %s not found on slave %d\n",
1020 slave->data->phy_id, slave->slave_num);
1021 slave->phy = NULL;
1022 } else {
1023 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1024 slave->phy->phy_id);
1025 phy_start(slave->phy);
1026 }
1027}
1028
3b72c2fe
M		 1029static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1030{
1031 const int vlan = priv->data.default_vlan;
1032 const int port = priv->host_port;
1033 u32 reg;
1034 int i;
1035
1036 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1037 CPSW2_PORT_VLAN;
1038
1039 writel(vlan, &priv->host_port_regs->port_vlan);
1040
0237c110 1041 for (i = 0; i < priv->data.slaves; i++)
3b72c2fe
M		 1042 slave_write(priv->slaves + i, vlan, reg);
1043
1044 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1045 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1046 (ALE_PORT_1 | ALE_PORT_2) << port);
1047}
1048
df828598
M		 1049static void cpsw_init_host_port(struct cpsw_priv *priv)
1050{
3b72c2fe 1051 u32 control_reg;
d9ba8f9e 1052 u32 fifo_mode;
3b72c2fe 1053
df828598
M		 1054 /* soft reset the controller and initialize ale */
1055 soft_reset("cpsw", &priv->regs->soft_reset);
1056 cpsw_ale_start(priv->ale);
1057
1058 /* switch to vlan unaware mode */
3b72c2fe
M		 1059 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1060 CPSW_ALE_VLAN_AWARE);
1061 control_reg = readl(&priv->regs->control);
1062 control_reg |= CPSW_VLAN_AWARE;
1063 writel(control_reg, &priv->regs->control);
d9ba8f9e
M		 1064 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1065 CPSW_FIFO_NORMAL_MODE;
1066 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
df828598
M		 1067
1068 /* setup host port priority mapping */
1069 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1070 &priv->host_port_regs->cpdma_tx_pri_map);
1071 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1072
1073 cpsw_ale_control_set(priv->ale, priv->host_port,
1074 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1075
d9ba8f9e
M		 1076 if (!priv->data.dual_emac) {
1077 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1078 0, 0);
1079 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1080 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1081 }
df828598
M		 1082}
1083
aacebbf8
SS		 1084static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1085{
1086 if (!slave->phy)
1087 return;
1088 phy_stop(slave->phy);
1089 phy_disconnect(slave->phy);
1090 slave->phy = NULL;
1091}
1092
df828598
M		 1093static int cpsw_ndo_open(struct net_device *ndev)
1094{
1095 struct cpsw_priv *priv = netdev_priv(ndev);
a11fbba9 1096 struct cpsw_priv *prim_cpsw;
df828598
M		 1097 int i, ret;
1098 u32 reg;
1099
d9ba8f9e
M		 1100 if (!cpsw_common_res_usage_state(priv))
1101 cpsw_intr_disable(priv);
df828598
M		 1102 netif_carrier_off(ndev);
1103
f150bd7f 1104 pm_runtime_get_sync(&priv->pdev->dev);
df828598 1105
549985ee 1106 reg = priv->version;
df828598
M		 1107
1108 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1109 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1110 CPSW_RTL_VERSION(reg));
1111
1112 /* initialize host and slave ports */
d9ba8f9e
M		 1113 if (!cpsw_common_res_usage_state(priv))
1114 cpsw_init_host_port(priv);
df828598
M		 1115 for_each_slave(priv, cpsw_slave_open, priv);
1116
3b72c2fe 1117 /* Add default VLAN */
d9ba8f9e
M		 1118 if (!priv->data.dual_emac)
1119 cpsw_add_default_vlan(priv);
3b72c2fe 1120
d9ba8f9e
M		 1121 if (!cpsw_common_res_usage_state(priv)) {
1122 /* setup tx dma to fixed prio and zero offset */
1123 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1124 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
df828598 1125
d9ba8f9e
M		 1126 /* disable priority elevation */
1127 __raw_writel(0, &priv->regs->ptype);
df828598 1128
d9ba8f9e
M		 1129 /* enable statistics collection only on all ports */
1130 __raw_writel(0x7, &priv->regs->stat_port_en);
df828598 1131
d9ba8f9e
M		 1132 if (WARN_ON(!priv->data.rx_descs))
1133 priv->data.rx_descs = 128;
df828598 1134
d9ba8f9e
M		 1135 for (i = 0; i < priv->data.rx_descs; i++) {
1136 struct sk_buff *skb;
df828598 1137
d9ba8f9e 1138 ret = -ENOMEM;
aacebbf8
SS		 1139 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1140 priv->rx_packet_max, GFP_KERNEL);
d9ba8f9e 1141 if (!skb)
aacebbf8 1142 goto err_cleanup;
d9ba8f9e 1143 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
aef614e1 1144 skb_tailroom(skb), 0);
aacebbf8
SS		 1145 if (ret < 0) {
1146 kfree_skb(skb);
1147 goto err_cleanup;
1148 }
d9ba8f9e
M		 1149 }
1150 /* continue even if we didn't manage to submit all
1151 * receive descs
1152 */
1153 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
df828598 1154 }
df828598 1155
ff5b8ef2
M		 1156 /* Enable Interrupt pacing if configured */
1157 if (priv->coal_intvl != 0) {
1158 struct ethtool_coalesce coal;
1159
1160 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1161 cpsw_set_coalesce(ndev, &coal);
1162 }
1163
a11fbba9
SS		 1164 prim_cpsw = cpsw_get_slave_priv(priv, 0);
1165 if (prim_cpsw->irq_enabled == false) {
1166 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1167 prim_cpsw->irq_enabled = true;
1168 cpsw_enable_irq(prim_cpsw);
1169 }
1170 }
1171
df828598
M		 1172 cpdma_ctlr_start(priv->dma);
1173 cpsw_intr_enable(priv);
1174 napi_enable(&priv->napi);
510a1e72
M		 1175 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1176 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
df828598 1177
d9ba8f9e
M		 1178 if (priv->data.dual_emac)
1179 priv->slaves[priv->emac_port].open_stat = true;
df828598 1180 return 0;
df828598 1181
aacebbf8
SS		 1182err_cleanup:
1183 cpdma_ctlr_stop(priv->dma);
1184 for_each_slave(priv, cpsw_slave_stop, priv);
1185 pm_runtime_put_sync(&priv->pdev->dev);
1186 netif_carrier_off(priv->ndev);
1187 return ret;
df828598
M		 1188}
1189
1190static int cpsw_ndo_stop(struct net_device *ndev)
1191{
1192 struct cpsw_priv *priv = netdev_priv(ndev);
1193
1194 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
df828598
M		 1195 netif_stop_queue(priv->ndev);
1196 napi_disable(&priv->napi);
1197 netif_carrier_off(priv->ndev);
d9ba8f9e
M		 1198
1199 if (cpsw_common_res_usage_state(priv) <= 1) {
1200 cpsw_intr_disable(priv);
1201 cpdma_ctlr_int_ctrl(priv->dma, false);
1202 cpdma_ctlr_stop(priv->dma);
1203 cpsw_ale_stop(priv->ale);
1204 }
df828598 1205 for_each_slave(priv, cpsw_slave_stop, priv);
f150bd7f 1206 pm_runtime_put_sync(&priv->pdev->dev);
d9ba8f9e
M		 1207 if (priv->data.dual_emac)
1208 priv->slaves[priv->emac_port].open_stat = false;
df828598
M		 1209 return 0;
1210}
1211
1212static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1213 struct net_device *ndev)
1214{
1215 struct cpsw_priv *priv = netdev_priv(ndev);
1216 int ret;
1217
1218 ndev->trans_start = jiffies;
1219
1220 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1221 cpsw_err(priv, tx_err, "packet pad failed\n");
1222 priv->stats.tx_dropped++;
1223 return NETDEV_TX_OK;
1224 }
1225
9232b16d
M		 1226 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1227 priv->cpts->tx_enable)
2e5b38ab
RC		 1228 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1229
1230 skb_tx_timestamp(skb);
1231
d9ba8f9e 1232 ret = cpsw_tx_packet_submit(ndev, priv, skb);
df828598
M		 1233 if (unlikely(ret != 0)) {
1234 cpsw_err(priv, tx_err, "desc submit failed\n");
1235 goto fail;
1236 }
1237
fae50823
M		 1238 /* If there is no more tx desc left free then we need to
1239 * tell the kernel to stop sending us tx frames.
1240 */
d35162f8 1241 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
fae50823
M		 1242 netif_stop_queue(ndev);
1243
df828598
M		 1244 return NETDEV_TX_OK;
1245fail:
1246 priv->stats.tx_dropped++;
1247 netif_stop_queue(ndev);
1248 return NETDEV_TX_BUSY;
1249}
1250
1251static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
1252{
1253 /*
1254 * The switch cannot operate in promiscuous mode without substantial
1255 * headache. For promiscuous mode to work, we would need to put the
1256 * ALE in bypass mode and route all traffic to the host port.
1257 * Subsequently, the host will need to operate as a "bridge", learn,
1258 * and flood as needed. For now, we simply complain here and
1259 * do nothing about it :-)
1260 */
1261 if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
1262 dev_err(&ndev->dev, "promiscuity ignored!\n");
1263
1264 /*
1265 * The switch cannot filter multicast traffic unless it is configured
1266 * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a
1267 * whole bunch of additional logic that this driver does not implement
1268 * at present.
1269 */
1270 if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
1271 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
1272}
1273
2e5b38ab
RC		 1274#ifdef CONFIG_TI_CPTS
1275
1276static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1277{
e86ac13b 1278 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
2e5b38ab
RC		 1279 u32 ts_en, seq_id;
1280
9232b16d 1281 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
2e5b38ab
RC		 1282 slave_write(slave, 0, CPSW1_TS_CTL);
1283 return;
1284 }
1285
1286 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1287 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1288
9232b16d 1289 if (priv->cpts->tx_enable)
2e5b38ab
RC		 1290 ts_en |= CPSW_V1_TS_TX_EN;
1291
9232b16d 1292 if (priv->cpts->rx_enable)
2e5b38ab
RC		 1293 ts_en |= CPSW_V1_TS_RX_EN;
1294
1295 slave_write(slave, ts_en, CPSW1_TS_CTL);
1296 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1297}
1298
1299static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1300{
d9ba8f9e 1301 struct cpsw_slave *slave;
2e5b38ab
RC		 1302 u32 ctrl, mtype;
1303
d9ba8f9e
M		 1304 if (priv->data.dual_emac)
1305 slave = &priv->slaves[priv->emac_port];
1306 else
e86ac13b 1307 slave = &priv->slaves[priv->data.active_slave];
d9ba8f9e 1308
2e5b38ab
RC		 1309 ctrl = slave_read(slave, CPSW2_CONTROL);
1310 ctrl &= ~CTRL_ALL_TS_MASK;
1311
9232b16d 1312 if (priv->cpts->tx_enable)
2e5b38ab
RC		 1313 ctrl |= CTRL_TX_TS_BITS;
1314
9232b16d 1315 if (priv->cpts->rx_enable)
2e5b38ab
RC		 1316 ctrl |= CTRL_RX_TS_BITS;
1317
1318 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1319
1320 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1321 slave_write(slave, ctrl, CPSW2_CONTROL);
1322 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1323}
1324
3177bf6f 1325static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
2e5b38ab 1326{
3177bf6f 1327 struct cpsw_priv *priv = netdev_priv(dev);
9232b16d 1328 struct cpts *cpts = priv->cpts;
2e5b38ab
RC		 1329 struct hwtstamp_config cfg;
1330
1331 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1332 return -EFAULT;
1333
1334 /* reserved for future extensions */
1335 if (cfg.flags)
1336 return -EINVAL;
1337
1338 switch (cfg.tx_type) {
1339 case HWTSTAMP_TX_OFF:
1340 cpts->tx_enable = 0;
1341 break;
1342 case HWTSTAMP_TX_ON:
1343 cpts->tx_enable = 1;
1344 break;
1345 default:
1346 return -ERANGE;
1347 }
1348
1349 switch (cfg.rx_filter) {
1350 case HWTSTAMP_FILTER_NONE:
1351 cpts->rx_enable = 0;
1352 break;
1353 case HWTSTAMP_FILTER_ALL:
1354 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1355 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1356 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1357 return -ERANGE;
1358 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1359 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1360 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1361 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1362 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1363 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1364 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1365 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1366 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1367 cpts->rx_enable = 1;
1368 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1369 break;
1370 default:
1371 return -ERANGE;
1372 }
1373
1374 switch (priv->version) {
1375 case CPSW_VERSION_1:
1376 cpsw_hwtstamp_v1(priv);
1377 break;
1378 case CPSW_VERSION_2:
1379 cpsw_hwtstamp_v2(priv);
1380 break;
1381 default:
1382 return -ENOTSUPP;
1383 }
1384
1385 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1386}
1387
1388#endif /*CONFIG_TI_CPTS*/
1389
1390static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1391{
11f2c988
M		 1392 struct cpsw_priv *priv = netdev_priv(dev);
1393 struct mii_ioctl_data *data = if_mii(req);
1394 int slave_no = cpsw_slave_index(priv);
1395
2e5b38ab
RC		 1396 if (!netif_running(dev))
1397 return -EINVAL;
1398
11f2c988 1399 switch (cmd) {
2e5b38ab 1400#ifdef CONFIG_TI_CPTS
11f2c988 1401 case SIOCSHWTSTAMP:
3177bf6f 1402 return cpsw_hwtstamp_ioctl(dev, req);
2e5b38ab 1403#endif
11f2c988
M		 1404 case SIOCGMIIPHY:
1405 data->phy_id = priv->slaves[slave_no].phy->addr;
1406 break;
1407 default:
1408 return -ENOTSUPP;
1409 }
1410
1411 return 0;
2e5b38ab
RC		 1412}
1413
df828598
M		 1414static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1415{
1416 struct cpsw_priv *priv = netdev_priv(ndev);
1417
1418 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1419 priv->stats.tx_errors++;
1420 cpsw_intr_disable(priv);
1421 cpdma_ctlr_int_ctrl(priv->dma, false);
1422 cpdma_chan_stop(priv->txch);
1423 cpdma_chan_start(priv->txch);
1424 cpdma_ctlr_int_ctrl(priv->dma, true);
1425 cpsw_intr_enable(priv);
510a1e72
M		 1426 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1427 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1428
df828598
M		 1429}
1430
dcfd8d58
M		 1431static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1432{
1433 struct cpsw_priv *priv = netdev_priv(ndev);
1434 struct sockaddr *addr = (struct sockaddr *)p;
1435 int flags = 0;
1436 u16 vid = 0;
1437
1438 if (!is_valid_ether_addr(addr->sa_data))
1439 return -EADDRNOTAVAIL;
1440
1441 if (priv->data.dual_emac) {
1442 vid = priv->slaves[priv->emac_port].port_vlan;
1443 flags = ALE_VLAN;
1444 }
1445
1446 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1447 flags, vid);
1448 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1449 flags, vid);
1450
1451 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1452 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1453 for_each_slave(priv, cpsw_set_slave_mac, priv);
1454
1455 return 0;
1456}
1457
df828598
M		 1458static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
1459{
1460 struct cpsw_priv *priv = netdev_priv(ndev);
1461 return &priv->stats;
1462}
1463
1464#ifdef CONFIG_NET_POLL_CONTROLLER
1465static void cpsw_ndo_poll_controller(struct net_device *ndev)
1466{
1467 struct cpsw_priv *priv = netdev_priv(ndev);
1468
1469 cpsw_intr_disable(priv);
1470 cpdma_ctlr_int_ctrl(priv->dma, false);
1471 cpsw_interrupt(ndev->irq, priv);
1472 cpdma_ctlr_int_ctrl(priv->dma, true);
1473 cpsw_intr_enable(priv);
510a1e72
M		 1474 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1475 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1476
df828598
M		 1477}
1478#endif
1479
3b72c2fe
M		 1480static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1481 unsigned short vid)
1482{
1483 int ret;
1484
1485 ret = cpsw_ale_add_vlan(priv->ale, vid,
1486 ALE_ALL_PORTS << priv->host_port,
1487 0, ALE_ALL_PORTS << priv->host_port,
1488 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1489 if (ret != 0)
1490 return ret;
1491
1492 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1493 priv->host_port, ALE_VLAN, vid);
1494 if (ret != 0)
1495 goto clean_vid;
1496
1497 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1498 ALE_ALL_PORTS << priv->host_port,
1499 ALE_VLAN, vid, 0);
1500 if (ret != 0)
1501 goto clean_vlan_ucast;
1502 return 0;
1503
1504clean_vlan_ucast:
1505 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1506 priv->host_port, ALE_VLAN, vid);
1507clean_vid:
1508 cpsw_ale_del_vlan(priv->ale, vid, 0);
1509 return ret;
1510}
1511
1512static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
80d5c368 1513 __be16 proto, u16 vid)
3b72c2fe
M		 1514{
1515 struct cpsw_priv *priv = netdev_priv(ndev);
1516
1517 if (vid == priv->data.default_vlan)
1518 return 0;
1519
1520 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1521 return cpsw_add_vlan_ale_entry(priv, vid);
1522}
1523
1524static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
80d5c368 1525 __be16 proto, u16 vid)
3b72c2fe
M		 1526{
1527 struct cpsw_priv *priv = netdev_priv(ndev);
1528 int ret;
1529
1530 if (vid == priv->data.default_vlan)
1531 return 0;
1532
1533 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1534 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1535 if (ret != 0)
1536 return ret;
1537
1538 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1539 priv->host_port, ALE_VLAN, vid);
1540 if (ret != 0)
1541 return ret;
1542
1543 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1544 0, ALE_VLAN, vid);
1545}
1546
df828598
M		 1547static const struct net_device_ops cpsw_netdev_ops = {
1548 .ndo_open = cpsw_ndo_open,
1549 .ndo_stop = cpsw_ndo_stop,
1550 .ndo_start_xmit = cpsw_ndo_start_xmit,
1551 .ndo_change_rx_flags = cpsw_ndo_change_rx_flags,
dcfd8d58 1552 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2e5b38ab 1553 .ndo_do_ioctl = cpsw_ndo_ioctl,
df828598 1554 .ndo_validate_addr = eth_validate_addr,
5c473ed2 1555 .ndo_change_mtu = eth_change_mtu,
df828598
M		 1556 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1557 .ndo_get_stats = cpsw_ndo_get_stats,
5c50a856 1558 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
df828598
M		 1559#ifdef CONFIG_NET_POLL_CONTROLLER
1560 .ndo_poll_controller = cpsw_ndo_poll_controller,
1561#endif
3b72c2fe
M		 1562 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1563 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
df828598
M		 1564};
1565
1566static void cpsw_get_drvinfo(struct net_device *ndev,
1567 struct ethtool_drvinfo *info)
1568{
1569 struct cpsw_priv *priv = netdev_priv(ndev);
7826d43f
JP		 1570
1571 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver));
1572 strlcpy(info->version, "1.0", sizeof(info->version));
1573 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
df828598
M		 1574}
1575
1576static u32 cpsw_get_msglevel(struct net_device *ndev)
1577{
1578 struct cpsw_priv *priv = netdev_priv(ndev);
1579 return priv->msg_enable;
1580}
1581
1582static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1583{
1584 struct cpsw_priv *priv = netdev_priv(ndev);
1585 priv->msg_enable = value;
1586}
1587
2e5b38ab
RC		 1588static int cpsw_get_ts_info(struct net_device *ndev,
1589 struct ethtool_ts_info *info)
1590{
1591#ifdef CONFIG_TI_CPTS
1592 struct cpsw_priv *priv = netdev_priv(ndev);
1593
1594 info->so_timestamping =
1595 SOF_TIMESTAMPING_TX_HARDWARE |
1596 SOF_TIMESTAMPING_TX_SOFTWARE |
1597 SOF_TIMESTAMPING_RX_HARDWARE |
1598 SOF_TIMESTAMPING_RX_SOFTWARE |
1599 SOF_TIMESTAMPING_SOFTWARE |
1600 SOF_TIMESTAMPING_RAW_HARDWARE;
9232b16d 1601 info->phc_index = priv->cpts->phc_index;
2e5b38ab
RC		 1602 info->tx_types =
1603 (1 << HWTSTAMP_TX_OFF) |
1604 (1 << HWTSTAMP_TX_ON);
1605 info->rx_filters =
1606 (1 << HWTSTAMP_FILTER_NONE) |
1607 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1608#else
1609 info->so_timestamping =
1610 SOF_TIMESTAMPING_TX_SOFTWARE |
1611 SOF_TIMESTAMPING_RX_SOFTWARE |
1612 SOF_TIMESTAMPING_SOFTWARE;
1613 info->phc_index = -1;
1614 info->tx_types = 0;
1615 info->rx_filters = 0;
1616#endif
1617 return 0;
1618}
1619
d3bb9c58
M		 1620static int cpsw_get_settings(struct net_device *ndev,
1621 struct ethtool_cmd *ecmd)
1622{
1623 struct cpsw_priv *priv = netdev_priv(ndev);
1624 int slave_no = cpsw_slave_index(priv);
1625
1626 if (priv->slaves[slave_no].phy)
1627 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1628 else
1629 return -EOPNOTSUPP;
1630}
1631
1632static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1633{
1634 struct cpsw_priv *priv = netdev_priv(ndev);
1635 int slave_no = cpsw_slave_index(priv);
1636
1637 if (priv->slaves[slave_no].phy)
1638 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1639 else
1640 return -EOPNOTSUPP;
1641}
1642
d8a64420
MU		 1643static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1644{
1645 struct cpsw_priv *priv = netdev_priv(ndev);
1646 int slave_no = cpsw_slave_index(priv);
1647
1648 wol->supported = 0;
1649 wol->wolopts = 0;
1650
1651 if (priv->slaves[slave_no].phy)
1652 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1653}
1654
1655static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1656{
1657 struct cpsw_priv *priv = netdev_priv(ndev);
1658 int slave_no = cpsw_slave_index(priv);
1659
1660 if (priv->slaves[slave_no].phy)
1661 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1662 else
1663 return -EOPNOTSUPP;
1664}
1665
df828598
M		 1666static const struct ethtool_ops cpsw_ethtool_ops = {
1667 .get_drvinfo = cpsw_get_drvinfo,
1668 .get_msglevel = cpsw_get_msglevel,
1669 .set_msglevel = cpsw_set_msglevel,
1670 .get_link = ethtool_op_get_link,
2e5b38ab 1671 .get_ts_info = cpsw_get_ts_info,
d3bb9c58
M		 1672 .get_settings = cpsw_get_settings,
1673 .set_settings = cpsw_set_settings,
ff5b8ef2
M		 1674 .get_coalesce = cpsw_get_coalesce,
1675 .set_coalesce = cpsw_set_coalesce,
d9718546
M		 1676 .get_sset_count = cpsw_get_sset_count,
1677 .get_strings = cpsw_get_strings,
1678 .get_ethtool_stats = cpsw_get_ethtool_stats,
d8a64420
MU		 1679 .get_wol = cpsw_get_wol,
1680 .set_wol = cpsw_set_wol,
df828598
M		 1681};
1682
549985ee
RC		 1683static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1684 u32 slave_reg_ofs, u32 sliver_reg_ofs)
df828598
M		 1685{
1686 void __iomem *regs = priv->regs;
1687 int slave_num = slave->slave_num;
1688 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1689
1690 slave->data = data;
549985ee
RC		 1691 slave->regs = regs + slave_reg_ofs;
1692 slave->sliver = regs + sliver_reg_ofs;
d9ba8f9e 1693 slave->port_vlan = data->dual_emac_res_vlan;
df828598
M		 1694}
1695
2eb32b0a
M		 1696static int cpsw_probe_dt(struct cpsw_platform_data *data,
1697 struct platform_device *pdev)
1698{
1699 struct device_node *node = pdev->dev.of_node;
1700 struct device_node *slave_node;
1701 int i = 0, ret;
1702 u32 prop;
1703
1704 if (!node)
1705 return -EINVAL;
1706
1707 if (of_property_read_u32(node, "slaves", &prop)) {
1708 pr_err("Missing slaves property in the DT.\n");
1709 return -EINVAL;
1710 }
1711 data->slaves = prop;
1712
e86ac13b
M		 1713 if (of_property_read_u32(node, "active_slave", &prop)) {
1714 pr_err("Missing active_slave property in the DT.\n");
78ca0b28
RC		 1715 ret = -EINVAL;
1716 goto error_ret;
1717 }
e86ac13b 1718 data->active_slave = prop;
78ca0b28 1719
00ab94ee
RC		 1720 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1721 pr_err("Missing cpts_clock_mult property in the DT.\n");
1722 ret = -EINVAL;
1723 goto error_ret;
1724 }
1725 data->cpts_clock_mult = prop;
1726
1727 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1728 pr_err("Missing cpts_clock_shift property in the DT.\n");
1729 ret = -EINVAL;
1730 goto error_ret;
1731 }
1732 data->cpts_clock_shift = prop;
1733
b2adaca9
JP		 1734 data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data),
1735 GFP_KERNEL);
1736 if (!data->slave_data)
2eb32b0a 1737 return -EINVAL;
2eb32b0a 1738
2eb32b0a
M		 1739 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1740 pr_err("Missing cpdma_channels property in the DT.\n");
1741 ret = -EINVAL;
1742 goto error_ret;
1743 }
1744 data->channels = prop;
1745
2eb32b0a
M		 1746 if (of_property_read_u32(node, "ale_entries", &prop)) {
1747 pr_err("Missing ale_entries property in the DT.\n");
1748 ret = -EINVAL;
1749 goto error_ret;
1750 }
1751 data->ale_entries = prop;
1752
2eb32b0a
M		 1753 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1754 pr_err("Missing bd_ram_size property in the DT.\n");
1755 ret = -EINVAL;
1756 goto error_ret;
1757 }
1758 data->bd_ram_size = prop;
1759
1760 if (of_property_read_u32(node, "rx_descs", &prop)) {
1761 pr_err("Missing rx_descs property in the DT.\n");
1762 ret = -EINVAL;
1763 goto error_ret;
1764 }
1765 data->rx_descs = prop;
1766
1767 if (of_property_read_u32(node, "mac_control", &prop)) {
1768 pr_err("Missing mac_control property in the DT.\n");
1769 ret = -EINVAL;
1770 goto error_ret;
1771 }
1772 data->mac_control = prop;
1773
d9ba8f9e
M		 1774 if (!of_property_read_u32(node, "dual_emac", &prop))
1775 data->dual_emac = prop;
1776
549985ee
RC		 1777 /*
1778 * Populate all the child nodes here...
1779 */
1780 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1781 /* We do not want to force this, as in some cases may not have child */
1782 if (ret)
1783 pr_warn("Doesn't have any child node\n");
1784
1fb19aa7 1785 for_each_node_by_name(slave_node, "slave") {
2eb32b0a 1786 struct cpsw_slave_data *slave_data = data->slave_data + i;
2eb32b0a 1787 const void *mac_addr = NULL;
549985ee
RC		 1788 u32 phyid;
1789 int lenp;
1790 const __be32 *parp;
1791 struct device_node *mdio_node;
1792 struct platform_device *mdio;
1793
1794 parp = of_get_property(slave_node, "phy_id", &lenp);
ce16294f 1795 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
2eb32b0a
M		 1796 pr_err("Missing slave[%d] phy_id property\n", i);
1797 ret = -EINVAL;
1798 goto error_ret;
1799 }
549985ee
RC		 1800 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1801 phyid = be32_to_cpup(parp+1);
1802 mdio = of_find_device_by_node(mdio_node);
1803 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1804 PHY_ID_FMT, mdio->name, phyid);
2eb32b0a
M		 1805
1806 mac_addr = of_get_mac_address(slave_node);
1807 if (mac_addr)
1808 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1809
c5ceea7a
M		 1810 slave_data->phy_if = of_get_phy_mode(slave_node);
1811
d9ba8f9e 1812 if (data->dual_emac) {
91c4166c 1813 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
d9ba8f9e
M		 1814 &prop)) {
1815 pr_err("Missing dual_emac_res_vlan in DT.\n");
1816 slave_data->dual_emac_res_vlan = i+1;
1817 pr_err("Using %d as Reserved VLAN for %d slave\n",
1818 slave_data->dual_emac_res_vlan, i);
1819 } else {
1820 slave_data->dual_emac_res_vlan = prop;
1821 }
1822 }
1823
2eb32b0a
M		 1824 i++;
1825 }
1826
1827 return 0;
1828
1829error_ret:
1830 kfree(data->slave_data);
1831 return ret;
1832}
1833
d9ba8f9e
M		 1834static int cpsw_probe_dual_emac(struct platform_device *pdev,
1835 struct cpsw_priv *priv)
1836{
1837 struct cpsw_platform_data *data = &priv->data;
1838 struct net_device *ndev;
1839 struct cpsw_priv *priv_sl2;
1840 int ret = 0, i;
1841
1842 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1843 if (!ndev) {
1844 pr_err("cpsw: error allocating net_device\n");
1845 return -ENOMEM;
1846 }
1847
1848 priv_sl2 = netdev_priv(ndev);
1849 spin_lock_init(&priv_sl2->lock);
1850 priv_sl2->data = *data;
1851 priv_sl2->pdev = pdev;
1852 priv_sl2->ndev = ndev;
1853 priv_sl2->dev = &ndev->dev;
1854 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1855 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
1856
1857 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
1858 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
1859 ETH_ALEN);
1860 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
1861 } else {
1862 random_ether_addr(priv_sl2->mac_addr);
1863 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
1864 }
1865 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
1866
1867 priv_sl2->slaves = priv->slaves;
1868 priv_sl2->clk = priv->clk;
1869
ff5b8ef2
M		 1870 priv_sl2->coal_intvl = 0;
1871 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
1872
d9ba8f9e
M		 1873 priv_sl2->cpsw_res = priv->cpsw_res;
1874 priv_sl2->regs = priv->regs;
1875 priv_sl2->host_port = priv->host_port;
1876 priv_sl2->host_port_regs = priv->host_port_regs;
1877 priv_sl2->wr_regs = priv->wr_regs;
d9718546 1878 priv_sl2->hw_stats = priv->hw_stats;
d9ba8f9e
M		 1879 priv_sl2->dma = priv->dma;
1880 priv_sl2->txch = priv->txch;
1881 priv_sl2->rxch = priv->rxch;
1882 priv_sl2->ale = priv->ale;
1883 priv_sl2->emac_port = 1;
1884 priv->slaves[1].ndev = ndev;
1885 priv_sl2->cpts = priv->cpts;
1886 priv_sl2->version = priv->version;
1887
1888 for (i = 0; i < priv->num_irqs; i++) {
1889 priv_sl2->irqs_table[i] = priv->irqs_table[i];
1890 priv_sl2->num_irqs = priv->num_irqs;
1891 }
f646968f 1892 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d9ba8f9e
M		 1893
1894 ndev->netdev_ops = &cpsw_netdev_ops;
1895 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1896 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1897
1898 /* register the network device */
1899 SET_NETDEV_DEV(ndev, &pdev->dev);
1900 ret = register_netdev(ndev);
1901 if (ret) {
1902 pr_err("cpsw: error registering net device\n");
1903 free_netdev(ndev);
1904 ret = -ENODEV;
1905 }
1906
1907 return ret;
1908}
1909
663e12e6 1910static int cpsw_probe(struct platform_device *pdev)
df828598 1911{
d1bd9acf 1912 struct cpsw_platform_data *data;
df828598
M		 1913 struct net_device *ndev;
1914 struct cpsw_priv *priv;
1915 struct cpdma_params dma_params;
1916 struct cpsw_ale_params ale_params;
549985ee 1917 void __iomem *ss_regs, *wr_regs;
df828598 1918 struct resource *res;
549985ee 1919 u32 slave_offset, sliver_offset, slave_size;
df828598
M		 1920 int ret = 0, i, k = 0;
1921
df828598
M		 1922 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1923 if (!ndev) {
1924 pr_err("error allocating net_device\n");
1925 return -ENOMEM;
1926 }
1927
1928 platform_set_drvdata(pdev, ndev);
1929 priv = netdev_priv(ndev);
1930 spin_lock_init(&priv->lock);
df828598
M		 1931 priv->pdev = pdev;
1932 priv->ndev = ndev;
1933 priv->dev = &ndev->dev;
1934 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1935 priv->rx_packet_max = max(rx_packet_max, 128);
9232b16d 1936 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
7dcf313a 1937 priv->irq_enabled = true;
ab8e99d2 1938 if (!priv->cpts) {
9232b16d
M		 1939 pr_err("error allocating cpts\n");
1940 goto clean_ndev_ret;
1941 }
df828598 1942
1fb19aa7
VH		 1943 /*
1944 * This may be required here for child devices.
1945 */
1946 pm_runtime_enable(&pdev->dev);
1947
739683b4
M		 1948 /* Select default pin state */
1949 pinctrl_pm_select_default_state(&pdev->dev);
1950
2eb32b0a
M		 1951 if (cpsw_probe_dt(&priv->data, pdev)) {
1952 pr_err("cpsw: platform data missing\n");
1953 ret = -ENODEV;
1954 goto clean_ndev_ret;
1955 }
1956 data = &priv->data;
1957
df828598
M		 1958 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
1959 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
cf6122be 1960 pr_info("Detected MACID = %pM\n", priv->mac_addr);
df828598 1961 } else {
7efd26d0 1962 eth_random_addr(priv->mac_addr);
cf6122be 1963 pr_info("Random MACID = %pM\n", priv->mac_addr);
df828598
M		 1964 }
1965
1966 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1967
1968 priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
1969 GFP_KERNEL);
1970 if (!priv->slaves) {
1971 ret = -EBUSY;
1972 goto clean_ndev_ret;
1973 }
1974 for (i = 0; i < data->slaves; i++)
1975 priv->slaves[i].slave_num = i;
1976
d9ba8f9e
M		 1977 priv->slaves[0].ndev = ndev;
1978 priv->emac_port = 0;
1979
f150bd7f 1980 priv->clk = clk_get(&pdev->dev, "fck");
df828598 1981 if (IS_ERR(priv->clk)) {
f150bd7f
M		 1982 dev_err(&pdev->dev, "fck is not found\n");
1983 ret = -ENODEV;
1984 goto clean_slave_ret;
df828598 1985 }
ff5b8ef2
M		 1986 priv->coal_intvl = 0;
1987 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
df828598
M		 1988
1989 priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1990 if (!priv->cpsw_res) {
1991 dev_err(priv->dev, "error getting i/o resource\n");
1992 ret = -ENOENT;
1993 goto clean_clk_ret;
1994 }
df828598
M		 1995 if (!request_mem_region(priv->cpsw_res->start,
1996 resource_size(priv->cpsw_res), ndev->name)) {
1997 dev_err(priv->dev, "failed request i/o region\n");
1998 ret = -ENXIO;
1999 goto clean_clk_ret;
2000 }
549985ee
RC		 2001 ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
2002 if (!ss_regs) {
df828598
M		 2003 dev_err(priv->dev, "unable to map i/o region\n");
2004 goto clean_cpsw_iores_ret;
2005 }
549985ee
RC		 2006 priv->regs = ss_regs;
2007 priv->version = __raw_readl(&priv->regs->id_ver);
2008 priv->host_port = HOST_PORT_NUM;
df828598 2009
a65dd5b2
RC		 2010 priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2011 if (!priv->cpsw_wr_res) {
df828598
M		 2012 dev_err(priv->dev, "error getting i/o resource\n");
2013 ret = -ENOENT;
5250c969 2014 goto clean_iomap_ret;
df828598 2015 }
a65dd5b2
RC		 2016 if (!request_mem_region(priv->cpsw_wr_res->start,
2017 resource_size(priv->cpsw_wr_res), ndev->name)) {
df828598
M		 2018 dev_err(priv->dev, "failed request i/o region\n");
2019 ret = -ENXIO;
5250c969 2020 goto clean_iomap_ret;
df828598 2021 }
549985ee 2022 wr_regs = ioremap(priv->cpsw_wr_res->start,
a65dd5b2 2023 resource_size(priv->cpsw_wr_res));
549985ee 2024 if (!wr_regs) {
df828598 2025 dev_err(priv->dev, "unable to map i/o region\n");
a65dd5b2 2026 goto clean_cpsw_wr_iores_ret;
df828598 2027 }
549985ee 2028 priv->wr_regs = wr_regs;
df828598
M		 2029
2030 memset(&dma_params, 0, sizeof(dma_params));
549985ee
RC		 2031 memset(&ale_params, 0, sizeof(ale_params));
2032
2033 switch (priv->version) {
2034 case CPSW_VERSION_1:
2035 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
d9718546
M		 2036 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2037 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
549985ee
RC		 2038 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2039 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2040 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2041 slave_offset = CPSW1_SLAVE_OFFSET;
2042 slave_size = CPSW1_SLAVE_SIZE;
2043 sliver_offset = CPSW1_SLIVER_OFFSET;
2044 dma_params.desc_mem_phys = 0;
2045 break;
2046 case CPSW_VERSION_2:
c193f365 2047 case CPSW_VERSION_3:
926489be 2048 case CPSW_VERSION_4:
549985ee 2049 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
d9718546
M		 2050 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2051 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
549985ee
RC		 2052 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2053 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2054 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2055 slave_offset = CPSW2_SLAVE_OFFSET;
2056 slave_size = CPSW2_SLAVE_SIZE;
2057 sliver_offset = CPSW2_SLIVER_OFFSET;
2058 dma_params.desc_mem_phys =
2059 (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET;
2060 break;
2061 default:
2062 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2063 ret = -ENODEV;
2064 goto clean_cpsw_wr_iores_ret;
2065 }
2066 for (i = 0; i < priv->data.slaves; i++) {
2067 struct cpsw_slave *slave = &priv->slaves[i];
2068 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2069 slave_offset += slave_size;
2070 sliver_offset += SLIVER_SIZE;
2071 }
2072
df828598 2073 dma_params.dev = &pdev->dev;
549985ee
RC		 2074 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2075 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2076 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2077 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2078 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
df828598
M		 2079
2080 dma_params.num_chan = data->channels;
2081 dma_params.has_soft_reset = true;
2082 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2083 dma_params.desc_mem_size = data->bd_ram_size;
2084 dma_params.desc_align = 16;
2085 dma_params.has_ext_regs = true;
549985ee 2086 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
df828598
M		 2087
2088 priv->dma = cpdma_ctlr_create(&dma_params);
2089 if (!priv->dma) {
2090 dev_err(priv->dev, "error initializing dma\n");
2091 ret = -ENOMEM;
5250c969 2092 goto clean_wr_iomap_ret;
df828598
M		 2093 }
2094
2095 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2096 cpsw_tx_handler);
2097 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2098 cpsw_rx_handler);
2099
2100 if (WARN_ON(!priv->txch || !priv->rxch)) {
2101 dev_err(priv->dev, "error initializing dma channels\n");
2102 ret = -ENOMEM;
2103 goto clean_dma_ret;
2104 }
2105
df828598 2106 ale_params.dev = &ndev->dev;
df828598
M		 2107 ale_params.ale_ageout = ale_ageout;
2108 ale_params.ale_entries = data->ale_entries;
2109 ale_params.ale_ports = data->slaves;
2110
2111 priv->ale = cpsw_ale_create(&ale_params);
2112 if (!priv->ale) {
2113 dev_err(priv->dev, "error initializing ale engine\n");
2114 ret = -ENODEV;
2115 goto clean_dma_ret;
2116 }
2117
2118 ndev->irq = platform_get_irq(pdev, 0);
2119 if (ndev->irq < 0) {
2120 dev_err(priv->dev, "error getting irq resource\n");
2121 ret = -ENOENT;
2122 goto clean_ale_ret;
2123 }
2124
2125 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2126 for (i = res->start; i <= res->end; i++) {
7069f982 2127 if (request_irq(i, cpsw_interrupt, 0,
df828598
M		 2128 dev_name(&pdev->dev), priv)) {
2129 dev_err(priv->dev, "error attaching irq\n");
2130 goto clean_ale_ret;
2131 }
2132 priv->irqs_table[k] = i;
d1bd9acf 2133 priv->num_irqs = k + 1;
df828598
M		 2134 }
2135 k++;
2136 }
2137
f646968f 2138 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
df828598
M		 2139
2140 ndev->netdev_ops = &cpsw_netdev_ops;
2141 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
2142 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2143
2144 /* register the network device */
2145 SET_NETDEV_DEV(ndev, &pdev->dev);
2146 ret = register_netdev(ndev);
2147 if (ret) {
2148 dev_err(priv->dev, "error registering net device\n");
2149 ret = -ENODEV;
2150 goto clean_irq_ret;
2151 }
2152
9232b16d 2153 if (cpts_register(&pdev->dev, priv->cpts,
2e5b38ab
RC		 2154 data->cpts_clock_mult, data->cpts_clock_shift))
2155 dev_err(priv->dev, "error registering cpts device\n");
2156
df828598
M		 2157 cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
2158 priv->cpsw_res->start, ndev->irq);
2159
d9ba8f9e
M		 2160 if (priv->data.dual_emac) {
2161 ret = cpsw_probe_dual_emac(pdev, priv);
2162 if (ret) {
2163 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2164 goto clean_irq_ret;
2165 }
2166 }
2167
df828598
M		 2168 return 0;
2169
2170clean_irq_ret:
d1bd9acf
SS		 2171 for (i = 0; i < priv->num_irqs; i++)
2172 free_irq(priv->irqs_table[i], priv);
df828598
M		 2173clean_ale_ret:
2174 cpsw_ale_destroy(priv->ale);
2175clean_dma_ret:
2176 cpdma_chan_destroy(priv->txch);
2177 cpdma_chan_destroy(priv->rxch);
2178 cpdma_ctlr_destroy(priv->dma);
5250c969
RC		 2179clean_wr_iomap_ret:
2180 iounmap(priv->wr_regs);
a65dd5b2
RC		 2181clean_cpsw_wr_iores_ret:
2182 release_mem_region(priv->cpsw_wr_res->start,
2183 resource_size(priv->cpsw_wr_res));
5250c969
RC		 2184clean_iomap_ret:
2185 iounmap(priv->regs);
df828598
M		 2186clean_cpsw_iores_ret:
2187 release_mem_region(priv->cpsw_res->start,
2188 resource_size(priv->cpsw_res));
2189clean_clk_ret:
2190 clk_put(priv->clk);
f150bd7f
M		 2191clean_slave_ret:
2192 pm_runtime_disable(&pdev->dev);
df828598
M		 2193 kfree(priv->slaves);
2194clean_ndev_ret:
d1bd9acf
SS		 2195 kfree(priv->data.slave_data);
2196 free_netdev(priv->ndev);
df828598
M		 2197 return ret;
2198}
2199
663e12e6 2200static int cpsw_remove(struct platform_device *pdev)
df828598
M		 2201{
2202 struct net_device *ndev = platform_get_drvdata(pdev);
2203 struct cpsw_priv *priv = netdev_priv(ndev);
d1bd9acf 2204 int i;
df828598 2205
d1bd9acf
SS		 2206 if (priv->data.dual_emac)
2207 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2208 unregister_netdev(ndev);
df828598 2209
9232b16d 2210 cpts_unregister(priv->cpts);
d1bd9acf
SS		 2211 for (i = 0; i < priv->num_irqs; i++)
2212 free_irq(priv->irqs_table[i], priv);
2213
df828598
M		 2214 cpsw_ale_destroy(priv->ale);
2215 cpdma_chan_destroy(priv->txch);
2216 cpdma_chan_destroy(priv->rxch);
2217 cpdma_ctlr_destroy(priv->dma);
2218 iounmap(priv->regs);
2219 release_mem_region(priv->cpsw_res->start,
2220 resource_size(priv->cpsw_res));
5250c969 2221 iounmap(priv->wr_regs);
a65dd5b2
RC		 2222 release_mem_region(priv->cpsw_wr_res->start,
2223 resource_size(priv->cpsw_wr_res));
f150bd7f 2224 pm_runtime_disable(&pdev->dev);
df828598
M		 2225 clk_put(priv->clk);
2226 kfree(priv->slaves);
d1bd9acf
SS		 2227 kfree(priv->data.slave_data);
2228 if (priv->data.dual_emac)
2229 free_netdev(cpsw_get_slave_ndev(priv, 1));
df828598 2230 free_netdev(ndev);
df828598
M		 2231 return 0;
2232}
2233
2234static int cpsw_suspend(struct device *dev)
2235{
2236 struct platform_device *pdev = to_platform_device(dev);
2237 struct net_device *ndev = platform_get_drvdata(pdev);
b90fc27a 2238 struct cpsw_priv *priv = netdev_priv(ndev);
df828598
M		 2239
2240 if (netif_running(ndev))
2241 cpsw_ndo_stop(ndev);
6d3d76f8
M		 2242 soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset);
2243 soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset);
f150bd7f
M		 2244 pm_runtime_put_sync(&pdev->dev);
2245
739683b4
M		 2246 /* Select sleep pin state */
2247 pinctrl_pm_select_sleep_state(&pdev->dev);
2248
df828598
M		 2249 return 0;
2250}
2251
2252static int cpsw_resume(struct device *dev)
2253{
2254 struct platform_device *pdev = to_platform_device(dev);
2255 struct net_device *ndev = platform_get_drvdata(pdev);
2256
f150bd7f 2257 pm_runtime_get_sync(&pdev->dev);
739683b4
M		 2258
2259 /* Select default pin state */
2260 pinctrl_pm_select_default_state(&pdev->dev);
2261
df828598
M		 2262 if (netif_running(ndev))
2263 cpsw_ndo_open(ndev);
2264 return 0;
2265}
2266
2267static const struct dev_pm_ops cpsw_pm_ops = {
2268 .suspend = cpsw_suspend,
2269 .resume = cpsw_resume,
2270};
2271
2eb32b0a
M		 2272static const struct of_device_id cpsw_of_mtable[] = {
2273 { .compatible = "ti,cpsw", },
2274 { /* sentinel */ },
2275};
4bc21d41 2276MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2eb32b0a 2277
df828598
M		 2278static struct platform_driver cpsw_driver = {
2279 .driver = {
2280 .name = "cpsw",
2281 .owner = THIS_MODULE,
2282 .pm = &cpsw_pm_ops,
2eb32b0a 2283 .of_match_table = of_match_ptr(cpsw_of_mtable),
df828598
M		 2284 },
2285 .probe = cpsw_probe,
663e12e6 2286 .remove = cpsw_remove,
df828598
M		 2287};
2288
2289static int __init cpsw_init(void)
2290{
2291 return platform_driver_register(&cpsw_driver);
2292}
2293late_initcall(cpsw_init);
2294
2295static void __exit cpsw_exit(void)
2296{
2297 platform_driver_unregister(&cpsw_driver);
2298}
2299module_exit(cpsw_exit);
2300
2301MODULE_LICENSE("GPL");
2302MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2303MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2304MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
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