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Merge tag 'linux-can-next-for-3.20-20150128' of git://git.kernel.org/pub/scm/linux...
[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
2e5b38ab 27#include <linux/net_tstamp.h>
df828598
M		 28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
f150bd7f 31#include <linux/pm_runtime.h>
2eb32b0a
M		 32#include <linux/of.h>
33#include <linux/of_net.h>
34#include <linux/of_device.h>
3b72c2fe 35#include <linux/if_vlan.h>
0ba517b1
MP		 36#include <linux/mfd/syscon.h>
37#include <linux/regmap.h>
df828598 38
739683b4 39#include <linux/pinctrl/consumer.h>
df828598 40
dbe34724 41#include "cpsw.h"
df828598 42#include "cpsw_ale.h"
2e5b38ab 43#include "cpts.h"
df828598
M		 44#include "davinci_cpdma.h"
45
46#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55#define cpsw_info(priv, type, format, ...) \
56do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59} while (0)
60
61#define cpsw_err(priv, type, format, ...) \
62do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65} while (0)
66
67#define cpsw_dbg(priv, type, format, ...) \
68do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71} while (0)
72
73#define cpsw_notice(priv, type, format, ...) \
74do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77} while (0)
78
5c50a856
M		 79#define ALE_ALL_PORTS 0x7
80
df828598
M		 81#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
e90cfac6
RC		 85#define CPSW_VERSION_1 0x19010a
86#define CPSW_VERSION_2 0x19010c
c193f365 87#define CPSW_VERSION_3 0x19010f
926489be 88#define CPSW_VERSION_4 0x190112
549985ee
RC		 89
90#define HOST_PORT_NUM 0
91#define SLIVER_SIZE 0x40
92
93#define CPSW1_HOST_PORT_OFFSET 0x028
94#define CPSW1_SLAVE_OFFSET 0x050
95#define CPSW1_SLAVE_SIZE 0x040
96#define CPSW1_CPDMA_OFFSET 0x100
97#define CPSW1_STATERAM_OFFSET 0x200
d9718546 98#define CPSW1_HW_STATS 0x400
549985ee
RC		 99#define CPSW1_CPTS_OFFSET 0x500
100#define CPSW1_ALE_OFFSET 0x600
101#define CPSW1_SLIVER_OFFSET 0x700
102
103#define CPSW2_HOST_PORT_OFFSET 0x108
104#define CPSW2_SLAVE_OFFSET 0x200
105#define CPSW2_SLAVE_SIZE 0x100
106#define CPSW2_CPDMA_OFFSET 0x800
d9718546 107#define CPSW2_HW_STATS 0x900
549985ee
RC		 108#define CPSW2_STATERAM_OFFSET 0xa00
109#define CPSW2_CPTS_OFFSET 0xc00
110#define CPSW2_ALE_OFFSET 0xd00
111#define CPSW2_SLIVER_OFFSET 0xd80
112#define CPSW2_BD_OFFSET 0x2000
113
df828598
M		 114#define CPDMA_RXTHRESH 0x0c0
115#define CPDMA_RXFREE 0x0e0
116#define CPDMA_TXHDP 0x00
117#define CPDMA_RXHDP 0x20
118#define CPDMA_TXCP 0x40
119#define CPDMA_RXCP 0x60
120
df828598
M		 121#define CPSW_POLL_WEIGHT 64
122#define CPSW_MIN_PACKET_SIZE 60
123#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125#define RX_PRIORITY_MAPPING 0x76543210
126#define TX_PRIORITY_MAPPING 0x33221100
127#define CPDMA_TX_PRIORITY_MAP 0x76543210
128
3b72c2fe
M		 129#define CPSW_VLAN_AWARE BIT(1)
130#define CPSW_ALE_VLAN_AWARE 1
131
35717d8d
JO		 132#define CPSW_FIFO_NORMAL_MODE (0 << 16)
133#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
d9ba8f9e 135
ff5b8ef2
M		 136#define CPSW_INTPACEEN (0x3f << 16)
137#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138#define CPSW_CMINTMAX_CNT 63
139#define CPSW_CMINTMIN_CNT 2
140#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
df828598
M		 143#define cpsw_enable_irq(priv) \
144 do { \
145 u32 i; \
146 for (i = 0; i < priv->num_irqs; i++) \
147 enable_irq(priv->irqs_table[i]); \
5f47dfb4 148 } while (0)
df828598
M		 149#define cpsw_disable_irq(priv) \
150 do { \
151 u32 i; \
152 for (i = 0; i < priv->num_irqs; i++) \
153 disable_irq_nosync(priv->irqs_table[i]); \
5f47dfb4 154 } while (0)
df828598 155
d3bb9c58
M		 156#define cpsw_slave_index(priv) \
157 ((priv->data.dual_emac) ? priv->emac_port : \
158 priv->data.active_slave)
159
df828598
M		 160static int debug_level;
161module_param(debug_level, int, 0);
162MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
163
164static int ale_ageout = 10;
165module_param(ale_ageout, int, 0);
166MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
167
168static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
169module_param(rx_packet_max, int, 0);
170MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
171
996a5c27 172struct cpsw_wr_regs {
df828598
M		 173 u32 id_ver;
174 u32 soft_reset;
175 u32 control;
176 u32 int_control;
177 u32 rx_thresh_en;
178 u32 rx_en;
179 u32 tx_en;
180 u32 misc_en;
ff5b8ef2
M		 181 u32 mem_allign1[8];
182 u32 rx_thresh_stat;
183 u32 rx_stat;
184 u32 tx_stat;
185 u32 misc_stat;
186 u32 mem_allign2[8];
187 u32 rx_imax;
188 u32 tx_imax;
189
df828598
M		 190};
191
996a5c27 192struct cpsw_ss_regs {
df828598
M		 193 u32 id_ver;
194 u32 control;
195 u32 soft_reset;
196 u32 stat_port_en;
197 u32 ptype;
bd357af2
RC		 198 u32 soft_idle;
199 u32 thru_rate;
200 u32 gap_thresh;
201 u32 tx_start_wds;
202 u32 flow_control;
203 u32 vlan_ltype;
204 u32 ts_ltype;
205 u32 dlr_ltype;
df828598
M		 206};
207
9750a3ad
RC		 208/* CPSW_PORT_V1 */
209#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
210#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
211#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
212#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
213#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
214#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
215#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
216#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
217
218/* CPSW_PORT_V2 */
219#define CPSW2_CONTROL 0x00 /* Control Register */
220#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
221#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
222#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
223#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
224#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
225#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
226
227/* CPSW_PORT_V1 and V2 */
228#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
229#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
230#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
231
232/* CPSW_PORT_V2 only */
233#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
234#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
235#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
236#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
237#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
238#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
239#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
240#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
241
242/* Bit definitions for the CPSW2_CONTROL register */
243#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
244#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
245#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
246#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
247#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
248#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
249#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
250#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
251#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
252#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
09c55372
GC		 253#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
254#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
9750a3ad
RC		 255#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
256#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
257#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
258#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
259#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
260
09c55372
GC		 261#define CTRL_V2_TS_BITS \
262 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
263 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
9750a3ad 264
09c55372
GC		 265#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
266#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
267#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
268
269
270#define CTRL_V3_TS_BITS \
271 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
272 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
273 TS_LTYPE1_EN)
274
275#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
276#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
277#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
9750a3ad
RC		 278
279/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
280#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
281#define TS_SEQ_ID_OFFSET_MASK (0x3f)
282#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
283#define TS_MSG_TYPE_EN_MASK (0xffff)
284
285/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
286#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598 287
2e5b38ab
RC		 288/* Bit definitions for the CPSW1_TS_CTL register */
289#define CPSW_V1_TS_RX_EN BIT(0)
290#define CPSW_V1_TS_TX_EN BIT(4)
291#define CPSW_V1_MSG_TYPE_OFS 16
292
293/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
294#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
295
df828598
M		 296struct cpsw_host_regs {
297 u32 max_blks;
298 u32 blk_cnt;
d9ba8f9e 299 u32 tx_in_ctl;
df828598
M		 300 u32 port_vlan;
301 u32 tx_pri_map;
302 u32 cpdma_tx_pri_map;
303 u32 cpdma_rx_chan_map;
304};
305
306struct cpsw_sliver_regs {
307 u32 id_ver;
308 u32 mac_control;
309 u32 mac_status;
310 u32 soft_reset;
311 u32 rx_maxlen;
312 u32 __reserved_0;
313 u32 rx_pause;
314 u32 tx_pause;
315 u32 __reserved_1;
316 u32 rx_pri_map;
317};
318
d9718546
M		 319struct cpsw_hw_stats {
320 u32 rxgoodframes;
321 u32 rxbroadcastframes;
322 u32 rxmulticastframes;
323 u32 rxpauseframes;
324 u32 rxcrcerrors;
325 u32 rxaligncodeerrors;
326 u32 rxoversizedframes;
327 u32 rxjabberframes;
328 u32 rxundersizedframes;
329 u32 rxfragments;
330 u32 __pad_0[2];
331 u32 rxoctets;
332 u32 txgoodframes;
333 u32 txbroadcastframes;
334 u32 txmulticastframes;
335 u32 txpauseframes;
336 u32 txdeferredframes;
337 u32 txcollisionframes;
338 u32 txsinglecollframes;
339 u32 txmultcollframes;
340 u32 txexcessivecollisions;
341 u32 txlatecollisions;
342 u32 txunderrun;
343 u32 txcarriersenseerrors;
344 u32 txoctets;
345 u32 octetframes64;
346 u32 octetframes65t127;
347 u32 octetframes128t255;
348 u32 octetframes256t511;
349 u32 octetframes512t1023;
350 u32 octetframes1024tup;
351 u32 netoctets;
352 u32 rxsofoverruns;
353 u32 rxmofoverruns;
354 u32 rxdmaoverruns;
355};
356
df828598 357struct cpsw_slave {
9750a3ad 358 void __iomem *regs;
df828598
M		 359 struct cpsw_sliver_regs __iomem *sliver;
360 int slave_num;
361 u32 mac_control;
362 struct cpsw_slave_data *data;
363 struct phy_device *phy;
d9ba8f9e
M		 364 struct net_device *ndev;
365 u32 port_vlan;
366 u32 open_stat;
df828598
M		 367};
368
9750a3ad
RC		 369static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
370{
371 return __raw_readl(slave->regs + offset);
372}
373
374static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
375{
376 __raw_writel(val, slave->regs + offset);
377}
378
df828598
M		 379struct cpsw_priv {
380 spinlock_t lock;
381 struct platform_device *pdev;
382 struct net_device *ndev;
df828598
M		 383 struct napi_struct napi;
384 struct device *dev;
385 struct cpsw_platform_data data;
996a5c27
RC		 386 struct cpsw_ss_regs __iomem *regs;
387 struct cpsw_wr_regs __iomem *wr_regs;
d9718546 388 u8 __iomem *hw_stats;
df828598
M		 389 struct cpsw_host_regs __iomem *host_port_regs;
390 u32 msg_enable;
e90cfac6 391 u32 version;
ff5b8ef2
M		 392 u32 coal_intvl;
393 u32 bus_freq_mhz;
df828598
M		 394 int rx_packet_max;
395 int host_port;
396 struct clk *clk;
397 u8 mac_addr[ETH_ALEN];
398 struct cpsw_slave *slaves;
399 struct cpdma_ctlr *dma;
400 struct cpdma_chan *txch, *rxch;
401 struct cpsw_ale *ale;
1923d6e4
M		 402 bool rx_pause;
403 bool tx_pause;
df828598
M		 404 /* snapshot of IRQ numbers */
405 u32 irqs_table[4];
406 u32 num_irqs;
a11fbba9 407 bool irq_enabled;
9232b16d 408 struct cpts *cpts;
d9ba8f9e 409 u32 emac_port;
df828598
M		 410};
411
d9718546
M		 412struct cpsw_stats {
413 char stat_string[ETH_GSTRING_LEN];
414 int type;
415 int sizeof_stat;
416 int stat_offset;
417};
418
419enum {
420 CPSW_STATS,
421 CPDMA_RX_STATS,
422 CPDMA_TX_STATS,
423};
424
425#define CPSW_STAT(m) CPSW_STATS, \
426 sizeof(((struct cpsw_hw_stats *)0)->m), \
427 offsetof(struct cpsw_hw_stats, m)
428#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
429 sizeof(((struct cpdma_chan_stats *)0)->m), \
430 offsetof(struct cpdma_chan_stats, m)
431#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
432 sizeof(((struct cpdma_chan_stats *)0)->m), \
433 offsetof(struct cpdma_chan_stats, m)
434
435static const struct cpsw_stats cpsw_gstrings_stats[] = {
436 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
437 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
438 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
439 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
440 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
441 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
442 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
443 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
444 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
445 { "Rx Fragments", CPSW_STAT(rxfragments) },
446 { "Rx Octets", CPSW_STAT(rxoctets) },
447 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
448 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
449 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
450 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
451 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
452 { "Collisions", CPSW_STAT(txcollisionframes) },
453 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
454 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
455 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
456 { "Late Collisions", CPSW_STAT(txlatecollisions) },
457 { "Tx Underrun", CPSW_STAT(txunderrun) },
458 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
459 { "Tx Octets", CPSW_STAT(txoctets) },
460 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
461 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
462 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
463 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
464 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
465 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
466 { "Net Octets", CPSW_STAT(netoctets) },
467 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
468 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
469 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
470 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
471 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
472 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
473 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
474 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
475 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
476 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
477 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
478 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
479 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
480 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
481 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
482 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
483 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
484 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
485 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
486 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
487 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
488 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
489 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
490 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
491 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
492 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
493 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
494 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
495 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
496};
497
498#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
499
df828598 500#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
d9ba8f9e
M		 501#define for_each_slave(priv, func, arg...) \
502 do { \
6e6ceaed
SS		 503 struct cpsw_slave *slave; \
504 int n; \
d9ba8f9e
M		 505 if (priv->data.dual_emac) \
506 (func)((priv)->slaves + priv->emac_port, ##arg);\
507 else \
6e6ceaed
SS		 508 for (n = (priv)->data.slaves, \
509 slave = (priv)->slaves; \
510 n; n--) \
511 (func)(slave++, ##arg); \
d9ba8f9e
M		 512 } while (0)
513#define cpsw_get_slave_ndev(priv, __slave_no__) \
514 (priv->slaves[__slave_no__].ndev)
515#define cpsw_get_slave_priv(priv, __slave_no__) \
516 ((priv->slaves[__slave_no__].ndev) ? \
517 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
518
519#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
520 do { \
521 if (!priv->data.dual_emac) \
522 break; \
523 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
524 ndev = cpsw_get_slave_ndev(priv, 0); \
525 priv = netdev_priv(ndev); \
526 skb->dev = ndev; \
527 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
528 ndev = cpsw_get_slave_ndev(priv, 1); \
529 priv = netdev_priv(ndev); \
530 skb->dev = ndev; \
531 } \
df828598 532 } while (0)
d9ba8f9e
M		 533#define cpsw_add_mcast(priv, addr) \
534 do { \
535 if (priv->data.dual_emac) { \
536 struct cpsw_slave *slave = priv->slaves + \
537 priv->emac_port; \
538 int slave_port = cpsw_get_slave_port(priv, \
539 slave->slave_num); \
540 cpsw_ale_add_mcast(priv->ale, addr, \
541 1 << slave_port | 1 << priv->host_port, \
542 ALE_VLAN, slave->port_vlan, 0); \
543 } else { \
544 cpsw_ale_add_mcast(priv->ale, addr, \
545 ALE_ALL_PORTS << priv->host_port, \
546 0, 0, 0); \
547 } \
548 } while (0)
549
550static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
551{
552 if (priv->host_port == 0)
553 return slave_num + 1;
554 else
555 return slave_num;
556}
df828598 557
0cd8f9cc
M		 558static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
559{
560 struct cpsw_priv *priv = netdev_priv(ndev);
561 struct cpsw_ale *ale = priv->ale;
562 int i;
563
564 if (priv->data.dual_emac) {
565 bool flag = false;
566
567 /* Enabling promiscuous mode for one interface will be
568 * common for both the interface as the interface shares
569 * the same hardware resource.
570 */
0d961b3b 571 for (i = 0; i < priv->data.slaves; i++)
0cd8f9cc
M		 572 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
573 flag = true;
574
575 if (!enable && flag) {
576 enable = true;
577 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
578 }
579
580 if (enable) {
581 /* Enable Bypass */
582 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
583
584 dev_dbg(&ndev->dev, "promiscuity enabled\n");
585 } else {
586 /* Disable Bypass */
587 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
588 dev_dbg(&ndev->dev, "promiscuity disabled\n");
589 }
590 } else {
591 if (enable) {
592 unsigned long timeout = jiffies + HZ;
593
6f979eb3
LS		 594 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
595 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 596 cpsw_ale_control_set(ale, i,
597 ALE_PORT_NOLEARN, 1);
598 cpsw_ale_control_set(ale, i,
599 ALE_PORT_NO_SA_UPDATE, 1);
600 }
601
602 /* Clear All Untouched entries */
603 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
604 do {
605 cpu_relax();
606 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
607 break;
608 } while (time_after(timeout, jiffies));
609 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
610
611 /* Clear all mcast from ALE */
612 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
25906052 613 priv->host_port, -1);
0cd8f9cc
M		 614
615 /* Flood All Unicast Packets to Host port */
616 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
617 dev_dbg(&ndev->dev, "promiscuity enabled\n");
618 } else {
6f979eb3 619 /* Don't Flood All Unicast Packets to Host port */
0cd8f9cc
M		 620 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
621
6f979eb3
LS		 622 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
623 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 624 cpsw_ale_control_set(ale, i,
625 ALE_PORT_NOLEARN, 0);
626 cpsw_ale_control_set(ale, i,
627 ALE_PORT_NO_SA_UPDATE, 0);
628 }
629 dev_dbg(&ndev->dev, "promiscuity disabled\n");
630 }
631 }
632}
633
5c50a856
M		 634static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
635{
636 struct cpsw_priv *priv = netdev_priv(ndev);
25906052
M		 637 int vid;
638
639 if (priv->data.dual_emac)
640 vid = priv->slaves[priv->emac_port].port_vlan;
641 else
642 vid = priv->data.default_vlan;
5c50a856
M		 643
644 if (ndev->flags & IFF_PROMISC) {
645 /* Enable promiscuous mode */
0cd8f9cc 646 cpsw_set_promiscious(ndev, true);
1e5c4bc4 647 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
5c50a856 648 return;
0cd8f9cc
M		 649 } else {
650 /* Disable promiscuous mode */
651 cpsw_set_promiscious(ndev, false);
5c50a856
M		 652 }
653
1e5c4bc4
LS		 654 /* Restore allmulti on vlans if necessary */
655 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
656
5c50a856 657 /* Clear all mcast from ALE */
25906052
M		 658 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
659 vid);
5c50a856
M		 660
661 if (!netdev_mc_empty(ndev)) {
662 struct netdev_hw_addr *ha;
663
664 /* program multicast address list into ALE register */
665 netdev_for_each_mc_addr(ha, ndev) {
d9ba8f9e 666 cpsw_add_mcast(priv, (u8 *)ha->addr);
5c50a856
M		 667 }
668 }
669}
670
df828598
M		 671static void cpsw_intr_enable(struct cpsw_priv *priv)
672{
996a5c27
RC		 673 __raw_writel(0xFF, &priv->wr_regs->tx_en);
674 __raw_writel(0xFF, &priv->wr_regs->rx_en);
df828598
M		 675
676 cpdma_ctlr_int_ctrl(priv->dma, true);
677 return;
678}
679
680static void cpsw_intr_disable(struct cpsw_priv *priv)
681{
996a5c27
RC		 682 __raw_writel(0, &priv->wr_regs->tx_en);
683 __raw_writel(0, &priv->wr_regs->rx_en);
df828598
M		 684
685 cpdma_ctlr_int_ctrl(priv->dma, false);
686 return;
687}
688
1a3b5056 689static void cpsw_tx_handler(void *token, int len, int status)
df828598
M		 690{
691 struct sk_buff *skb = token;
692 struct net_device *ndev = skb->dev;
693 struct cpsw_priv *priv = netdev_priv(ndev);
694
fae50823
M		 695 /* Check whether the queue is stopped due to stalled tx dma, if the
696 * queue is stopped then start the queue as we have free desc for tx
697 */
df828598 698 if (unlikely(netif_queue_stopped(ndev)))
b56d6b3f 699 netif_wake_queue(ndev);
9232b16d 700 cpts_tx_timestamp(priv->cpts, skb);
8dc43ddc
TK		 701 ndev->stats.tx_packets++;
702 ndev->stats.tx_bytes += len;
df828598
M		 703 dev_kfree_skb_any(skb);
704}
705
1a3b5056 706static void cpsw_rx_handler(void *token, int len, int status)
df828598
M		 707{
708 struct sk_buff *skb = token;
b4727e69 709 struct sk_buff *new_skb;
df828598
M		 710 struct net_device *ndev = skb->dev;
711 struct cpsw_priv *priv = netdev_priv(ndev);
712 int ret = 0;
713
d9ba8f9e
M		 714 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
715
16e5c57d 716 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
a0e2c822
M		 717 bool ndev_status = false;
718 struct cpsw_slave *slave = priv->slaves;
719 int n;
720
721 if (priv->data.dual_emac) {
722 /* In dual emac mode check for all interfaces */
723 for (n = priv->data.slaves; n; n--, slave++)
724 if (netif_running(slave->ndev))
725 ndev_status = true;
726 }
727
728 if (ndev_status && (status >= 0)) {
729 /* The packet received is for the interface which
730 * is already down and the other interface is up
731 * and running, intead of freeing which results
732 * in reducing of the number of rx descriptor in
733 * DMA engine, requeue skb back to cpdma.
734 */
735 new_skb = skb;
736 goto requeue;
737 }
738
b4727e69 739 /* the interface is going down, skbs are purged */
df828598
M		 740 dev_kfree_skb_any(skb);
741 return;
742 }
b4727e69
SS		 743
744 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
745 if (new_skb) {
df828598 746 skb_put(skb, len);
9232b16d 747 cpts_rx_timestamp(priv->cpts, skb);
df828598
M		 748 skb->protocol = eth_type_trans(skb, ndev);
749 netif_receive_skb(skb);
8dc43ddc
TK		 750 ndev->stats.rx_bytes += len;
751 ndev->stats.rx_packets++;
b4727e69 752 } else {
8dc43ddc 753 ndev->stats.rx_dropped++;
b4727e69 754 new_skb = skb;
df828598
M		 755 }
756
a0e2c822 757requeue:
b4727e69
SS		 758 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
759 skb_tailroom(new_skb), 0);
760 if (WARN_ON(ret < 0))
761 dev_kfree_skb_any(new_skb);
df828598
M		 762}
763
c03abd84 764static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
df828598
M		 765{
766 struct cpsw_priv *priv = dev_id;
7ce67a38 767
c03abd84
FB		 768 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
769 cpdma_chan_process(priv->txch, 128);
770
771 priv = cpsw_get_slave_priv(priv, 1);
772 if (priv)
773 cpdma_chan_process(priv->txch, 128);
774
775 return IRQ_HANDLED;
776}
777
778static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
779{
780 struct cpsw_priv *priv = dev_id;
781
782 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
fd51cf19
SS		 783
784 cpsw_intr_disable(priv);
a11fbba9
SS		 785 if (priv->irq_enabled == true) {
786 cpsw_disable_irq(priv);
787 priv->irq_enabled = false;
788 }
fd51cf19
SS		 789
790 if (netif_running(priv->ndev)) {
df828598 791 napi_schedule(&priv->napi);
fd51cf19
SS		 792 return IRQ_HANDLED;
793 }
794
795 priv = cpsw_get_slave_priv(priv, 1);
796 if (!priv)
797 return IRQ_NONE;
798
799 if (netif_running(priv->ndev)) {
800 napi_schedule(&priv->napi);
801 return IRQ_HANDLED;
df828598 802 }
fd51cf19 803 return IRQ_NONE;
df828598
M		 804}
805
df828598
M		 806static int cpsw_poll(struct napi_struct *napi, int budget)
807{
808 struct cpsw_priv *priv = napi_to_priv(napi);
809 int num_tx, num_rx;
810
811 num_tx = cpdma_chan_process(priv->txch, 128);
df828598 812
510a1e72 813 num_rx = cpdma_chan_process(priv->rxch, budget);
df828598 814 if (num_rx < budget) {
a11fbba9
SS		 815 struct cpsw_priv *prim_cpsw;
816
df828598
M		 817 napi_complete(napi);
818 cpsw_intr_enable(priv);
a11fbba9
SS		 819 prim_cpsw = cpsw_get_slave_priv(priv, 0);
820 if (prim_cpsw->irq_enabled == false) {
a11fbba9 821 prim_cpsw->irq_enabled = true;
af5c6df7 822 cpsw_enable_irq(priv);
a11fbba9 823 }
df828598
M		 824 }
825
510a1e72
M		 826 if (num_rx || num_tx)
827 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
828 num_rx, num_tx);
829
df828598
M		 830 return num_rx;
831}
832
833static inline void soft_reset(const char *module, void __iomem *reg)
834{
835 unsigned long timeout = jiffies + HZ;
836
837 __raw_writel(1, reg);
838 do {
839 cpu_relax();
840 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
841
842 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
843}
844
845#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
846 ((mac)[2] << 16) | ((mac)[3] << 24))
847#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
848
849static void cpsw_set_slave_mac(struct cpsw_slave *slave,
850 struct cpsw_priv *priv)
851{
9750a3ad
RC		 852 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
853 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 854}
855
856static void _cpsw_adjust_link(struct cpsw_slave *slave,
857 struct cpsw_priv *priv, bool *link)
858{
859 struct phy_device *phy = slave->phy;
860 u32 mac_control = 0;
861 u32 slave_port;
862
863 if (!phy)
864 return;
865
866 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
867
868 if (phy->link) {
869 mac_control = priv->data.mac_control;
870
871 /* enable forwarding */
872 cpsw_ale_control_set(priv->ale, slave_port,
873 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
874
875 if (phy->speed == 1000)
876 mac_control |= BIT(7); /* GIGABITEN */
877 if (phy->duplex)
878 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 879
880 /* set speed_in input in case RMII mode is used in 100Mbps */
881 if (phy->speed == 100)
882 mac_control |= BIT(15);
a81d8762
M		 883 else if (phy->speed == 10)
884 mac_control |= BIT(18); /* In Band mode */
342b7b74 885
1923d6e4
M		 886 if (priv->rx_pause)
887 mac_control |= BIT(3);
888
889 if (priv->tx_pause)
890 mac_control |= BIT(4);
891
df828598
M		 892 *link = true;
893 } else {
894 mac_control = 0;
895 /* disable forwarding */
896 cpsw_ale_control_set(priv->ale, slave_port,
897 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
898 }
899
900 if (mac_control != slave->mac_control) {
901 phy_print_status(phy);
902 __raw_writel(mac_control, &slave->sliver->mac_control);
903 }
904
905 slave->mac_control = mac_control;
906}
907
908static void cpsw_adjust_link(struct net_device *ndev)
909{
910 struct cpsw_priv *priv = netdev_priv(ndev);
911 bool link = false;
912
913 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
914
915 if (link) {
916 netif_carrier_on(ndev);
917 if (netif_running(ndev))
918 netif_wake_queue(ndev);
919 } else {
920 netif_carrier_off(ndev);
921 netif_stop_queue(ndev);
922 }
923}
924
ff5b8ef2
M		 925static int cpsw_get_coalesce(struct net_device *ndev,
926 struct ethtool_coalesce *coal)
927{
928 struct cpsw_priv *priv = netdev_priv(ndev);
929
930 coal->rx_coalesce_usecs = priv->coal_intvl;
931 return 0;
932}
933
934static int cpsw_set_coalesce(struct net_device *ndev,
935 struct ethtool_coalesce *coal)
936{
937 struct cpsw_priv *priv = netdev_priv(ndev);
938 u32 int_ctrl;
939 u32 num_interrupts = 0;
940 u32 prescale = 0;
941 u32 addnl_dvdr = 1;
942 u32 coal_intvl = 0;
943
ff5b8ef2
M		 944 coal_intvl = coal->rx_coalesce_usecs;
945
946 int_ctrl = readl(&priv->wr_regs->int_control);
947 prescale = priv->bus_freq_mhz * 4;
948
a84bc2a9
M		 949 if (!coal->rx_coalesce_usecs) {
950 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
951 goto update_return;
952 }
953
ff5b8ef2
M		 954 if (coal_intvl < CPSW_CMINTMIN_INTVL)
955 coal_intvl = CPSW_CMINTMIN_INTVL;
956
957 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
958 /* Interrupt pacer works with 4us Pulse, we can
959 * throttle further by dilating the 4us pulse.
960 */
961 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
962
963 if (addnl_dvdr > 1) {
964 prescale *= addnl_dvdr;
965 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
966 coal_intvl = (CPSW_CMINTMAX_INTVL
967 * addnl_dvdr);
968 } else {
969 addnl_dvdr = 1;
970 coal_intvl = CPSW_CMINTMAX_INTVL;
971 }
972 }
973
974 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
975 writel(num_interrupts, &priv->wr_regs->rx_imax);
976 writel(num_interrupts, &priv->wr_regs->tx_imax);
977
978 int_ctrl |= CPSW_INTPACEEN;
979 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
980 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
a84bc2a9
M		 981
982update_return:
ff5b8ef2
M		 983 writel(int_ctrl, &priv->wr_regs->int_control);
984
985 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
986 if (priv->data.dual_emac) {
987 int i;
988
989 for (i = 0; i < priv->data.slaves; i++) {
990 priv = netdev_priv(priv->slaves[i].ndev);
991 priv->coal_intvl = coal_intvl;
992 }
993 } else {
994 priv->coal_intvl = coal_intvl;
995 }
996
997 return 0;
998}
999
d9718546
M		 1000static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1001{
1002 switch (sset) {
1003 case ETH_SS_STATS:
1004 return CPSW_STATS_LEN;
1005 default:
1006 return -EOPNOTSUPP;
1007 }
1008}
1009
1010static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1011{
1012 u8 *p = data;
1013 int i;
1014
1015 switch (stringset) {
1016 case ETH_SS_STATS:
1017 for (i = 0; i < CPSW_STATS_LEN; i++) {
1018 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1019 ETH_GSTRING_LEN);
1020 p += ETH_GSTRING_LEN;
1021 }
1022 break;
1023 }
1024}
1025
1026static void cpsw_get_ethtool_stats(struct net_device *ndev,
1027 struct ethtool_stats *stats, u64 *data)
1028{
1029 struct cpsw_priv *priv = netdev_priv(ndev);
1030 struct cpdma_chan_stats rx_stats;
1031 struct cpdma_chan_stats tx_stats;
1032 u32 val;
1033 u8 *p;
1034 int i;
1035
1036 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1037 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1038 cpdma_chan_get_stats(priv->txch, &tx_stats);
1039
1040 for (i = 0; i < CPSW_STATS_LEN; i++) {
1041 switch (cpsw_gstrings_stats[i].type) {
1042 case CPSW_STATS:
1043 val = readl(priv->hw_stats +
1044 cpsw_gstrings_stats[i].stat_offset);
1045 data[i] = val;
1046 break;
1047
1048 case CPDMA_RX_STATS:
1049 p = (u8 *)&rx_stats +
1050 cpsw_gstrings_stats[i].stat_offset;
1051 data[i] = *(u32 *)p;
1052 break;
1053
1054 case CPDMA_TX_STATS:
1055 p = (u8 *)&tx_stats +
1056 cpsw_gstrings_stats[i].stat_offset;
1057 data[i] = *(u32 *)p;
1058 break;
1059 }
1060 }
1061}
1062
d9ba8f9e
M		 1063static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1064{
1065 u32 i;
1066 u32 usage_count = 0;
1067
1068 if (!priv->data.dual_emac)
1069 return 0;
1070
1071 for (i = 0; i < priv->data.slaves; i++)
1072 if (priv->slaves[i].open_stat)
1073 usage_count++;
1074
1075 return usage_count;
1076}
1077
1078static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1079 struct cpsw_priv *priv, struct sk_buff *skb)
1080{
1081 if (!priv->data.dual_emac)
1082 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1083 skb->len, 0);
d9ba8f9e
M		 1084
1085 if (ndev == cpsw_get_slave_ndev(priv, 0))
1086 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1087 skb->len, 1);
d9ba8f9e
M		 1088 else
1089 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1090 skb->len, 2);
d9ba8f9e
M		 1091}
1092
1093static inline void cpsw_add_dual_emac_def_ale_entries(
1094 struct cpsw_priv *priv, struct cpsw_slave *slave,
1095 u32 slave_port)
1096{
1097 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1098
1099 if (priv->version == CPSW_VERSION_1)
1100 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1101 else
1102 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1103 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1104 port_mask, port_mask, 0);
1105 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1106 port_mask, ALE_VLAN, slave->port_vlan, 0);
1107 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1108 priv->host_port, ALE_VLAN, slave->port_vlan);
1109}
1110
1e7a2e21 1111static void soft_reset_slave(struct cpsw_slave *slave)
df828598
M		 1112{
1113 char name[32];
df828598 1114
1e7a2e21 1115 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
df828598 1116 soft_reset(name, &slave->sliver->soft_reset);
1e7a2e21
DM		 1117}
1118
1119static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1120{
1121 u32 slave_port;
1122
1123 soft_reset_slave(slave);
df828598
M		 1124
1125 /* setup priority mapping */
1126 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad
RC		 1127
1128 switch (priv->version) {
1129 case CPSW_VERSION_1:
1130 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1131 break;
1132 case CPSW_VERSION_2:
c193f365 1133 case CPSW_VERSION_3:
926489be 1134 case CPSW_VERSION_4:
9750a3ad
RC		 1135 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1136 break;
1137 }
df828598
M		 1138
1139 /* setup max packet size, and mac address */
1140 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1141 cpsw_set_slave_mac(slave, priv);
1142
1143 slave->mac_control = 0; /* no link yet */
1144
1145 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1146
d9ba8f9e
M		 1147 if (priv->data.dual_emac)
1148 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1149 else
1150 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1151 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
df828598
M		 1152
1153 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
f9a8f83b 1154 &cpsw_adjust_link, slave->data->phy_if);
df828598
M		 1155 if (IS_ERR(slave->phy)) {
1156 dev_err(priv->dev, "phy %s not found on slave %d\n",
1157 slave->data->phy_id, slave->slave_num);
1158 slave->phy = NULL;
1159 } else {
1160 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1161 slave->phy->phy_id);
1162 phy_start(slave->phy);
388367a5
M		 1163
1164 /* Configure GMII_SEL register */
1165 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1166 slave->slave_num);
df828598
M		 1167 }
1168}
1169
3b72c2fe
M		 1170static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1171{
1172 const int vlan = priv->data.default_vlan;
1173 const int port = priv->host_port;
1174 u32 reg;
1175 int i;
1e5c4bc4 1176 int unreg_mcast_mask;
3b72c2fe
M		 1177
1178 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1179 CPSW2_PORT_VLAN;
1180
1181 writel(vlan, &priv->host_port_regs->port_vlan);
1182
0237c110 1183 for (i = 0; i < priv->data.slaves; i++)
3b72c2fe
M		 1184 slave_write(priv->slaves + i, vlan, reg);
1185
1e5c4bc4
LS		 1186 if (priv->ndev->flags & IFF_ALLMULTI)
1187 unreg_mcast_mask = ALE_ALL_PORTS;
1188 else
1189 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1190
3b72c2fe
M		 1191 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1192 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1e5c4bc4 1193 unreg_mcast_mask << port);
3b72c2fe
M		 1194}
1195
df828598
M		 1196static void cpsw_init_host_port(struct cpsw_priv *priv)
1197{
3b72c2fe 1198 u32 control_reg;
d9ba8f9e 1199 u32 fifo_mode;
3b72c2fe 1200
df828598
M		 1201 /* soft reset the controller and initialize ale */
1202 soft_reset("cpsw", &priv->regs->soft_reset);
1203 cpsw_ale_start(priv->ale);
1204
1205 /* switch to vlan unaware mode */
3b72c2fe
M		 1206 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1207 CPSW_ALE_VLAN_AWARE);
1208 control_reg = readl(&priv->regs->control);
1209 control_reg |= CPSW_VLAN_AWARE;
1210 writel(control_reg, &priv->regs->control);
d9ba8f9e
M		 1211 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1212 CPSW_FIFO_NORMAL_MODE;
1213 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
df828598
M		 1214
1215 /* setup host port priority mapping */
1216 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1217 &priv->host_port_regs->cpdma_tx_pri_map);
1218 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1219
1220 cpsw_ale_control_set(priv->ale, priv->host_port,
1221 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1222
d9ba8f9e
M		 1223 if (!priv->data.dual_emac) {
1224 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1225 0, 0);
1226 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1227 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1228 }
df828598
M		 1229}
1230
aacebbf8
SS		 1231static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1232{
3995d265
SP		 1233 u32 slave_port;
1234
1235 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1236
aacebbf8
SS		 1237 if (!slave->phy)
1238 return;
1239 phy_stop(slave->phy);
1240 phy_disconnect(slave->phy);
1241 slave->phy = NULL;
3995d265
SP		 1242 cpsw_ale_control_set(priv->ale, slave_port,
1243 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
aacebbf8
SS		 1244}
1245
df828598
M		 1246static int cpsw_ndo_open(struct net_device *ndev)
1247{
1248 struct cpsw_priv *priv = netdev_priv(ndev);
a11fbba9 1249 struct cpsw_priv *prim_cpsw;
df828598
M		 1250 int i, ret;
1251 u32 reg;
1252
d9ba8f9e
M		 1253 if (!cpsw_common_res_usage_state(priv))
1254 cpsw_intr_disable(priv);
df828598
M		 1255 netif_carrier_off(ndev);
1256
f150bd7f 1257 pm_runtime_get_sync(&priv->pdev->dev);
df828598 1258
549985ee 1259 reg = priv->version;
df828598
M		 1260
1261 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1262 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1263 CPSW_RTL_VERSION(reg));
1264
1265 /* initialize host and slave ports */
d9ba8f9e
M		 1266 if (!cpsw_common_res_usage_state(priv))
1267 cpsw_init_host_port(priv);
df828598
M		 1268 for_each_slave(priv, cpsw_slave_open, priv);
1269
3b72c2fe 1270 /* Add default VLAN */
e6afea0b
M		 1271 if (!priv->data.dual_emac)
1272 cpsw_add_default_vlan(priv);
1273 else
1274 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1275 ALE_ALL_PORTS << priv->host_port,
1276 ALE_ALL_PORTS << priv->host_port, 0, 0);
3b72c2fe 1277
d9ba8f9e
M		 1278 if (!cpsw_common_res_usage_state(priv)) {
1279 /* setup tx dma to fixed prio and zero offset */
1280 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1281 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
df828598 1282
d9ba8f9e
M		 1283 /* disable priority elevation */
1284 __raw_writel(0, &priv->regs->ptype);
df828598 1285
d9ba8f9e
M		 1286 /* enable statistics collection only on all ports */
1287 __raw_writel(0x7, &priv->regs->stat_port_en);
df828598 1288
1923d6e4
M		 1289 /* Enable internal fifo flow control */
1290 writel(0x7, &priv->regs->flow_control);
1291
d9ba8f9e
M		 1292 if (WARN_ON(!priv->data.rx_descs))
1293 priv->data.rx_descs = 128;
df828598 1294
d9ba8f9e
M		 1295 for (i = 0; i < priv->data.rx_descs; i++) {
1296 struct sk_buff *skb;
df828598 1297
d9ba8f9e 1298 ret = -ENOMEM;
aacebbf8
SS		 1299 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1300 priv->rx_packet_max, GFP_KERNEL);
d9ba8f9e 1301 if (!skb)
aacebbf8 1302 goto err_cleanup;
d9ba8f9e 1303 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
aef614e1 1304 skb_tailroom(skb), 0);
aacebbf8
SS		 1305 if (ret < 0) {
1306 kfree_skb(skb);
1307 goto err_cleanup;
1308 }
d9ba8f9e
M		 1309 }
1310 /* continue even if we didn't manage to submit all
1311 * receive descs
1312 */
1313 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
f280e89a
M		 1314
1315 if (cpts_register(&priv->pdev->dev, priv->cpts,
1316 priv->data.cpts_clock_mult,
1317 priv->data.cpts_clock_shift))
1318 dev_err(priv->dev, "error registering cpts device\n");
1319
df828598 1320 }
df828598 1321
ff5b8ef2
M		 1322 /* Enable Interrupt pacing if configured */
1323 if (priv->coal_intvl != 0) {
1324 struct ethtool_coalesce coal;
1325
1326 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1327 cpsw_set_coalesce(ndev, &coal);
1328 }
1329
f63a975e
M		 1330 napi_enable(&priv->napi);
1331 cpdma_ctlr_start(priv->dma);
1332 cpsw_intr_enable(priv);
f63a975e 1333
a11fbba9
SS		 1334 prim_cpsw = cpsw_get_slave_priv(priv, 0);
1335 if (prim_cpsw->irq_enabled == false) {
1336 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1337 prim_cpsw->irq_enabled = true;
1338 cpsw_enable_irq(prim_cpsw);
1339 }
1340 }
1341
d9ba8f9e
M		 1342 if (priv->data.dual_emac)
1343 priv->slaves[priv->emac_port].open_stat = true;
df828598 1344 return 0;
df828598 1345
aacebbf8
SS		 1346err_cleanup:
1347 cpdma_ctlr_stop(priv->dma);
1348 for_each_slave(priv, cpsw_slave_stop, priv);
1349 pm_runtime_put_sync(&priv->pdev->dev);
1350 netif_carrier_off(priv->ndev);
1351 return ret;
df828598
M		 1352}
1353
1354static int cpsw_ndo_stop(struct net_device *ndev)
1355{
1356 struct cpsw_priv *priv = netdev_priv(ndev);
1357
1358 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
df828598
M		 1359 netif_stop_queue(priv->ndev);
1360 napi_disable(&priv->napi);
1361 netif_carrier_off(priv->ndev);
d9ba8f9e
M		 1362
1363 if (cpsw_common_res_usage_state(priv) <= 1) {
f280e89a 1364 cpts_unregister(priv->cpts);
d9ba8f9e
M		 1365 cpsw_intr_disable(priv);
1366 cpdma_ctlr_int_ctrl(priv->dma, false);
1367 cpdma_ctlr_stop(priv->dma);
1368 cpsw_ale_stop(priv->ale);
1369 }
df828598 1370 for_each_slave(priv, cpsw_slave_stop, priv);
f150bd7f 1371 pm_runtime_put_sync(&priv->pdev->dev);
d9ba8f9e
M		 1372 if (priv->data.dual_emac)
1373 priv->slaves[priv->emac_port].open_stat = false;
df828598
M		 1374 return 0;
1375}
1376
1377static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1378 struct net_device *ndev)
1379{
1380 struct cpsw_priv *priv = netdev_priv(ndev);
1381 int ret;
1382
1383 ndev->trans_start = jiffies;
1384
1385 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1386 cpsw_err(priv, tx_err, "packet pad failed\n");
8dc43ddc 1387 ndev->stats.tx_dropped++;
df828598
M		 1388 return NETDEV_TX_OK;
1389 }
1390
9232b16d
M		 1391 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1392 priv->cpts->tx_enable)
2e5b38ab
RC		 1393 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1394
1395 skb_tx_timestamp(skb);
1396
d9ba8f9e 1397 ret = cpsw_tx_packet_submit(ndev, priv, skb);
df828598
M		 1398 if (unlikely(ret != 0)) {
1399 cpsw_err(priv, tx_err, "desc submit failed\n");
1400 goto fail;
1401 }
1402
fae50823
M		 1403 /* If there is no more tx desc left free then we need to
1404 * tell the kernel to stop sending us tx frames.
1405 */
d35162f8 1406 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
fae50823
M		 1407 netif_stop_queue(ndev);
1408
df828598
M		 1409 return NETDEV_TX_OK;
1410fail:
8dc43ddc 1411 ndev->stats.tx_dropped++;
df828598
M		 1412 netif_stop_queue(ndev);
1413 return NETDEV_TX_BUSY;
1414}
1415
2e5b38ab
RC		 1416#ifdef CONFIG_TI_CPTS
1417
1418static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1419{
e86ac13b 1420 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
2e5b38ab
RC		 1421 u32 ts_en, seq_id;
1422
9232b16d 1423 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
2e5b38ab
RC		 1424 slave_write(slave, 0, CPSW1_TS_CTL);
1425 return;
1426 }
1427
1428 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1429 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1430
9232b16d 1431 if (priv->cpts->tx_enable)
2e5b38ab
RC		 1432 ts_en |= CPSW_V1_TS_TX_EN;
1433
9232b16d 1434 if (priv->cpts->rx_enable)
2e5b38ab
RC		 1435 ts_en |= CPSW_V1_TS_RX_EN;
1436
1437 slave_write(slave, ts_en, CPSW1_TS_CTL);
1438 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1439}
1440
1441static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1442{
d9ba8f9e 1443 struct cpsw_slave *slave;
2e5b38ab
RC		 1444 u32 ctrl, mtype;
1445
d9ba8f9e
M		 1446 if (priv->data.dual_emac)
1447 slave = &priv->slaves[priv->emac_port];
1448 else
e86ac13b 1449 slave = &priv->slaves[priv->data.active_slave];
d9ba8f9e 1450
2e5b38ab 1451 ctrl = slave_read(slave, CPSW2_CONTROL);
09c55372
GC		 1452 switch (priv->version) {
1453 case CPSW_VERSION_2:
1454 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2e5b38ab 1455
09c55372
GC		 1456 if (priv->cpts->tx_enable)
1457 ctrl |= CTRL_V2_TX_TS_BITS;
2e5b38ab 1458
09c55372
GC		 1459 if (priv->cpts->rx_enable)
1460 ctrl |= CTRL_V2_RX_TS_BITS;
1461 break;
1462 case CPSW_VERSION_3:
1463 default:
1464 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1465
1466 if (priv->cpts->tx_enable)
1467 ctrl |= CTRL_V3_TX_TS_BITS;
1468
1469 if (priv->cpts->rx_enable)
1470 ctrl |= CTRL_V3_RX_TS_BITS;
1471 break;
1472 }
2e5b38ab
RC		 1473
1474 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1475
1476 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1477 slave_write(slave, ctrl, CPSW2_CONTROL);
1478 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1479}
1480
a5b4145b 1481static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2e5b38ab 1482{
3177bf6f 1483 struct cpsw_priv *priv = netdev_priv(dev);
9232b16d 1484 struct cpts *cpts = priv->cpts;
2e5b38ab
RC		 1485 struct hwtstamp_config cfg;
1486
2ee91e54 1487 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1488 priv->version != CPSW_VERSION_2 &&
1489 priv->version != CPSW_VERSION_3)
2ee91e54
BH		 1490 return -EOPNOTSUPP;
1491
2e5b38ab
RC		 1492 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1493 return -EFAULT;
1494
1495 /* reserved for future extensions */
1496 if (cfg.flags)
1497 return -EINVAL;
1498
2ee91e54 1499 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2e5b38ab 1500 return -ERANGE;
2e5b38ab
RC		 1501
1502 switch (cfg.rx_filter) {
1503 case HWTSTAMP_FILTER_NONE:
1504 cpts->rx_enable = 0;
1505 break;
1506 case HWTSTAMP_FILTER_ALL:
1507 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1508 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1509 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1510 return -ERANGE;
1511 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1512 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1513 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1514 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1515 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1516 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1517 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1518 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1519 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1520 cpts->rx_enable = 1;
1521 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1522 break;
1523 default:
1524 return -ERANGE;
1525 }
1526
2ee91e54
BH		 1527 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1528
2e5b38ab
RC		 1529 switch (priv->version) {
1530 case CPSW_VERSION_1:
1531 cpsw_hwtstamp_v1(priv);
1532 break;
1533 case CPSW_VERSION_2:
f7d403cb 1534 case CPSW_VERSION_3:
2e5b38ab
RC		 1535 cpsw_hwtstamp_v2(priv);
1536 break;
1537 default:
2ee91e54 1538 WARN_ON(1);
2e5b38ab
RC		 1539 }
1540
1541 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1542}
1543
a5b4145b
BH		 1544static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1545{
1546 struct cpsw_priv *priv = netdev_priv(dev);
1547 struct cpts *cpts = priv->cpts;
1548 struct hwtstamp_config cfg;
1549
1550 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1551 priv->version != CPSW_VERSION_2 &&
1552 priv->version != CPSW_VERSION_3)
a5b4145b
BH		 1553 return -EOPNOTSUPP;
1554
1555 cfg.flags = 0;
1556 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1557 cfg.rx_filter = (cpts->rx_enable ?
1558 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1559
1560 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1561}
1562
2e5b38ab
RC		 1563#endif /*CONFIG_TI_CPTS*/
1564
1565static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1566{
11f2c988 1567 struct cpsw_priv *priv = netdev_priv(dev);
11f2c988
M		 1568 int slave_no = cpsw_slave_index(priv);
1569
2e5b38ab
RC		 1570 if (!netif_running(dev))
1571 return -EINVAL;
1572
11f2c988 1573 switch (cmd) {
2e5b38ab 1574#ifdef CONFIG_TI_CPTS
11f2c988 1575 case SIOCSHWTSTAMP:
a5b4145b
BH		 1576 return cpsw_hwtstamp_set(dev, req);
1577 case SIOCGHWTSTAMP:
1578 return cpsw_hwtstamp_get(dev, req);
2e5b38ab 1579#endif
11f2c988
M		 1580 }
1581
c1b59947
SS		 1582 if (!priv->slaves[slave_no].phy)
1583 return -EOPNOTSUPP;
1584 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
2e5b38ab
RC		 1585}
1586
df828598
M		 1587static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1588{
1589 struct cpsw_priv *priv = netdev_priv(ndev);
1590
1591 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
8dc43ddc 1592 ndev->stats.tx_errors++;
df828598
M		 1593 cpsw_intr_disable(priv);
1594 cpdma_ctlr_int_ctrl(priv->dma, false);
1595 cpdma_chan_stop(priv->txch);
1596 cpdma_chan_start(priv->txch);
1597 cpdma_ctlr_int_ctrl(priv->dma, true);
1598 cpsw_intr_enable(priv);
df828598
M		 1599}
1600
dcfd8d58
M		 1601static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1602{
1603 struct cpsw_priv *priv = netdev_priv(ndev);
1604 struct sockaddr *addr = (struct sockaddr *)p;
1605 int flags = 0;
1606 u16 vid = 0;
1607
1608 if (!is_valid_ether_addr(addr->sa_data))
1609 return -EADDRNOTAVAIL;
1610
1611 if (priv->data.dual_emac) {
1612 vid = priv->slaves[priv->emac_port].port_vlan;
1613 flags = ALE_VLAN;
1614 }
1615
1616 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1617 flags, vid);
1618 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1619 flags, vid);
1620
1621 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1622 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1623 for_each_slave(priv, cpsw_set_slave_mac, priv);
1624
1625 return 0;
1626}
1627
df828598
M		 1628#ifdef CONFIG_NET_POLL_CONTROLLER
1629static void cpsw_ndo_poll_controller(struct net_device *ndev)
1630{
1631 struct cpsw_priv *priv = netdev_priv(ndev);
1632
1633 cpsw_intr_disable(priv);
1634 cpdma_ctlr_int_ctrl(priv->dma, false);
92cb13fb
FB		 1635 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1636 cpsw_tx_interrupt(priv->irqs_table[1], priv);
df828598
M		 1637 cpdma_ctlr_int_ctrl(priv->dma, true);
1638 cpsw_intr_enable(priv);
df828598
M		 1639}
1640#endif
1641
3b72c2fe
M		 1642static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1643 unsigned short vid)
1644{
1645 int ret;
9f6bd8fa
M		 1646 int unreg_mcast_mask = 0;
1647 u32 port_mask;
1e5c4bc4 1648
9f6bd8fa
M		 1649 if (priv->data.dual_emac) {
1650 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
3b72c2fe 1651
9f6bd8fa
M		 1652 if (priv->ndev->flags & IFF_ALLMULTI)
1653 unreg_mcast_mask = port_mask;
1654 } else {
1655 port_mask = ALE_ALL_PORTS;
1656
1657 if (priv->ndev->flags & IFF_ALLMULTI)
1658 unreg_mcast_mask = ALE_ALL_PORTS;
1659 else
1660 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1661 }
3b72c2fe 1662
9f6bd8fa 1663 ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1e5c4bc4 1664 unreg_mcast_mask << priv->host_port);
3b72c2fe
M		 1665 if (ret != 0)
1666 return ret;
1667
1668 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1669 priv->host_port, ALE_VLAN, vid);
1670 if (ret != 0)
1671 goto clean_vid;
1672
1673 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
9f6bd8fa 1674 port_mask, ALE_VLAN, vid, 0);
3b72c2fe
M		 1675 if (ret != 0)
1676 goto clean_vlan_ucast;
1677 return 0;
1678
1679clean_vlan_ucast:
1680 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1681 priv->host_port, ALE_VLAN, vid);
1682clean_vid:
1683 cpsw_ale_del_vlan(priv->ale, vid, 0);
1684 return ret;
1685}
1686
1687static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
80d5c368 1688 __be16 proto, u16 vid)
3b72c2fe
M		 1689{
1690 struct cpsw_priv *priv = netdev_priv(ndev);
1691
1692 if (vid == priv->data.default_vlan)
1693 return 0;
1694
02a54164
M		 1695 if (priv->data.dual_emac) {
1696 /* In dual EMAC, reserved VLAN id should not be used for
1697 * creating VLAN interfaces as this can break the dual
1698 * EMAC port separation
1699 */
1700 int i;
1701
1702 for (i = 0; i < priv->data.slaves; i++) {
1703 if (vid == priv->slaves[i].port_vlan)
1704 return -EINVAL;
1705 }
1706 }
1707
3b72c2fe
M		 1708 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1709 return cpsw_add_vlan_ale_entry(priv, vid);
1710}
1711
1712static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
80d5c368 1713 __be16 proto, u16 vid)
3b72c2fe
M		 1714{
1715 struct cpsw_priv *priv = netdev_priv(ndev);
1716 int ret;
1717
1718 if (vid == priv->data.default_vlan)
1719 return 0;
1720
02a54164
M		 1721 if (priv->data.dual_emac) {
1722 int i;
1723
1724 for (i = 0; i < priv->data.slaves; i++) {
1725 if (vid == priv->slaves[i].port_vlan)
1726 return -EINVAL;
1727 }
1728 }
1729
3b72c2fe
M		 1730 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1731 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1732 if (ret != 0)
1733 return ret;
1734
1735 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1736 priv->host_port, ALE_VLAN, vid);
1737 if (ret != 0)
1738 return ret;
1739
1740 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1741 0, ALE_VLAN, vid);
1742}
1743
df828598
M		 1744static const struct net_device_ops cpsw_netdev_ops = {
1745 .ndo_open = cpsw_ndo_open,
1746 .ndo_stop = cpsw_ndo_stop,
1747 .ndo_start_xmit = cpsw_ndo_start_xmit,
dcfd8d58 1748 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2e5b38ab 1749 .ndo_do_ioctl = cpsw_ndo_ioctl,
df828598 1750 .ndo_validate_addr = eth_validate_addr,
5c473ed2 1751 .ndo_change_mtu = eth_change_mtu,
df828598 1752 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
5c50a856 1753 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
df828598
M		 1754#ifdef CONFIG_NET_POLL_CONTROLLER
1755 .ndo_poll_controller = cpsw_ndo_poll_controller,
1756#endif
3b72c2fe
M		 1757 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1758 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
df828598
M		 1759};
1760
52c4f0ec
M		 1761static int cpsw_get_regs_len(struct net_device *ndev)
1762{
1763 struct cpsw_priv *priv = netdev_priv(ndev);
1764
1765 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1766}
1767
1768static void cpsw_get_regs(struct net_device *ndev,
1769 struct ethtool_regs *regs, void *p)
1770{
1771 struct cpsw_priv *priv = netdev_priv(ndev);
1772 u32 *reg = p;
1773
1774 /* update CPSW IP version */
1775 regs->version = priv->version;
1776
1777 cpsw_ale_dump(priv->ale, reg);
1778}
1779
df828598
M		 1780static void cpsw_get_drvinfo(struct net_device *ndev,
1781 struct ethtool_drvinfo *info)
1782{
1783 struct cpsw_priv *priv = netdev_priv(ndev);
7826d43f 1784
52c4f0ec 1785 strlcpy(info->driver, "cpsw", sizeof(info->driver));
7826d43f
JP		 1786 strlcpy(info->version, "1.0", sizeof(info->version));
1787 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
52c4f0ec 1788 info->regdump_len = cpsw_get_regs_len(ndev);
df828598
M		 1789}
1790
1791static u32 cpsw_get_msglevel(struct net_device *ndev)
1792{
1793 struct cpsw_priv *priv = netdev_priv(ndev);
1794 return priv->msg_enable;
1795}
1796
1797static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1798{
1799 struct cpsw_priv *priv = netdev_priv(ndev);
1800 priv->msg_enable = value;
1801}
1802
2e5b38ab
RC		 1803static int cpsw_get_ts_info(struct net_device *ndev,
1804 struct ethtool_ts_info *info)
1805{
1806#ifdef CONFIG_TI_CPTS
1807 struct cpsw_priv *priv = netdev_priv(ndev);
1808
1809 info->so_timestamping =
1810 SOF_TIMESTAMPING_TX_HARDWARE |
1811 SOF_TIMESTAMPING_TX_SOFTWARE |
1812 SOF_TIMESTAMPING_RX_HARDWARE |
1813 SOF_TIMESTAMPING_RX_SOFTWARE |
1814 SOF_TIMESTAMPING_SOFTWARE |
1815 SOF_TIMESTAMPING_RAW_HARDWARE;
9232b16d 1816 info->phc_index = priv->cpts->phc_index;
2e5b38ab
RC		 1817 info->tx_types =
1818 (1 << HWTSTAMP_TX_OFF) |
1819 (1 << HWTSTAMP_TX_ON);
1820 info->rx_filters =
1821 (1 << HWTSTAMP_FILTER_NONE) |
1822 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1823#else
1824 info->so_timestamping =
1825 SOF_TIMESTAMPING_TX_SOFTWARE |
1826 SOF_TIMESTAMPING_RX_SOFTWARE |
1827 SOF_TIMESTAMPING_SOFTWARE;
1828 info->phc_index = -1;
1829 info->tx_types = 0;
1830 info->rx_filters = 0;
1831#endif
1832 return 0;
1833}
1834
d3bb9c58
M		 1835static int cpsw_get_settings(struct net_device *ndev,
1836 struct ethtool_cmd *ecmd)
1837{
1838 struct cpsw_priv *priv = netdev_priv(ndev);
1839 int slave_no = cpsw_slave_index(priv);
1840
1841 if (priv->slaves[slave_no].phy)
1842 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1843 else
1844 return -EOPNOTSUPP;
1845}
1846
1847static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1848{
1849 struct cpsw_priv *priv = netdev_priv(ndev);
1850 int slave_no = cpsw_slave_index(priv);
1851
1852 if (priv->slaves[slave_no].phy)
1853 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1854 else
1855 return -EOPNOTSUPP;
1856}
1857
d8a64420
MU		 1858static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1859{
1860 struct cpsw_priv *priv = netdev_priv(ndev);
1861 int slave_no = cpsw_slave_index(priv);
1862
1863 wol->supported = 0;
1864 wol->wolopts = 0;
1865
1866 if (priv->slaves[slave_no].phy)
1867 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1868}
1869
1870static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1871{
1872 struct cpsw_priv *priv = netdev_priv(ndev);
1873 int slave_no = cpsw_slave_index(priv);
1874
1875 if (priv->slaves[slave_no].phy)
1876 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1877 else
1878 return -EOPNOTSUPP;
1879}
1880
1923d6e4
M		 1881static void cpsw_get_pauseparam(struct net_device *ndev,
1882 struct ethtool_pauseparam *pause)
1883{
1884 struct cpsw_priv *priv = netdev_priv(ndev);
1885
1886 pause->autoneg = AUTONEG_DISABLE;
1887 pause->rx_pause = priv->rx_pause ? true : false;
1888 pause->tx_pause = priv->tx_pause ? true : false;
1889}
1890
1891static int cpsw_set_pauseparam(struct net_device *ndev,
1892 struct ethtool_pauseparam *pause)
1893{
1894 struct cpsw_priv *priv = netdev_priv(ndev);
1895 bool link;
1896
1897 priv->rx_pause = pause->rx_pause ? true : false;
1898 priv->tx_pause = pause->tx_pause ? true : false;
1899
1900 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1901
1902 return 0;
1903}
1904
df828598
M		 1905static const struct ethtool_ops cpsw_ethtool_ops = {
1906 .get_drvinfo = cpsw_get_drvinfo,
1907 .get_msglevel = cpsw_get_msglevel,
1908 .set_msglevel = cpsw_set_msglevel,
1909 .get_link = ethtool_op_get_link,
2e5b38ab 1910 .get_ts_info = cpsw_get_ts_info,
d3bb9c58
M		 1911 .get_settings = cpsw_get_settings,
1912 .set_settings = cpsw_set_settings,
ff5b8ef2
M		 1913 .get_coalesce = cpsw_get_coalesce,
1914 .set_coalesce = cpsw_set_coalesce,
d9718546
M		 1915 .get_sset_count = cpsw_get_sset_count,
1916 .get_strings = cpsw_get_strings,
1917 .get_ethtool_stats = cpsw_get_ethtool_stats,
1923d6e4
M		 1918 .get_pauseparam = cpsw_get_pauseparam,
1919 .set_pauseparam = cpsw_set_pauseparam,
d8a64420
MU		 1920 .get_wol = cpsw_get_wol,
1921 .set_wol = cpsw_set_wol,
52c4f0ec
M		 1922 .get_regs_len = cpsw_get_regs_len,
1923 .get_regs = cpsw_get_regs,
df828598
M		 1924};
1925
549985ee
RC		 1926static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1927 u32 slave_reg_ofs, u32 sliver_reg_ofs)
df828598
M		 1928{
1929 void __iomem *regs = priv->regs;
1930 int slave_num = slave->slave_num;
1931 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1932
1933 slave->data = data;
549985ee
RC		 1934 slave->regs = regs + slave_reg_ofs;
1935 slave->sliver = regs + sliver_reg_ofs;
d9ba8f9e 1936 slave->port_vlan = data->dual_emac_res_vlan;
df828598
M		 1937}
1938
0ba517b1
MP		 1939#define AM33XX_CTRL_MAC_LO_REG(id) (0x630 + 0x8 * id)
1940#define AM33XX_CTRL_MAC_HI_REG(id) (0x630 + 0x8 * id + 0x4)
1941
1942static int cpsw_am33xx_cm_get_macid(struct device *dev, int slave,
1943 u8 *mac_addr)
1944{
1945 u32 macid_lo;
1946 u32 macid_hi;
1947 struct regmap *syscon;
1948
1949 syscon = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
1950 if (IS_ERR(syscon)) {
1951 if (PTR_ERR(syscon) == -ENODEV)
1952 return 0;
1953 return PTR_ERR(syscon);
1954 }
1955
1956 regmap_read(syscon, AM33XX_CTRL_MAC_LO_REG(slave), &macid_lo);
1957 regmap_read(syscon, AM33XX_CTRL_MAC_HI_REG(slave), &macid_hi);
1958
1959 mac_addr[5] = (macid_lo >> 8) & 0xff;
1960 mac_addr[4] = macid_lo & 0xff;
1961 mac_addr[3] = (macid_hi >> 24) & 0xff;
1962 mac_addr[2] = (macid_hi >> 16) & 0xff;
1963 mac_addr[1] = (macid_hi >> 8) & 0xff;
1964 mac_addr[0] = macid_hi & 0xff;
1965
1966 return 0;
1967}
1968
2eb32b0a
M		 1969static int cpsw_probe_dt(struct cpsw_platform_data *data,
1970 struct platform_device *pdev)
1971{
1972 struct device_node *node = pdev->dev.of_node;
1973 struct device_node *slave_node;
1974 int i = 0, ret;
1975 u32 prop;
1976
1977 if (!node)
1978 return -EINVAL;
1979
1980 if (of_property_read_u32(node, "slaves", &prop)) {
88c99ff6 1981 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2eb32b0a
M		 1982 return -EINVAL;
1983 }
1984 data->slaves = prop;
1985
e86ac13b 1986 if (of_property_read_u32(node, "active_slave", &prop)) {
88c99ff6 1987 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
aa1a15e2 1988 return -EINVAL;
78ca0b28 1989 }
e86ac13b 1990 data->active_slave = prop;
78ca0b28 1991
00ab94ee 1992 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
88c99ff6 1993 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
aa1a15e2 1994 return -EINVAL;
00ab94ee
RC		 1995 }
1996 data->cpts_clock_mult = prop;
1997
1998 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
88c99ff6 1999 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
aa1a15e2 2000 return -EINVAL;
00ab94ee
RC		 2001 }
2002 data->cpts_clock_shift = prop;
2003
aa1a15e2
DM		 2004 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2005 * sizeof(struct cpsw_slave_data),
2006 GFP_KERNEL);
b2adaca9 2007 if (!data->slave_data)
aa1a15e2 2008 return -ENOMEM;
2eb32b0a 2009
2eb32b0a 2010 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
88c99ff6 2011 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
aa1a15e2 2012 return -EINVAL;
2eb32b0a
M		 2013 }
2014 data->channels = prop;
2015
2eb32b0a 2016 if (of_property_read_u32(node, "ale_entries", &prop)) {
88c99ff6 2017 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
aa1a15e2 2018 return -EINVAL;
2eb32b0a
M		 2019 }
2020 data->ale_entries = prop;
2021
2eb32b0a 2022 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
88c99ff6 2023 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
aa1a15e2 2024 return -EINVAL;
2eb32b0a
M		 2025 }
2026 data->bd_ram_size = prop;
2027
2028 if (of_property_read_u32(node, "rx_descs", &prop)) {
88c99ff6 2029 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
aa1a15e2 2030 return -EINVAL;
2eb32b0a
M		 2031 }
2032 data->rx_descs = prop;
2033
2034 if (of_property_read_u32(node, "mac_control", &prop)) {
88c99ff6 2035 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
aa1a15e2 2036 return -EINVAL;
2eb32b0a
M		 2037 }
2038 data->mac_control = prop;
2039
281abd96
MP		 2040 if (of_property_read_bool(node, "dual_emac"))
2041 data->dual_emac = 1;
d9ba8f9e 2042
549985ee
RC		 2043 /*
2044 * Populate all the child nodes here...
2045 */
2046 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2047 /* We do not want to force this, as in some cases may not have child */
2048 if (ret)
88c99ff6 2049 dev_warn(&pdev->dev, "Doesn't have any child node\n");
549985ee 2050
f468b10e 2051 for_each_child_of_node(node, slave_node) {
2eb32b0a 2052 struct cpsw_slave_data *slave_data = data->slave_data + i;
2eb32b0a 2053 const void *mac_addr = NULL;
549985ee
RC		 2054 u32 phyid;
2055 int lenp;
2056 const __be32 *parp;
2057 struct device_node *mdio_node;
2058 struct platform_device *mdio;
2059
f468b10e
MP		 2060 /* This is no slave child node, continue */
2061 if (strcmp(slave_node->name, "slave"))
2062 continue;
2063
549985ee 2064 parp = of_get_property(slave_node, "phy_id", &lenp);
ce16294f 2065 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
88c99ff6 2066 dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
47276fcc 2067 goto no_phy_slave;
2eb32b0a 2068 }
549985ee
RC		 2069 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2070 phyid = be32_to_cpup(parp+1);
2071 mdio = of_find_device_by_node(mdio_node);
60e71ab5 2072 of_node_put(mdio_node);
6954cc1f 2073 if (!mdio) {
56fdb2e0 2074 dev_err(&pdev->dev, "Missing mdio platform device\n");
6954cc1f 2075 return -EINVAL;
f8d56d8f 2076 }
59993f48
JH		 2077 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2078 PHY_ID_FMT, mdio->name, phyid);
2eb32b0a 2079
47276fcc
M		 2080 slave_data->phy_if = of_get_phy_mode(slave_node);
2081 if (slave_data->phy_if < 0) {
2082 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2083 i);
2084 return slave_data->phy_if;
2085 }
2086
2087no_phy_slave:
2eb32b0a 2088 mac_addr = of_get_mac_address(slave_node);
0ba517b1 2089 if (mac_addr) {
2eb32b0a 2090 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
0ba517b1
MP		 2091 } else {
2092 if (of_machine_is_compatible("ti,am33xx")) {
2093 ret = cpsw_am33xx_cm_get_macid(&pdev->dev, i,
2094 slave_data->mac_addr);
2095 if (ret)
2096 return ret;
2097 }
2098 }
d9ba8f9e 2099 if (data->dual_emac) {
91c4166c 2100 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
d9ba8f9e 2101 &prop)) {
88c99ff6 2102 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
d9ba8f9e 2103 slave_data->dual_emac_res_vlan = i+1;
88c99ff6
GC		 2104 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2105 slave_data->dual_emac_res_vlan, i);
d9ba8f9e
M		 2106 } else {
2107 slave_data->dual_emac_res_vlan = prop;
2108 }
2109 }
2110
2eb32b0a 2111 i++;
3a27bfac
M		 2112 if (i == data->slaves)
2113 break;
2eb32b0a
M		 2114 }
2115
2116 return 0;
2eb32b0a
M		 2117}
2118
d9ba8f9e
M		 2119static int cpsw_probe_dual_emac(struct platform_device *pdev,
2120 struct cpsw_priv *priv)
2121{
2122 struct cpsw_platform_data *data = &priv->data;
2123 struct net_device *ndev;
2124 struct cpsw_priv *priv_sl2;
2125 int ret = 0, i;
2126
2127 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2128 if (!ndev) {
88c99ff6 2129 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
d9ba8f9e
M		 2130 return -ENOMEM;
2131 }
2132
2133 priv_sl2 = netdev_priv(ndev);
2134 spin_lock_init(&priv_sl2->lock);
2135 priv_sl2->data = *data;
2136 priv_sl2->pdev = pdev;
2137 priv_sl2->ndev = ndev;
2138 priv_sl2->dev = &ndev->dev;
2139 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2140 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2141
2142 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2143 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2144 ETH_ALEN);
88c99ff6 2145 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2146 } else {
2147 random_ether_addr(priv_sl2->mac_addr);
88c99ff6 2148 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2149 }
2150 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2151
2152 priv_sl2->slaves = priv->slaves;
2153 priv_sl2->clk = priv->clk;
2154
ff5b8ef2
M		 2155 priv_sl2->coal_intvl = 0;
2156 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2157
d9ba8f9e
M		 2158 priv_sl2->regs = priv->regs;
2159 priv_sl2->host_port = priv->host_port;
2160 priv_sl2->host_port_regs = priv->host_port_regs;
2161 priv_sl2->wr_regs = priv->wr_regs;
d9718546 2162 priv_sl2->hw_stats = priv->hw_stats;
d9ba8f9e
M		 2163 priv_sl2->dma = priv->dma;
2164 priv_sl2->txch = priv->txch;
2165 priv_sl2->rxch = priv->rxch;
2166 priv_sl2->ale = priv->ale;
2167 priv_sl2->emac_port = 1;
2168 priv->slaves[1].ndev = ndev;
2169 priv_sl2->cpts = priv->cpts;
2170 priv_sl2->version = priv->version;
2171
2172 for (i = 0; i < priv->num_irqs; i++) {
2173 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2174 priv_sl2->num_irqs = priv->num_irqs;
2175 }
f646968f 2176 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d9ba8f9e
M		 2177
2178 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2179 ndev->ethtool_ops = &cpsw_ethtool_ops;
d9ba8f9e
M		 2180 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2181
2182 /* register the network device */
2183 SET_NETDEV_DEV(ndev, &pdev->dev);
2184 ret = register_netdev(ndev);
2185 if (ret) {
88c99ff6 2186 dev_err(&pdev->dev, "cpsw: error registering net device\n");
d9ba8f9e
M		 2187 free_netdev(ndev);
2188 ret = -ENODEV;
2189 }
2190
2191 return ret;
2192}
2193
663e12e6 2194static int cpsw_probe(struct platform_device *pdev)
df828598 2195{
d1bd9acf 2196 struct cpsw_platform_data *data;
df828598
M		 2197 struct net_device *ndev;
2198 struct cpsw_priv *priv;
2199 struct cpdma_params dma_params;
2200 struct cpsw_ale_params ale_params;
aa1a15e2
DM		 2201 void __iomem *ss_regs;
2202 struct resource *res, *ss_res;
549985ee 2203 u32 slave_offset, sliver_offset, slave_size;
5087b915
FB		 2204 int ret = 0, i;
2205 int irq;
df828598 2206
df828598
M		 2207 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2208 if (!ndev) {
88c99ff6 2209 dev_err(&pdev->dev, "error allocating net_device\n");
df828598
M		 2210 return -ENOMEM;
2211 }
2212
2213 platform_set_drvdata(pdev, ndev);
2214 priv = netdev_priv(ndev);
2215 spin_lock_init(&priv->lock);
df828598
M		 2216 priv->pdev = pdev;
2217 priv->ndev = ndev;
2218 priv->dev = &ndev->dev;
2219 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2220 priv->rx_packet_max = max(rx_packet_max, 128);
9232b16d 2221 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
7dcf313a 2222 priv->irq_enabled = true;
ab8e99d2 2223 if (!priv->cpts) {
88c99ff6 2224 dev_err(&pdev->dev, "error allocating cpts\n");
4d507dff 2225 ret = -ENOMEM;
9232b16d
M		 2226 goto clean_ndev_ret;
2227 }
df828598 2228
1fb19aa7
VH		 2229 /*
2230 * This may be required here for child devices.
2231 */
2232 pm_runtime_enable(&pdev->dev);
2233
739683b4
M		 2234 /* Select default pin state */
2235 pinctrl_pm_select_default_state(&pdev->dev);
2236
2eb32b0a 2237 if (cpsw_probe_dt(&priv->data, pdev)) {
88c99ff6 2238 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2eb32b0a 2239 ret = -ENODEV;
aa1a15e2 2240 goto clean_runtime_disable_ret;
2eb32b0a
M		 2241 }
2242 data = &priv->data;
2243
df828598
M		 2244 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2245 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
88c99ff6 2246 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
df828598 2247 } else {
7efd26d0 2248 eth_random_addr(priv->mac_addr);
88c99ff6 2249 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
df828598
M		 2250 }
2251
2252 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2253
aa1a15e2
DM		 2254 priv->slaves = devm_kzalloc(&pdev->dev,
2255 sizeof(struct cpsw_slave) * data->slaves,
2256 GFP_KERNEL);
df828598 2257 if (!priv->slaves) {
aa1a15e2
DM		 2258 ret = -ENOMEM;
2259 goto clean_runtime_disable_ret;
df828598
M		 2260 }
2261 for (i = 0; i < data->slaves; i++)
2262 priv->slaves[i].slave_num = i;
2263
d9ba8f9e
M		 2264 priv->slaves[0].ndev = ndev;
2265 priv->emac_port = 0;
2266
aa1a15e2 2267 priv->clk = devm_clk_get(&pdev->dev, "fck");
df828598 2268 if (IS_ERR(priv->clk)) {
aa1a15e2 2269 dev_err(priv->dev, "fck is not found\n");
f150bd7f 2270 ret = -ENODEV;
aa1a15e2 2271 goto clean_runtime_disable_ret;
df828598 2272 }
ff5b8ef2
M		 2273 priv->coal_intvl = 0;
2274 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
df828598 2275
aa1a15e2
DM		 2276 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2277 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2278 if (IS_ERR(ss_regs)) {
2279 ret = PTR_ERR(ss_regs);
2280 goto clean_runtime_disable_ret;
df828598 2281 }
549985ee 2282 priv->regs = ss_regs;
549985ee 2283 priv->host_port = HOST_PORT_NUM;
df828598 2284
f280e89a
M		 2285 /* Need to enable clocks with runtime PM api to access module
2286 * registers
2287 */
2288 pm_runtime_get_sync(&pdev->dev);
2289 priv->version = readl(&priv->regs->id_ver);
2290 pm_runtime_put_sync(&pdev->dev);
2291
aa1a15e2
DM		 2292 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2293 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2294 if (IS_ERR(priv->wr_regs)) {
2295 ret = PTR_ERR(priv->wr_regs);
2296 goto clean_runtime_disable_ret;
df828598 2297 }
df828598
M		 2298
2299 memset(&dma_params, 0, sizeof(dma_params));
549985ee
RC		 2300 memset(&ale_params, 0, sizeof(ale_params));
2301
2302 switch (priv->version) {
2303 case CPSW_VERSION_1:
2304 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
d9718546
M		 2305 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2306 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
549985ee
RC		 2307 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2308 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2309 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2310 slave_offset = CPSW1_SLAVE_OFFSET;
2311 slave_size = CPSW1_SLAVE_SIZE;
2312 sliver_offset = CPSW1_SLIVER_OFFSET;
2313 dma_params.desc_mem_phys = 0;
2314 break;
2315 case CPSW_VERSION_2:
c193f365 2316 case CPSW_VERSION_3:
926489be 2317 case CPSW_VERSION_4:
549985ee 2318 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
d9718546
M		 2319 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2320 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
549985ee
RC		 2321 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2322 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2323 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2324 slave_offset = CPSW2_SLAVE_OFFSET;
2325 slave_size = CPSW2_SLAVE_SIZE;
2326 sliver_offset = CPSW2_SLIVER_OFFSET;
2327 dma_params.desc_mem_phys =
aa1a15e2 2328 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
549985ee
RC		 2329 break;
2330 default:
2331 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2332 ret = -ENODEV;
aa1a15e2 2333 goto clean_runtime_disable_ret;
549985ee
RC		 2334 }
2335 for (i = 0; i < priv->data.slaves; i++) {
2336 struct cpsw_slave *slave = &priv->slaves[i];
2337 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2338 slave_offset += slave_size;
2339 sliver_offset += SLIVER_SIZE;
2340 }
2341
df828598 2342 dma_params.dev = &pdev->dev;
549985ee
RC		 2343 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2344 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2345 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2346 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2347 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
df828598
M		 2348
2349 dma_params.num_chan = data->channels;
2350 dma_params.has_soft_reset = true;
2351 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2352 dma_params.desc_mem_size = data->bd_ram_size;
2353 dma_params.desc_align = 16;
2354 dma_params.has_ext_regs = true;
549985ee 2355 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
df828598
M		 2356
2357 priv->dma = cpdma_ctlr_create(&dma_params);
2358 if (!priv->dma) {
2359 dev_err(priv->dev, "error initializing dma\n");
2360 ret = -ENOMEM;
aa1a15e2 2361 goto clean_runtime_disable_ret;
df828598
M		 2362 }
2363
2364 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2365 cpsw_tx_handler);
2366 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2367 cpsw_rx_handler);
2368
2369 if (WARN_ON(!priv->txch || !priv->rxch)) {
2370 dev_err(priv->dev, "error initializing dma channels\n");
2371 ret = -ENOMEM;
2372 goto clean_dma_ret;
2373 }
2374
df828598 2375 ale_params.dev = &ndev->dev;
df828598
M		 2376 ale_params.ale_ageout = ale_ageout;
2377 ale_params.ale_entries = data->ale_entries;
2378 ale_params.ale_ports = data->slaves;
2379
2380 priv->ale = cpsw_ale_create(&ale_params);
2381 if (!priv->ale) {
2382 dev_err(priv->dev, "error initializing ale engine\n");
2383 ret = -ENODEV;
2384 goto clean_dma_ret;
2385 }
2386
c03abd84 2387 ndev->irq = platform_get_irq(pdev, 1);
df828598
M		 2388 if (ndev->irq < 0) {
2389 dev_err(priv->dev, "error getting irq resource\n");
2390 ret = -ENOENT;
2391 goto clean_ale_ret;
2392 }
2393
c03abd84
FB		 2394 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2395 * MISC IRQs which are always kept disabled with this driver so
2396 * we will not request them.
2397 *
2398 * If anyone wants to implement support for those, make sure to
2399 * first request and append them to irqs_table array.
2400 */
c2b32e58 2401
c03abd84 2402 /* RX IRQ */
5087b915
FB		 2403 irq = platform_get_irq(pdev, 1);
2404 if (irq < 0)
2405 goto clean_ale_ret;
2406
c03abd84
FB		 2407 priv->irqs_table[0] = irq;
2408 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
5087b915
FB		 2409 0, dev_name(&pdev->dev), priv);
2410 if (ret < 0) {
2411 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2412 goto clean_ale_ret;
2413 }
2414
c03abd84 2415 /* TX IRQ */
5087b915
FB		 2416 irq = platform_get_irq(pdev, 2);
2417 if (irq < 0)
2418 goto clean_ale_ret;
2419
c03abd84
FB		 2420 priv->irqs_table[1] = irq;
2421 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
5087b915
FB		 2422 0, dev_name(&pdev->dev), priv);
2423 if (ret < 0) {
2424 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2425 goto clean_ale_ret;
df828598 2426 }
c03abd84 2427 priv->num_irqs = 2;
c2b32e58 2428
f646968f 2429 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
df828598
M		 2430
2431 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2432 ndev->ethtool_ops = &cpsw_ethtool_ops;
df828598
M		 2433 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2434
2435 /* register the network device */
2436 SET_NETDEV_DEV(ndev, &pdev->dev);
2437 ret = register_netdev(ndev);
2438 if (ret) {
2439 dev_err(priv->dev, "error registering net device\n");
2440 ret = -ENODEV;
aa1a15e2 2441 goto clean_ale_ret;
df828598
M		 2442 }
2443
1a3b5056
OJ		 2444 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2445 &ss_res->start, ndev->irq);
df828598 2446
d9ba8f9e
M		 2447 if (priv->data.dual_emac) {
2448 ret = cpsw_probe_dual_emac(pdev, priv);
2449 if (ret) {
2450 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
aa1a15e2 2451 goto clean_ale_ret;
d9ba8f9e
M		 2452 }
2453 }
2454
df828598
M		 2455 return 0;
2456
df828598
M		 2457clean_ale_ret:
2458 cpsw_ale_destroy(priv->ale);
2459clean_dma_ret:
2460 cpdma_chan_destroy(priv->txch);
2461 cpdma_chan_destroy(priv->rxch);
2462 cpdma_ctlr_destroy(priv->dma);
aa1a15e2 2463clean_runtime_disable_ret:
f150bd7f 2464 pm_runtime_disable(&pdev->dev);
df828598 2465clean_ndev_ret:
d1bd9acf 2466 free_netdev(priv->ndev);
df828598
M		 2467 return ret;
2468}
2469
030b16a0
M		 2470static int cpsw_remove_child_device(struct device *dev, void *c)
2471{
2472 struct platform_device *pdev = to_platform_device(dev);
2473
2474 of_device_unregister(pdev);
2475
2476 return 0;
2477}
2478
663e12e6 2479static int cpsw_remove(struct platform_device *pdev)
df828598
M		 2480{
2481 struct net_device *ndev = platform_get_drvdata(pdev);
2482 struct cpsw_priv *priv = netdev_priv(ndev);
2483
d1bd9acf
SS		 2484 if (priv->data.dual_emac)
2485 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2486 unregister_netdev(ndev);
df828598 2487
df828598
M		 2488 cpsw_ale_destroy(priv->ale);
2489 cpdma_chan_destroy(priv->txch);
2490 cpdma_chan_destroy(priv->rxch);
2491 cpdma_ctlr_destroy(priv->dma);
f150bd7f 2492 pm_runtime_disable(&pdev->dev);
030b16a0 2493 device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
d1bd9acf
SS		 2494 if (priv->data.dual_emac)
2495 free_netdev(cpsw_get_slave_ndev(priv, 1));
df828598 2496 free_netdev(ndev);
df828598
M		 2497 return 0;
2498}
2499
2500static int cpsw_suspend(struct device *dev)
2501{
2502 struct platform_device *pdev = to_platform_device(dev);
2503 struct net_device *ndev = platform_get_drvdata(pdev);
b90fc27a 2504 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2505
618073e3
M		 2506 if (priv->data.dual_emac) {
2507 int i;
1e7a2e21 2508
618073e3
M		 2509 for (i = 0; i < priv->data.slaves; i++) {
2510 if (netif_running(priv->slaves[i].ndev))
2511 cpsw_ndo_stop(priv->slaves[i].ndev);
2512 soft_reset_slave(priv->slaves + i);
2513 }
2514 } else {
2515 if (netif_running(ndev))
2516 cpsw_ndo_stop(ndev);
2517 for_each_slave(priv, soft_reset_slave);
2518 }
1e7a2e21 2519
f150bd7f
M		 2520 pm_runtime_put_sync(&pdev->dev);
2521
739683b4
M		 2522 /* Select sleep pin state */
2523 pinctrl_pm_select_sleep_state(&pdev->dev);
2524
df828598
M		 2525 return 0;
2526}
2527
2528static int cpsw_resume(struct device *dev)
2529{
2530 struct platform_device *pdev = to_platform_device(dev);
2531 struct net_device *ndev = platform_get_drvdata(pdev);
618073e3 2532 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2533
f150bd7f 2534 pm_runtime_get_sync(&pdev->dev);
739683b4
M		 2535
2536 /* Select default pin state */
2537 pinctrl_pm_select_default_state(&pdev->dev);
2538
618073e3
M		 2539 if (priv->data.dual_emac) {
2540 int i;
2541
2542 for (i = 0; i < priv->data.slaves; i++) {
2543 if (netif_running(priv->slaves[i].ndev))
2544 cpsw_ndo_open(priv->slaves[i].ndev);
2545 }
2546 } else {
2547 if (netif_running(ndev))
2548 cpsw_ndo_open(ndev);
2549 }
df828598
M		 2550 return 0;
2551}
2552
2553static const struct dev_pm_ops cpsw_pm_ops = {
2554 .suspend = cpsw_suspend,
2555 .resume = cpsw_resume,
2556};
2557
2eb32b0a
M		 2558static const struct of_device_id cpsw_of_mtable[] = {
2559 { .compatible = "ti,cpsw", },
2560 { /* sentinel */ },
2561};
4bc21d41 2562MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2eb32b0a 2563
df828598
M		 2564static struct platform_driver cpsw_driver = {
2565 .driver = {
2566 .name = "cpsw",
df828598 2567 .pm = &cpsw_pm_ops,
1e5c76d4 2568 .of_match_table = cpsw_of_mtable,
df828598
M		 2569 },
2570 .probe = cpsw_probe,
663e12e6 2571 .remove = cpsw_remove,
df828598
M		 2572};
2573
2574static int __init cpsw_init(void)
2575{
2576 return platform_driver_register(&cpsw_driver);
2577}
2578late_initcall(cpsw_init);
2579
2580static void __exit cpsw_exit(void)
2581{
2582 platform_driver_unregister(&cpsw_driver);
2583}
2584module_exit(cpsw_exit);
2585
2586MODULE_LICENSE("GPL");
2587MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2588MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2589MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
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