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net: ethernet: cpsw: unroll IRQ request loop
[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
2e5b38ab 27#include <linux/net_tstamp.h>
df828598
M		 28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
f150bd7f 31#include <linux/pm_runtime.h>
2eb32b0a
M		 32#include <linux/of.h>
33#include <linux/of_net.h>
34#include <linux/of_device.h>
3b72c2fe 35#include <linux/if_vlan.h>
0ba517b1
MP		 36#include <linux/mfd/syscon.h>
37#include <linux/regmap.h>
df828598 38
739683b4 39#include <linux/pinctrl/consumer.h>
df828598 40
dbe34724 41#include "cpsw.h"
df828598 42#include "cpsw_ale.h"
2e5b38ab 43#include "cpts.h"
df828598
M		 44#include "davinci_cpdma.h"
45
46#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55#define cpsw_info(priv, type, format, ...) \
56do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59} while (0)
60
61#define cpsw_err(priv, type, format, ...) \
62do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65} while (0)
66
67#define cpsw_dbg(priv, type, format, ...) \
68do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71} while (0)
72
73#define cpsw_notice(priv, type, format, ...) \
74do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77} while (0)
78
5c50a856
M		 79#define ALE_ALL_PORTS 0x7
80
df828598
M		 81#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
e90cfac6
RC		 85#define CPSW_VERSION_1 0x19010a
86#define CPSW_VERSION_2 0x19010c
c193f365 87#define CPSW_VERSION_3 0x19010f
926489be 88#define CPSW_VERSION_4 0x190112
549985ee
RC		 89
90#define HOST_PORT_NUM 0
91#define SLIVER_SIZE 0x40
92
93#define CPSW1_HOST_PORT_OFFSET 0x028
94#define CPSW1_SLAVE_OFFSET 0x050
95#define CPSW1_SLAVE_SIZE 0x040
96#define CPSW1_CPDMA_OFFSET 0x100
97#define CPSW1_STATERAM_OFFSET 0x200
d9718546 98#define CPSW1_HW_STATS 0x400
549985ee
RC		 99#define CPSW1_CPTS_OFFSET 0x500
100#define CPSW1_ALE_OFFSET 0x600
101#define CPSW1_SLIVER_OFFSET 0x700
102
103#define CPSW2_HOST_PORT_OFFSET 0x108
104#define CPSW2_SLAVE_OFFSET 0x200
105#define CPSW2_SLAVE_SIZE 0x100
106#define CPSW2_CPDMA_OFFSET 0x800
d9718546 107#define CPSW2_HW_STATS 0x900
549985ee
RC		 108#define CPSW2_STATERAM_OFFSET 0xa00
109#define CPSW2_CPTS_OFFSET 0xc00
110#define CPSW2_ALE_OFFSET 0xd00
111#define CPSW2_SLIVER_OFFSET 0xd80
112#define CPSW2_BD_OFFSET 0x2000
113
df828598
M		 114#define CPDMA_RXTHRESH 0x0c0
115#define CPDMA_RXFREE 0x0e0
116#define CPDMA_TXHDP 0x00
117#define CPDMA_RXHDP 0x20
118#define CPDMA_TXCP 0x40
119#define CPDMA_RXCP 0x60
120
df828598
M		 121#define CPSW_POLL_WEIGHT 64
122#define CPSW_MIN_PACKET_SIZE 60
123#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125#define RX_PRIORITY_MAPPING 0x76543210
126#define TX_PRIORITY_MAPPING 0x33221100
127#define CPDMA_TX_PRIORITY_MAP 0x76543210
128
3b72c2fe
M		 129#define CPSW_VLAN_AWARE BIT(1)
130#define CPSW_ALE_VLAN_AWARE 1
131
35717d8d
JO		 132#define CPSW_FIFO_NORMAL_MODE (0 << 16)
133#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
d9ba8f9e 135
ff5b8ef2
M		 136#define CPSW_INTPACEEN (0x3f << 16)
137#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138#define CPSW_CMINTMAX_CNT 63
139#define CPSW_CMINTMIN_CNT 2
140#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
df828598
M		 143#define cpsw_enable_irq(priv) \
144 do { \
145 u32 i; \
146 for (i = 0; i < priv->num_irqs; i++) \
147 enable_irq(priv->irqs_table[i]); \
5f47dfb4 148 } while (0)
df828598
M		 149#define cpsw_disable_irq(priv) \
150 do { \
151 u32 i; \
152 for (i = 0; i < priv->num_irqs; i++) \
153 disable_irq_nosync(priv->irqs_table[i]); \
5f47dfb4 154 } while (0)
df828598 155
d3bb9c58
M		 156#define cpsw_slave_index(priv) \
157 ((priv->data.dual_emac) ? priv->emac_port : \
158 priv->data.active_slave)
159
df828598
M		 160static int debug_level;
161module_param(debug_level, int, 0);
162MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
163
164static int ale_ageout = 10;
165module_param(ale_ageout, int, 0);
166MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
167
168static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
169module_param(rx_packet_max, int, 0);
170MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
171
996a5c27 172struct cpsw_wr_regs {
df828598
M		 173 u32 id_ver;
174 u32 soft_reset;
175 u32 control;
176 u32 int_control;
177 u32 rx_thresh_en;
178 u32 rx_en;
179 u32 tx_en;
180 u32 misc_en;
ff5b8ef2
M		 181 u32 mem_allign1[8];
182 u32 rx_thresh_stat;
183 u32 rx_stat;
184 u32 tx_stat;
185 u32 misc_stat;
186 u32 mem_allign2[8];
187 u32 rx_imax;
188 u32 tx_imax;
189
df828598
M		 190};
191
996a5c27 192struct cpsw_ss_regs {
df828598
M		 193 u32 id_ver;
194 u32 control;
195 u32 soft_reset;
196 u32 stat_port_en;
197 u32 ptype;
bd357af2
RC		 198 u32 soft_idle;
199 u32 thru_rate;
200 u32 gap_thresh;
201 u32 tx_start_wds;
202 u32 flow_control;
203 u32 vlan_ltype;
204 u32 ts_ltype;
205 u32 dlr_ltype;
df828598
M		 206};
207
9750a3ad
RC		 208/* CPSW_PORT_V1 */
209#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
210#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
211#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
212#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
213#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
214#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
215#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
216#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
217
218/* CPSW_PORT_V2 */
219#define CPSW2_CONTROL 0x00 /* Control Register */
220#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
221#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
222#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
223#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
224#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
225#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
226
227/* CPSW_PORT_V1 and V2 */
228#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
229#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
230#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
231
232/* CPSW_PORT_V2 only */
233#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
234#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
235#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
236#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
237#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
238#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
239#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
240#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
241
242/* Bit definitions for the CPSW2_CONTROL register */
243#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
244#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
245#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
246#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
247#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
248#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
249#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
250#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
251#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
252#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
09c55372
GC		 253#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
254#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
9750a3ad
RC		 255#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
256#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
257#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
258#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
259#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
260
09c55372
GC		 261#define CTRL_V2_TS_BITS \
262 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
263 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
9750a3ad 264
09c55372
GC		 265#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
266#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
267#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
268
269
270#define CTRL_V3_TS_BITS \
271 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
272 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
273 TS_LTYPE1_EN)
274
275#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
276#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
277#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
9750a3ad
RC		 278
279/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
280#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
281#define TS_SEQ_ID_OFFSET_MASK (0x3f)
282#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
283#define TS_MSG_TYPE_EN_MASK (0xffff)
284
285/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
286#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598 287
2e5b38ab
RC		 288/* Bit definitions for the CPSW1_TS_CTL register */
289#define CPSW_V1_TS_RX_EN BIT(0)
290#define CPSW_V1_TS_TX_EN BIT(4)
291#define CPSW_V1_MSG_TYPE_OFS 16
292
293/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
294#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
295
df828598
M		 296struct cpsw_host_regs {
297 u32 max_blks;
298 u32 blk_cnt;
d9ba8f9e 299 u32 tx_in_ctl;
df828598
M		 300 u32 port_vlan;
301 u32 tx_pri_map;
302 u32 cpdma_tx_pri_map;
303 u32 cpdma_rx_chan_map;
304};
305
306struct cpsw_sliver_regs {
307 u32 id_ver;
308 u32 mac_control;
309 u32 mac_status;
310 u32 soft_reset;
311 u32 rx_maxlen;
312 u32 __reserved_0;
313 u32 rx_pause;
314 u32 tx_pause;
315 u32 __reserved_1;
316 u32 rx_pri_map;
317};
318
d9718546
M		 319struct cpsw_hw_stats {
320 u32 rxgoodframes;
321 u32 rxbroadcastframes;
322 u32 rxmulticastframes;
323 u32 rxpauseframes;
324 u32 rxcrcerrors;
325 u32 rxaligncodeerrors;
326 u32 rxoversizedframes;
327 u32 rxjabberframes;
328 u32 rxundersizedframes;
329 u32 rxfragments;
330 u32 __pad_0[2];
331 u32 rxoctets;
332 u32 txgoodframes;
333 u32 txbroadcastframes;
334 u32 txmulticastframes;
335 u32 txpauseframes;
336 u32 txdeferredframes;
337 u32 txcollisionframes;
338 u32 txsinglecollframes;
339 u32 txmultcollframes;
340 u32 txexcessivecollisions;
341 u32 txlatecollisions;
342 u32 txunderrun;
343 u32 txcarriersenseerrors;
344 u32 txoctets;
345 u32 octetframes64;
346 u32 octetframes65t127;
347 u32 octetframes128t255;
348 u32 octetframes256t511;
349 u32 octetframes512t1023;
350 u32 octetframes1024tup;
351 u32 netoctets;
352 u32 rxsofoverruns;
353 u32 rxmofoverruns;
354 u32 rxdmaoverruns;
355};
356
df828598 357struct cpsw_slave {
9750a3ad 358 void __iomem *regs;
df828598
M		 359 struct cpsw_sliver_regs __iomem *sliver;
360 int slave_num;
361 u32 mac_control;
362 struct cpsw_slave_data *data;
363 struct phy_device *phy;
d9ba8f9e
M		 364 struct net_device *ndev;
365 u32 port_vlan;
366 u32 open_stat;
df828598
M		 367};
368
9750a3ad
RC		 369static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
370{
371 return __raw_readl(slave->regs + offset);
372}
373
374static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
375{
376 __raw_writel(val, slave->regs + offset);
377}
378
df828598
M		 379struct cpsw_priv {
380 spinlock_t lock;
381 struct platform_device *pdev;
382 struct net_device *ndev;
df828598
M		 383 struct napi_struct napi;
384 struct device *dev;
385 struct cpsw_platform_data data;
996a5c27
RC		 386 struct cpsw_ss_regs __iomem *regs;
387 struct cpsw_wr_regs __iomem *wr_regs;
d9718546 388 u8 __iomem *hw_stats;
df828598
M		 389 struct cpsw_host_regs __iomem *host_port_regs;
390 u32 msg_enable;
e90cfac6 391 u32 version;
ff5b8ef2
M		 392 u32 coal_intvl;
393 u32 bus_freq_mhz;
df828598
M		 394 int rx_packet_max;
395 int host_port;
396 struct clk *clk;
397 u8 mac_addr[ETH_ALEN];
398 struct cpsw_slave *slaves;
399 struct cpdma_ctlr *dma;
400 struct cpdma_chan *txch, *rxch;
401 struct cpsw_ale *ale;
1923d6e4
M		 402 bool rx_pause;
403 bool tx_pause;
df828598
M		 404 /* snapshot of IRQ numbers */
405 u32 irqs_table[4];
406 u32 num_irqs;
a11fbba9 407 bool irq_enabled;
9232b16d 408 struct cpts *cpts;
d9ba8f9e 409 u32 emac_port;
df828598
M		 410};
411
d9718546
M		 412struct cpsw_stats {
413 char stat_string[ETH_GSTRING_LEN];
414 int type;
415 int sizeof_stat;
416 int stat_offset;
417};
418
419enum {
420 CPSW_STATS,
421 CPDMA_RX_STATS,
422 CPDMA_TX_STATS,
423};
424
425#define CPSW_STAT(m) CPSW_STATS, \
426 sizeof(((struct cpsw_hw_stats *)0)->m), \
427 offsetof(struct cpsw_hw_stats, m)
428#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
429 sizeof(((struct cpdma_chan_stats *)0)->m), \
430 offsetof(struct cpdma_chan_stats, m)
431#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
432 sizeof(((struct cpdma_chan_stats *)0)->m), \
433 offsetof(struct cpdma_chan_stats, m)
434
435static const struct cpsw_stats cpsw_gstrings_stats[] = {
436 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
437 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
438 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
439 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
440 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
441 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
442 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
443 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
444 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
445 { "Rx Fragments", CPSW_STAT(rxfragments) },
446 { "Rx Octets", CPSW_STAT(rxoctets) },
447 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
448 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
449 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
450 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
451 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
452 { "Collisions", CPSW_STAT(txcollisionframes) },
453 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
454 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
455 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
456 { "Late Collisions", CPSW_STAT(txlatecollisions) },
457 { "Tx Underrun", CPSW_STAT(txunderrun) },
458 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
459 { "Tx Octets", CPSW_STAT(txoctets) },
460 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
461 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
462 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
463 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
464 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
465 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
466 { "Net Octets", CPSW_STAT(netoctets) },
467 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
468 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
469 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
470 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
471 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
472 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
473 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
474 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
475 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
476 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
477 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
478 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
479 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
480 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
481 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
482 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
483 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
484 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
485 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
486 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
487 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
488 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
489 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
490 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
491 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
492 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
493 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
494 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
495 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
496};
497
498#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
499
df828598 500#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
d9ba8f9e
M		 501#define for_each_slave(priv, func, arg...) \
502 do { \
6e6ceaed
SS		 503 struct cpsw_slave *slave; \
504 int n; \
d9ba8f9e
M		 505 if (priv->data.dual_emac) \
506 (func)((priv)->slaves + priv->emac_port, ##arg);\
507 else \
6e6ceaed
SS		 508 for (n = (priv)->data.slaves, \
509 slave = (priv)->slaves; \
510 n; n--) \
511 (func)(slave++, ##arg); \
d9ba8f9e
M		 512 } while (0)
513#define cpsw_get_slave_ndev(priv, __slave_no__) \
514 (priv->slaves[__slave_no__].ndev)
515#define cpsw_get_slave_priv(priv, __slave_no__) \
516 ((priv->slaves[__slave_no__].ndev) ? \
517 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
518
519#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
520 do { \
521 if (!priv->data.dual_emac) \
522 break; \
523 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
524 ndev = cpsw_get_slave_ndev(priv, 0); \
525 priv = netdev_priv(ndev); \
526 skb->dev = ndev; \
527 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
528 ndev = cpsw_get_slave_ndev(priv, 1); \
529 priv = netdev_priv(ndev); \
530 skb->dev = ndev; \
531 } \
df828598 532 } while (0)
d9ba8f9e
M		 533#define cpsw_add_mcast(priv, addr) \
534 do { \
535 if (priv->data.dual_emac) { \
536 struct cpsw_slave *slave = priv->slaves + \
537 priv->emac_port; \
538 int slave_port = cpsw_get_slave_port(priv, \
539 slave->slave_num); \
540 cpsw_ale_add_mcast(priv->ale, addr, \
541 1 << slave_port | 1 << priv->host_port, \
542 ALE_VLAN, slave->port_vlan, 0); \
543 } else { \
544 cpsw_ale_add_mcast(priv->ale, addr, \
545 ALE_ALL_PORTS << priv->host_port, \
546 0, 0, 0); \
547 } \
548 } while (0)
549
550static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
551{
552 if (priv->host_port == 0)
553 return slave_num + 1;
554 else
555 return slave_num;
556}
df828598 557
0cd8f9cc
M		 558static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
559{
560 struct cpsw_priv *priv = netdev_priv(ndev);
561 struct cpsw_ale *ale = priv->ale;
562 int i;
563
564 if (priv->data.dual_emac) {
565 bool flag = false;
566
567 /* Enabling promiscuous mode for one interface will be
568 * common for both the interface as the interface shares
569 * the same hardware resource.
570 */
0d961b3b 571 for (i = 0; i < priv->data.slaves; i++)
0cd8f9cc
M		 572 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
573 flag = true;
574
575 if (!enable && flag) {
576 enable = true;
577 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
578 }
579
580 if (enable) {
581 /* Enable Bypass */
582 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
583
584 dev_dbg(&ndev->dev, "promiscuity enabled\n");
585 } else {
586 /* Disable Bypass */
587 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
588 dev_dbg(&ndev->dev, "promiscuity disabled\n");
589 }
590 } else {
591 if (enable) {
592 unsigned long timeout = jiffies + HZ;
593
6f979eb3
LS		 594 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
595 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 596 cpsw_ale_control_set(ale, i,
597 ALE_PORT_NOLEARN, 1);
598 cpsw_ale_control_set(ale, i,
599 ALE_PORT_NO_SA_UPDATE, 1);
600 }
601
602 /* Clear All Untouched entries */
603 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
604 do {
605 cpu_relax();
606 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
607 break;
608 } while (time_after(timeout, jiffies));
609 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
610
611 /* Clear all mcast from ALE */
612 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
25906052 613 priv->host_port, -1);
0cd8f9cc
M		 614
615 /* Flood All Unicast Packets to Host port */
616 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
617 dev_dbg(&ndev->dev, "promiscuity enabled\n");
618 } else {
6f979eb3 619 /* Don't Flood All Unicast Packets to Host port */
0cd8f9cc
M		 620 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
621
6f979eb3
LS		 622 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
623 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 624 cpsw_ale_control_set(ale, i,
625 ALE_PORT_NOLEARN, 0);
626 cpsw_ale_control_set(ale, i,
627 ALE_PORT_NO_SA_UPDATE, 0);
628 }
629 dev_dbg(&ndev->dev, "promiscuity disabled\n");
630 }
631 }
632}
633
5c50a856
M		 634static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
635{
636 struct cpsw_priv *priv = netdev_priv(ndev);
25906052
M		 637 int vid;
638
639 if (priv->data.dual_emac)
640 vid = priv->slaves[priv->emac_port].port_vlan;
641 else
642 vid = priv->data.default_vlan;
5c50a856
M		 643
644 if (ndev->flags & IFF_PROMISC) {
645 /* Enable promiscuous mode */
0cd8f9cc 646 cpsw_set_promiscious(ndev, true);
1e5c4bc4 647 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
5c50a856 648 return;
0cd8f9cc
M		 649 } else {
650 /* Disable promiscuous mode */
651 cpsw_set_promiscious(ndev, false);
5c50a856
M		 652 }
653
1e5c4bc4
LS		 654 /* Restore allmulti on vlans if necessary */
655 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
656
5c50a856 657 /* Clear all mcast from ALE */
25906052
M		 658 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
659 vid);
5c50a856
M		 660
661 if (!netdev_mc_empty(ndev)) {
662 struct netdev_hw_addr *ha;
663
664 /* program multicast address list into ALE register */
665 netdev_for_each_mc_addr(ha, ndev) {
d9ba8f9e 666 cpsw_add_mcast(priv, (u8 *)ha->addr);
5c50a856
M		 667 }
668 }
669}
670
df828598
M		 671static void cpsw_intr_enable(struct cpsw_priv *priv)
672{
996a5c27
RC		 673 __raw_writel(0xFF, &priv->wr_regs->tx_en);
674 __raw_writel(0xFF, &priv->wr_regs->rx_en);
df828598
M		 675
676 cpdma_ctlr_int_ctrl(priv->dma, true);
677 return;
678}
679
680static void cpsw_intr_disable(struct cpsw_priv *priv)
681{
996a5c27
RC		 682 __raw_writel(0, &priv->wr_regs->tx_en);
683 __raw_writel(0, &priv->wr_regs->rx_en);
df828598
M		 684
685 cpdma_ctlr_int_ctrl(priv->dma, false);
686 return;
687}
688
1a3b5056 689static void cpsw_tx_handler(void *token, int len, int status)
df828598
M		 690{
691 struct sk_buff *skb = token;
692 struct net_device *ndev = skb->dev;
693 struct cpsw_priv *priv = netdev_priv(ndev);
694
fae50823
M		 695 /* Check whether the queue is stopped due to stalled tx dma, if the
696 * queue is stopped then start the queue as we have free desc for tx
697 */
df828598 698 if (unlikely(netif_queue_stopped(ndev)))
b56d6b3f 699 netif_wake_queue(ndev);
9232b16d 700 cpts_tx_timestamp(priv->cpts, skb);
8dc43ddc
TK		 701 ndev->stats.tx_packets++;
702 ndev->stats.tx_bytes += len;
df828598
M		 703 dev_kfree_skb_any(skb);
704}
705
1a3b5056 706static void cpsw_rx_handler(void *token, int len, int status)
df828598
M		 707{
708 struct sk_buff *skb = token;
b4727e69 709 struct sk_buff *new_skb;
df828598
M		 710 struct net_device *ndev = skb->dev;
711 struct cpsw_priv *priv = netdev_priv(ndev);
712 int ret = 0;
713
d9ba8f9e
M		 714 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
715
16e5c57d 716 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
a0e2c822
M		 717 bool ndev_status = false;
718 struct cpsw_slave *slave = priv->slaves;
719 int n;
720
721 if (priv->data.dual_emac) {
722 /* In dual emac mode check for all interfaces */
723 for (n = priv->data.slaves; n; n--, slave++)
724 if (netif_running(slave->ndev))
725 ndev_status = true;
726 }
727
728 if (ndev_status && (status >= 0)) {
729 /* The packet received is for the interface which
730 * is already down and the other interface is up
731 * and running, intead of freeing which results
732 * in reducing of the number of rx descriptor in
733 * DMA engine, requeue skb back to cpdma.
734 */
735 new_skb = skb;
736 goto requeue;
737 }
738
b4727e69 739 /* the interface is going down, skbs are purged */
df828598
M		 740 dev_kfree_skb_any(skb);
741 return;
742 }
b4727e69
SS		 743
744 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
745 if (new_skb) {
df828598 746 skb_put(skb, len);
9232b16d 747 cpts_rx_timestamp(priv->cpts, skb);
df828598
M		 748 skb->protocol = eth_type_trans(skb, ndev);
749 netif_receive_skb(skb);
8dc43ddc
TK		 750 ndev->stats.rx_bytes += len;
751 ndev->stats.rx_packets++;
b4727e69 752 } else {
8dc43ddc 753 ndev->stats.rx_dropped++;
b4727e69 754 new_skb = skb;
df828598
M		 755 }
756
a0e2c822 757requeue:
b4727e69
SS		 758 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
759 skb_tailroom(new_skb), 0);
760 if (WARN_ON(ret < 0))
761 dev_kfree_skb_any(new_skb);
df828598
M		 762}
763
764static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
765{
766 struct cpsw_priv *priv = dev_id;
7ce67a38
FB		 767 int value = irq - priv->irqs_table[0];
768
769 /* NOTICE: Ending IRQ here. The trick with the 'value' variable above
770 * is to make sure we will always write the correct value to the EOI
771 * register. Namely 0 for RX_THRESH Interrupt, 1 for RX Interrupt, 2
772 * for TX Interrupt and 3 for MISC Interrupt.
773 */
774 cpdma_ctlr_eoi(priv->dma, value);
fd51cf19
SS		 775
776 cpsw_intr_disable(priv);
a11fbba9
SS		 777 if (priv->irq_enabled == true) {
778 cpsw_disable_irq(priv);
779 priv->irq_enabled = false;
780 }
fd51cf19
SS		 781
782 if (netif_running(priv->ndev)) {
df828598 783 napi_schedule(&priv->napi);
fd51cf19
SS		 784 return IRQ_HANDLED;
785 }
786
787 priv = cpsw_get_slave_priv(priv, 1);
788 if (!priv)
789 return IRQ_NONE;
790
791 if (netif_running(priv->ndev)) {
792 napi_schedule(&priv->napi);
793 return IRQ_HANDLED;
df828598 794 }
fd51cf19 795 return IRQ_NONE;
df828598
M		 796}
797
df828598
M		 798static int cpsw_poll(struct napi_struct *napi, int budget)
799{
800 struct cpsw_priv *priv = napi_to_priv(napi);
801 int num_tx, num_rx;
802
803 num_tx = cpdma_chan_process(priv->txch, 128);
df828598 804
510a1e72 805 num_rx = cpdma_chan_process(priv->rxch, budget);
df828598 806 if (num_rx < budget) {
a11fbba9
SS		 807 struct cpsw_priv *prim_cpsw;
808
df828598
M		 809 napi_complete(napi);
810 cpsw_intr_enable(priv);
a11fbba9
SS		 811 prim_cpsw = cpsw_get_slave_priv(priv, 0);
812 if (prim_cpsw->irq_enabled == false) {
a11fbba9 813 prim_cpsw->irq_enabled = true;
af5c6df7 814 cpsw_enable_irq(priv);
a11fbba9 815 }
df828598
M		 816 }
817
510a1e72
M		 818 if (num_rx || num_tx)
819 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
820 num_rx, num_tx);
821
df828598
M		 822 return num_rx;
823}
824
825static inline void soft_reset(const char *module, void __iomem *reg)
826{
827 unsigned long timeout = jiffies + HZ;
828
829 __raw_writel(1, reg);
830 do {
831 cpu_relax();
832 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
833
834 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
835}
836
837#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
838 ((mac)[2] << 16) | ((mac)[3] << 24))
839#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
840
841static void cpsw_set_slave_mac(struct cpsw_slave *slave,
842 struct cpsw_priv *priv)
843{
9750a3ad
RC		 844 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
845 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 846}
847
848static void _cpsw_adjust_link(struct cpsw_slave *slave,
849 struct cpsw_priv *priv, bool *link)
850{
851 struct phy_device *phy = slave->phy;
852 u32 mac_control = 0;
853 u32 slave_port;
854
855 if (!phy)
856 return;
857
858 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
859
860 if (phy->link) {
861 mac_control = priv->data.mac_control;
862
863 /* enable forwarding */
864 cpsw_ale_control_set(priv->ale, slave_port,
865 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
866
867 if (phy->speed == 1000)
868 mac_control |= BIT(7); /* GIGABITEN */
869 if (phy->duplex)
870 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 871
872 /* set speed_in input in case RMII mode is used in 100Mbps */
873 if (phy->speed == 100)
874 mac_control |= BIT(15);
a81d8762
M		 875 else if (phy->speed == 10)
876 mac_control |= BIT(18); /* In Band mode */
342b7b74 877
1923d6e4
M		 878 if (priv->rx_pause)
879 mac_control |= BIT(3);
880
881 if (priv->tx_pause)
882 mac_control |= BIT(4);
883
df828598
M		 884 *link = true;
885 } else {
886 mac_control = 0;
887 /* disable forwarding */
888 cpsw_ale_control_set(priv->ale, slave_port,
889 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
890 }
891
892 if (mac_control != slave->mac_control) {
893 phy_print_status(phy);
894 __raw_writel(mac_control, &slave->sliver->mac_control);
895 }
896
897 slave->mac_control = mac_control;
898}
899
900static void cpsw_adjust_link(struct net_device *ndev)
901{
902 struct cpsw_priv *priv = netdev_priv(ndev);
903 bool link = false;
904
905 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
906
907 if (link) {
908 netif_carrier_on(ndev);
909 if (netif_running(ndev))
910 netif_wake_queue(ndev);
911 } else {
912 netif_carrier_off(ndev);
913 netif_stop_queue(ndev);
914 }
915}
916
ff5b8ef2
M		 917static int cpsw_get_coalesce(struct net_device *ndev,
918 struct ethtool_coalesce *coal)
919{
920 struct cpsw_priv *priv = netdev_priv(ndev);
921
922 coal->rx_coalesce_usecs = priv->coal_intvl;
923 return 0;
924}
925
926static int cpsw_set_coalesce(struct net_device *ndev,
927 struct ethtool_coalesce *coal)
928{
929 struct cpsw_priv *priv = netdev_priv(ndev);
930 u32 int_ctrl;
931 u32 num_interrupts = 0;
932 u32 prescale = 0;
933 u32 addnl_dvdr = 1;
934 u32 coal_intvl = 0;
935
ff5b8ef2
M		 936 coal_intvl = coal->rx_coalesce_usecs;
937
938 int_ctrl = readl(&priv->wr_regs->int_control);
939 prescale = priv->bus_freq_mhz * 4;
940
a84bc2a9
M		 941 if (!coal->rx_coalesce_usecs) {
942 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
943 goto update_return;
944 }
945
ff5b8ef2
M		 946 if (coal_intvl < CPSW_CMINTMIN_INTVL)
947 coal_intvl = CPSW_CMINTMIN_INTVL;
948
949 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
950 /* Interrupt pacer works with 4us Pulse, we can
951 * throttle further by dilating the 4us pulse.
952 */
953 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
954
955 if (addnl_dvdr > 1) {
956 prescale *= addnl_dvdr;
957 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
958 coal_intvl = (CPSW_CMINTMAX_INTVL
959 * addnl_dvdr);
960 } else {
961 addnl_dvdr = 1;
962 coal_intvl = CPSW_CMINTMAX_INTVL;
963 }
964 }
965
966 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
967 writel(num_interrupts, &priv->wr_regs->rx_imax);
968 writel(num_interrupts, &priv->wr_regs->tx_imax);
969
970 int_ctrl |= CPSW_INTPACEEN;
971 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
972 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
a84bc2a9
M		 973
974update_return:
ff5b8ef2
M		 975 writel(int_ctrl, &priv->wr_regs->int_control);
976
977 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
978 if (priv->data.dual_emac) {
979 int i;
980
981 for (i = 0; i < priv->data.slaves; i++) {
982 priv = netdev_priv(priv->slaves[i].ndev);
983 priv->coal_intvl = coal_intvl;
984 }
985 } else {
986 priv->coal_intvl = coal_intvl;
987 }
988
989 return 0;
990}
991
d9718546
M		 992static int cpsw_get_sset_count(struct net_device *ndev, int sset)
993{
994 switch (sset) {
995 case ETH_SS_STATS:
996 return CPSW_STATS_LEN;
997 default:
998 return -EOPNOTSUPP;
999 }
1000}
1001
1002static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1003{
1004 u8 *p = data;
1005 int i;
1006
1007 switch (stringset) {
1008 case ETH_SS_STATS:
1009 for (i = 0; i < CPSW_STATS_LEN; i++) {
1010 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1011 ETH_GSTRING_LEN);
1012 p += ETH_GSTRING_LEN;
1013 }
1014 break;
1015 }
1016}
1017
1018static void cpsw_get_ethtool_stats(struct net_device *ndev,
1019 struct ethtool_stats *stats, u64 *data)
1020{
1021 struct cpsw_priv *priv = netdev_priv(ndev);
1022 struct cpdma_chan_stats rx_stats;
1023 struct cpdma_chan_stats tx_stats;
1024 u32 val;
1025 u8 *p;
1026 int i;
1027
1028 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1029 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1030 cpdma_chan_get_stats(priv->txch, &tx_stats);
1031
1032 for (i = 0; i < CPSW_STATS_LEN; i++) {
1033 switch (cpsw_gstrings_stats[i].type) {
1034 case CPSW_STATS:
1035 val = readl(priv->hw_stats +
1036 cpsw_gstrings_stats[i].stat_offset);
1037 data[i] = val;
1038 break;
1039
1040 case CPDMA_RX_STATS:
1041 p = (u8 *)&rx_stats +
1042 cpsw_gstrings_stats[i].stat_offset;
1043 data[i] = *(u32 *)p;
1044 break;
1045
1046 case CPDMA_TX_STATS:
1047 p = (u8 *)&tx_stats +
1048 cpsw_gstrings_stats[i].stat_offset;
1049 data[i] = *(u32 *)p;
1050 break;
1051 }
1052 }
1053}
1054
d9ba8f9e
M		 1055static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1056{
1057 u32 i;
1058 u32 usage_count = 0;
1059
1060 if (!priv->data.dual_emac)
1061 return 0;
1062
1063 for (i = 0; i < priv->data.slaves; i++)
1064 if (priv->slaves[i].open_stat)
1065 usage_count++;
1066
1067 return usage_count;
1068}
1069
1070static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1071 struct cpsw_priv *priv, struct sk_buff *skb)
1072{
1073 if (!priv->data.dual_emac)
1074 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1075 skb->len, 0);
d9ba8f9e
M		 1076
1077 if (ndev == cpsw_get_slave_ndev(priv, 0))
1078 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1079 skb->len, 1);
d9ba8f9e
M		 1080 else
1081 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1082 skb->len, 2);
d9ba8f9e
M		 1083}
1084
1085static inline void cpsw_add_dual_emac_def_ale_entries(
1086 struct cpsw_priv *priv, struct cpsw_slave *slave,
1087 u32 slave_port)
1088{
1089 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1090
1091 if (priv->version == CPSW_VERSION_1)
1092 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1093 else
1094 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1095 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1096 port_mask, port_mask, 0);
1097 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1098 port_mask, ALE_VLAN, slave->port_vlan, 0);
1099 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1100 priv->host_port, ALE_VLAN, slave->port_vlan);
1101}
1102
1e7a2e21 1103static void soft_reset_slave(struct cpsw_slave *slave)
df828598
M		 1104{
1105 char name[32];
df828598 1106
1e7a2e21 1107 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
df828598 1108 soft_reset(name, &slave->sliver->soft_reset);
1e7a2e21
DM		 1109}
1110
1111static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1112{
1113 u32 slave_port;
1114
1115 soft_reset_slave(slave);
df828598
M		 1116
1117 /* setup priority mapping */
1118 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad
RC		 1119
1120 switch (priv->version) {
1121 case CPSW_VERSION_1:
1122 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1123 break;
1124 case CPSW_VERSION_2:
c193f365 1125 case CPSW_VERSION_3:
926489be 1126 case CPSW_VERSION_4:
9750a3ad
RC		 1127 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1128 break;
1129 }
df828598
M		 1130
1131 /* setup max packet size, and mac address */
1132 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1133 cpsw_set_slave_mac(slave, priv);
1134
1135 slave->mac_control = 0; /* no link yet */
1136
1137 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1138
d9ba8f9e
M		 1139 if (priv->data.dual_emac)
1140 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1141 else
1142 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1143 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
df828598
M		 1144
1145 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
f9a8f83b 1146 &cpsw_adjust_link, slave->data->phy_if);
df828598
M		 1147 if (IS_ERR(slave->phy)) {
1148 dev_err(priv->dev, "phy %s not found on slave %d\n",
1149 slave->data->phy_id, slave->slave_num);
1150 slave->phy = NULL;
1151 } else {
1152 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1153 slave->phy->phy_id);
1154 phy_start(slave->phy);
388367a5
M		 1155
1156 /* Configure GMII_SEL register */
1157 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1158 slave->slave_num);
df828598
M		 1159 }
1160}
1161
3b72c2fe
M		 1162static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1163{
1164 const int vlan = priv->data.default_vlan;
1165 const int port = priv->host_port;
1166 u32 reg;
1167 int i;
1e5c4bc4 1168 int unreg_mcast_mask;
3b72c2fe
M		 1169
1170 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1171 CPSW2_PORT_VLAN;
1172
1173 writel(vlan, &priv->host_port_regs->port_vlan);
1174
0237c110 1175 for (i = 0; i < priv->data.slaves; i++)
3b72c2fe
M		 1176 slave_write(priv->slaves + i, vlan, reg);
1177
1e5c4bc4
LS		 1178 if (priv->ndev->flags & IFF_ALLMULTI)
1179 unreg_mcast_mask = ALE_ALL_PORTS;
1180 else
1181 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1182
3b72c2fe
M		 1183 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1184 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1e5c4bc4 1185 unreg_mcast_mask << port);
3b72c2fe
M		 1186}
1187
df828598
M		 1188static void cpsw_init_host_port(struct cpsw_priv *priv)
1189{
3b72c2fe 1190 u32 control_reg;
d9ba8f9e 1191 u32 fifo_mode;
3b72c2fe 1192
df828598
M		 1193 /* soft reset the controller and initialize ale */
1194 soft_reset("cpsw", &priv->regs->soft_reset);
1195 cpsw_ale_start(priv->ale);
1196
1197 /* switch to vlan unaware mode */
3b72c2fe
M		 1198 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1199 CPSW_ALE_VLAN_AWARE);
1200 control_reg = readl(&priv->regs->control);
1201 control_reg |= CPSW_VLAN_AWARE;
1202 writel(control_reg, &priv->regs->control);
d9ba8f9e
M		 1203 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1204 CPSW_FIFO_NORMAL_MODE;
1205 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
df828598
M		 1206
1207 /* setup host port priority mapping */
1208 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1209 &priv->host_port_regs->cpdma_tx_pri_map);
1210 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1211
1212 cpsw_ale_control_set(priv->ale, priv->host_port,
1213 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1214
d9ba8f9e
M		 1215 if (!priv->data.dual_emac) {
1216 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1217 0, 0);
1218 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1219 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1220 }
df828598
M		 1221}
1222
aacebbf8
SS		 1223static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1224{
3995d265
SP		 1225 u32 slave_port;
1226
1227 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1228
aacebbf8
SS		 1229 if (!slave->phy)
1230 return;
1231 phy_stop(slave->phy);
1232 phy_disconnect(slave->phy);
1233 slave->phy = NULL;
3995d265
SP		 1234 cpsw_ale_control_set(priv->ale, slave_port,
1235 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
aacebbf8
SS		 1236}
1237
df828598
M		 1238static int cpsw_ndo_open(struct net_device *ndev)
1239{
1240 struct cpsw_priv *priv = netdev_priv(ndev);
a11fbba9 1241 struct cpsw_priv *prim_cpsw;
df828598
M		 1242 int i, ret;
1243 u32 reg;
1244
d9ba8f9e
M		 1245 if (!cpsw_common_res_usage_state(priv))
1246 cpsw_intr_disable(priv);
df828598
M		 1247 netif_carrier_off(ndev);
1248
f150bd7f 1249 pm_runtime_get_sync(&priv->pdev->dev);
df828598 1250
549985ee 1251 reg = priv->version;
df828598
M		 1252
1253 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1254 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1255 CPSW_RTL_VERSION(reg));
1256
1257 /* initialize host and slave ports */
d9ba8f9e
M		 1258 if (!cpsw_common_res_usage_state(priv))
1259 cpsw_init_host_port(priv);
df828598
M		 1260 for_each_slave(priv, cpsw_slave_open, priv);
1261
3b72c2fe 1262 /* Add default VLAN */
e6afea0b
M		 1263 if (!priv->data.dual_emac)
1264 cpsw_add_default_vlan(priv);
1265 else
1266 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1267 ALE_ALL_PORTS << priv->host_port,
1268 ALE_ALL_PORTS << priv->host_port, 0, 0);
3b72c2fe 1269
d9ba8f9e
M		 1270 if (!cpsw_common_res_usage_state(priv)) {
1271 /* setup tx dma to fixed prio and zero offset */
1272 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1273 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
df828598 1274
d9ba8f9e
M		 1275 /* disable priority elevation */
1276 __raw_writel(0, &priv->regs->ptype);
df828598 1277
d9ba8f9e
M		 1278 /* enable statistics collection only on all ports */
1279 __raw_writel(0x7, &priv->regs->stat_port_en);
df828598 1280
1923d6e4
M		 1281 /* Enable internal fifo flow control */
1282 writel(0x7, &priv->regs->flow_control);
1283
d9ba8f9e
M		 1284 if (WARN_ON(!priv->data.rx_descs))
1285 priv->data.rx_descs = 128;
df828598 1286
d9ba8f9e
M		 1287 for (i = 0; i < priv->data.rx_descs; i++) {
1288 struct sk_buff *skb;
df828598 1289
d9ba8f9e 1290 ret = -ENOMEM;
aacebbf8
SS		 1291 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1292 priv->rx_packet_max, GFP_KERNEL);
d9ba8f9e 1293 if (!skb)
aacebbf8 1294 goto err_cleanup;
d9ba8f9e 1295 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
aef614e1 1296 skb_tailroom(skb), 0);
aacebbf8
SS		 1297 if (ret < 0) {
1298 kfree_skb(skb);
1299 goto err_cleanup;
1300 }
d9ba8f9e
M		 1301 }
1302 /* continue even if we didn't manage to submit all
1303 * receive descs
1304 */
1305 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
f280e89a
M		 1306
1307 if (cpts_register(&priv->pdev->dev, priv->cpts,
1308 priv->data.cpts_clock_mult,
1309 priv->data.cpts_clock_shift))
1310 dev_err(priv->dev, "error registering cpts device\n");
1311
df828598 1312 }
df828598 1313
ff5b8ef2
M		 1314 /* Enable Interrupt pacing if configured */
1315 if (priv->coal_intvl != 0) {
1316 struct ethtool_coalesce coal;
1317
1318 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1319 cpsw_set_coalesce(ndev, &coal);
1320 }
1321
f63a975e
M		 1322 napi_enable(&priv->napi);
1323 cpdma_ctlr_start(priv->dma);
1324 cpsw_intr_enable(priv);
f63a975e 1325
a11fbba9
SS		 1326 prim_cpsw = cpsw_get_slave_priv(priv, 0);
1327 if (prim_cpsw->irq_enabled == false) {
1328 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1329 prim_cpsw->irq_enabled = true;
1330 cpsw_enable_irq(prim_cpsw);
1331 }
1332 }
1333
d9ba8f9e
M		 1334 if (priv->data.dual_emac)
1335 priv->slaves[priv->emac_port].open_stat = true;
df828598 1336 return 0;
df828598 1337
aacebbf8
SS		 1338err_cleanup:
1339 cpdma_ctlr_stop(priv->dma);
1340 for_each_slave(priv, cpsw_slave_stop, priv);
1341 pm_runtime_put_sync(&priv->pdev->dev);
1342 netif_carrier_off(priv->ndev);
1343 return ret;
df828598
M		 1344}
1345
1346static int cpsw_ndo_stop(struct net_device *ndev)
1347{
1348 struct cpsw_priv *priv = netdev_priv(ndev);
1349
1350 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
df828598
M		 1351 netif_stop_queue(priv->ndev);
1352 napi_disable(&priv->napi);
1353 netif_carrier_off(priv->ndev);
d9ba8f9e
M		 1354
1355 if (cpsw_common_res_usage_state(priv) <= 1) {
f280e89a 1356 cpts_unregister(priv->cpts);
d9ba8f9e
M		 1357 cpsw_intr_disable(priv);
1358 cpdma_ctlr_int_ctrl(priv->dma, false);
1359 cpdma_ctlr_stop(priv->dma);
1360 cpsw_ale_stop(priv->ale);
1361 }
df828598 1362 for_each_slave(priv, cpsw_slave_stop, priv);
f150bd7f 1363 pm_runtime_put_sync(&priv->pdev->dev);
d9ba8f9e
M		 1364 if (priv->data.dual_emac)
1365 priv->slaves[priv->emac_port].open_stat = false;
df828598
M		 1366 return 0;
1367}
1368
1369static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1370 struct net_device *ndev)
1371{
1372 struct cpsw_priv *priv = netdev_priv(ndev);
1373 int ret;
1374
1375 ndev->trans_start = jiffies;
1376
1377 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1378 cpsw_err(priv, tx_err, "packet pad failed\n");
8dc43ddc 1379 ndev->stats.tx_dropped++;
df828598
M		 1380 return NETDEV_TX_OK;
1381 }
1382
9232b16d
M		 1383 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1384 priv->cpts->tx_enable)
2e5b38ab
RC		 1385 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1386
1387 skb_tx_timestamp(skb);
1388
d9ba8f9e 1389 ret = cpsw_tx_packet_submit(ndev, priv, skb);
df828598
M		 1390 if (unlikely(ret != 0)) {
1391 cpsw_err(priv, tx_err, "desc submit failed\n");
1392 goto fail;
1393 }
1394
fae50823
M		 1395 /* If there is no more tx desc left free then we need to
1396 * tell the kernel to stop sending us tx frames.
1397 */
d35162f8 1398 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
fae50823
M		 1399 netif_stop_queue(ndev);
1400
df828598
M		 1401 return NETDEV_TX_OK;
1402fail:
8dc43ddc 1403 ndev->stats.tx_dropped++;
df828598
M		 1404 netif_stop_queue(ndev);
1405 return NETDEV_TX_BUSY;
1406}
1407
2e5b38ab
RC		 1408#ifdef CONFIG_TI_CPTS
1409
1410static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1411{
e86ac13b 1412 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
2e5b38ab
RC		 1413 u32 ts_en, seq_id;
1414
9232b16d 1415 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
2e5b38ab
RC		 1416 slave_write(slave, 0, CPSW1_TS_CTL);
1417 return;
1418 }
1419
1420 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1421 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1422
9232b16d 1423 if (priv->cpts->tx_enable)
2e5b38ab
RC		 1424 ts_en |= CPSW_V1_TS_TX_EN;
1425
9232b16d 1426 if (priv->cpts->rx_enable)
2e5b38ab
RC		 1427 ts_en |= CPSW_V1_TS_RX_EN;
1428
1429 slave_write(slave, ts_en, CPSW1_TS_CTL);
1430 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1431}
1432
1433static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1434{
d9ba8f9e 1435 struct cpsw_slave *slave;
2e5b38ab
RC		 1436 u32 ctrl, mtype;
1437
d9ba8f9e
M		 1438 if (priv->data.dual_emac)
1439 slave = &priv->slaves[priv->emac_port];
1440 else
e86ac13b 1441 slave = &priv->slaves[priv->data.active_slave];
d9ba8f9e 1442
2e5b38ab 1443 ctrl = slave_read(slave, CPSW2_CONTROL);
09c55372
GC		 1444 switch (priv->version) {
1445 case CPSW_VERSION_2:
1446 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2e5b38ab 1447
09c55372
GC		 1448 if (priv->cpts->tx_enable)
1449 ctrl |= CTRL_V2_TX_TS_BITS;
2e5b38ab 1450
09c55372
GC		 1451 if (priv->cpts->rx_enable)
1452 ctrl |= CTRL_V2_RX_TS_BITS;
1453 break;
1454 case CPSW_VERSION_3:
1455 default:
1456 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1457
1458 if (priv->cpts->tx_enable)
1459 ctrl |= CTRL_V3_TX_TS_BITS;
1460
1461 if (priv->cpts->rx_enable)
1462 ctrl |= CTRL_V3_RX_TS_BITS;
1463 break;
1464 }
2e5b38ab
RC		 1465
1466 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1467
1468 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1469 slave_write(slave, ctrl, CPSW2_CONTROL);
1470 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1471}
1472
a5b4145b 1473static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2e5b38ab 1474{
3177bf6f 1475 struct cpsw_priv *priv = netdev_priv(dev);
9232b16d 1476 struct cpts *cpts = priv->cpts;
2e5b38ab
RC		 1477 struct hwtstamp_config cfg;
1478
2ee91e54 1479 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1480 priv->version != CPSW_VERSION_2 &&
1481 priv->version != CPSW_VERSION_3)
2ee91e54
BH		 1482 return -EOPNOTSUPP;
1483
2e5b38ab
RC		 1484 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1485 return -EFAULT;
1486
1487 /* reserved for future extensions */
1488 if (cfg.flags)
1489 return -EINVAL;
1490
2ee91e54 1491 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2e5b38ab 1492 return -ERANGE;
2e5b38ab
RC		 1493
1494 switch (cfg.rx_filter) {
1495 case HWTSTAMP_FILTER_NONE:
1496 cpts->rx_enable = 0;
1497 break;
1498 case HWTSTAMP_FILTER_ALL:
1499 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1500 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1501 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1502 return -ERANGE;
1503 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1504 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1505 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1506 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1507 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1508 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1509 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1510 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1511 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1512 cpts->rx_enable = 1;
1513 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1514 break;
1515 default:
1516 return -ERANGE;
1517 }
1518
2ee91e54
BH		 1519 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1520
2e5b38ab
RC		 1521 switch (priv->version) {
1522 case CPSW_VERSION_1:
1523 cpsw_hwtstamp_v1(priv);
1524 break;
1525 case CPSW_VERSION_2:
f7d403cb 1526 case CPSW_VERSION_3:
2e5b38ab
RC		 1527 cpsw_hwtstamp_v2(priv);
1528 break;
1529 default:
2ee91e54 1530 WARN_ON(1);
2e5b38ab
RC		 1531 }
1532
1533 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1534}
1535
a5b4145b
BH		 1536static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1537{
1538 struct cpsw_priv *priv = netdev_priv(dev);
1539 struct cpts *cpts = priv->cpts;
1540 struct hwtstamp_config cfg;
1541
1542 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1543 priv->version != CPSW_VERSION_2 &&
1544 priv->version != CPSW_VERSION_3)
a5b4145b
BH		 1545 return -EOPNOTSUPP;
1546
1547 cfg.flags = 0;
1548 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1549 cfg.rx_filter = (cpts->rx_enable ?
1550 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1551
1552 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1553}
1554
2e5b38ab
RC		 1555#endif /*CONFIG_TI_CPTS*/
1556
1557static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1558{
11f2c988 1559 struct cpsw_priv *priv = netdev_priv(dev);
11f2c988
M		 1560 int slave_no = cpsw_slave_index(priv);
1561
2e5b38ab
RC		 1562 if (!netif_running(dev))
1563 return -EINVAL;
1564
11f2c988 1565 switch (cmd) {
2e5b38ab 1566#ifdef CONFIG_TI_CPTS
11f2c988 1567 case SIOCSHWTSTAMP:
a5b4145b
BH		 1568 return cpsw_hwtstamp_set(dev, req);
1569 case SIOCGHWTSTAMP:
1570 return cpsw_hwtstamp_get(dev, req);
2e5b38ab 1571#endif
11f2c988
M		 1572 }
1573
c1b59947
SS		 1574 if (!priv->slaves[slave_no].phy)
1575 return -EOPNOTSUPP;
1576 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
2e5b38ab
RC		 1577}
1578
df828598
M		 1579static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1580{
1581 struct cpsw_priv *priv = netdev_priv(ndev);
1582
1583 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
8dc43ddc 1584 ndev->stats.tx_errors++;
df828598
M		 1585 cpsw_intr_disable(priv);
1586 cpdma_ctlr_int_ctrl(priv->dma, false);
1587 cpdma_chan_stop(priv->txch);
1588 cpdma_chan_start(priv->txch);
1589 cpdma_ctlr_int_ctrl(priv->dma, true);
1590 cpsw_intr_enable(priv);
df828598
M		 1591}
1592
dcfd8d58
M		 1593static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1594{
1595 struct cpsw_priv *priv = netdev_priv(ndev);
1596 struct sockaddr *addr = (struct sockaddr *)p;
1597 int flags = 0;
1598 u16 vid = 0;
1599
1600 if (!is_valid_ether_addr(addr->sa_data))
1601 return -EADDRNOTAVAIL;
1602
1603 if (priv->data.dual_emac) {
1604 vid = priv->slaves[priv->emac_port].port_vlan;
1605 flags = ALE_VLAN;
1606 }
1607
1608 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1609 flags, vid);
1610 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1611 flags, vid);
1612
1613 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1614 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1615 for_each_slave(priv, cpsw_set_slave_mac, priv);
1616
1617 return 0;
1618}
1619
df828598
M		 1620#ifdef CONFIG_NET_POLL_CONTROLLER
1621static void cpsw_ndo_poll_controller(struct net_device *ndev)
1622{
1623 struct cpsw_priv *priv = netdev_priv(ndev);
1624
1625 cpsw_intr_disable(priv);
1626 cpdma_ctlr_int_ctrl(priv->dma, false);
1627 cpsw_interrupt(ndev->irq, priv);
1628 cpdma_ctlr_int_ctrl(priv->dma, true);
1629 cpsw_intr_enable(priv);
df828598
M		 1630}
1631#endif
1632
3b72c2fe
M		 1633static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1634 unsigned short vid)
1635{
1636 int ret;
1e5c4bc4
LS		 1637 int unreg_mcast_mask;
1638
1639 if (priv->ndev->flags & IFF_ALLMULTI)
1640 unreg_mcast_mask = ALE_ALL_PORTS;
1641 else
1642 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
3b72c2fe
M		 1643
1644 ret = cpsw_ale_add_vlan(priv->ale, vid,
1645 ALE_ALL_PORTS << priv->host_port,
1646 0, ALE_ALL_PORTS << priv->host_port,
1e5c4bc4 1647 unreg_mcast_mask << priv->host_port);
3b72c2fe
M		 1648 if (ret != 0)
1649 return ret;
1650
1651 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1652 priv->host_port, ALE_VLAN, vid);
1653 if (ret != 0)
1654 goto clean_vid;
1655
1656 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1657 ALE_ALL_PORTS << priv->host_port,
1658 ALE_VLAN, vid, 0);
1659 if (ret != 0)
1660 goto clean_vlan_ucast;
1661 return 0;
1662
1663clean_vlan_ucast:
1664 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1665 priv->host_port, ALE_VLAN, vid);
1666clean_vid:
1667 cpsw_ale_del_vlan(priv->ale, vid, 0);
1668 return ret;
1669}
1670
1671static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
80d5c368 1672 __be16 proto, u16 vid)
3b72c2fe
M		 1673{
1674 struct cpsw_priv *priv = netdev_priv(ndev);
1675
1676 if (vid == priv->data.default_vlan)
1677 return 0;
1678
1679 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1680 return cpsw_add_vlan_ale_entry(priv, vid);
1681}
1682
1683static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
80d5c368 1684 __be16 proto, u16 vid)
3b72c2fe
M		 1685{
1686 struct cpsw_priv *priv = netdev_priv(ndev);
1687 int ret;
1688
1689 if (vid == priv->data.default_vlan)
1690 return 0;
1691
1692 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1693 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1694 if (ret != 0)
1695 return ret;
1696
1697 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1698 priv->host_port, ALE_VLAN, vid);
1699 if (ret != 0)
1700 return ret;
1701
1702 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1703 0, ALE_VLAN, vid);
1704}
1705
df828598
M		 1706static const struct net_device_ops cpsw_netdev_ops = {
1707 .ndo_open = cpsw_ndo_open,
1708 .ndo_stop = cpsw_ndo_stop,
1709 .ndo_start_xmit = cpsw_ndo_start_xmit,
dcfd8d58 1710 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2e5b38ab 1711 .ndo_do_ioctl = cpsw_ndo_ioctl,
df828598 1712 .ndo_validate_addr = eth_validate_addr,
5c473ed2 1713 .ndo_change_mtu = eth_change_mtu,
df828598 1714 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
5c50a856 1715 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
df828598
M		 1716#ifdef CONFIG_NET_POLL_CONTROLLER
1717 .ndo_poll_controller = cpsw_ndo_poll_controller,
1718#endif
3b72c2fe
M		 1719 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1720 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
df828598
M		 1721};
1722
52c4f0ec
M		 1723static int cpsw_get_regs_len(struct net_device *ndev)
1724{
1725 struct cpsw_priv *priv = netdev_priv(ndev);
1726
1727 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1728}
1729
1730static void cpsw_get_regs(struct net_device *ndev,
1731 struct ethtool_regs *regs, void *p)
1732{
1733 struct cpsw_priv *priv = netdev_priv(ndev);
1734 u32 *reg = p;
1735
1736 /* update CPSW IP version */
1737 regs->version = priv->version;
1738
1739 cpsw_ale_dump(priv->ale, reg);
1740}
1741
df828598
M		 1742static void cpsw_get_drvinfo(struct net_device *ndev,
1743 struct ethtool_drvinfo *info)
1744{
1745 struct cpsw_priv *priv = netdev_priv(ndev);
7826d43f 1746
52c4f0ec 1747 strlcpy(info->driver, "cpsw", sizeof(info->driver));
7826d43f
JP		 1748 strlcpy(info->version, "1.0", sizeof(info->version));
1749 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
52c4f0ec 1750 info->regdump_len = cpsw_get_regs_len(ndev);
df828598
M		 1751}
1752
1753static u32 cpsw_get_msglevel(struct net_device *ndev)
1754{
1755 struct cpsw_priv *priv = netdev_priv(ndev);
1756 return priv->msg_enable;
1757}
1758
1759static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1760{
1761 struct cpsw_priv *priv = netdev_priv(ndev);
1762 priv->msg_enable = value;
1763}
1764
2e5b38ab
RC		 1765static int cpsw_get_ts_info(struct net_device *ndev,
1766 struct ethtool_ts_info *info)
1767{
1768#ifdef CONFIG_TI_CPTS
1769 struct cpsw_priv *priv = netdev_priv(ndev);
1770
1771 info->so_timestamping =
1772 SOF_TIMESTAMPING_TX_HARDWARE |
1773 SOF_TIMESTAMPING_TX_SOFTWARE |
1774 SOF_TIMESTAMPING_RX_HARDWARE |
1775 SOF_TIMESTAMPING_RX_SOFTWARE |
1776 SOF_TIMESTAMPING_SOFTWARE |
1777 SOF_TIMESTAMPING_RAW_HARDWARE;
9232b16d 1778 info->phc_index = priv->cpts->phc_index;
2e5b38ab
RC		 1779 info->tx_types =
1780 (1 << HWTSTAMP_TX_OFF) |
1781 (1 << HWTSTAMP_TX_ON);
1782 info->rx_filters =
1783 (1 << HWTSTAMP_FILTER_NONE) |
1784 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1785#else
1786 info->so_timestamping =
1787 SOF_TIMESTAMPING_TX_SOFTWARE |
1788 SOF_TIMESTAMPING_RX_SOFTWARE |
1789 SOF_TIMESTAMPING_SOFTWARE;
1790 info->phc_index = -1;
1791 info->tx_types = 0;
1792 info->rx_filters = 0;
1793#endif
1794 return 0;
1795}
1796
d3bb9c58
M		 1797static int cpsw_get_settings(struct net_device *ndev,
1798 struct ethtool_cmd *ecmd)
1799{
1800 struct cpsw_priv *priv = netdev_priv(ndev);
1801 int slave_no = cpsw_slave_index(priv);
1802
1803 if (priv->slaves[slave_no].phy)
1804 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1805 else
1806 return -EOPNOTSUPP;
1807}
1808
1809static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1810{
1811 struct cpsw_priv *priv = netdev_priv(ndev);
1812 int slave_no = cpsw_slave_index(priv);
1813
1814 if (priv->slaves[slave_no].phy)
1815 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1816 else
1817 return -EOPNOTSUPP;
1818}
1819
d8a64420
MU		 1820static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1821{
1822 struct cpsw_priv *priv = netdev_priv(ndev);
1823 int slave_no = cpsw_slave_index(priv);
1824
1825 wol->supported = 0;
1826 wol->wolopts = 0;
1827
1828 if (priv->slaves[slave_no].phy)
1829 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1830}
1831
1832static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1833{
1834 struct cpsw_priv *priv = netdev_priv(ndev);
1835 int slave_no = cpsw_slave_index(priv);
1836
1837 if (priv->slaves[slave_no].phy)
1838 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1839 else
1840 return -EOPNOTSUPP;
1841}
1842
1923d6e4
M		 1843static void cpsw_get_pauseparam(struct net_device *ndev,
1844 struct ethtool_pauseparam *pause)
1845{
1846 struct cpsw_priv *priv = netdev_priv(ndev);
1847
1848 pause->autoneg = AUTONEG_DISABLE;
1849 pause->rx_pause = priv->rx_pause ? true : false;
1850 pause->tx_pause = priv->tx_pause ? true : false;
1851}
1852
1853static int cpsw_set_pauseparam(struct net_device *ndev,
1854 struct ethtool_pauseparam *pause)
1855{
1856 struct cpsw_priv *priv = netdev_priv(ndev);
1857 bool link;
1858
1859 priv->rx_pause = pause->rx_pause ? true : false;
1860 priv->tx_pause = pause->tx_pause ? true : false;
1861
1862 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1863
1864 return 0;
1865}
1866
df828598
M		 1867static const struct ethtool_ops cpsw_ethtool_ops = {
1868 .get_drvinfo = cpsw_get_drvinfo,
1869 .get_msglevel = cpsw_get_msglevel,
1870 .set_msglevel = cpsw_set_msglevel,
1871 .get_link = ethtool_op_get_link,
2e5b38ab 1872 .get_ts_info = cpsw_get_ts_info,
d3bb9c58
M		 1873 .get_settings = cpsw_get_settings,
1874 .set_settings = cpsw_set_settings,
ff5b8ef2
M		 1875 .get_coalesce = cpsw_get_coalesce,
1876 .set_coalesce = cpsw_set_coalesce,
d9718546
M		 1877 .get_sset_count = cpsw_get_sset_count,
1878 .get_strings = cpsw_get_strings,
1879 .get_ethtool_stats = cpsw_get_ethtool_stats,
1923d6e4
M		 1880 .get_pauseparam = cpsw_get_pauseparam,
1881 .set_pauseparam = cpsw_set_pauseparam,
d8a64420
MU		 1882 .get_wol = cpsw_get_wol,
1883 .set_wol = cpsw_set_wol,
52c4f0ec
M		 1884 .get_regs_len = cpsw_get_regs_len,
1885 .get_regs = cpsw_get_regs,
df828598
M		 1886};
1887
549985ee
RC		 1888static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1889 u32 slave_reg_ofs, u32 sliver_reg_ofs)
df828598
M		 1890{
1891 void __iomem *regs = priv->regs;
1892 int slave_num = slave->slave_num;
1893 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1894
1895 slave->data = data;
549985ee
RC		 1896 slave->regs = regs + slave_reg_ofs;
1897 slave->sliver = regs + sliver_reg_ofs;
d9ba8f9e 1898 slave->port_vlan = data->dual_emac_res_vlan;
df828598
M		 1899}
1900
0ba517b1
MP		 1901#define AM33XX_CTRL_MAC_LO_REG(id) (0x630 + 0x8 * id)
1902#define AM33XX_CTRL_MAC_HI_REG(id) (0x630 + 0x8 * id + 0x4)
1903
1904static int cpsw_am33xx_cm_get_macid(struct device *dev, int slave,
1905 u8 *mac_addr)
1906{
1907 u32 macid_lo;
1908 u32 macid_hi;
1909 struct regmap *syscon;
1910
1911 syscon = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
1912 if (IS_ERR(syscon)) {
1913 if (PTR_ERR(syscon) == -ENODEV)
1914 return 0;
1915 return PTR_ERR(syscon);
1916 }
1917
1918 regmap_read(syscon, AM33XX_CTRL_MAC_LO_REG(slave), &macid_lo);
1919 regmap_read(syscon, AM33XX_CTRL_MAC_HI_REG(slave), &macid_hi);
1920
1921 mac_addr[5] = (macid_lo >> 8) & 0xff;
1922 mac_addr[4] = macid_lo & 0xff;
1923 mac_addr[3] = (macid_hi >> 24) & 0xff;
1924 mac_addr[2] = (macid_hi >> 16) & 0xff;
1925 mac_addr[1] = (macid_hi >> 8) & 0xff;
1926 mac_addr[0] = macid_hi & 0xff;
1927
1928 return 0;
1929}
1930
2eb32b0a
M		 1931static int cpsw_probe_dt(struct cpsw_platform_data *data,
1932 struct platform_device *pdev)
1933{
1934 struct device_node *node = pdev->dev.of_node;
1935 struct device_node *slave_node;
1936 int i = 0, ret;
1937 u32 prop;
1938
1939 if (!node)
1940 return -EINVAL;
1941
1942 if (of_property_read_u32(node, "slaves", &prop)) {
88c99ff6 1943 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2eb32b0a
M		 1944 return -EINVAL;
1945 }
1946 data->slaves = prop;
1947
e86ac13b 1948 if (of_property_read_u32(node, "active_slave", &prop)) {
88c99ff6 1949 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
aa1a15e2 1950 return -EINVAL;
78ca0b28 1951 }
e86ac13b 1952 data->active_slave = prop;
78ca0b28 1953
00ab94ee 1954 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
88c99ff6 1955 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
aa1a15e2 1956 return -EINVAL;
00ab94ee
RC		 1957 }
1958 data->cpts_clock_mult = prop;
1959
1960 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
88c99ff6 1961 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
aa1a15e2 1962 return -EINVAL;
00ab94ee
RC		 1963 }
1964 data->cpts_clock_shift = prop;
1965
aa1a15e2
DM		 1966 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1967 * sizeof(struct cpsw_slave_data),
1968 GFP_KERNEL);
b2adaca9 1969 if (!data->slave_data)
aa1a15e2 1970 return -ENOMEM;
2eb32b0a 1971
2eb32b0a 1972 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
88c99ff6 1973 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
aa1a15e2 1974 return -EINVAL;
2eb32b0a
M		 1975 }
1976 data->channels = prop;
1977
2eb32b0a 1978 if (of_property_read_u32(node, "ale_entries", &prop)) {
88c99ff6 1979 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
aa1a15e2 1980 return -EINVAL;
2eb32b0a
M		 1981 }
1982 data->ale_entries = prop;
1983
2eb32b0a 1984 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
88c99ff6 1985 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
aa1a15e2 1986 return -EINVAL;
2eb32b0a
M		 1987 }
1988 data->bd_ram_size = prop;
1989
1990 if (of_property_read_u32(node, "rx_descs", &prop)) {
88c99ff6 1991 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
aa1a15e2 1992 return -EINVAL;
2eb32b0a
M		 1993 }
1994 data->rx_descs = prop;
1995
1996 if (of_property_read_u32(node, "mac_control", &prop)) {
88c99ff6 1997 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
aa1a15e2 1998 return -EINVAL;
2eb32b0a
M		 1999 }
2000 data->mac_control = prop;
2001
281abd96
MP		 2002 if (of_property_read_bool(node, "dual_emac"))
2003 data->dual_emac = 1;
d9ba8f9e 2004
549985ee
RC		 2005 /*
2006 * Populate all the child nodes here...
2007 */
2008 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2009 /* We do not want to force this, as in some cases may not have child */
2010 if (ret)
88c99ff6 2011 dev_warn(&pdev->dev, "Doesn't have any child node\n");
549985ee 2012
f468b10e 2013 for_each_child_of_node(node, slave_node) {
2eb32b0a 2014 struct cpsw_slave_data *slave_data = data->slave_data + i;
2eb32b0a 2015 const void *mac_addr = NULL;
549985ee
RC		 2016 u32 phyid;
2017 int lenp;
2018 const __be32 *parp;
2019 struct device_node *mdio_node;
2020 struct platform_device *mdio;
2021
f468b10e
MP		 2022 /* This is no slave child node, continue */
2023 if (strcmp(slave_node->name, "slave"))
2024 continue;
2025
549985ee 2026 parp = of_get_property(slave_node, "phy_id", &lenp);
ce16294f 2027 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
88c99ff6 2028 dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
47276fcc 2029 goto no_phy_slave;
2eb32b0a 2030 }
549985ee
RC		 2031 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2032 phyid = be32_to_cpup(parp+1);
2033 mdio = of_find_device_by_node(mdio_node);
60e71ab5 2034 of_node_put(mdio_node);
6954cc1f 2035 if (!mdio) {
56fdb2e0 2036 dev_err(&pdev->dev, "Missing mdio platform device\n");
6954cc1f 2037 return -EINVAL;
f8d56d8f 2038 }
59993f48
JH		 2039 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2040 PHY_ID_FMT, mdio->name, phyid);
2eb32b0a 2041
47276fcc
M		 2042 slave_data->phy_if = of_get_phy_mode(slave_node);
2043 if (slave_data->phy_if < 0) {
2044 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2045 i);
2046 return slave_data->phy_if;
2047 }
2048
2049no_phy_slave:
2eb32b0a 2050 mac_addr = of_get_mac_address(slave_node);
0ba517b1 2051 if (mac_addr) {
2eb32b0a 2052 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
0ba517b1
MP		 2053 } else {
2054 if (of_machine_is_compatible("ti,am33xx")) {
2055 ret = cpsw_am33xx_cm_get_macid(&pdev->dev, i,
2056 slave_data->mac_addr);
2057 if (ret)
2058 return ret;
2059 }
2060 }
d9ba8f9e 2061 if (data->dual_emac) {
91c4166c 2062 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
d9ba8f9e 2063 &prop)) {
88c99ff6 2064 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
d9ba8f9e 2065 slave_data->dual_emac_res_vlan = i+1;
88c99ff6
GC		 2066 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2067 slave_data->dual_emac_res_vlan, i);
d9ba8f9e
M		 2068 } else {
2069 slave_data->dual_emac_res_vlan = prop;
2070 }
2071 }
2072
2eb32b0a 2073 i++;
3a27bfac
M		 2074 if (i == data->slaves)
2075 break;
2eb32b0a
M		 2076 }
2077
2078 return 0;
2eb32b0a
M		 2079}
2080
d9ba8f9e
M		 2081static int cpsw_probe_dual_emac(struct platform_device *pdev,
2082 struct cpsw_priv *priv)
2083{
2084 struct cpsw_platform_data *data = &priv->data;
2085 struct net_device *ndev;
2086 struct cpsw_priv *priv_sl2;
2087 int ret = 0, i;
2088
2089 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2090 if (!ndev) {
88c99ff6 2091 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
d9ba8f9e
M		 2092 return -ENOMEM;
2093 }
2094
2095 priv_sl2 = netdev_priv(ndev);
2096 spin_lock_init(&priv_sl2->lock);
2097 priv_sl2->data = *data;
2098 priv_sl2->pdev = pdev;
2099 priv_sl2->ndev = ndev;
2100 priv_sl2->dev = &ndev->dev;
2101 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2102 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2103
2104 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2105 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2106 ETH_ALEN);
88c99ff6 2107 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2108 } else {
2109 random_ether_addr(priv_sl2->mac_addr);
88c99ff6 2110 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2111 }
2112 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2113
2114 priv_sl2->slaves = priv->slaves;
2115 priv_sl2->clk = priv->clk;
2116
ff5b8ef2
M		 2117 priv_sl2->coal_intvl = 0;
2118 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2119
d9ba8f9e
M		 2120 priv_sl2->regs = priv->regs;
2121 priv_sl2->host_port = priv->host_port;
2122 priv_sl2->host_port_regs = priv->host_port_regs;
2123 priv_sl2->wr_regs = priv->wr_regs;
d9718546 2124 priv_sl2->hw_stats = priv->hw_stats;
d9ba8f9e
M		 2125 priv_sl2->dma = priv->dma;
2126 priv_sl2->txch = priv->txch;
2127 priv_sl2->rxch = priv->rxch;
2128 priv_sl2->ale = priv->ale;
2129 priv_sl2->emac_port = 1;
2130 priv->slaves[1].ndev = ndev;
2131 priv_sl2->cpts = priv->cpts;
2132 priv_sl2->version = priv->version;
2133
2134 for (i = 0; i < priv->num_irqs; i++) {
2135 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2136 priv_sl2->num_irqs = priv->num_irqs;
2137 }
f646968f 2138 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d9ba8f9e
M		 2139
2140 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2141 ndev->ethtool_ops = &cpsw_ethtool_ops;
d9ba8f9e
M		 2142 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2143
2144 /* register the network device */
2145 SET_NETDEV_DEV(ndev, &pdev->dev);
2146 ret = register_netdev(ndev);
2147 if (ret) {
88c99ff6 2148 dev_err(&pdev->dev, "cpsw: error registering net device\n");
d9ba8f9e
M		 2149 free_netdev(ndev);
2150 ret = -ENODEV;
2151 }
2152
2153 return ret;
2154}
2155
663e12e6 2156static int cpsw_probe(struct platform_device *pdev)
df828598 2157{
d1bd9acf 2158 struct cpsw_platform_data *data;
df828598
M		 2159 struct net_device *ndev;
2160 struct cpsw_priv *priv;
2161 struct cpdma_params dma_params;
2162 struct cpsw_ale_params ale_params;
aa1a15e2
DM		 2163 void __iomem *ss_regs;
2164 struct resource *res, *ss_res;
549985ee 2165 u32 slave_offset, sliver_offset, slave_size;
5087b915
FB		 2166 int ret = 0, i;
2167 int irq;
df828598 2168
df828598
M		 2169 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2170 if (!ndev) {
88c99ff6 2171 dev_err(&pdev->dev, "error allocating net_device\n");
df828598
M		 2172 return -ENOMEM;
2173 }
2174
2175 platform_set_drvdata(pdev, ndev);
2176 priv = netdev_priv(ndev);
2177 spin_lock_init(&priv->lock);
df828598
M		 2178 priv->pdev = pdev;
2179 priv->ndev = ndev;
2180 priv->dev = &ndev->dev;
2181 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2182 priv->rx_packet_max = max(rx_packet_max, 128);
9232b16d 2183 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
7dcf313a 2184 priv->irq_enabled = true;
ab8e99d2 2185 if (!priv->cpts) {
88c99ff6 2186 dev_err(&pdev->dev, "error allocating cpts\n");
4d507dff 2187 ret = -ENOMEM;
9232b16d
M		 2188 goto clean_ndev_ret;
2189 }
df828598 2190
1fb19aa7
VH		 2191 /*
2192 * This may be required here for child devices.
2193 */
2194 pm_runtime_enable(&pdev->dev);
2195
739683b4
M		 2196 /* Select default pin state */
2197 pinctrl_pm_select_default_state(&pdev->dev);
2198
2eb32b0a 2199 if (cpsw_probe_dt(&priv->data, pdev)) {
88c99ff6 2200 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2eb32b0a 2201 ret = -ENODEV;
aa1a15e2 2202 goto clean_runtime_disable_ret;
2eb32b0a
M		 2203 }
2204 data = &priv->data;
2205
df828598
M		 2206 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2207 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
88c99ff6 2208 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
df828598 2209 } else {
7efd26d0 2210 eth_random_addr(priv->mac_addr);
88c99ff6 2211 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
df828598
M		 2212 }
2213
2214 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2215
aa1a15e2
DM		 2216 priv->slaves = devm_kzalloc(&pdev->dev,
2217 sizeof(struct cpsw_slave) * data->slaves,
2218 GFP_KERNEL);
df828598 2219 if (!priv->slaves) {
aa1a15e2
DM		 2220 ret = -ENOMEM;
2221 goto clean_runtime_disable_ret;
df828598
M		 2222 }
2223 for (i = 0; i < data->slaves; i++)
2224 priv->slaves[i].slave_num = i;
2225
d9ba8f9e
M		 2226 priv->slaves[0].ndev = ndev;
2227 priv->emac_port = 0;
2228
aa1a15e2 2229 priv->clk = devm_clk_get(&pdev->dev, "fck");
df828598 2230 if (IS_ERR(priv->clk)) {
aa1a15e2 2231 dev_err(priv->dev, "fck is not found\n");
f150bd7f 2232 ret = -ENODEV;
aa1a15e2 2233 goto clean_runtime_disable_ret;
df828598 2234 }
ff5b8ef2
M		 2235 priv->coal_intvl = 0;
2236 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
df828598 2237
aa1a15e2
DM		 2238 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2239 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2240 if (IS_ERR(ss_regs)) {
2241 ret = PTR_ERR(ss_regs);
2242 goto clean_runtime_disable_ret;
df828598 2243 }
549985ee 2244 priv->regs = ss_regs;
549985ee 2245 priv->host_port = HOST_PORT_NUM;
df828598 2246
f280e89a
M		 2247 /* Need to enable clocks with runtime PM api to access module
2248 * registers
2249 */
2250 pm_runtime_get_sync(&pdev->dev);
2251 priv->version = readl(&priv->regs->id_ver);
2252 pm_runtime_put_sync(&pdev->dev);
2253
aa1a15e2
DM		 2254 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2255 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2256 if (IS_ERR(priv->wr_regs)) {
2257 ret = PTR_ERR(priv->wr_regs);
2258 goto clean_runtime_disable_ret;
df828598 2259 }
df828598
M		 2260
2261 memset(&dma_params, 0, sizeof(dma_params));
549985ee
RC		 2262 memset(&ale_params, 0, sizeof(ale_params));
2263
2264 switch (priv->version) {
2265 case CPSW_VERSION_1:
2266 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
d9718546
M		 2267 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2268 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
549985ee
RC		 2269 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2270 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2271 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2272 slave_offset = CPSW1_SLAVE_OFFSET;
2273 slave_size = CPSW1_SLAVE_SIZE;
2274 sliver_offset = CPSW1_SLIVER_OFFSET;
2275 dma_params.desc_mem_phys = 0;
2276 break;
2277 case CPSW_VERSION_2:
c193f365 2278 case CPSW_VERSION_3:
926489be 2279 case CPSW_VERSION_4:
549985ee 2280 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
d9718546
M		 2281 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2282 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
549985ee
RC		 2283 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2284 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2285 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2286 slave_offset = CPSW2_SLAVE_OFFSET;
2287 slave_size = CPSW2_SLAVE_SIZE;
2288 sliver_offset = CPSW2_SLIVER_OFFSET;
2289 dma_params.desc_mem_phys =
aa1a15e2 2290 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
549985ee
RC		 2291 break;
2292 default:
2293 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2294 ret = -ENODEV;
aa1a15e2 2295 goto clean_runtime_disable_ret;
549985ee
RC		 2296 }
2297 for (i = 0; i < priv->data.slaves; i++) {
2298 struct cpsw_slave *slave = &priv->slaves[i];
2299 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2300 slave_offset += slave_size;
2301 sliver_offset += SLIVER_SIZE;
2302 }
2303
df828598 2304 dma_params.dev = &pdev->dev;
549985ee
RC		 2305 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2306 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2307 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2308 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2309 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
df828598
M		 2310
2311 dma_params.num_chan = data->channels;
2312 dma_params.has_soft_reset = true;
2313 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2314 dma_params.desc_mem_size = data->bd_ram_size;
2315 dma_params.desc_align = 16;
2316 dma_params.has_ext_regs = true;
549985ee 2317 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
df828598
M		 2318
2319 priv->dma = cpdma_ctlr_create(&dma_params);
2320 if (!priv->dma) {
2321 dev_err(priv->dev, "error initializing dma\n");
2322 ret = -ENOMEM;
aa1a15e2 2323 goto clean_runtime_disable_ret;
df828598
M		 2324 }
2325
2326 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2327 cpsw_tx_handler);
2328 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2329 cpsw_rx_handler);
2330
2331 if (WARN_ON(!priv->txch || !priv->rxch)) {
2332 dev_err(priv->dev, "error initializing dma channels\n");
2333 ret = -ENOMEM;
2334 goto clean_dma_ret;
2335 }
2336
df828598 2337 ale_params.dev = &ndev->dev;
df828598
M		 2338 ale_params.ale_ageout = ale_ageout;
2339 ale_params.ale_entries = data->ale_entries;
2340 ale_params.ale_ports = data->slaves;
2341
2342 priv->ale = cpsw_ale_create(&ale_params);
2343 if (!priv->ale) {
2344 dev_err(priv->dev, "error initializing ale engine\n");
2345 ret = -ENODEV;
2346 goto clean_dma_ret;
2347 }
2348
2349 ndev->irq = platform_get_irq(pdev, 0);
2350 if (ndev->irq < 0) {
2351 dev_err(priv->dev, "error getting irq resource\n");
2352 ret = -ENOENT;
2353 goto clean_ale_ret;
2354 }
2355
5087b915
FB		 2356 irq = platform_get_irq(pdev, 0);
2357 if (irq < 0)
2358 goto clean_ale_ret;
c2b32e58 2359
5087b915
FB		 2360 priv->irqs_table[0] = irq;
2361 ret = devm_request_irq(&pdev->dev, irq, cpsw_interrupt,
2362 0, dev_name(&pdev->dev), priv);
2363 if (ret < 0) {
2364 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2365 goto clean_ale_ret;
2366 }
c2b32e58 2367
5087b915
FB		 2368 irq = platform_get_irq(pdev, 1);
2369 if (irq < 0)
2370 goto clean_ale_ret;
2371
2372 priv->irqs_table[1] = irq;
2373 ret = devm_request_irq(&pdev->dev, irq, cpsw_interrupt,
2374 0, dev_name(&pdev->dev), priv);
2375 if (ret < 0) {
2376 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2377 goto clean_ale_ret;
2378 }
2379
2380 irq = platform_get_irq(pdev, 2);
2381 if (irq < 0)
2382 goto clean_ale_ret;
2383
2384 priv->irqs_table[2] = irq;
2385 ret = devm_request_irq(&pdev->dev, irq, cpsw_interrupt,
2386 0, dev_name(&pdev->dev), priv);
2387 if (ret < 0) {
2388 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2389 goto clean_ale_ret;
2390 }
2391
2392 irq = platform_get_irq(pdev, 3);
2393 if (irq < 0)
2394 goto clean_ale_ret;
2395
2396 priv->irqs_table[3] = irq;
2397 ret = devm_request_irq(&pdev->dev, irq, cpsw_interrupt,
2398 0, dev_name(&pdev->dev), priv);
2399 if (ret < 0) {
2400 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2401 goto clean_ale_ret;
df828598
M		 2402 }
2403
5087b915 2404 priv->num_irqs = 4;
c2b32e58 2405
f646968f 2406 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
df828598
M		 2407
2408 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2409 ndev->ethtool_ops = &cpsw_ethtool_ops;
df828598
M		 2410 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2411
2412 /* register the network device */
2413 SET_NETDEV_DEV(ndev, &pdev->dev);
2414 ret = register_netdev(ndev);
2415 if (ret) {
2416 dev_err(priv->dev, "error registering net device\n");
2417 ret = -ENODEV;
aa1a15e2 2418 goto clean_ale_ret;
df828598
M		 2419 }
2420
1a3b5056
OJ		 2421 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2422 &ss_res->start, ndev->irq);
df828598 2423
d9ba8f9e
M		 2424 if (priv->data.dual_emac) {
2425 ret = cpsw_probe_dual_emac(pdev, priv);
2426 if (ret) {
2427 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
aa1a15e2 2428 goto clean_ale_ret;
d9ba8f9e
M		 2429 }
2430 }
2431
df828598
M		 2432 return 0;
2433
df828598
M		 2434clean_ale_ret:
2435 cpsw_ale_destroy(priv->ale);
2436clean_dma_ret:
2437 cpdma_chan_destroy(priv->txch);
2438 cpdma_chan_destroy(priv->rxch);
2439 cpdma_ctlr_destroy(priv->dma);
aa1a15e2 2440clean_runtime_disable_ret:
f150bd7f 2441 pm_runtime_disable(&pdev->dev);
df828598 2442clean_ndev_ret:
d1bd9acf 2443 free_netdev(priv->ndev);
df828598
M		 2444 return ret;
2445}
2446
030b16a0
M		 2447static int cpsw_remove_child_device(struct device *dev, void *c)
2448{
2449 struct platform_device *pdev = to_platform_device(dev);
2450
2451 of_device_unregister(pdev);
2452
2453 return 0;
2454}
2455
663e12e6 2456static int cpsw_remove(struct platform_device *pdev)
df828598
M		 2457{
2458 struct net_device *ndev = platform_get_drvdata(pdev);
2459 struct cpsw_priv *priv = netdev_priv(ndev);
2460
d1bd9acf
SS		 2461 if (priv->data.dual_emac)
2462 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2463 unregister_netdev(ndev);
df828598 2464
df828598
M		 2465 cpsw_ale_destroy(priv->ale);
2466 cpdma_chan_destroy(priv->txch);
2467 cpdma_chan_destroy(priv->rxch);
2468 cpdma_ctlr_destroy(priv->dma);
f150bd7f 2469 pm_runtime_disable(&pdev->dev);
030b16a0 2470 device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
d1bd9acf
SS		 2471 if (priv->data.dual_emac)
2472 free_netdev(cpsw_get_slave_ndev(priv, 1));
df828598 2473 free_netdev(ndev);
df828598
M		 2474 return 0;
2475}
2476
2477static int cpsw_suspend(struct device *dev)
2478{
2479 struct platform_device *pdev = to_platform_device(dev);
2480 struct net_device *ndev = platform_get_drvdata(pdev);
b90fc27a 2481 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2482
618073e3
M		 2483 if (priv->data.dual_emac) {
2484 int i;
1e7a2e21 2485
618073e3
M		 2486 for (i = 0; i < priv->data.slaves; i++) {
2487 if (netif_running(priv->slaves[i].ndev))
2488 cpsw_ndo_stop(priv->slaves[i].ndev);
2489 soft_reset_slave(priv->slaves + i);
2490 }
2491 } else {
2492 if (netif_running(ndev))
2493 cpsw_ndo_stop(ndev);
2494 for_each_slave(priv, soft_reset_slave);
2495 }
1e7a2e21 2496
f150bd7f
M		 2497 pm_runtime_put_sync(&pdev->dev);
2498
739683b4
M		 2499 /* Select sleep pin state */
2500 pinctrl_pm_select_sleep_state(&pdev->dev);
2501
df828598
M		 2502 return 0;
2503}
2504
2505static int cpsw_resume(struct device *dev)
2506{
2507 struct platform_device *pdev = to_platform_device(dev);
2508 struct net_device *ndev = platform_get_drvdata(pdev);
618073e3 2509 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2510
f150bd7f 2511 pm_runtime_get_sync(&pdev->dev);
739683b4
M		 2512
2513 /* Select default pin state */
2514 pinctrl_pm_select_default_state(&pdev->dev);
2515
618073e3
M		 2516 if (priv->data.dual_emac) {
2517 int i;
2518
2519 for (i = 0; i < priv->data.slaves; i++) {
2520 if (netif_running(priv->slaves[i].ndev))
2521 cpsw_ndo_open(priv->slaves[i].ndev);
2522 }
2523 } else {
2524 if (netif_running(ndev))
2525 cpsw_ndo_open(ndev);
2526 }
df828598
M		 2527 return 0;
2528}
2529
2530static const struct dev_pm_ops cpsw_pm_ops = {
2531 .suspend = cpsw_suspend,
2532 .resume = cpsw_resume,
2533};
2534
2eb32b0a
M		 2535static const struct of_device_id cpsw_of_mtable[] = {
2536 { .compatible = "ti,cpsw", },
2537 { /* sentinel */ },
2538};
4bc21d41 2539MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2eb32b0a 2540
df828598
M		 2541static struct platform_driver cpsw_driver = {
2542 .driver = {
2543 .name = "cpsw",
df828598 2544 .pm = &cpsw_pm_ops,
1e5c76d4 2545 .of_match_table = cpsw_of_mtable,
df828598
M		 2546 },
2547 .probe = cpsw_probe,
663e12e6 2548 .remove = cpsw_remove,
df828598
M		 2549};
2550
2551static int __init cpsw_init(void)
2552{
2553 return platform_driver_register(&cpsw_driver);
2554}
2555late_initcall(cpsw_init);
2556
2557static void __exit cpsw_exit(void)
2558{
2559 platform_driver_unregister(&cpsw_driver);
2560}
2561module_exit(cpsw_exit);
2562
2563MODULE_LICENSE("GPL");
2564MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2565MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2566MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
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