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net: ethernet: ti: cpsw: move links on h/w registers to cpsw_common
[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
2e5b38ab 27#include <linux/net_tstamp.h>
df828598
M		 28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
f150bd7f 31#include <linux/pm_runtime.h>
1d147ccb 32#include <linux/gpio.h>
2eb32b0a 33#include <linux/of.h>
9e42f715 34#include <linux/of_mdio.h>
2eb32b0a
M		 35#include <linux/of_net.h>
36#include <linux/of_device.h>
3b72c2fe 37#include <linux/if_vlan.h>
df828598 38
739683b4 39#include <linux/pinctrl/consumer.h>
df828598 40
dbe34724 41#include "cpsw.h"
df828598 42#include "cpsw_ale.h"
2e5b38ab 43#include "cpts.h"
df828598
M		 44#include "davinci_cpdma.h"
45
46#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55#define cpsw_info(priv, type, format, ...) \
56do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59} while (0)
60
61#define cpsw_err(priv, type, format, ...) \
62do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65} while (0)
66
67#define cpsw_dbg(priv, type, format, ...) \
68do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71} while (0)
72
73#define cpsw_notice(priv, type, format, ...) \
74do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77} while (0)
78
5c50a856
M		 79#define ALE_ALL_PORTS 0x7
80
df828598
M		 81#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
e90cfac6
RC		 85#define CPSW_VERSION_1 0x19010a
86#define CPSW_VERSION_2 0x19010c
c193f365 87#define CPSW_VERSION_3 0x19010f
926489be 88#define CPSW_VERSION_4 0x190112
549985ee
RC		 89
90#define HOST_PORT_NUM 0
91#define SLIVER_SIZE 0x40
92
93#define CPSW1_HOST_PORT_OFFSET 0x028
94#define CPSW1_SLAVE_OFFSET 0x050
95#define CPSW1_SLAVE_SIZE 0x040
96#define CPSW1_CPDMA_OFFSET 0x100
97#define CPSW1_STATERAM_OFFSET 0x200
d9718546 98#define CPSW1_HW_STATS 0x400
549985ee
RC		 99#define CPSW1_CPTS_OFFSET 0x500
100#define CPSW1_ALE_OFFSET 0x600
101#define CPSW1_SLIVER_OFFSET 0x700
102
103#define CPSW2_HOST_PORT_OFFSET 0x108
104#define CPSW2_SLAVE_OFFSET 0x200
105#define CPSW2_SLAVE_SIZE 0x100
106#define CPSW2_CPDMA_OFFSET 0x800
d9718546 107#define CPSW2_HW_STATS 0x900
549985ee
RC		 108#define CPSW2_STATERAM_OFFSET 0xa00
109#define CPSW2_CPTS_OFFSET 0xc00
110#define CPSW2_ALE_OFFSET 0xd00
111#define CPSW2_SLIVER_OFFSET 0xd80
112#define CPSW2_BD_OFFSET 0x2000
113
df828598
M		 114#define CPDMA_RXTHRESH 0x0c0
115#define CPDMA_RXFREE 0x0e0
116#define CPDMA_TXHDP 0x00
117#define CPDMA_RXHDP 0x20
118#define CPDMA_TXCP 0x40
119#define CPDMA_RXCP 0x60
120
df828598
M		 121#define CPSW_POLL_WEIGHT 64
122#define CPSW_MIN_PACKET_SIZE 60
123#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125#define RX_PRIORITY_MAPPING 0x76543210
126#define TX_PRIORITY_MAPPING 0x33221100
127#define CPDMA_TX_PRIORITY_MAP 0x76543210
128
3b72c2fe
M		 129#define CPSW_VLAN_AWARE BIT(1)
130#define CPSW_ALE_VLAN_AWARE 1
131
35717d8d
JO		 132#define CPSW_FIFO_NORMAL_MODE (0 << 16)
133#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
d9ba8f9e 135
ff5b8ef2
M		 136#define CPSW_INTPACEEN (0x3f << 16)
137#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138#define CPSW_CMINTMAX_CNT 63
139#define CPSW_CMINTMIN_CNT 2
140#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
d3bb9c58
M		 143#define cpsw_slave_index(priv) \
144 ((priv->data.dual_emac) ? priv->emac_port : \
145 priv->data.active_slave)
146
df828598
M		 147static int debug_level;
148module_param(debug_level, int, 0);
149MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
150
151static int ale_ageout = 10;
152module_param(ale_ageout, int, 0);
153MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
154
155static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
156module_param(rx_packet_max, int, 0);
157MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
158
996a5c27 159struct cpsw_wr_regs {
df828598
M		 160 u32 id_ver;
161 u32 soft_reset;
162 u32 control;
163 u32 int_control;
164 u32 rx_thresh_en;
165 u32 rx_en;
166 u32 tx_en;
167 u32 misc_en;
ff5b8ef2
M		 168 u32 mem_allign1[8];
169 u32 rx_thresh_stat;
170 u32 rx_stat;
171 u32 tx_stat;
172 u32 misc_stat;
173 u32 mem_allign2[8];
174 u32 rx_imax;
175 u32 tx_imax;
176
df828598
M		 177};
178
996a5c27 179struct cpsw_ss_regs {
df828598
M		 180 u32 id_ver;
181 u32 control;
182 u32 soft_reset;
183 u32 stat_port_en;
184 u32 ptype;
bd357af2
RC		 185 u32 soft_idle;
186 u32 thru_rate;
187 u32 gap_thresh;
188 u32 tx_start_wds;
189 u32 flow_control;
190 u32 vlan_ltype;
191 u32 ts_ltype;
192 u32 dlr_ltype;
df828598
M		 193};
194
9750a3ad
RC		 195/* CPSW_PORT_V1 */
196#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
197#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
198#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
199#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
200#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
201#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
202#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
203#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
204
205/* CPSW_PORT_V2 */
206#define CPSW2_CONTROL 0x00 /* Control Register */
207#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
208#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
209#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
210#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
211#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
212#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
213
214/* CPSW_PORT_V1 and V2 */
215#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
216#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
217#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
218
219/* CPSW_PORT_V2 only */
220#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
221#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
222#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
223#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
224#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
225#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
226#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
227#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
228
229/* Bit definitions for the CPSW2_CONTROL register */
230#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
231#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
232#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
233#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
234#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
235#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
236#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
237#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
238#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
239#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
09c55372
GC		 240#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
241#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
9750a3ad
RC		 242#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
243#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
244#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
245#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
246#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
247
09c55372
GC		 248#define CTRL_V2_TS_BITS \
249 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
250 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
9750a3ad 251
09c55372
GC		 252#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
253#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
254#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
255
256
257#define CTRL_V3_TS_BITS \
258 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
259 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
260 TS_LTYPE1_EN)
261
262#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
263#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
264#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
9750a3ad
RC		 265
266/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268#define TS_SEQ_ID_OFFSET_MASK (0x3f)
269#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270#define TS_MSG_TYPE_EN_MASK (0xffff)
271
272/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598 274
2e5b38ab
RC		 275/* Bit definitions for the CPSW1_TS_CTL register */
276#define CPSW_V1_TS_RX_EN BIT(0)
277#define CPSW_V1_TS_TX_EN BIT(4)
278#define CPSW_V1_MSG_TYPE_OFS 16
279
280/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
282
df828598
M		 283struct cpsw_host_regs {
284 u32 max_blks;
285 u32 blk_cnt;
d9ba8f9e 286 u32 tx_in_ctl;
df828598
M		 287 u32 port_vlan;
288 u32 tx_pri_map;
289 u32 cpdma_tx_pri_map;
290 u32 cpdma_rx_chan_map;
291};
292
293struct cpsw_sliver_regs {
294 u32 id_ver;
295 u32 mac_control;
296 u32 mac_status;
297 u32 soft_reset;
298 u32 rx_maxlen;
299 u32 __reserved_0;
300 u32 rx_pause;
301 u32 tx_pause;
302 u32 __reserved_1;
303 u32 rx_pri_map;
304};
305
d9718546
M		 306struct cpsw_hw_stats {
307 u32 rxgoodframes;
308 u32 rxbroadcastframes;
309 u32 rxmulticastframes;
310 u32 rxpauseframes;
311 u32 rxcrcerrors;
312 u32 rxaligncodeerrors;
313 u32 rxoversizedframes;
314 u32 rxjabberframes;
315 u32 rxundersizedframes;
316 u32 rxfragments;
317 u32 __pad_0[2];
318 u32 rxoctets;
319 u32 txgoodframes;
320 u32 txbroadcastframes;
321 u32 txmulticastframes;
322 u32 txpauseframes;
323 u32 txdeferredframes;
324 u32 txcollisionframes;
325 u32 txsinglecollframes;
326 u32 txmultcollframes;
327 u32 txexcessivecollisions;
328 u32 txlatecollisions;
329 u32 txunderrun;
330 u32 txcarriersenseerrors;
331 u32 txoctets;
332 u32 octetframes64;
333 u32 octetframes65t127;
334 u32 octetframes128t255;
335 u32 octetframes256t511;
336 u32 octetframes512t1023;
337 u32 octetframes1024tup;
338 u32 netoctets;
339 u32 rxsofoverruns;
340 u32 rxmofoverruns;
341 u32 rxdmaoverruns;
342};
343
df828598 344struct cpsw_slave {
9750a3ad 345 void __iomem *regs;
df828598
M		 346 struct cpsw_sliver_regs __iomem *sliver;
347 int slave_num;
348 u32 mac_control;
349 struct cpsw_slave_data *data;
350 struct phy_device *phy;
d9ba8f9e
M		 351 struct net_device *ndev;
352 u32 port_vlan;
353 u32 open_stat;
df828598
M		 354};
355
9750a3ad
RC		 356static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
357{
358 return __raw_readl(slave->regs + offset);
359}
360
361static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
362{
363 __raw_writel(val, slave->regs + offset);
364}
365
649a1688 366struct cpsw_common {
56e31bd8 367 struct device *dev;
5d8d0d4d
IK		 368 struct cpsw_ss_regs __iomem *regs;
369 struct cpsw_wr_regs __iomem *wr_regs;
370 u8 __iomem *hw_stats;
371 struct cpsw_host_regs __iomem *host_port_regs;
649a1688
IK		 372};
373
374struct cpsw_priv {
df828598 375 struct net_device *ndev;
32a7432c
M		 376 struct napi_struct napi_rx;
377 struct napi_struct napi_tx;
df828598
M		 378 struct device *dev;
379 struct cpsw_platform_data data;
df828598 380 u32 msg_enable;
e90cfac6 381 u32 version;
ff5b8ef2
M		 382 u32 coal_intvl;
383 u32 bus_freq_mhz;
df828598 384 int rx_packet_max;
df828598
M		 385 u8 mac_addr[ETH_ALEN];
386 struct cpsw_slave *slaves;
387 struct cpdma_ctlr *dma;
388 struct cpdma_chan *txch, *rxch;
389 struct cpsw_ale *ale;
1923d6e4
M		 390 bool rx_pause;
391 bool tx_pause;
7da11600
M		 392 bool quirk_irq;
393 bool rx_irq_disabled;
394 bool tx_irq_disabled;
df828598
M		 395 /* snapshot of IRQ numbers */
396 u32 irqs_table[4];
397 u32 num_irqs;
9232b16d 398 struct cpts *cpts;
d9ba8f9e 399 u32 emac_port;
649a1688 400 struct cpsw_common *cpsw;
df828598
M		 401};
402
d9718546
M		 403struct cpsw_stats {
404 char stat_string[ETH_GSTRING_LEN];
405 int type;
406 int sizeof_stat;
407 int stat_offset;
408};
409
410enum {
411 CPSW_STATS,
412 CPDMA_RX_STATS,
413 CPDMA_TX_STATS,
414};
415
416#define CPSW_STAT(m) CPSW_STATS, \
417 sizeof(((struct cpsw_hw_stats *)0)->m), \
418 offsetof(struct cpsw_hw_stats, m)
419#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
420 sizeof(((struct cpdma_chan_stats *)0)->m), \
421 offsetof(struct cpdma_chan_stats, m)
422#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
423 sizeof(((struct cpdma_chan_stats *)0)->m), \
424 offsetof(struct cpdma_chan_stats, m)
425
426static const struct cpsw_stats cpsw_gstrings_stats[] = {
427 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
428 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
429 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
430 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
431 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
432 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
433 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
434 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
435 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
436 { "Rx Fragments", CPSW_STAT(rxfragments) },
437 { "Rx Octets", CPSW_STAT(rxoctets) },
438 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
439 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
440 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
441 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
442 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
443 { "Collisions", CPSW_STAT(txcollisionframes) },
444 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
445 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
446 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
447 { "Late Collisions", CPSW_STAT(txlatecollisions) },
448 { "Tx Underrun", CPSW_STAT(txunderrun) },
449 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
450 { "Tx Octets", CPSW_STAT(txoctets) },
451 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
452 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
453 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
454 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
455 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
456 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
457 { "Net Octets", CPSW_STAT(netoctets) },
458 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
459 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
460 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
461 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
462 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
463 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
464 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
465 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
466 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
467 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
468 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
469 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
470 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
471 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
472 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
473 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
474 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
475 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
476 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
477 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
478 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
479 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
480 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
481 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
482 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
483 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
484 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
485 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
486 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
487};
488
489#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
490
649a1688 491#define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
df828598 492#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
d9ba8f9e
M		 493#define for_each_slave(priv, func, arg...) \
494 do { \
6e6ceaed
SS		 495 struct cpsw_slave *slave; \
496 int n; \
d9ba8f9e
M		 497 if (priv->data.dual_emac) \
498 (func)((priv)->slaves + priv->emac_port, ##arg);\
499 else \
6e6ceaed
SS		 500 for (n = (priv)->data.slaves, \
501 slave = (priv)->slaves; \
502 n; n--) \
503 (func)(slave++, ##arg); \
d9ba8f9e 504 } while (0)
d9ba8f9e 505#define cpsw_get_slave_priv(priv, __slave_no__) \
1973db0d
M		 506 (((__slave_no__ < priv->data.slaves) && \
507 (priv->slaves[__slave_no__].ndev)) ? \
d9ba8f9e
M		 508 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
509
510#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
511 do { \
512 if (!priv->data.dual_emac) \
513 break; \
514 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
82b52104 515 ndev = priv->slaves[0].ndev; \
d9ba8f9e
M		 516 priv = netdev_priv(ndev); \
517 skb->dev = ndev; \
518 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
82b52104 519 ndev = priv->slaves[1].ndev; \
d9ba8f9e
M		 520 priv = netdev_priv(ndev); \
521 skb->dev = ndev; \
522 } \
df828598 523 } while (0)
d9ba8f9e
M		 524#define cpsw_add_mcast(priv, addr) \
525 do { \
526 if (priv->data.dual_emac) { \
527 struct cpsw_slave *slave = priv->slaves + \
528 priv->emac_port; \
6f1f5836 529 int slave_port = cpsw_get_slave_port( \
d9ba8f9e
M		 530 slave->slave_num); \
531 cpsw_ale_add_mcast(priv->ale, addr, \
71a2cbb7 532 1 << slave_port | ALE_PORT_HOST, \
d9ba8f9e
M		 533 ALE_VLAN, slave->port_vlan, 0); \
534 } else { \
535 cpsw_ale_add_mcast(priv->ale, addr, \
61f1cef9 536 ALE_ALL_PORTS, \
d9ba8f9e
M		 537 0, 0, 0); \
538 } \
539 } while (0)
540
6f1f5836 541static inline int cpsw_get_slave_port(u32 slave_num)
d9ba8f9e 542{
71a2cbb7 543 return slave_num + 1;
d9ba8f9e 544}
df828598 545
0cd8f9cc
M		 546static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
547{
548 struct cpsw_priv *priv = netdev_priv(ndev);
549 struct cpsw_ale *ale = priv->ale;
550 int i;
551
552 if (priv->data.dual_emac) {
553 bool flag = false;
554
555 /* Enabling promiscuous mode for one interface will be
556 * common for both the interface as the interface shares
557 * the same hardware resource.
558 */
0d961b3b 559 for (i = 0; i < priv->data.slaves; i++)
0cd8f9cc
M		 560 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
561 flag = true;
562
563 if (!enable && flag) {
564 enable = true;
565 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
566 }
567
568 if (enable) {
569 /* Enable Bypass */
570 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
571
572 dev_dbg(&ndev->dev, "promiscuity enabled\n");
573 } else {
574 /* Disable Bypass */
575 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
576 dev_dbg(&ndev->dev, "promiscuity disabled\n");
577 }
578 } else {
579 if (enable) {
580 unsigned long timeout = jiffies + HZ;
581
6f979eb3
LS		 582 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
583 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 584 cpsw_ale_control_set(ale, i,
585 ALE_PORT_NOLEARN, 1);
586 cpsw_ale_control_set(ale, i,
587 ALE_PORT_NO_SA_UPDATE, 1);
588 }
589
590 /* Clear All Untouched entries */
591 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
592 do {
593 cpu_relax();
594 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
595 break;
596 } while (time_after(timeout, jiffies));
597 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
598
599 /* Clear all mcast from ALE */
61f1cef9 600 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
0cd8f9cc
M		 601
602 /* Flood All Unicast Packets to Host port */
603 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
604 dev_dbg(&ndev->dev, "promiscuity enabled\n");
605 } else {
6f979eb3 606 /* Don't Flood All Unicast Packets to Host port */
0cd8f9cc
M		 607 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
608
6f979eb3
LS		 609 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
610 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 611 cpsw_ale_control_set(ale, i,
612 ALE_PORT_NOLEARN, 0);
613 cpsw_ale_control_set(ale, i,
614 ALE_PORT_NO_SA_UPDATE, 0);
615 }
616 dev_dbg(&ndev->dev, "promiscuity disabled\n");
617 }
618 }
619}
620
5c50a856
M		 621static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
622{
623 struct cpsw_priv *priv = netdev_priv(ndev);
25906052
M		 624 int vid;
625
626 if (priv->data.dual_emac)
627 vid = priv->slaves[priv->emac_port].port_vlan;
628 else
629 vid = priv->data.default_vlan;
5c50a856
M		 630
631 if (ndev->flags & IFF_PROMISC) {
632 /* Enable promiscuous mode */
0cd8f9cc 633 cpsw_set_promiscious(ndev, true);
1e5c4bc4 634 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
5c50a856 635 return;
0cd8f9cc
M		 636 } else {
637 /* Disable promiscuous mode */
638 cpsw_set_promiscious(ndev, false);
5c50a856
M		 639 }
640
1e5c4bc4
LS		 641 /* Restore allmulti on vlans if necessary */
642 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
643
5c50a856 644 /* Clear all mcast from ALE */
61f1cef9 645 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS, vid);
5c50a856
M		 646
647 if (!netdev_mc_empty(ndev)) {
648 struct netdev_hw_addr *ha;
649
650 /* program multicast address list into ALE register */
651 netdev_for_each_mc_addr(ha, ndev) {
d9ba8f9e 652 cpsw_add_mcast(priv, (u8 *)ha->addr);
5c50a856
M		 653 }
654 }
655}
656
df828598
M		 657static void cpsw_intr_enable(struct cpsw_priv *priv)
658{
5d8d0d4d
IK		 659 struct cpsw_common *cpsw = priv->cpsw;
660
661 __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
662 __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
df828598
M		 663
664 cpdma_ctlr_int_ctrl(priv->dma, true);
665 return;
666}
667
668static void cpsw_intr_disable(struct cpsw_priv *priv)
669{
5d8d0d4d
IK		 670 struct cpsw_common *cpsw = priv->cpsw;
671
672 __raw_writel(0, &cpsw->wr_regs->tx_en);
673 __raw_writel(0, &cpsw->wr_regs->rx_en);
df828598
M		 674
675 cpdma_ctlr_int_ctrl(priv->dma, false);
676 return;
677}
678
1a3b5056 679static void cpsw_tx_handler(void *token, int len, int status)
df828598
M		 680{
681 struct sk_buff *skb = token;
682 struct net_device *ndev = skb->dev;
683 struct cpsw_priv *priv = netdev_priv(ndev);
684
fae50823
M		 685 /* Check whether the queue is stopped due to stalled tx dma, if the
686 * queue is stopped then start the queue as we have free desc for tx
687 */
df828598 688 if (unlikely(netif_queue_stopped(ndev)))
b56d6b3f 689 netif_wake_queue(ndev);
9232b16d 690 cpts_tx_timestamp(priv->cpts, skb);
8dc43ddc
TK		 691 ndev->stats.tx_packets++;
692 ndev->stats.tx_bytes += len;
df828598
M		 693 dev_kfree_skb_any(skb);
694}
695
1a3b5056 696static void cpsw_rx_handler(void *token, int len, int status)
df828598
M		 697{
698 struct sk_buff *skb = token;
b4727e69 699 struct sk_buff *new_skb;
df828598
M		 700 struct net_device *ndev = skb->dev;
701 struct cpsw_priv *priv = netdev_priv(ndev);
702 int ret = 0;
703
d9ba8f9e
M		 704 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
705
16e5c57d 706 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
a0e2c822
M		 707 bool ndev_status = false;
708 struct cpsw_slave *slave = priv->slaves;
709 int n;
710
711 if (priv->data.dual_emac) {
712 /* In dual emac mode check for all interfaces */
713 for (n = priv->data.slaves; n; n--, slave++)
714 if (netif_running(slave->ndev))
715 ndev_status = true;
716 }
717
718 if (ndev_status && (status >= 0)) {
719 /* The packet received is for the interface which
720 * is already down and the other interface is up
dbedd44e 721 * and running, instead of freeing which results
a0e2c822
M		 722 * in reducing of the number of rx descriptor in
723 * DMA engine, requeue skb back to cpdma.
724 */
725 new_skb = skb;
726 goto requeue;
727 }
728
b4727e69 729 /* the interface is going down, skbs are purged */
df828598
M		 730 dev_kfree_skb_any(skb);
731 return;
732 }
b4727e69
SS		 733
734 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
735 if (new_skb) {
df828598 736 skb_put(skb, len);
9232b16d 737 cpts_rx_timestamp(priv->cpts, skb);
df828598
M		 738 skb->protocol = eth_type_trans(skb, ndev);
739 netif_receive_skb(skb);
8dc43ddc
TK		 740 ndev->stats.rx_bytes += len;
741 ndev->stats.rx_packets++;
b4727e69 742 } else {
8dc43ddc 743 ndev->stats.rx_dropped++;
b4727e69 744 new_skb = skb;
df828598
M		 745 }
746
a0e2c822 747requeue:
b4727e69
SS		 748 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
749 skb_tailroom(new_skb), 0);
750 if (WARN_ON(ret < 0))
751 dev_kfree_skb_any(new_skb);
df828598
M		 752}
753
c03abd84 754static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
df828598
M		 755{
756 struct cpsw_priv *priv = dev_id;
5d8d0d4d 757 struct cpsw_common *cpsw = priv->cpsw;
7ce67a38 758
5d8d0d4d 759 writel(0, &cpsw->wr_regs->tx_en);
c03abd84 760 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
c03abd84 761
7da11600
M		 762 if (priv->quirk_irq) {
763 disable_irq_nosync(priv->irqs_table[1]);
764 priv->tx_irq_disabled = true;
765 }
766
32a7432c 767 napi_schedule(&priv->napi_tx);
c03abd84
FB		 768 return IRQ_HANDLED;
769}
770
771static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
772{
773 struct cpsw_priv *priv = dev_id;
5d8d0d4d 774 struct cpsw_common *cpsw = priv->cpsw;
c03abd84
FB		 775
776 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
5d8d0d4d 777 writel(0, &cpsw->wr_regs->rx_en);
fd51cf19 778
7da11600
M		 779 if (priv->quirk_irq) {
780 disable_irq_nosync(priv->irqs_table[0]);
781 priv->rx_irq_disabled = true;
782 }
783
32a7432c 784 napi_schedule(&priv->napi_rx);
d354eb85 785 return IRQ_HANDLED;
df828598
M		 786}
787
32a7432c
M		 788static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
789{
790 struct cpsw_priv *priv = napi_to_priv(napi_tx);
791 int num_tx;
5d8d0d4d 792 struct cpsw_common *cpsw = priv->cpsw;
32a7432c
M		 793
794 num_tx = cpdma_chan_process(priv->txch, budget);
795 if (num_tx < budget) {
796 napi_complete(napi_tx);
5d8d0d4d 797 writel(0xff, &cpsw->wr_regs->tx_en);
7da11600
M		 798 if (priv->quirk_irq && priv->tx_irq_disabled) {
799 priv->tx_irq_disabled = false;
800 enable_irq(priv->irqs_table[1]);
801 }
32a7432c
M		 802 }
803
32a7432c
M		 804 return num_tx;
805}
806
807static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
df828598 808{
32a7432c 809 struct cpsw_priv *priv = napi_to_priv(napi_rx);
1e353cdd 810 int num_rx;
5d8d0d4d 811 struct cpsw_common *cpsw = priv->cpsw;
df828598 812
510a1e72 813 num_rx = cpdma_chan_process(priv->rxch, budget);
df828598 814 if (num_rx < budget) {
32a7432c 815 napi_complete(napi_rx);
5d8d0d4d 816 writel(0xff, &cpsw->wr_regs->rx_en);
7da11600
M		 817 if (priv->quirk_irq && priv->rx_irq_disabled) {
818 priv->rx_irq_disabled = false;
819 enable_irq(priv->irqs_table[0]);
820 }
df828598
M		 821 }
822
823 return num_rx;
824}
825
826static inline void soft_reset(const char *module, void __iomem *reg)
827{
828 unsigned long timeout = jiffies + HZ;
829
830 __raw_writel(1, reg);
831 do {
832 cpu_relax();
833 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
834
835 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
836}
837
838#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
839 ((mac)[2] << 16) | ((mac)[3] << 24))
840#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
841
842static void cpsw_set_slave_mac(struct cpsw_slave *slave,
843 struct cpsw_priv *priv)
844{
9750a3ad
RC		 845 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
846 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 847}
848
849static void _cpsw_adjust_link(struct cpsw_slave *slave,
850 struct cpsw_priv *priv, bool *link)
851{
852 struct phy_device *phy = slave->phy;
853 u32 mac_control = 0;
854 u32 slave_port;
855
856 if (!phy)
857 return;
858
6f1f5836 859 slave_port = cpsw_get_slave_port(slave->slave_num);
df828598
M		 860
861 if (phy->link) {
862 mac_control = priv->data.mac_control;
863
864 /* enable forwarding */
865 cpsw_ale_control_set(priv->ale, slave_port,
866 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
867
868 if (phy->speed == 1000)
869 mac_control |= BIT(7); /* GIGABITEN */
870 if (phy->duplex)
871 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 872
873 /* set speed_in input in case RMII mode is used in 100Mbps */
874 if (phy->speed == 100)
875 mac_control |= BIT(15);
a81d8762
M		 876 else if (phy->speed == 10)
877 mac_control |= BIT(18); /* In Band mode */
342b7b74 878
1923d6e4
M		 879 if (priv->rx_pause)
880 mac_control |= BIT(3);
881
882 if (priv->tx_pause)
883 mac_control |= BIT(4);
884
df828598
M		 885 *link = true;
886 } else {
887 mac_control = 0;
888 /* disable forwarding */
889 cpsw_ale_control_set(priv->ale, slave_port,
890 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
891 }
892
893 if (mac_control != slave->mac_control) {
894 phy_print_status(phy);
895 __raw_writel(mac_control, &slave->sliver->mac_control);
896 }
897
898 slave->mac_control = mac_control;
899}
900
901static void cpsw_adjust_link(struct net_device *ndev)
902{
903 struct cpsw_priv *priv = netdev_priv(ndev);
904 bool link = false;
905
906 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
907
908 if (link) {
909 netif_carrier_on(ndev);
910 if (netif_running(ndev))
911 netif_wake_queue(ndev);
912 } else {
913 netif_carrier_off(ndev);
914 netif_stop_queue(ndev);
915 }
916}
917
ff5b8ef2
M		 918static int cpsw_get_coalesce(struct net_device *ndev,
919 struct ethtool_coalesce *coal)
920{
921 struct cpsw_priv *priv = netdev_priv(ndev);
922
923 coal->rx_coalesce_usecs = priv->coal_intvl;
924 return 0;
925}
926
927static int cpsw_set_coalesce(struct net_device *ndev,
928 struct ethtool_coalesce *coal)
929{
930 struct cpsw_priv *priv = netdev_priv(ndev);
931 u32 int_ctrl;
932 u32 num_interrupts = 0;
933 u32 prescale = 0;
934 u32 addnl_dvdr = 1;
935 u32 coal_intvl = 0;
5d8d0d4d 936 struct cpsw_common *cpsw = priv->cpsw;
ff5b8ef2 937
ff5b8ef2
M		 938 coal_intvl = coal->rx_coalesce_usecs;
939
5d8d0d4d 940 int_ctrl = readl(&cpsw->wr_regs->int_control);
ff5b8ef2
M		 941 prescale = priv->bus_freq_mhz * 4;
942
a84bc2a9
M		 943 if (!coal->rx_coalesce_usecs) {
944 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
945 goto update_return;
946 }
947
ff5b8ef2
M		 948 if (coal_intvl < CPSW_CMINTMIN_INTVL)
949 coal_intvl = CPSW_CMINTMIN_INTVL;
950
951 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
952 /* Interrupt pacer works with 4us Pulse, we can
953 * throttle further by dilating the 4us pulse.
954 */
955 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
956
957 if (addnl_dvdr > 1) {
958 prescale *= addnl_dvdr;
959 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
960 coal_intvl = (CPSW_CMINTMAX_INTVL
961 * addnl_dvdr);
962 } else {
963 addnl_dvdr = 1;
964 coal_intvl = CPSW_CMINTMAX_INTVL;
965 }
966 }
967
968 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
5d8d0d4d
IK		 969 writel(num_interrupts, &cpsw->wr_regs->rx_imax);
970 writel(num_interrupts, &cpsw->wr_regs->tx_imax);
ff5b8ef2
M		 971
972 int_ctrl |= CPSW_INTPACEEN;
973 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
974 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
a84bc2a9
M		 975
976update_return:
5d8d0d4d 977 writel(int_ctrl, &cpsw->wr_regs->int_control);
ff5b8ef2
M		 978
979 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
980 if (priv->data.dual_emac) {
981 int i;
982
983 for (i = 0; i < priv->data.slaves; i++) {
984 priv = netdev_priv(priv->slaves[i].ndev);
985 priv->coal_intvl = coal_intvl;
986 }
987 } else {
988 priv->coal_intvl = coal_intvl;
989 }
990
991 return 0;
992}
993
d9718546
M		 994static int cpsw_get_sset_count(struct net_device *ndev, int sset)
995{
996 switch (sset) {
997 case ETH_SS_STATS:
998 return CPSW_STATS_LEN;
999 default:
1000 return -EOPNOTSUPP;
1001 }
1002}
1003
1004static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1005{
1006 u8 *p = data;
1007 int i;
1008
1009 switch (stringset) {
1010 case ETH_SS_STATS:
1011 for (i = 0; i < CPSW_STATS_LEN; i++) {
1012 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1013 ETH_GSTRING_LEN);
1014 p += ETH_GSTRING_LEN;
1015 }
1016 break;
1017 }
1018}
1019
1020static void cpsw_get_ethtool_stats(struct net_device *ndev,
1021 struct ethtool_stats *stats, u64 *data)
1022{
1023 struct cpsw_priv *priv = netdev_priv(ndev);
1024 struct cpdma_chan_stats rx_stats;
1025 struct cpdma_chan_stats tx_stats;
1026 u32 val;
1027 u8 *p;
1028 int i;
5d8d0d4d 1029 struct cpsw_common *cpsw = priv->cpsw;
d9718546
M		 1030
1031 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1032 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1033 cpdma_chan_get_stats(priv->txch, &tx_stats);
1034
1035 for (i = 0; i < CPSW_STATS_LEN; i++) {
1036 switch (cpsw_gstrings_stats[i].type) {
1037 case CPSW_STATS:
5d8d0d4d 1038 val = readl(cpsw->hw_stats +
d9718546
M		 1039 cpsw_gstrings_stats[i].stat_offset);
1040 data[i] = val;
1041 break;
1042
1043 case CPDMA_RX_STATS:
1044 p = (u8 *)&rx_stats +
1045 cpsw_gstrings_stats[i].stat_offset;
1046 data[i] = *(u32 *)p;
1047 break;
1048
1049 case CPDMA_TX_STATS:
1050 p = (u8 *)&tx_stats +
1051 cpsw_gstrings_stats[i].stat_offset;
1052 data[i] = *(u32 *)p;
1053 break;
1054 }
1055 }
1056}
1057
d9ba8f9e
M		 1058static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1059{
1060 u32 i;
1061 u32 usage_count = 0;
1062
1063 if (!priv->data.dual_emac)
1064 return 0;
1065
1066 for (i = 0; i < priv->data.slaves; i++)
1067 if (priv->slaves[i].open_stat)
1068 usage_count++;
1069
1070 return usage_count;
1071}
1072
27e9e103
IK		 1073static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1074 struct sk_buff *skb)
d9ba8f9e 1075{
27e9e103
IK		 1076 return cpdma_chan_submit(priv->txch, skb, skb->data, skb->len,
1077 priv->emac_port + priv->data.dual_emac);
d9ba8f9e
M		 1078}
1079
1080static inline void cpsw_add_dual_emac_def_ale_entries(
1081 struct cpsw_priv *priv, struct cpsw_slave *slave,
1082 u32 slave_port)
1083{
71a2cbb7 1084 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
d9ba8f9e
M		 1085
1086 if (priv->version == CPSW_VERSION_1)
1087 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1088 else
1089 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1090 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1091 port_mask, port_mask, 0);
1092 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1093 port_mask, ALE_VLAN, slave->port_vlan, 0);
1094 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
71a2cbb7 1095 HOST_PORT_NUM, ALE_VLAN | ALE_SECURE, slave->port_vlan);
d9ba8f9e
M		 1096}
1097
1e7a2e21 1098static void soft_reset_slave(struct cpsw_slave *slave)
df828598
M		 1099{
1100 char name[32];
df828598 1101
1e7a2e21 1102 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
df828598 1103 soft_reset(name, &slave->sliver->soft_reset);
1e7a2e21
DM		 1104}
1105
1106static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1107{
1108 u32 slave_port;
649a1688 1109 struct cpsw_common *cpsw = priv->cpsw;
1e7a2e21
DM		 1110
1111 soft_reset_slave(slave);
df828598
M		 1112
1113 /* setup priority mapping */
1114 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad
RC		 1115
1116 switch (priv->version) {
1117 case CPSW_VERSION_1:
1118 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1119 break;
1120 case CPSW_VERSION_2:
c193f365 1121 case CPSW_VERSION_3:
926489be 1122 case CPSW_VERSION_4:
9750a3ad
RC		 1123 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1124 break;
1125 }
df828598
M		 1126
1127 /* setup max packet size, and mac address */
1128 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1129 cpsw_set_slave_mac(slave, priv);
1130
1131 slave->mac_control = 0; /* no link yet */
1132
6f1f5836 1133 slave_port = cpsw_get_slave_port(slave->slave_num);
df828598 1134
d9ba8f9e
M		 1135 if (priv->data.dual_emac)
1136 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1137 else
1138 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1139 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
df828598 1140
d733f754 1141 if (slave->data->phy_node) {
552165bc 1142 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
9e42f715 1143 &cpsw_adjust_link, 0, slave->data->phy_if);
d733f754
DR		 1144 if (!slave->phy) {
1145 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1146 slave->data->phy_node->full_name,
1147 slave->slave_num);
1148 return;
1149 }
1150 } else {
9e42f715 1151 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
f9a8f83b 1152 &cpsw_adjust_link, slave->data->phy_if);
d733f754
DR		 1153 if (IS_ERR(slave->phy)) {
1154 dev_err(priv->dev,
1155 "phy \"%s\" not found on slave %d, err %ld\n",
1156 slave->data->phy_id, slave->slave_num,
1157 PTR_ERR(slave->phy));
1158 slave->phy = NULL;
1159 return;
1160 }
1161 }
2220943a 1162
d733f754 1163 phy_attached_info(slave->phy);
388367a5 1164
d733f754
DR		 1165 phy_start(slave->phy);
1166
1167 /* Configure GMII_SEL register */
56e31bd8 1168 cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
df828598
M		 1169}
1170
3b72c2fe
M		 1171static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1172{
1173 const int vlan = priv->data.default_vlan;
3b72c2fe
M		 1174 u32 reg;
1175 int i;
1e5c4bc4 1176 int unreg_mcast_mask;
5d8d0d4d 1177 struct cpsw_common *cpsw = priv->cpsw;
3b72c2fe
M		 1178
1179 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1180 CPSW2_PORT_VLAN;
1181
5d8d0d4d 1182 writel(vlan, &cpsw->host_port_regs->port_vlan);
3b72c2fe 1183
0237c110 1184 for (i = 0; i < priv->data.slaves; i++)
3b72c2fe
M		 1185 slave_write(priv->slaves + i, vlan, reg);
1186
1e5c4bc4
LS		 1187 if (priv->ndev->flags & IFF_ALLMULTI)
1188 unreg_mcast_mask = ALE_ALL_PORTS;
1189 else
1190 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1191
61f1cef9
GS		 1192 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS,
1193 ALE_ALL_PORTS, ALE_ALL_PORTS,
1194 unreg_mcast_mask);
3b72c2fe
M		 1195}
1196
df828598
M		 1197static void cpsw_init_host_port(struct cpsw_priv *priv)
1198{
d9ba8f9e 1199 u32 fifo_mode;
5d8d0d4d
IK		 1200 u32 control_reg;
1201 struct cpsw_common *cpsw = priv->cpsw;
3b72c2fe 1202
df828598 1203 /* soft reset the controller and initialize ale */
5d8d0d4d 1204 soft_reset("cpsw", &cpsw->regs->soft_reset);
df828598
M		 1205 cpsw_ale_start(priv->ale);
1206
1207 /* switch to vlan unaware mode */
71a2cbb7 1208 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
3b72c2fe 1209 CPSW_ALE_VLAN_AWARE);
5d8d0d4d 1210 control_reg = readl(&cpsw->regs->control);
3b72c2fe 1211 control_reg |= CPSW_VLAN_AWARE;
5d8d0d4d 1212 writel(control_reg, &cpsw->regs->control);
d9ba8f9e
M		 1213 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1214 CPSW_FIFO_NORMAL_MODE;
5d8d0d4d 1215 writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
df828598
M		 1216
1217 /* setup host port priority mapping */
1218 __raw_writel(CPDMA_TX_PRIORITY_MAP,
5d8d0d4d
IK		 1219 &cpsw->host_port_regs->cpdma_tx_pri_map);
1220 __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
df828598 1221
71a2cbb7 1222 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM,
df828598
M		 1223 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1224
d9ba8f9e 1225 if (!priv->data.dual_emac) {
71a2cbb7 1226 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
d9ba8f9e
M		 1227 0, 0);
1228 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
71a2cbb7 1229 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
d9ba8f9e 1230 }
df828598
M		 1231}
1232
aacebbf8
SS		 1233static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1234{
3995d265
SP		 1235 u32 slave_port;
1236
6f1f5836 1237 slave_port = cpsw_get_slave_port(slave->slave_num);
3995d265 1238
aacebbf8
SS		 1239 if (!slave->phy)
1240 return;
1241 phy_stop(slave->phy);
1242 phy_disconnect(slave->phy);
1243 slave->phy = NULL;
3995d265
SP		 1244 cpsw_ale_control_set(priv->ale, slave_port,
1245 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1f95ba00 1246 soft_reset_slave(slave);
aacebbf8
SS		 1247}
1248
df828598
M		 1249static int cpsw_ndo_open(struct net_device *ndev)
1250{
1251 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1252 struct cpsw_common *cpsw = priv->cpsw;
df828598
M		 1253 int i, ret;
1254 u32 reg;
1255
56e31bd8 1256 ret = pm_runtime_get_sync(cpsw->dev);
108a6537 1257 if (ret < 0) {
56e31bd8 1258 pm_runtime_put_noidle(cpsw->dev);
108a6537
GS		 1259 return ret;
1260 }
3fa88c51 1261
d9ba8f9e
M		 1262 if (!cpsw_common_res_usage_state(priv))
1263 cpsw_intr_disable(priv);
df828598
M		 1264 netif_carrier_off(ndev);
1265
549985ee 1266 reg = priv->version;
df828598
M		 1267
1268 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1269 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1270 CPSW_RTL_VERSION(reg));
1271
1272 /* initialize host and slave ports */
d9ba8f9e
M		 1273 if (!cpsw_common_res_usage_state(priv))
1274 cpsw_init_host_port(priv);
df828598
M		 1275 for_each_slave(priv, cpsw_slave_open, priv);
1276
3b72c2fe 1277 /* Add default VLAN */
e6afea0b
M		 1278 if (!priv->data.dual_emac)
1279 cpsw_add_default_vlan(priv);
1280 else
1281 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
61f1cef9 1282 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
3b72c2fe 1283
d9ba8f9e 1284 if (!cpsw_common_res_usage_state(priv)) {
d354eb85 1285 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1793331e 1286 int buf_num;
d354eb85 1287
d9ba8f9e
M		 1288 /* setup tx dma to fixed prio and zero offset */
1289 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1290 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
df828598 1291
d9ba8f9e 1292 /* disable priority elevation */
5d8d0d4d 1293 __raw_writel(0, &cpsw->regs->ptype);
df828598 1294
d9ba8f9e 1295 /* enable statistics collection only on all ports */
5d8d0d4d 1296 __raw_writel(0x7, &cpsw->regs->stat_port_en);
df828598 1297
1923d6e4 1298 /* Enable internal fifo flow control */
5d8d0d4d 1299 writel(0x7, &cpsw->regs->flow_control);
1923d6e4 1300
32a7432c
M		 1301 napi_enable(&priv_sl0->napi_rx);
1302 napi_enable(&priv_sl0->napi_tx);
d354eb85 1303
7da11600
M		 1304 if (priv_sl0->tx_irq_disabled) {
1305 priv_sl0->tx_irq_disabled = false;
1306 enable_irq(priv->irqs_table[1]);
1307 }
1308
1309 if (priv_sl0->rx_irq_disabled) {
1310 priv_sl0->rx_irq_disabled = false;
1311 enable_irq(priv->irqs_table[0]);
1312 }
1313
1793331e
IK		 1314 buf_num = cpdma_chan_get_rx_buf_num(priv->dma);
1315 for (i = 0; i < buf_num; i++) {
d9ba8f9e 1316 struct sk_buff *skb;
df828598 1317
d9ba8f9e 1318 ret = -ENOMEM;
aacebbf8
SS		 1319 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1320 priv->rx_packet_max, GFP_KERNEL);
d9ba8f9e 1321 if (!skb)
aacebbf8 1322 goto err_cleanup;
d9ba8f9e 1323 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
aef614e1 1324 skb_tailroom(skb), 0);
aacebbf8
SS		 1325 if (ret < 0) {
1326 kfree_skb(skb);
1327 goto err_cleanup;
1328 }
d9ba8f9e
M		 1329 }
1330 /* continue even if we didn't manage to submit all
1331 * receive descs
1332 */
1333 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
f280e89a 1334
56e31bd8 1335 if (cpts_register(cpsw->dev, priv->cpts,
f280e89a
M		 1336 priv->data.cpts_clock_mult,
1337 priv->data.cpts_clock_shift))
1338 dev_err(priv->dev, "error registering cpts device\n");
1339
df828598 1340 }
df828598 1341
ff5b8ef2
M		 1342 /* Enable Interrupt pacing if configured */
1343 if (priv->coal_intvl != 0) {
1344 struct ethtool_coalesce coal;
1345
8478b6cd 1346 coal.rx_coalesce_usecs = priv->coal_intvl;
ff5b8ef2
M		 1347 cpsw_set_coalesce(ndev, &coal);
1348 }
1349
f63a975e
M		 1350 cpdma_ctlr_start(priv->dma);
1351 cpsw_intr_enable(priv);
f63a975e 1352
d9ba8f9e
M		 1353 if (priv->data.dual_emac)
1354 priv->slaves[priv->emac_port].open_stat = true;
df828598 1355 return 0;
df828598 1356
aacebbf8
SS		 1357err_cleanup:
1358 cpdma_ctlr_stop(priv->dma);
1359 for_each_slave(priv, cpsw_slave_stop, priv);
56e31bd8 1360 pm_runtime_put_sync(cpsw->dev);
aacebbf8
SS		 1361 netif_carrier_off(priv->ndev);
1362 return ret;
df828598
M		 1363}
1364
1365static int cpsw_ndo_stop(struct net_device *ndev)
1366{
1367 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1368 struct cpsw_common *cpsw = priv->cpsw;
df828598
M		 1369
1370 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
df828598 1371 netif_stop_queue(priv->ndev);
df828598 1372 netif_carrier_off(priv->ndev);
d9ba8f9e
M		 1373
1374 if (cpsw_common_res_usage_state(priv) <= 1) {
d354eb85
M		 1375 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1376
32a7432c
M		 1377 napi_disable(&priv_sl0->napi_rx);
1378 napi_disable(&priv_sl0->napi_tx);
f280e89a 1379 cpts_unregister(priv->cpts);
d9ba8f9e 1380 cpsw_intr_disable(priv);
d9ba8f9e
M		 1381 cpdma_ctlr_stop(priv->dma);
1382 cpsw_ale_stop(priv->ale);
1383 }
df828598 1384 for_each_slave(priv, cpsw_slave_stop, priv);
56e31bd8 1385 pm_runtime_put_sync(cpsw->dev);
d9ba8f9e
M		 1386 if (priv->data.dual_emac)
1387 priv->slaves[priv->emac_port].open_stat = false;
df828598
M		 1388 return 0;
1389}
1390
1391static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1392 struct net_device *ndev)
1393{
1394 struct cpsw_priv *priv = netdev_priv(ndev);
1395 int ret;
1396
860e9538 1397 netif_trans_update(ndev);
df828598
M		 1398
1399 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1400 cpsw_err(priv, tx_err, "packet pad failed\n");
8dc43ddc 1401 ndev->stats.tx_dropped++;
df828598
M		 1402 return NETDEV_TX_OK;
1403 }
1404
9232b16d
M		 1405 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1406 priv->cpts->tx_enable)
2e5b38ab
RC		 1407 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1408
1409 skb_tx_timestamp(skb);
1410
27e9e103 1411 ret = cpsw_tx_packet_submit(priv, skb);
df828598
M		 1412 if (unlikely(ret != 0)) {
1413 cpsw_err(priv, tx_err, "desc submit failed\n");
1414 goto fail;
1415 }
1416
fae50823
M		 1417 /* If there is no more tx desc left free then we need to
1418 * tell the kernel to stop sending us tx frames.
1419 */
d35162f8 1420 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
fae50823
M		 1421 netif_stop_queue(ndev);
1422
df828598
M		 1423 return NETDEV_TX_OK;
1424fail:
8dc43ddc 1425 ndev->stats.tx_dropped++;
df828598
M		 1426 netif_stop_queue(ndev);
1427 return NETDEV_TX_BUSY;
1428}
1429
2e5b38ab
RC		 1430#ifdef CONFIG_TI_CPTS
1431
1432static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1433{
e86ac13b 1434 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
2e5b38ab
RC		 1435 u32 ts_en, seq_id;
1436
9232b16d 1437 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
2e5b38ab
RC		 1438 slave_write(slave, 0, CPSW1_TS_CTL);
1439 return;
1440 }
1441
1442 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1443 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1444
9232b16d 1445 if (priv->cpts->tx_enable)
2e5b38ab
RC		 1446 ts_en |= CPSW_V1_TS_TX_EN;
1447
9232b16d 1448 if (priv->cpts->rx_enable)
2e5b38ab
RC		 1449 ts_en |= CPSW_V1_TS_RX_EN;
1450
1451 slave_write(slave, ts_en, CPSW1_TS_CTL);
1452 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1453}
1454
1455static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1456{
d9ba8f9e 1457 struct cpsw_slave *slave;
5d8d0d4d 1458 struct cpsw_common *cpsw = priv->cpsw;
2e5b38ab
RC		 1459 u32 ctrl, mtype;
1460
d9ba8f9e
M		 1461 if (priv->data.dual_emac)
1462 slave = &priv->slaves[priv->emac_port];
1463 else
e86ac13b 1464 slave = &priv->slaves[priv->data.active_slave];
d9ba8f9e 1465
2e5b38ab 1466 ctrl = slave_read(slave, CPSW2_CONTROL);
09c55372
GC		 1467 switch (priv->version) {
1468 case CPSW_VERSION_2:
1469 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2e5b38ab 1470
09c55372
GC		 1471 if (priv->cpts->tx_enable)
1472 ctrl |= CTRL_V2_TX_TS_BITS;
2e5b38ab 1473
09c55372
GC		 1474 if (priv->cpts->rx_enable)
1475 ctrl |= CTRL_V2_RX_TS_BITS;
26fe7eb8 1476 break;
09c55372
GC		 1477 case CPSW_VERSION_3:
1478 default:
1479 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1480
1481 if (priv->cpts->tx_enable)
1482 ctrl |= CTRL_V3_TX_TS_BITS;
1483
1484 if (priv->cpts->rx_enable)
1485 ctrl |= CTRL_V3_RX_TS_BITS;
26fe7eb8 1486 break;
09c55372 1487 }
2e5b38ab
RC		 1488
1489 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1490
1491 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1492 slave_write(slave, ctrl, CPSW2_CONTROL);
5d8d0d4d 1493 __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
2e5b38ab
RC		 1494}
1495
a5b4145b 1496static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2e5b38ab 1497{
3177bf6f 1498 struct cpsw_priv *priv = netdev_priv(dev);
9232b16d 1499 struct cpts *cpts = priv->cpts;
2e5b38ab
RC		 1500 struct hwtstamp_config cfg;
1501
2ee91e54 1502 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1503 priv->version != CPSW_VERSION_2 &&
1504 priv->version != CPSW_VERSION_3)
2ee91e54
BH		 1505 return -EOPNOTSUPP;
1506
2e5b38ab
RC		 1507 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1508 return -EFAULT;
1509
1510 /* reserved for future extensions */
1511 if (cfg.flags)
1512 return -EINVAL;
1513
2ee91e54 1514 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2e5b38ab 1515 return -ERANGE;
2e5b38ab
RC		 1516
1517 switch (cfg.rx_filter) {
1518 case HWTSTAMP_FILTER_NONE:
1519 cpts->rx_enable = 0;
1520 break;
1521 case HWTSTAMP_FILTER_ALL:
1522 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1523 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1524 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1525 return -ERANGE;
1526 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1527 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1528 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1529 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1530 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1531 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1532 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1533 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1534 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1535 cpts->rx_enable = 1;
1536 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1537 break;
1538 default:
1539 return -ERANGE;
1540 }
1541
2ee91e54
BH		 1542 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1543
2e5b38ab
RC		 1544 switch (priv->version) {
1545 case CPSW_VERSION_1:
1546 cpsw_hwtstamp_v1(priv);
1547 break;
1548 case CPSW_VERSION_2:
f7d403cb 1549 case CPSW_VERSION_3:
2e5b38ab
RC		 1550 cpsw_hwtstamp_v2(priv);
1551 break;
1552 default:
2ee91e54 1553 WARN_ON(1);
2e5b38ab
RC		 1554 }
1555
1556 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1557}
1558
a5b4145b
BH		 1559static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1560{
1561 struct cpsw_priv *priv = netdev_priv(dev);
1562 struct cpts *cpts = priv->cpts;
1563 struct hwtstamp_config cfg;
1564
1565 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1566 priv->version != CPSW_VERSION_2 &&
1567 priv->version != CPSW_VERSION_3)
a5b4145b
BH		 1568 return -EOPNOTSUPP;
1569
1570 cfg.flags = 0;
1571 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1572 cfg.rx_filter = (cpts->rx_enable ?
1573 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1574
1575 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1576}
1577
2e5b38ab
RC		 1578#endif /*CONFIG_TI_CPTS*/
1579
1580static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1581{
11f2c988 1582 struct cpsw_priv *priv = netdev_priv(dev);
11f2c988
M		 1583 int slave_no = cpsw_slave_index(priv);
1584
2e5b38ab
RC		 1585 if (!netif_running(dev))
1586 return -EINVAL;
1587
11f2c988 1588 switch (cmd) {
2e5b38ab 1589#ifdef CONFIG_TI_CPTS
11f2c988 1590 case SIOCSHWTSTAMP:
a5b4145b
BH		 1591 return cpsw_hwtstamp_set(dev, req);
1592 case SIOCGHWTSTAMP:
1593 return cpsw_hwtstamp_get(dev, req);
2e5b38ab 1594#endif
11f2c988
M		 1595 }
1596
c1b59947
SS		 1597 if (!priv->slaves[slave_no].phy)
1598 return -EOPNOTSUPP;
1599 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
2e5b38ab
RC		 1600}
1601
df828598
M		 1602static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1603{
1604 struct cpsw_priv *priv = netdev_priv(ndev);
1605
1606 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
8dc43ddc 1607 ndev->stats.tx_errors++;
df828598 1608 cpsw_intr_disable(priv);
df828598
M		 1609 cpdma_chan_stop(priv->txch);
1610 cpdma_chan_start(priv->txch);
df828598 1611 cpsw_intr_enable(priv);
df828598
M		 1612}
1613
dcfd8d58
M		 1614static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1615{
1616 struct cpsw_priv *priv = netdev_priv(ndev);
1617 struct sockaddr *addr = (struct sockaddr *)p;
649a1688 1618 struct cpsw_common *cpsw = priv->cpsw;
dcfd8d58
M		 1619 int flags = 0;
1620 u16 vid = 0;
a6c5d14f 1621 int ret;
dcfd8d58
M		 1622
1623 if (!is_valid_ether_addr(addr->sa_data))
1624 return -EADDRNOTAVAIL;
1625
56e31bd8 1626 ret = pm_runtime_get_sync(cpsw->dev);
a6c5d14f 1627 if (ret < 0) {
56e31bd8 1628 pm_runtime_put_noidle(cpsw->dev);
a6c5d14f
GS		 1629 return ret;
1630 }
1631
dcfd8d58
M		 1632 if (priv->data.dual_emac) {
1633 vid = priv->slaves[priv->emac_port].port_vlan;
1634 flags = ALE_VLAN;
1635 }
1636
71a2cbb7 1637 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
dcfd8d58 1638 flags, vid);
71a2cbb7 1639 cpsw_ale_add_ucast(priv->ale, addr->sa_data, HOST_PORT_NUM,
dcfd8d58
M		 1640 flags, vid);
1641
1642 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1643 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1644 for_each_slave(priv, cpsw_set_slave_mac, priv);
1645
56e31bd8 1646 pm_runtime_put(cpsw->dev);
a6c5d14f 1647
dcfd8d58
M		 1648 return 0;
1649}
1650
df828598
M		 1651#ifdef CONFIG_NET_POLL_CONTROLLER
1652static void cpsw_ndo_poll_controller(struct net_device *ndev)
1653{
1654 struct cpsw_priv *priv = netdev_priv(ndev);
1655
1656 cpsw_intr_disable(priv);
92cb13fb
FB		 1657 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1658 cpsw_tx_interrupt(priv->irqs_table[1], priv);
df828598 1659 cpsw_intr_enable(priv);
df828598
M		 1660}
1661#endif
1662
3b72c2fe
M		 1663static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1664 unsigned short vid)
1665{
1666 int ret;
9f6bd8fa
M		 1667 int unreg_mcast_mask = 0;
1668 u32 port_mask;
1e5c4bc4 1669
9f6bd8fa
M		 1670 if (priv->data.dual_emac) {
1671 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
3b72c2fe 1672
9f6bd8fa
M		 1673 if (priv->ndev->flags & IFF_ALLMULTI)
1674 unreg_mcast_mask = port_mask;
1675 } else {
1676 port_mask = ALE_ALL_PORTS;
1677
1678 if (priv->ndev->flags & IFF_ALLMULTI)
1679 unreg_mcast_mask = ALE_ALL_PORTS;
1680 else
1681 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1682 }
3b72c2fe 1683
9f6bd8fa 1684 ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
61f1cef9 1685 unreg_mcast_mask);
3b72c2fe
M		 1686 if (ret != 0)
1687 return ret;
1688
1689 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
71a2cbb7 1690 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1691 if (ret != 0)
1692 goto clean_vid;
1693
1694 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
9f6bd8fa 1695 port_mask, ALE_VLAN, vid, 0);
3b72c2fe
M		 1696 if (ret != 0)
1697 goto clean_vlan_ucast;
1698 return 0;
1699
1700clean_vlan_ucast:
1701 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
71a2cbb7 1702 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1703clean_vid:
1704 cpsw_ale_del_vlan(priv->ale, vid, 0);
1705 return ret;
1706}
1707
1708static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
80d5c368 1709 __be16 proto, u16 vid)
3b72c2fe
M		 1710{
1711 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1712 struct cpsw_common *cpsw = priv->cpsw;
a6c5d14f 1713 int ret;
3b72c2fe
M		 1714
1715 if (vid == priv->data.default_vlan)
1716 return 0;
1717
56e31bd8 1718 ret = pm_runtime_get_sync(cpsw->dev);
a6c5d14f 1719 if (ret < 0) {
56e31bd8 1720 pm_runtime_put_noidle(cpsw->dev);
a6c5d14f
GS		 1721 return ret;
1722 }
1723
02a54164
M		 1724 if (priv->data.dual_emac) {
1725 /* In dual EMAC, reserved VLAN id should not be used for
1726 * creating VLAN interfaces as this can break the dual
1727 * EMAC port separation
1728 */
1729 int i;
1730
1731 for (i = 0; i < priv->data.slaves; i++) {
1732 if (vid == priv->slaves[i].port_vlan)
1733 return -EINVAL;
1734 }
1735 }
1736
3b72c2fe 1737 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
a6c5d14f
GS		 1738 ret = cpsw_add_vlan_ale_entry(priv, vid);
1739
56e31bd8 1740 pm_runtime_put(cpsw->dev);
a6c5d14f 1741 return ret;
3b72c2fe
M		 1742}
1743
1744static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
80d5c368 1745 __be16 proto, u16 vid)
3b72c2fe
M		 1746{
1747 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1748 struct cpsw_common *cpsw = priv->cpsw;
3b72c2fe
M		 1749 int ret;
1750
1751 if (vid == priv->data.default_vlan)
1752 return 0;
1753
56e31bd8 1754 ret = pm_runtime_get_sync(cpsw->dev);
a6c5d14f 1755 if (ret < 0) {
56e31bd8 1756 pm_runtime_put_noidle(cpsw->dev);
a6c5d14f
GS		 1757 return ret;
1758 }
1759
02a54164
M		 1760 if (priv->data.dual_emac) {
1761 int i;
1762
1763 for (i = 0; i < priv->data.slaves; i++) {
1764 if (vid == priv->slaves[i].port_vlan)
1765 return -EINVAL;
1766 }
1767 }
1768
3b72c2fe
M		 1769 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1770 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1771 if (ret != 0)
1772 return ret;
1773
1774 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
61f1cef9 1775 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1776 if (ret != 0)
1777 return ret;
1778
a6c5d14f
GS		 1779 ret = cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1780 0, ALE_VLAN, vid);
56e31bd8 1781 pm_runtime_put(cpsw->dev);
a6c5d14f 1782 return ret;
3b72c2fe
M		 1783}
1784
df828598
M		 1785static const struct net_device_ops cpsw_netdev_ops = {
1786 .ndo_open = cpsw_ndo_open,
1787 .ndo_stop = cpsw_ndo_stop,
1788 .ndo_start_xmit = cpsw_ndo_start_xmit,
dcfd8d58 1789 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2e5b38ab 1790 .ndo_do_ioctl = cpsw_ndo_ioctl,
df828598 1791 .ndo_validate_addr = eth_validate_addr,
5c473ed2 1792 .ndo_change_mtu = eth_change_mtu,
df828598 1793 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
5c50a856 1794 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
df828598
M		 1795#ifdef CONFIG_NET_POLL_CONTROLLER
1796 .ndo_poll_controller = cpsw_ndo_poll_controller,
1797#endif
3b72c2fe
M		 1798 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1799 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
df828598
M		 1800};
1801
52c4f0ec
M		 1802static int cpsw_get_regs_len(struct net_device *ndev)
1803{
1804 struct cpsw_priv *priv = netdev_priv(ndev);
1805
1806 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1807}
1808
1809static void cpsw_get_regs(struct net_device *ndev,
1810 struct ethtool_regs *regs, void *p)
1811{
1812 struct cpsw_priv *priv = netdev_priv(ndev);
1813 u32 *reg = p;
1814
1815 /* update CPSW IP version */
1816 regs->version = priv->version;
1817
1818 cpsw_ale_dump(priv->ale, reg);
1819}
1820
df828598
M		 1821static void cpsw_get_drvinfo(struct net_device *ndev,
1822 struct ethtool_drvinfo *info)
1823{
649a1688 1824 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
56e31bd8 1825 struct platform_device *pdev = to_platform_device(cpsw->dev);
7826d43f 1826
52c4f0ec 1827 strlcpy(info->driver, "cpsw", sizeof(info->driver));
7826d43f 1828 strlcpy(info->version, "1.0", sizeof(info->version));
56e31bd8 1829 strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
df828598
M		 1830}
1831
1832static u32 cpsw_get_msglevel(struct net_device *ndev)
1833{
1834 struct cpsw_priv *priv = netdev_priv(ndev);
1835 return priv->msg_enable;
1836}
1837
1838static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1839{
1840 struct cpsw_priv *priv = netdev_priv(ndev);
1841 priv->msg_enable = value;
1842}
1843
2e5b38ab
RC		 1844static int cpsw_get_ts_info(struct net_device *ndev,
1845 struct ethtool_ts_info *info)
1846{
1847#ifdef CONFIG_TI_CPTS
1848 struct cpsw_priv *priv = netdev_priv(ndev);
1849
1850 info->so_timestamping =
1851 SOF_TIMESTAMPING_TX_HARDWARE |
1852 SOF_TIMESTAMPING_TX_SOFTWARE |
1853 SOF_TIMESTAMPING_RX_HARDWARE |
1854 SOF_TIMESTAMPING_RX_SOFTWARE |
1855 SOF_TIMESTAMPING_SOFTWARE |
1856 SOF_TIMESTAMPING_RAW_HARDWARE;
9232b16d 1857 info->phc_index = priv->cpts->phc_index;
2e5b38ab
RC		 1858 info->tx_types =
1859 (1 << HWTSTAMP_TX_OFF) |
1860 (1 << HWTSTAMP_TX_ON);
1861 info->rx_filters =
1862 (1 << HWTSTAMP_FILTER_NONE) |
1863 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1864#else
1865 info->so_timestamping =
1866 SOF_TIMESTAMPING_TX_SOFTWARE |
1867 SOF_TIMESTAMPING_RX_SOFTWARE |
1868 SOF_TIMESTAMPING_SOFTWARE;
1869 info->phc_index = -1;
1870 info->tx_types = 0;
1871 info->rx_filters = 0;
1872#endif
1873 return 0;
1874}
1875
d3bb9c58
M		 1876static int cpsw_get_settings(struct net_device *ndev,
1877 struct ethtool_cmd *ecmd)
1878{
1879 struct cpsw_priv *priv = netdev_priv(ndev);
1880 int slave_no = cpsw_slave_index(priv);
1881
1882 if (priv->slaves[slave_no].phy)
1883 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1884 else
1885 return -EOPNOTSUPP;
1886}
1887
1888static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1889{
1890 struct cpsw_priv *priv = netdev_priv(ndev);
1891 int slave_no = cpsw_slave_index(priv);
1892
1893 if (priv->slaves[slave_no].phy)
1894 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1895 else
1896 return -EOPNOTSUPP;
1897}
1898
d8a64420
MU		 1899static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1900{
1901 struct cpsw_priv *priv = netdev_priv(ndev);
1902 int slave_no = cpsw_slave_index(priv);
1903
1904 wol->supported = 0;
1905 wol->wolopts = 0;
1906
1907 if (priv->slaves[slave_no].phy)
1908 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1909}
1910
1911static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1912{
1913 struct cpsw_priv *priv = netdev_priv(ndev);
1914 int slave_no = cpsw_slave_index(priv);
1915
1916 if (priv->slaves[slave_no].phy)
1917 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1918 else
1919 return -EOPNOTSUPP;
1920}
1921
1923d6e4
M		 1922static void cpsw_get_pauseparam(struct net_device *ndev,
1923 struct ethtool_pauseparam *pause)
1924{
1925 struct cpsw_priv *priv = netdev_priv(ndev);
1926
1927 pause->autoneg = AUTONEG_DISABLE;
1928 pause->rx_pause = priv->rx_pause ? true : false;
1929 pause->tx_pause = priv->tx_pause ? true : false;
1930}
1931
1932static int cpsw_set_pauseparam(struct net_device *ndev,
1933 struct ethtool_pauseparam *pause)
1934{
1935 struct cpsw_priv *priv = netdev_priv(ndev);
1936 bool link;
1937
1938 priv->rx_pause = pause->rx_pause ? true : false;
1939 priv->tx_pause = pause->tx_pause ? true : false;
1940
1941 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1923d6e4
M		 1942 return 0;
1943}
1944
7898b1da
GS		 1945static int cpsw_ethtool_op_begin(struct net_device *ndev)
1946{
1947 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1948 struct cpsw_common *cpsw = priv->cpsw;
7898b1da
GS		 1949 int ret;
1950
56e31bd8 1951 ret = pm_runtime_get_sync(cpsw->dev);
7898b1da
GS		 1952 if (ret < 0) {
1953 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
56e31bd8 1954 pm_runtime_put_noidle(cpsw->dev);
7898b1da
GS		 1955 }
1956
1957 return ret;
1958}
1959
1960static void cpsw_ethtool_op_complete(struct net_device *ndev)
1961{
1962 struct cpsw_priv *priv = netdev_priv(ndev);
1963 int ret;
1964
56e31bd8 1965 ret = pm_runtime_put(priv->cpsw->dev);
7898b1da
GS		 1966 if (ret < 0)
1967 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
1968}
1969
df828598
M		 1970static const struct ethtool_ops cpsw_ethtool_ops = {
1971 .get_drvinfo = cpsw_get_drvinfo,
1972 .get_msglevel = cpsw_get_msglevel,
1973 .set_msglevel = cpsw_set_msglevel,
1974 .get_link = ethtool_op_get_link,
2e5b38ab 1975 .get_ts_info = cpsw_get_ts_info,
d3bb9c58
M		 1976 .get_settings = cpsw_get_settings,
1977 .set_settings = cpsw_set_settings,
ff5b8ef2
M		 1978 .get_coalesce = cpsw_get_coalesce,
1979 .set_coalesce = cpsw_set_coalesce,
d9718546
M		 1980 .get_sset_count = cpsw_get_sset_count,
1981 .get_strings = cpsw_get_strings,
1982 .get_ethtool_stats = cpsw_get_ethtool_stats,
1923d6e4
M		 1983 .get_pauseparam = cpsw_get_pauseparam,
1984 .set_pauseparam = cpsw_set_pauseparam,
d8a64420
MU		 1985 .get_wol = cpsw_get_wol,
1986 .set_wol = cpsw_set_wol,
52c4f0ec
M		 1987 .get_regs_len = cpsw_get_regs_len,
1988 .get_regs = cpsw_get_regs,
7898b1da
GS		 1989 .begin = cpsw_ethtool_op_begin,
1990 .complete = cpsw_ethtool_op_complete,
df828598
M		 1991};
1992
549985ee
RC		 1993static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1994 u32 slave_reg_ofs, u32 sliver_reg_ofs)
df828598 1995{
5d8d0d4d
IK		 1996 struct cpsw_common *cpsw = priv->cpsw;
1997 void __iomem *regs = cpsw->regs;
df828598
M		 1998 int slave_num = slave->slave_num;
1999 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
2000
2001 slave->data = data;
549985ee
RC		 2002 slave->regs = regs + slave_reg_ofs;
2003 slave->sliver = regs + sliver_reg_ofs;
d9ba8f9e 2004 slave->port_vlan = data->dual_emac_res_vlan;
df828598
M		 2005}
2006
552165bc 2007static int cpsw_probe_dt(struct cpsw_platform_data *data,
2eb32b0a
M		 2008 struct platform_device *pdev)
2009{
2010 struct device_node *node = pdev->dev.of_node;
2011 struct device_node *slave_node;
2012 int i = 0, ret;
2013 u32 prop;
2014
2015 if (!node)
2016 return -EINVAL;
2017
2018 if (of_property_read_u32(node, "slaves", &prop)) {
88c99ff6 2019 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2eb32b0a
M		 2020 return -EINVAL;
2021 }
2022 data->slaves = prop;
2023
e86ac13b 2024 if (of_property_read_u32(node, "active_slave", &prop)) {
88c99ff6 2025 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
aa1a15e2 2026 return -EINVAL;
78ca0b28 2027 }
e86ac13b 2028 data->active_slave = prop;
78ca0b28 2029
00ab94ee 2030 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
88c99ff6 2031 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
aa1a15e2 2032 return -EINVAL;
00ab94ee
RC		 2033 }
2034 data->cpts_clock_mult = prop;
2035
2036 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
88c99ff6 2037 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
aa1a15e2 2038 return -EINVAL;
00ab94ee
RC		 2039 }
2040 data->cpts_clock_shift = prop;
2041
aa1a15e2
DM		 2042 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2043 * sizeof(struct cpsw_slave_data),
2044 GFP_KERNEL);
b2adaca9 2045 if (!data->slave_data)
aa1a15e2 2046 return -ENOMEM;
2eb32b0a 2047
2eb32b0a 2048 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
88c99ff6 2049 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
aa1a15e2 2050 return -EINVAL;
2eb32b0a
M		 2051 }
2052 data->channels = prop;
2053
2eb32b0a 2054 if (of_property_read_u32(node, "ale_entries", &prop)) {
88c99ff6 2055 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
aa1a15e2 2056 return -EINVAL;
2eb32b0a
M		 2057 }
2058 data->ale_entries = prop;
2059
2eb32b0a 2060 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
88c99ff6 2061 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
aa1a15e2 2062 return -EINVAL;
2eb32b0a
M		 2063 }
2064 data->bd_ram_size = prop;
2065
2eb32b0a 2066 if (of_property_read_u32(node, "mac_control", &prop)) {
88c99ff6 2067 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
aa1a15e2 2068 return -EINVAL;
2eb32b0a
M		 2069 }
2070 data->mac_control = prop;
2071
281abd96
MP		 2072 if (of_property_read_bool(node, "dual_emac"))
2073 data->dual_emac = 1;
d9ba8f9e 2074
549985ee
RC		 2075 /*
2076 * Populate all the child nodes here...
2077 */
2078 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2079 /* We do not want to force this, as in some cases may not have child */
2080 if (ret)
88c99ff6 2081 dev_warn(&pdev->dev, "Doesn't have any child node\n");
549985ee 2082
8658aaf2 2083 for_each_available_child_of_node(node, slave_node) {
2eb32b0a 2084 struct cpsw_slave_data *slave_data = data->slave_data + i;
2eb32b0a 2085 const void *mac_addr = NULL;
549985ee
RC		 2086 int lenp;
2087 const __be32 *parp;
549985ee 2088
f468b10e
MP		 2089 /* This is no slave child node, continue */
2090 if (strcmp(slave_node->name, "slave"))
2091 continue;
2092
552165bc
DR		 2093 slave_data->phy_node = of_parse_phandle(slave_node,
2094 "phy-handle", 0);
f1eea5c1 2095 parp = of_get_property(slave_node, "phy_id", &lenp);
ae092b5b
DR		 2096 if (slave_data->phy_node) {
2097 dev_dbg(&pdev->dev,
2098 "slave[%d] using phy-handle=\"%s\"\n",
2099 i, slave_data->phy_node->full_name);
2100 } else if (of_phy_is_fixed_link(slave_node)) {
dfc0a6d3
DR		 2101 /* In the case of a fixed PHY, the DT node associated
2102 * to the PHY is the Ethernet MAC DT node.
2103 */
1f71e8c9
MB		 2104 ret = of_phy_register_fixed_link(slave_node);
2105 if (ret)
2106 return ret;
06cd6d6e 2107 slave_data->phy_node = of_node_get(slave_node);
f1eea5c1
DR		 2108 } else if (parp) {
2109 u32 phyid;
2110 struct device_node *mdio_node;
2111 struct platform_device *mdio;
2112
2113 if (lenp != (sizeof(__be32) * 2)) {
2114 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2115 goto no_phy_slave;
2116 }
2117 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2118 phyid = be32_to_cpup(parp+1);
2119 mdio = of_find_device_by_node(mdio_node);
2120 of_node_put(mdio_node);
2121 if (!mdio) {
2122 dev_err(&pdev->dev, "Missing mdio platform device\n");
2123 return -EINVAL;
2124 }
2125 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2126 PHY_ID_FMT, mdio->name, phyid);
2127 } else {
ae092b5b
DR		 2128 dev_err(&pdev->dev,
2129 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2130 i);
47276fcc 2131 goto no_phy_slave;
2eb32b0a 2132 }
47276fcc
M		 2133 slave_data->phy_if = of_get_phy_mode(slave_node);
2134 if (slave_data->phy_if < 0) {
2135 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2136 i);
2137 return slave_data->phy_if;
2138 }
2139
2140no_phy_slave:
2eb32b0a 2141 mac_addr = of_get_mac_address(slave_node);
0ba517b1 2142 if (mac_addr) {
2eb32b0a 2143 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
0ba517b1 2144 } else {
b6745f6e
M		 2145 ret = ti_cm_get_macid(&pdev->dev, i,
2146 slave_data->mac_addr);
2147 if (ret)
2148 return ret;
0ba517b1 2149 }
d9ba8f9e 2150 if (data->dual_emac) {
91c4166c 2151 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
d9ba8f9e 2152 &prop)) {
88c99ff6 2153 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
d9ba8f9e 2154 slave_data->dual_emac_res_vlan = i+1;
88c99ff6
GC		 2155 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2156 slave_data->dual_emac_res_vlan, i);
d9ba8f9e
M		 2157 } else {
2158 slave_data->dual_emac_res_vlan = prop;
2159 }
2160 }
2161
2eb32b0a 2162 i++;
3a27bfac
M		 2163 if (i == data->slaves)
2164 break;
2eb32b0a
M		 2165 }
2166
2167 return 0;
2eb32b0a
M		 2168}
2169
56e31bd8 2170static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
d9ba8f9e
M		 2171{
2172 struct cpsw_platform_data *data = &priv->data;
2173 struct net_device *ndev;
2174 struct cpsw_priv *priv_sl2;
2175 int ret = 0, i;
56e31bd8 2176 struct cpsw_common *cpsw = priv->cpsw;
d9ba8f9e
M		 2177
2178 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2179 if (!ndev) {
56e31bd8 2180 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
d9ba8f9e
M		 2181 return -ENOMEM;
2182 }
2183
2184 priv_sl2 = netdev_priv(ndev);
649a1688 2185 priv_sl2->cpsw = priv->cpsw;
d9ba8f9e 2186 priv_sl2->data = *data;
d9ba8f9e
M		 2187 priv_sl2->ndev = ndev;
2188 priv_sl2->dev = &ndev->dev;
2189 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2190 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2191
2192 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2193 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2194 ETH_ALEN);
56e31bd8
IK		 2195 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2196 priv_sl2->mac_addr);
d9ba8f9e
M		 2197 } else {
2198 random_ether_addr(priv_sl2->mac_addr);
56e31bd8
IK		 2199 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2200 priv_sl2->mac_addr);
d9ba8f9e
M		 2201 }
2202 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2203
2204 priv_sl2->slaves = priv->slaves;
ff5b8ef2
M		 2205 priv_sl2->coal_intvl = 0;
2206 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
d9ba8f9e
M		 2207 priv_sl2->dma = priv->dma;
2208 priv_sl2->txch = priv->txch;
2209 priv_sl2->rxch = priv->rxch;
2210 priv_sl2->ale = priv->ale;
2211 priv_sl2->emac_port = 1;
2212 priv->slaves[1].ndev = ndev;
2213 priv_sl2->cpts = priv->cpts;
2214 priv_sl2->version = priv->version;
2215
2216 for (i = 0; i < priv->num_irqs; i++) {
2217 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2218 priv_sl2->num_irqs = priv->num_irqs;
2219 }
f646968f 2220 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d9ba8f9e
M		 2221
2222 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2223 ndev->ethtool_ops = &cpsw_ethtool_ops;
d9ba8f9e
M		 2224
2225 /* register the network device */
56e31bd8 2226 SET_NETDEV_DEV(ndev, cpsw->dev);
d9ba8f9e
M		 2227 ret = register_netdev(ndev);
2228 if (ret) {
56e31bd8 2229 dev_err(cpsw->dev, "cpsw: error registering net device\n");
d9ba8f9e
M		 2230 free_netdev(ndev);
2231 ret = -ENODEV;
2232 }
2233
2234 return ret;
2235}
2236
7da11600
M		 2237#define CPSW_QUIRK_IRQ BIT(0)
2238
2239static struct platform_device_id cpsw_devtype[] = {
2240 {
2241 /* keep it for existing comaptibles */
2242 .name = "cpsw",
2243 .driver_data = CPSW_QUIRK_IRQ,
2244 }, {
2245 .name = "am335x-cpsw",
2246 .driver_data = CPSW_QUIRK_IRQ,
2247 }, {
2248 .name = "am4372-cpsw",
2249 .driver_data = 0,
2250 }, {
2251 .name = "dra7-cpsw",
2252 .driver_data = 0,
2253 }, {
2254 /* sentinel */
2255 }
2256};
2257MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2258
2259enum ti_cpsw_type {
2260 CPSW = 0,
2261 AM335X_CPSW,
2262 AM4372_CPSW,
2263 DRA7_CPSW,
2264};
2265
2266static const struct of_device_id cpsw_of_mtable[] = {
2267 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2268 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2269 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2270 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2271 { /* sentinel */ },
2272};
2273MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2274
663e12e6 2275static int cpsw_probe(struct platform_device *pdev)
df828598 2276{
ef4183a1 2277 struct clk *clk;
d1bd9acf 2278 struct cpsw_platform_data *data;
df828598
M		 2279 struct net_device *ndev;
2280 struct cpsw_priv *priv;
2281 struct cpdma_params dma_params;
2282 struct cpsw_ale_params ale_params;
aa1a15e2
DM		 2283 void __iomem *ss_regs;
2284 struct resource *res, *ss_res;
7da11600 2285 const struct of_device_id *of_id;
1d147ccb 2286 struct gpio_descs *mode;
549985ee 2287 u32 slave_offset, sliver_offset, slave_size;
649a1688 2288 struct cpsw_common *cpsw;
5087b915
FB		 2289 int ret = 0, i;
2290 int irq;
df828598 2291
649a1688 2292 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
56e31bd8 2293 cpsw->dev = &pdev->dev;
649a1688 2294
df828598
M		 2295 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2296 if (!ndev) {
88c99ff6 2297 dev_err(&pdev->dev, "error allocating net_device\n");
df828598
M		 2298 return -ENOMEM;
2299 }
2300
2301 platform_set_drvdata(pdev, ndev);
2302 priv = netdev_priv(ndev);
649a1688 2303 priv->cpsw = cpsw;
df828598
M		 2304 priv->ndev = ndev;
2305 priv->dev = &ndev->dev;
2306 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2307 priv->rx_packet_max = max(rx_packet_max, 128);
9232b16d 2308 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
ab8e99d2 2309 if (!priv->cpts) {
88c99ff6 2310 dev_err(&pdev->dev, "error allocating cpts\n");
4d507dff 2311 ret = -ENOMEM;
9232b16d
M		 2312 goto clean_ndev_ret;
2313 }
df828598 2314
1d147ccb
M		 2315 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2316 if (IS_ERR(mode)) {
2317 ret = PTR_ERR(mode);
2318 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2319 goto clean_ndev_ret;
2320 }
2321
1fb19aa7
VH		 2322 /*
2323 * This may be required here for child devices.
2324 */
2325 pm_runtime_enable(&pdev->dev);
2326
739683b4
M		 2327 /* Select default pin state */
2328 pinctrl_pm_select_default_state(&pdev->dev);
2329
552165bc 2330 if (cpsw_probe_dt(&priv->data, pdev)) {
88c99ff6 2331 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2eb32b0a 2332 ret = -ENODEV;
aa1a15e2 2333 goto clean_runtime_disable_ret;
2eb32b0a
M		 2334 }
2335 data = &priv->data;
2336
df828598
M		 2337 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2338 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
88c99ff6 2339 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
df828598 2340 } else {
7efd26d0 2341 eth_random_addr(priv->mac_addr);
88c99ff6 2342 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
df828598
M		 2343 }
2344
2345 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2346
aa1a15e2
DM		 2347 priv->slaves = devm_kzalloc(&pdev->dev,
2348 sizeof(struct cpsw_slave) * data->slaves,
2349 GFP_KERNEL);
df828598 2350 if (!priv->slaves) {
aa1a15e2
DM		 2351 ret = -ENOMEM;
2352 goto clean_runtime_disable_ret;
df828598
M		 2353 }
2354 for (i = 0; i < data->slaves; i++)
2355 priv->slaves[i].slave_num = i;
2356
d9ba8f9e
M		 2357 priv->slaves[0].ndev = ndev;
2358 priv->emac_port = 0;
2359
ef4183a1
IK		 2360 clk = devm_clk_get(&pdev->dev, "fck");
2361 if (IS_ERR(clk)) {
aa1a15e2 2362 dev_err(priv->dev, "fck is not found\n");
f150bd7f 2363 ret = -ENODEV;
aa1a15e2 2364 goto clean_runtime_disable_ret;
df828598 2365 }
ff5b8ef2 2366 priv->coal_intvl = 0;
ef4183a1 2367 priv->bus_freq_mhz = clk_get_rate(clk) / 1000000;
df828598 2368
aa1a15e2
DM		 2369 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2370 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2371 if (IS_ERR(ss_regs)) {
2372 ret = PTR_ERR(ss_regs);
2373 goto clean_runtime_disable_ret;
df828598 2374 }
5d8d0d4d 2375 cpsw->regs = ss_regs;
df828598 2376
f280e89a
M		 2377 /* Need to enable clocks with runtime PM api to access module
2378 * registers
2379 */
108a6537
GS		 2380 ret = pm_runtime_get_sync(&pdev->dev);
2381 if (ret < 0) {
2382 pm_runtime_put_noidle(&pdev->dev);
2383 goto clean_runtime_disable_ret;
2384 }
5d8d0d4d 2385 priv->version = readl(&cpsw->regs->id_ver);
f280e89a
M		 2386 pm_runtime_put_sync(&pdev->dev);
2387
aa1a15e2 2388 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5d8d0d4d
IK		 2389 cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2390 if (IS_ERR(cpsw->wr_regs)) {
2391 ret = PTR_ERR(cpsw->wr_regs);
aa1a15e2 2392 goto clean_runtime_disable_ret;
df828598 2393 }
df828598
M		 2394
2395 memset(&dma_params, 0, sizeof(dma_params));
549985ee
RC		 2396 memset(&ale_params, 0, sizeof(ale_params));
2397
2398 switch (priv->version) {
2399 case CPSW_VERSION_1:
5d8d0d4d 2400 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
d9718546 2401 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
5d8d0d4d 2402 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
549985ee
RC		 2403 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2404 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2405 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2406 slave_offset = CPSW1_SLAVE_OFFSET;
2407 slave_size = CPSW1_SLAVE_SIZE;
2408 sliver_offset = CPSW1_SLIVER_OFFSET;
2409 dma_params.desc_mem_phys = 0;
2410 break;
2411 case CPSW_VERSION_2:
c193f365 2412 case CPSW_VERSION_3:
926489be 2413 case CPSW_VERSION_4:
5d8d0d4d 2414 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
d9718546 2415 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
5d8d0d4d 2416 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
549985ee
RC		 2417 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2418 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2419 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2420 slave_offset = CPSW2_SLAVE_OFFSET;
2421 slave_size = CPSW2_SLAVE_SIZE;
2422 sliver_offset = CPSW2_SLIVER_OFFSET;
2423 dma_params.desc_mem_phys =
aa1a15e2 2424 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
549985ee
RC		 2425 break;
2426 default:
2427 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2428 ret = -ENODEV;
aa1a15e2 2429 goto clean_runtime_disable_ret;
549985ee
RC		 2430 }
2431 for (i = 0; i < priv->data.slaves; i++) {
2432 struct cpsw_slave *slave = &priv->slaves[i];
2433 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2434 slave_offset += slave_size;
2435 sliver_offset += SLIVER_SIZE;
2436 }
2437
df828598 2438 dma_params.dev = &pdev->dev;
549985ee
RC		 2439 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2440 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2441 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2442 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2443 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
df828598
M		 2444
2445 dma_params.num_chan = data->channels;
2446 dma_params.has_soft_reset = true;
2447 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2448 dma_params.desc_mem_size = data->bd_ram_size;
2449 dma_params.desc_align = 16;
2450 dma_params.has_ext_regs = true;
549985ee 2451 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
df828598
M		 2452
2453 priv->dma = cpdma_ctlr_create(&dma_params);
2454 if (!priv->dma) {
2455 dev_err(priv->dev, "error initializing dma\n");
2456 ret = -ENOMEM;
aa1a15e2 2457 goto clean_runtime_disable_ret;
df828598
M		 2458 }
2459
2460 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2461 cpsw_tx_handler);
2462 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2463 cpsw_rx_handler);
2464
2465 if (WARN_ON(!priv->txch || !priv->rxch)) {
2466 dev_err(priv->dev, "error initializing dma channels\n");
2467 ret = -ENOMEM;
2468 goto clean_dma_ret;
2469 }
2470
df828598 2471 ale_params.dev = &ndev->dev;
df828598
M		 2472 ale_params.ale_ageout = ale_ageout;
2473 ale_params.ale_entries = data->ale_entries;
2474 ale_params.ale_ports = data->slaves;
2475
2476 priv->ale = cpsw_ale_create(&ale_params);
2477 if (!priv->ale) {
2478 dev_err(priv->dev, "error initializing ale engine\n");
2479 ret = -ENODEV;
2480 goto clean_dma_ret;
2481 }
2482
c03abd84 2483 ndev->irq = platform_get_irq(pdev, 1);
df828598
M		 2484 if (ndev->irq < 0) {
2485 dev_err(priv->dev, "error getting irq resource\n");
c1e3334f 2486 ret = ndev->irq;
df828598
M		 2487 goto clean_ale_ret;
2488 }
2489
7da11600
M		 2490 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2491 if (of_id) {
2492 pdev->id_entry = of_id->data;
2493 if (pdev->id_entry->driver_data)
2494 priv->quirk_irq = true;
2495 }
2496
c03abd84
FB		 2497 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2498 * MISC IRQs which are always kept disabled with this driver so
2499 * we will not request them.
2500 *
2501 * If anyone wants to implement support for those, make sure to
2502 * first request and append them to irqs_table array.
2503 */
c2b32e58 2504
c03abd84 2505 /* RX IRQ */
5087b915 2506 irq = platform_get_irq(pdev, 1);
c1e3334f
JL		 2507 if (irq < 0) {
2508 ret = irq;
5087b915 2509 goto clean_ale_ret;
c1e3334f 2510 }
5087b915 2511
c03abd84
FB		 2512 priv->irqs_table[0] = irq;
2513 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
5087b915
FB		 2514 0, dev_name(&pdev->dev), priv);
2515 if (ret < 0) {
2516 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2517 goto clean_ale_ret;
2518 }
2519
c03abd84 2520 /* TX IRQ */
5087b915 2521 irq = platform_get_irq(pdev, 2);
c1e3334f
JL		 2522 if (irq < 0) {
2523 ret = irq;
5087b915 2524 goto clean_ale_ret;
c1e3334f 2525 }
5087b915 2526
c03abd84
FB		 2527 priv->irqs_table[1] = irq;
2528 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
5087b915
FB		 2529 0, dev_name(&pdev->dev), priv);
2530 if (ret < 0) {
2531 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2532 goto clean_ale_ret;
df828598 2533 }
c03abd84 2534 priv->num_irqs = 2;
c2b32e58 2535
f646968f 2536 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
df828598
M		 2537
2538 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2539 ndev->ethtool_ops = &cpsw_ethtool_ops;
32a7432c 2540 netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
d64b5e85 2541 netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
df828598
M		 2542
2543 /* register the network device */
2544 SET_NETDEV_DEV(ndev, &pdev->dev);
2545 ret = register_netdev(ndev);
2546 if (ret) {
2547 dev_err(priv->dev, "error registering net device\n");
2548 ret = -ENODEV;
aa1a15e2 2549 goto clean_ale_ret;
df828598
M		 2550 }
2551
1a3b5056
OJ		 2552 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2553 &ss_res->start, ndev->irq);
df828598 2554
d9ba8f9e 2555 if (priv->data.dual_emac) {
56e31bd8 2556 ret = cpsw_probe_dual_emac(priv);
d9ba8f9e
M		 2557 if (ret) {
2558 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
aa1a15e2 2559 goto clean_ale_ret;
d9ba8f9e
M		 2560 }
2561 }
2562
df828598
M		 2563 return 0;
2564
df828598
M		 2565clean_ale_ret:
2566 cpsw_ale_destroy(priv->ale);
2567clean_dma_ret:
df828598 2568 cpdma_ctlr_destroy(priv->dma);
aa1a15e2 2569clean_runtime_disable_ret:
f150bd7f 2570 pm_runtime_disable(&pdev->dev);
df828598 2571clean_ndev_ret:
d1bd9acf 2572 free_netdev(priv->ndev);
df828598
M		 2573 return ret;
2574}
2575
663e12e6 2576static int cpsw_remove(struct platform_device *pdev)
df828598
M		 2577{
2578 struct net_device *ndev = platform_get_drvdata(pdev);
2579 struct cpsw_priv *priv = netdev_priv(ndev);
8a0b6dc9
GS		 2580 int ret;
2581
2582 ret = pm_runtime_get_sync(&pdev->dev);
2583 if (ret < 0) {
2584 pm_runtime_put_noidle(&pdev->dev);
2585 return ret;
2586 }
df828598 2587
d1bd9acf 2588 if (priv->data.dual_emac)
82b52104 2589 unregister_netdev(priv->slaves[1].ndev);
d1bd9acf 2590 unregister_netdev(ndev);
df828598 2591
df828598 2592 cpsw_ale_destroy(priv->ale);
df828598 2593 cpdma_ctlr_destroy(priv->dma);
3bf2cb3a 2594 of_platform_depopulate(&pdev->dev);
8a0b6dc9
GS		 2595 pm_runtime_put_sync(&pdev->dev);
2596 pm_runtime_disable(&pdev->dev);
d1bd9acf 2597 if (priv->data.dual_emac)
82b52104 2598 free_netdev(priv->slaves[1].ndev);
df828598 2599 free_netdev(ndev);
df828598
M		 2600 return 0;
2601}
2602
8963a504 2603#ifdef CONFIG_PM_SLEEP
df828598
M		 2604static int cpsw_suspend(struct device *dev)
2605{
2606 struct platform_device *pdev = to_platform_device(dev);
2607 struct net_device *ndev = platform_get_drvdata(pdev);
b90fc27a 2608 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2609
618073e3
M		 2610 if (priv->data.dual_emac) {
2611 int i;
1e7a2e21 2612
618073e3
M		 2613 for (i = 0; i < priv->data.slaves; i++) {
2614 if (netif_running(priv->slaves[i].ndev))
2615 cpsw_ndo_stop(priv->slaves[i].ndev);
618073e3
M		 2616 }
2617 } else {
2618 if (netif_running(ndev))
2619 cpsw_ndo_stop(ndev);
618073e3 2620 }
1e7a2e21 2621
739683b4 2622 /* Select sleep pin state */
56e31bd8 2623 pinctrl_pm_select_sleep_state(dev);
739683b4 2624
df828598
M		 2625 return 0;
2626}
2627
2628static int cpsw_resume(struct device *dev)
2629{
2630 struct platform_device *pdev = to_platform_device(dev);
2631 struct net_device *ndev = platform_get_drvdata(pdev);
618073e3 2632 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2633
739683b4 2634 /* Select default pin state */
56e31bd8 2635 pinctrl_pm_select_default_state(dev);
739683b4 2636
618073e3
M		 2637 if (priv->data.dual_emac) {
2638 int i;
2639
2640 for (i = 0; i < priv->data.slaves; i++) {
2641 if (netif_running(priv->slaves[i].ndev))
2642 cpsw_ndo_open(priv->slaves[i].ndev);
2643 }
2644 } else {
2645 if (netif_running(ndev))
2646 cpsw_ndo_open(ndev);
2647 }
df828598
M		 2648 return 0;
2649}
8963a504 2650#endif
df828598 2651
8963a504 2652static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
df828598
M		 2653
2654static struct platform_driver cpsw_driver = {
2655 .driver = {
2656 .name = "cpsw",
df828598 2657 .pm = &cpsw_pm_ops,
1e5c76d4 2658 .of_match_table = cpsw_of_mtable,
df828598
M		 2659 },
2660 .probe = cpsw_probe,
663e12e6 2661 .remove = cpsw_remove,
df828598
M		 2662};
2663
6fb3b6b5 2664module_platform_driver(cpsw_driver);
df828598
M		 2665
2666MODULE_LICENSE("GPL");
2667MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2668MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2669MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
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