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net/temac: FIX segfault when process old irqs
[deliverable/linux.git] / drivers / net / ethernet / xilinx / ll_temac_main.c
CommitLineData
92744989
GL		 1/*
2 * Driver for Xilinx TEMAC Ethernet device
3 *
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 *
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
10 *
11 * Notes:
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
21 *
22 * TODO:
92744989
GL		 23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/etherdevice.h>
32#include <linux/init.h>
33#include <linux/mii.h>
34#include <linux/module.h>
35#include <linux/mutex.h>
36#include <linux/netdevice.h>
37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_mdio.h>
40#include <linux/of_platform.h>
9f1a1fca 41#include <linux/of_address.h>
92744989
GL		 42#include <linux/skbuff.h>
43#include <linux/spinlock.h>
44#include <linux/tcp.h> /* needed for sizeof(tcphdr) */
45#include <linux/udp.h> /* needed for sizeof(udphdr) */
46#include <linux/phy.h>
47#include <linux/in.h>
48#include <linux/io.h>
49#include <linux/ip.h>
5a0e3ad6 50#include <linux/slab.h>
ffbc03bc 51#include <linux/interrupt.h>
84cac398 52#include <linux/dma-mapping.h>
92744989
GL		 53
54#include "ll_temac.h"
55
56#define TX_BD_NUM 64
57#define RX_BD_NUM 128
58
59/* ---------------------------------------------------------------------
60 * Low level register access functions
61 */
62
63u32 temac_ior(struct temac_local *lp, int offset)
64{
65 return in_be32((u32 *)(lp->regs + offset));
66}
67
68void temac_iow(struct temac_local *lp, int offset, u32 value)
69{
70 out_be32((u32 *) (lp->regs + offset), value);
71}
72
73int temac_indirect_busywait(struct temac_local *lp)
74{
75 long end = jiffies + 2;
76
77 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
78 if (end - jiffies <= 0) {
79 WARN_ON(1);
80 return -ETIMEDOUT;
81 }
82 msleep(1);
83 }
84 return 0;
85}
86
87/**
88 * temac_indirect_in32
89 *
90 * lp->indirect_mutex must be held when calling this function
91 */
92u32 temac_indirect_in32(struct temac_local *lp, int reg)
93{
94 u32 val;
95
96 if (temac_indirect_busywait(lp))
97 return -ETIMEDOUT;
98 temac_iow(lp, XTE_CTL0_OFFSET, reg);
99 if (temac_indirect_busywait(lp))
100 return -ETIMEDOUT;
101 val = temac_ior(lp, XTE_LSW0_OFFSET);
102
103 return val;
104}
105
106/**
107 * temac_indirect_out32
108 *
109 * lp->indirect_mutex must be held when calling this function
110 */
111void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
112{
113 if (temac_indirect_busywait(lp))
114 return;
115 temac_iow(lp, XTE_LSW0_OFFSET, value);
116 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
117}
118
e44171f1
JL		 119/**
120 * temac_dma_in32 - Memory mapped DMA read, this function expects a
121 * register input that is based on DCR word addresses which
122 * are then converted to memory mapped byte addresses
123 */
92744989
GL		 124static u32 temac_dma_in32(struct temac_local *lp, int reg)
125{
e44171f1 126 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
92744989
GL		 127}
128
e44171f1
JL		 129/**
130 * temac_dma_out32 - Memory mapped DMA read, this function expects a
131 * register input that is based on DCR word addresses which
132 * are then converted to memory mapped byte addresses
133 */
92744989 134static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
e44171f1
JL		 135{
136 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
137}
138
139/* DMA register access functions can be DCR based or memory mapped.
140 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
141 * memory mapped.
142 */
143#ifdef CONFIG_PPC_DCR
144
145/**
146 * temac_dma_dcr_in32 - DCR based DMA read
147 */
148static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
149{
150 return dcr_read(lp->sdma_dcrs, reg);
151}
152
153/**
154 * temac_dma_dcr_out32 - DCR based DMA write
155 */
156static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
92744989
GL		 157{
158 dcr_write(lp->sdma_dcrs, reg, value);
159}
160
e44171f1
JL		 161/**
162 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
163 * I/O functions
164 */
2dc11581 165static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 166 struct device_node *np)
167{
168 unsigned int dcrs;
169
170 /* setup the dcr address mapping if it's in the device tree */
171
172 dcrs = dcr_resource_start(np, 0);
173 if (dcrs != 0) {
174 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
175 lp->dma_in = temac_dma_dcr_in;
176 lp->dma_out = temac_dma_dcr_out;
177 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
178 return 0;
179 }
180 /* no DCR in the device tree, indicate a failure */
181 return -1;
182}
183
184#else
185
186/*
187 * temac_dcr_setup - This is a stub for when DCR is not supported,
188 * such as with MicroBlaze
189 */
2dc11581 190static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 191 struct device_node *np)
192{
193 return -1;
194}
195
196#endif
197
301e9d96
DK		 198/**
199 * * temac_dma_bd_release - Release buffer descriptor rings
200 */
201static void temac_dma_bd_release(struct net_device *ndev)
202{
203 struct temac_local *lp = netdev_priv(ndev);
204 int i;
205
50ec1538
RR		 206 /* Reset Local Link (DMA) */
207 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
208
301e9d96
DK		 209 for (i = 0; i < RX_BD_NUM; i++) {
210 if (!lp->rx_skb[i])
211 break;
212 else {
213 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
214 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
215 dev_kfree_skb(lp->rx_skb[i]);
216 }
217 }
218 if (lp->rx_bd_v)
219 dma_free_coherent(ndev->dev.parent,
220 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
221 lp->rx_bd_v, lp->rx_bd_p);
222 if (lp->tx_bd_v)
223 dma_free_coherent(ndev->dev.parent,
224 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
225 lp->tx_bd_v, lp->tx_bd_p);
226 if (lp->rx_skb)
227 kfree(lp->rx_skb);
228}
229
92744989
GL		 230/**
231 * temac_dma_bd_init - Setup buffer descriptor rings
232 */
233static int temac_dma_bd_init(struct net_device *ndev)
234{
235 struct temac_local *lp = netdev_priv(ndev);
236 struct sk_buff *skb;
237 int i;
238
5d66fe92 239 lp->rx_skb = kzalloc(sizeof(*lp->rx_skb) * RX_BD_NUM, GFP_KERNEL);
fe62c298
DK		 240 if (!lp->rx_skb) {
241 dev_err(&ndev->dev,
242 "can't allocate memory for DMA RX buffer\n");
243 goto out;
244 }
92744989 245 /* allocate the tx and rx ring buffer descriptors. */
b595076a 246 /* returns a virtual address and a physical address. */
92744989
GL		 247 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
248 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
249 &lp->tx_bd_p, GFP_KERNEL);
fe62c298
DK		 250 if (!lp->tx_bd_v) {
251 dev_err(&ndev->dev,
252 "unable to allocate DMA TX buffer descriptors");
253 goto out;
254 }
92744989
GL		 255 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
256 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
257 &lp->rx_bd_p, GFP_KERNEL);
fe62c298
DK		 258 if (!lp->rx_bd_v) {
259 dev_err(&ndev->dev,
260 "unable to allocate DMA RX buffer descriptors");
261 goto out;
262 }
92744989
GL		 263
264 memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
265 for (i = 0; i < TX_BD_NUM; i++) {
266 lp->tx_bd_v[i].next = lp->tx_bd_p +
267 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
268 }
269
270 memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
271 for (i = 0; i < RX_BD_NUM; i++) {
272 lp->rx_bd_v[i].next = lp->rx_bd_p +
273 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
274
e44171f1
JL		 275 skb = netdev_alloc_skb_ip_align(ndev,
276 XTE_MAX_JUMBO_FRAME_SIZE);
277
92744989
GL		 278 if (skb == 0) {
279 dev_err(&ndev->dev, "alloc_skb error %d\n", i);
fe62c298 280 goto out;
92744989
GL		 281 }
282 lp->rx_skb[i] = skb;
92744989
GL		 283 /* returns physical address of skb->data */
284 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
285 skb->data,
286 XTE_MAX_JUMBO_FRAME_SIZE,
287 DMA_FROM_DEVICE);
288 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
289 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
290 }
291
e44171f1 292 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
92744989
GL		 293 CHNL_CTRL_IRQ_EN |
294 CHNL_CTRL_IRQ_DLY_EN |
295 CHNL_CTRL_IRQ_COAL_EN);
296 /* 0x10220483 */
297 /* 0x00100483 */
23ecc4bd 298 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
92744989
GL		 299 CHNL_CTRL_IRQ_EN |
300 CHNL_CTRL_IRQ_DLY_EN |
301 CHNL_CTRL_IRQ_COAL_EN |
302 CHNL_CTRL_IRQ_IOE);
303 /* 0xff010283 */
304
e44171f1
JL		 305 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
306 lp->dma_out(lp, RX_TAILDESC_PTR,
92744989 307 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
e44171f1 308 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
92744989
GL		 309
310 return 0;
fe62c298
DK		 311
312out:
301e9d96 313 temac_dma_bd_release(ndev);
fe62c298 314 return -ENOMEM;
92744989
GL		 315}
316
317/* ---------------------------------------------------------------------
318 * net_device_ops
319 */
320
321static int temac_set_mac_address(struct net_device *ndev, void *address)
322{
323 struct temac_local *lp = netdev_priv(ndev);
324
325 if (address)
326 memcpy(ndev->dev_addr, address, ETH_ALEN);
327
328 if (!is_valid_ether_addr(ndev->dev_addr))
329 random_ether_addr(ndev->dev_addr);
330
331 /* set up unicast MAC address filter set its mac address */
332 mutex_lock(&lp->indirect_mutex);
333 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
334 (ndev->dev_addr[0]) |
335 (ndev->dev_addr[1] << 8) |
336 (ndev->dev_addr[2] << 16) |
337 (ndev->dev_addr[3] << 24));
338 /* There are reserved bits in EUAW1
339 * so don't affect them Set MAC bits [47:32] in EUAW1 */
340 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
341 (ndev->dev_addr[4] & 0x000000ff) |
342 (ndev->dev_addr[5] << 8));
343 mutex_unlock(&lp->indirect_mutex);
344
345 return 0;
346}
347
8ea7a37c
SM		 348static int netdev_set_mac_address(struct net_device *ndev, void *p)
349{
350 struct sockaddr *addr = p;
351
352 return temac_set_mac_address(ndev, addr->sa_data);
353}
354
92744989
GL		 355static void temac_set_multicast_list(struct net_device *ndev)
356{
357 struct temac_local *lp = netdev_priv(ndev);
358 u32 multi_addr_msw, multi_addr_lsw, val;
359 int i;
360
361 mutex_lock(&lp->indirect_mutex);
8e95a202 362 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
4cd24eaf 363 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
92744989
GL		 364 /*
365 * We must make the kernel realise we had to move
366 * into promisc mode or we start all out war on
367 * the cable. If it was a promisc request the
368 * flag is already set. If not we assert it.
369 */
370 ndev->flags |= IFF_PROMISC;
371 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
372 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
4cd24eaf 373 } else if (!netdev_mc_empty(ndev)) {
22bedad3 374 struct netdev_hw_addr *ha;
92744989 375
f9dcbcc9 376 i = 0;
22bedad3 377 netdev_for_each_mc_addr(ha, ndev) {
92744989
GL		 378 if (i >= MULTICAST_CAM_TABLE_NUM)
379 break;
22bedad3
JP		 380 multi_addr_msw = ((ha->addr[3] << 24) |
381 (ha->addr[2] << 16) |
382 (ha->addr[1] << 8) |
383 (ha->addr[0]));
92744989
GL		 384 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
385 multi_addr_msw);
22bedad3
JP		 386 multi_addr_lsw = ((ha->addr[5] << 8) |
387 (ha->addr[4]) | (i << 16));
92744989
GL		 388 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
389 multi_addr_lsw);
f9dcbcc9 390 i++;
92744989
GL		 391 }
392 } else {
393 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
394 temac_indirect_out32(lp, XTE_AFM_OFFSET,
395 val & ~XTE_AFM_EPPRM_MASK);
396 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
397 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
398 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
399 }
400 mutex_unlock(&lp->indirect_mutex);
401}
402
403struct temac_option {
404 int flg;
405 u32 opt;
406 u32 reg;
407 u32 m_or;
408 u32 m_and;
409} temac_options[] = {
410 /* Turn on jumbo packet support for both Rx and Tx */
411 {
412 .opt = XTE_OPTION_JUMBO,
413 .reg = XTE_TXC_OFFSET,
414 .m_or = XTE_TXC_TXJMBO_MASK,
415 },
416 {
417 .opt = XTE_OPTION_JUMBO,
418 .reg = XTE_RXC1_OFFSET,
419 .m_or =XTE_RXC1_RXJMBO_MASK,
420 },
421 /* Turn on VLAN packet support for both Rx and Tx */
422 {
423 .opt = XTE_OPTION_VLAN,
424 .reg = XTE_TXC_OFFSET,
425 .m_or =XTE_TXC_TXVLAN_MASK,
426 },
427 {
428 .opt = XTE_OPTION_VLAN,
429 .reg = XTE_RXC1_OFFSET,
430 .m_or =XTE_RXC1_RXVLAN_MASK,
431 },
432 /* Turn on FCS stripping on receive packets */
433 {
434 .opt = XTE_OPTION_FCS_STRIP,
435 .reg = XTE_RXC1_OFFSET,
436 .m_or =XTE_RXC1_RXFCS_MASK,
437 },
438 /* Turn on FCS insertion on transmit packets */
439 {
440 .opt = XTE_OPTION_FCS_INSERT,
441 .reg = XTE_TXC_OFFSET,
442 .m_or =XTE_TXC_TXFCS_MASK,
443 },
444 /* Turn on length/type field checking on receive packets */
445 {
446 .opt = XTE_OPTION_LENTYPE_ERR,
447 .reg = XTE_RXC1_OFFSET,
448 .m_or =XTE_RXC1_RXLT_MASK,
449 },
450 /* Turn on flow control */
451 {
452 .opt = XTE_OPTION_FLOW_CONTROL,
453 .reg = XTE_FCC_OFFSET,
454 .m_or =XTE_FCC_RXFLO_MASK,
455 },
456 /* Turn on flow control */
457 {
458 .opt = XTE_OPTION_FLOW_CONTROL,
459 .reg = XTE_FCC_OFFSET,
460 .m_or =XTE_FCC_TXFLO_MASK,
461 },
462 /* Turn on promiscuous frame filtering (all frames are received ) */
463 {
464 .opt = XTE_OPTION_PROMISC,
465 .reg = XTE_AFM_OFFSET,
466 .m_or =XTE_AFM_EPPRM_MASK,
467 },
468 /* Enable transmitter if not already enabled */
469 {
470 .opt = XTE_OPTION_TXEN,
471 .reg = XTE_TXC_OFFSET,
472 .m_or =XTE_TXC_TXEN_MASK,
473 },
474 /* Enable receiver? */
475 {
476 .opt = XTE_OPTION_RXEN,
477 .reg = XTE_RXC1_OFFSET,
478 .m_or =XTE_RXC1_RXEN_MASK,
479 },
480 {}
481};
482
483/**
484 * temac_setoptions
485 */
486static u32 temac_setoptions(struct net_device *ndev, u32 options)
487{
488 struct temac_local *lp = netdev_priv(ndev);
489 struct temac_option *tp = &temac_options[0];
490 int reg;
491
492 mutex_lock(&lp->indirect_mutex);
493 while (tp->opt) {
494 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
495 if (options & tp->opt)
496 reg |= tp->m_or;
497 temac_indirect_out32(lp, tp->reg, reg);
498 tp++;
499 }
500 lp->options |= options;
501 mutex_unlock(&lp->indirect_mutex);
502
807540ba 503 return 0;
92744989
GL		 504}
505
421f91d2 506/* Initialize temac */
92744989
GL		 507static void temac_device_reset(struct net_device *ndev)
508{
509 struct temac_local *lp = netdev_priv(ndev);
510 u32 timeout;
511 u32 val;
512
513 /* Perform a software reset */
514
515 /* 0x300 host enable bit ? */
516 /* reset PHY through control register ?:1 */
517
518 dev_dbg(&ndev->dev, "%s()\n", __func__);
519
520 mutex_lock(&lp->indirect_mutex);
521 /* Reset the receiver and wait for it to finish reset */
522 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
523 timeout = 1000;
524 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
525 udelay(1);
526 if (--timeout == 0) {
527 dev_err(&ndev->dev,
528 "temac_device_reset RX reset timeout!!\n");
529 break;
530 }
531 }
532
533 /* Reset the transmitter and wait for it to finish reset */
534 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
535 timeout = 1000;
536 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
537 udelay(1);
538 if (--timeout == 0) {
539 dev_err(&ndev->dev,
540 "temac_device_reset TX reset timeout!!\n");
541 break;
542 }
543 }
544
545 /* Disable the receiver */
546 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
547 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
548
549 /* Reset Local Link (DMA) */
e44171f1 550 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
92744989 551 timeout = 1000;
e44171f1 552 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
92744989
GL		 553 udelay(1);
554 if (--timeout == 0) {
555 dev_err(&ndev->dev,
556 "temac_device_reset DMA reset timeout!!\n");
557 break;
558 }
559 }
e44171f1 560 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
92744989 561
fe62c298
DK		 562 if (temac_dma_bd_init(ndev)) {
563 dev_err(&ndev->dev,
564 "temac_device_reset descriptor allocation failed\n");
565 }
92744989
GL		 566
567 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
568 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
569 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
570 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
571
572 mutex_unlock(&lp->indirect_mutex);
573
574 /* Sync default options with HW
575 * but leave receiver and transmitter disabled. */
576 temac_setoptions(ndev,
577 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
578
579 temac_set_mac_address(ndev, NULL);
580
581 /* Set address filter table */
582 temac_set_multicast_list(ndev);
583 if (temac_setoptions(ndev, lp->options))
584 dev_err(&ndev->dev, "Error setting TEMAC options\n");
585
586 /* Init Driver variable */
1ae5dc34 587 ndev->trans_start = jiffies; /* prevent tx timeout */
92744989
GL		 588}
589
590void temac_adjust_link(struct net_device *ndev)
591{
592 struct temac_local *lp = netdev_priv(ndev);
593 struct phy_device *phy = lp->phy_dev;
594 u32 mii_speed;
595 int link_state;
596
597 /* hash together the state values to decide if something has changed */
598 link_state = phy->speed | (phy->duplex << 1) | phy->link;
599
600 mutex_lock(&lp->indirect_mutex);
601 if (lp->last_link != link_state) {
602 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
603 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
604
605 switch (phy->speed) {
606 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
607 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
608 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
609 }
610
611 /* Write new speed setting out to TEMAC */
612 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
613 lp->last_link = link_state;
614 phy_print_status(phy);
615 }
616 mutex_unlock(&lp->indirect_mutex);
617}
618
619static void temac_start_xmit_done(struct net_device *ndev)
620{
621 struct temac_local *lp = netdev_priv(ndev);
622 struct cdmac_bd *cur_p;
623 unsigned int stat = 0;
624
625 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
626 stat = cur_p->app0;
627
628 while (stat & STS_CTRL_APP0_CMPLT) {
629 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
630 DMA_TO_DEVICE);
631 if (cur_p->app4)
632 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
633 cur_p->app0 = 0;
23ecc4bd
BH		 634 cur_p->app1 = 0;
635 cur_p->app2 = 0;
636 cur_p->app3 = 0;
637 cur_p->app4 = 0;
92744989
GL		 638
639 ndev->stats.tx_packets++;
640 ndev->stats.tx_bytes += cur_p->len;
641
642 lp->tx_bd_ci++;
643 if (lp->tx_bd_ci >= TX_BD_NUM)
644 lp->tx_bd_ci = 0;
645
646 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
647 stat = cur_p->app0;
648 }
649
650 netif_wake_queue(ndev);
651}
652
23ecc4bd
BH		 653static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
654{
655 struct cdmac_bd *cur_p;
656 int tail;
657
658 tail = lp->tx_bd_tail;
659 cur_p = &lp->tx_bd_v[tail];
660
661 do {
662 if (cur_p->app0)
663 return NETDEV_TX_BUSY;
664
665 tail++;
666 if (tail >= TX_BD_NUM)
667 tail = 0;
668
669 cur_p = &lp->tx_bd_v[tail];
670 num_frag--;
671 } while (num_frag >= 0);
672
673 return 0;
674}
675
92744989
GL		 676static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
677{
678 struct temac_local *lp = netdev_priv(ndev);
679 struct cdmac_bd *cur_p;
680 dma_addr_t start_p, tail_p;
681 int ii;
682 unsigned long num_frag;
683 skb_frag_t *frag;
684
685 num_frag = skb_shinfo(skb)->nr_frags;
686 frag = &skb_shinfo(skb)->frags[0];
687 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
688 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
689
23ecc4bd 690 if (temac_check_tx_bd_space(lp, num_frag)) {
92744989
GL		 691 if (!netif_queue_stopped(ndev)) {
692 netif_stop_queue(ndev);
693 return NETDEV_TX_BUSY;
694 }
695 return NETDEV_TX_BUSY;
696 }
697
698 cur_p->app0 = 0;
699 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 700 unsigned int csum_start_off = skb_checksum_start_offset(skb);
23ecc4bd
BH		 701 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
702
703 cur_p->app0 |= 1; /* TX Checksum Enabled */
704 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
705 cur_p->app2 = 0; /* initial checksum seed */
92744989 706 }
23ecc4bd 707
92744989
GL		 708 cur_p->app0 |= STS_CTRL_APP0_SOP;
709 cur_p->len = skb_headlen(skb);
710 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
711 DMA_TO_DEVICE);
712 cur_p->app4 = (unsigned long)skb;
713
714 for (ii = 0; ii < num_frag; ii++) {
715 lp->tx_bd_tail++;
716 if (lp->tx_bd_tail >= TX_BD_NUM)
717 lp->tx_bd_tail = 0;
718
719 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
720 cur_p->phys = dma_map_single(ndev->dev.parent,
3ed6f695 721 skb_frag_address(frag),
2edcd4ca
SR		 722 skb_frag_size(frag), DMA_TO_DEVICE);
723 cur_p->len = skb_frag_size(frag);
92744989
GL		 724 cur_p->app0 = 0;
725 frag++;
726 }
727 cur_p->app0 |= STS_CTRL_APP0_EOP;
728
729 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
730 lp->tx_bd_tail++;
731 if (lp->tx_bd_tail >= TX_BD_NUM)
732 lp->tx_bd_tail = 0;
733
93e0ed15
RC		 734 skb_tx_timestamp(skb);
735
92744989 736 /* Kick off the transfer */
e44171f1 737 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
92744989 738
6ed10654 739 return NETDEV_TX_OK;
92744989
GL		 740}
741
742
743static void ll_temac_recv(struct net_device *ndev)
744{
745 struct temac_local *lp = netdev_priv(ndev);
746 struct sk_buff *skb, *new_skb;
747 unsigned int bdstat;
748 struct cdmac_bd *cur_p;
749 dma_addr_t tail_p;
750 int length;
92744989
GL		 751 unsigned long flags;
752
753 spin_lock_irqsave(&lp->rx_lock, flags);
754
755 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
756 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
757
758 bdstat = cur_p->app0;
759 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
760
761 skb = lp->rx_skb[lp->rx_bd_ci];
c3b7c12c 762 length = cur_p->app4 & 0x3FFF;
92744989 763
33646d7f 764 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
92744989
GL		 765 DMA_FROM_DEVICE);
766
767 skb_put(skb, length);
768 skb->dev = ndev;
769 skb->protocol = eth_type_trans(skb, ndev);
bc8acf2c 770 skb_checksum_none_assert(skb);
92744989 771
23ecc4bd
BH		 772 /* if we're doing rx csum offload, set it up */
773 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
774 (skb->protocol == __constant_htons(ETH_P_IP)) &&
775 (skb->len > 64)) {
776
777 skb->csum = cur_p->app3 & 0xFFFF;
778 skb->ip_summed = CHECKSUM_COMPLETE;
779 }
780
93e0ed15
RC		 781 if (!skb_defer_rx_timestamp(skb))
782 netif_rx(skb);
92744989
GL		 783
784 ndev->stats.rx_packets++;
785 ndev->stats.rx_bytes += length;
786
e44171f1
JL		 787 new_skb = netdev_alloc_skb_ip_align(ndev,
788 XTE_MAX_JUMBO_FRAME_SIZE);
789
92744989
GL		 790 if (new_skb == 0) {
791 dev_err(&ndev->dev, "no memory for new sk_buff\n");
792 spin_unlock_irqrestore(&lp->rx_lock, flags);
793 return;
794 }
795
92744989
GL		 796 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
797 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
798 XTE_MAX_JUMBO_FRAME_SIZE,
799 DMA_FROM_DEVICE);
800 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
801 lp->rx_skb[lp->rx_bd_ci] = new_skb;
802
803 lp->rx_bd_ci++;
804 if (lp->rx_bd_ci >= RX_BD_NUM)
805 lp->rx_bd_ci = 0;
806
807 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
808 bdstat = cur_p->app0;
809 }
e44171f1 810 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
92744989
GL		 811
812 spin_unlock_irqrestore(&lp->rx_lock, flags);
813}
814
815static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
816{
817 struct net_device *ndev = _ndev;
818 struct temac_local *lp = netdev_priv(ndev);
819 unsigned int status;
820
e44171f1
JL		 821 status = lp->dma_in(lp, TX_IRQ_REG);
822 lp->dma_out(lp, TX_IRQ_REG, status);
92744989
GL		 823
824 if (status & (IRQ_COAL | IRQ_DLY))
825 temac_start_xmit_done(lp->ndev);
826 if (status & 0x080)
827 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
828
829 return IRQ_HANDLED;
830}
831
832static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
833{
834 struct net_device *ndev = _ndev;
835 struct temac_local *lp = netdev_priv(ndev);
836 unsigned int status;
837
838 /* Read and clear the status registers */
e44171f1
JL		 839 status = lp->dma_in(lp, RX_IRQ_REG);
840 lp->dma_out(lp, RX_IRQ_REG, status);
92744989
GL		 841
842 if (status & (IRQ_COAL | IRQ_DLY))
843 ll_temac_recv(lp->ndev);
844
845 return IRQ_HANDLED;
846}
847
848static int temac_open(struct net_device *ndev)
849{
850 struct temac_local *lp = netdev_priv(ndev);
851 int rc;
852
853 dev_dbg(&ndev->dev, "temac_open()\n");
854
855 if (lp->phy_node) {
856 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
857 temac_adjust_link, 0, 0);
858 if (!lp->phy_dev) {
859 dev_err(lp->dev, "of_phy_connect() failed\n");
860 return -ENODEV;
861 }
862
863 phy_start(lp->phy_dev);
864 }
865
50ec1538
RR		 866 temac_device_reset(ndev);
867
92744989
GL		 868 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
869 if (rc)
870 goto err_tx_irq;
871 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
872 if (rc)
873 goto err_rx_irq;
874
92744989
GL		 875 return 0;
876
877 err_rx_irq:
878 free_irq(lp->tx_irq, ndev);
879 err_tx_irq:
880 if (lp->phy_dev)
881 phy_disconnect(lp->phy_dev);
882 lp->phy_dev = NULL;
883 dev_err(lp->dev, "request_irq() failed\n");
884 return rc;
885}
886
887static int temac_stop(struct net_device *ndev)
888{
889 struct temac_local *lp = netdev_priv(ndev);
890
891 dev_dbg(&ndev->dev, "temac_close()\n");
892
893 free_irq(lp->tx_irq, ndev);
894 free_irq(lp->rx_irq, ndev);
895
896 if (lp->phy_dev)
897 phy_disconnect(lp->phy_dev);
898 lp->phy_dev = NULL;
899
301e9d96
DK		 900 temac_dma_bd_release(ndev);
901
92744989
GL		 902 return 0;
903}
904
905#ifdef CONFIG_NET_POLL_CONTROLLER
906static void
907temac_poll_controller(struct net_device *ndev)
908{
909 struct temac_local *lp = netdev_priv(ndev);
910
911 disable_irq(lp->tx_irq);
912 disable_irq(lp->rx_irq);
913
8539992f
MS		 914 ll_temac_rx_irq(lp->tx_irq, ndev);
915 ll_temac_tx_irq(lp->rx_irq, ndev);
92744989
GL		 916
917 enable_irq(lp->tx_irq);
918 enable_irq(lp->rx_irq);
919}
920#endif
921
922static const struct net_device_ops temac_netdev_ops = {
923 .ndo_open = temac_open,
924 .ndo_stop = temac_stop,
925 .ndo_start_xmit = temac_start_xmit,
8ea7a37c 926 .ndo_set_mac_address = netdev_set_mac_address,
60eb5fd1 927 .ndo_validate_addr = eth_validate_addr,
92744989
GL		 928#ifdef CONFIG_NET_POLL_CONTROLLER
929 .ndo_poll_controller = temac_poll_controller,
930#endif
931};
932
933/* ---------------------------------------------------------------------
934 * SYSFS device attributes
935 */
936static ssize_t temac_show_llink_regs(struct device *dev,
937 struct device_attribute *attr, char *buf)
938{
939 struct net_device *ndev = dev_get_drvdata(dev);
940 struct temac_local *lp = netdev_priv(ndev);
941 int i, len = 0;
942
943 for (i = 0; i < 0x11; i++)
e44171f1 944 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
92744989
GL		 945 (i % 8) == 7 ? "\n" : " ");
946 len += sprintf(buf + len, "\n");
947
948 return len;
949}
950
951static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
952
953static struct attribute *temac_device_attrs[] = {
954 &dev_attr_llink_regs.attr,
955 NULL,
956};
957
958static const struct attribute_group temac_attr_group = {
959 .attrs = temac_device_attrs,
960};
961
9eac2d4d
R		 962/* ethtool support */
963static int temac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
964{
965 struct temac_local *lp = netdev_priv(ndev);
966 return phy_ethtool_gset(lp->phy_dev, cmd);
967}
968
969static int temac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
970{
971 struct temac_local *lp = netdev_priv(ndev);
972 return phy_ethtool_sset(lp->phy_dev, cmd);
973}
974
975static int temac_nway_reset(struct net_device *ndev)
976{
977 struct temac_local *lp = netdev_priv(ndev);
978 return phy_start_aneg(lp->phy_dev);
979}
980
981static const struct ethtool_ops temac_ethtool_ops = {
982 .get_settings = temac_get_settings,
983 .set_settings = temac_set_settings,
984 .nway_reset = temac_nway_reset,
985 .get_link = ethtool_op_get_link,
986};
987
74888760 988static int __devinit temac_of_probe(struct platform_device *op)
92744989
GL		 989{
990 struct device_node *np;
991 struct temac_local *lp;
992 struct net_device *ndev;
993 const void *addr;
23ecc4bd 994 __be32 *p;
92744989 995 int size, rc = 0;
92744989
GL		 996
997 /* Init network device structure */
998 ndev = alloc_etherdev(sizeof(*lp));
999 if (!ndev) {
1000 dev_err(&op->dev, "could not allocate device.\n");
1001 return -ENOMEM;
1002 }
1003 ether_setup(ndev);
1004 dev_set_drvdata(&op->dev, ndev);
1005 SET_NETDEV_DEV(ndev, &op->dev);
1006 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1007 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
1008 ndev->netdev_ops = &temac_netdev_ops;
9eac2d4d 1009 ndev->ethtool_ops = &temac_ethtool_ops;
92744989
GL		 1010#if 0
1011 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1012 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1013 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1014 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1015 ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
1016 ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
1017 ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
1018 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1019 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1020 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1021 ndev->features |= NETIF_F_LRO; /* large receive offload */
1022#endif
1023
1024 /* setup temac private info structure */
1025 lp = netdev_priv(ndev);
1026 lp->ndev = ndev;
1027 lp->dev = &op->dev;
1028 lp->options = XTE_OPTION_DEFAULTS;
1029 spin_lock_init(&lp->rx_lock);
1030 mutex_init(&lp->indirect_mutex);
1031
1032 /* map device registers */
61c7a080 1033 lp->regs = of_iomap(op->dev.of_node, 0);
92744989
GL		 1034 if (!lp->regs) {
1035 dev_err(&op->dev, "could not map temac regs.\n");
1036 goto nodev;
1037 }
1038
23ecc4bd
BH		 1039 /* Setup checksum offload, but default to off if not specified */
1040 lp->temac_features = 0;
1041 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1042 if (p && be32_to_cpu(*p)) {
1043 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1044 /* Can checksum TCP/UDP over IPv4. */
1045 ndev->features |= NETIF_F_IP_CSUM;
1046 }
1047 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1048 if (p && be32_to_cpu(*p))
1049 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1050
92744989 1051 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
61c7a080 1052 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
92744989
GL		 1053 if (!np) {
1054 dev_err(&op->dev, "could not find DMA node\n");
dfe1e8ed 1055 goto err_iounmap;
92744989
GL		 1056 }
1057
e44171f1
JL		 1058 /* Setup the DMA register accesses, could be DCR or memory mapped */
1059 if (temac_dcr_setup(lp, op, np)) {
1060
1061 /* no DCR in the device tree, try non-DCR */
1062 lp->sdma_regs = of_iomap(np, 0);
1063 if (lp->sdma_regs) {
1064 lp->dma_in = temac_dma_in32;
1065 lp->dma_out = temac_dma_out32;
1066 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1067 } else {
1068 dev_err(&op->dev, "unable to map DMA registers\n");
7cc36f6f 1069 of_node_put(np);
dfe1e8ed 1070 goto err_iounmap;
e44171f1 1071 }
92744989 1072 }
92744989
GL		 1073
1074 lp->rx_irq = irq_of_parse_and_map(np, 0);
1075 lp->tx_irq = irq_of_parse_and_map(np, 1);
7cc36f6f
KV		 1076
1077 of_node_put(np); /* Finished with the DMA node; drop the reference */
1078
755fae0a 1079 if ((lp->rx_irq == NO_IRQ) || (lp->tx_irq == NO_IRQ)) {
92744989
GL		 1080 dev_err(&op->dev, "could not determine irqs\n");
1081 rc = -ENOMEM;
dfe1e8ed 1082 goto err_iounmap_2;
92744989
GL		 1083 }
1084
92744989
GL		 1085
1086 /* Retrieve the MAC address */
61c7a080 1087 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
92744989
GL		 1088 if ((!addr) || (size != 6)) {
1089 dev_err(&op->dev, "could not find MAC address\n");
1090 rc = -ENODEV;
dfe1e8ed 1091 goto err_iounmap_2;
92744989
GL		 1092 }
1093 temac_set_mac_address(ndev, (void *)addr);
1094
61c7a080 1095 rc = temac_mdio_setup(lp, op->dev.of_node);
92744989
GL		 1096 if (rc)
1097 dev_warn(&op->dev, "error registering MDIO bus\n");
1098
61c7a080 1099 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
92744989
GL		 1100 if (lp->phy_node)
1101 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1102
1103 /* Add the device attributes */
1104 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1105 if (rc) {
1106 dev_err(lp->dev, "Error creating sysfs files\n");
dfe1e8ed 1107 goto err_iounmap_2;
92744989
GL		 1108 }
1109
1110 rc = register_netdev(lp->ndev);
1111 if (rc) {
1112 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1113 goto err_register_ndev;
1114 }
1115
1116 return 0;
1117
1118 err_register_ndev:
1119 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
dfe1e8ed
DK		 1120 err_iounmap_2:
1121 if (lp->sdma_regs)
1122 iounmap(lp->sdma_regs);
1123 err_iounmap:
1124 iounmap(lp->regs);
92744989
GL		 1125 nodev:
1126 free_netdev(ndev);
1127 ndev = NULL;
1128 return rc;
1129}
1130
2dc11581 1131static int __devexit temac_of_remove(struct platform_device *op)
92744989
GL		 1132{
1133 struct net_device *ndev = dev_get_drvdata(&op->dev);
1134 struct temac_local *lp = netdev_priv(ndev);
1135
1136 temac_mdio_teardown(lp);
1137 unregister_netdev(ndev);
1138 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1139 if (lp->phy_node)
1140 of_node_put(lp->phy_node);
1141 lp->phy_node = NULL;
1142 dev_set_drvdata(&op->dev, NULL);
dfe1e8ed
DK		 1143 iounmap(lp->regs);
1144 if (lp->sdma_regs)
1145 iounmap(lp->sdma_regs);
92744989
GL		 1146 free_netdev(ndev);
1147 return 0;
1148}
1149
1150static struct of_device_id temac_of_match[] __devinitdata = {
1151 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
c3b7c12c
SM		 1152 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1153 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1154 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
92744989
GL		 1155 {},
1156};
1157MODULE_DEVICE_TABLE(of, temac_of_match);
1158
74888760 1159static struct platform_driver temac_of_driver = {
92744989
GL		 1160 .probe = temac_of_probe,
1161 .remove = __devexit_p(temac_of_remove),
1162 .driver = {
1163 .owner = THIS_MODULE,
1164 .name = "xilinx_temac",
4018294b 1165 .of_match_table = temac_of_match,
92744989
GL		 1166 },
1167};
1168
1169static int __init temac_init(void)
1170{
74888760 1171 return platform_driver_register(&temac_of_driver);
92744989
GL		 1172}
1173module_init(temac_init);
1174
1175static void __exit temac_exit(void)
1176{
74888760 1177 platform_driver_unregister(&temac_of_driver);
92744989
GL		 1178}
1179module_exit(temac_exit);
1180
1181MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1182MODULE_AUTHOR("Yoshio Kashiwagi");
1183MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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