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a1702857 TR |
1 | /* |
2 | * linux/drivers/net/ethoc.c | |
3 | * | |
4 | * Copyright (C) 2007-2008 Avionic Design Development GmbH | |
5 | * Copyright (C) 2008-2009 Avionic Design GmbH | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * Written by Thierry Reding <thierry.reding@avionic-design.de> | |
12 | */ | |
13 | ||
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/crc32.h> | |
a6b7a407 | 16 | #include <linux/interrupt.h> |
a1702857 TR |
17 | #include <linux/io.h> |
18 | #include <linux/mii.h> | |
19 | #include <linux/phy.h> | |
20 | #include <linux/platform_device.h> | |
d43c36dc | 21 | #include <linux/sched.h> |
5a0e3ad6 | 22 | #include <linux/slab.h> |
e0f4258b | 23 | #include <linux/of.h> |
a1702857 TR |
24 | #include <net/ethoc.h> |
25 | ||
0baa080c TC |
26 | static int buffer_size = 0x8000; /* 32 KBytes */ |
27 | module_param(buffer_size, int, 0); | |
28 | MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size"); | |
29 | ||
a1702857 TR |
30 | /* register offsets */ |
31 | #define MODER 0x00 | |
32 | #define INT_SOURCE 0x04 | |
33 | #define INT_MASK 0x08 | |
34 | #define IPGT 0x0c | |
35 | #define IPGR1 0x10 | |
36 | #define IPGR2 0x14 | |
37 | #define PACKETLEN 0x18 | |
38 | #define COLLCONF 0x1c | |
39 | #define TX_BD_NUM 0x20 | |
40 | #define CTRLMODER 0x24 | |
41 | #define MIIMODER 0x28 | |
42 | #define MIICOMMAND 0x2c | |
43 | #define MIIADDRESS 0x30 | |
44 | #define MIITX_DATA 0x34 | |
45 | #define MIIRX_DATA 0x38 | |
46 | #define MIISTATUS 0x3c | |
47 | #define MAC_ADDR0 0x40 | |
48 | #define MAC_ADDR1 0x44 | |
49 | #define ETH_HASH0 0x48 | |
50 | #define ETH_HASH1 0x4c | |
51 | #define ETH_TXCTRL 0x50 | |
52 | ||
53 | /* mode register */ | |
54 | #define MODER_RXEN (1 << 0) /* receive enable */ | |
55 | #define MODER_TXEN (1 << 1) /* transmit enable */ | |
56 | #define MODER_NOPRE (1 << 2) /* no preamble */ | |
57 | #define MODER_BRO (1 << 3) /* broadcast address */ | |
58 | #define MODER_IAM (1 << 4) /* individual address mode */ | |
59 | #define MODER_PRO (1 << 5) /* promiscuous mode */ | |
60 | #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */ | |
61 | #define MODER_LOOP (1 << 7) /* loopback */ | |
62 | #define MODER_NBO (1 << 8) /* no back-off */ | |
63 | #define MODER_EDE (1 << 9) /* excess defer enable */ | |
64 | #define MODER_FULLD (1 << 10) /* full duplex */ | |
65 | #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */ | |
66 | #define MODER_DCRC (1 << 12) /* delayed CRC enable */ | |
67 | #define MODER_CRC (1 << 13) /* CRC enable */ | |
68 | #define MODER_HUGE (1 << 14) /* huge packets enable */ | |
69 | #define MODER_PAD (1 << 15) /* padding enabled */ | |
70 | #define MODER_RSM (1 << 16) /* receive small packets */ | |
71 | ||
72 | /* interrupt source and mask registers */ | |
73 | #define INT_MASK_TXF (1 << 0) /* transmit frame */ | |
74 | #define INT_MASK_TXE (1 << 1) /* transmit error */ | |
75 | #define INT_MASK_RXF (1 << 2) /* receive frame */ | |
76 | #define INT_MASK_RXE (1 << 3) /* receive error */ | |
77 | #define INT_MASK_BUSY (1 << 4) | |
78 | #define INT_MASK_TXC (1 << 5) /* transmit control frame */ | |
79 | #define INT_MASK_RXC (1 << 6) /* receive control frame */ | |
80 | ||
81 | #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE) | |
82 | #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE) | |
83 | ||
84 | #define INT_MASK_ALL ( \ | |
85 | INT_MASK_TXF | INT_MASK_TXE | \ | |
86 | INT_MASK_RXF | INT_MASK_RXE | \ | |
87 | INT_MASK_TXC | INT_MASK_RXC | \ | |
88 | INT_MASK_BUSY \ | |
89 | ) | |
90 | ||
91 | /* packet length register */ | |
92 | #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16) | |
93 | #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0) | |
94 | #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \ | |
95 | PACKETLEN_MAX(max)) | |
96 | ||
97 | /* transmit buffer number register */ | |
98 | #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80) | |
99 | ||
100 | /* control module mode register */ | |
101 | #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */ | |
102 | #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */ | |
103 | #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */ | |
104 | ||
105 | /* MII mode register */ | |
106 | #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */ | |
107 | #define MIIMODER_NOPRE (1 << 8) /* no preamble */ | |
108 | ||
109 | /* MII command register */ | |
110 | #define MIICOMMAND_SCAN (1 << 0) /* scan status */ | |
111 | #define MIICOMMAND_READ (1 << 1) /* read status */ | |
112 | #define MIICOMMAND_WRITE (1 << 2) /* write control data */ | |
113 | ||
114 | /* MII address register */ | |
115 | #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0) | |
116 | #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8) | |
117 | #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \ | |
118 | MIIADDRESS_RGAD(reg)) | |
119 | ||
120 | /* MII transmit data register */ | |
121 | #define MIITX_DATA_VAL(x) ((x) & 0xffff) | |
122 | ||
123 | /* MII receive data register */ | |
124 | #define MIIRX_DATA_VAL(x) ((x) & 0xffff) | |
125 | ||
126 | /* MII status register */ | |
127 | #define MIISTATUS_LINKFAIL (1 << 0) | |
128 | #define MIISTATUS_BUSY (1 << 1) | |
129 | #define MIISTATUS_INVALID (1 << 2) | |
130 | ||
131 | /* TX buffer descriptor */ | |
132 | #define TX_BD_CS (1 << 0) /* carrier sense lost */ | |
133 | #define TX_BD_DF (1 << 1) /* defer indication */ | |
134 | #define TX_BD_LC (1 << 2) /* late collision */ | |
135 | #define TX_BD_RL (1 << 3) /* retransmission limit */ | |
136 | #define TX_BD_RETRY_MASK (0x00f0) | |
137 | #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4) | |
138 | #define TX_BD_UR (1 << 8) /* transmitter underrun */ | |
139 | #define TX_BD_CRC (1 << 11) /* TX CRC enable */ | |
140 | #define TX_BD_PAD (1 << 12) /* pad enable for short packets */ | |
141 | #define TX_BD_WRAP (1 << 13) | |
142 | #define TX_BD_IRQ (1 << 14) /* interrupt request enable */ | |
143 | #define TX_BD_READY (1 << 15) /* TX buffer ready */ | |
144 | #define TX_BD_LEN(x) (((x) & 0xffff) << 16) | |
145 | #define TX_BD_LEN_MASK (0xffff << 16) | |
146 | ||
147 | #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \ | |
148 | TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR) | |
149 | ||
150 | /* RX buffer descriptor */ | |
151 | #define RX_BD_LC (1 << 0) /* late collision */ | |
152 | #define RX_BD_CRC (1 << 1) /* RX CRC error */ | |
153 | #define RX_BD_SF (1 << 2) /* short frame */ | |
154 | #define RX_BD_TL (1 << 3) /* too long */ | |
155 | #define RX_BD_DN (1 << 4) /* dribble nibble */ | |
156 | #define RX_BD_IS (1 << 5) /* invalid symbol */ | |
157 | #define RX_BD_OR (1 << 6) /* receiver overrun */ | |
158 | #define RX_BD_MISS (1 << 7) | |
159 | #define RX_BD_CF (1 << 8) /* control frame */ | |
160 | #define RX_BD_WRAP (1 << 13) | |
161 | #define RX_BD_IRQ (1 << 14) /* interrupt request enable */ | |
162 | #define RX_BD_EMPTY (1 << 15) | |
163 | #define RX_BD_LEN(x) (((x) & 0xffff) << 16) | |
164 | ||
165 | #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \ | |
166 | RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS) | |
167 | ||
168 | #define ETHOC_BUFSIZ 1536 | |
169 | #define ETHOC_ZLEN 64 | |
170 | #define ETHOC_BD_BASE 0x400 | |
171 | #define ETHOC_TIMEOUT (HZ / 2) | |
172 | #define ETHOC_MII_TIMEOUT (1 + (HZ / 5)) | |
173 | ||
174 | /** | |
175 | * struct ethoc - driver-private device structure | |
176 | * @iobase: pointer to I/O memory region | |
177 | * @membase: pointer to buffer memory region | |
0baa080c | 178 | * @dma_alloc: dma allocated buffer size |
ee02a4ef | 179 | * @io_region_size: I/O memory region size |
a1702857 TR |
180 | * @num_tx: number of send buffers |
181 | * @cur_tx: last send buffer written | |
182 | * @dty_tx: last buffer actually sent | |
183 | * @num_rx: number of receive buffers | |
184 | * @cur_rx: current receive buffer | |
f8555ad0 | 185 | * @vma: pointer to array of virtual memory addresses for buffers |
a1702857 TR |
186 | * @netdev: pointer to network device structure |
187 | * @napi: NAPI structure | |
a1702857 | 188 | * @msg_enable: device state flags |
a1702857 TR |
189 | * @lock: device lock |
190 | * @phy: attached PHY | |
191 | * @mdio: MDIO bus for PHY access | |
192 | * @phy_id: address of attached PHY | |
193 | */ | |
194 | struct ethoc { | |
195 | void __iomem *iobase; | |
196 | void __iomem *membase; | |
0baa080c | 197 | int dma_alloc; |
ee02a4ef | 198 | resource_size_t io_region_size; |
a1702857 TR |
199 | |
200 | unsigned int num_tx; | |
201 | unsigned int cur_tx; | |
202 | unsigned int dty_tx; | |
203 | ||
204 | unsigned int num_rx; | |
205 | unsigned int cur_rx; | |
206 | ||
f8555ad0 JB |
207 | void** vma; |
208 | ||
a1702857 TR |
209 | struct net_device *netdev; |
210 | struct napi_struct napi; | |
a1702857 TR |
211 | u32 msg_enable; |
212 | ||
a1702857 TR |
213 | spinlock_t lock; |
214 | ||
215 | struct phy_device *phy; | |
216 | struct mii_bus *mdio; | |
217 | s8 phy_id; | |
218 | }; | |
219 | ||
220 | /** | |
221 | * struct ethoc_bd - buffer descriptor | |
222 | * @stat: buffer statistics | |
223 | * @addr: physical memory address | |
224 | */ | |
225 | struct ethoc_bd { | |
226 | u32 stat; | |
227 | u32 addr; | |
228 | }; | |
229 | ||
16dd18b0 | 230 | static inline u32 ethoc_read(struct ethoc *dev, loff_t offset) |
a1702857 TR |
231 | { |
232 | return ioread32(dev->iobase + offset); | |
233 | } | |
234 | ||
16dd18b0 | 235 | static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data) |
a1702857 TR |
236 | { |
237 | iowrite32(data, dev->iobase + offset); | |
238 | } | |
239 | ||
16dd18b0 TC |
240 | static inline void ethoc_read_bd(struct ethoc *dev, int index, |
241 | struct ethoc_bd *bd) | |
a1702857 TR |
242 | { |
243 | loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); | |
244 | bd->stat = ethoc_read(dev, offset + 0); | |
245 | bd->addr = ethoc_read(dev, offset + 4); | |
246 | } | |
247 | ||
16dd18b0 | 248 | static inline void ethoc_write_bd(struct ethoc *dev, int index, |
a1702857 TR |
249 | const struct ethoc_bd *bd) |
250 | { | |
251 | loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); | |
252 | ethoc_write(dev, offset + 0, bd->stat); | |
253 | ethoc_write(dev, offset + 4, bd->addr); | |
254 | } | |
255 | ||
16dd18b0 | 256 | static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask) |
a1702857 TR |
257 | { |
258 | u32 imask = ethoc_read(dev, INT_MASK); | |
259 | imask |= mask; | |
260 | ethoc_write(dev, INT_MASK, imask); | |
261 | } | |
262 | ||
16dd18b0 | 263 | static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask) |
a1702857 TR |
264 | { |
265 | u32 imask = ethoc_read(dev, INT_MASK); | |
266 | imask &= ~mask; | |
267 | ethoc_write(dev, INT_MASK, imask); | |
268 | } | |
269 | ||
16dd18b0 | 270 | static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask) |
a1702857 TR |
271 | { |
272 | ethoc_write(dev, INT_SOURCE, mask); | |
273 | } | |
274 | ||
16dd18b0 | 275 | static inline void ethoc_enable_rx_and_tx(struct ethoc *dev) |
a1702857 TR |
276 | { |
277 | u32 mode = ethoc_read(dev, MODER); | |
278 | mode |= MODER_RXEN | MODER_TXEN; | |
279 | ethoc_write(dev, MODER, mode); | |
280 | } | |
281 | ||
16dd18b0 | 282 | static inline void ethoc_disable_rx_and_tx(struct ethoc *dev) |
a1702857 TR |
283 | { |
284 | u32 mode = ethoc_read(dev, MODER); | |
285 | mode &= ~(MODER_RXEN | MODER_TXEN); | |
286 | ethoc_write(dev, MODER, mode); | |
287 | } | |
288 | ||
5cf3e034 | 289 | static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start) |
a1702857 TR |
290 | { |
291 | struct ethoc_bd bd; | |
292 | int i; | |
f8555ad0 | 293 | void* vma; |
a1702857 TR |
294 | |
295 | dev->cur_tx = 0; | |
296 | dev->dty_tx = 0; | |
297 | dev->cur_rx = 0; | |
298 | ||
ee4f56b9 JB |
299 | ethoc_write(dev, TX_BD_NUM, dev->num_tx); |
300 | ||
a1702857 | 301 | /* setup transmission buffers */ |
f8555ad0 | 302 | bd.addr = mem_start; |
a1702857 | 303 | bd.stat = TX_BD_IRQ | TX_BD_CRC; |
f8555ad0 | 304 | vma = dev->membase; |
a1702857 TR |
305 | |
306 | for (i = 0; i < dev->num_tx; i++) { | |
307 | if (i == dev->num_tx - 1) | |
308 | bd.stat |= TX_BD_WRAP; | |
309 | ||
310 | ethoc_write_bd(dev, i, &bd); | |
311 | bd.addr += ETHOC_BUFSIZ; | |
f8555ad0 JB |
312 | |
313 | dev->vma[i] = vma; | |
314 | vma += ETHOC_BUFSIZ; | |
a1702857 TR |
315 | } |
316 | ||
a1702857 TR |
317 | bd.stat = RX_BD_EMPTY | RX_BD_IRQ; |
318 | ||
319 | for (i = 0; i < dev->num_rx; i++) { | |
320 | if (i == dev->num_rx - 1) | |
321 | bd.stat |= RX_BD_WRAP; | |
322 | ||
323 | ethoc_write_bd(dev, dev->num_tx + i, &bd); | |
324 | bd.addr += ETHOC_BUFSIZ; | |
f8555ad0 JB |
325 | |
326 | dev->vma[dev->num_tx + i] = vma; | |
327 | vma += ETHOC_BUFSIZ; | |
a1702857 TR |
328 | } |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | static int ethoc_reset(struct ethoc *dev) | |
334 | { | |
335 | u32 mode; | |
336 | ||
337 | /* TODO: reset controller? */ | |
338 | ||
339 | ethoc_disable_rx_and_tx(dev); | |
340 | ||
341 | /* TODO: setup registers */ | |
342 | ||
343 | /* enable FCS generation and automatic padding */ | |
344 | mode = ethoc_read(dev, MODER); | |
345 | mode |= MODER_CRC | MODER_PAD; | |
346 | ethoc_write(dev, MODER, mode); | |
347 | ||
348 | /* set full-duplex mode */ | |
349 | mode = ethoc_read(dev, MODER); | |
350 | mode |= MODER_FULLD; | |
351 | ethoc_write(dev, MODER, mode); | |
352 | ethoc_write(dev, IPGT, 0x15); | |
353 | ||
354 | ethoc_ack_irq(dev, INT_MASK_ALL); | |
355 | ethoc_enable_irq(dev, INT_MASK_ALL); | |
356 | ethoc_enable_rx_and_tx(dev); | |
357 | return 0; | |
358 | } | |
359 | ||
360 | static unsigned int ethoc_update_rx_stats(struct ethoc *dev, | |
361 | struct ethoc_bd *bd) | |
362 | { | |
363 | struct net_device *netdev = dev->netdev; | |
364 | unsigned int ret = 0; | |
365 | ||
366 | if (bd->stat & RX_BD_TL) { | |
367 | dev_err(&netdev->dev, "RX: frame too long\n"); | |
57616ee4 | 368 | netdev->stats.rx_length_errors++; |
a1702857 TR |
369 | ret++; |
370 | } | |
371 | ||
372 | if (bd->stat & RX_BD_SF) { | |
373 | dev_err(&netdev->dev, "RX: frame too short\n"); | |
57616ee4 | 374 | netdev->stats.rx_length_errors++; |
a1702857 TR |
375 | ret++; |
376 | } | |
377 | ||
378 | if (bd->stat & RX_BD_DN) { | |
379 | dev_err(&netdev->dev, "RX: dribble nibble\n"); | |
57616ee4 | 380 | netdev->stats.rx_frame_errors++; |
a1702857 TR |
381 | } |
382 | ||
383 | if (bd->stat & RX_BD_CRC) { | |
384 | dev_err(&netdev->dev, "RX: wrong CRC\n"); | |
57616ee4 | 385 | netdev->stats.rx_crc_errors++; |
a1702857 TR |
386 | ret++; |
387 | } | |
388 | ||
389 | if (bd->stat & RX_BD_OR) { | |
390 | dev_err(&netdev->dev, "RX: overrun\n"); | |
57616ee4 | 391 | netdev->stats.rx_over_errors++; |
a1702857 TR |
392 | ret++; |
393 | } | |
394 | ||
395 | if (bd->stat & RX_BD_MISS) | |
57616ee4 | 396 | netdev->stats.rx_missed_errors++; |
a1702857 TR |
397 | |
398 | if (bd->stat & RX_BD_LC) { | |
399 | dev_err(&netdev->dev, "RX: late collision\n"); | |
57616ee4 | 400 | netdev->stats.collisions++; |
a1702857 TR |
401 | ret++; |
402 | } | |
403 | ||
404 | return ret; | |
405 | } | |
406 | ||
407 | static int ethoc_rx(struct net_device *dev, int limit) | |
408 | { | |
409 | struct ethoc *priv = netdev_priv(dev); | |
410 | int count; | |
411 | ||
412 | for (count = 0; count < limit; ++count) { | |
413 | unsigned int entry; | |
414 | struct ethoc_bd bd; | |
415 | ||
6a632625 | 416 | entry = priv->num_tx + priv->cur_rx; |
a1702857 | 417 | ethoc_read_bd(priv, entry, &bd); |
20f70ddd JB |
418 | if (bd.stat & RX_BD_EMPTY) { |
419 | ethoc_ack_irq(priv, INT_MASK_RX); | |
420 | /* If packet (interrupt) came in between checking | |
421 | * BD_EMTPY and clearing the interrupt source, then we | |
422 | * risk missing the packet as the RX interrupt won't | |
423 | * trigger right away when we reenable it; hence, check | |
424 | * BD_EMTPY here again to make sure there isn't such a | |
425 | * packet waiting for us... | |
426 | */ | |
427 | ethoc_read_bd(priv, entry, &bd); | |
428 | if (bd.stat & RX_BD_EMPTY) | |
429 | break; | |
430 | } | |
a1702857 TR |
431 | |
432 | if (ethoc_update_rx_stats(priv, &bd) == 0) { | |
433 | int size = bd.stat >> 16; | |
89d71a66 | 434 | struct sk_buff *skb; |
050f91dc TC |
435 | |
436 | size -= 4; /* strip the CRC */ | |
89d71a66 | 437 | skb = netdev_alloc_skb_ip_align(dev, size); |
050f91dc | 438 | |
a1702857 | 439 | if (likely(skb)) { |
f8555ad0 | 440 | void *src = priv->vma[entry]; |
a1702857 TR |
441 | memcpy_fromio(skb_put(skb, size), src, size); |
442 | skb->protocol = eth_type_trans(skb, dev); | |
57616ee4 KV |
443 | dev->stats.rx_packets++; |
444 | dev->stats.rx_bytes += size; | |
a1702857 TR |
445 | netif_receive_skb(skb); |
446 | } else { | |
447 | if (net_ratelimit()) | |
448 | dev_warn(&dev->dev, "low on memory - " | |
449 | "packet dropped\n"); | |
450 | ||
57616ee4 | 451 | dev->stats.rx_dropped++; |
a1702857 TR |
452 | break; |
453 | } | |
454 | } | |
455 | ||
456 | /* clear the buffer descriptor so it can be reused */ | |
457 | bd.stat &= ~RX_BD_STATS; | |
458 | bd.stat |= RX_BD_EMPTY; | |
459 | ethoc_write_bd(priv, entry, &bd); | |
6a632625 JB |
460 | if (++priv->cur_rx == priv->num_rx) |
461 | priv->cur_rx = 0; | |
a1702857 TR |
462 | } |
463 | ||
464 | return count; | |
465 | } | |
466 | ||
4f64bcb2 | 467 | static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd) |
a1702857 TR |
468 | { |
469 | struct net_device *netdev = dev->netdev; | |
470 | ||
471 | if (bd->stat & TX_BD_LC) { | |
472 | dev_err(&netdev->dev, "TX: late collision\n"); | |
57616ee4 | 473 | netdev->stats.tx_window_errors++; |
a1702857 TR |
474 | } |
475 | ||
476 | if (bd->stat & TX_BD_RL) { | |
477 | dev_err(&netdev->dev, "TX: retransmit limit\n"); | |
57616ee4 | 478 | netdev->stats.tx_aborted_errors++; |
a1702857 TR |
479 | } |
480 | ||
481 | if (bd->stat & TX_BD_UR) { | |
482 | dev_err(&netdev->dev, "TX: underrun\n"); | |
57616ee4 | 483 | netdev->stats.tx_fifo_errors++; |
a1702857 TR |
484 | } |
485 | ||
486 | if (bd->stat & TX_BD_CS) { | |
487 | dev_err(&netdev->dev, "TX: carrier sense lost\n"); | |
57616ee4 | 488 | netdev->stats.tx_carrier_errors++; |
a1702857 TR |
489 | } |
490 | ||
491 | if (bd->stat & TX_BD_STATS) | |
57616ee4 | 492 | netdev->stats.tx_errors++; |
a1702857 | 493 | |
57616ee4 KV |
494 | netdev->stats.collisions += (bd->stat >> 4) & 0xf; |
495 | netdev->stats.tx_bytes += bd->stat >> 16; | |
496 | netdev->stats.tx_packets++; | |
a1702857 TR |
497 | } |
498 | ||
fa98eb0e | 499 | static int ethoc_tx(struct net_device *dev, int limit) |
a1702857 TR |
500 | { |
501 | struct ethoc *priv = netdev_priv(dev); | |
fa98eb0e JB |
502 | int count; |
503 | struct ethoc_bd bd; | |
a1702857 | 504 | |
fa98eb0e JB |
505 | for (count = 0; count < limit; ++count) { |
506 | unsigned int entry; | |
a1702857 | 507 | |
6a632625 | 508 | entry = priv->dty_tx & (priv->num_tx-1); |
a1702857 TR |
509 | |
510 | ethoc_read_bd(priv, entry, &bd); | |
a1702857 | 511 | |
fa98eb0e JB |
512 | if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) { |
513 | ethoc_ack_irq(priv, INT_MASK_TX); | |
514 | /* If interrupt came in between reading in the BD | |
515 | * and clearing the interrupt source, then we risk | |
516 | * missing the event as the TX interrupt won't trigger | |
517 | * right away when we reenable it; hence, check | |
518 | * BD_EMPTY here again to make sure there isn't such an | |
519 | * event pending... | |
520 | */ | |
521 | ethoc_read_bd(priv, entry, &bd); | |
522 | if (bd.stat & TX_BD_READY || | |
523 | (priv->dty_tx == priv->cur_tx)) | |
524 | break; | |
525 | } | |
526 | ||
4f64bcb2 | 527 | ethoc_update_tx_stats(priv, &bd); |
fa98eb0e | 528 | priv->dty_tx++; |
a1702857 TR |
529 | } |
530 | ||
531 | if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2)) | |
532 | netif_wake_queue(dev); | |
533 | ||
fa98eb0e | 534 | return count; |
a1702857 TR |
535 | } |
536 | ||
537 | static irqreturn_t ethoc_interrupt(int irq, void *dev_id) | |
538 | { | |
57616ee4 | 539 | struct net_device *dev = dev_id; |
a1702857 TR |
540 | struct ethoc *priv = netdev_priv(dev); |
541 | u32 pending; | |
fa98eb0e JB |
542 | u32 mask; |
543 | ||
544 | /* Figure out what triggered the interrupt... | |
545 | * The tricky bit here is that the interrupt source bits get | |
25985edc | 546 | * set in INT_SOURCE for an event regardless of whether that |
fa98eb0e JB |
547 | * event is masked or not. Thus, in order to figure out what |
548 | * triggered the interrupt, we need to remove the sources | |
549 | * for all events that are currently masked. This behaviour | |
550 | * is not particularly well documented but reasonable... | |
551 | */ | |
552 | mask = ethoc_read(priv, INT_MASK); | |
a1702857 | 553 | pending = ethoc_read(priv, INT_SOURCE); |
fa98eb0e JB |
554 | pending &= mask; |
555 | ||
a1702857 | 556 | if (unlikely(pending == 0)) { |
a1702857 TR |
557 | return IRQ_NONE; |
558 | } | |
559 | ||
50c54a57 | 560 | ethoc_ack_irq(priv, pending); |
a1702857 | 561 | |
fa98eb0e | 562 | /* We always handle the dropped packet interrupt */ |
a1702857 TR |
563 | if (pending & INT_MASK_BUSY) { |
564 | dev_err(&dev->dev, "packet dropped\n"); | |
57616ee4 | 565 | dev->stats.rx_dropped++; |
a1702857 TR |
566 | } |
567 | ||
fa98eb0e JB |
568 | /* Handle receive/transmit event by switching to polling */ |
569 | if (pending & (INT_MASK_TX | INT_MASK_RX)) { | |
570 | ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX); | |
571 | napi_schedule(&priv->napi); | |
a1702857 TR |
572 | } |
573 | ||
a1702857 TR |
574 | return IRQ_HANDLED; |
575 | } | |
576 | ||
577 | static int ethoc_get_mac_address(struct net_device *dev, void *addr) | |
578 | { | |
579 | struct ethoc *priv = netdev_priv(dev); | |
580 | u8 *mac = (u8 *)addr; | |
581 | u32 reg; | |
582 | ||
583 | reg = ethoc_read(priv, MAC_ADDR0); | |
584 | mac[2] = (reg >> 24) & 0xff; | |
585 | mac[3] = (reg >> 16) & 0xff; | |
586 | mac[4] = (reg >> 8) & 0xff; | |
587 | mac[5] = (reg >> 0) & 0xff; | |
588 | ||
589 | reg = ethoc_read(priv, MAC_ADDR1); | |
590 | mac[0] = (reg >> 8) & 0xff; | |
591 | mac[1] = (reg >> 0) & 0xff; | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | static int ethoc_poll(struct napi_struct *napi, int budget) | |
597 | { | |
598 | struct ethoc *priv = container_of(napi, struct ethoc, napi); | |
fa98eb0e JB |
599 | int rx_work_done = 0; |
600 | int tx_work_done = 0; | |
601 | ||
602 | rx_work_done = ethoc_rx(priv->netdev, budget); | |
603 | tx_work_done = ethoc_tx(priv->netdev, budget); | |
a1702857 | 604 | |
fa98eb0e | 605 | if (rx_work_done < budget && tx_work_done < budget) { |
a1702857 | 606 | napi_complete(napi); |
fa98eb0e | 607 | ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX); |
a1702857 TR |
608 | } |
609 | ||
fa98eb0e | 610 | return rx_work_done; |
a1702857 TR |
611 | } |
612 | ||
613 | static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg) | |
614 | { | |
a1702857 | 615 | struct ethoc *priv = bus->priv; |
8dac428a | 616 | int i; |
a1702857 TR |
617 | |
618 | ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg)); | |
619 | ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ); | |
620 | ||
8dac428a | 621 | for (i=0; i < 5; i++) { |
a1702857 TR |
622 | u32 status = ethoc_read(priv, MIISTATUS); |
623 | if (!(status & MIISTATUS_BUSY)) { | |
624 | u32 data = ethoc_read(priv, MIIRX_DATA); | |
625 | /* reset MII command register */ | |
626 | ethoc_write(priv, MIICOMMAND, 0); | |
627 | return data; | |
628 | } | |
8dac428a | 629 | usleep_range(100,200); |
a1702857 TR |
630 | } |
631 | ||
632 | return -EBUSY; | |
633 | } | |
634 | ||
635 | static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) | |
636 | { | |
a1702857 | 637 | struct ethoc *priv = bus->priv; |
8dac428a | 638 | int i; |
a1702857 TR |
639 | |
640 | ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg)); | |
641 | ethoc_write(priv, MIITX_DATA, val); | |
642 | ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE); | |
643 | ||
8dac428a | 644 | for (i=0; i < 5; i++) { |
a1702857 | 645 | u32 stat = ethoc_read(priv, MIISTATUS); |
b46773db JB |
646 | if (!(stat & MIISTATUS_BUSY)) { |
647 | /* reset MII command register */ | |
648 | ethoc_write(priv, MIICOMMAND, 0); | |
a1702857 | 649 | return 0; |
b46773db | 650 | } |
8dac428a | 651 | usleep_range(100,200); |
a1702857 TR |
652 | } |
653 | ||
654 | return -EBUSY; | |
655 | } | |
656 | ||
657 | static int ethoc_mdio_reset(struct mii_bus *bus) | |
658 | { | |
659 | return 0; | |
660 | } | |
661 | ||
662 | static void ethoc_mdio_poll(struct net_device *dev) | |
663 | { | |
664 | } | |
665 | ||
f78f09f7 | 666 | static int __devinit ethoc_mdio_probe(struct net_device *dev) |
a1702857 TR |
667 | { |
668 | struct ethoc *priv = netdev_priv(dev); | |
669 | struct phy_device *phy; | |
637f33b8 | 670 | int err; |
a1702857 | 671 | |
637f33b8 JB |
672 | if (priv->phy_id != -1) { |
673 | phy = priv->mdio->phy_map[priv->phy_id]; | |
674 | } else { | |
675 | phy = phy_find_first(priv->mdio); | |
a1702857 TR |
676 | } |
677 | ||
678 | if (!phy) { | |
679 | dev_err(&dev->dev, "no PHY found\n"); | |
680 | return -ENXIO; | |
681 | } | |
682 | ||
637f33b8 | 683 | err = phy_connect_direct(dev, phy, ethoc_mdio_poll, 0, |
a1702857 | 684 | PHY_INTERFACE_MODE_GMII); |
637f33b8 | 685 | if (err) { |
a1702857 | 686 | dev_err(&dev->dev, "could not attach to PHY\n"); |
637f33b8 | 687 | return err; |
a1702857 TR |
688 | } |
689 | ||
690 | priv->phy = phy; | |
691 | return 0; | |
692 | } | |
693 | ||
694 | static int ethoc_open(struct net_device *dev) | |
695 | { | |
696 | struct ethoc *priv = netdev_priv(dev); | |
a1702857 TR |
697 | int ret; |
698 | ||
699 | ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED, | |
700 | dev->name, dev); | |
701 | if (ret) | |
702 | return ret; | |
703 | ||
5cf3e034 | 704 | ethoc_init_ring(priv, dev->mem_start); |
a1702857 TR |
705 | ethoc_reset(priv); |
706 | ||
707 | if (netif_queue_stopped(dev)) { | |
708 | dev_dbg(&dev->dev, " resuming queue\n"); | |
709 | netif_wake_queue(dev); | |
710 | } else { | |
711 | dev_dbg(&dev->dev, " starting queue\n"); | |
712 | netif_start_queue(dev); | |
713 | } | |
714 | ||
715 | phy_start(priv->phy); | |
716 | napi_enable(&priv->napi); | |
717 | ||
718 | if (netif_msg_ifup(priv)) { | |
719 | dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n", | |
720 | dev->base_addr, dev->mem_start, dev->mem_end); | |
721 | } | |
722 | ||
723 | return 0; | |
724 | } | |
725 | ||
726 | static int ethoc_stop(struct net_device *dev) | |
727 | { | |
728 | struct ethoc *priv = netdev_priv(dev); | |
729 | ||
730 | napi_disable(&priv->napi); | |
731 | ||
732 | if (priv->phy) | |
733 | phy_stop(priv->phy); | |
734 | ||
735 | ethoc_disable_rx_and_tx(priv); | |
736 | free_irq(dev->irq, dev); | |
737 | ||
738 | if (!netif_queue_stopped(dev)) | |
739 | netif_stop_queue(dev); | |
740 | ||
741 | return 0; | |
742 | } | |
743 | ||
744 | static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
745 | { | |
746 | struct ethoc *priv = netdev_priv(dev); | |
747 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
748 | struct phy_device *phy = NULL; | |
749 | ||
750 | if (!netif_running(dev)) | |
751 | return -EINVAL; | |
752 | ||
753 | if (cmd != SIOCGMIIPHY) { | |
754 | if (mdio->phy_id >= PHY_MAX_ADDR) | |
755 | return -ERANGE; | |
756 | ||
757 | phy = priv->mdio->phy_map[mdio->phy_id]; | |
758 | if (!phy) | |
759 | return -ENODEV; | |
760 | } else { | |
761 | phy = priv->phy; | |
762 | } | |
763 | ||
28b04113 | 764 | return phy_mii_ioctl(phy, ifr, cmd); |
a1702857 TR |
765 | } |
766 | ||
767 | static int ethoc_config(struct net_device *dev, struct ifmap *map) | |
768 | { | |
769 | return -ENOSYS; | |
770 | } | |
771 | ||
772 | static int ethoc_set_mac_address(struct net_device *dev, void *addr) | |
773 | { | |
774 | struct ethoc *priv = netdev_priv(dev); | |
775 | u8 *mac = (u8 *)addr; | |
776 | ||
777 | ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) | | |
778 | (mac[4] << 8) | (mac[5] << 0)); | |
779 | ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0)); | |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
784 | static void ethoc_set_multicast_list(struct net_device *dev) | |
785 | { | |
786 | struct ethoc *priv = netdev_priv(dev); | |
787 | u32 mode = ethoc_read(priv, MODER); | |
22bedad3 | 788 | struct netdev_hw_addr *ha; |
a1702857 TR |
789 | u32 hash[2] = { 0, 0 }; |
790 | ||
791 | /* set loopback mode if requested */ | |
792 | if (dev->flags & IFF_LOOPBACK) | |
793 | mode |= MODER_LOOP; | |
794 | else | |
795 | mode &= ~MODER_LOOP; | |
796 | ||
797 | /* receive broadcast frames if requested */ | |
798 | if (dev->flags & IFF_BROADCAST) | |
799 | mode &= ~MODER_BRO; | |
800 | else | |
801 | mode |= MODER_BRO; | |
802 | ||
803 | /* enable promiscuous mode if requested */ | |
804 | if (dev->flags & IFF_PROMISC) | |
805 | mode |= MODER_PRO; | |
806 | else | |
807 | mode &= ~MODER_PRO; | |
808 | ||
809 | ethoc_write(priv, MODER, mode); | |
810 | ||
811 | /* receive multicast frames */ | |
812 | if (dev->flags & IFF_ALLMULTI) { | |
813 | hash[0] = 0xffffffff; | |
814 | hash[1] = 0xffffffff; | |
815 | } else { | |
22bedad3 JP |
816 | netdev_for_each_mc_addr(ha, dev) { |
817 | u32 crc = ether_crc(ETH_ALEN, ha->addr); | |
a1702857 TR |
818 | int bit = (crc >> 26) & 0x3f; |
819 | hash[bit >> 5] |= 1 << (bit & 0x1f); | |
820 | } | |
821 | } | |
822 | ||
823 | ethoc_write(priv, ETH_HASH0, hash[0]); | |
824 | ethoc_write(priv, ETH_HASH1, hash[1]); | |
825 | } | |
826 | ||
827 | static int ethoc_change_mtu(struct net_device *dev, int new_mtu) | |
828 | { | |
829 | return -ENOSYS; | |
830 | } | |
831 | ||
832 | static void ethoc_tx_timeout(struct net_device *dev) | |
833 | { | |
834 | struct ethoc *priv = netdev_priv(dev); | |
835 | u32 pending = ethoc_read(priv, INT_SOURCE); | |
836 | if (likely(pending)) | |
837 | ethoc_interrupt(dev->irq, dev); | |
838 | } | |
839 | ||
61357325 | 840 | static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev) |
a1702857 TR |
841 | { |
842 | struct ethoc *priv = netdev_priv(dev); | |
843 | struct ethoc_bd bd; | |
844 | unsigned int entry; | |
845 | void *dest; | |
846 | ||
847 | if (unlikely(skb->len > ETHOC_BUFSIZ)) { | |
57616ee4 | 848 | dev->stats.tx_errors++; |
3790c8cd | 849 | goto out; |
a1702857 TR |
850 | } |
851 | ||
852 | entry = priv->cur_tx % priv->num_tx; | |
853 | spin_lock_irq(&priv->lock); | |
854 | priv->cur_tx++; | |
855 | ||
856 | ethoc_read_bd(priv, entry, &bd); | |
857 | if (unlikely(skb->len < ETHOC_ZLEN)) | |
858 | bd.stat |= TX_BD_PAD; | |
859 | else | |
860 | bd.stat &= ~TX_BD_PAD; | |
861 | ||
f8555ad0 | 862 | dest = priv->vma[entry]; |
a1702857 TR |
863 | memcpy_toio(dest, skb->data, skb->len); |
864 | ||
865 | bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK); | |
866 | bd.stat |= TX_BD_LEN(skb->len); | |
867 | ethoc_write_bd(priv, entry, &bd); | |
868 | ||
869 | bd.stat |= TX_BD_READY; | |
870 | ethoc_write_bd(priv, entry, &bd); | |
871 | ||
872 | if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) { | |
873 | dev_dbg(&dev->dev, "stopping queue\n"); | |
874 | netif_stop_queue(dev); | |
875 | } | |
876 | ||
a1702857 | 877 | spin_unlock_irq(&priv->lock); |
3790c8cd PM |
878 | out: |
879 | dev_kfree_skb(skb); | |
a1702857 TR |
880 | return NETDEV_TX_OK; |
881 | } | |
882 | ||
883 | static const struct net_device_ops ethoc_netdev_ops = { | |
884 | .ndo_open = ethoc_open, | |
885 | .ndo_stop = ethoc_stop, | |
886 | .ndo_do_ioctl = ethoc_ioctl, | |
887 | .ndo_set_config = ethoc_config, | |
888 | .ndo_set_mac_address = ethoc_set_mac_address, | |
889 | .ndo_set_multicast_list = ethoc_set_multicast_list, | |
890 | .ndo_change_mtu = ethoc_change_mtu, | |
891 | .ndo_tx_timeout = ethoc_tx_timeout, | |
a1702857 TR |
892 | .ndo_start_xmit = ethoc_start_xmit, |
893 | }; | |
894 | ||
895 | /** | |
896 | * ethoc_probe() - initialize OpenCores ethernet MAC | |
897 | * pdev: platform device | |
898 | */ | |
f78f09f7 | 899 | static int __devinit ethoc_probe(struct platform_device *pdev) |
a1702857 TR |
900 | { |
901 | struct net_device *netdev = NULL; | |
902 | struct resource *res = NULL; | |
903 | struct resource *mmio = NULL; | |
904 | struct resource *mem = NULL; | |
905 | struct ethoc *priv = NULL; | |
906 | unsigned int phy; | |
c527f814 | 907 | int num_bd; |
a1702857 TR |
908 | int ret = 0; |
909 | ||
910 | /* allocate networking device */ | |
911 | netdev = alloc_etherdev(sizeof(struct ethoc)); | |
912 | if (!netdev) { | |
913 | dev_err(&pdev->dev, "cannot allocate network device\n"); | |
914 | ret = -ENOMEM; | |
915 | goto out; | |
916 | } | |
917 | ||
918 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
919 | platform_set_drvdata(pdev, netdev); | |
920 | ||
921 | /* obtain I/O memory space */ | |
922 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
923 | if (!res) { | |
924 | dev_err(&pdev->dev, "cannot obtain I/O memory space\n"); | |
925 | ret = -ENXIO; | |
926 | goto free; | |
927 | } | |
928 | ||
929 | mmio = devm_request_mem_region(&pdev->dev, res->start, | |
d8645847 | 930 | resource_size(res), res->name); |
463889e2 | 931 | if (!mmio) { |
a1702857 TR |
932 | dev_err(&pdev->dev, "cannot request I/O memory space\n"); |
933 | ret = -ENXIO; | |
934 | goto free; | |
935 | } | |
936 | ||
937 | netdev->base_addr = mmio->start; | |
938 | ||
939 | /* obtain buffer memory space */ | |
940 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
0baa080c TC |
941 | if (res) { |
942 | mem = devm_request_mem_region(&pdev->dev, res->start, | |
d8645847 | 943 | resource_size(res), res->name); |
0baa080c TC |
944 | if (!mem) { |
945 | dev_err(&pdev->dev, "cannot request memory space\n"); | |
946 | ret = -ENXIO; | |
947 | goto free; | |
948 | } | |
949 | ||
950 | netdev->mem_start = mem->start; | |
951 | netdev->mem_end = mem->end; | |
a1702857 TR |
952 | } |
953 | ||
a1702857 TR |
954 | |
955 | /* obtain device IRQ number */ | |
956 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
957 | if (!res) { | |
958 | dev_err(&pdev->dev, "cannot obtain IRQ\n"); | |
959 | ret = -ENXIO; | |
960 | goto free; | |
961 | } | |
962 | ||
963 | netdev->irq = res->start; | |
964 | ||
965 | /* setup driver-private data */ | |
966 | priv = netdev_priv(netdev); | |
967 | priv->netdev = netdev; | |
0baa080c | 968 | priv->dma_alloc = 0; |
ee02a4ef | 969 | priv->io_region_size = mmio->end - mmio->start + 1; |
a1702857 TR |
970 | |
971 | priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr, | |
d8645847 | 972 | resource_size(mmio)); |
a1702857 TR |
973 | if (!priv->iobase) { |
974 | dev_err(&pdev->dev, "cannot remap I/O memory space\n"); | |
975 | ret = -ENXIO; | |
976 | goto error; | |
977 | } | |
978 | ||
0baa080c TC |
979 | if (netdev->mem_end) { |
980 | priv->membase = devm_ioremap_nocache(&pdev->dev, | |
d8645847 | 981 | netdev->mem_start, resource_size(mem)); |
0baa080c TC |
982 | if (!priv->membase) { |
983 | dev_err(&pdev->dev, "cannot remap memory space\n"); | |
984 | ret = -ENXIO; | |
985 | goto error; | |
986 | } | |
987 | } else { | |
988 | /* Allocate buffer memory */ | |
a71fba97 | 989 | priv->membase = dmam_alloc_coherent(&pdev->dev, |
0baa080c TC |
990 | buffer_size, (void *)&netdev->mem_start, |
991 | GFP_KERNEL); | |
992 | if (!priv->membase) { | |
993 | dev_err(&pdev->dev, "cannot allocate %dB buffer\n", | |
994 | buffer_size); | |
995 | ret = -ENOMEM; | |
996 | goto error; | |
997 | } | |
998 | netdev->mem_end = netdev->mem_start + buffer_size; | |
999 | priv->dma_alloc = buffer_size; | |
a1702857 TR |
1000 | } |
1001 | ||
c527f814 JB |
1002 | /* calculate the number of TX/RX buffers, maximum 128 supported */ |
1003 | num_bd = min_t(unsigned int, | |
1004 | 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ); | |
6a632625 JB |
1005 | if (num_bd < 4) { |
1006 | ret = -ENODEV; | |
1007 | goto error; | |
1008 | } | |
1009 | /* num_tx must be a power of two */ | |
1010 | priv->num_tx = rounddown_pow_of_two(num_bd >> 1); | |
c527f814 JB |
1011 | priv->num_rx = num_bd - priv->num_tx; |
1012 | ||
6a632625 JB |
1013 | dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n", |
1014 | priv->num_tx, priv->num_rx); | |
1015 | ||
f8555ad0 JB |
1016 | priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void*), GFP_KERNEL); |
1017 | if (!priv->vma) { | |
1018 | ret = -ENOMEM; | |
1019 | goto error; | |
1020 | } | |
1021 | ||
a1702857 TR |
1022 | /* Allow the platform setup code to pass in a MAC address. */ |
1023 | if (pdev->dev.platform_data) { | |
e0f4258b | 1024 | struct ethoc_platform_data *pdata = pdev->dev.platform_data; |
a1702857 TR |
1025 | memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN); |
1026 | priv->phy_id = pdata->phy_id; | |
e0f4258b JB |
1027 | } else { |
1028 | priv->phy_id = -1; | |
1029 | ||
1030 | #ifdef CONFIG_OF | |
1031 | { | |
1032 | const uint8_t* mac; | |
1033 | ||
1034 | mac = of_get_property(pdev->dev.of_node, | |
1035 | "local-mac-address", | |
1036 | NULL); | |
1037 | if (mac) | |
1038 | memcpy(netdev->dev_addr, mac, IFHWADDRLEN); | |
1039 | } | |
1040 | #endif | |
a1702857 TR |
1041 | } |
1042 | ||
1043 | /* Check that the given MAC address is valid. If it isn't, read the | |
1044 | * current MAC from the controller. */ | |
1045 | if (!is_valid_ether_addr(netdev->dev_addr)) | |
1046 | ethoc_get_mac_address(netdev, netdev->dev_addr); | |
1047 | ||
1048 | /* Check the MAC again for validity, if it still isn't choose and | |
1049 | * program a random one. */ | |
1050 | if (!is_valid_ether_addr(netdev->dev_addr)) | |
1051 | random_ether_addr(netdev->dev_addr); | |
1052 | ||
1053 | ethoc_set_mac_address(netdev, netdev->dev_addr); | |
1054 | ||
1055 | /* register MII bus */ | |
1056 | priv->mdio = mdiobus_alloc(); | |
1057 | if (!priv->mdio) { | |
1058 | ret = -ENOMEM; | |
1059 | goto free; | |
1060 | } | |
1061 | ||
1062 | priv->mdio->name = "ethoc-mdio"; | |
1063 | snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d", | |
1064 | priv->mdio->name, pdev->id); | |
1065 | priv->mdio->read = ethoc_mdio_read; | |
1066 | priv->mdio->write = ethoc_mdio_write; | |
1067 | priv->mdio->reset = ethoc_mdio_reset; | |
1068 | priv->mdio->priv = priv; | |
1069 | ||
1070 | priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
1071 | if (!priv->mdio->irq) { | |
1072 | ret = -ENOMEM; | |
1073 | goto free_mdio; | |
1074 | } | |
1075 | ||
1076 | for (phy = 0; phy < PHY_MAX_ADDR; phy++) | |
1077 | priv->mdio->irq[phy] = PHY_POLL; | |
1078 | ||
1079 | ret = mdiobus_register(priv->mdio); | |
1080 | if (ret) { | |
1081 | dev_err(&netdev->dev, "failed to register MDIO bus\n"); | |
1082 | goto free_mdio; | |
1083 | } | |
1084 | ||
1085 | ret = ethoc_mdio_probe(netdev); | |
1086 | if (ret) { | |
1087 | dev_err(&netdev->dev, "failed to probe MDIO bus\n"); | |
1088 | goto error; | |
1089 | } | |
1090 | ||
1091 | ether_setup(netdev); | |
1092 | ||
1093 | /* setup the net_device structure */ | |
1094 | netdev->netdev_ops = ðoc_netdev_ops; | |
1095 | netdev->watchdog_timeo = ETHOC_TIMEOUT; | |
1096 | netdev->features |= 0; | |
1097 | ||
1098 | /* setup NAPI */ | |
a1702857 TR |
1099 | netif_napi_add(netdev, &priv->napi, ethoc_poll, 64); |
1100 | ||
a1702857 TR |
1101 | spin_lock_init(&priv->lock); |
1102 | ||
1103 | ret = register_netdev(netdev); | |
1104 | if (ret < 0) { | |
1105 | dev_err(&netdev->dev, "failed to register interface\n"); | |
ee02a4ef | 1106 | goto error2; |
a1702857 TR |
1107 | } |
1108 | ||
1109 | goto out; | |
1110 | ||
ee02a4ef TC |
1111 | error2: |
1112 | netif_napi_del(&priv->napi); | |
a1702857 TR |
1113 | error: |
1114 | mdiobus_unregister(priv->mdio); | |
1115 | free_mdio: | |
1116 | kfree(priv->mdio->irq); | |
1117 | mdiobus_free(priv->mdio); | |
1118 | free: | |
1119 | free_netdev(netdev); | |
1120 | out: | |
1121 | return ret; | |
1122 | } | |
1123 | ||
1124 | /** | |
1125 | * ethoc_remove() - shutdown OpenCores ethernet MAC | |
1126 | * @pdev: platform device | |
1127 | */ | |
f78f09f7 | 1128 | static int __devexit ethoc_remove(struct platform_device *pdev) |
a1702857 TR |
1129 | { |
1130 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1131 | struct ethoc *priv = netdev_priv(netdev); | |
1132 | ||
1133 | platform_set_drvdata(pdev, NULL); | |
1134 | ||
1135 | if (netdev) { | |
ee02a4ef | 1136 | netif_napi_del(&priv->napi); |
a1702857 TR |
1137 | phy_disconnect(priv->phy); |
1138 | priv->phy = NULL; | |
1139 | ||
1140 | if (priv->mdio) { | |
1141 | mdiobus_unregister(priv->mdio); | |
1142 | kfree(priv->mdio->irq); | |
1143 | mdiobus_free(priv->mdio); | |
1144 | } | |
a1702857 TR |
1145 | unregister_netdev(netdev); |
1146 | free_netdev(netdev); | |
1147 | } | |
1148 | ||
1149 | return 0; | |
1150 | } | |
1151 | ||
1152 | #ifdef CONFIG_PM | |
1153 | static int ethoc_suspend(struct platform_device *pdev, pm_message_t state) | |
1154 | { | |
1155 | return -ENOSYS; | |
1156 | } | |
1157 | ||
1158 | static int ethoc_resume(struct platform_device *pdev) | |
1159 | { | |
1160 | return -ENOSYS; | |
1161 | } | |
1162 | #else | |
1163 | # define ethoc_suspend NULL | |
1164 | # define ethoc_resume NULL | |
1165 | #endif | |
1166 | ||
e0f4258b | 1167 | static struct of_device_id ethoc_match[] = { |
c9e358df | 1168 | { .compatible = "opencores,ethoc", }, |
e0f4258b JB |
1169 | {}, |
1170 | }; | |
1171 | MODULE_DEVICE_TABLE(of, ethoc_match); | |
e0f4258b | 1172 | |
a1702857 TR |
1173 | static struct platform_driver ethoc_driver = { |
1174 | .probe = ethoc_probe, | |
f78f09f7 | 1175 | .remove = __devexit_p(ethoc_remove), |
a1702857 TR |
1176 | .suspend = ethoc_suspend, |
1177 | .resume = ethoc_resume, | |
1178 | .driver = { | |
1179 | .name = "ethoc", | |
e0f4258b | 1180 | .owner = THIS_MODULE, |
e0f4258b | 1181 | .of_match_table = ethoc_match, |
a1702857 TR |
1182 | }, |
1183 | }; | |
1184 | ||
1185 | static int __init ethoc_init(void) | |
1186 | { | |
1187 | return platform_driver_register(ðoc_driver); | |
1188 | } | |
1189 | ||
1190 | static void __exit ethoc_exit(void) | |
1191 | { | |
1192 | platform_driver_unregister(ðoc_driver); | |
1193 | } | |
1194 | ||
1195 | module_init(ethoc_init); | |
1196 | module_exit(ethoc_exit); | |
1197 | ||
1198 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); | |
1199 | MODULE_DESCRIPTION("OpenCores Ethernet MAC driver"); | |
1200 | MODULE_LICENSE("GPL v2"); | |
1201 |