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fealnx: Write outside array bounds
[deliverable/linux.git] / drivers / net / fealnx.c
CommitLineData
1da177e4
LT		 1/*
2 Written 1998-2000 by Donald Becker.
3
4 This software may be used and distributed according to the terms of
5 the GNU General Public License (GPL), incorporated herein by reference.
6 Drivers based on or derived from this code fall under the GPL and must
7 retain the authorship, copyright and license notice. This file is not
8 a complete program and may only be used when the entire operating
9 system is licensed under the GPL.
10
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
14 Annapolis MD 21403
15
16 Support information and updates available at
17 http://www.scyld.com/network/pci-skeleton.html
18
19 Linux kernel updates:
20
21 Version 2.51, Nov 17, 2001 (jgarzik):
22 - Add ethtool support
23 - Replace some MII-related magic numbers with constants
24
25*/
26
27#define DRV_NAME "fealnx"
d5b20697
AG		 28#define DRV_VERSION "2.52"
29#define DRV_RELDATE "Sep-11-2006"
1da177e4
LT		 30
31static int debug; /* 1-> print debug message */
32static int max_interrupt_work = 20;
33
34/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
35static int multicast_filter_limit = 32;
36
37/* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
38/* Setting to > 1518 effectively disables this feature. */
39static int rx_copybreak;
40
41/* Used to pass the media type, etc. */
42/* Both 'options[]' and 'full_duplex[]' should exist for driver */
43/* interoperability. */
44/* The media type is usually passed in 'options[]'. */
45#define MAX_UNITS 8 /* More are supported, limit only on options */
46static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
47static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
48
49/* Operational parameters that are set at compile time. */
50/* Keep the ring sizes a power of two for compile efficiency. */
51/* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */
52/* Making the Tx ring too large decreases the effectiveness of channel */
53/* bonding and packet priority. */
54/* There are no ill effects from too-large receive rings. */
55// 88-12-9 modify,
56// #define TX_RING_SIZE 16
57// #define RX_RING_SIZE 32
58#define TX_RING_SIZE 6
59#define RX_RING_SIZE 12
60#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc)
61#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc)
62
63/* Operational parameters that usually are not changed. */
64/* Time in jiffies before concluding the transmitter is hung. */
65#define TX_TIMEOUT (2*HZ)
66
67#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
68
69
70/* Include files, designed to support most kernel versions 2.0.0 and later. */
71#include <linux/module.h>
72#include <linux/kernel.h>
73#include <linux/string.h>
74#include <linux/timer.h>
75#include <linux/errno.h>
76#include <linux/ioport.h>
77#include <linux/slab.h>
78#include <linux/interrupt.h>
79#include <linux/pci.h>
80#include <linux/netdevice.h>
81#include <linux/etherdevice.h>
82#include <linux/skbuff.h>
83#include <linux/init.h>
84#include <linux/mii.h>
85#include <linux/ethtool.h>
86#include <linux/crc32.h>
87#include <linux/delay.h>
88#include <linux/bitops.h>
89
90#include <asm/processor.h> /* Processor type for cache alignment. */
91#include <asm/io.h>
92#include <asm/uaccess.h>
28cd4289 93#include <asm/byteorder.h>
1da177e4
LT		 94
95/* These identify the driver base version and may not be removed. */
6f101d19
SH		 96static const char version[] __devinitconst =
97 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
1da177e4
LT		 98
99
100/* This driver was written to use PCI memory space, however some x86 systems
101 work only with I/O space accesses. */
102#ifndef __alpha__
103#define USE_IO_OPS
104#endif
105
106/* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
107/* This is only in the support-all-kernels source code. */
108
109#define RUN_AT(x) (jiffies + (x))
110
111MODULE_AUTHOR("Myson or whoever");
112MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
113MODULE_LICENSE("GPL");
114module_param(max_interrupt_work, int, 0);
1da177e4
LT		 115module_param(debug, int, 0);
116module_param(rx_copybreak, int, 0);
117module_param(multicast_filter_limit, int, 0);
118module_param_array(options, int, NULL, 0);
119module_param_array(full_duplex, int, NULL, 0);
120MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
121MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
122MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
123MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
124MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
125MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
126
46009c8b
JG		 127enum {
128 MIN_REGION_SIZE = 136,
129};
1da177e4 130
1da177e4
LT		 131/* A chip capabilities table, matching the entries in pci_tbl[] above. */
132enum chip_capability_flags {
133 HAS_MII_XCVR,
134 HAS_CHIP_XCVR,
135};
136
137/* 89/6/13 add, */
138/* for different PHY */
139enum phy_type_flags {
140 MysonPHY = 1,
141 AhdocPHY = 2,
142 SeeqPHY = 3,
143 MarvellPHY = 4,
144 Myson981 = 5,
145 LevelOnePHY = 6,
146 OtherPHY = 10,
147};
148
149struct chip_info {
150 char *chip_name;
1da177e4
LT		 151 int flags;
152};
153
46009c8b 154static const struct chip_info skel_netdrv_tbl[] __devinitdata = {
c3d8e682
JG		 155 { "100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
156 { "100/10M Ethernet PCI Adapter", HAS_CHIP_XCVR },
157 { "1000/100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
1da177e4
LT		 158};
159
160/* Offsets to the Command and Status Registers. */
161enum fealnx_offsets {
162 PAR0 = 0x0, /* physical address 0-3 */
163 PAR1 = 0x04, /* physical address 4-5 */
164 MAR0 = 0x08, /* multicast address 0-3 */
165 MAR1 = 0x0C, /* multicast address 4-7 */
166 FAR0 = 0x10, /* flow-control address 0-3 */
167 FAR1 = 0x14, /* flow-control address 4-5 */
168 TCRRCR = 0x18, /* receive & transmit configuration */
169 BCR = 0x1C, /* bus command */
170 TXPDR = 0x20, /* transmit polling demand */
171 RXPDR = 0x24, /* receive polling demand */
172 RXCWP = 0x28, /* receive current word pointer */
173 TXLBA = 0x2C, /* transmit list base address */
174 RXLBA = 0x30, /* receive list base address */
175 ISR = 0x34, /* interrupt status */
176 IMR = 0x38, /* interrupt mask */
177 FTH = 0x3C, /* flow control high/low threshold */
178 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */
179 TALLY = 0x44, /* tally counters for crc and mpa */
180 TSR = 0x48, /* tally counter for transmit status */
181 BMCRSR = 0x4c, /* basic mode control and status */
182 PHYIDENTIFIER = 0x50, /* phy identifier */
183 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link
184 partner ability */
185 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */
186 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */
187};
188
189/* Bits in the interrupt status/enable registers. */
190/* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
191enum intr_status_bits {
192 RFCON = 0x00020000, /* receive flow control xon packet */
193 RFCOFF = 0x00010000, /* receive flow control xoff packet */
194 LSCStatus = 0x00008000, /* link status change */
195 ANCStatus = 0x00004000, /* autonegotiation completed */
196 FBE = 0x00002000, /* fatal bus error */
197 FBEMask = 0x00001800, /* mask bit12-11 */
198 ParityErr = 0x00000000, /* parity error */
199 TargetErr = 0x00001000, /* target abort */
200 MasterErr = 0x00000800, /* master error */
201 TUNF = 0x00000400, /* transmit underflow */
202 ROVF = 0x00000200, /* receive overflow */
203 ETI = 0x00000100, /* transmit early int */
204 ERI = 0x00000080, /* receive early int */
205 CNTOVF = 0x00000040, /* counter overflow */
206 RBU = 0x00000020, /* receive buffer unavailable */
207 TBU = 0x00000010, /* transmit buffer unavilable */
208 TI = 0x00000008, /* transmit interrupt */
209 RI = 0x00000004, /* receive interrupt */
210 RxErr = 0x00000002, /* receive error */
211};
212
213/* Bits in the NetworkConfig register, W for writing, R for reading */
214/* FIXME: some names are invented by me. Marked with (name?) */
215/* If you have docs and know bit names, please fix 'em */
216enum rx_mode_bits {
217 CR_W_ENH = 0x02000000, /* enhanced mode (name?) */
218 CR_W_FD = 0x00100000, /* full duplex */
219 CR_W_PS10 = 0x00080000, /* 10 mbit */
220 CR_W_TXEN = 0x00040000, /* tx enable (name?) */
221 CR_W_PS1000 = 0x00010000, /* 1000 mbit */
222 /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */
223 CR_W_RXMODEMASK = 0x000000e0,
224 CR_W_PROM = 0x00000080, /* promiscuous mode */
225 CR_W_AB = 0x00000040, /* accept broadcast */
226 CR_W_AM = 0x00000020, /* accept mutlicast */
227 CR_W_ARP = 0x00000008, /* receive runt pkt */
228 CR_W_ALP = 0x00000004, /* receive long pkt */
229 CR_W_SEP = 0x00000002, /* receive error pkt */
230 CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */
231
232 CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */
233 CR_R_FD = 0x00100000, /* full duplex detected */
234 CR_R_PS10 = 0x00080000, /* 10 mbit detected */
235 CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */
236};
237
238/* The Tulip Rx and Tx buffer descriptors. */
239struct fealnx_desc {
240 s32 status;
241 s32 control;
242 u32 buffer;
243 u32 next_desc;
244 struct fealnx_desc *next_desc_logical;
245 struct sk_buff *skbuff;
246 u32 reserved1;
247 u32 reserved2;
248};
249
250/* Bits in network_desc.status */
251enum rx_desc_status_bits {
252 RXOWN = 0x80000000, /* own bit */
253 FLNGMASK = 0x0fff0000, /* frame length */
254 FLNGShift = 16,
255 MARSTATUS = 0x00004000, /* multicast address received */
256 BARSTATUS = 0x00002000, /* broadcast address received */
257 PHYSTATUS = 0x00001000, /* physical address received */
258 RXFSD = 0x00000800, /* first descriptor */
259 RXLSD = 0x00000400, /* last descriptor */
260 ErrorSummary = 0x80, /* error summary */
261 RUNT = 0x40, /* runt packet received */
262 LONG = 0x20, /* long packet received */
263 FAE = 0x10, /* frame align error */
264 CRC = 0x08, /* crc error */
265 RXER = 0x04, /* receive error */
266};
267
268enum rx_desc_control_bits {
269 RXIC = 0x00800000, /* interrupt control */
270 RBSShift = 0,
271};
272
273enum tx_desc_status_bits {
274 TXOWN = 0x80000000, /* own bit */
275 JABTO = 0x00004000, /* jabber timeout */
276 CSL = 0x00002000, /* carrier sense lost */
277 LC = 0x00001000, /* late collision */
278 EC = 0x00000800, /* excessive collision */
279 UDF = 0x00000400, /* fifo underflow */
280 DFR = 0x00000200, /* deferred */
281 HF = 0x00000100, /* heartbeat fail */
282 NCRMask = 0x000000ff, /* collision retry count */
283 NCRShift = 0,
284};
285
286enum tx_desc_control_bits {
287 TXIC = 0x80000000, /* interrupt control */
288 ETIControl = 0x40000000, /* early transmit interrupt */
289 TXLD = 0x20000000, /* last descriptor */
290 TXFD = 0x10000000, /* first descriptor */
291 CRCEnable = 0x08000000, /* crc control */
292 PADEnable = 0x04000000, /* padding control */
293 RetryTxLC = 0x02000000, /* retry late collision */
294 PKTSMask = 0x3ff800, /* packet size bit21-11 */
295 PKTSShift = 11,
296 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */
297 TBSShift = 0,
298};
299
300/* BootROM/EEPROM/MII Management Register */
301#define MASK_MIIR_MII_READ 0x00000000
302#define MASK_MIIR_MII_WRITE 0x00000008
303#define MASK_MIIR_MII_MDO 0x00000004
304#define MASK_MIIR_MII_MDI 0x00000002
305#define MASK_MIIR_MII_MDC 0x00000001
306
307/* ST+OP+PHYAD+REGAD+TA */
308#define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
309#define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
310
311/* ------------------------------------------------------------------------- */
312/* Constants for Myson PHY */
313/* ------------------------------------------------------------------------- */
314#define MysonPHYID 0xd0000302
315/* 89-7-27 add, (begin) */
316#define MysonPHYID0 0x0302
317#define StatusRegister 18
318#define SPEED100 0x0400 // bit10
319#define FULLMODE 0x0800 // bit11
320/* 89-7-27 add, (end) */
321
322/* ------------------------------------------------------------------------- */
323/* Constants for Seeq 80225 PHY */
324/* ------------------------------------------------------------------------- */
325#define SeeqPHYID0 0x0016
326
327#define MIIRegister18 18
328#define SPD_DET_100 0x80
329#define DPLX_DET_FULL 0x40
330
331/* ------------------------------------------------------------------------- */
332/* Constants for Ahdoc 101 PHY */
333/* ------------------------------------------------------------------------- */
334#define AhdocPHYID0 0x0022
335
336#define DiagnosticReg 18
337#define DPLX_FULL 0x0800
338#define Speed_100 0x0400
339
340/* 89/6/13 add, */
341/* -------------------------------------------------------------------------- */
342/* Constants */
343/* -------------------------------------------------------------------------- */
344#define MarvellPHYID0 0x0141
345#define LevelOnePHYID0 0x0013
346
347#define MII1000BaseTControlReg 9
348#define MII1000BaseTStatusReg 10
349#define SpecificReg 17
350
351/* for 1000BaseT Control Register */
352#define PHYAbletoPerform1000FullDuplex 0x0200
353#define PHYAbletoPerform1000HalfDuplex 0x0100
354#define PHY1000AbilityMask 0x300
355
356// for phy specific status register, marvell phy.
357#define SpeedMask 0x0c000
358#define Speed_1000M 0x08000
359#define Speed_100M 0x4000
360#define Speed_10M 0
361#define Full_Duplex 0x2000
362
363// 89/12/29 add, for phy specific status register, levelone phy, (begin)
364#define LXT1000_100M 0x08000
365#define LXT1000_1000M 0x0c000
366#define LXT1000_Full 0x200
367// 89/12/29 add, for phy specific status register, levelone phy, (end)
368
369/* for 3-in-1 case, BMCRSR register */
370#define LinkIsUp2 0x00040000
371
372/* for PHY */
373#define LinkIsUp 0x0004
374
375
376struct netdev_private {
377 /* Descriptor rings first for alignment. */
378 struct fealnx_desc *rx_ring;
379 struct fealnx_desc *tx_ring;
380
381 dma_addr_t rx_ring_dma;
382 dma_addr_t tx_ring_dma;
383
384 spinlock_t lock;
385
386 struct net_device_stats stats;
387
388 /* Media monitoring timer. */
389 struct timer_list timer;
390
391 /* Reset timer */
392 struct timer_list reset_timer;
393 int reset_timer_armed;
394 unsigned long crvalue_sv;
395 unsigned long imrvalue_sv;
396
397 /* Frequently used values: keep some adjacent for cache effect. */
398 int flags;
399 struct pci_dev *pci_dev;
400 unsigned long crvalue;
401 unsigned long bcrvalue;
402 unsigned long imrvalue;
403 struct fealnx_desc *cur_rx;
404 struct fealnx_desc *lack_rxbuf;
405 int really_rx_count;
406 struct fealnx_desc *cur_tx;
407 struct fealnx_desc *cur_tx_copy;
408 int really_tx_count;
409 int free_tx_count;
410 unsigned int rx_buf_sz; /* Based on MTU+slack. */
411
412 /* These values are keep track of the transceiver/media in use. */
413 unsigned int linkok;
414 unsigned int line_speed;
415 unsigned int duplexmode;
416 unsigned int default_port:4; /* Last dev->if_port value. */
417 unsigned int PHYType;
418
419 /* MII transceiver section. */
420 int mii_cnt; /* MII device addresses. */
421 unsigned char phys[2]; /* MII device addresses. */
422 struct mii_if_info mii;
423 void __iomem *mem;
424};
425
426
427static int mdio_read(struct net_device *dev, int phy_id, int location);
428static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
429static int netdev_open(struct net_device *dev);
430static void getlinktype(struct net_device *dev);
431static void getlinkstatus(struct net_device *dev);
432static void netdev_timer(unsigned long data);
433static void reset_timer(unsigned long data);
ed4cb133 434static void fealnx_tx_timeout(struct net_device *dev);
1da177e4
LT		 435static void init_ring(struct net_device *dev);
436static int start_tx(struct sk_buff *skb, struct net_device *dev);
7d12e780 437static irqreturn_t intr_handler(int irq, void *dev_instance);
1da177e4
LT		 438static int netdev_rx(struct net_device *dev);
439static void set_rx_mode(struct net_device *dev);
440static void __set_rx_mode(struct net_device *dev);
441static struct net_device_stats *get_stats(struct net_device *dev);
442static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
7282d491 443static const struct ethtool_ops netdev_ethtool_ops;
1da177e4
LT		 444static int netdev_close(struct net_device *dev);
445static void reset_rx_descriptors(struct net_device *dev);
446static void reset_tx_descriptors(struct net_device *dev);
447
448static void stop_nic_rx(void __iomem *ioaddr, long crvalue)
449{
450 int delay = 0x1000;
451 iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
452 while (--delay) {
453 if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
454 break;
455 }
456}
457
458
459static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue)
460{
461 int delay = 0x1000;
462 iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
463 while (--delay) {
464 if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
465 == (CR_R_RXSTOP+CR_R_TXSTOP) )
466 break;
467 }
468}
469
e287157f
SH		 470static const struct net_device_ops netdev_ops = {
471 .ndo_open = netdev_open,
472 .ndo_stop = netdev_close,
473 .ndo_start_xmit = start_tx,
474 .ndo_get_stats = get_stats,
475 .ndo_set_multicast_list = set_rx_mode,
476 .ndo_do_ioctl = mii_ioctl,
477 .ndo_tx_timeout = fealnx_tx_timeout,
478 .ndo_change_mtu = eth_change_mtu,
479 .ndo_set_mac_address = eth_mac_addr,
480 .ndo_validate_addr = eth_validate_addr,
481};
1da177e4
LT		 482
483static int __devinit fealnx_init_one(struct pci_dev *pdev,
484 const struct pci_device_id *ent)
485{
486 struct netdev_private *np;
487 int i, option, err, irq;
488 static int card_idx = -1;
489 char boardname[12];
490 void __iomem *ioaddr;
491 unsigned long len;
492 unsigned int chip_id = ent->driver_data;
493 struct net_device *dev;
494 void *ring_space;
495 dma_addr_t ring_dma;
496#ifdef USE_IO_OPS
497 int bar = 0;
498#else
499 int bar = 1;
500#endif
6aa20a22 501
1da177e4
LT		 502/* when built into the kernel, we only print version if device is found */
503#ifndef MODULE
504 static int printed_version;
505 if (!printed_version++)
506 printk(version);
507#endif
6aa20a22 508
1da177e4
LT		 509 card_idx++;
510 sprintf(boardname, "fealnx%d", card_idx);
6aa20a22 511
1da177e4
LT		 512 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
513
514 i = pci_enable_device(pdev);
515 if (i) return i;
516 pci_set_master(pdev);
6aa20a22 517
1da177e4
LT		 518 len = pci_resource_len(pdev, bar);
519 if (len < MIN_REGION_SIZE) {
9b91cf9d 520 dev_err(&pdev->dev,
46009c8b 521 "region size %ld too small, aborting\n", len);
1da177e4
LT		 522 return -ENODEV;
523 }
524
525 i = pci_request_regions(pdev, boardname);
46009c8b
JG		 526 if (i)
527 return i;
6aa20a22 528
1da177e4
LT		 529 irq = pdev->irq;
530
531 ioaddr = pci_iomap(pdev, bar, len);
532 if (!ioaddr) {
533 err = -ENOMEM;
534 goto err_out_res;
535 }
536
537 dev = alloc_etherdev(sizeof(struct netdev_private));
538 if (!dev) {
539 err = -ENOMEM;
540 goto err_out_unmap;
541 }
1da177e4
LT		 542 SET_NETDEV_DEV(dev, &pdev->dev);
543
544 /* read ethernet id */
545 for (i = 0; i < 6; ++i)
546 dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i);
547
548 /* Reset the chip to erase previous misconfiguration. */
549 iowrite32(0x00000001, ioaddr + BCR);
550
551 dev->base_addr = (unsigned long)ioaddr;
552 dev->irq = irq;
553
554 /* Make certain the descriptor lists are aligned. */
555 np = netdev_priv(dev);
556 np->mem = ioaddr;
557 spin_lock_init(&np->lock);
558 np->pci_dev = pdev;
559 np->flags = skel_netdrv_tbl[chip_id].flags;
560 pci_set_drvdata(pdev, dev);
561 np->mii.dev = dev;
562 np->mii.mdio_read = mdio_read;
563 np->mii.mdio_write = mdio_write;
564 np->mii.phy_id_mask = 0x1f;
565 np->mii.reg_num_mask = 0x1f;
566
567 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
568 if (!ring_space) {
569 err = -ENOMEM;
570 goto err_out_free_dev;
571 }
572 np->rx_ring = (struct fealnx_desc *)ring_space;
573 np->rx_ring_dma = ring_dma;
574
575 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
576 if (!ring_space) {
577 err = -ENOMEM;
578 goto err_out_free_rx;
579 }
580 np->tx_ring = (struct fealnx_desc *)ring_space;
581 np->tx_ring_dma = ring_dma;
582
583 /* find the connected MII xcvrs */
584 if (np->flags == HAS_MII_XCVR) {
585 int phy, phy_idx = 0;
586
f83284fe 587 for (phy = 1; phy < 32 && phy_idx < ARRAY_SIZE(np->phys);
588 phy++) {
1da177e4
LT		 589 int mii_status = mdio_read(dev, phy, 1);
590
591 if (mii_status != 0xffff && mii_status != 0x0000) {
592 np->phys[phy_idx++] = phy;
9b91cf9d 593 dev_info(&pdev->dev,
2e8a538d
JG		 594 "MII PHY found at address %d, status "
595 "0x%4.4x.\n", phy, mii_status);
1da177e4
LT		 596 /* get phy type */
597 {
598 unsigned int data;
599
600 data = mdio_read(dev, np->phys[0], 2);
601 if (data == SeeqPHYID0)
602 np->PHYType = SeeqPHY;
603 else if (data == AhdocPHYID0)
604 np->PHYType = AhdocPHY;
605 else if (data == MarvellPHYID0)
606 np->PHYType = MarvellPHY;
607 else if (data == MysonPHYID0)
608 np->PHYType = Myson981;
609 else if (data == LevelOnePHYID0)
610 np->PHYType = LevelOnePHY;
611 else
612 np->PHYType = OtherPHY;
613 }
614 }
615 }
616
617 np->mii_cnt = phy_idx;
2e8a538d 618 if (phy_idx == 0)
9b91cf9d 619 dev_warn(&pdev->dev,
2e8a538d
JG		 620 "MII PHY not found -- this device may "
621 "not operate correctly.\n");
1da177e4
LT		 622 } else {
623 np->phys[0] = 32;
624/* 89/6/23 add, (begin) */
625 /* get phy type */
626 if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID)
627 np->PHYType = MysonPHY;
628 else
629 np->PHYType = OtherPHY;
630 }
631 np->mii.phy_id = np->phys[0];
632
633 if (dev->mem_start)
634 option = dev->mem_start;
635
636 /* The lower four bits are the media type. */
637 if (option > 0) {
638 if (option & 0x200)
639 np->mii.full_duplex = 1;
640 np->default_port = option & 15;
641 }
642
643 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
644 np->mii.full_duplex = full_duplex[card_idx];
645
646 if (np->mii.full_duplex) {
9b91cf9d 647 dev_info(&pdev->dev, "Media type forced to Full Duplex.\n");
1da177e4
LT		 648/* 89/6/13 add, (begin) */
649// if (np->PHYType==MarvellPHY)
650 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
651 unsigned int data;
652
653 data = mdio_read(dev, np->phys[0], 9);
654 data = (data & 0xfcff) | 0x0200;
655 mdio_write(dev, np->phys[0], 9, data);
656 }
657/* 89/6/13 add, (end) */
658 if (np->flags == HAS_MII_XCVR)
659 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
660 else
661 iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR);
662 np->mii.force_media = 1;
663 }
664
e287157f 665 dev->netdev_ops = &netdev_ops;
1da177e4 666 dev->ethtool_ops = &netdev_ethtool_ops;
1da177e4 667 dev->watchdog_timeo = TX_TIMEOUT;
6aa20a22 668
1da177e4
LT		 669 err = register_netdev(dev);
670 if (err)
671 goto err_out_free_tx;
672
e174961c 673 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
0795af57 674 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr,
e174961c 675 dev->dev_addr, irq);
1da177e4
LT		 676
677 return 0;
678
679err_out_free_tx:
680 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
681err_out_free_rx:
682 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
683err_out_free_dev:
684 free_netdev(dev);
685err_out_unmap:
686 pci_iounmap(pdev, ioaddr);
687err_out_res:
688 pci_release_regions(pdev);
689 return err;
690}
691
692
693static void __devexit fealnx_remove_one(struct pci_dev *pdev)
694{
695 struct net_device *dev = pci_get_drvdata(pdev);
696
697 if (dev) {
698 struct netdev_private *np = netdev_priv(dev);
699
700 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
701 np->tx_ring_dma);
702 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
703 np->rx_ring_dma);
704 unregister_netdev(dev);
705 pci_iounmap(pdev, np->mem);
706 free_netdev(dev);
707 pci_release_regions(pdev);
708 pci_set_drvdata(pdev, NULL);
709 } else
710 printk(KERN_ERR "fealnx: remove for unknown device\n");
711}
712
713
714static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad)
715{
716 ulong miir;
717 int i;
718 unsigned int mask, data;
719
720 /* enable MII output */
721 miir = (ulong) ioread32(miiport);
722 miir &= 0xfffffff0;
723
724 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
725
726 /* send 32 1's preamble */
727 for (i = 0; i < 32; i++) {
728 /* low MDC; MDO is already high (miir) */
729 miir &= ~MASK_MIIR_MII_MDC;
730 iowrite32(miir, miiport);
731
732 /* high MDC */
733 miir |= MASK_MIIR_MII_MDC;
734 iowrite32(miir, miiport);
735 }
736
737 /* calculate ST+OP+PHYAD+REGAD+TA */
738 data = opcode | (phyad << 7) | (regad << 2);
739
740 /* sent out */
741 mask = 0x8000;
742 while (mask) {
743 /* low MDC, prepare MDO */
744 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
745 if (mask & data)
746 miir |= MASK_MIIR_MII_MDO;
747
748 iowrite32(miir, miiport);
749 /* high MDC */
750 miir |= MASK_MIIR_MII_MDC;
751 iowrite32(miir, miiport);
752 udelay(30);
753
754 /* next */
755 mask >>= 1;
756 if (mask == 0x2 && opcode == OP_READ)
757 miir &= ~MASK_MIIR_MII_WRITE;
758 }
759 return miir;
760}
761
762
763static int mdio_read(struct net_device *dev, int phyad, int regad)
764{
765 struct netdev_private *np = netdev_priv(dev);
766 void __iomem *miiport = np->mem + MANAGEMENT;
767 ulong miir;
768 unsigned int mask, data;
769
770 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
771
772 /* read data */
773 mask = 0x8000;
774 data = 0;
775 while (mask) {
776 /* low MDC */
777 miir &= ~MASK_MIIR_MII_MDC;
778 iowrite32(miir, miiport);
779
780 /* read MDI */
781 miir = ioread32(miiport);
782 if (miir & MASK_MIIR_MII_MDI)
783 data |= mask;
784
785 /* high MDC, and wait */
786 miir |= MASK_MIIR_MII_MDC;
787 iowrite32(miir, miiport);
788 udelay(30);
789
790 /* next */
791 mask >>= 1;
792 }
793
794 /* low MDC */
795 miir &= ~MASK_MIIR_MII_MDC;
796 iowrite32(miir, miiport);
797
798 return data & 0xffff;
799}
800
801
802static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
803{
804 struct netdev_private *np = netdev_priv(dev);
805 void __iomem *miiport = np->mem + MANAGEMENT;
806 ulong miir;
807 unsigned int mask;
808
809 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
810
811 /* write data */
812 mask = 0x8000;
813 while (mask) {
814 /* low MDC, prepare MDO */
815 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
816 if (mask & data)
817 miir |= MASK_MIIR_MII_MDO;
818 iowrite32(miir, miiport);
819
820 /* high MDC */
821 miir |= MASK_MIIR_MII_MDC;
822 iowrite32(miir, miiport);
823
824 /* next */
825 mask >>= 1;
826 }
827
828 /* low MDC */
829 miir &= ~MASK_MIIR_MII_MDC;
830 iowrite32(miir, miiport);
831}
832
833
834static int netdev_open(struct net_device *dev)
835{
836 struct netdev_private *np = netdev_priv(dev);
837 void __iomem *ioaddr = np->mem;
838 int i;
839
840 iowrite32(0x00000001, ioaddr + BCR); /* Reset */
841
1fb9df5d 842 if (request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev))
1da177e4
LT		 843 return -EAGAIN;
844
845 for (i = 0; i < 3; i++)
846 iowrite16(((unsigned short*)dev->dev_addr)[i],
847 ioaddr + PAR0 + i*2);
848
849 init_ring(dev);
850
851 iowrite32(np->rx_ring_dma, ioaddr + RXLBA);
852 iowrite32(np->tx_ring_dma, ioaddr + TXLBA);
853
854 /* Initialize other registers. */
855 /* Configure the PCI bus bursts and FIFO thresholds.
856 486: Set 8 longword burst.
857 586: no burst limit.
858 Burst length 5:3
859 0 0 0 1
860 0 0 1 4
861 0 1 0 8
862 0 1 1 16
863 1 0 0 32
864 1 0 1 64
865 1 1 0 128
866 1 1 1 256
867 Wait the specified 50 PCI cycles after a reset by initializing
868 Tx and Rx queues and the address filter list.
869 FIXME (Ueimor): optimistic for alpha + posted writes ? */
28cd4289 870
1da177e4 871 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
28cd4289
JG		 872#ifdef __BIG_ENDIAN
873 np->bcrvalue |= 0x04; /* big-endian */
1da177e4 874#endif
28cd4289
JG		 875
876#if defined(__i386__) && !defined(MODULE)
877 if (boot_cpu_data.x86 <= 4)
878 np->crvalue = 0xa00;
879 else
1da177e4 880#endif
28cd4289
JG		 881 np->crvalue = 0xe00; /* rx 128 burst length */
882
883
1da177e4
LT		 884// 89/12/29 add,
885// 90/1/16 modify,
886// np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
887 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
888 if (np->pci_dev->device == 0x891) {
889 np->bcrvalue |= 0x200; /* set PROG bit */
890 np->crvalue |= CR_W_ENH; /* set enhanced bit */
891 np->imrvalue |= ETI;
892 }
893 iowrite32(np->bcrvalue, ioaddr + BCR);
894
895 if (dev->if_port == 0)
896 dev->if_port = np->default_port;
897
898 iowrite32(0, ioaddr + RXPDR);
899// 89/9/1 modify,
900// np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
901 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
902 np->mii.full_duplex = np->mii.force_media;
903 getlinkstatus(dev);
904 if (np->linkok)
905 getlinktype(dev);
906 __set_rx_mode(dev);
907
908 netif_start_queue(dev);
909
910 /* Clear and Enable interrupts by setting the interrupt mask. */
911 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
912 iowrite32(np->imrvalue, ioaddr + IMR);
913
914 if (debug)
915 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
916
917 /* Set the timer to check for link beat. */
918 init_timer(&np->timer);
919 np->timer.expires = RUN_AT(3 * HZ);
920 np->timer.data = (unsigned long) dev;
921 np->timer.function = &netdev_timer;
922
923 /* timer handler */
924 add_timer(&np->timer);
925
926 init_timer(&np->reset_timer);
927 np->reset_timer.data = (unsigned long) dev;
928 np->reset_timer.function = &reset_timer;
929 np->reset_timer_armed = 0;
930
931 return 0;
932}
933
934
935static void getlinkstatus(struct net_device *dev)
936/* function: Routine will read MII Status Register to get link status. */
937/* input : dev... pointer to the adapter block. */
938/* output : none. */
939{
940 struct netdev_private *np = netdev_priv(dev);
941 unsigned int i, DelayTime = 0x1000;
942
943 np->linkok = 0;
944
945 if (np->PHYType == MysonPHY) {
946 for (i = 0; i < DelayTime; ++i) {
947 if (ioread32(np->mem + BMCRSR) & LinkIsUp2) {
948 np->linkok = 1;
949 return;
950 }
951 udelay(100);
952 }
953 } else {
954 for (i = 0; i < DelayTime; ++i) {
955 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
956 np->linkok = 1;
957 return;
958 }
959 udelay(100);
960 }
961 }
962}
963
964
965static void getlinktype(struct net_device *dev)
966{
967 struct netdev_private *np = netdev_priv(dev);
968
969 if (np->PHYType == MysonPHY) { /* 3-in-1 case */
970 if (ioread32(np->mem + TCRRCR) & CR_R_FD)
971 np->duplexmode = 2; /* full duplex */
972 else
973 np->duplexmode = 1; /* half duplex */
974 if (ioread32(np->mem + TCRRCR) & CR_R_PS10)
975 np->line_speed = 1; /* 10M */
976 else
977 np->line_speed = 2; /* 100M */
978 } else {
979 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
980 unsigned int data;
981
982 data = mdio_read(dev, np->phys[0], MIIRegister18);
983 if (data & SPD_DET_100)
984 np->line_speed = 2; /* 100M */
985 else
986 np->line_speed = 1; /* 10M */
987 if (data & DPLX_DET_FULL)
988 np->duplexmode = 2; /* full duplex mode */
989 else
990 np->duplexmode = 1; /* half duplex mode */
991 } else if (np->PHYType == AhdocPHY) {
992 unsigned int data;
993
994 data = mdio_read(dev, np->phys[0], DiagnosticReg);
995 if (data & Speed_100)
996 np->line_speed = 2; /* 100M */
997 else
998 np->line_speed = 1; /* 10M */
999 if (data & DPLX_FULL)
1000 np->duplexmode = 2; /* full duplex mode */
1001 else
1002 np->duplexmode = 1; /* half duplex mode */
1003 }
1004/* 89/6/13 add, (begin) */
1005 else if (np->PHYType == MarvellPHY) {
1006 unsigned int data;
1007
1008 data = mdio_read(dev, np->phys[0], SpecificReg);
1009 if (data & Full_Duplex)
1010 np->duplexmode = 2; /* full duplex mode */
1011 else
1012 np->duplexmode = 1; /* half duplex mode */
1013 data &= SpeedMask;
1014 if (data == Speed_1000M)
1015 np->line_speed = 3; /* 1000M */
1016 else if (data == Speed_100M)
1017 np->line_speed = 2; /* 100M */
1018 else
1019 np->line_speed = 1; /* 10M */
1020 }
1021/* 89/6/13 add, (end) */
1022/* 89/7/27 add, (begin) */
1023 else if (np->PHYType == Myson981) {
1024 unsigned int data;
1025
1026 data = mdio_read(dev, np->phys[0], StatusRegister);
1027
1028 if (data & SPEED100)
1029 np->line_speed = 2;
1030 else
1031 np->line_speed = 1;
1032
1033 if (data & FULLMODE)
1034 np->duplexmode = 2;
1035 else
1036 np->duplexmode = 1;
1037 }
1038/* 89/7/27 add, (end) */
1039/* 89/12/29 add */
1040 else if (np->PHYType == LevelOnePHY) {
1041 unsigned int data;
1042
1043 data = mdio_read(dev, np->phys[0], SpecificReg);
1044 if (data & LXT1000_Full)
1045 np->duplexmode = 2; /* full duplex mode */
1046 else
1047 np->duplexmode = 1; /* half duplex mode */
1048 data &= SpeedMask;
1049 if (data == LXT1000_1000M)
1050 np->line_speed = 3; /* 1000M */
1051 else if (data == LXT1000_100M)
1052 np->line_speed = 2; /* 100M */
1053 else
1054 np->line_speed = 1; /* 10M */
1055 }
1056 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1057 if (np->line_speed == 1)
1058 np->crvalue |= CR_W_PS10;
1059 else if (np->line_speed == 3)
1060 np->crvalue |= CR_W_PS1000;
1061 if (np->duplexmode == 2)
1062 np->crvalue |= CR_W_FD;
1063 }
1064}
1065
1066
1067/* Take lock before calling this */
1068static void allocate_rx_buffers(struct net_device *dev)
1069{
1070 struct netdev_private *np = netdev_priv(dev);
1071
1072 /* allocate skb for rx buffers */
1073 while (np->really_rx_count != RX_RING_SIZE) {
1074 struct sk_buff *skb;
1075
1076 skb = dev_alloc_skb(np->rx_buf_sz);
1077 if (skb == NULL)
1078 break; /* Better luck next round. */
1079
1080 while (np->lack_rxbuf->skbuff)
1081 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1082
1083 skb->dev = dev; /* Mark as being used by this device. */
1084 np->lack_rxbuf->skbuff = skb;
689be439 1085 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->data,
1da177e4
LT		 1086 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1087 np->lack_rxbuf->status = RXOWN;
1088 ++np->really_rx_count;
1089 }
1090}
1091
1092
1093static void netdev_timer(unsigned long data)
1094{
1095 struct net_device *dev = (struct net_device *) data;
1096 struct netdev_private *np = netdev_priv(dev);
1097 void __iomem *ioaddr = np->mem;
1098 int old_crvalue = np->crvalue;
1099 unsigned int old_linkok = np->linkok;
1100 unsigned long flags;
1101
1102 if (debug)
1103 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1104 "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR),
1105 ioread32(ioaddr + TCRRCR));
1106
1107 spin_lock_irqsave(&np->lock, flags);
1108
1109 if (np->flags == HAS_MII_XCVR) {
1110 getlinkstatus(dev);
1111 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1112 getlinktype(dev);
1113 if (np->crvalue != old_crvalue) {
1114 stop_nic_rxtx(ioaddr, np->crvalue);
1115 iowrite32(np->crvalue, ioaddr + TCRRCR);
1116 }
1117 }
1118 }
1119
1120 allocate_rx_buffers(dev);
1121
1122 spin_unlock_irqrestore(&np->lock, flags);
1123
1124 np->timer.expires = RUN_AT(10 * HZ);
1125 add_timer(&np->timer);
1126}
1127
1128
1129/* Take lock before calling */
1130/* Reset chip and disable rx, tx and interrupts */
1131static void reset_and_disable_rxtx(struct net_device *dev)
1132{
1133 struct netdev_private *np = netdev_priv(dev);
1134 void __iomem *ioaddr = np->mem;
1135 int delay=51;
1136
1137 /* Reset the chip's Tx and Rx processes. */
1138 stop_nic_rxtx(ioaddr, 0);
1139
1140 /* Disable interrupts by clearing the interrupt mask. */
1141 iowrite32(0, ioaddr + IMR);
1142
1143 /* Reset the chip to erase previous misconfiguration. */
1144 iowrite32(0x00000001, ioaddr + BCR);
1145
6aa20a22 1146 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1da177e4
LT		 1147 We surely wait too long (address+data phase). Who cares? */
1148 while (--delay) {
1149 ioread32(ioaddr + BCR);
1150 rmb();
1151 }
1152}
1153
1154
1155/* Take lock before calling */
1156/* Restore chip after reset */
1157static void enable_rxtx(struct net_device *dev)
1158{
1159 struct netdev_private *np = netdev_priv(dev);
1160 void __iomem *ioaddr = np->mem;
1161
1162 reset_rx_descriptors(dev);
1163
1164 iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1165 ioaddr + TXLBA);
1166 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1167 ioaddr + RXLBA);
1168
1169 iowrite32(np->bcrvalue, ioaddr + BCR);
1170
1171 iowrite32(0, ioaddr + RXPDR);
1172 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1173
1174 /* Clear and Enable interrupts by setting the interrupt mask. */
1175 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1176 iowrite32(np->imrvalue, ioaddr + IMR);
1177
1178 iowrite32(0, ioaddr + TXPDR);
1179}
1180
1181
1182static void reset_timer(unsigned long data)
1183{
1184 struct net_device *dev = (struct net_device *) data;
1185 struct netdev_private *np = netdev_priv(dev);
1186 unsigned long flags;
1187
1188 printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
1189
1190 spin_lock_irqsave(&np->lock, flags);
1191 np->crvalue = np->crvalue_sv;
1192 np->imrvalue = np->imrvalue_sv;
1193
1194 reset_and_disable_rxtx(dev);
1195 /* works for me without this:
1196 reset_tx_descriptors(dev); */
1197 enable_rxtx(dev);
1198 netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */
6aa20a22 1199
1da177e4
LT		 1200 np->reset_timer_armed = 0;
1201
1202 spin_unlock_irqrestore(&np->lock, flags);
1203}
1204
1205
ed4cb133 1206static void fealnx_tx_timeout(struct net_device *dev)
1da177e4
LT		 1207{
1208 struct netdev_private *np = netdev_priv(dev);
1209 void __iomem *ioaddr = np->mem;
1210 unsigned long flags;
1211 int i;
1212
1213 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
1214 " resetting...\n", dev->name, ioread32(ioaddr + ISR));
1215
1216 {
1217 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1218 for (i = 0; i < RX_RING_SIZE; i++)
1219 printk(" %8.8x", (unsigned int) np->rx_ring[i].status);
1220 printk("\n" KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1221 for (i = 0; i < TX_RING_SIZE; i++)
1222 printk(" %4.4x", np->tx_ring[i].status);
1223 printk("\n");
1224 }
6aa20a22 1225
1da177e4
LT		 1226 spin_lock_irqsave(&np->lock, flags);
1227
1228 reset_and_disable_rxtx(dev);
1229 reset_tx_descriptors(dev);
1230 enable_rxtx(dev);
1231
1232 spin_unlock_irqrestore(&np->lock, flags);
1233
1234 dev->trans_start = jiffies;
1235 np->stats.tx_errors++;
1236 netif_wake_queue(dev); /* or .._start_.. ?? */
1237}
1238
1239
1240/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1241static void init_ring(struct net_device *dev)
1242{
1243 struct netdev_private *np = netdev_priv(dev);
1244 int i;
1245
1246 /* initialize rx variables */
1247 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1248 np->cur_rx = &np->rx_ring[0];
1249 np->lack_rxbuf = np->rx_ring;
1250 np->really_rx_count = 0;
1251
1252 /* initial rx descriptors. */
1253 for (i = 0; i < RX_RING_SIZE; i++) {
1254 np->rx_ring[i].status = 0;
1255 np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1256 np->rx_ring[i].next_desc = np->rx_ring_dma +
1257 (i + 1)*sizeof(struct fealnx_desc);
1258 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1259 np->rx_ring[i].skbuff = NULL;
1260 }
1261
1262 /* for the last rx descriptor */
1263 np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1264 np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1265
1266 /* allocate skb for rx buffers */
1267 for (i = 0; i < RX_RING_SIZE; i++) {
1268 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1269
1270 if (skb == NULL) {
1271 np->lack_rxbuf = &np->rx_ring[i];
1272 break;
1273 }
1274
1275 ++np->really_rx_count;
1276 np->rx_ring[i].skbuff = skb;
1277 skb->dev = dev; /* Mark as being used by this device. */
689be439 1278 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->data,
1da177e4
LT		 1279 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1280 np->rx_ring[i].status = RXOWN;
1281 np->rx_ring[i].control |= RXIC;
1282 }
1283
1284 /* initialize tx variables */
1285 np->cur_tx = &np->tx_ring[0];
1286 np->cur_tx_copy = &np->tx_ring[0];
1287 np->really_tx_count = 0;
1288 np->free_tx_count = TX_RING_SIZE;
1289
1290 for (i = 0; i < TX_RING_SIZE; i++) {
1291 np->tx_ring[i].status = 0;
1292 /* do we need np->tx_ring[i].control = XXX; ?? */
1293 np->tx_ring[i].next_desc = np->tx_ring_dma +
1294 (i + 1)*sizeof(struct fealnx_desc);
1295 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1296 np->tx_ring[i].skbuff = NULL;
1297 }
1298
1299 /* for the last tx descriptor */
1300 np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1301 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1302}
1303
1304
1305static int start_tx(struct sk_buff *skb, struct net_device *dev)
1306{
1307 struct netdev_private *np = netdev_priv(dev);
1308 unsigned long flags;
1309
1310 spin_lock_irqsave(&np->lock, flags);
1311
1312 np->cur_tx_copy->skbuff = skb;
1313
1314#define one_buffer
1315#define BPT 1022
1316#if defined(one_buffer)
1317 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1318 skb->len, PCI_DMA_TODEVICE);
1319 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1320 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1321 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1322// 89/12/29 add,
1323 if (np->pci_dev->device == 0x891)
1324 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1325 np->cur_tx_copy->status = TXOWN;
1326 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1327 --np->free_tx_count;
1328#elif defined(two_buffer)
1329 if (skb->len > BPT) {
1330 struct fealnx_desc *next;
1331
1332 /* for the first descriptor */
1333 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1334 BPT, PCI_DMA_TODEVICE);
1335 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1336 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1337 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1338
1339 /* for the last descriptor */
1340 next = np->cur_tx_copy->next_desc_logical;
1341 next->skbuff = skb;
1342 next->control = TXIC | TXLD | CRCEnable | PADEnable;
1343 next->control |= (skb->len << PKTSShift); /* pkt size */
1344 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */
1345// 89/12/29 add,
1346 if (np->pci_dev->device == 0x891)
1347 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1348 next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1349 skb->len - BPT, PCI_DMA_TODEVICE);
1350
1351 next->status = TXOWN;
1352 np->cur_tx_copy->status = TXOWN;
1353
1354 np->cur_tx_copy = next->next_desc_logical;
1355 np->free_tx_count -= 2;
1356 } else {
1357 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1358 skb->len, PCI_DMA_TODEVICE);
1359 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1360 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1361 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1362// 89/12/29 add,
1363 if (np->pci_dev->device == 0x891)
1364 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1365 np->cur_tx_copy->status = TXOWN;
1366 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1367 --np->free_tx_count;
1368 }
1369#endif
1370
1371 if (np->free_tx_count < 2)
1372 netif_stop_queue(dev);
1373 ++np->really_tx_count;
1374 iowrite32(0, np->mem + TXPDR);
1375 dev->trans_start = jiffies;
1376
1377 spin_unlock_irqrestore(&np->lock, flags);
1378 return 0;
1379}
1380
1381
1382/* Take lock before calling */
1383/* Chip probably hosed tx ring. Clean up. */
1384static void reset_tx_descriptors(struct net_device *dev)
1385{
1386 struct netdev_private *np = netdev_priv(dev);
1387 struct fealnx_desc *cur;
1388 int i;
1389
1390 /* initialize tx variables */
1391 np->cur_tx = &np->tx_ring[0];
1392 np->cur_tx_copy = &np->tx_ring[0];
1393 np->really_tx_count = 0;
1394 np->free_tx_count = TX_RING_SIZE;
1395
1396 for (i = 0; i < TX_RING_SIZE; i++) {
1397 cur = &np->tx_ring[i];
1398 if (cur->skbuff) {
1399 pci_unmap_single(np->pci_dev, cur->buffer,
1400 cur->skbuff->len, PCI_DMA_TODEVICE);
400de2c0 1401 dev_kfree_skb_any(cur->skbuff);
1da177e4
LT		 1402 cur->skbuff = NULL;
1403 }
1404 cur->status = 0;
1405 cur->control = 0; /* needed? */
1406 /* probably not needed. We do it for purely paranoid reasons */
1407 cur->next_desc = np->tx_ring_dma +
1408 (i + 1)*sizeof(struct fealnx_desc);
1409 cur->next_desc_logical = &np->tx_ring[i + 1];
1410 }
1411 /* for the last tx descriptor */
1412 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1413 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1414}
1415
1416
1417/* Take lock and stop rx before calling this */
1418static void reset_rx_descriptors(struct net_device *dev)
1419{
1420 struct netdev_private *np = netdev_priv(dev);
1421 struct fealnx_desc *cur = np->cur_rx;
1422 int i;
1423
1424 allocate_rx_buffers(dev);
1425
1426 for (i = 0; i < RX_RING_SIZE; i++) {
1427 if (cur->skbuff)
1428 cur->status = RXOWN;
1429 cur = cur->next_desc_logical;
1430 }
1431
1432 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1433 np->mem + RXLBA);
1434}
1435
1436
1437/* The interrupt handler does all of the Rx thread work and cleans up
1438 after the Tx thread. */
7d12e780 1439static irqreturn_t intr_handler(int irq, void *dev_instance)
1da177e4
LT		 1440{
1441 struct net_device *dev = (struct net_device *) dev_instance;
1442 struct netdev_private *np = netdev_priv(dev);
1443 void __iomem *ioaddr = np->mem;
1444 long boguscnt = max_interrupt_work;
1445 unsigned int num_tx = 0;
1446 int handled = 0;
1447
1448 spin_lock(&np->lock);
1449
1450 iowrite32(0, ioaddr + IMR);
1451
1452 do {
1453 u32 intr_status = ioread32(ioaddr + ISR);
1454
1455 /* Acknowledge all of the current interrupt sources ASAP. */
1456 iowrite32(intr_status, ioaddr + ISR);
1457
1458 if (debug)
1459 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1460 intr_status);
1461
1462 if (!(intr_status & np->imrvalue))
1463 break;
1464
1465 handled = 1;
1466
1467// 90/1/16 delete,
1468//
1469// if (intr_status & FBE)
1470// { /* fatal error */
1471// stop_nic_tx(ioaddr, 0);
1472// stop_nic_rx(ioaddr, 0);
1473// break;
1474// };
1475
1476 if (intr_status & TUNF)
1477 iowrite32(0, ioaddr + TXPDR);
1478
1479 if (intr_status & CNTOVF) {
1480 /* missed pkts */
1481 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1482
1483 /* crc error */
1484 np->stats.rx_crc_errors +=
1485 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1486 }
1487
1488 if (intr_status & (RI | RBU)) {
1489 if (intr_status & RI)
1490 netdev_rx(dev);
1491 else {
1492 stop_nic_rx(ioaddr, np->crvalue);
1493 reset_rx_descriptors(dev);
1494 iowrite32(np->crvalue, ioaddr + TCRRCR);
6aa20a22 1495 }
1da177e4
LT		 1496 }
1497
1498 while (np->really_tx_count) {
1499 long tx_status = np->cur_tx->status;
1500 long tx_control = np->cur_tx->control;
1501
1502 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
1503 struct fealnx_desc *next;
1504
1505 next = np->cur_tx->next_desc_logical;
1506 tx_status = next->status;
1507 tx_control = next->control;
1508 }
1509
1510 if (tx_status & TXOWN)
1511 break;
1512
1513 if (!(np->crvalue & CR_W_ENH)) {
1514 if (tx_status & (CSL | LC | EC | UDF | HF)) {
1515 np->stats.tx_errors++;
1516 if (tx_status & EC)
1517 np->stats.tx_aborted_errors++;
1518 if (tx_status & CSL)
1519 np->stats.tx_carrier_errors++;
1520 if (tx_status & LC)
1521 np->stats.tx_window_errors++;
1522 if (tx_status & UDF)
1523 np->stats.tx_fifo_errors++;
1524 if ((tx_status & HF) && np->mii.full_duplex == 0)
1525 np->stats.tx_heartbeat_errors++;
1526
1527 } else {
1528 np->stats.tx_bytes +=
1529 ((tx_control & PKTSMask) >> PKTSShift);
1530
1531 np->stats.collisions +=
1532 ((tx_status & NCRMask) >> NCRShift);
1533 np->stats.tx_packets++;
1534 }
1535 } else {
1536 np->stats.tx_bytes +=
1537 ((tx_control & PKTSMask) >> PKTSShift);
1538 np->stats.tx_packets++;
1539 }
1540
1541 /* Free the original skb. */
1542 pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1543 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1544 dev_kfree_skb_irq(np->cur_tx->skbuff);
1545 np->cur_tx->skbuff = NULL;
1546 --np->really_tx_count;
1547 if (np->cur_tx->control & TXLD) {
1548 np->cur_tx = np->cur_tx->next_desc_logical;
1549 ++np->free_tx_count;
1550 } else {
1551 np->cur_tx = np->cur_tx->next_desc_logical;
1552 np->cur_tx = np->cur_tx->next_desc_logical;
1553 np->free_tx_count += 2;
1554 }
1555 num_tx++;
1556 } /* end of for loop */
6aa20a22 1557
1da177e4
LT		 1558 if (num_tx && np->free_tx_count >= 2)
1559 netif_wake_queue(dev);
1560
1561 /* read transmit status for enhanced mode only */
1562 if (np->crvalue & CR_W_ENH) {
1563 long data;
1564
1565 data = ioread32(ioaddr + TSR);
1566 np->stats.tx_errors += (data & 0xff000000) >> 24;
1567 np->stats.tx_aborted_errors += (data & 0xff000000) >> 24;
1568 np->stats.tx_window_errors += (data & 0x00ff0000) >> 16;
1569 np->stats.collisions += (data & 0x0000ffff);
1570 }
1571
1572 if (--boguscnt < 0) {
1573 printk(KERN_WARNING "%s: Too much work at interrupt, "
1574 "status=0x%4.4x.\n", dev->name, intr_status);
1575 if (!np->reset_timer_armed) {
1576 np->reset_timer_armed = 1;
1577 np->reset_timer.expires = RUN_AT(HZ/2);
1578 add_timer(&np->reset_timer);
1579 stop_nic_rxtx(ioaddr, 0);
1580 netif_stop_queue(dev);
1581 /* or netif_tx_disable(dev); ?? */
1582 /* Prevent other paths from enabling tx,rx,intrs */
1583 np->crvalue_sv = np->crvalue;
1584 np->imrvalue_sv = np->imrvalue;
1585 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1586 np->imrvalue = 0;
1587 }
1588
1589 break;
1590 }
1591 } while (1);
1592
1593 /* read the tally counters */
1594 /* missed pkts */
1595 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1596
1597 /* crc error */
1598 np->stats.rx_crc_errors += (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1599
1600 if (debug)
1601 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1602 dev->name, ioread32(ioaddr + ISR));
1603
1604 iowrite32(np->imrvalue, ioaddr + IMR);
1605
1606 spin_unlock(&np->lock);
1607
1608 return IRQ_RETVAL(handled);
1609}
1610
1611
1612/* This routine is logically part of the interrupt handler, but separated
1613 for clarity and better register allocation. */
1614static int netdev_rx(struct net_device *dev)
1615{
1616 struct netdev_private *np = netdev_priv(dev);
1617 void __iomem *ioaddr = np->mem;
1618
1619 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1620 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1621 s32 rx_status = np->cur_rx->status;
1622
1623 if (np->really_rx_count == 0)
1624 break;
1625
1626 if (debug)
1627 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status);
1628
1629 if ((!((rx_status & RXFSD) && (rx_status & RXLSD)))
1630 || (rx_status & ErrorSummary)) {
1631 if (rx_status & ErrorSummary) { /* there was a fatal error */
1632 if (debug)
1633 printk(KERN_DEBUG
1634 "%s: Receive error, Rx status %8.8x.\n",
1635 dev->name, rx_status);
1636
1637 np->stats.rx_errors++; /* end of a packet. */
1638 if (rx_status & (LONG | RUNT))
1639 np->stats.rx_length_errors++;
1640 if (rx_status & RXER)
1641 np->stats.rx_frame_errors++;
1642 if (rx_status & CRC)
1643 np->stats.rx_crc_errors++;
1644 } else {
1645 int need_to_reset = 0;
1646 int desno = 0;
1647
1648 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */
1649 struct fealnx_desc *cur;
1650
1651 /* check this packet is received completely? */
1652 cur = np->cur_rx;
1653 while (desno <= np->really_rx_count) {
1654 ++desno;
1655 if ((!(cur->status & RXOWN))
1656 && (cur->status & RXLSD))
1657 break;
1658 /* goto next rx descriptor */
1659 cur = cur->next_desc_logical;
1660 }
1661 if (desno > np->really_rx_count)
1662 need_to_reset = 1;
1663 } else /* RXLSD did not find, something error */
1664 need_to_reset = 1;
1665
1666 if (need_to_reset == 0) {
1667 int i;
1668
1669 np->stats.rx_length_errors++;
1670
1671 /* free all rx descriptors related this long pkt */
1672 for (i = 0; i < desno; ++i) {
1673 if (!np->cur_rx->skbuff) {
1674 printk(KERN_DEBUG
1675 "%s: I'm scared\n", dev->name);
1676 break;
1677 }
1678 np->cur_rx->status = RXOWN;
1679 np->cur_rx = np->cur_rx->next_desc_logical;
1680 }
1681 continue;
1682 } else { /* rx error, need to reset this chip */
1683 stop_nic_rx(ioaddr, np->crvalue);
1684 reset_rx_descriptors(dev);
1685 iowrite32(np->crvalue, ioaddr + TCRRCR);
1686 }
1687 break; /* exit the while loop */
1688 }
1689 } else { /* this received pkt is ok */
1690
1691 struct sk_buff *skb;
1692 /* Omit the four octet CRC from the length. */
1693 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1694
1695#ifndef final_version
1696 if (debug)
1697 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1698 " status %x.\n", pkt_len, rx_status);
1699#endif
1700
1701 /* Check if the packet is long enough to accept without copying
1702 to a minimally-sized skbuff. */
1703 if (pkt_len < rx_copybreak &&
1704 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 1705 skb_reserve(skb, 2); /* 16 byte align the IP header */
1706 pci_dma_sync_single_for_cpu(np->pci_dev,
1707 np->cur_rx->buffer,
1708 np->rx_buf_sz,
1709 PCI_DMA_FROMDEVICE);
1710 /* Call copy + cksum if available. */
1711
1712#if ! defined(__alpha__)
8c7b7faa
DM		 1713 skb_copy_to_linear_data(skb,
1714 np->cur_rx->skbuff->data, pkt_len);
1da177e4
LT		 1715 skb_put(skb, pkt_len);
1716#else
1717 memcpy(skb_put(skb, pkt_len),
689be439 1718 np->cur_rx->skbuff->data, pkt_len);
1da177e4
LT		 1719#endif
1720 pci_dma_sync_single_for_device(np->pci_dev,
1721 np->cur_rx->buffer,
1722 np->rx_buf_sz,
1723 PCI_DMA_FROMDEVICE);
1724 } else {
1725 pci_unmap_single(np->pci_dev,
1726 np->cur_rx->buffer,
1727 np->rx_buf_sz,
1728 PCI_DMA_FROMDEVICE);
1729 skb_put(skb = np->cur_rx->skbuff, pkt_len);
1730 np->cur_rx->skbuff = NULL;
1731 --np->really_rx_count;
1732 }
1733 skb->protocol = eth_type_trans(skb, dev);
1734 netif_rx(skb);
1da177e4
LT		 1735 np->stats.rx_packets++;
1736 np->stats.rx_bytes += pkt_len;
1737 }
1738
1739 np->cur_rx = np->cur_rx->next_desc_logical;
1740 } /* end of while loop */
1741
1742 /* allocate skb for rx buffers */
1743 allocate_rx_buffers(dev);
1744
1745 return 0;
1746}
1747
1748
1749static struct net_device_stats *get_stats(struct net_device *dev)
1750{
1751 struct netdev_private *np = netdev_priv(dev);
1752 void __iomem *ioaddr = np->mem;
1753
1754 /* The chip only need report frame silently dropped. */
1755 if (netif_running(dev)) {
1756 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1757 np->stats.rx_crc_errors += (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1758 }
1759
1760 return &np->stats;
1761}
1762
1763
1764/* for dev->set_multicast_list */
1765static void set_rx_mode(struct net_device *dev)
1766{
1767 spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock;
1768 unsigned long flags;
1769 spin_lock_irqsave(lp, flags);
1770 __set_rx_mode(dev);
1771 spin_unlock_irqrestore(lp, flags);
1772}
1773
1774
1775/* Take lock before calling */
1776static void __set_rx_mode(struct net_device *dev)
1777{
1778 struct netdev_private *np = netdev_priv(dev);
1779 void __iomem *ioaddr = np->mem;
1780 u32 mc_filter[2]; /* Multicast hash filter */
1781 u32 rx_mode;
1782
1783 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT		 1784 memset(mc_filter, 0xff, sizeof(mc_filter));
1785 rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM;
1786 } else if ((dev->mc_count > multicast_filter_limit)
1787 || (dev->flags & IFF_ALLMULTI)) {
1788 /* Too many to match, or accept all multicasts. */
1789 memset(mc_filter, 0xff, sizeof(mc_filter));
1790 rx_mode = CR_W_AB | CR_W_AM;
1791 } else {
1792 struct dev_mc_list *mclist;
1793 int i;
1794
1795 memset(mc_filter, 0, sizeof(mc_filter));
1796 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1797 i++, mclist = mclist->next) {
1798 unsigned int bit;
1799 bit = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F;
1800 mc_filter[bit >> 5] |= (1 << bit);
1801 }
1802 rx_mode = CR_W_AB | CR_W_AM;
1803 }
1804
1805 stop_nic_rxtx(ioaddr, np->crvalue);
1806
1807 iowrite32(mc_filter[0], ioaddr + MAR0);
1808 iowrite32(mc_filter[1], ioaddr + MAR1);
1809 np->crvalue &= ~CR_W_RXMODEMASK;
1810 np->crvalue |= rx_mode;
1811 iowrite32(np->crvalue, ioaddr + TCRRCR);
1812}
1813
1814static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1815{
1816 struct netdev_private *np = netdev_priv(dev);
1817
1818 strcpy(info->driver, DRV_NAME);
1819 strcpy(info->version, DRV_VERSION);
1820 strcpy(info->bus_info, pci_name(np->pci_dev));
1821}
1822
1823static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1824{
1825 struct netdev_private *np = netdev_priv(dev);
1826 int rc;
1827
1828 spin_lock_irq(&np->lock);
1829 rc = mii_ethtool_gset(&np->mii, cmd);
1830 spin_unlock_irq(&np->lock);
1831
1832 return rc;
1833}
1834
1835static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1836{
1837 struct netdev_private *np = netdev_priv(dev);
1838 int rc;
1839
1840 spin_lock_irq(&np->lock);
1841 rc = mii_ethtool_sset(&np->mii, cmd);
1842 spin_unlock_irq(&np->lock);
1843
1844 return rc;
1845}
1846
1847static int netdev_nway_reset(struct net_device *dev)
1848{
1849 struct netdev_private *np = netdev_priv(dev);
1850 return mii_nway_restart(&np->mii);
1851}
1852
1853static u32 netdev_get_link(struct net_device *dev)
1854{
1855 struct netdev_private *np = netdev_priv(dev);
1856 return mii_link_ok(&np->mii);
1857}
1858
1859static u32 netdev_get_msglevel(struct net_device *dev)
1860{
1861 return debug;
1862}
1863
1864static void netdev_set_msglevel(struct net_device *dev, u32 value)
1865{
1866 debug = value;
1867}
1868
7282d491 1869static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 1870 .get_drvinfo = netdev_get_drvinfo,
1871 .get_settings = netdev_get_settings,
1872 .set_settings = netdev_set_settings,
1873 .nway_reset = netdev_nway_reset,
1874 .get_link = netdev_get_link,
1875 .get_msglevel = netdev_get_msglevel,
1876 .set_msglevel = netdev_set_msglevel,
1da177e4
LT		 1877};
1878
1879static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1880{
1881 struct netdev_private *np = netdev_priv(dev);
1882 int rc;
1883
1884 if (!netif_running(dev))
1885 return -EINVAL;
1886
1887 spin_lock_irq(&np->lock);
1888 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
1889 spin_unlock_irq(&np->lock);
1890
1891 return rc;
1892}
1893
1894
1895static int netdev_close(struct net_device *dev)
1896{
1897 struct netdev_private *np = netdev_priv(dev);
1898 void __iomem *ioaddr = np->mem;
1899 int i;
1900
1901 netif_stop_queue(dev);
1902
1903 /* Disable interrupts by clearing the interrupt mask. */
1904 iowrite32(0x0000, ioaddr + IMR);
1905
1906 /* Stop the chip's Tx and Rx processes. */
1907 stop_nic_rxtx(ioaddr, 0);
1908
1909 del_timer_sync(&np->timer);
1910 del_timer_sync(&np->reset_timer);
1911
1912 free_irq(dev->irq, dev);
1913
1914 /* Free all the skbuffs in the Rx queue. */
1915 for (i = 0; i < RX_RING_SIZE; i++) {
1916 struct sk_buff *skb = np->rx_ring[i].skbuff;
1917
1918 np->rx_ring[i].status = 0;
1919 if (skb) {
1920 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1921 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1922 dev_kfree_skb(skb);
1923 np->rx_ring[i].skbuff = NULL;
1924 }
1925 }
1926
1927 for (i = 0; i < TX_RING_SIZE; i++) {
1928 struct sk_buff *skb = np->tx_ring[i].skbuff;
1929
1930 if (skb) {
1931 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1932 skb->len, PCI_DMA_TODEVICE);
1933 dev_kfree_skb(skb);
1934 np->tx_ring[i].skbuff = NULL;
1935 }
1936 }
1937
1938 return 0;
1939}
1940
1941static struct pci_device_id fealnx_pci_tbl[] = {
1942 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1943 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1944 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1945 {} /* terminate list */
1946};
1947MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1948
1949
1950static struct pci_driver fealnx_driver = {
1951 .name = "fealnx",
1952 .id_table = fealnx_pci_tbl,
1953 .probe = fealnx_init_one,
1954 .remove = __devexit_p(fealnx_remove_one),
1955};
1956
1957static int __init fealnx_init(void)
1958{
1959/* when a module, this is printed whether or not devices are found in probe */
1960#ifdef MODULE
1961 printk(version);
1962#endif
1963
29917620 1964 return pci_register_driver(&fealnx_driver);
1da177e4
LT		 1965}
1966
1967static void __exit fealnx_exit(void)
1968{
1969 pci_unregister_driver(&fealnx_driver);
1970}
1971
1972module_init(fealnx_init);
1973module_exit(fealnx_exit);
Linux kernel - Deliverables
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