Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b SG |
20 | * |
21 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/workqueue.h> | |
40 | #include <linux/bitops.h> | |
6f501b17 SH |
41 | #include <linux/io.h> |
42 | #include <linux/irq.h> | |
196719ec | 43 | #include <linux/clk.h> |
ead73183 | 44 | #include <linux/platform_device.h> |
e6b043d5 | 45 | #include <linux/phy.h> |
5eb32bd0 | 46 | #include <linux/fec.h> |
1da177e4 | 47 | |
080853af | 48 | #include <asm/cacheflush.h> |
196719ec | 49 | |
b5680e0b | 50 | #ifndef CONFIG_ARM |
1da177e4 LT |
51 | #include <asm/coldfire.h> |
52 | #include <asm/mcfsim.h> | |
196719ec | 53 | #endif |
6f501b17 | 54 | |
1da177e4 | 55 | #include "fec.h" |
1da177e4 | 56 | |
085e79ed | 57 | #if defined(CONFIG_ARM) |
196719ec SH |
58 | #define FEC_ALIGNMENT 0xf |
59 | #else | |
60 | #define FEC_ALIGNMENT 0x3 | |
61 | #endif | |
62 | ||
b5680e0b SG |
63 | #define DRIVER_NAME "fec" |
64 | ||
65 | /* Controller is ENET-MAC */ | |
66 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
67 | /* Controller needs driver to swap frame */ | |
68 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
69 | ||
70 | static struct platform_device_id fec_devtype[] = { | |
71 | { | |
72 | .name = DRIVER_NAME, | |
73 | .driver_data = 0, | |
74 | }, { | |
75 | .name = "imx28-fec", | |
76 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
77 | } | |
78 | }; | |
79 | ||
49da97dc SG |
80 | static unsigned char macaddr[ETH_ALEN]; |
81 | module_param_array(macaddr, byte, NULL, 0); | |
82 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 83 | |
49da97dc | 84 | #if defined(CONFIG_M5272) |
1da177e4 LT |
85 | /* |
86 | * Some hardware gets it MAC address out of local flash memory. | |
87 | * if this is non-zero then assume it is the address to get MAC from. | |
88 | */ | |
89 | #if defined(CONFIG_NETtel) | |
90 | #define FEC_FLASHMAC 0xf0006006 | |
91 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
92 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
93 | #elif defined(CONFIG_CANCam) |
94 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
95 | #elif defined (CONFIG_M5272C3) |
96 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
97 | #elif defined(CONFIG_MOD5272) | |
98 | #define FEC_FLASHMAC 0xffc0406b | |
1da177e4 LT |
99 | #else |
100 | #define FEC_FLASHMAC 0 | |
101 | #endif | |
43be6366 | 102 | #endif /* CONFIG_M5272 */ |
ead73183 | 103 | |
1da177e4 LT |
104 | /* The number of Tx and Rx buffers. These are allocated from the page |
105 | * pool. The code may assume these are power of two, so it it best | |
106 | * to keep them that size. | |
107 | * We don't need to allocate pages for the transmitter. We just use | |
108 | * the skbuffer directly. | |
109 | */ | |
110 | #define FEC_ENET_RX_PAGES 8 | |
111 | #define FEC_ENET_RX_FRSIZE 2048 | |
112 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
113 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
114 | #define FEC_ENET_TX_FRSIZE 2048 | |
115 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
116 | #define TX_RING_SIZE 16 /* Must be power of two */ | |
117 | #define TX_RING_MOD_MASK 15 /* for this to work */ | |
118 | ||
562d2f8c | 119 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 120 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
121 | #endif |
122 | ||
22f6b860 | 123 | /* Interrupt events/masks. */ |
1da177e4 LT |
124 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
125 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
126 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
127 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
128 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
129 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
130 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
131 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
132 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
133 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
134 | ||
4bee1f9a WS |
135 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
136 | ||
1da177e4 LT |
137 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
138 | */ | |
139 | #define PKT_MAXBUF_SIZE 1518 | |
140 | #define PKT_MINBUF_SIZE 64 | |
141 | #define PKT_MAXBLR_SIZE 1520 | |
142 | ||
143 | ||
144 | /* | |
6b265293 | 145 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
146 | * size bits. Other FEC hardware does not, so we need to take that into |
147 | * account when setting it. | |
148 | */ | |
562d2f8c | 149 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 150 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
151 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
152 | #else | |
153 | #define OPT_FRAME_SIZE 0 | |
154 | #endif | |
155 | ||
156 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | |
157 | * tx_bd_base always point to the base of the buffer descriptors. The | |
158 | * cur_rx and cur_tx point to the currently available buffer. | |
159 | * The dirty_tx tracks the current buffer that is being sent by the | |
160 | * controller. The cur_tx and dirty_tx are equal under both completely | |
161 | * empty and completely full conditions. The empty/ready indicator in | |
162 | * the buffer descriptor determines the actual condition. | |
163 | */ | |
164 | struct fec_enet_private { | |
165 | /* Hardware registers of the FEC device */ | |
f44d6305 | 166 | void __iomem *hwp; |
1da177e4 | 167 | |
cb84d6e7 GU |
168 | struct net_device *netdev; |
169 | ||
ead73183 SH |
170 | struct clk *clk; |
171 | ||
1da177e4 LT |
172 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
173 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
174 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
f0b3fbea | 175 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; |
1da177e4 LT |
176 | ushort skb_cur; |
177 | ushort skb_dirty; | |
178 | ||
22f6b860 | 179 | /* CPM dual port RAM relative addresses */ |
4661e75b | 180 | dma_addr_t bd_dma; |
22f6b860 | 181 | /* Address of Rx and Tx buffers */ |
2e28532f SH |
182 | struct bufdesc *rx_bd_base; |
183 | struct bufdesc *tx_bd_base; | |
184 | /* The next free ring entry */ | |
db8880bc | 185 | struct bufdesc *cur_rx, *cur_tx; |
22f6b860 | 186 | /* The ring entries to be free()ed */ |
2e28532f SH |
187 | struct bufdesc *dirty_tx; |
188 | ||
1da177e4 | 189 | uint tx_full; |
3b2b74ca SS |
190 | /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ |
191 | spinlock_t hw_lock; | |
1da177e4 | 192 | |
db8880bc | 193 | struct platform_device *pdev; |
1da177e4 | 194 | |
e6b043d5 | 195 | int opened; |
1da177e4 | 196 | |
e6b043d5 | 197 | /* Phylib and MDIO interface */ |
db8880bc UKK |
198 | struct mii_bus *mii_bus; |
199 | struct phy_device *phy_dev; | |
200 | int mii_timeout; | |
201 | uint phy_speed; | |
5eb32bd0 | 202 | phy_interface_t phy_interface; |
1da177e4 | 203 | int link; |
1da177e4 | 204 | int full_duplex; |
97b72e43 | 205 | struct completion mdio_done; |
1da177e4 LT |
206 | }; |
207 | ||
e6b043d5 BW |
208 | /* FEC MII MMFR bits definition */ |
209 | #define FEC_MMFR_ST (1 << 30) | |
210 | #define FEC_MMFR_OP_READ (2 << 28) | |
211 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
212 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
213 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
214 | #define FEC_MMFR_TA (2 << 16) | |
215 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 216 | |
97b72e43 | 217 | #define FEC_MII_TIMEOUT 1000 /* us */ |
1da177e4 | 218 | |
22f6b860 SH |
219 | /* Transmitter timeout */ |
220 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 221 | |
b5680e0b SG |
222 | static void *swap_buffer(void *bufaddr, int len) |
223 | { | |
224 | int i; | |
225 | unsigned int *buf = bufaddr; | |
226 | ||
227 | for (i = 0; i < (len + 3) / 4; i++, buf++) | |
228 | *buf = cpu_to_be32(*buf); | |
229 | ||
230 | return bufaddr; | |
231 | } | |
232 | ||
c7621cb3 | 233 | static netdev_tx_t |
c556167f | 234 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
1da177e4 | 235 | { |
c556167f | 236 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
237 | const struct platform_device_id *id_entry = |
238 | platform_get_device_id(fep->pdev); | |
2e28532f | 239 | struct bufdesc *bdp; |
9555b31e | 240 | void *bufaddr; |
0e702ab3 | 241 | unsigned short status; |
3b2b74ca | 242 | unsigned long flags; |
1da177e4 | 243 | |
1da177e4 LT |
244 | if (!fep->link) { |
245 | /* Link is down or autonegotiation is in progress. */ | |
5b548140 | 246 | return NETDEV_TX_BUSY; |
1da177e4 LT |
247 | } |
248 | ||
3b2b74ca | 249 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 LT |
250 | /* Fill in a Tx ring entry */ |
251 | bdp = fep->cur_tx; | |
252 | ||
0e702ab3 | 253 | status = bdp->cbd_sc; |
22f6b860 | 254 | |
0e702ab3 | 255 | if (status & BD_ENET_TX_READY) { |
1da177e4 | 256 | /* Ooops. All transmit buffers are full. Bail out. |
c556167f | 257 | * This should not happen, since ndev->tbusy should be set. |
1da177e4 | 258 | */ |
c556167f | 259 | printk("%s: tx queue full!.\n", ndev->name); |
3b2b74ca | 260 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
5b548140 | 261 | return NETDEV_TX_BUSY; |
1da177e4 | 262 | } |
1da177e4 | 263 | |
22f6b860 | 264 | /* Clear all of the status flags */ |
0e702ab3 | 265 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 266 | |
22f6b860 | 267 | /* Set buffer length and buffer pointer */ |
9555b31e | 268 | bufaddr = skb->data; |
1da177e4 LT |
269 | bdp->cbd_datlen = skb->len; |
270 | ||
271 | /* | |
22f6b860 SH |
272 | * On some FEC implementations data must be aligned on |
273 | * 4-byte boundaries. Use bounce buffers to copy data | |
274 | * and get it aligned. Ugh. | |
1da177e4 | 275 | */ |
9555b31e | 276 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
1da177e4 LT |
277 | unsigned int index; |
278 | index = bdp - fep->tx_bd_base; | |
8a73b0bc | 279 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 280 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
281 | } |
282 | ||
b5680e0b SG |
283 | /* |
284 | * Some design made an incorrect assumption on endian mode of | |
285 | * the system that it's running on. As the result, driver has to | |
286 | * swap every frame going to and coming from the controller. | |
287 | */ | |
288 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
289 | swap_buffer(bufaddr, skb->len); | |
290 | ||
22f6b860 | 291 | /* Save skb pointer */ |
1da177e4 LT |
292 | fep->tx_skbuff[fep->skb_cur] = skb; |
293 | ||
c556167f | 294 | ndev->stats.tx_bytes += skb->len; |
1da177e4 | 295 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
6aa20a22 | 296 | |
1da177e4 LT |
297 | /* Push the data cache so the CPM does not get stale memory |
298 | * data. | |
299 | */ | |
c556167f | 300 | bdp->cbd_bufaddr = dma_map_single(&ndev->dev, bufaddr, |
f0b3fbea | 301 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 302 | |
0e702ab3 GU |
303 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
304 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 305 | */ |
0e702ab3 | 306 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 307 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 308 | bdp->cbd_sc = status; |
1da177e4 | 309 | |
1da177e4 | 310 | /* Trigger transmission start */ |
f44d6305 | 311 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); |
1da177e4 | 312 | |
22f6b860 SH |
313 | /* If this was the last BD in the ring, start at the beginning again. */ |
314 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 315 | bdp = fep->tx_bd_base; |
22f6b860 | 316 | else |
1da177e4 | 317 | bdp++; |
1da177e4 LT |
318 | |
319 | if (bdp == fep->dirty_tx) { | |
320 | fep->tx_full = 1; | |
c556167f | 321 | netif_stop_queue(ndev); |
1da177e4 LT |
322 | } |
323 | ||
2e28532f | 324 | fep->cur_tx = bdp; |
1da177e4 | 325 | |
3b2b74ca | 326 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
1da177e4 | 327 | |
6ed10654 | 328 | return NETDEV_TX_OK; |
1da177e4 LT |
329 | } |
330 | ||
45993653 UKK |
331 | /* This function is called to start or restart the FEC during a link |
332 | * change. This only happens when switching between half and full | |
333 | * duplex. | |
334 | */ | |
1da177e4 | 335 | static void |
45993653 | 336 | fec_restart(struct net_device *ndev, int duplex) |
1da177e4 | 337 | { |
c556167f | 338 | struct fec_enet_private *fep = netdev_priv(ndev); |
45993653 UKK |
339 | const struct platform_device_id *id_entry = |
340 | platform_get_device_id(fep->pdev); | |
341 | int i; | |
342 | u32 val, temp_mac[2]; | |
1da177e4 | 343 | |
45993653 UKK |
344 | /* Whack a reset. We should wait for this. */ |
345 | writel(1, fep->hwp + FEC_ECNTRL); | |
346 | udelay(10); | |
1da177e4 | 347 | |
45993653 UKK |
348 | /* |
349 | * enet-mac reset will reset mac address registers too, | |
350 | * so need to reconfigure it. | |
351 | */ | |
352 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
353 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); | |
354 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
355 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
356 | } | |
1da177e4 | 357 | |
45993653 UKK |
358 | /* Clear any outstanding interrupt. */ |
359 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 360 | |
45993653 UKK |
361 | /* Reset all multicast. */ |
362 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
363 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
364 | #ifndef CONFIG_M5272 | |
365 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
366 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
367 | #endif | |
1da177e4 | 368 | |
45993653 UKK |
369 | /* Set maximum receive buffer size. */ |
370 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 371 | |
45993653 UKK |
372 | /* Set receive and transmit descriptor base. */ |
373 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
374 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, | |
375 | fep->hwp + FEC_X_DES_START); | |
376 | ||
377 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
378 | fep->cur_rx = fep->rx_bd_base; | |
379 | ||
380 | /* Reset SKB transmit buffers. */ | |
381 | fep->skb_cur = fep->skb_dirty = 0; | |
382 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { | |
383 | if (fep->tx_skbuff[i]) { | |
384 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
385 | fep->tx_skbuff[i] = NULL; | |
1da177e4 | 386 | } |
45993653 | 387 | } |
97b72e43 | 388 | |
45993653 UKK |
389 | /* Enable MII mode */ |
390 | if (duplex) { | |
391 | /* MII enable / FD enable */ | |
392 | writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); | |
393 | writel(0x04, fep->hwp + FEC_X_CNTRL); | |
394 | } else { | |
395 | /* MII enable / No Rcv on Xmit */ | |
396 | writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL); | |
397 | writel(0x0, fep->hwp + FEC_X_CNTRL); | |
398 | } | |
399 | fep->full_duplex = duplex; | |
400 | ||
401 | /* Set MII speed */ | |
402 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
403 | ||
404 | /* | |
405 | * The phy interface and speed need to get configured | |
406 | * differently on enet-mac. | |
407 | */ | |
408 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
409 | val = readl(fep->hwp + FEC_R_CNTRL); | |
410 | ||
411 | /* MII or RMII */ | |
412 | if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
413 | val |= (1 << 8); | |
414 | else | |
415 | val &= ~(1 << 8); | |
416 | ||
417 | /* 10M or 100M */ | |
418 | if (fep->phy_dev && fep->phy_dev->speed == SPEED_100) | |
419 | val &= ~(1 << 9); | |
420 | else | |
421 | val |= (1 << 9); | |
422 | ||
423 | writel(val, fep->hwp + FEC_R_CNTRL); | |
424 | } else { | |
425 | #ifdef FEC_MIIGSK_ENR | |
426 | if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) { | |
427 | /* disable the gasket and wait */ | |
428 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
429 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
430 | udelay(1); | |
431 | ||
432 | /* | |
433 | * configure the gasket: | |
434 | * RMII, 50 MHz, no loopback, no echo | |
435 | */ | |
436 | writel(1, fep->hwp + FEC_MIIGSK_CFGR); | |
437 | ||
438 | /* re-enable the gasket */ | |
439 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 440 | } |
45993653 UKK |
441 | #endif |
442 | } | |
3b2b74ca | 443 | |
45993653 UKK |
444 | /* And last, enable the transmit and receive processing */ |
445 | writel(2, fep->hwp + FEC_ECNTRL); | |
446 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
447 | ||
448 | /* Enable interrupts we wish to service */ | |
449 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
450 | } | |
451 | ||
452 | static void | |
453 | fec_stop(struct net_device *ndev) | |
454 | { | |
455 | struct fec_enet_private *fep = netdev_priv(ndev); | |
456 | ||
457 | /* We cannot expect a graceful transmit stop without link !!! */ | |
458 | if (fep->link) { | |
459 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
460 | udelay(10); | |
461 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
462 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | |
463 | } | |
464 | ||
465 | /* Whack a reset. We should wait for this. */ | |
466 | writel(1, fep->hwp + FEC_ECNTRL); | |
467 | udelay(10); | |
468 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
469 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
1da177e4 LT |
470 | } |
471 | ||
472 | ||
45993653 UKK |
473 | static void |
474 | fec_timeout(struct net_device *ndev) | |
475 | { | |
476 | struct fec_enet_private *fep = netdev_priv(ndev); | |
477 | ||
478 | ndev->stats.tx_errors++; | |
479 | ||
480 | fec_restart(ndev, fep->full_duplex); | |
481 | netif_wake_queue(ndev); | |
482 | } | |
483 | ||
1da177e4 | 484 | static void |
c556167f | 485 | fec_enet_tx(struct net_device *ndev) |
1da177e4 LT |
486 | { |
487 | struct fec_enet_private *fep; | |
2e28532f | 488 | struct bufdesc *bdp; |
0e702ab3 | 489 | unsigned short status; |
1da177e4 LT |
490 | struct sk_buff *skb; |
491 | ||
c556167f | 492 | fep = netdev_priv(ndev); |
81538e74 | 493 | spin_lock(&fep->hw_lock); |
1da177e4 LT |
494 | bdp = fep->dirty_tx; |
495 | ||
0e702ab3 | 496 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
f0b3fbea SH |
497 | if (bdp == fep->cur_tx && fep->tx_full == 0) |
498 | break; | |
499 | ||
c556167f | 500 | dma_unmap_single(&ndev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
f0b3fbea | 501 | bdp->cbd_bufaddr = 0; |
1da177e4 LT |
502 | |
503 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
504 | /* Check for errors. */ | |
0e702ab3 | 505 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
506 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
507 | BD_ENET_TX_CSL)) { | |
c556167f | 508 | ndev->stats.tx_errors++; |
0e702ab3 | 509 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 510 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 511 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 512 | ndev->stats.tx_window_errors++; |
0e702ab3 | 513 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 514 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 515 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 516 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 517 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 518 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 519 | } else { |
c556167f | 520 | ndev->stats.tx_packets++; |
1da177e4 LT |
521 | } |
522 | ||
0e702ab3 | 523 | if (status & BD_ENET_TX_READY) |
1da177e4 | 524 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
22f6b860 | 525 | |
1da177e4 LT |
526 | /* Deferred means some collisions occurred during transmit, |
527 | * but we eventually sent the packet OK. | |
528 | */ | |
0e702ab3 | 529 | if (status & BD_ENET_TX_DEF) |
c556167f | 530 | ndev->stats.collisions++; |
6aa20a22 | 531 | |
22f6b860 | 532 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 LT |
533 | dev_kfree_skb_any(skb); |
534 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
535 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 536 | |
22f6b860 | 537 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 538 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
539 | bdp = fep->tx_bd_base; |
540 | else | |
541 | bdp++; | |
6aa20a22 | 542 | |
22f6b860 | 543 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 LT |
544 | */ |
545 | if (fep->tx_full) { | |
546 | fep->tx_full = 0; | |
c556167f UKK |
547 | if (netif_queue_stopped(ndev)) |
548 | netif_wake_queue(ndev); | |
1da177e4 LT |
549 | } |
550 | } | |
2e28532f | 551 | fep->dirty_tx = bdp; |
81538e74 | 552 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
553 | } |
554 | ||
555 | ||
556 | /* During a receive, the cur_rx points to the current incoming buffer. | |
557 | * When we update through the ring, if the next incoming buffer has | |
558 | * not been given to the system, we just set the empty indicator, | |
559 | * effectively tossing the packet. | |
560 | */ | |
561 | static void | |
c556167f | 562 | fec_enet_rx(struct net_device *ndev) |
1da177e4 | 563 | { |
c556167f | 564 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
565 | const struct platform_device_id *id_entry = |
566 | platform_get_device_id(fep->pdev); | |
2e28532f | 567 | struct bufdesc *bdp; |
0e702ab3 | 568 | unsigned short status; |
1da177e4 LT |
569 | struct sk_buff *skb; |
570 | ushort pkt_len; | |
571 | __u8 *data; | |
6aa20a22 | 572 | |
0e702ab3 GU |
573 | #ifdef CONFIG_M532x |
574 | flush_cache_all(); | |
6aa20a22 | 575 | #endif |
1da177e4 | 576 | |
81538e74 | 577 | spin_lock(&fep->hw_lock); |
3b2b74ca | 578 | |
1da177e4 LT |
579 | /* First, grab all of the stats for the incoming packet. |
580 | * These get messed up if we get called due to a busy condition. | |
581 | */ | |
582 | bdp = fep->cur_rx; | |
583 | ||
22f6b860 | 584 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 585 | |
22f6b860 SH |
586 | /* Since we have allocated space to hold a complete frame, |
587 | * the last indicator should be set. | |
588 | */ | |
589 | if ((status & BD_ENET_RX_LAST) == 0) | |
590 | printk("FEC ENET: rcv is not +last\n"); | |
1da177e4 | 591 | |
22f6b860 SH |
592 | if (!fep->opened) |
593 | goto rx_processing_done; | |
1da177e4 | 594 | |
22f6b860 SH |
595 | /* Check for errors. */ |
596 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 597 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
c556167f | 598 | ndev->stats.rx_errors++; |
22f6b860 SH |
599 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
600 | /* Frame too long or too short. */ | |
c556167f | 601 | ndev->stats.rx_length_errors++; |
22f6b860 SH |
602 | } |
603 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
c556167f | 604 | ndev->stats.rx_frame_errors++; |
22f6b860 | 605 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 606 | ndev->stats.rx_crc_errors++; |
22f6b860 | 607 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
c556167f | 608 | ndev->stats.rx_fifo_errors++; |
1da177e4 | 609 | } |
1da177e4 | 610 | |
22f6b860 SH |
611 | /* Report late collisions as a frame error. |
612 | * On this error, the BD is closed, but we don't know what we | |
613 | * have in the buffer. So, just drop this frame on the floor. | |
614 | */ | |
615 | if (status & BD_ENET_RX_CL) { | |
c556167f UKK |
616 | ndev->stats.rx_errors++; |
617 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
618 | goto rx_processing_done; |
619 | } | |
1da177e4 | 620 | |
22f6b860 | 621 | /* Process the incoming frame. */ |
c556167f | 622 | ndev->stats.rx_packets++; |
22f6b860 | 623 | pkt_len = bdp->cbd_datlen; |
c556167f | 624 | ndev->stats.rx_bytes += pkt_len; |
22f6b860 | 625 | data = (__u8*)__va(bdp->cbd_bufaddr); |
1da177e4 | 626 | |
db8880bc UKK |
627 | dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen, |
628 | DMA_FROM_DEVICE); | |
ccdc4f19 | 629 | |
b5680e0b SG |
630 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
631 | swap_buffer(data, pkt_len); | |
632 | ||
22f6b860 SH |
633 | /* This does 16 byte alignment, exactly what we need. |
634 | * The packet length includes FCS, but we don't want to | |
635 | * include that when passing upstream as it messes up | |
636 | * bridging applications. | |
637 | */ | |
8549889c | 638 | skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 639 | |
8549889c | 640 | if (unlikely(!skb)) { |
22f6b860 | 641 | printk("%s: Memory squeeze, dropping packet.\n", |
c556167f UKK |
642 | ndev->name); |
643 | ndev->stats.rx_dropped++; | |
22f6b860 | 644 | } else { |
8549889c | 645 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 SH |
646 | skb_put(skb, pkt_len - 4); /* Make room */ |
647 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
c556167f | 648 | skb->protocol = eth_type_trans(skb, ndev); |
22f6b860 SH |
649 | netif_rx(skb); |
650 | } | |
f0b3fbea | 651 | |
db8880bc | 652 | bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen, |
f0b3fbea | 653 | DMA_FROM_DEVICE); |
22f6b860 SH |
654 | rx_processing_done: |
655 | /* Clear the status flags for this buffer */ | |
656 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 657 | |
22f6b860 SH |
658 | /* Mark the buffer empty */ |
659 | status |= BD_ENET_RX_EMPTY; | |
660 | bdp->cbd_sc = status; | |
6aa20a22 | 661 | |
22f6b860 SH |
662 | /* Update BD pointer to next entry */ |
663 | if (status & BD_ENET_RX_WRAP) | |
664 | bdp = fep->rx_bd_base; | |
665 | else | |
666 | bdp++; | |
667 | /* Doing this here will keep the FEC running while we process | |
668 | * incoming frames. On a heavily loaded network, we should be | |
669 | * able to keep up at the expense of system resources. | |
670 | */ | |
671 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
672 | } | |
2e28532f | 673 | fep->cur_rx = bdp; |
1da177e4 | 674 | |
81538e74 | 675 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
676 | } |
677 | ||
45993653 UKK |
678 | static irqreturn_t |
679 | fec_enet_interrupt(int irq, void *dev_id) | |
680 | { | |
681 | struct net_device *ndev = dev_id; | |
682 | struct fec_enet_private *fep = netdev_priv(ndev); | |
683 | uint int_events; | |
684 | irqreturn_t ret = IRQ_NONE; | |
685 | ||
686 | do { | |
687 | int_events = readl(fep->hwp + FEC_IEVENT); | |
688 | writel(int_events, fep->hwp + FEC_IEVENT); | |
689 | ||
690 | if (int_events & FEC_ENET_RXF) { | |
691 | ret = IRQ_HANDLED; | |
692 | fec_enet_rx(ndev); | |
693 | } | |
694 | ||
695 | /* Transmit OK, or non-fatal error. Update the buffer | |
696 | * descriptors. FEC handles all errors, we just discover | |
697 | * them as part of the transmit process. | |
698 | */ | |
699 | if (int_events & FEC_ENET_TXF) { | |
700 | ret = IRQ_HANDLED; | |
701 | fec_enet_tx(ndev); | |
702 | } | |
703 | ||
704 | if (int_events & FEC_ENET_MII) { | |
705 | ret = IRQ_HANDLED; | |
706 | complete(&fep->mdio_done); | |
707 | } | |
708 | } while (int_events); | |
709 | ||
710 | return ret; | |
711 | } | |
712 | ||
713 | ||
714 | ||
e6b043d5 | 715 | /* ------------------------------------------------------------------------- */ |
c556167f | 716 | static void __inline__ fec_get_mac(struct net_device *ndev) |
1da177e4 | 717 | { |
c556167f | 718 | struct fec_enet_private *fep = netdev_priv(ndev); |
49da97dc | 719 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 720 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 721 | |
49da97dc SG |
722 | /* |
723 | * try to get mac address in following order: | |
724 | * | |
725 | * 1) module parameter via kernel command line in form | |
726 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
727 | */ | |
728 | iap = macaddr; | |
729 | ||
730 | /* | |
731 | * 2) from flash or fuse (via platform data) | |
732 | */ | |
733 | if (!is_valid_ether_addr(iap)) { | |
734 | #ifdef CONFIG_M5272 | |
735 | if (FEC_FLASHMAC) | |
736 | iap = (unsigned char *)FEC_FLASHMAC; | |
737 | #else | |
738 | if (pdata) | |
739 | memcpy(iap, pdata->mac, ETH_ALEN); | |
740 | #endif | |
741 | } | |
742 | ||
743 | /* | |
744 | * 3) FEC mac registers set by bootloader | |
745 | */ | |
746 | if (!is_valid_ether_addr(iap)) { | |
747 | *((unsigned long *) &tmpaddr[0]) = | |
748 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
749 | *((unsigned short *) &tmpaddr[4]) = | |
750 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 751 | iap = &tmpaddr[0]; |
1da177e4 LT |
752 | } |
753 | ||
c556167f | 754 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 755 | |
49da97dc SG |
756 | /* Adjust MAC if using macaddr */ |
757 | if (iap == macaddr) | |
c556167f | 758 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id; |
1da177e4 LT |
759 | } |
760 | ||
e6b043d5 | 761 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 762 | |
e6b043d5 BW |
763 | /* |
764 | * Phy section | |
765 | */ | |
c556167f | 766 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 767 | { |
c556167f | 768 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 BW |
769 | struct phy_device *phy_dev = fep->phy_dev; |
770 | unsigned long flags; | |
1da177e4 | 771 | |
e6b043d5 | 772 | int status_change = 0; |
1da177e4 | 773 | |
e6b043d5 | 774 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 | 775 | |
e6b043d5 BW |
776 | /* Prevent a state halted on mii error */ |
777 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
778 | phy_dev->state = PHY_RESUMING; | |
779 | goto spin_unlock; | |
780 | } | |
1da177e4 | 781 | |
e6b043d5 BW |
782 | /* Duplex link change */ |
783 | if (phy_dev->link) { | |
784 | if (fep->full_duplex != phy_dev->duplex) { | |
c556167f | 785 | fec_restart(ndev, phy_dev->duplex); |
e6b043d5 BW |
786 | status_change = 1; |
787 | } | |
788 | } | |
1da177e4 | 789 | |
e6b043d5 BW |
790 | /* Link on or off change */ |
791 | if (phy_dev->link != fep->link) { | |
792 | fep->link = phy_dev->link; | |
793 | if (phy_dev->link) | |
c556167f | 794 | fec_restart(ndev, phy_dev->duplex); |
1da177e4 | 795 | else |
c556167f | 796 | fec_stop(ndev); |
e6b043d5 | 797 | status_change = 1; |
1da177e4 | 798 | } |
6aa20a22 | 799 | |
e6b043d5 BW |
800 | spin_unlock: |
801 | spin_unlock_irqrestore(&fep->hw_lock, flags); | |
1da177e4 | 802 | |
e6b043d5 BW |
803 | if (status_change) |
804 | phy_print_status(phy_dev); | |
805 | } | |
1da177e4 | 806 | |
e6b043d5 | 807 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 808 | { |
e6b043d5 | 809 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 810 | unsigned long time_left; |
1da177e4 | 811 | |
e6b043d5 | 812 | fep->mii_timeout = 0; |
97b72e43 | 813 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
814 | |
815 | /* start a read op */ | |
816 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
817 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
818 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
819 | ||
820 | /* wait for end of transfer */ | |
97b72e43 BS |
821 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
822 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
823 | if (time_left == 0) { | |
824 | fep->mii_timeout = 1; | |
825 | printk(KERN_ERR "FEC: MDIO read timeout\n"); | |
826 | return -ETIMEDOUT; | |
1da177e4 | 827 | } |
1da177e4 | 828 | |
e6b043d5 BW |
829 | /* return value */ |
830 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 831 | } |
6aa20a22 | 832 | |
e6b043d5 BW |
833 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
834 | u16 value) | |
1da177e4 | 835 | { |
e6b043d5 | 836 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 837 | unsigned long time_left; |
1da177e4 | 838 | |
e6b043d5 | 839 | fep->mii_timeout = 0; |
97b72e43 | 840 | init_completion(&fep->mdio_done); |
1da177e4 | 841 | |
862f0982 SG |
842 | /* start a write op */ |
843 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
844 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
845 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
846 | fep->hwp + FEC_MII_DATA); | |
847 | ||
848 | /* wait for end of transfer */ | |
97b72e43 BS |
849 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
850 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
851 | if (time_left == 0) { | |
852 | fep->mii_timeout = 1; | |
853 | printk(KERN_ERR "FEC: MDIO write timeout\n"); | |
854 | return -ETIMEDOUT; | |
e6b043d5 | 855 | } |
1da177e4 | 856 | |
e6b043d5 BW |
857 | return 0; |
858 | } | |
1da177e4 | 859 | |
e6b043d5 | 860 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 861 | { |
e6b043d5 | 862 | return 0; |
1da177e4 LT |
863 | } |
864 | ||
c556167f | 865 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 866 | { |
c556167f | 867 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 868 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
869 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
870 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
871 | int phy_id; | |
b5680e0b | 872 | int dev_id = fep->pdev->id; |
562d2f8c | 873 | |
418bd0d4 BW |
874 | fep->phy_dev = NULL; |
875 | ||
6fcc040f GU |
876 | /* check for attached phy */ |
877 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
878 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
879 | continue; | |
880 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
881 | continue; | |
882 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
883 | continue; | |
b5680e0b SG |
884 | if (dev_id--) |
885 | continue; | |
6fcc040f GU |
886 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
887 | break; | |
e6b043d5 | 888 | } |
1da177e4 | 889 | |
6fcc040f GU |
890 | if (phy_id >= PHY_MAX_ADDR) { |
891 | printk(KERN_INFO "%s: no PHY, assuming direct connection " | |
c556167f | 892 | "to switch\n", ndev->name); |
6fcc040f GU |
893 | strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); |
894 | phy_id = 0; | |
895 | } | |
896 | ||
897 | snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id); | |
c556167f | 898 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0, |
6fcc040f GU |
899 | PHY_INTERFACE_MODE_MII); |
900 | if (IS_ERR(phy_dev)) { | |
c556167f | 901 | printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name); |
6fcc040f | 902 | return PTR_ERR(phy_dev); |
e6b043d5 | 903 | } |
1da177e4 | 904 | |
e6b043d5 BW |
905 | /* mask with MAC supported features */ |
906 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
907 | phy_dev->advertising = phy_dev->supported; | |
1da177e4 | 908 | |
e6b043d5 BW |
909 | fep->phy_dev = phy_dev; |
910 | fep->link = 0; | |
911 | fep->full_duplex = 0; | |
1da177e4 | 912 | |
418bd0d4 | 913 | printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] " |
c556167f | 914 | "(mii_bus:phy_addr=%s, irq=%d)\n", ndev->name, |
418bd0d4 BW |
915 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), |
916 | fep->phy_dev->irq); | |
917 | ||
e6b043d5 | 918 | return 0; |
1da177e4 LT |
919 | } |
920 | ||
e6b043d5 | 921 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 922 | { |
b5680e0b | 923 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
924 | struct net_device *ndev = platform_get_drvdata(pdev); |
925 | struct fec_enet_private *fep = netdev_priv(ndev); | |
b5680e0b SG |
926 | const struct platform_device_id *id_entry = |
927 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 928 | int err = -ENXIO, i; |
6b265293 | 929 | |
b5680e0b SG |
930 | /* |
931 | * The dual fec interfaces are not equivalent with enet-mac. | |
932 | * Here are the differences: | |
933 | * | |
934 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
935 | * - fec0 acts as the 1588 time master while fec1 is slave | |
936 | * - external phys can only be configured by fec0 | |
937 | * | |
938 | * That is to say fec1 can not work independently. It only works | |
939 | * when fec0 is working. The reason behind this design is that the | |
940 | * second interface is added primarily for Switch mode. | |
941 | * | |
942 | * Because of the last point above, both phys are attached on fec0 | |
943 | * mdio interface in board design, and need to be configured by | |
944 | * fec0 mii_bus. | |
945 | */ | |
946 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) { | |
947 | /* fec1 uses fec0 mii_bus */ | |
948 | fep->mii_bus = fec0_mii_bus; | |
949 | return 0; | |
950 | } | |
951 | ||
e6b043d5 | 952 | fep->mii_timeout = 0; |
1da177e4 | 953 | |
e6b043d5 BW |
954 | /* |
955 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
956 | */ | |
957 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1; | |
958 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
1da177e4 | 959 | |
e6b043d5 BW |
960 | fep->mii_bus = mdiobus_alloc(); |
961 | if (fep->mii_bus == NULL) { | |
962 | err = -ENOMEM; | |
963 | goto err_out; | |
1da177e4 LT |
964 | } |
965 | ||
e6b043d5 BW |
966 | fep->mii_bus->name = "fec_enet_mii_bus"; |
967 | fep->mii_bus->read = fec_enet_mdio_read; | |
968 | fep->mii_bus->write = fec_enet_mdio_write; | |
969 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
6fcc040f | 970 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id + 1); |
e6b043d5 BW |
971 | fep->mii_bus->priv = fep; |
972 | fep->mii_bus->parent = &pdev->dev; | |
973 | ||
974 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
975 | if (!fep->mii_bus->irq) { | |
976 | err = -ENOMEM; | |
977 | goto err_out_free_mdiobus; | |
1da177e4 LT |
978 | } |
979 | ||
e6b043d5 BW |
980 | for (i = 0; i < PHY_MAX_ADDR; i++) |
981 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 982 | |
c556167f | 983 | platform_set_drvdata(ndev, fep->mii_bus); |
1da177e4 | 984 | |
e6b043d5 BW |
985 | if (mdiobus_register(fep->mii_bus)) |
986 | goto err_out_free_mdio_irq; | |
1da177e4 | 987 | |
b5680e0b SG |
988 | /* save fec0 mii_bus */ |
989 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
990 | fec0_mii_bus = fep->mii_bus; | |
991 | ||
e6b043d5 | 992 | return 0; |
1da177e4 | 993 | |
e6b043d5 BW |
994 | err_out_free_mdio_irq: |
995 | kfree(fep->mii_bus->irq); | |
996 | err_out_free_mdiobus: | |
997 | mdiobus_free(fep->mii_bus); | |
998 | err_out: | |
999 | return err; | |
1da177e4 LT |
1000 | } |
1001 | ||
e6b043d5 | 1002 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 1003 | { |
e6b043d5 BW |
1004 | if (fep->phy_dev) |
1005 | phy_disconnect(fep->phy_dev); | |
1006 | mdiobus_unregister(fep->mii_bus); | |
1007 | kfree(fep->mii_bus->irq); | |
1008 | mdiobus_free(fep->mii_bus); | |
1da177e4 LT |
1009 | } |
1010 | ||
c556167f | 1011 | static int fec_enet_get_settings(struct net_device *ndev, |
e6b043d5 | 1012 | struct ethtool_cmd *cmd) |
1da177e4 | 1013 | { |
c556167f | 1014 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1015 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1016 | |
e6b043d5 BW |
1017 | if (!phydev) |
1018 | return -ENODEV; | |
1da177e4 | 1019 | |
e6b043d5 | 1020 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
1021 | } |
1022 | ||
c556167f | 1023 | static int fec_enet_set_settings(struct net_device *ndev, |
e6b043d5 | 1024 | struct ethtool_cmd *cmd) |
1da177e4 | 1025 | { |
c556167f | 1026 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1027 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1028 | |
e6b043d5 BW |
1029 | if (!phydev) |
1030 | return -ENODEV; | |
1da177e4 | 1031 | |
e6b043d5 | 1032 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
1033 | } |
1034 | ||
c556167f | 1035 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 1036 | struct ethtool_drvinfo *info) |
1da177e4 | 1037 | { |
c556167f | 1038 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 1039 | |
e6b043d5 BW |
1040 | strcpy(info->driver, fep->pdev->dev.driver->name); |
1041 | strcpy(info->version, "Revision: 1.0"); | |
c556167f | 1042 | strcpy(info->bus_info, dev_name(&ndev->dev)); |
1da177e4 LT |
1043 | } |
1044 | ||
e6b043d5 BW |
1045 | static struct ethtool_ops fec_enet_ethtool_ops = { |
1046 | .get_settings = fec_enet_get_settings, | |
1047 | .set_settings = fec_enet_set_settings, | |
1048 | .get_drvinfo = fec_enet_get_drvinfo, | |
1049 | .get_link = ethtool_op_get_link, | |
1050 | }; | |
1da177e4 | 1051 | |
c556167f | 1052 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 1053 | { |
c556167f | 1054 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1055 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1056 | |
c556167f | 1057 | if (!netif_running(ndev)) |
e6b043d5 | 1058 | return -EINVAL; |
1da177e4 | 1059 | |
e6b043d5 BW |
1060 | if (!phydev) |
1061 | return -ENODEV; | |
1062 | ||
28b04113 | 1063 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
1064 | } |
1065 | ||
c556167f | 1066 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 1067 | { |
c556167f | 1068 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea SH |
1069 | int i; |
1070 | struct sk_buff *skb; | |
1071 | struct bufdesc *bdp; | |
1072 | ||
1073 | bdp = fep->rx_bd_base; | |
1074 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1075 | skb = fep->rx_skbuff[i]; | |
1076 | ||
1077 | if (bdp->cbd_bufaddr) | |
c556167f | 1078 | dma_unmap_single(&ndev->dev, bdp->cbd_bufaddr, |
f0b3fbea SH |
1079 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1080 | if (skb) | |
1081 | dev_kfree_skb(skb); | |
1082 | bdp++; | |
1083 | } | |
1084 | ||
1085 | bdp = fep->tx_bd_base; | |
1086 | for (i = 0; i < TX_RING_SIZE; i++) | |
1087 | kfree(fep->tx_bounce[i]); | |
1088 | } | |
1089 | ||
c556167f | 1090 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
f0b3fbea | 1091 | { |
c556167f | 1092 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea SH |
1093 | int i; |
1094 | struct sk_buff *skb; | |
1095 | struct bufdesc *bdp; | |
1096 | ||
1097 | bdp = fep->rx_bd_base; | |
1098 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1099 | skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE); | |
1100 | if (!skb) { | |
c556167f | 1101 | fec_enet_free_buffers(ndev); |
f0b3fbea SH |
1102 | return -ENOMEM; |
1103 | } | |
1104 | fep->rx_skbuff[i] = skb; | |
1105 | ||
c556167f | 1106 | bdp->cbd_bufaddr = dma_map_single(&ndev->dev, skb->data, |
f0b3fbea SH |
1107 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1108 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
1109 | bdp++; | |
1110 | } | |
1111 | ||
1112 | /* Set the last buffer to wrap. */ | |
1113 | bdp--; | |
1114 | bdp->cbd_sc |= BD_SC_WRAP; | |
1115 | ||
1116 | bdp = fep->tx_bd_base; | |
1117 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1118 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
1119 | ||
1120 | bdp->cbd_sc = 0; | |
1121 | bdp->cbd_bufaddr = 0; | |
1122 | bdp++; | |
1123 | } | |
1124 | ||
1125 | /* Set the last buffer to wrap. */ | |
1126 | bdp--; | |
1127 | bdp->cbd_sc |= BD_SC_WRAP; | |
1128 | ||
1129 | return 0; | |
1130 | } | |
1131 | ||
1da177e4 | 1132 | static int |
c556167f | 1133 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 1134 | { |
c556167f | 1135 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1136 | int ret; |
1da177e4 LT |
1137 | |
1138 | /* I should reset the ring buffers here, but I don't yet know | |
1139 | * a simple way to do that. | |
1140 | */ | |
1da177e4 | 1141 | |
c556167f | 1142 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea SH |
1143 | if (ret) |
1144 | return ret; | |
1145 | ||
418bd0d4 | 1146 | /* Probe and connect to PHY when open the interface */ |
c556167f | 1147 | ret = fec_enet_mii_probe(ndev); |
418bd0d4 | 1148 | if (ret) { |
c556167f | 1149 | fec_enet_free_buffers(ndev); |
418bd0d4 BW |
1150 | return ret; |
1151 | } | |
e6b043d5 | 1152 | phy_start(fep->phy_dev); |
c556167f | 1153 | netif_start_queue(ndev); |
1da177e4 | 1154 | fep->opened = 1; |
22f6b860 | 1155 | return 0; |
1da177e4 LT |
1156 | } |
1157 | ||
1158 | static int | |
c556167f | 1159 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 1160 | { |
c556167f | 1161 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 1162 | |
22f6b860 | 1163 | /* Don't know what to do yet. */ |
1da177e4 | 1164 | fep->opened = 0; |
c556167f UKK |
1165 | netif_stop_queue(ndev); |
1166 | fec_stop(ndev); | |
1da177e4 | 1167 | |
e497ba82 UKK |
1168 | if (fep->phy_dev) { |
1169 | phy_stop(fep->phy_dev); | |
418bd0d4 | 1170 | phy_disconnect(fep->phy_dev); |
e497ba82 | 1171 | } |
418bd0d4 | 1172 | |
db8880bc | 1173 | fec_enet_free_buffers(ndev); |
f0b3fbea | 1174 | |
1da177e4 LT |
1175 | return 0; |
1176 | } | |
1177 | ||
1da177e4 LT |
1178 | /* Set or clear the multicast filter for this adaptor. |
1179 | * Skeleton taken from sunlance driver. | |
1180 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1181 | * MAC address filtering. Some of the drivers check to make sure it is | |
1182 | * a group multicast address, and discard those that are not. I guess I | |
1183 | * will do the same for now, but just remove the test if you want | |
1184 | * individual filtering as well (do the upper net layers want or support | |
1185 | * this kind of feature?). | |
1186 | */ | |
1187 | ||
1188 | #define HASH_BITS 6 /* #bits in hash */ | |
1189 | #define CRC32_POLY 0xEDB88320 | |
1190 | ||
c556167f | 1191 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 1192 | { |
c556167f | 1193 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 1194 | struct netdev_hw_addr *ha; |
48e2f183 | 1195 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1196 | unsigned char hash; |
1197 | ||
c556167f | 1198 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
1199 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1200 | tmp |= 0x8; | |
1201 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1202 | return; |
1203 | } | |
1da177e4 | 1204 | |
4e831836 SH |
1205 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1206 | tmp &= ~0x8; | |
1207 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1208 | ||
c556167f | 1209 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
1210 | /* Catch all multicast addresses, so set the |
1211 | * filter to all 1's | |
1212 | */ | |
1213 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1214 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1215 | ||
1216 | return; | |
1217 | } | |
1218 | ||
1219 | /* Clear filter and add the addresses in hash register | |
1220 | */ | |
1221 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1222 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1223 | ||
c556167f | 1224 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 | 1225 | /* Only support group multicast for now */ |
22bedad3 | 1226 | if (!(ha->addr[0] & 1)) |
4e831836 SH |
1227 | continue; |
1228 | ||
1229 | /* calculate crc32 value of mac address */ | |
1230 | crc = 0xffffffff; | |
1231 | ||
c556167f | 1232 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 1233 | data = ha->addr[i]; |
4e831836 SH |
1234 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1235 | crc = (crc >> 1) ^ | |
1236 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1237 | } |
1238 | } | |
4e831836 SH |
1239 | |
1240 | /* only upper 6 bits (HASH_BITS) are used | |
1241 | * which point to specific bit in he hash registers | |
1242 | */ | |
1243 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1244 | ||
1245 | if (hash > 31) { | |
1246 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1247 | tmp |= 1 << (hash - 32); | |
1248 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1249 | } else { | |
1250 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1251 | tmp |= 1 << hash; | |
1252 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1253 | } | |
1da177e4 LT |
1254 | } |
1255 | } | |
1256 | ||
22f6b860 | 1257 | /* Set a MAC change in hardware. */ |
009fda83 | 1258 | static int |
c556167f | 1259 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 1260 | { |
c556167f | 1261 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
1262 | struct sockaddr *addr = p; |
1263 | ||
1264 | if (!is_valid_ether_addr(addr->sa_data)) | |
1265 | return -EADDRNOTAVAIL; | |
1266 | ||
c556167f | 1267 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); |
1da177e4 | 1268 | |
c556167f UKK |
1269 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
1270 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 1271 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 1272 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 1273 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1274 | return 0; |
1da177e4 LT |
1275 | } |
1276 | ||
009fda83 SH |
1277 | static const struct net_device_ops fec_netdev_ops = { |
1278 | .ndo_open = fec_enet_open, | |
1279 | .ndo_stop = fec_enet_close, | |
1280 | .ndo_start_xmit = fec_enet_start_xmit, | |
1281 | .ndo_set_multicast_list = set_multicast_list, | |
635ecaa7 | 1282 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1283 | .ndo_validate_addr = eth_validate_addr, |
1284 | .ndo_tx_timeout = fec_timeout, | |
1285 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 1286 | .ndo_do_ioctl = fec_enet_ioctl, |
009fda83 SH |
1287 | }; |
1288 | ||
1da177e4 LT |
1289 | /* |
1290 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1291 | * |
1da177e4 | 1292 | */ |
c556167f | 1293 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 1294 | { |
c556167f | 1295 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1296 | struct bufdesc *cbd_base; |
633e7533 | 1297 | struct bufdesc *bdp; |
f0b3fbea | 1298 | int i; |
1da177e4 | 1299 | |
8d4dd5cf SH |
1300 | /* Allocate memory for buffer descriptors. */ |
1301 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
1302 | GFP_KERNEL); | |
1303 | if (!cbd_base) { | |
562d2f8c GU |
1304 | printk("FEC: allocate descriptor memory failed?\n"); |
1305 | return -ENOMEM; | |
1306 | } | |
1307 | ||
3b2b74ca | 1308 | spin_lock_init(&fep->hw_lock); |
3b2b74ca | 1309 | |
c556167f | 1310 | fep->netdev = ndev; |
1da177e4 | 1311 | |
49da97dc | 1312 | /* Get the Ethernet address */ |
c556167f | 1313 | fec_get_mac(ndev); |
1da177e4 | 1314 | |
8d4dd5cf | 1315 | /* Set receive and transmit descriptor base. */ |
1da177e4 LT |
1316 | fep->rx_bd_base = cbd_base; |
1317 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1318 | ||
22f6b860 | 1319 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
1320 | ndev->watchdog_timeo = TX_TIMEOUT; |
1321 | ndev->netdev_ops = &fec_netdev_ops; | |
1322 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 RH |
1323 | |
1324 | /* Initialize the receive buffer descriptors. */ | |
1325 | bdp = fep->rx_bd_base; | |
1326 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1327 | ||
1328 | /* Initialize the BD for every fragment in the page. */ | |
1329 | bdp->cbd_sc = 0; | |
1330 | bdp++; | |
1331 | } | |
1332 | ||
1333 | /* Set the last buffer to wrap */ | |
1334 | bdp--; | |
1335 | bdp->cbd_sc |= BD_SC_WRAP; | |
1336 | ||
1337 | /* ...and the same for transmit */ | |
1338 | bdp = fep->tx_bd_base; | |
1339 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1340 | ||
1341 | /* Initialize the BD for every fragment in the page. */ | |
1342 | bdp->cbd_sc = 0; | |
1343 | bdp->cbd_bufaddr = 0; | |
1344 | bdp++; | |
1345 | } | |
1346 | ||
1347 | /* Set the last buffer to wrap */ | |
1348 | bdp--; | |
1349 | bdp->cbd_sc |= BD_SC_WRAP; | |
1350 | ||
c556167f | 1351 | fec_restart(ndev, 0); |
1da177e4 | 1352 | |
1da177e4 LT |
1353 | return 0; |
1354 | } | |
1355 | ||
ead73183 SH |
1356 | static int __devinit |
1357 | fec_probe(struct platform_device *pdev) | |
1358 | { | |
1359 | struct fec_enet_private *fep; | |
5eb32bd0 | 1360 | struct fec_platform_data *pdata; |
ead73183 SH |
1361 | struct net_device *ndev; |
1362 | int i, irq, ret = 0; | |
1363 | struct resource *r; | |
1364 | ||
1365 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1366 | if (!r) | |
1367 | return -ENXIO; | |
1368 | ||
1369 | r = request_mem_region(r->start, resource_size(r), pdev->name); | |
1370 | if (!r) | |
1371 | return -EBUSY; | |
1372 | ||
1373 | /* Init network device */ | |
1374 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
28e2188e UKK |
1375 | if (!ndev) { |
1376 | ret = -ENOMEM; | |
1377 | goto failed_alloc_etherdev; | |
1378 | } | |
ead73183 SH |
1379 | |
1380 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1381 | ||
1382 | /* setup board info structure */ | |
1383 | fep = netdev_priv(ndev); | |
ead73183 | 1384 | |
24e531b4 | 1385 | fep->hwp = ioremap(r->start, resource_size(r)); |
e6b043d5 | 1386 | fep->pdev = pdev; |
ead73183 | 1387 | |
24e531b4 | 1388 | if (!fep->hwp) { |
ead73183 SH |
1389 | ret = -ENOMEM; |
1390 | goto failed_ioremap; | |
1391 | } | |
1392 | ||
1393 | platform_set_drvdata(pdev, ndev); | |
1394 | ||
5eb32bd0 BS |
1395 | pdata = pdev->dev.platform_data; |
1396 | if (pdata) | |
1397 | fep->phy_interface = pdata->phy; | |
1398 | ||
ead73183 SH |
1399 | /* This device has up to three irqs on some platforms */ |
1400 | for (i = 0; i < 3; i++) { | |
1401 | irq = platform_get_irq(pdev, i); | |
1402 | if (i && irq < 0) | |
1403 | break; | |
1404 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
1405 | if (ret) { | |
b2b09ad6 | 1406 | while (--i >= 0) { |
ead73183 SH |
1407 | irq = platform_get_irq(pdev, i); |
1408 | free_irq(irq, ndev); | |
ead73183 SH |
1409 | } |
1410 | goto failed_irq; | |
1411 | } | |
1412 | } | |
1413 | ||
1414 | fep->clk = clk_get(&pdev->dev, "fec_clk"); | |
1415 | if (IS_ERR(fep->clk)) { | |
1416 | ret = PTR_ERR(fep->clk); | |
1417 | goto failed_clk; | |
1418 | } | |
1419 | clk_enable(fep->clk); | |
1420 | ||
8649a230 | 1421 | ret = fec_enet_init(ndev); |
ead73183 SH |
1422 | if (ret) |
1423 | goto failed_init; | |
1424 | ||
e6b043d5 BW |
1425 | ret = fec_enet_mii_init(pdev); |
1426 | if (ret) | |
1427 | goto failed_mii_init; | |
1428 | ||
03c698c9 OS |
1429 | /* Carrier starts down, phylib will bring it up */ |
1430 | netif_carrier_off(ndev); | |
1431 | ||
ead73183 SH |
1432 | ret = register_netdev(ndev); |
1433 | if (ret) | |
1434 | goto failed_register; | |
1435 | ||
1436 | return 0; | |
1437 | ||
1438 | failed_register: | |
e6b043d5 BW |
1439 | fec_enet_mii_remove(fep); |
1440 | failed_mii_init: | |
ead73183 SH |
1441 | failed_init: |
1442 | clk_disable(fep->clk); | |
1443 | clk_put(fep->clk); | |
1444 | failed_clk: | |
1445 | for (i = 0; i < 3; i++) { | |
1446 | irq = platform_get_irq(pdev, i); | |
1447 | if (irq > 0) | |
1448 | free_irq(irq, ndev); | |
1449 | } | |
1450 | failed_irq: | |
24e531b4 | 1451 | iounmap(fep->hwp); |
ead73183 SH |
1452 | failed_ioremap: |
1453 | free_netdev(ndev); | |
28e2188e UKK |
1454 | failed_alloc_etherdev: |
1455 | release_mem_region(r->start, resource_size(r)); | |
ead73183 SH |
1456 | |
1457 | return ret; | |
1458 | } | |
1459 | ||
1460 | static int __devexit | |
1461 | fec_drv_remove(struct platform_device *pdev) | |
1462 | { | |
1463 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1464 | struct fec_enet_private *fep = netdev_priv(ndev); | |
28e2188e | 1465 | struct resource *r; |
ead73183 SH |
1466 | |
1467 | platform_set_drvdata(pdev, NULL); | |
1468 | ||
1469 | fec_stop(ndev); | |
e6b043d5 | 1470 | fec_enet_mii_remove(fep); |
ead73183 SH |
1471 | clk_disable(fep->clk); |
1472 | clk_put(fep->clk); | |
24e531b4 | 1473 | iounmap(fep->hwp); |
ead73183 SH |
1474 | unregister_netdev(ndev); |
1475 | free_netdev(ndev); | |
28e2188e UKK |
1476 | |
1477 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1478 | BUG_ON(!r); | |
1479 | release_mem_region(r->start, resource_size(r)); | |
1480 | ||
ead73183 SH |
1481 | return 0; |
1482 | } | |
1483 | ||
59d4289b | 1484 | #ifdef CONFIG_PM |
ead73183 | 1485 | static int |
87cad5c3 | 1486 | fec_suspend(struct device *dev) |
ead73183 | 1487 | { |
87cad5c3 | 1488 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1489 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1490 | |
04e5216d UKK |
1491 | if (netif_running(ndev)) { |
1492 | fec_stop(ndev); | |
1493 | netif_device_detach(ndev); | |
ead73183 | 1494 | } |
04e5216d UKK |
1495 | clk_disable(fep->clk); |
1496 | ||
ead73183 SH |
1497 | return 0; |
1498 | } | |
1499 | ||
1500 | static int | |
87cad5c3 | 1501 | fec_resume(struct device *dev) |
ead73183 | 1502 | { |
87cad5c3 | 1503 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1504 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1505 | |
04e5216d UKK |
1506 | clk_enable(fep->clk); |
1507 | if (netif_running(ndev)) { | |
1508 | fec_restart(ndev, fep->full_duplex); | |
1509 | netif_device_attach(ndev); | |
ead73183 | 1510 | } |
04e5216d | 1511 | |
ead73183 SH |
1512 | return 0; |
1513 | } | |
1514 | ||
59d4289b DK |
1515 | static const struct dev_pm_ops fec_pm_ops = { |
1516 | .suspend = fec_suspend, | |
1517 | .resume = fec_resume, | |
1518 | .freeze = fec_suspend, | |
1519 | .thaw = fec_resume, | |
1520 | .poweroff = fec_suspend, | |
1521 | .restore = fec_resume, | |
1522 | }; | |
87cad5c3 | 1523 | #endif |
59d4289b | 1524 | |
ead73183 SH |
1525 | static struct platform_driver fec_driver = { |
1526 | .driver = { | |
b5680e0b | 1527 | .name = DRIVER_NAME, |
87cad5c3 EB |
1528 | .owner = THIS_MODULE, |
1529 | #ifdef CONFIG_PM | |
1530 | .pm = &fec_pm_ops, | |
1531 | #endif | |
ead73183 | 1532 | }, |
b5680e0b | 1533 | .id_table = fec_devtype, |
87cad5c3 EB |
1534 | .probe = fec_probe, |
1535 | .remove = __devexit_p(fec_drv_remove), | |
ead73183 SH |
1536 | }; |
1537 | ||
1538 | static int __init | |
1539 | fec_enet_module_init(void) | |
1540 | { | |
1541 | printk(KERN_INFO "FEC Ethernet Driver\n"); | |
1542 | ||
1543 | return platform_driver_register(&fec_driver); | |
1544 | } | |
1545 | ||
1546 | static void __exit | |
1547 | fec_enet_cleanup(void) | |
1548 | { | |
1549 | platform_driver_unregister(&fec_driver); | |
1550 | } | |
1551 | ||
1552 | module_exit(fec_enet_cleanup); | |
1da177e4 LT |
1553 | module_init(fec_enet_module_init); |
1554 | ||
1555 | MODULE_LICENSE("GPL"); |