Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * forcedeth: Ethernet driver for NVIDIA nForce media access controllers. | |
3 | * | |
4 | * Note: This driver is a cleanroom reimplementation based on reverse | |
5 | * engineered documentation written by Carl-Daniel Hailfinger | |
87046e50 | 6 | * and Andrew de Quincey. |
1da177e4 LT |
7 | * |
8 | * NVIDIA, nForce and other NVIDIA marks are trademarks or registered | |
9 | * trademarks of NVIDIA Corporation in the United States and other | |
10 | * countries. | |
11 | * | |
1836098f | 12 | * Copyright (C) 2003,4,5 Manfred Spraul |
1da177e4 LT |
13 | * Copyright (C) 2004 Andrew de Quincey (wol support) |
14 | * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane | |
15 | * IRQ rate fixes, bigendian fixes, cleanups, verification) | |
f1405d32 | 16 | * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation |
1da177e4 LT |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
31 | * | |
1da177e4 LT |
32 | * Known bugs: |
33 | * We suspect that on some hardware no TX done interrupts are generated. | |
34 | * This means recovery from netif_stop_queue only happens if the hw timer | |
35 | * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) | |
36 | * and the timer is active in the IRQMask, or if a rx packet arrives by chance. | |
37 | * If your hardware reliably generates tx done interrupts, then you can remove | |
38 | * DEV_NEED_TIMERIRQ from the driver_data flags. | |
39 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few | |
40 | * superfluous timer interrupts from the nic. | |
41 | */ | |
294a554e JP |
42 | |
43 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
44 | ||
3e1a3ce2 | 45 | #define FORCEDETH_VERSION "0.64" |
1da177e4 LT |
46 | #define DRV_NAME "forcedeth" |
47 | ||
48 | #include <linux/module.h> | |
49 | #include <linux/types.h> | |
50 | #include <linux/pci.h> | |
51 | #include <linux/interrupt.h> | |
52 | #include <linux/netdevice.h> | |
53 | #include <linux/etherdevice.h> | |
54 | #include <linux/delay.h> | |
d43c36dc | 55 | #include <linux/sched.h> |
1da177e4 LT |
56 | #include <linux/spinlock.h> |
57 | #include <linux/ethtool.h> | |
58 | #include <linux/timer.h> | |
59 | #include <linux/skbuff.h> | |
60 | #include <linux/mii.h> | |
61 | #include <linux/random.h> | |
62 | #include <linux/init.h> | |
22c6d143 | 63 | #include <linux/if_vlan.h> |
910638ae | 64 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 65 | #include <linux/slab.h> |
5504e139 SJ |
66 | #include <linux/uaccess.h> |
67 | #include <linux/io.h> | |
1da177e4 LT |
68 | |
69 | #include <asm/irq.h> | |
1da177e4 LT |
70 | #include <asm/system.h> |
71 | ||
bea3348e SH |
72 | #define TX_WORK_PER_LOOP 64 |
73 | #define RX_WORK_PER_LOOP 64 | |
1da177e4 LT |
74 | |
75 | /* | |
76 | * Hardware access: | |
77 | */ | |
78 | ||
3c2e1c11 AA |
79 | #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */ |
80 | #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */ | |
81 | #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */ | |
82 | #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */ | |
83 | #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */ | |
84 | #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */ | |
85 | #define DEV_HAS_MSI 0x0000040 /* device supports MSI */ | |
86 | #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */ | |
87 | #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */ | |
88 | #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */ | |
7b5e078c MD |
89 | #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */ |
90 | #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */ | |
91 | #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */ | |
92 | #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */ | |
3c2e1c11 AA |
93 | #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */ |
94 | #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */ | |
95 | #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */ | |
96 | #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */ | |
97 | #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */ | |
98 | #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */ | |
99 | #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */ | |
100 | #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */ | |
101 | #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */ | |
102 | #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */ | |
103 | #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */ | |
104 | #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */ | |
105 | #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */ | |
1da177e4 LT |
106 | |
107 | enum { | |
108 | NvRegIrqStatus = 0x000, | |
109 | #define NVREG_IRQSTAT_MIIEVENT 0x040 | |
daa91a9d | 110 | #define NVREG_IRQSTAT_MASK 0x83ff |
1da177e4 LT |
111 | NvRegIrqMask = 0x004, |
112 | #define NVREG_IRQ_RX_ERROR 0x0001 | |
113 | #define NVREG_IRQ_RX 0x0002 | |
114 | #define NVREG_IRQ_RX_NOBUF 0x0004 | |
115 | #define NVREG_IRQ_TX_ERR 0x0008 | |
c2dba06d | 116 | #define NVREG_IRQ_TX_OK 0x0010 |
1da177e4 LT |
117 | #define NVREG_IRQ_TIMER 0x0020 |
118 | #define NVREG_IRQ_LINK 0x0040 | |
d33a73c8 AA |
119 | #define NVREG_IRQ_RX_FORCED 0x0080 |
120 | #define NVREG_IRQ_TX_FORCED 0x0100 | |
daa91a9d | 121 | #define NVREG_IRQ_RECOVER_ERROR 0x8200 |
a971c324 | 122 | #define NVREG_IRQMASK_THROUGHPUT 0x00df |
096a458c | 123 | #define NVREG_IRQMASK_CPU 0x0060 |
d33a73c8 AA |
124 | #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
125 | #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) | |
c5cf9101 | 126 | #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR) |
c2dba06d | 127 | |
1da177e4 LT |
128 | NvRegUnknownSetupReg6 = 0x008, |
129 | #define NVREG_UNKSETUP6_VAL 3 | |
130 | ||
131 | /* | |
132 | * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic | |
133 | * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms | |
134 | */ | |
135 | NvRegPollingInterval = 0x00c, | |
6cef67a0 | 136 | #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */ |
a971c324 | 137 | #define NVREG_POLL_DEFAULT_CPU 13 |
d33a73c8 AA |
138 | NvRegMSIMap0 = 0x020, |
139 | NvRegMSIMap1 = 0x024, | |
140 | NvRegMSIIrqMask = 0x030, | |
141 | #define NVREG_MSI_VECTOR_0_ENABLED 0x01 | |
1da177e4 | 142 | NvRegMisc1 = 0x080, |
eb91f61b | 143 | #define NVREG_MISC1_PAUSE_TX 0x01 |
1da177e4 LT |
144 | #define NVREG_MISC1_HD 0x02 |
145 | #define NVREG_MISC1_FORCE 0x3b0f3c | |
146 | ||
0a62677b | 147 | NvRegMacReset = 0x34, |
86a0f043 | 148 | #define NVREG_MAC_RESET_ASSERT 0x0F3 |
1da177e4 LT |
149 | NvRegTransmitterControl = 0x084, |
150 | #define NVREG_XMITCTL_START 0x01 | |
7e680c22 AA |
151 | #define NVREG_XMITCTL_MGMT_ST 0x40000000 |
152 | #define NVREG_XMITCTL_SYNC_MASK 0x000f0000 | |
153 | #define NVREG_XMITCTL_SYNC_NOT_READY 0x0 | |
154 | #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000 | |
155 | #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00 | |
156 | #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0 | |
157 | #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000 | |
158 | #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000 | |
159 | #define NVREG_XMITCTL_HOST_LOADED 0x00004000 | |
f35723ec | 160 | #define NVREG_XMITCTL_TX_PATH_EN 0x01000000 |
cac1c52c AA |
161 | #define NVREG_XMITCTL_DATA_START 0x00100000 |
162 | #define NVREG_XMITCTL_DATA_READY 0x00010000 | |
163 | #define NVREG_XMITCTL_DATA_ERROR 0x00020000 | |
1da177e4 LT |
164 | NvRegTransmitterStatus = 0x088, |
165 | #define NVREG_XMITSTAT_BUSY 0x01 | |
166 | ||
167 | NvRegPacketFilterFlags = 0x8c, | |
eb91f61b AA |
168 | #define NVREG_PFF_PAUSE_RX 0x08 |
169 | #define NVREG_PFF_ALWAYS 0x7F0000 | |
1da177e4 LT |
170 | #define NVREG_PFF_PROMISC 0x80 |
171 | #define NVREG_PFF_MYADDR 0x20 | |
9589c77a | 172 | #define NVREG_PFF_LOOPBACK 0x10 |
1da177e4 LT |
173 | |
174 | NvRegOffloadConfig = 0x90, | |
175 | #define NVREG_OFFLOAD_HOMEPHY 0x601 | |
176 | #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE | |
177 | NvRegReceiverControl = 0x094, | |
178 | #define NVREG_RCVCTL_START 0x01 | |
f35723ec | 179 | #define NVREG_RCVCTL_RX_PATH_EN 0x01000000 |
1da177e4 LT |
180 | NvRegReceiverStatus = 0x98, |
181 | #define NVREG_RCVSTAT_BUSY 0x01 | |
182 | ||
a433686c AA |
183 | NvRegSlotTime = 0x9c, |
184 | #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000 | |
185 | #define NVREG_SLOTTIME_10_100_FULL 0x00007f00 | |
78aea4fc | 186 | #define NVREG_SLOTTIME_1000_FULL 0x0003ff00 |
a433686c | 187 | #define NVREG_SLOTTIME_HALF 0x0000ff00 |
78aea4fc | 188 | #define NVREG_SLOTTIME_DEFAULT 0x00007f00 |
a433686c | 189 | #define NVREG_SLOTTIME_MASK 0x000000ff |
1da177e4 | 190 | |
9744e218 | 191 | NvRegTxDeferral = 0xA0, |
fd9b558c AA |
192 | #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f |
193 | #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f | |
194 | #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f | |
195 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f | |
196 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f | |
197 | #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000 | |
9744e218 AA |
198 | NvRegRxDeferral = 0xA4, |
199 | #define NVREG_RX_DEFERRAL_DEFAULT 0x16 | |
1da177e4 LT |
200 | NvRegMacAddrA = 0xA8, |
201 | NvRegMacAddrB = 0xAC, | |
202 | NvRegMulticastAddrA = 0xB0, | |
203 | #define NVREG_MCASTADDRA_FORCE 0x01 | |
204 | NvRegMulticastAddrB = 0xB4, | |
205 | NvRegMulticastMaskA = 0xB8, | |
bb9a4fd1 | 206 | #define NVREG_MCASTMASKA_NONE 0xffffffff |
1da177e4 | 207 | NvRegMulticastMaskB = 0xBC, |
bb9a4fd1 | 208 | #define NVREG_MCASTMASKB_NONE 0xffff |
1da177e4 LT |
209 | |
210 | NvRegPhyInterface = 0xC0, | |
211 | #define PHY_RGMII 0x10000000 | |
a433686c AA |
212 | NvRegBackOffControl = 0xC4, |
213 | #define NVREG_BKOFFCTRL_DEFAULT 0x70000000 | |
214 | #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff | |
215 | #define NVREG_BKOFFCTRL_SELECT 24 | |
216 | #define NVREG_BKOFFCTRL_GEAR 12 | |
1da177e4 LT |
217 | |
218 | NvRegTxRingPhysAddr = 0x100, | |
219 | NvRegRxRingPhysAddr = 0x104, | |
220 | NvRegRingSizes = 0x108, | |
221 | #define NVREG_RINGSZ_TXSHIFT 0 | |
222 | #define NVREG_RINGSZ_RXSHIFT 16 | |
5070d340 AA |
223 | NvRegTransmitPoll = 0x10c, |
224 | #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000 | |
1da177e4 LT |
225 | NvRegLinkSpeed = 0x110, |
226 | #define NVREG_LINKSPEED_FORCE 0x10000 | |
227 | #define NVREG_LINKSPEED_10 1000 | |
228 | #define NVREG_LINKSPEED_100 100 | |
229 | #define NVREG_LINKSPEED_1000 50 | |
230 | #define NVREG_LINKSPEED_MASK (0xFFF) | |
231 | NvRegUnknownSetupReg5 = 0x130, | |
232 | #define NVREG_UNKSETUP5_BIT31 (1<<31) | |
95d161cb AA |
233 | NvRegTxWatermark = 0x13c, |
234 | #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 | |
235 | #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000 | |
236 | #define NVREG_TX_WM_DESC2_3_1000 0xfe08000 | |
1da177e4 LT |
237 | NvRegTxRxControl = 0x144, |
238 | #define NVREG_TXRXCTL_KICK 0x0001 | |
239 | #define NVREG_TXRXCTL_BIT1 0x0002 | |
240 | #define NVREG_TXRXCTL_BIT2 0x0004 | |
241 | #define NVREG_TXRXCTL_IDLE 0x0008 | |
242 | #define NVREG_TXRXCTL_RESET 0x0010 | |
243 | #define NVREG_TXRXCTL_RXCHECK 0x0400 | |
8a4ae7f2 | 244 | #define NVREG_TXRXCTL_DESC_1 0 |
d2f78412 AA |
245 | #define NVREG_TXRXCTL_DESC_2 0x002100 |
246 | #define NVREG_TXRXCTL_DESC_3 0xc02200 | |
ee407b02 AA |
247 | #define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
248 | #define NVREG_TXRXCTL_VLANINS 0x00080 | |
0832b25a AA |
249 | NvRegTxRingPhysAddrHigh = 0x148, |
250 | NvRegRxRingPhysAddrHigh = 0x14C, | |
eb91f61b | 251 | NvRegTxPauseFrame = 0x170, |
5289b4c4 AA |
252 | #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080 |
253 | #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010 | |
254 | #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0 | |
255 | #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880 | |
9a33e883 AA |
256 | NvRegTxPauseFrameLimit = 0x174, |
257 | #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000 | |
1da177e4 LT |
258 | NvRegMIIStatus = 0x180, |
259 | #define NVREG_MIISTAT_ERROR 0x0001 | |
260 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 | |
eb798428 AA |
261 | #define NVREG_MIISTAT_MASK_RW 0x0007 |
262 | #define NVREG_MIISTAT_MASK_ALL 0x000f | |
7e680c22 AA |
263 | NvRegMIIMask = 0x184, |
264 | #define NVREG_MII_LINKCHANGE 0x0008 | |
1da177e4 LT |
265 | |
266 | NvRegAdapterControl = 0x188, | |
267 | #define NVREG_ADAPTCTL_START 0x02 | |
268 | #define NVREG_ADAPTCTL_LINKUP 0x04 | |
269 | #define NVREG_ADAPTCTL_PHYVALID 0x40000 | |
270 | #define NVREG_ADAPTCTL_RUNNING 0x100000 | |
271 | #define NVREG_ADAPTCTL_PHYSHIFT 24 | |
272 | NvRegMIISpeed = 0x18c, | |
273 | #define NVREG_MIISPEED_BIT8 (1<<8) | |
274 | #define NVREG_MIIDELAY 5 | |
275 | NvRegMIIControl = 0x190, | |
276 | #define NVREG_MIICTL_INUSE 0x08000 | |
277 | #define NVREG_MIICTL_WRITE 0x00400 | |
278 | #define NVREG_MIICTL_ADDRSHIFT 5 | |
279 | NvRegMIIData = 0x194, | |
9c662435 AA |
280 | NvRegTxUnicast = 0x1a0, |
281 | NvRegTxMulticast = 0x1a4, | |
282 | NvRegTxBroadcast = 0x1a8, | |
1da177e4 LT |
283 | NvRegWakeUpFlags = 0x200, |
284 | #define NVREG_WAKEUPFLAGS_VAL 0x7770 | |
285 | #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 | |
286 | #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 | |
287 | #define NVREG_WAKEUPFLAGS_D3SHIFT 12 | |
288 | #define NVREG_WAKEUPFLAGS_D2SHIFT 8 | |
289 | #define NVREG_WAKEUPFLAGS_D1SHIFT 4 | |
290 | #define NVREG_WAKEUPFLAGS_D0SHIFT 0 | |
291 | #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 | |
292 | #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 | |
293 | #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 | |
294 | #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 | |
295 | ||
cac1c52c | 296 | NvRegMgmtUnitGetVersion = 0x204, |
78aea4fc | 297 | #define NVREG_MGMTUNITGETVERSION 0x01 |
cac1c52c AA |
298 | NvRegMgmtUnitVersion = 0x208, |
299 | #define NVREG_MGMTUNITVERSION 0x08 | |
1da177e4 LT |
300 | NvRegPowerCap = 0x268, |
301 | #define NVREG_POWERCAP_D3SUPP (1<<30) | |
302 | #define NVREG_POWERCAP_D2SUPP (1<<26) | |
303 | #define NVREG_POWERCAP_D1SUPP (1<<25) | |
304 | NvRegPowerState = 0x26c, | |
305 | #define NVREG_POWERSTATE_POWEREDUP 0x8000 | |
306 | #define NVREG_POWERSTATE_VALID 0x0100 | |
307 | #define NVREG_POWERSTATE_MASK 0x0003 | |
308 | #define NVREG_POWERSTATE_D0 0x0000 | |
309 | #define NVREG_POWERSTATE_D1 0x0001 | |
310 | #define NVREG_POWERSTATE_D2 0x0002 | |
311 | #define NVREG_POWERSTATE_D3 0x0003 | |
cac1c52c AA |
312 | NvRegMgmtUnitControl = 0x278, |
313 | #define NVREG_MGMTUNITCONTROL_INUSE 0x20000 | |
52da3578 AA |
314 | NvRegTxCnt = 0x280, |
315 | NvRegTxZeroReXmt = 0x284, | |
316 | NvRegTxOneReXmt = 0x288, | |
317 | NvRegTxManyReXmt = 0x28c, | |
318 | NvRegTxLateCol = 0x290, | |
319 | NvRegTxUnderflow = 0x294, | |
320 | NvRegTxLossCarrier = 0x298, | |
321 | NvRegTxExcessDef = 0x29c, | |
322 | NvRegTxRetryErr = 0x2a0, | |
323 | NvRegRxFrameErr = 0x2a4, | |
324 | NvRegRxExtraByte = 0x2a8, | |
325 | NvRegRxLateCol = 0x2ac, | |
326 | NvRegRxRunt = 0x2b0, | |
327 | NvRegRxFrameTooLong = 0x2b4, | |
328 | NvRegRxOverflow = 0x2b8, | |
329 | NvRegRxFCSErr = 0x2bc, | |
330 | NvRegRxFrameAlignErr = 0x2c0, | |
331 | NvRegRxLenErr = 0x2c4, | |
332 | NvRegRxUnicast = 0x2c8, | |
333 | NvRegRxMulticast = 0x2cc, | |
334 | NvRegRxBroadcast = 0x2d0, | |
335 | NvRegTxDef = 0x2d4, | |
336 | NvRegTxFrame = 0x2d8, | |
337 | NvRegRxCnt = 0x2dc, | |
338 | NvRegTxPause = 0x2e0, | |
339 | NvRegRxPause = 0x2e4, | |
340 | NvRegRxDropFrame = 0x2e8, | |
ee407b02 AA |
341 | NvRegVlanControl = 0x300, |
342 | #define NVREG_VLANCONTROL_ENABLE 0x2000 | |
d33a73c8 AA |
343 | NvRegMSIXMap0 = 0x3e0, |
344 | NvRegMSIXMap1 = 0x3e4, | |
345 | NvRegMSIXIrqStatus = 0x3f0, | |
86a0f043 AA |
346 | |
347 | NvRegPowerState2 = 0x600, | |
1545e205 | 348 | #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15 |
86a0f043 | 349 | #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 |
22ae03a1 | 350 | #define NVREG_POWERSTATE2_PHY_RESET 0x0004 |
88d7d8b0 | 351 | #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00 |
1da177e4 LT |
352 | }; |
353 | ||
354 | /* Big endian: should work, but is untested */ | |
355 | struct ring_desc { | |
a8bed49e SH |
356 | __le32 buf; |
357 | __le32 flaglen; | |
1da177e4 LT |
358 | }; |
359 | ||
ee73362c | 360 | struct ring_desc_ex { |
a8bed49e SH |
361 | __le32 bufhigh; |
362 | __le32 buflow; | |
363 | __le32 txvlan; | |
364 | __le32 flaglen; | |
ee73362c MS |
365 | }; |
366 | ||
f82a9352 | 367 | union ring_type { |
78aea4fc SJ |
368 | struct ring_desc *orig; |
369 | struct ring_desc_ex *ex; | |
f82a9352 | 370 | }; |
ee73362c | 371 | |
1da177e4 LT |
372 | #define FLAG_MASK_V1 0xffff0000 |
373 | #define FLAG_MASK_V2 0xffffc000 | |
374 | #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) | |
375 | #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) | |
376 | ||
377 | #define NV_TX_LASTPACKET (1<<16) | |
378 | #define NV_TX_RETRYERROR (1<<19) | |
a433686c | 379 | #define NV_TX_RETRYCOUNT_MASK (0xF<<20) |
c2dba06d | 380 | #define NV_TX_FORCED_INTERRUPT (1<<24) |
1da177e4 LT |
381 | #define NV_TX_DEFERRED (1<<26) |
382 | #define NV_TX_CARRIERLOST (1<<27) | |
383 | #define NV_TX_LATECOLLISION (1<<28) | |
384 | #define NV_TX_UNDERFLOW (1<<29) | |
385 | #define NV_TX_ERROR (1<<30) | |
386 | #define NV_TX_VALID (1<<31) | |
387 | ||
388 | #define NV_TX2_LASTPACKET (1<<29) | |
389 | #define NV_TX2_RETRYERROR (1<<18) | |
a433686c | 390 | #define NV_TX2_RETRYCOUNT_MASK (0xF<<19) |
c2dba06d | 391 | #define NV_TX2_FORCED_INTERRUPT (1<<30) |
1da177e4 LT |
392 | #define NV_TX2_DEFERRED (1<<25) |
393 | #define NV_TX2_CARRIERLOST (1<<26) | |
394 | #define NV_TX2_LATECOLLISION (1<<27) | |
395 | #define NV_TX2_UNDERFLOW (1<<28) | |
396 | /* error and valid are the same for both */ | |
397 | #define NV_TX2_ERROR (1<<30) | |
398 | #define NV_TX2_VALID (1<<31) | |
ac9c1897 AA |
399 | #define NV_TX2_TSO (1<<28) |
400 | #define NV_TX2_TSO_SHIFT 14 | |
fa45459e AA |
401 | #define NV_TX2_TSO_MAX_SHIFT 14 |
402 | #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT) | |
8a4ae7f2 MS |
403 | #define NV_TX2_CHECKSUM_L3 (1<<27) |
404 | #define NV_TX2_CHECKSUM_L4 (1<<26) | |
1da177e4 | 405 | |
ee407b02 AA |
406 | #define NV_TX3_VLAN_TAG_PRESENT (1<<18) |
407 | ||
1da177e4 LT |
408 | #define NV_RX_DESCRIPTORVALID (1<<16) |
409 | #define NV_RX_MISSEDFRAME (1<<17) | |
410 | #define NV_RX_SUBSTRACT1 (1<<18) | |
411 | #define NV_RX_ERROR1 (1<<23) | |
412 | #define NV_RX_ERROR2 (1<<24) | |
413 | #define NV_RX_ERROR3 (1<<25) | |
414 | #define NV_RX_ERROR4 (1<<26) | |
415 | #define NV_RX_CRCERR (1<<27) | |
416 | #define NV_RX_OVERFLOW (1<<28) | |
417 | #define NV_RX_FRAMINGERR (1<<29) | |
418 | #define NV_RX_ERROR (1<<30) | |
419 | #define NV_RX_AVAIL (1<<31) | |
1ef6841b | 420 | #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR) |
1da177e4 LT |
421 | |
422 | #define NV_RX2_CHECKSUMMASK (0x1C000000) | |
bfaffe8f AA |
423 | #define NV_RX2_CHECKSUM_IP (0x10000000) |
424 | #define NV_RX2_CHECKSUM_IP_TCP (0x14000000) | |
425 | #define NV_RX2_CHECKSUM_IP_UDP (0x18000000) | |
1da177e4 LT |
426 | #define NV_RX2_DESCRIPTORVALID (1<<29) |
427 | #define NV_RX2_SUBSTRACT1 (1<<25) | |
428 | #define NV_RX2_ERROR1 (1<<18) | |
429 | #define NV_RX2_ERROR2 (1<<19) | |
430 | #define NV_RX2_ERROR3 (1<<20) | |
431 | #define NV_RX2_ERROR4 (1<<21) | |
432 | #define NV_RX2_CRCERR (1<<22) | |
433 | #define NV_RX2_OVERFLOW (1<<23) | |
434 | #define NV_RX2_FRAMINGERR (1<<24) | |
435 | /* error and avail are the same for both */ | |
436 | #define NV_RX2_ERROR (1<<30) | |
437 | #define NV_RX2_AVAIL (1<<31) | |
1ef6841b | 438 | #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR) |
1da177e4 | 439 | |
ee407b02 AA |
440 | #define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
441 | #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) | |
442 | ||
25985edc | 443 | /* Miscellaneous hardware related defines: */ |
78aea4fc SJ |
444 | #define NV_PCI_REGSZ_VER1 0x270 |
445 | #define NV_PCI_REGSZ_VER2 0x2d4 | |
446 | #define NV_PCI_REGSZ_VER3 0x604 | |
447 | #define NV_PCI_REGSZ_MAX 0x604 | |
1da177e4 LT |
448 | |
449 | /* various timeout delays: all in usec */ | |
450 | #define NV_TXRX_RESET_DELAY 4 | |
451 | #define NV_TXSTOP_DELAY1 10 | |
452 | #define NV_TXSTOP_DELAY1MAX 500000 | |
453 | #define NV_TXSTOP_DELAY2 100 | |
454 | #define NV_RXSTOP_DELAY1 10 | |
455 | #define NV_RXSTOP_DELAY1MAX 500000 | |
456 | #define NV_RXSTOP_DELAY2 100 | |
457 | #define NV_SETUP5_DELAY 5 | |
458 | #define NV_SETUP5_DELAYMAX 50000 | |
459 | #define NV_POWERUP_DELAY 5 | |
460 | #define NV_POWERUP_DELAYMAX 5000 | |
461 | #define NV_MIIBUSY_DELAY 50 | |
462 | #define NV_MIIPHY_DELAY 10 | |
463 | #define NV_MIIPHY_DELAYMAX 10000 | |
86a0f043 | 464 | #define NV_MAC_RESET_DELAY 64 |
1da177e4 LT |
465 | |
466 | #define NV_WAKEUPPATTERNS 5 | |
467 | #define NV_WAKEUPMASKENTRIES 4 | |
468 | ||
469 | /* General driver defaults */ | |
470 | #define NV_WATCHDOG_TIMEO (5*HZ) | |
471 | ||
6cef67a0 | 472 | #define RX_RING_DEFAULT 512 |
eafa59f6 AA |
473 | #define TX_RING_DEFAULT 256 |
474 | #define RX_RING_MIN 128 | |
475 | #define TX_RING_MIN 64 | |
476 | #define RING_MAX_DESC_VER_1 1024 | |
477 | #define RING_MAX_DESC_VER_2_3 16384 | |
1da177e4 LT |
478 | |
479 | /* rx/tx mac addr + type + vlan + align + slack*/ | |
d81c0983 MS |
480 | #define NV_RX_HEADERS (64) |
481 | /* even more slack. */ | |
482 | #define NV_RX_ALLOC_PAD (64) | |
483 | ||
484 | /* maximum mtu size */ | |
485 | #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */ | |
486 | #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */ | |
1da177e4 LT |
487 | |
488 | #define OOM_REFILL (1+HZ/20) | |
489 | #define POLL_WAIT (1+HZ/100) | |
490 | #define LINK_TIMEOUT (3*HZ) | |
52da3578 | 491 | #define STATS_INTERVAL (10*HZ) |
1da177e4 | 492 | |
f3b197ac | 493 | /* |
1da177e4 | 494 | * desc_ver values: |
8a4ae7f2 MS |
495 | * The nic supports three different descriptor types: |
496 | * - DESC_VER_1: Original | |
497 | * - DESC_VER_2: support for jumbo frames. | |
498 | * - DESC_VER_3: 64-bit format. | |
1da177e4 | 499 | */ |
8a4ae7f2 MS |
500 | #define DESC_VER_1 1 |
501 | #define DESC_VER_2 2 | |
502 | #define DESC_VER_3 3 | |
1da177e4 LT |
503 | |
504 | /* PHY defines */ | |
9f3f7910 AA |
505 | #define PHY_OUI_MARVELL 0x5043 |
506 | #define PHY_OUI_CICADA 0x03f1 | |
507 | #define PHY_OUI_VITESSE 0x01c1 | |
508 | #define PHY_OUI_REALTEK 0x0732 | |
509 | #define PHY_OUI_REALTEK2 0x0020 | |
1da177e4 LT |
510 | #define PHYID1_OUI_MASK 0x03ff |
511 | #define PHYID1_OUI_SHFT 6 | |
512 | #define PHYID2_OUI_MASK 0xfc00 | |
513 | #define PHYID2_OUI_SHFT 10 | |
edf7e5ec | 514 | #define PHYID2_MODEL_MASK 0x03f0 |
9f3f7910 AA |
515 | #define PHY_MODEL_REALTEK_8211 0x0110 |
516 | #define PHY_REV_MASK 0x0001 | |
517 | #define PHY_REV_REALTEK_8211B 0x0000 | |
518 | #define PHY_REV_REALTEK_8211C 0x0001 | |
519 | #define PHY_MODEL_REALTEK_8201 0x0200 | |
520 | #define PHY_MODEL_MARVELL_E3016 0x0220 | |
edf7e5ec | 521 | #define PHY_MARVELL_E3016_INITMASK 0x0300 |
14a67f3c AA |
522 | #define PHY_CICADA_INIT1 0x0f000 |
523 | #define PHY_CICADA_INIT2 0x0e00 | |
524 | #define PHY_CICADA_INIT3 0x01000 | |
525 | #define PHY_CICADA_INIT4 0x0200 | |
526 | #define PHY_CICADA_INIT5 0x0004 | |
527 | #define PHY_CICADA_INIT6 0x02000 | |
d215d8a2 AA |
528 | #define PHY_VITESSE_INIT_REG1 0x1f |
529 | #define PHY_VITESSE_INIT_REG2 0x10 | |
530 | #define PHY_VITESSE_INIT_REG3 0x11 | |
531 | #define PHY_VITESSE_INIT_REG4 0x12 | |
532 | #define PHY_VITESSE_INIT_MSK1 0xc | |
533 | #define PHY_VITESSE_INIT_MSK2 0x0180 | |
534 | #define PHY_VITESSE_INIT1 0x52b5 | |
535 | #define PHY_VITESSE_INIT2 0xaf8a | |
536 | #define PHY_VITESSE_INIT3 0x8 | |
537 | #define PHY_VITESSE_INIT4 0x8f8a | |
538 | #define PHY_VITESSE_INIT5 0xaf86 | |
539 | #define PHY_VITESSE_INIT6 0x8f86 | |
540 | #define PHY_VITESSE_INIT7 0xaf82 | |
541 | #define PHY_VITESSE_INIT8 0x0100 | |
542 | #define PHY_VITESSE_INIT9 0x8f82 | |
543 | #define PHY_VITESSE_INIT10 0x0 | |
c5e3ae88 AA |
544 | #define PHY_REALTEK_INIT_REG1 0x1f |
545 | #define PHY_REALTEK_INIT_REG2 0x19 | |
546 | #define PHY_REALTEK_INIT_REG3 0x13 | |
9f3f7910 AA |
547 | #define PHY_REALTEK_INIT_REG4 0x14 |
548 | #define PHY_REALTEK_INIT_REG5 0x18 | |
549 | #define PHY_REALTEK_INIT_REG6 0x11 | |
22ae03a1 | 550 | #define PHY_REALTEK_INIT_REG7 0x01 |
c5e3ae88 AA |
551 | #define PHY_REALTEK_INIT1 0x0000 |
552 | #define PHY_REALTEK_INIT2 0x8e00 | |
553 | #define PHY_REALTEK_INIT3 0x0001 | |
554 | #define PHY_REALTEK_INIT4 0xad17 | |
9f3f7910 AA |
555 | #define PHY_REALTEK_INIT5 0xfb54 |
556 | #define PHY_REALTEK_INIT6 0xf5c7 | |
557 | #define PHY_REALTEK_INIT7 0x1000 | |
558 | #define PHY_REALTEK_INIT8 0x0003 | |
22ae03a1 AA |
559 | #define PHY_REALTEK_INIT9 0x0008 |
560 | #define PHY_REALTEK_INIT10 0x0005 | |
561 | #define PHY_REALTEK_INIT11 0x0200 | |
9f3f7910 | 562 | #define PHY_REALTEK_INIT_MSK1 0x0003 |
d215d8a2 | 563 | |
1da177e4 LT |
564 | #define PHY_GIGABIT 0x0100 |
565 | ||
566 | #define PHY_TIMEOUT 0x1 | |
567 | #define PHY_ERROR 0x2 | |
568 | ||
569 | #define PHY_100 0x1 | |
570 | #define PHY_1000 0x2 | |
571 | #define PHY_HALF 0x100 | |
572 | ||
eb91f61b AA |
573 | #define NV_PAUSEFRAME_RX_CAPABLE 0x0001 |
574 | #define NV_PAUSEFRAME_TX_CAPABLE 0x0002 | |
575 | #define NV_PAUSEFRAME_RX_ENABLE 0x0004 | |
576 | #define NV_PAUSEFRAME_TX_ENABLE 0x0008 | |
b6d0773f AA |
577 | #define NV_PAUSEFRAME_RX_REQ 0x0010 |
578 | #define NV_PAUSEFRAME_TX_REQ 0x0020 | |
579 | #define NV_PAUSEFRAME_AUTONEG 0x0040 | |
1da177e4 | 580 | |
d33a73c8 AA |
581 | /* MSI/MSI-X defines */ |
582 | #define NV_MSI_X_MAX_VECTORS 8 | |
583 | #define NV_MSI_X_VECTORS_MASK 0x000f | |
584 | #define NV_MSI_CAPABLE 0x0010 | |
585 | #define NV_MSI_X_CAPABLE 0x0020 | |
586 | #define NV_MSI_ENABLED 0x0040 | |
587 | #define NV_MSI_X_ENABLED 0x0080 | |
588 | ||
589 | #define NV_MSI_X_VECTOR_ALL 0x0 | |
590 | #define NV_MSI_X_VECTOR_RX 0x0 | |
591 | #define NV_MSI_X_VECTOR_TX 0x1 | |
592 | #define NV_MSI_X_VECTOR_OTHER 0x2 | |
1da177e4 | 593 | |
b6e4405b AA |
594 | #define NV_MSI_PRIV_OFFSET 0x68 |
595 | #define NV_MSI_PRIV_VALUE 0xffffffff | |
596 | ||
b2976d23 AA |
597 | #define NV_RESTART_TX 0x1 |
598 | #define NV_RESTART_RX 0x2 | |
599 | ||
3b446c3e AA |
600 | #define NV_TX_LIMIT_COUNT 16 |
601 | ||
4145ade2 AA |
602 | #define NV_DYNAMIC_THRESHOLD 4 |
603 | #define NV_DYNAMIC_MAX_QUIET_COUNT 2048 | |
604 | ||
52da3578 AA |
605 | /* statistics */ |
606 | struct nv_ethtool_str { | |
607 | char name[ETH_GSTRING_LEN]; | |
608 | }; | |
609 | ||
610 | static const struct nv_ethtool_str nv_estats_str[] = { | |
611 | { "tx_bytes" }, | |
612 | { "tx_zero_rexmt" }, | |
613 | { "tx_one_rexmt" }, | |
614 | { "tx_many_rexmt" }, | |
615 | { "tx_late_collision" }, | |
616 | { "tx_fifo_errors" }, | |
617 | { "tx_carrier_errors" }, | |
618 | { "tx_excess_deferral" }, | |
619 | { "tx_retry_error" }, | |
52da3578 AA |
620 | { "rx_frame_error" }, |
621 | { "rx_extra_byte" }, | |
622 | { "rx_late_collision" }, | |
623 | { "rx_runt" }, | |
624 | { "rx_frame_too_long" }, | |
625 | { "rx_over_errors" }, | |
626 | { "rx_crc_errors" }, | |
627 | { "rx_frame_align_error" }, | |
628 | { "rx_length_error" }, | |
629 | { "rx_unicast" }, | |
630 | { "rx_multicast" }, | |
631 | { "rx_broadcast" }, | |
57fff698 AA |
632 | { "rx_packets" }, |
633 | { "rx_errors_total" }, | |
634 | { "tx_errors_total" }, | |
635 | ||
636 | /* version 2 stats */ | |
637 | { "tx_deferral" }, | |
638 | { "tx_packets" }, | |
52da3578 | 639 | { "rx_bytes" }, |
57fff698 | 640 | { "tx_pause" }, |
52da3578 | 641 | { "rx_pause" }, |
9c662435 AA |
642 | { "rx_drop_frame" }, |
643 | ||
644 | /* version 3 stats */ | |
645 | { "tx_unicast" }, | |
646 | { "tx_multicast" }, | |
647 | { "tx_broadcast" } | |
52da3578 AA |
648 | }; |
649 | ||
650 | struct nv_ethtool_stats { | |
651 | u64 tx_bytes; | |
652 | u64 tx_zero_rexmt; | |
653 | u64 tx_one_rexmt; | |
654 | u64 tx_many_rexmt; | |
655 | u64 tx_late_collision; | |
656 | u64 tx_fifo_errors; | |
657 | u64 tx_carrier_errors; | |
658 | u64 tx_excess_deferral; | |
659 | u64 tx_retry_error; | |
52da3578 AA |
660 | u64 rx_frame_error; |
661 | u64 rx_extra_byte; | |
662 | u64 rx_late_collision; | |
663 | u64 rx_runt; | |
664 | u64 rx_frame_too_long; | |
665 | u64 rx_over_errors; | |
666 | u64 rx_crc_errors; | |
667 | u64 rx_frame_align_error; | |
668 | u64 rx_length_error; | |
669 | u64 rx_unicast; | |
670 | u64 rx_multicast; | |
671 | u64 rx_broadcast; | |
57fff698 AA |
672 | u64 rx_packets; |
673 | u64 rx_errors_total; | |
674 | u64 tx_errors_total; | |
675 | ||
676 | /* version 2 stats */ | |
677 | u64 tx_deferral; | |
678 | u64 tx_packets; | |
52da3578 | 679 | u64 rx_bytes; |
57fff698 | 680 | u64 tx_pause; |
52da3578 AA |
681 | u64 rx_pause; |
682 | u64 rx_drop_frame; | |
9c662435 AA |
683 | |
684 | /* version 3 stats */ | |
685 | u64 tx_unicast; | |
686 | u64 tx_multicast; | |
687 | u64 tx_broadcast; | |
52da3578 AA |
688 | }; |
689 | ||
9c662435 AA |
690 | #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64)) |
691 | #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3) | |
57fff698 AA |
692 | #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6) |
693 | ||
9589c77a AA |
694 | /* diagnostics */ |
695 | #define NV_TEST_COUNT_BASE 3 | |
696 | #define NV_TEST_COUNT_EXTENDED 4 | |
697 | ||
698 | static const struct nv_ethtool_str nv_etests_str[] = { | |
699 | { "link (online/offline)" }, | |
700 | { "register (offline) " }, | |
701 | { "interrupt (offline) " }, | |
702 | { "loopback (offline) " } | |
703 | }; | |
704 | ||
705 | struct register_test { | |
5bb7ea26 AV |
706 | __u32 reg; |
707 | __u32 mask; | |
9589c77a AA |
708 | }; |
709 | ||
710 | static const struct register_test nv_registers_test[] = { | |
711 | { NvRegUnknownSetupReg6, 0x01 }, | |
712 | { NvRegMisc1, 0x03c }, | |
713 | { NvRegOffloadConfig, 0x03ff }, | |
714 | { NvRegMulticastAddrA, 0xffffffff }, | |
95d161cb | 715 | { NvRegTxWatermark, 0x0ff }, |
9589c77a | 716 | { NvRegWakeUpFlags, 0x07777 }, |
78aea4fc | 717 | { 0, 0 } |
9589c77a AA |
718 | }; |
719 | ||
761fcd9e AA |
720 | struct nv_skb_map { |
721 | struct sk_buff *skb; | |
722 | dma_addr_t dma; | |
73a37079 ED |
723 | unsigned int dma_len:31; |
724 | unsigned int dma_single:1; | |
3b446c3e AA |
725 | struct ring_desc_ex *first_tx_desc; |
726 | struct nv_skb_map *next_tx_ctx; | |
761fcd9e AA |
727 | }; |
728 | ||
1da177e4 LT |
729 | /* |
730 | * SMP locking: | |
b74ca3a8 | 731 | * All hardware access under netdev_priv(dev)->lock, except the performance |
1da177e4 LT |
732 | * critical parts: |
733 | * - rx is (pseudo-) lockless: it relies on the single-threading provided | |
734 | * by the arch code for interrupts. | |
932ff279 | 735 | * - tx setup is lockless: it relies on netif_tx_lock. Actual submission |
b74ca3a8 | 736 | * needs netdev_priv(dev)->lock :-( |
932ff279 | 737 | * - set_multicast_list: preparation lockless, relies on netif_tx_lock. |
1da177e4 LT |
738 | */ |
739 | ||
740 | /* in dev: base, irq */ | |
741 | struct fe_priv { | |
742 | spinlock_t lock; | |
743 | ||
bea3348e SH |
744 | struct net_device *dev; |
745 | struct napi_struct napi; | |
746 | ||
1da177e4 LT |
747 | /* General data: |
748 | * Locking: spin_lock(&np->lock); */ | |
52da3578 | 749 | struct nv_ethtool_stats estats; |
1da177e4 LT |
750 | int in_shutdown; |
751 | u32 linkspeed; | |
752 | int duplex; | |
753 | int autoneg; | |
754 | int fixed_mode; | |
755 | int phyaddr; | |
756 | int wolenabled; | |
757 | unsigned int phy_oui; | |
edf7e5ec | 758 | unsigned int phy_model; |
9f3f7910 | 759 | unsigned int phy_rev; |
1da177e4 | 760 | u16 gigabit; |
9589c77a | 761 | int intr_test; |
c5cf9101 | 762 | int recover_error; |
4145ade2 | 763 | int quiet_count; |
1da177e4 LT |
764 | |
765 | /* General data: RO fields */ | |
766 | dma_addr_t ring_addr; | |
767 | struct pci_dev *pci_dev; | |
768 | u32 orig_mac[2]; | |
582806be | 769 | u32 events; |
1da177e4 LT |
770 | u32 irqmask; |
771 | u32 desc_ver; | |
8a4ae7f2 | 772 | u32 txrxctl_bits; |
ee407b02 | 773 | u32 vlanctl_bits; |
86a0f043 | 774 | u32 driver_data; |
9f3f7910 | 775 | u32 device_id; |
86a0f043 | 776 | u32 register_size; |
7e680c22 | 777 | u32 mac_in_use; |
cac1c52c AA |
778 | int mgmt_version; |
779 | int mgmt_sema; | |
1da177e4 LT |
780 | |
781 | void __iomem *base; | |
782 | ||
783 | /* rx specific fields. | |
784 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
785 | */ | |
761fcd9e AA |
786 | union ring_type get_rx, put_rx, first_rx, last_rx; |
787 | struct nv_skb_map *get_rx_ctx, *put_rx_ctx; | |
788 | struct nv_skb_map *first_rx_ctx, *last_rx_ctx; | |
789 | struct nv_skb_map *rx_skb; | |
790 | ||
f82a9352 | 791 | union ring_type rx_ring; |
1da177e4 | 792 | unsigned int rx_buf_sz; |
d81c0983 | 793 | unsigned int pkt_limit; |
1da177e4 LT |
794 | struct timer_list oom_kick; |
795 | struct timer_list nic_poll; | |
52da3578 | 796 | struct timer_list stats_poll; |
d33a73c8 | 797 | u32 nic_poll_irq; |
eafa59f6 | 798 | int rx_ring_size; |
1da177e4 LT |
799 | |
800 | /* media detection workaround. | |
801 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
802 | */ | |
803 | int need_linktimer; | |
804 | unsigned long link_timeout; | |
805 | /* | |
806 | * tx specific fields. | |
807 | */ | |
761fcd9e AA |
808 | union ring_type get_tx, put_tx, first_tx, last_tx; |
809 | struct nv_skb_map *get_tx_ctx, *put_tx_ctx; | |
810 | struct nv_skb_map *first_tx_ctx, *last_tx_ctx; | |
811 | struct nv_skb_map *tx_skb; | |
812 | ||
f82a9352 | 813 | union ring_type tx_ring; |
1da177e4 | 814 | u32 tx_flags; |
eafa59f6 | 815 | int tx_ring_size; |
3b446c3e AA |
816 | int tx_limit; |
817 | u32 tx_pkts_in_progress; | |
818 | struct nv_skb_map *tx_change_owner; | |
819 | struct nv_skb_map *tx_end_flip; | |
aaa37d2d | 820 | int tx_stop; |
ee407b02 AA |
821 | |
822 | /* vlan fields */ | |
823 | struct vlan_group *vlangrp; | |
d33a73c8 AA |
824 | |
825 | /* msi/msi-x fields */ | |
826 | u32 msi_flags; | |
827 | struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; | |
eb91f61b AA |
828 | |
829 | /* flow control */ | |
830 | u32 pause_flags; | |
1a1ca861 TD |
831 | |
832 | /* power saved state */ | |
833 | u32 saved_config_space[NV_PCI_REGSZ_MAX/4]; | |
ddb213f0 YL |
834 | |
835 | /* for different msi-x irq type */ | |
836 | char name_rx[IFNAMSIZ + 3]; /* -rx */ | |
837 | char name_tx[IFNAMSIZ + 3]; /* -tx */ | |
838 | char name_other[IFNAMSIZ + 6]; /* -other */ | |
1da177e4 LT |
839 | }; |
840 | ||
841 | /* | |
842 | * Maximum number of loops until we assume that a bit in the irq mask | |
843 | * is stuck. Overridable with module param. | |
844 | */ | |
4145ade2 | 845 | static int max_interrupt_work = 4; |
1da177e4 | 846 | |
a971c324 AA |
847 | /* |
848 | * Optimization can be either throuput mode or cpu mode | |
f3b197ac | 849 | * |
a971c324 AA |
850 | * Throughput Mode: Every tx and rx packet will generate an interrupt. |
851 | * CPU Mode: Interrupts are controlled by a timer. | |
852 | */ | |
69fe3fd7 AA |
853 | enum { |
854 | NV_OPTIMIZATION_MODE_THROUGHPUT, | |
9e184767 AA |
855 | NV_OPTIMIZATION_MODE_CPU, |
856 | NV_OPTIMIZATION_MODE_DYNAMIC | |
69fe3fd7 | 857 | }; |
9e184767 | 858 | static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC; |
a971c324 AA |
859 | |
860 | /* | |
861 | * Poll interval for timer irq | |
862 | * | |
863 | * This interval determines how frequent an interrupt is generated. | |
864 | * The is value is determined by [(time_in_micro_secs * 100) / (2^10)] | |
865 | * Min = 0, and Max = 65535 | |
866 | */ | |
867 | static int poll_interval = -1; | |
868 | ||
d33a73c8 | 869 | /* |
69fe3fd7 | 870 | * MSI interrupts |
d33a73c8 | 871 | */ |
69fe3fd7 AA |
872 | enum { |
873 | NV_MSI_INT_DISABLED, | |
874 | NV_MSI_INT_ENABLED | |
875 | }; | |
876 | static int msi = NV_MSI_INT_ENABLED; | |
d33a73c8 AA |
877 | |
878 | /* | |
69fe3fd7 | 879 | * MSIX interrupts |
d33a73c8 | 880 | */ |
69fe3fd7 AA |
881 | enum { |
882 | NV_MSIX_INT_DISABLED, | |
883 | NV_MSIX_INT_ENABLED | |
884 | }; | |
39482791 | 885 | static int msix = NV_MSIX_INT_ENABLED; |
69fe3fd7 AA |
886 | |
887 | /* | |
888 | * DMA 64bit | |
889 | */ | |
890 | enum { | |
891 | NV_DMA_64BIT_DISABLED, | |
892 | NV_DMA_64BIT_ENABLED | |
893 | }; | |
894 | static int dma_64bit = NV_DMA_64BIT_ENABLED; | |
d33a73c8 | 895 | |
9f3f7910 AA |
896 | /* |
897 | * Crossover Detection | |
898 | * Realtek 8201 phy + some OEM boards do not work properly. | |
899 | */ | |
900 | enum { | |
901 | NV_CROSSOVER_DETECTION_DISABLED, | |
902 | NV_CROSSOVER_DETECTION_ENABLED | |
903 | }; | |
904 | static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED; | |
905 | ||
5a9a8e32 ES |
906 | /* |
907 | * Power down phy when interface is down (persists through reboot; | |
908 | * older Linux and other OSes may not power it up again) | |
909 | */ | |
78aea4fc | 910 | static int phy_power_down; |
5a9a8e32 | 911 | |
1da177e4 LT |
912 | static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
913 | { | |
914 | return netdev_priv(dev); | |
915 | } | |
916 | ||
917 | static inline u8 __iomem *get_hwbase(struct net_device *dev) | |
918 | { | |
ac9c1897 | 919 | return ((struct fe_priv *)netdev_priv(dev))->base; |
1da177e4 LT |
920 | } |
921 | ||
922 | static inline void pci_push(u8 __iomem *base) | |
923 | { | |
924 | /* force out pending posted writes */ | |
925 | readl(base); | |
926 | } | |
927 | ||
928 | static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) | |
929 | { | |
f82a9352 | 930 | return le32_to_cpu(prd->flaglen) |
1da177e4 LT |
931 | & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); |
932 | } | |
933 | ||
ee73362c MS |
934 | static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v) |
935 | { | |
f82a9352 | 936 | return le32_to_cpu(prd->flaglen) & LEN_MASK_V2; |
ee73362c MS |
937 | } |
938 | ||
36b30ea9 JG |
939 | static bool nv_optimized(struct fe_priv *np) |
940 | { | |
941 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | |
942 | return false; | |
943 | return true; | |
944 | } | |
945 | ||
1da177e4 | 946 | static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
344d0dce | 947 | int delay, int delaymax) |
1da177e4 LT |
948 | { |
949 | u8 __iomem *base = get_hwbase(dev); | |
950 | ||
951 | pci_push(base); | |
952 | do { | |
953 | udelay(delay); | |
954 | delaymax -= delay; | |
344d0dce | 955 | if (delaymax < 0) |
1da177e4 | 956 | return 1; |
1da177e4 LT |
957 | } while ((readl(base + offset) & mask) != target); |
958 | return 0; | |
959 | } | |
960 | ||
0832b25a AA |
961 | #define NV_SETUP_RX_RING 0x01 |
962 | #define NV_SETUP_TX_RING 0x02 | |
963 | ||
5bb7ea26 AV |
964 | static inline u32 dma_low(dma_addr_t addr) |
965 | { | |
966 | return addr; | |
967 | } | |
968 | ||
969 | static inline u32 dma_high(dma_addr_t addr) | |
970 | { | |
971 | return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */ | |
972 | } | |
973 | ||
0832b25a AA |
974 | static void setup_hw_rings(struct net_device *dev, int rxtx_flags) |
975 | { | |
976 | struct fe_priv *np = get_nvpriv(dev); | |
977 | u8 __iomem *base = get_hwbase(dev); | |
978 | ||
36b30ea9 | 979 | if (!nv_optimized(np)) { |
78aea4fc | 980 | if (rxtx_flags & NV_SETUP_RX_RING) |
5bb7ea26 | 981 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
78aea4fc | 982 | if (rxtx_flags & NV_SETUP_TX_RING) |
5bb7ea26 | 983 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
0832b25a AA |
984 | } else { |
985 | if (rxtx_flags & NV_SETUP_RX_RING) { | |
5bb7ea26 AV |
986 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
987 | writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh); | |
0832b25a AA |
988 | } |
989 | if (rxtx_flags & NV_SETUP_TX_RING) { | |
5bb7ea26 AV |
990 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr); |
991 | writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh); | |
0832b25a AA |
992 | } |
993 | } | |
994 | } | |
995 | ||
eafa59f6 AA |
996 | static void free_rings(struct net_device *dev) |
997 | { | |
998 | struct fe_priv *np = get_nvpriv(dev); | |
999 | ||
36b30ea9 | 1000 | if (!nv_optimized(np)) { |
f82a9352 | 1001 | if (np->rx_ring.orig) |
eafa59f6 AA |
1002 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
1003 | np->rx_ring.orig, np->ring_addr); | |
1004 | } else { | |
1005 | if (np->rx_ring.ex) | |
1006 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), | |
1007 | np->rx_ring.ex, np->ring_addr); | |
1008 | } | |
9b03b06b SJ |
1009 | kfree(np->rx_skb); |
1010 | kfree(np->tx_skb); | |
eafa59f6 AA |
1011 | } |
1012 | ||
84b3932b AA |
1013 | static int using_multi_irqs(struct net_device *dev) |
1014 | { | |
1015 | struct fe_priv *np = get_nvpriv(dev); | |
1016 | ||
1017 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || | |
1018 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
1019 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) | |
1020 | return 0; | |
1021 | else | |
1022 | return 1; | |
1023 | } | |
1024 | ||
88d7d8b0 AA |
1025 | static void nv_txrx_gate(struct net_device *dev, bool gate) |
1026 | { | |
1027 | struct fe_priv *np = get_nvpriv(dev); | |
1028 | u8 __iomem *base = get_hwbase(dev); | |
1029 | u32 powerstate; | |
1030 | ||
1031 | if (!np->mac_in_use && | |
1032 | (np->driver_data & DEV_HAS_POWER_CNTRL)) { | |
1033 | powerstate = readl(base + NvRegPowerState2); | |
1034 | if (gate) | |
1035 | powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS; | |
1036 | else | |
1037 | powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS; | |
1038 | writel(powerstate, base + NvRegPowerState2); | |
1039 | } | |
1040 | } | |
1041 | ||
84b3932b AA |
1042 | static void nv_enable_irq(struct net_device *dev) |
1043 | { | |
1044 | struct fe_priv *np = get_nvpriv(dev); | |
1045 | ||
1046 | if (!using_multi_irqs(dev)) { | |
1047 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1048 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1049 | else | |
a7475906 | 1050 | enable_irq(np->pci_dev->irq); |
84b3932b AA |
1051 | } else { |
1052 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1053 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1054 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1055 | } | |
1056 | } | |
1057 | ||
1058 | static void nv_disable_irq(struct net_device *dev) | |
1059 | { | |
1060 | struct fe_priv *np = get_nvpriv(dev); | |
1061 | ||
1062 | if (!using_multi_irqs(dev)) { | |
1063 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1064 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1065 | else | |
a7475906 | 1066 | disable_irq(np->pci_dev->irq); |
84b3932b AA |
1067 | } else { |
1068 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1069 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1070 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | /* In MSIX mode, a write to irqmask behaves as XOR */ | |
1075 | static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask) | |
1076 | { | |
1077 | u8 __iomem *base = get_hwbase(dev); | |
1078 | ||
1079 | writel(mask, base + NvRegIrqMask); | |
1080 | } | |
1081 | ||
1082 | static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask) | |
1083 | { | |
1084 | struct fe_priv *np = get_nvpriv(dev); | |
1085 | u8 __iomem *base = get_hwbase(dev); | |
1086 | ||
1087 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
1088 | writel(mask, base + NvRegIrqMask); | |
1089 | } else { | |
1090 | if (np->msi_flags & NV_MSI_ENABLED) | |
1091 | writel(0, base + NvRegMSIIrqMask); | |
1092 | writel(0, base + NvRegIrqMask); | |
1093 | } | |
1094 | } | |
1095 | ||
08d93575 AA |
1096 | static void nv_napi_enable(struct net_device *dev) |
1097 | { | |
08d93575 AA |
1098 | struct fe_priv *np = get_nvpriv(dev); |
1099 | ||
1100 | napi_enable(&np->napi); | |
08d93575 AA |
1101 | } |
1102 | ||
1103 | static void nv_napi_disable(struct net_device *dev) | |
1104 | { | |
08d93575 AA |
1105 | struct fe_priv *np = get_nvpriv(dev); |
1106 | ||
1107 | napi_disable(&np->napi); | |
08d93575 AA |
1108 | } |
1109 | ||
1da177e4 LT |
1110 | #define MII_READ (-1) |
1111 | /* mii_rw: read/write a register on the PHY. | |
1112 | * | |
1113 | * Caller must guarantee serialization | |
1114 | */ | |
1115 | static int mii_rw(struct net_device *dev, int addr, int miireg, int value) | |
1116 | { | |
1117 | u8 __iomem *base = get_hwbase(dev); | |
1118 | u32 reg; | |
1119 | int retval; | |
1120 | ||
eb798428 | 1121 | writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus); |
1da177e4 LT |
1122 | |
1123 | reg = readl(base + NvRegMIIControl); | |
1124 | if (reg & NVREG_MIICTL_INUSE) { | |
1125 | writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); | |
1126 | udelay(NV_MIIBUSY_DELAY); | |
1127 | } | |
1128 | ||
1129 | reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; | |
1130 | if (value != MII_READ) { | |
1131 | writel(value, base + NvRegMIIData); | |
1132 | reg |= NVREG_MIICTL_WRITE; | |
1133 | } | |
1134 | writel(reg, base + NvRegMIIControl); | |
1135 | ||
1136 | if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, | |
344d0dce | 1137 | NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) { |
1da177e4 LT |
1138 | retval = -1; |
1139 | } else if (value != MII_READ) { | |
1140 | /* it was a write operation - fewer failures are detectable */ | |
1da177e4 LT |
1141 | retval = 0; |
1142 | } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { | |
1da177e4 LT |
1143 | retval = -1; |
1144 | } else { | |
1145 | retval = readl(base + NvRegMIIData); | |
1da177e4 LT |
1146 | } |
1147 | ||
1148 | return retval; | |
1149 | } | |
1150 | ||
edf7e5ec | 1151 | static int phy_reset(struct net_device *dev, u32 bmcr_setup) |
1da177e4 | 1152 | { |
ac9c1897 | 1153 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1154 | u32 miicontrol; |
1155 | unsigned int tries = 0; | |
1156 | ||
edf7e5ec | 1157 | miicontrol = BMCR_RESET | bmcr_setup; |
78aea4fc | 1158 | if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) |
1da177e4 | 1159 | return -1; |
1da177e4 LT |
1160 | |
1161 | /* wait for 500ms */ | |
1162 | msleep(500); | |
1163 | ||
1164 | /* must wait till reset is deasserted */ | |
1165 | while (miicontrol & BMCR_RESET) { | |
de855b99 | 1166 | usleep_range(10000, 20000); |
1da177e4 LT |
1167 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1168 | /* FIXME: 100 tries seem excessive */ | |
1169 | if (tries++ > 100) | |
1170 | return -1; | |
1171 | } | |
1172 | return 0; | |
1173 | } | |
1174 | ||
c41d41e1 JP |
1175 | static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np) |
1176 | { | |
1177 | static const struct { | |
1178 | int reg; | |
1179 | int init; | |
1180 | } ri[] = { | |
1181 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 }, | |
1182 | { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 }, | |
1183 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 }, | |
1184 | { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 }, | |
1185 | { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 }, | |
1186 | { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 }, | |
1187 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 }, | |
1188 | }; | |
1189 | int i; | |
1190 | ||
1191 | for (i = 0; i < ARRAY_SIZE(ri); i++) { | |
cd66328b JP |
1192 | if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) |
1193 | return PHY_ERROR; | |
1194 | } | |
1195 | ||
1196 | return 0; | |
1197 | } | |
1198 | ||
1199 | static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np) | |
1200 | { | |
1201 | u32 reg; | |
1202 | u8 __iomem *base = get_hwbase(dev); | |
1203 | u32 powerstate = readl(base + NvRegPowerState2); | |
1204 | ||
1205 | /* need to perform hw phy reset */ | |
1206 | powerstate |= NVREG_POWERSTATE2_PHY_RESET; | |
1207 | writel(powerstate, base + NvRegPowerState2); | |
1208 | msleep(25); | |
1209 | ||
1210 | powerstate &= ~NVREG_POWERSTATE2_PHY_RESET; | |
1211 | writel(powerstate, base + NvRegPowerState2); | |
1212 | msleep(25); | |
1213 | ||
1214 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | |
1215 | reg |= PHY_REALTEK_INIT9; | |
1216 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) | |
1217 | return PHY_ERROR; | |
1218 | if (mii_rw(dev, np->phyaddr, | |
1219 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) | |
1220 | return PHY_ERROR; | |
1221 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); | |
1222 | if (!(reg & PHY_REALTEK_INIT11)) { | |
1223 | reg |= PHY_REALTEK_INIT11; | |
1224 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) | |
1225 | return PHY_ERROR; | |
1226 | } | |
1227 | if (mii_rw(dev, np->phyaddr, | |
1228 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) | |
1229 | return PHY_ERROR; | |
1230 | ||
1231 | return 0; | |
1232 | } | |
1233 | ||
1234 | static int init_realtek_8201(struct net_device *dev, struct fe_priv *np) | |
1235 | { | |
1236 | u32 phy_reserved; | |
1237 | ||
1238 | if (np->driver_data & DEV_NEED_PHY_INIT_FIX) { | |
1239 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1240 | PHY_REALTEK_INIT_REG6, MII_READ); | |
1241 | phy_reserved |= PHY_REALTEK_INIT7; | |
1242 | if (mii_rw(dev, np->phyaddr, | |
1243 | PHY_REALTEK_INIT_REG6, phy_reserved)) | |
1244 | return PHY_ERROR; | |
1245 | } | |
1246 | ||
1247 | return 0; | |
1248 | } | |
1249 | ||
1250 | static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np) | |
1251 | { | |
1252 | u32 phy_reserved; | |
1253 | ||
1254 | if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | |
1255 | if (mii_rw(dev, np->phyaddr, | |
1256 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) | |
1257 | return PHY_ERROR; | |
1258 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1259 | PHY_REALTEK_INIT_REG2, MII_READ); | |
1260 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | |
1261 | phy_reserved |= PHY_REALTEK_INIT3; | |
1262 | if (mii_rw(dev, np->phyaddr, | |
1263 | PHY_REALTEK_INIT_REG2, phy_reserved)) | |
1264 | return PHY_ERROR; | |
1265 | if (mii_rw(dev, np->phyaddr, | |
1266 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) | |
c41d41e1 | 1267 | return PHY_ERROR; |
c41d41e1 JP |
1268 | } |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
cd66328b JP |
1273 | static int init_cicada(struct net_device *dev, struct fe_priv *np, |
1274 | u32 phyinterface) | |
1275 | { | |
1276 | u32 phy_reserved; | |
1277 | ||
1278 | if (phyinterface & PHY_RGMII) { | |
1279 | phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); | |
1280 | phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); | |
1281 | phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); | |
1282 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) | |
1283 | return PHY_ERROR; | |
1284 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
1285 | phy_reserved |= PHY_CICADA_INIT5; | |
1286 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) | |
1287 | return PHY_ERROR; | |
1288 | } | |
1289 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); | |
1290 | phy_reserved |= PHY_CICADA_INIT6; | |
1291 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) | |
1292 | return PHY_ERROR; | |
1293 | ||
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | static int init_vitesse(struct net_device *dev, struct fe_priv *np) | |
1298 | { | |
1299 | u32 phy_reserved; | |
1300 | ||
1301 | if (mii_rw(dev, np->phyaddr, | |
1302 | PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) | |
1303 | return PHY_ERROR; | |
1304 | if (mii_rw(dev, np->phyaddr, | |
1305 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) | |
1306 | return PHY_ERROR; | |
1307 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1308 | PHY_VITESSE_INIT_REG4, MII_READ); | |
1309 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) | |
1310 | return PHY_ERROR; | |
1311 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1312 | PHY_VITESSE_INIT_REG3, MII_READ); | |
1313 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1314 | phy_reserved |= PHY_VITESSE_INIT3; | |
1315 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) | |
1316 | return PHY_ERROR; | |
1317 | if (mii_rw(dev, np->phyaddr, | |
1318 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) | |
1319 | return PHY_ERROR; | |
1320 | if (mii_rw(dev, np->phyaddr, | |
1321 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) | |
1322 | return PHY_ERROR; | |
1323 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1324 | PHY_VITESSE_INIT_REG4, MII_READ); | |
1325 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1326 | phy_reserved |= PHY_VITESSE_INIT3; | |
1327 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) | |
1328 | return PHY_ERROR; | |
1329 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1330 | PHY_VITESSE_INIT_REG3, MII_READ); | |
1331 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) | |
1332 | return PHY_ERROR; | |
1333 | if (mii_rw(dev, np->phyaddr, | |
1334 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) | |
1335 | return PHY_ERROR; | |
1336 | if (mii_rw(dev, np->phyaddr, | |
1337 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) | |
1338 | return PHY_ERROR; | |
1339 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1340 | PHY_VITESSE_INIT_REG4, MII_READ); | |
1341 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) | |
1342 | return PHY_ERROR; | |
1343 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1344 | PHY_VITESSE_INIT_REG3, MII_READ); | |
1345 | phy_reserved &= ~PHY_VITESSE_INIT_MSK2; | |
1346 | phy_reserved |= PHY_VITESSE_INIT8; | |
1347 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) | |
1348 | return PHY_ERROR; | |
1349 | if (mii_rw(dev, np->phyaddr, | |
1350 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) | |
1351 | return PHY_ERROR; | |
1352 | if (mii_rw(dev, np->phyaddr, | |
1353 | PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) | |
1354 | return PHY_ERROR; | |
1355 | ||
1356 | return 0; | |
1357 | } | |
1358 | ||
1da177e4 LT |
1359 | static int phy_init(struct net_device *dev) |
1360 | { | |
1361 | struct fe_priv *np = get_nvpriv(dev); | |
1362 | u8 __iomem *base = get_hwbase(dev); | |
cd66328b JP |
1363 | u32 phyinterface; |
1364 | u32 mii_status, mii_control, mii_control_1000, reg; | |
1da177e4 | 1365 | |
edf7e5ec AA |
1366 | /* phy errata for E3016 phy */ |
1367 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { | |
1368 | reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
1369 | reg &= ~PHY_MARVELL_E3016_INITMASK; | |
1370 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { | |
1d397f36 JP |
1371 | netdev_info(dev, "%s: phy write to errata reg failed\n", |
1372 | pci_name(np->pci_dev)); | |
edf7e5ec AA |
1373 | return PHY_ERROR; |
1374 | } | |
1375 | } | |
c5e3ae88 | 1376 | if (np->phy_oui == PHY_OUI_REALTEK) { |
9f3f7910 AA |
1377 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1378 | np->phy_rev == PHY_REV_REALTEK_8211B) { | |
cd66328b | 1379 | if (init_realtek_8211b(dev, np)) { |
1d397f36 JP |
1380 | netdev_info(dev, "%s: phy init failed\n", |
1381 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1382 | return PHY_ERROR; |
1383 | } | |
cd66328b JP |
1384 | } else if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1385 | np->phy_rev == PHY_REV_REALTEK_8211C) { | |
1386 | if (init_realtek_8211c(dev, np)) { | |
1d397f36 JP |
1387 | netdev_info(dev, "%s: phy init failed\n", |
1388 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1389 | return PHY_ERROR; |
1390 | } | |
cd66328b JP |
1391 | } else if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
1392 | if (init_realtek_8201(dev, np)) { | |
1d397f36 JP |
1393 | netdev_info(dev, "%s: phy init failed\n", |
1394 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1395 | return PHY_ERROR; |
1396 | } | |
1397 | } | |
c5e3ae88 | 1398 | } |
edf7e5ec | 1399 | |
1da177e4 LT |
1400 | /* set advertise register */ |
1401 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
cd66328b JP |
1402 | reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
1403 | ADVERTISE_100HALF | ADVERTISE_100FULL | | |
1404 | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); | |
1da177e4 | 1405 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
1d397f36 JP |
1406 | netdev_info(dev, "%s: phy write to advertise failed\n", |
1407 | pci_name(np->pci_dev)); | |
1da177e4 LT |
1408 | return PHY_ERROR; |
1409 | } | |
1410 | ||
1411 | /* get phy interface type */ | |
1412 | phyinterface = readl(base + NvRegPhyInterface); | |
1413 | ||
1414 | /* see if gigabit phy */ | |
1415 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
1416 | if (mii_status & PHY_GIGABIT) { | |
1417 | np->gigabit = PHY_GIGABIT; | |
cd66328b JP |
1418 | mii_control_1000 = mii_rw(dev, np->phyaddr, |
1419 | MII_CTRL1000, MII_READ); | |
1da177e4 LT |
1420 | mii_control_1000 &= ~ADVERTISE_1000HALF; |
1421 | if (phyinterface & PHY_RGMII) | |
1422 | mii_control_1000 |= ADVERTISE_1000FULL; | |
1423 | else | |
1424 | mii_control_1000 &= ~ADVERTISE_1000FULL; | |
1425 | ||
eb91f61b | 1426 | if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { |
1d397f36 JP |
1427 | netdev_info(dev, "%s: phy init failed\n", |
1428 | pci_name(np->pci_dev)); | |
1da177e4 LT |
1429 | return PHY_ERROR; |
1430 | } | |
78aea4fc | 1431 | } else |
1da177e4 LT |
1432 | np->gigabit = 0; |
1433 | ||
edf7e5ec AA |
1434 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1435 | mii_control |= BMCR_ANENABLE; | |
1436 | ||
22ae03a1 AA |
1437 | if (np->phy_oui == PHY_OUI_REALTEK && |
1438 | np->phy_model == PHY_MODEL_REALTEK_8211 && | |
1439 | np->phy_rev == PHY_REV_REALTEK_8211C) { | |
1440 | /* start autoneg since we already performed hw reset above */ | |
1441 | mii_control |= BMCR_ANRESTART; | |
1442 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { | |
1d397f36 JP |
1443 | netdev_info(dev, "%s: phy init failed\n", |
1444 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1445 | return PHY_ERROR; |
1446 | } | |
1447 | } else { | |
1448 | /* reset the phy | |
1449 | * (certain phys need bmcr to be setup with reset) | |
1450 | */ | |
1451 | if (phy_reset(dev, mii_control)) { | |
1d397f36 JP |
1452 | netdev_info(dev, "%s: phy reset failed\n", |
1453 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1454 | return PHY_ERROR; |
1455 | } | |
1da177e4 LT |
1456 | } |
1457 | ||
1458 | /* phy vendor specific configuration */ | |
cd66328b JP |
1459 | if ((np->phy_oui == PHY_OUI_CICADA)) { |
1460 | if (init_cicada(dev, np, phyinterface)) { | |
1d397f36 JP |
1461 | netdev_info(dev, "%s: phy init failed\n", |
1462 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1463 | return PHY_ERROR; |
1464 | } | |
cd66328b JP |
1465 | } else if (np->phy_oui == PHY_OUI_VITESSE) { |
1466 | if (init_vitesse(dev, np)) { | |
1d397f36 JP |
1467 | netdev_info(dev, "%s: phy init failed\n", |
1468 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1469 | return PHY_ERROR; |
1470 | } | |
cd66328b | 1471 | } else if (np->phy_oui == PHY_OUI_REALTEK) { |
9f3f7910 AA |
1472 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1473 | np->phy_rev == PHY_REV_REALTEK_8211B) { | |
1474 | /* reset could have cleared these out, set them back */ | |
cd66328b JP |
1475 | if (init_realtek_8211b(dev, np)) { |
1476 | netdev_info(dev, "%s: phy init failed\n", | |
1477 | pci_name(np->pci_dev)); | |
9f3f7910 | 1478 | return PHY_ERROR; |
9f3f7910 | 1479 | } |
cd66328b JP |
1480 | } else if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
1481 | if (init_realtek_8201(dev, np) || | |
1482 | init_realtek_8201_cross(dev, np)) { | |
1483 | netdev_info(dev, "%s: phy init failed\n", | |
1484 | pci_name(np->pci_dev)); | |
1485 | return PHY_ERROR; | |
9f3f7910 | 1486 | } |
c5e3ae88 AA |
1487 | } |
1488 | } | |
1489 | ||
25985edc | 1490 | /* some phys clear out pause advertisement on reset, set it back */ |
eb91f61b | 1491 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); |
1da177e4 | 1492 | |
cb52deba | 1493 | /* restart auto negotiation, power down phy */ |
1da177e4 | 1494 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
5a9a8e32 | 1495 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); |
78aea4fc | 1496 | if (phy_power_down) |
5a9a8e32 | 1497 | mii_control |= BMCR_PDOWN; |
78aea4fc | 1498 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) |
1da177e4 | 1499 | return PHY_ERROR; |
1da177e4 LT |
1500 | |
1501 | return 0; | |
1502 | } | |
1503 | ||
1504 | static void nv_start_rx(struct net_device *dev) | |
1505 | { | |
ac9c1897 | 1506 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1507 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1508 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 | 1509 | |
1da177e4 | 1510 | /* Already running? Stop it. */ |
f35723ec AA |
1511 | if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { |
1512 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1513 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1514 | pci_push(base); |
1515 | } | |
1516 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
1517 | pci_push(base); | |
78aea4fc SJ |
1518 | rx_ctrl |= NVREG_RCVCTL_START; |
1519 | if (np->mac_in_use) | |
f35723ec AA |
1520 | rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; |
1521 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1522 | pci_push(base); |
1523 | } | |
1524 | ||
1525 | static void nv_stop_rx(struct net_device *dev) | |
1526 | { | |
f35723ec | 1527 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1528 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1529 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 | 1530 | |
f35723ec AA |
1531 | if (!np->mac_in_use) |
1532 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1533 | else | |
1534 | rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; | |
1535 | writel(rx_ctrl, base + NvRegReceiverControl); | |
344d0dce JP |
1536 | if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
1537 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX)) | |
1d397f36 JP |
1538 | netdev_info(dev, "%s: ReceiverStatus remained busy\n", |
1539 | __func__); | |
1da177e4 LT |
1540 | |
1541 | udelay(NV_RXSTOP_DELAY2); | |
f35723ec AA |
1542 | if (!np->mac_in_use) |
1543 | writel(0, base + NvRegLinkSpeed); | |
1da177e4 LT |
1544 | } |
1545 | ||
1546 | static void nv_start_tx(struct net_device *dev) | |
1547 | { | |
f35723ec | 1548 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1549 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1550 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 | 1551 | |
f35723ec AA |
1552 | tx_ctrl |= NVREG_XMITCTL_START; |
1553 | if (np->mac_in_use) | |
1554 | tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; | |
1555 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
1da177e4 LT |
1556 | pci_push(base); |
1557 | } | |
1558 | ||
1559 | static void nv_stop_tx(struct net_device *dev) | |
1560 | { | |
f35723ec | 1561 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1562 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1563 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 | 1564 | |
f35723ec AA |
1565 | if (!np->mac_in_use) |
1566 | tx_ctrl &= ~NVREG_XMITCTL_START; | |
1567 | else | |
1568 | tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; | |
1569 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
344d0dce JP |
1570 | if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
1571 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX)) | |
1d397f36 JP |
1572 | netdev_info(dev, "%s: TransmitterStatus remained busy\n", |
1573 | __func__); | |
1da177e4 LT |
1574 | |
1575 | udelay(NV_TXSTOP_DELAY2); | |
f35723ec AA |
1576 | if (!np->mac_in_use) |
1577 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, | |
1578 | base + NvRegTransmitPoll); | |
1da177e4 LT |
1579 | } |
1580 | ||
36b30ea9 JG |
1581 | static void nv_start_rxtx(struct net_device *dev) |
1582 | { | |
1583 | nv_start_rx(dev); | |
1584 | nv_start_tx(dev); | |
1585 | } | |
1586 | ||
1587 | static void nv_stop_rxtx(struct net_device *dev) | |
1588 | { | |
1589 | nv_stop_rx(dev); | |
1590 | nv_stop_tx(dev); | |
1591 | } | |
1592 | ||
1da177e4 LT |
1593 | static void nv_txrx_reset(struct net_device *dev) |
1594 | { | |
ac9c1897 | 1595 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1596 | u8 __iomem *base = get_hwbase(dev); |
1597 | ||
8a4ae7f2 | 1598 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1599 | pci_push(base); |
1600 | udelay(NV_TXRX_RESET_DELAY); | |
8a4ae7f2 | 1601 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1602 | pci_push(base); |
1603 | } | |
1604 | ||
86a0f043 AA |
1605 | static void nv_mac_reset(struct net_device *dev) |
1606 | { | |
1607 | struct fe_priv *np = netdev_priv(dev); | |
1608 | u8 __iomem *base = get_hwbase(dev); | |
4e84f9b1 | 1609 | u32 temp1, temp2, temp3; |
86a0f043 | 1610 | |
86a0f043 AA |
1611 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1612 | pci_push(base); | |
4e84f9b1 AA |
1613 | |
1614 | /* save registers since they will be cleared on reset */ | |
1615 | temp1 = readl(base + NvRegMacAddrA); | |
1616 | temp2 = readl(base + NvRegMacAddrB); | |
1617 | temp3 = readl(base + NvRegTransmitPoll); | |
1618 | ||
86a0f043 AA |
1619 | writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); |
1620 | pci_push(base); | |
1621 | udelay(NV_MAC_RESET_DELAY); | |
1622 | writel(0, base + NvRegMacReset); | |
1623 | pci_push(base); | |
1624 | udelay(NV_MAC_RESET_DELAY); | |
4e84f9b1 AA |
1625 | |
1626 | /* restore saved registers */ | |
1627 | writel(temp1, base + NvRegMacAddrA); | |
1628 | writel(temp2, base + NvRegMacAddrB); | |
1629 | writel(temp3, base + NvRegTransmitPoll); | |
1630 | ||
86a0f043 AA |
1631 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1632 | pci_push(base); | |
1633 | } | |
1634 | ||
57fff698 AA |
1635 | static void nv_get_hw_stats(struct net_device *dev) |
1636 | { | |
1637 | struct fe_priv *np = netdev_priv(dev); | |
1638 | u8 __iomem *base = get_hwbase(dev); | |
1639 | ||
1640 | np->estats.tx_bytes += readl(base + NvRegTxCnt); | |
1641 | np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); | |
1642 | np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); | |
1643 | np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); | |
1644 | np->estats.tx_late_collision += readl(base + NvRegTxLateCol); | |
1645 | np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); | |
1646 | np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); | |
1647 | np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); | |
1648 | np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); | |
1649 | np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); | |
1650 | np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); | |
1651 | np->estats.rx_late_collision += readl(base + NvRegRxLateCol); | |
1652 | np->estats.rx_runt += readl(base + NvRegRxRunt); | |
1653 | np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); | |
1654 | np->estats.rx_over_errors += readl(base + NvRegRxOverflow); | |
1655 | np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); | |
1656 | np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); | |
1657 | np->estats.rx_length_error += readl(base + NvRegRxLenErr); | |
1658 | np->estats.rx_unicast += readl(base + NvRegRxUnicast); | |
1659 | np->estats.rx_multicast += readl(base + NvRegRxMulticast); | |
1660 | np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); | |
1661 | np->estats.rx_packets = | |
1662 | np->estats.rx_unicast + | |
1663 | np->estats.rx_multicast + | |
1664 | np->estats.rx_broadcast; | |
1665 | np->estats.rx_errors_total = | |
1666 | np->estats.rx_crc_errors + | |
1667 | np->estats.rx_over_errors + | |
1668 | np->estats.rx_frame_error + | |
1669 | (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) + | |
1670 | np->estats.rx_late_collision + | |
1671 | np->estats.rx_runt + | |
1672 | np->estats.rx_frame_too_long; | |
1673 | np->estats.tx_errors_total = | |
1674 | np->estats.tx_late_collision + | |
1675 | np->estats.tx_fifo_errors + | |
1676 | np->estats.tx_carrier_errors + | |
1677 | np->estats.tx_excess_deferral + | |
1678 | np->estats.tx_retry_error; | |
1679 | ||
1680 | if (np->driver_data & DEV_HAS_STATISTICS_V2) { | |
1681 | np->estats.tx_deferral += readl(base + NvRegTxDef); | |
1682 | np->estats.tx_packets += readl(base + NvRegTxFrame); | |
1683 | np->estats.rx_bytes += readl(base + NvRegRxCnt); | |
1684 | np->estats.tx_pause += readl(base + NvRegTxPause); | |
1685 | np->estats.rx_pause += readl(base + NvRegRxPause); | |
1686 | np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); | |
1687 | } | |
9c662435 AA |
1688 | |
1689 | if (np->driver_data & DEV_HAS_STATISTICS_V3) { | |
1690 | np->estats.tx_unicast += readl(base + NvRegTxUnicast); | |
1691 | np->estats.tx_multicast += readl(base + NvRegTxMulticast); | |
1692 | np->estats.tx_broadcast += readl(base + NvRegTxBroadcast); | |
1693 | } | |
57fff698 AA |
1694 | } |
1695 | ||
1da177e4 LT |
1696 | /* |
1697 | * nv_get_stats: dev->get_stats function | |
1698 | * Get latest stats value from the nic. | |
1699 | * Called with read_lock(&dev_base_lock) held for read - | |
1700 | * only synchronized against unregister_netdevice. | |
1701 | */ | |
1702 | static struct net_device_stats *nv_get_stats(struct net_device *dev) | |
1703 | { | |
ac9c1897 | 1704 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1705 | |
21828163 | 1706 | /* If the nic supports hw counters then retrieve latest values */ |
9c662435 | 1707 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) { |
21828163 AA |
1708 | nv_get_hw_stats(dev); |
1709 | ||
1710 | /* copy to net_device stats */ | |
8148ff45 JG |
1711 | dev->stats.tx_bytes = np->estats.tx_bytes; |
1712 | dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors; | |
1713 | dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors; | |
1714 | dev->stats.rx_crc_errors = np->estats.rx_crc_errors; | |
1715 | dev->stats.rx_over_errors = np->estats.rx_over_errors; | |
1716 | dev->stats.rx_errors = np->estats.rx_errors_total; | |
1717 | dev->stats.tx_errors = np->estats.tx_errors_total; | |
21828163 | 1718 | } |
8148ff45 JG |
1719 | |
1720 | return &dev->stats; | |
1da177e4 LT |
1721 | } |
1722 | ||
1723 | /* | |
1724 | * nv_alloc_rx: fill rx ring entries. | |
1725 | * Return 1 if the allocations for the skbs failed and the | |
1726 | * rx engine is without Available descriptors | |
1727 | */ | |
1728 | static int nv_alloc_rx(struct net_device *dev) | |
1729 | { | |
ac9c1897 | 1730 | struct fe_priv *np = netdev_priv(dev); |
78aea4fc | 1731 | struct ring_desc *less_rx; |
1da177e4 | 1732 | |
86b22b0d AA |
1733 | less_rx = np->get_rx.orig; |
1734 | if (less_rx-- == np->first_rx.orig) | |
1735 | less_rx = np->last_rx.orig; | |
761fcd9e | 1736 | |
86b22b0d AA |
1737 | while (np->put_rx.orig != less_rx) { |
1738 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); | |
1739 | if (skb) { | |
86b22b0d | 1740 | np->put_rx_ctx->skb = skb; |
4305b541 ACM |
1741 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, |
1742 | skb->data, | |
8b5be268 | 1743 | skb_tailroom(skb), |
4305b541 | 1744 | PCI_DMA_FROMDEVICE); |
8b5be268 | 1745 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
86b22b0d AA |
1746 | np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma); |
1747 | wmb(); | |
1748 | np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); | |
b01867cb | 1749 | if (unlikely(np->put_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 1750 | np->put_rx.orig = np->first_rx.orig; |
b01867cb | 1751 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d | 1752 | np->put_rx_ctx = np->first_rx_ctx; |
78aea4fc | 1753 | } else |
86b22b0d | 1754 | return 1; |
86b22b0d AA |
1755 | } |
1756 | return 0; | |
1757 | } | |
1758 | ||
1759 | static int nv_alloc_rx_optimized(struct net_device *dev) | |
1760 | { | |
1761 | struct fe_priv *np = netdev_priv(dev); | |
78aea4fc | 1762 | struct ring_desc_ex *less_rx; |
86b22b0d AA |
1763 | |
1764 | less_rx = np->get_rx.ex; | |
1765 | if (less_rx-- == np->first_rx.ex) | |
1766 | less_rx = np->last_rx.ex; | |
761fcd9e | 1767 | |
86b22b0d AA |
1768 | while (np->put_rx.ex != less_rx) { |
1769 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); | |
0d63fb32 | 1770 | if (skb) { |
761fcd9e | 1771 | np->put_rx_ctx->skb = skb; |
4305b541 ACM |
1772 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, |
1773 | skb->data, | |
8b5be268 | 1774 | skb_tailroom(skb), |
4305b541 | 1775 | PCI_DMA_FROMDEVICE); |
8b5be268 | 1776 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
5bb7ea26 AV |
1777 | np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma)); |
1778 | np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma)); | |
86b22b0d AA |
1779 | wmb(); |
1780 | np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); | |
b01867cb | 1781 | if (unlikely(np->put_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 1782 | np->put_rx.ex = np->first_rx.ex; |
b01867cb | 1783 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
0d63fb32 | 1784 | np->put_rx_ctx = np->first_rx_ctx; |
78aea4fc | 1785 | } else |
0d63fb32 | 1786 | return 1; |
1da177e4 | 1787 | } |
1da177e4 LT |
1788 | return 0; |
1789 | } | |
1790 | ||
e27cdba5 | 1791 | /* If rx bufs are exhausted called after 50ms to attempt to refresh */ |
e27cdba5 SH |
1792 | static void nv_do_rx_refill(unsigned long data) |
1793 | { | |
1794 | struct net_device *dev = (struct net_device *) data; | |
bea3348e | 1795 | struct fe_priv *np = netdev_priv(dev); |
e27cdba5 SH |
1796 | |
1797 | /* Just reschedule NAPI rx processing */ | |
288379f0 | 1798 | napi_schedule(&np->napi); |
e27cdba5 | 1799 | } |
1da177e4 | 1800 | |
f3b197ac | 1801 | static void nv_init_rx(struct net_device *dev) |
1da177e4 | 1802 | { |
ac9c1897 | 1803 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1804 | int i; |
36b30ea9 | 1805 | |
761fcd9e | 1806 | np->get_rx = np->put_rx = np->first_rx = np->rx_ring; |
36b30ea9 JG |
1807 | |
1808 | if (!nv_optimized(np)) | |
761fcd9e AA |
1809 | np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1]; |
1810 | else | |
1811 | np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1]; | |
1812 | np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb; | |
1813 | np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1]; | |
1da177e4 | 1814 | |
761fcd9e | 1815 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 1816 | if (!nv_optimized(np)) { |
f82a9352 | 1817 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1818 | np->rx_ring.orig[i].buf = 0; |
1819 | } else { | |
f82a9352 | 1820 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1821 | np->rx_ring.ex[i].txvlan = 0; |
1822 | np->rx_ring.ex[i].bufhigh = 0; | |
1823 | np->rx_ring.ex[i].buflow = 0; | |
1824 | } | |
1825 | np->rx_skb[i].skb = NULL; | |
1826 | np->rx_skb[i].dma = 0; | |
1827 | } | |
d81c0983 MS |
1828 | } |
1829 | ||
1830 | static void nv_init_tx(struct net_device *dev) | |
1831 | { | |
ac9c1897 | 1832 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 | 1833 | int i; |
36b30ea9 | 1834 | |
761fcd9e | 1835 | np->get_tx = np->put_tx = np->first_tx = np->tx_ring; |
36b30ea9 JG |
1836 | |
1837 | if (!nv_optimized(np)) | |
761fcd9e AA |
1838 | np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1]; |
1839 | else | |
1840 | np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1]; | |
1841 | np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb; | |
1842 | np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1]; | |
3b446c3e AA |
1843 | np->tx_pkts_in_progress = 0; |
1844 | np->tx_change_owner = NULL; | |
1845 | np->tx_end_flip = NULL; | |
8f955d7f | 1846 | np->tx_stop = 0; |
d81c0983 | 1847 | |
eafa59f6 | 1848 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 1849 | if (!nv_optimized(np)) { |
f82a9352 | 1850 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1851 | np->tx_ring.orig[i].buf = 0; |
1852 | } else { | |
f82a9352 | 1853 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1854 | np->tx_ring.ex[i].txvlan = 0; |
1855 | np->tx_ring.ex[i].bufhigh = 0; | |
1856 | np->tx_ring.ex[i].buflow = 0; | |
1857 | } | |
1858 | np->tx_skb[i].skb = NULL; | |
1859 | np->tx_skb[i].dma = 0; | |
3b446c3e | 1860 | np->tx_skb[i].dma_len = 0; |
73a37079 | 1861 | np->tx_skb[i].dma_single = 0; |
3b446c3e AA |
1862 | np->tx_skb[i].first_tx_desc = NULL; |
1863 | np->tx_skb[i].next_tx_ctx = NULL; | |
ac9c1897 | 1864 | } |
d81c0983 MS |
1865 | } |
1866 | ||
1867 | static int nv_init_ring(struct net_device *dev) | |
1868 | { | |
86b22b0d AA |
1869 | struct fe_priv *np = netdev_priv(dev); |
1870 | ||
d81c0983 MS |
1871 | nv_init_tx(dev); |
1872 | nv_init_rx(dev); | |
36b30ea9 JG |
1873 | |
1874 | if (!nv_optimized(np)) | |
86b22b0d AA |
1875 | return nv_alloc_rx(dev); |
1876 | else | |
1877 | return nv_alloc_rx_optimized(dev); | |
1da177e4 LT |
1878 | } |
1879 | ||
73a37079 | 1880 | static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb) |
ac9c1897 | 1881 | { |
761fcd9e | 1882 | if (tx_skb->dma) { |
73a37079 ED |
1883 | if (tx_skb->dma_single) |
1884 | pci_unmap_single(np->pci_dev, tx_skb->dma, | |
1885 | tx_skb->dma_len, | |
1886 | PCI_DMA_TODEVICE); | |
1887 | else | |
1888 | pci_unmap_page(np->pci_dev, tx_skb->dma, | |
1889 | tx_skb->dma_len, | |
1890 | PCI_DMA_TODEVICE); | |
761fcd9e | 1891 | tx_skb->dma = 0; |
fa45459e | 1892 | } |
73a37079 ED |
1893 | } |
1894 | ||
1895 | static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb) | |
1896 | { | |
1897 | nv_unmap_txskb(np, tx_skb); | |
761fcd9e AA |
1898 | if (tx_skb->skb) { |
1899 | dev_kfree_skb_any(tx_skb->skb); | |
1900 | tx_skb->skb = NULL; | |
fa45459e | 1901 | return 1; |
ac9c1897 | 1902 | } |
73a37079 | 1903 | return 0; |
ac9c1897 AA |
1904 | } |
1905 | ||
1da177e4 LT |
1906 | static void nv_drain_tx(struct net_device *dev) |
1907 | { | |
ac9c1897 AA |
1908 | struct fe_priv *np = netdev_priv(dev); |
1909 | unsigned int i; | |
f3b197ac | 1910 | |
eafa59f6 | 1911 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 1912 | if (!nv_optimized(np)) { |
f82a9352 | 1913 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1914 | np->tx_ring.orig[i].buf = 0; |
1915 | } else { | |
f82a9352 | 1916 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1917 | np->tx_ring.ex[i].txvlan = 0; |
1918 | np->tx_ring.ex[i].bufhigh = 0; | |
1919 | np->tx_ring.ex[i].buflow = 0; | |
1920 | } | |
73a37079 | 1921 | if (nv_release_txskb(np, &np->tx_skb[i])) |
8148ff45 | 1922 | dev->stats.tx_dropped++; |
3b446c3e AA |
1923 | np->tx_skb[i].dma = 0; |
1924 | np->tx_skb[i].dma_len = 0; | |
73a37079 | 1925 | np->tx_skb[i].dma_single = 0; |
3b446c3e AA |
1926 | np->tx_skb[i].first_tx_desc = NULL; |
1927 | np->tx_skb[i].next_tx_ctx = NULL; | |
1da177e4 | 1928 | } |
3b446c3e AA |
1929 | np->tx_pkts_in_progress = 0; |
1930 | np->tx_change_owner = NULL; | |
1931 | np->tx_end_flip = NULL; | |
1da177e4 LT |
1932 | } |
1933 | ||
1934 | static void nv_drain_rx(struct net_device *dev) | |
1935 | { | |
ac9c1897 | 1936 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1937 | int i; |
761fcd9e | 1938 | |
eafa59f6 | 1939 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 1940 | if (!nv_optimized(np)) { |
f82a9352 | 1941 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1942 | np->rx_ring.orig[i].buf = 0; |
1943 | } else { | |
f82a9352 | 1944 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1945 | np->rx_ring.ex[i].txvlan = 0; |
1946 | np->rx_ring.ex[i].bufhigh = 0; | |
1947 | np->rx_ring.ex[i].buflow = 0; | |
1948 | } | |
1da177e4 | 1949 | wmb(); |
761fcd9e AA |
1950 | if (np->rx_skb[i].skb) { |
1951 | pci_unmap_single(np->pci_dev, np->rx_skb[i].dma, | |
4305b541 ACM |
1952 | (skb_end_pointer(np->rx_skb[i].skb) - |
1953 | np->rx_skb[i].skb->data), | |
1954 | PCI_DMA_FROMDEVICE); | |
761fcd9e AA |
1955 | dev_kfree_skb(np->rx_skb[i].skb); |
1956 | np->rx_skb[i].skb = NULL; | |
1da177e4 LT |
1957 | } |
1958 | } | |
1959 | } | |
1960 | ||
36b30ea9 | 1961 | static void nv_drain_rxtx(struct net_device *dev) |
1da177e4 LT |
1962 | { |
1963 | nv_drain_tx(dev); | |
1964 | nv_drain_rx(dev); | |
1965 | } | |
1966 | ||
761fcd9e AA |
1967 | static inline u32 nv_get_empty_tx_slots(struct fe_priv *np) |
1968 | { | |
1969 | return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size)); | |
1970 | } | |
1971 | ||
a433686c AA |
1972 | static void nv_legacybackoff_reseed(struct net_device *dev) |
1973 | { | |
1974 | u8 __iomem *base = get_hwbase(dev); | |
1975 | u32 reg; | |
1976 | u32 low; | |
1977 | int tx_status = 0; | |
1978 | ||
1979 | reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK; | |
1980 | get_random_bytes(&low, sizeof(low)); | |
1981 | reg |= low & NVREG_SLOTTIME_MASK; | |
1982 | ||
1983 | /* Need to stop tx before change takes effect. | |
1984 | * Caller has already gained np->lock. | |
1985 | */ | |
1986 | tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START; | |
1987 | if (tx_status) | |
1988 | nv_stop_tx(dev); | |
1989 | nv_stop_rx(dev); | |
1990 | writel(reg, base + NvRegSlotTime); | |
1991 | if (tx_status) | |
1992 | nv_start_tx(dev); | |
1993 | nv_start_rx(dev); | |
1994 | } | |
1995 | ||
1996 | /* Gear Backoff Seeds */ | |
1997 | #define BACKOFF_SEEDSET_ROWS 8 | |
1998 | #define BACKOFF_SEEDSET_LFSRS 15 | |
1999 | ||
2000 | /* Known Good seed sets */ | |
2001 | static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
78aea4fc SJ |
2002 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, |
2003 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974}, | |
2004 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, | |
2005 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974}, | |
2006 | {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984}, | |
2007 | {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984}, | |
2008 | {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84}, | |
2009 | {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} }; | |
a433686c AA |
2010 | |
2011 | static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
78aea4fc SJ |
2012 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, |
2013 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2014 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397}, | |
2015 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
2016 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
2017 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2018 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2019 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} }; | |
a433686c AA |
2020 | |
2021 | static void nv_gear_backoff_reseed(struct net_device *dev) | |
2022 | { | |
2023 | u8 __iomem *base = get_hwbase(dev); | |
2024 | u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed; | |
2025 | u32 temp, seedset, combinedSeed; | |
2026 | int i; | |
2027 | ||
2028 | /* Setup seed for free running LFSR */ | |
2029 | /* We are going to read the time stamp counter 3 times | |
2030 | and swizzle bits around to increase randomness */ | |
2031 | get_random_bytes(&miniseed1, sizeof(miniseed1)); | |
2032 | miniseed1 &= 0x0fff; | |
2033 | if (miniseed1 == 0) | |
2034 | miniseed1 = 0xabc; | |
2035 | ||
2036 | get_random_bytes(&miniseed2, sizeof(miniseed2)); | |
2037 | miniseed2 &= 0x0fff; | |
2038 | if (miniseed2 == 0) | |
2039 | miniseed2 = 0xabc; | |
2040 | miniseed2_reversed = | |
2041 | ((miniseed2 & 0xF00) >> 8) | | |
2042 | (miniseed2 & 0x0F0) | | |
2043 | ((miniseed2 & 0x00F) << 8); | |
2044 | ||
2045 | get_random_bytes(&miniseed3, sizeof(miniseed3)); | |
2046 | miniseed3 &= 0x0fff; | |
2047 | if (miniseed3 == 0) | |
2048 | miniseed3 = 0xabc; | |
2049 | miniseed3_reversed = | |
2050 | ((miniseed3 & 0xF00) >> 8) | | |
2051 | (miniseed3 & 0x0F0) | | |
2052 | ((miniseed3 & 0x00F) << 8); | |
2053 | ||
2054 | combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) | | |
2055 | (miniseed2 ^ miniseed3_reversed); | |
2056 | ||
2057 | /* Seeds can not be zero */ | |
2058 | if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0) | |
2059 | combinedSeed |= 0x08; | |
2060 | if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0) | |
2061 | combinedSeed |= 0x8000; | |
2062 | ||
2063 | /* No need to disable tx here */ | |
2064 | temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT); | |
2065 | temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK; | |
2066 | temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR; | |
78aea4fc | 2067 | writel(temp, base + NvRegBackOffControl); |
a433686c | 2068 | |
78aea4fc | 2069 | /* Setup seeds for all gear LFSRs. */ |
a433686c AA |
2070 | get_random_bytes(&seedset, sizeof(seedset)); |
2071 | seedset = seedset % BACKOFF_SEEDSET_ROWS; | |
78aea4fc | 2072 | for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) { |
a433686c AA |
2073 | temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT); |
2074 | temp |= main_seedset[seedset][i-1] & 0x3ff; | |
2075 | temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR); | |
2076 | writel(temp, base + NvRegBackOffControl); | |
2077 | } | |
2078 | } | |
2079 | ||
1da177e4 LT |
2080 | /* |
2081 | * nv_start_xmit: dev->hard_start_xmit function | |
932ff279 | 2082 | * Called with netif_tx_lock held. |
1da177e4 | 2083 | */ |
61357325 | 2084 | static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 2085 | { |
ac9c1897 | 2086 | struct fe_priv *np = netdev_priv(dev); |
fa45459e | 2087 | u32 tx_flags = 0; |
ac9c1897 AA |
2088 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
2089 | unsigned int fragments = skb_shinfo(skb)->nr_frags; | |
ac9c1897 | 2090 | unsigned int i; |
fa45459e AA |
2091 | u32 offset = 0; |
2092 | u32 bcnt; | |
e743d313 | 2093 | u32 size = skb_headlen(skb); |
fa45459e | 2094 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
761fcd9e | 2095 | u32 empty_slots; |
78aea4fc SJ |
2096 | struct ring_desc *put_tx; |
2097 | struct ring_desc *start_tx; | |
2098 | struct ring_desc *prev_tx; | |
2099 | struct nv_skb_map *prev_tx_ctx; | |
bd6ca637 | 2100 | unsigned long flags; |
fa45459e AA |
2101 | |
2102 | /* add fragments to entries count */ | |
2103 | for (i = 0; i < fragments; i++) { | |
2104 | entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + | |
2105 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
2106 | } | |
ac9c1897 | 2107 | |
001eb84b | 2108 | spin_lock_irqsave(&np->lock, flags); |
761fcd9e | 2109 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 2110 | if (unlikely(empty_slots <= entries)) { |
ac9c1897 | 2111 | netif_stop_queue(dev); |
aaa37d2d | 2112 | np->tx_stop = 1; |
bd6ca637 | 2113 | spin_unlock_irqrestore(&np->lock, flags); |
ac9c1897 AA |
2114 | return NETDEV_TX_BUSY; |
2115 | } | |
001eb84b | 2116 | spin_unlock_irqrestore(&np->lock, flags); |
1da177e4 | 2117 | |
86b22b0d | 2118 | start_tx = put_tx = np->put_tx.orig; |
761fcd9e | 2119 | |
fa45459e AA |
2120 | /* setup the header buffer */ |
2121 | do { | |
761fcd9e AA |
2122 | prev_tx = put_tx; |
2123 | prev_tx_ctx = np->put_tx_ctx; | |
fa45459e | 2124 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
761fcd9e | 2125 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, |
fa45459e | 2126 | PCI_DMA_TODEVICE); |
761fcd9e | 2127 | np->put_tx_ctx->dma_len = bcnt; |
73a37079 | 2128 | np->put_tx_ctx->dma_single = 1; |
86b22b0d AA |
2129 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
2130 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 2131 | |
fa45459e AA |
2132 | tx_flags = np->tx_flags; |
2133 | offset += bcnt; | |
2134 | size -= bcnt; | |
445583b8 | 2135 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 2136 | put_tx = np->first_tx.orig; |
445583b8 | 2137 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2138 | np->put_tx_ctx = np->first_tx_ctx; |
f82a9352 | 2139 | } while (size); |
fa45459e AA |
2140 | |
2141 | /* setup the fragments */ | |
2142 | for (i = 0; i < fragments; i++) { | |
2143 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2144 | u32 size = frag->size; | |
2145 | offset = 0; | |
2146 | ||
2147 | do { | |
761fcd9e AA |
2148 | prev_tx = put_tx; |
2149 | prev_tx_ctx = np->put_tx_ctx; | |
fa45459e | 2150 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
761fcd9e AA |
2151 | np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, |
2152 | PCI_DMA_TODEVICE); | |
2153 | np->put_tx_ctx->dma_len = bcnt; | |
73a37079 | 2154 | np->put_tx_ctx->dma_single = 0; |
86b22b0d AA |
2155 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
2156 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 2157 | |
fa45459e AA |
2158 | offset += bcnt; |
2159 | size -= bcnt; | |
445583b8 | 2160 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 2161 | put_tx = np->first_tx.orig; |
445583b8 | 2162 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2163 | np->put_tx_ctx = np->first_tx_ctx; |
fa45459e AA |
2164 | } while (size); |
2165 | } | |
ac9c1897 | 2166 | |
fa45459e | 2167 | /* set last fragment flag */ |
86b22b0d | 2168 | prev_tx->flaglen |= cpu_to_le32(tx_flags_extra); |
ac9c1897 | 2169 | |
761fcd9e AA |
2170 | /* save skb in this slot's context area */ |
2171 | prev_tx_ctx->skb = skb; | |
fa45459e | 2172 | |
89114afd | 2173 | if (skb_is_gso(skb)) |
7967168c | 2174 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); |
ac9c1897 | 2175 | else |
1d39ed56 | 2176 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? |
84fa7933 | 2177 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; |
ac9c1897 | 2178 | |
bd6ca637 | 2179 | spin_lock_irqsave(&np->lock, flags); |
164a86e4 | 2180 | |
fa45459e | 2181 | /* set tx flags */ |
86b22b0d AA |
2182 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
2183 | np->put_tx.orig = put_tx; | |
1da177e4 | 2184 | |
bd6ca637 | 2185 | spin_unlock_irqrestore(&np->lock, flags); |
761fcd9e | 2186 | |
8a4ae7f2 | 2187 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
ac9c1897 | 2188 | return NETDEV_TX_OK; |
1da177e4 LT |
2189 | } |
2190 | ||
61357325 SH |
2191 | static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb, |
2192 | struct net_device *dev) | |
86b22b0d AA |
2193 | { |
2194 | struct fe_priv *np = netdev_priv(dev); | |
2195 | u32 tx_flags = 0; | |
445583b8 | 2196 | u32 tx_flags_extra; |
86b22b0d AA |
2197 | unsigned int fragments = skb_shinfo(skb)->nr_frags; |
2198 | unsigned int i; | |
2199 | u32 offset = 0; | |
2200 | u32 bcnt; | |
e743d313 | 2201 | u32 size = skb_headlen(skb); |
86b22b0d AA |
2202 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
2203 | u32 empty_slots; | |
78aea4fc SJ |
2204 | struct ring_desc_ex *put_tx; |
2205 | struct ring_desc_ex *start_tx; | |
2206 | struct ring_desc_ex *prev_tx; | |
2207 | struct nv_skb_map *prev_tx_ctx; | |
2208 | struct nv_skb_map *start_tx_ctx; | |
bd6ca637 | 2209 | unsigned long flags; |
86b22b0d AA |
2210 | |
2211 | /* add fragments to entries count */ | |
2212 | for (i = 0; i < fragments; i++) { | |
2213 | entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + | |
2214 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
2215 | } | |
2216 | ||
001eb84b | 2217 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2218 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 2219 | if (unlikely(empty_slots <= entries)) { |
86b22b0d | 2220 | netif_stop_queue(dev); |
aaa37d2d | 2221 | np->tx_stop = 1; |
bd6ca637 | 2222 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2223 | return NETDEV_TX_BUSY; |
2224 | } | |
001eb84b | 2225 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2226 | |
2227 | start_tx = put_tx = np->put_tx.ex; | |
3b446c3e | 2228 | start_tx_ctx = np->put_tx_ctx; |
86b22b0d AA |
2229 | |
2230 | /* setup the header buffer */ | |
2231 | do { | |
2232 | prev_tx = put_tx; | |
2233 | prev_tx_ctx = np->put_tx_ctx; | |
2234 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
2235 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, | |
2236 | PCI_DMA_TODEVICE); | |
2237 | np->put_tx_ctx->dma_len = bcnt; | |
73a37079 | 2238 | np->put_tx_ctx->dma_single = 1; |
5bb7ea26 AV |
2239 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2240 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2241 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 AA |
2242 | |
2243 | tx_flags = NV_TX2_VALID; | |
86b22b0d AA |
2244 | offset += bcnt; |
2245 | size -= bcnt; | |
445583b8 | 2246 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 2247 | put_tx = np->first_tx.ex; |
445583b8 | 2248 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2249 | np->put_tx_ctx = np->first_tx_ctx; |
2250 | } while (size); | |
2251 | ||
2252 | /* setup the fragments */ | |
2253 | for (i = 0; i < fragments; i++) { | |
2254 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2255 | u32 size = frag->size; | |
2256 | offset = 0; | |
2257 | ||
2258 | do { | |
2259 | prev_tx = put_tx; | |
2260 | prev_tx_ctx = np->put_tx_ctx; | |
2261 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
2262 | np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, | |
2263 | PCI_DMA_TODEVICE); | |
2264 | np->put_tx_ctx->dma_len = bcnt; | |
73a37079 | 2265 | np->put_tx_ctx->dma_single = 0; |
5bb7ea26 AV |
2266 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2267 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2268 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 | 2269 | |
86b22b0d AA |
2270 | offset += bcnt; |
2271 | size -= bcnt; | |
445583b8 | 2272 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 2273 | put_tx = np->first_tx.ex; |
445583b8 | 2274 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2275 | np->put_tx_ctx = np->first_tx_ctx; |
2276 | } while (size); | |
2277 | } | |
2278 | ||
2279 | /* set last fragment flag */ | |
445583b8 | 2280 | prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET); |
86b22b0d AA |
2281 | |
2282 | /* save skb in this slot's context area */ | |
2283 | prev_tx_ctx->skb = skb; | |
2284 | ||
2285 | if (skb_is_gso(skb)) | |
2286 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); | |
2287 | else | |
2288 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? | |
2289 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; | |
2290 | ||
2291 | /* vlan tag */ | |
eab6d18d JG |
2292 | if (vlan_tx_tag_present(skb)) |
2293 | start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | | |
2294 | vlan_tx_tag_get(skb)); | |
2295 | else | |
445583b8 | 2296 | start_tx->txvlan = 0; |
86b22b0d | 2297 | |
bd6ca637 | 2298 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2299 | |
3b446c3e AA |
2300 | if (np->tx_limit) { |
2301 | /* Limit the number of outstanding tx. Setup all fragments, but | |
2302 | * do not set the VALID bit on the first descriptor. Save a pointer | |
2303 | * to that descriptor and also for next skb_map element. | |
2304 | */ | |
2305 | ||
2306 | if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) { | |
2307 | if (!np->tx_change_owner) | |
2308 | np->tx_change_owner = start_tx_ctx; | |
2309 | ||
2310 | /* remove VALID bit */ | |
2311 | tx_flags &= ~NV_TX2_VALID; | |
2312 | start_tx_ctx->first_tx_desc = start_tx; | |
2313 | start_tx_ctx->next_tx_ctx = np->put_tx_ctx; | |
2314 | np->tx_end_flip = np->put_tx_ctx; | |
2315 | } else { | |
2316 | np->tx_pkts_in_progress++; | |
2317 | } | |
2318 | } | |
2319 | ||
86b22b0d | 2320 | /* set tx flags */ |
86b22b0d AA |
2321 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
2322 | np->put_tx.ex = put_tx; | |
2323 | ||
bd6ca637 | 2324 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d | 2325 | |
86b22b0d | 2326 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
86b22b0d AA |
2327 | return NETDEV_TX_OK; |
2328 | } | |
2329 | ||
3b446c3e AA |
2330 | static inline void nv_tx_flip_ownership(struct net_device *dev) |
2331 | { | |
2332 | struct fe_priv *np = netdev_priv(dev); | |
2333 | ||
2334 | np->tx_pkts_in_progress--; | |
2335 | if (np->tx_change_owner) { | |
30ecce90 AV |
2336 | np->tx_change_owner->first_tx_desc->flaglen |= |
2337 | cpu_to_le32(NV_TX2_VALID); | |
3b446c3e AA |
2338 | np->tx_pkts_in_progress++; |
2339 | ||
2340 | np->tx_change_owner = np->tx_change_owner->next_tx_ctx; | |
2341 | if (np->tx_change_owner == np->tx_end_flip) | |
2342 | np->tx_change_owner = NULL; | |
2343 | ||
2344 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
2345 | } | |
2346 | } | |
2347 | ||
1da177e4 LT |
2348 | /* |
2349 | * nv_tx_done: check for completed packets, release the skbs. | |
2350 | * | |
2351 | * Caller must own np->lock. | |
2352 | */ | |
33912e72 | 2353 | static int nv_tx_done(struct net_device *dev, int limit) |
1da177e4 | 2354 | { |
ac9c1897 | 2355 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2356 | u32 flags; |
33912e72 | 2357 | int tx_work = 0; |
78aea4fc | 2358 | struct ring_desc *orig_get_tx = np->get_tx.orig; |
1da177e4 | 2359 | |
445583b8 | 2360 | while ((np->get_tx.orig != np->put_tx.orig) && |
33912e72 AA |
2361 | !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) && |
2362 | (tx_work < limit)) { | |
1da177e4 | 2363 | |
73a37079 | 2364 | nv_unmap_txskb(np, np->get_tx_ctx); |
445583b8 | 2365 | |
1da177e4 | 2366 | if (np->desc_ver == DESC_VER_1) { |
f82a9352 | 2367 | if (flags & NV_TX_LASTPACKET) { |
445583b8 | 2368 | if (flags & NV_TX_ERROR) { |
f82a9352 | 2369 | if (flags & NV_TX_UNDERFLOW) |
8148ff45 | 2370 | dev->stats.tx_fifo_errors++; |
f82a9352 | 2371 | if (flags & NV_TX_CARRIERLOST) |
8148ff45 | 2372 | dev->stats.tx_carrier_errors++; |
a433686c AA |
2373 | if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK)) |
2374 | nv_legacybackoff_reseed(dev); | |
8148ff45 | 2375 | dev->stats.tx_errors++; |
ac9c1897 | 2376 | } else { |
8148ff45 JG |
2377 | dev->stats.tx_packets++; |
2378 | dev->stats.tx_bytes += np->get_tx_ctx->skb->len; | |
ac9c1897 | 2379 | } |
445583b8 AA |
2380 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2381 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2382 | tx_work++; |
1da177e4 LT |
2383 | } |
2384 | } else { | |
f82a9352 | 2385 | if (flags & NV_TX2_LASTPACKET) { |
445583b8 | 2386 | if (flags & NV_TX2_ERROR) { |
f82a9352 | 2387 | if (flags & NV_TX2_UNDERFLOW) |
8148ff45 | 2388 | dev->stats.tx_fifo_errors++; |
f82a9352 | 2389 | if (flags & NV_TX2_CARRIERLOST) |
8148ff45 | 2390 | dev->stats.tx_carrier_errors++; |
a433686c AA |
2391 | if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) |
2392 | nv_legacybackoff_reseed(dev); | |
8148ff45 | 2393 | dev->stats.tx_errors++; |
ac9c1897 | 2394 | } else { |
8148ff45 JG |
2395 | dev->stats.tx_packets++; |
2396 | dev->stats.tx_bytes += np->get_tx_ctx->skb->len; | |
f3b197ac | 2397 | } |
445583b8 AA |
2398 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2399 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2400 | tx_work++; |
1da177e4 LT |
2401 | } |
2402 | } | |
445583b8 | 2403 | if (unlikely(np->get_tx.orig++ == np->last_tx.orig)) |
86b22b0d | 2404 | np->get_tx.orig = np->first_tx.orig; |
445583b8 | 2405 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2406 | np->get_tx_ctx = np->first_tx_ctx; |
2407 | } | |
445583b8 | 2408 | if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) { |
aaa37d2d | 2409 | np->tx_stop = 0; |
86b22b0d | 2410 | netif_wake_queue(dev); |
aaa37d2d | 2411 | } |
33912e72 | 2412 | return tx_work; |
86b22b0d AA |
2413 | } |
2414 | ||
33912e72 | 2415 | static int nv_tx_done_optimized(struct net_device *dev, int limit) |
86b22b0d AA |
2416 | { |
2417 | struct fe_priv *np = netdev_priv(dev); | |
2418 | u32 flags; | |
33912e72 | 2419 | int tx_work = 0; |
78aea4fc | 2420 | struct ring_desc_ex *orig_get_tx = np->get_tx.ex; |
86b22b0d | 2421 | |
445583b8 | 2422 | while ((np->get_tx.ex != np->put_tx.ex) && |
217d32dc | 2423 | !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) && |
33912e72 | 2424 | (tx_work < limit)) { |
86b22b0d | 2425 | |
73a37079 | 2426 | nv_unmap_txskb(np, np->get_tx_ctx); |
445583b8 | 2427 | |
86b22b0d | 2428 | if (flags & NV_TX2_LASTPACKET) { |
21828163 | 2429 | if (!(flags & NV_TX2_ERROR)) |
8148ff45 | 2430 | dev->stats.tx_packets++; |
a433686c AA |
2431 | else { |
2432 | if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) { | |
2433 | if (np->driver_data & DEV_HAS_GEAR_MODE) | |
2434 | nv_gear_backoff_reseed(dev); | |
2435 | else | |
2436 | nv_legacybackoff_reseed(dev); | |
2437 | } | |
2438 | } | |
2439 | ||
445583b8 AA |
2440 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2441 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2442 | tx_work++; |
3b446c3e | 2443 | |
78aea4fc | 2444 | if (np->tx_limit) |
3b446c3e | 2445 | nv_tx_flip_ownership(dev); |
761fcd9e | 2446 | } |
445583b8 | 2447 | if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) |
86b22b0d | 2448 | np->get_tx.ex = np->first_tx.ex; |
445583b8 | 2449 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2450 | np->get_tx_ctx = np->first_tx_ctx; |
1da177e4 | 2451 | } |
445583b8 | 2452 | if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) { |
aaa37d2d | 2453 | np->tx_stop = 0; |
1da177e4 | 2454 | netif_wake_queue(dev); |
aaa37d2d | 2455 | } |
33912e72 | 2456 | return tx_work; |
1da177e4 LT |
2457 | } |
2458 | ||
2459 | /* | |
2460 | * nv_tx_timeout: dev->tx_timeout function | |
932ff279 | 2461 | * Called with netif_tx_lock held. |
1da177e4 LT |
2462 | */ |
2463 | static void nv_tx_timeout(struct net_device *dev) | |
2464 | { | |
ac9c1897 | 2465 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2466 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 2467 | u32 status; |
8f955d7f AA |
2468 | union ring_type put_tx; |
2469 | int saved_tx_limit; | |
294a554e | 2470 | int i; |
d33a73c8 AA |
2471 | |
2472 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
2473 | status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
2474 | else | |
2475 | status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
1da177e4 | 2476 | |
1d397f36 | 2477 | netdev_info(dev, "Got tx_timeout. irq: %08x\n", status); |
1da177e4 | 2478 | |
1d397f36 JP |
2479 | netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr); |
2480 | netdev_info(dev, "Dumping tx registers\n"); | |
294a554e | 2481 | for (i = 0; i <= np->register_size; i += 32) { |
1d397f36 JP |
2482 | netdev_info(dev, |
2483 | "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", | |
2484 | i, | |
2485 | readl(base + i + 0), readl(base + i + 4), | |
2486 | readl(base + i + 8), readl(base + i + 12), | |
2487 | readl(base + i + 16), readl(base + i + 20), | |
2488 | readl(base + i + 24), readl(base + i + 28)); | |
2489 | } | |
2490 | netdev_info(dev, "Dumping tx ring\n"); | |
294a554e JP |
2491 | for (i = 0; i < np->tx_ring_size; i += 4) { |
2492 | if (!nv_optimized(np)) { | |
1d397f36 JP |
2493 | netdev_info(dev, |
2494 | "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", | |
2495 | i, | |
2496 | le32_to_cpu(np->tx_ring.orig[i].buf), | |
2497 | le32_to_cpu(np->tx_ring.orig[i].flaglen), | |
2498 | le32_to_cpu(np->tx_ring.orig[i+1].buf), | |
2499 | le32_to_cpu(np->tx_ring.orig[i+1].flaglen), | |
2500 | le32_to_cpu(np->tx_ring.orig[i+2].buf), | |
2501 | le32_to_cpu(np->tx_ring.orig[i+2].flaglen), | |
2502 | le32_to_cpu(np->tx_ring.orig[i+3].buf), | |
2503 | le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); | |
294a554e | 2504 | } else { |
1d397f36 JP |
2505 | netdev_info(dev, |
2506 | "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", | |
2507 | i, | |
2508 | le32_to_cpu(np->tx_ring.ex[i].bufhigh), | |
2509 | le32_to_cpu(np->tx_ring.ex[i].buflow), | |
2510 | le32_to_cpu(np->tx_ring.ex[i].flaglen), | |
2511 | le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), | |
2512 | le32_to_cpu(np->tx_ring.ex[i+1].buflow), | |
2513 | le32_to_cpu(np->tx_ring.ex[i+1].flaglen), | |
2514 | le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), | |
2515 | le32_to_cpu(np->tx_ring.ex[i+2].buflow), | |
2516 | le32_to_cpu(np->tx_ring.ex[i+2].flaglen), | |
2517 | le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), | |
2518 | le32_to_cpu(np->tx_ring.ex[i+3].buflow), | |
2519 | le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); | |
c2dba06d MS |
2520 | } |
2521 | } | |
2522 | ||
1da177e4 LT |
2523 | spin_lock_irq(&np->lock); |
2524 | ||
2525 | /* 1) stop tx engine */ | |
2526 | nv_stop_tx(dev); | |
2527 | ||
8f955d7f AA |
2528 | /* 2) complete any outstanding tx and do not give HW any limited tx pkts */ |
2529 | saved_tx_limit = np->tx_limit; | |
2530 | np->tx_limit = 0; /* prevent giving HW any limited pkts */ | |
2531 | np->tx_stop = 0; /* prevent waking tx queue */ | |
36b30ea9 | 2532 | if (!nv_optimized(np)) |
33912e72 | 2533 | nv_tx_done(dev, np->tx_ring_size); |
86b22b0d | 2534 | else |
4e16ed1b | 2535 | nv_tx_done_optimized(dev, np->tx_ring_size); |
1da177e4 | 2536 | |
25985edc | 2537 | /* save current HW position */ |
8f955d7f AA |
2538 | if (np->tx_change_owner) |
2539 | put_tx.ex = np->tx_change_owner->first_tx_desc; | |
2540 | else | |
2541 | put_tx = np->put_tx; | |
1da177e4 | 2542 | |
8f955d7f AA |
2543 | /* 3) clear all tx state */ |
2544 | nv_drain_tx(dev); | |
2545 | nv_init_tx(dev); | |
2546 | ||
2547 | /* 4) restore state to current HW position */ | |
2548 | np->get_tx = np->put_tx = put_tx; | |
2549 | np->tx_limit = saved_tx_limit; | |
3ba4d093 | 2550 | |
8f955d7f | 2551 | /* 5) restart tx engine */ |
1da177e4 | 2552 | nv_start_tx(dev); |
8f955d7f | 2553 | netif_wake_queue(dev); |
1da177e4 LT |
2554 | spin_unlock_irq(&np->lock); |
2555 | } | |
2556 | ||
22c6d143 MS |
2557 | /* |
2558 | * Called when the nic notices a mismatch between the actual data len on the | |
2559 | * wire and the len indicated in the 802 header | |
2560 | */ | |
2561 | static int nv_getlen(struct net_device *dev, void *packet, int datalen) | |
2562 | { | |
2563 | int hdrlen; /* length of the 802 header */ | |
2564 | int protolen; /* length as stored in the proto field */ | |
2565 | ||
2566 | /* 1) calculate len according to header */ | |
78aea4fc SJ |
2567 | if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) { |
2568 | protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto); | |
22c6d143 MS |
2569 | hdrlen = VLAN_HLEN; |
2570 | } else { | |
78aea4fc | 2571 | protolen = ntohs(((struct ethhdr *)packet)->h_proto); |
22c6d143 MS |
2572 | hdrlen = ETH_HLEN; |
2573 | } | |
22c6d143 MS |
2574 | if (protolen > ETH_DATA_LEN) |
2575 | return datalen; /* Value in proto field not a len, no checks possible */ | |
2576 | ||
2577 | protolen += hdrlen; | |
2578 | /* consistency checks: */ | |
2579 | if (datalen > ETH_ZLEN) { | |
2580 | if (datalen >= protolen) { | |
2581 | /* more data on wire than in 802 header, trim of | |
2582 | * additional data. | |
2583 | */ | |
22c6d143 MS |
2584 | return protolen; |
2585 | } else { | |
2586 | /* less data on wire than mentioned in header. | |
2587 | * Discard the packet. | |
2588 | */ | |
22c6d143 MS |
2589 | return -1; |
2590 | } | |
2591 | } else { | |
2592 | /* short packet. Accept only if 802 values are also short */ | |
2593 | if (protolen > ETH_ZLEN) { | |
22c6d143 MS |
2594 | return -1; |
2595 | } | |
22c6d143 MS |
2596 | return datalen; |
2597 | } | |
2598 | } | |
2599 | ||
e27cdba5 | 2600 | static int nv_rx_process(struct net_device *dev, int limit) |
1da177e4 | 2601 | { |
ac9c1897 | 2602 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2603 | u32 flags; |
bcb5febb | 2604 | int rx_work = 0; |
b01867cb AA |
2605 | struct sk_buff *skb; |
2606 | int len; | |
1da177e4 | 2607 | |
78aea4fc | 2608 | while ((np->get_rx.orig != np->put_rx.orig) && |
b01867cb | 2609 | !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) && |
bcb5febb | 2610 | (rx_work < limit)) { |
1da177e4 | 2611 | |
1da177e4 LT |
2612 | /* |
2613 | * the packet is for us - immediately tear down the pci mapping. | |
2614 | * TODO: check if a prefetch of the first cacheline improves | |
2615 | * the performance. | |
2616 | */ | |
761fcd9e AA |
2617 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, |
2618 | np->get_rx_ctx->dma_len, | |
1da177e4 | 2619 | PCI_DMA_FROMDEVICE); |
0d63fb32 AA |
2620 | skb = np->get_rx_ctx->skb; |
2621 | np->get_rx_ctx->skb = NULL; | |
1da177e4 | 2622 | |
1da177e4 LT |
2623 | /* look at what we actually got: */ |
2624 | if (np->desc_ver == DESC_VER_1) { | |
b01867cb AA |
2625 | if (likely(flags & NV_RX_DESCRIPTORVALID)) { |
2626 | len = flags & LEN_MASK_V1; | |
2627 | if (unlikely(flags & NV_RX_ERROR)) { | |
1ef6841b | 2628 | if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) { |
b01867cb AA |
2629 | len = nv_getlen(dev, skb->data, len); |
2630 | if (len < 0) { | |
8148ff45 | 2631 | dev->stats.rx_errors++; |
b01867cb AA |
2632 | dev_kfree_skb(skb); |
2633 | goto next_pkt; | |
2634 | } | |
2635 | } | |
2636 | /* framing errors are soft errors */ | |
1ef6841b | 2637 | else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) { |
78aea4fc | 2638 | if (flags & NV_RX_SUBSTRACT1) |
b01867cb | 2639 | len--; |
b01867cb AA |
2640 | } |
2641 | /* the rest are hard errors */ | |
2642 | else { | |
2643 | if (flags & NV_RX_MISSEDFRAME) | |
8148ff45 | 2644 | dev->stats.rx_missed_errors++; |
b01867cb | 2645 | if (flags & NV_RX_CRCERR) |
8148ff45 | 2646 | dev->stats.rx_crc_errors++; |
b01867cb | 2647 | if (flags & NV_RX_OVERFLOW) |
8148ff45 JG |
2648 | dev->stats.rx_over_errors++; |
2649 | dev->stats.rx_errors++; | |
0d63fb32 | 2650 | dev_kfree_skb(skb); |
a971c324 AA |
2651 | goto next_pkt; |
2652 | } | |
2653 | } | |
b01867cb | 2654 | } else { |
0d63fb32 | 2655 | dev_kfree_skb(skb); |
1da177e4 | 2656 | goto next_pkt; |
0d63fb32 | 2657 | } |
b01867cb AA |
2658 | } else { |
2659 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { | |
2660 | len = flags & LEN_MASK_V2; | |
2661 | if (unlikely(flags & NV_RX2_ERROR)) { | |
1ef6841b | 2662 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
b01867cb AA |
2663 | len = nv_getlen(dev, skb->data, len); |
2664 | if (len < 0) { | |
8148ff45 | 2665 | dev->stats.rx_errors++; |
b01867cb AA |
2666 | dev_kfree_skb(skb); |
2667 | goto next_pkt; | |
2668 | } | |
2669 | } | |
2670 | /* framing errors are soft errors */ | |
1ef6841b | 2671 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
78aea4fc | 2672 | if (flags & NV_RX2_SUBSTRACT1) |
b01867cb | 2673 | len--; |
b01867cb AA |
2674 | } |
2675 | /* the rest are hard errors */ | |
2676 | else { | |
2677 | if (flags & NV_RX2_CRCERR) | |
8148ff45 | 2678 | dev->stats.rx_crc_errors++; |
b01867cb | 2679 | if (flags & NV_RX2_OVERFLOW) |
8148ff45 JG |
2680 | dev->stats.rx_over_errors++; |
2681 | dev->stats.rx_errors++; | |
0d63fb32 | 2682 | dev_kfree_skb(skb); |
a971c324 AA |
2683 | goto next_pkt; |
2684 | } | |
2685 | } | |
bfaffe8f AA |
2686 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2687 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
0d63fb32 | 2688 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2689 | } else { |
2690 | dev_kfree_skb(skb); | |
2691 | goto next_pkt; | |
1da177e4 LT |
2692 | } |
2693 | } | |
2694 | /* got a valid packet - forward it to the network core */ | |
1da177e4 LT |
2695 | skb_put(skb, len); |
2696 | skb->protocol = eth_type_trans(skb, dev); | |
53f224cc | 2697 | napi_gro_receive(&np->napi, skb); |
8148ff45 JG |
2698 | dev->stats.rx_packets++; |
2699 | dev->stats.rx_bytes += len; | |
1da177e4 | 2700 | next_pkt: |
b01867cb | 2701 | if (unlikely(np->get_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 2702 | np->get_rx.orig = np->first_rx.orig; |
b01867cb | 2703 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d | 2704 | np->get_rx_ctx = np->first_rx_ctx; |
bcb5febb IM |
2705 | |
2706 | rx_work++; | |
86b22b0d AA |
2707 | } |
2708 | ||
bcb5febb | 2709 | return rx_work; |
86b22b0d AA |
2710 | } |
2711 | ||
2712 | static int nv_rx_process_optimized(struct net_device *dev, int limit) | |
2713 | { | |
2714 | struct fe_priv *np = netdev_priv(dev); | |
2715 | u32 flags; | |
2716 | u32 vlanflags = 0; | |
c1b7151a | 2717 | int rx_work = 0; |
b01867cb AA |
2718 | struct sk_buff *skb; |
2719 | int len; | |
86b22b0d | 2720 | |
78aea4fc | 2721 | while ((np->get_rx.ex != np->put_rx.ex) && |
b01867cb | 2722 | !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) && |
c1b7151a | 2723 | (rx_work < limit)) { |
86b22b0d | 2724 | |
86b22b0d AA |
2725 | /* |
2726 | * the packet is for us - immediately tear down the pci mapping. | |
2727 | * TODO: check if a prefetch of the first cacheline improves | |
2728 | * the performance. | |
2729 | */ | |
2730 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, | |
2731 | np->get_rx_ctx->dma_len, | |
2732 | PCI_DMA_FROMDEVICE); | |
2733 | skb = np->get_rx_ctx->skb; | |
2734 | np->get_rx_ctx->skb = NULL; | |
2735 | ||
86b22b0d | 2736 | /* look at what we actually got: */ |
b01867cb AA |
2737 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { |
2738 | len = flags & LEN_MASK_V2; | |
2739 | if (unlikely(flags & NV_RX2_ERROR)) { | |
1ef6841b | 2740 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
b01867cb AA |
2741 | len = nv_getlen(dev, skb->data, len); |
2742 | if (len < 0) { | |
b01867cb AA |
2743 | dev_kfree_skb(skb); |
2744 | goto next_pkt; | |
2745 | } | |
2746 | } | |
2747 | /* framing errors are soft errors */ | |
1ef6841b | 2748 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
78aea4fc | 2749 | if (flags & NV_RX2_SUBSTRACT1) |
b01867cb | 2750 | len--; |
b01867cb AA |
2751 | } |
2752 | /* the rest are hard errors */ | |
2753 | else { | |
86b22b0d AA |
2754 | dev_kfree_skb(skb); |
2755 | goto next_pkt; | |
2756 | } | |
2757 | } | |
b01867cb | 2758 | |
bfaffe8f AA |
2759 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2760 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
86b22b0d | 2761 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2762 | |
2763 | /* got a valid packet - forward it to the network core */ | |
2764 | skb_put(skb, len); | |
2765 | skb->protocol = eth_type_trans(skb, dev); | |
2766 | prefetch(skb->data); | |
2767 | ||
b01867cb | 2768 | if (likely(!np->vlangrp)) { |
53f224cc | 2769 | napi_gro_receive(&np->napi, skb); |
b01867cb AA |
2770 | } else { |
2771 | vlanflags = le32_to_cpu(np->get_rx.ex->buflow); | |
2772 | if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) { | |
53f224cc TH |
2773 | vlan_gro_receive(&np->napi, np->vlangrp, |
2774 | vlanflags & NV_RX3_VLAN_TAG_MASK, skb); | |
b01867cb | 2775 | } else { |
53f224cc | 2776 | napi_gro_receive(&np->napi, skb); |
b01867cb AA |
2777 | } |
2778 | } | |
2779 | ||
8148ff45 JG |
2780 | dev->stats.rx_packets++; |
2781 | dev->stats.rx_bytes += len; | |
b01867cb AA |
2782 | } else { |
2783 | dev_kfree_skb(skb); | |
2784 | } | |
86b22b0d | 2785 | next_pkt: |
b01867cb | 2786 | if (unlikely(np->get_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 2787 | np->get_rx.ex = np->first_rx.ex; |
b01867cb | 2788 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
761fcd9e | 2789 | np->get_rx_ctx = np->first_rx_ctx; |
c1b7151a IM |
2790 | |
2791 | rx_work++; | |
1da177e4 | 2792 | } |
e27cdba5 | 2793 | |
c1b7151a | 2794 | return rx_work; |
1da177e4 LT |
2795 | } |
2796 | ||
d81c0983 MS |
2797 | static void set_bufsize(struct net_device *dev) |
2798 | { | |
2799 | struct fe_priv *np = netdev_priv(dev); | |
2800 | ||
2801 | if (dev->mtu <= ETH_DATA_LEN) | |
2802 | np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; | |
2803 | else | |
2804 | np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; | |
2805 | } | |
2806 | ||
1da177e4 LT |
2807 | /* |
2808 | * nv_change_mtu: dev->change_mtu function | |
2809 | * Called with dev_base_lock held for read. | |
2810 | */ | |
2811 | static int nv_change_mtu(struct net_device *dev, int new_mtu) | |
2812 | { | |
ac9c1897 | 2813 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 MS |
2814 | int old_mtu; |
2815 | ||
2816 | if (new_mtu < 64 || new_mtu > np->pkt_limit) | |
1da177e4 | 2817 | return -EINVAL; |
d81c0983 MS |
2818 | |
2819 | old_mtu = dev->mtu; | |
1da177e4 | 2820 | dev->mtu = new_mtu; |
d81c0983 MS |
2821 | |
2822 | /* return early if the buffer sizes will not change */ | |
2823 | if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) | |
2824 | return 0; | |
2825 | if (old_mtu == new_mtu) | |
2826 | return 0; | |
2827 | ||
2828 | /* synchronized against open : rtnl_lock() held by caller */ | |
2829 | if (netif_running(dev)) { | |
25097d4b | 2830 | u8 __iomem *base = get_hwbase(dev); |
d81c0983 MS |
2831 | /* |
2832 | * It seems that the nic preloads valid ring entries into an | |
2833 | * internal buffer. The procedure for flushing everything is | |
2834 | * guessed, there is probably a simpler approach. | |
2835 | * Changing the MTU is a rare event, it shouldn't matter. | |
2836 | */ | |
84b3932b | 2837 | nv_disable_irq(dev); |
08d93575 | 2838 | nv_napi_disable(dev); |
932ff279 | 2839 | netif_tx_lock_bh(dev); |
e308a5d8 | 2840 | netif_addr_lock(dev); |
d81c0983 MS |
2841 | spin_lock(&np->lock); |
2842 | /* stop engines */ | |
36b30ea9 | 2843 | nv_stop_rxtx(dev); |
d81c0983 MS |
2844 | nv_txrx_reset(dev); |
2845 | /* drain rx queue */ | |
36b30ea9 | 2846 | nv_drain_rxtx(dev); |
d81c0983 | 2847 | /* reinit driver view of the rx queue */ |
d81c0983 | 2848 | set_bufsize(dev); |
eafa59f6 | 2849 | if (nv_init_ring(dev)) { |
d81c0983 MS |
2850 | if (!np->in_shutdown) |
2851 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
2852 | } | |
2853 | /* reinit nic view of the rx queue */ | |
2854 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
0832b25a | 2855 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
78aea4fc | 2856 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
d81c0983 MS |
2857 | base + NvRegRingSizes); |
2858 | pci_push(base); | |
8a4ae7f2 | 2859 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
d81c0983 MS |
2860 | pci_push(base); |
2861 | ||
2862 | /* restart rx engine */ | |
36b30ea9 | 2863 | nv_start_rxtx(dev); |
d81c0983 | 2864 | spin_unlock(&np->lock); |
e308a5d8 | 2865 | netif_addr_unlock(dev); |
932ff279 | 2866 | netif_tx_unlock_bh(dev); |
08d93575 | 2867 | nv_napi_enable(dev); |
84b3932b | 2868 | nv_enable_irq(dev); |
d81c0983 | 2869 | } |
1da177e4 LT |
2870 | return 0; |
2871 | } | |
2872 | ||
72b31782 MS |
2873 | static void nv_copy_mac_to_hw(struct net_device *dev) |
2874 | { | |
25097d4b | 2875 | u8 __iomem *base = get_hwbase(dev); |
72b31782 MS |
2876 | u32 mac[2]; |
2877 | ||
2878 | mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + | |
2879 | (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); | |
2880 | mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); | |
2881 | ||
2882 | writel(mac[0], base + NvRegMacAddrA); | |
2883 | writel(mac[1], base + NvRegMacAddrB); | |
2884 | } | |
2885 | ||
2886 | /* | |
2887 | * nv_set_mac_address: dev->set_mac_address function | |
2888 | * Called with rtnl_lock() held. | |
2889 | */ | |
2890 | static int nv_set_mac_address(struct net_device *dev, void *addr) | |
2891 | { | |
ac9c1897 | 2892 | struct fe_priv *np = netdev_priv(dev); |
78aea4fc | 2893 | struct sockaddr *macaddr = (struct sockaddr *)addr; |
72b31782 | 2894 | |
f82a9352 | 2895 | if (!is_valid_ether_addr(macaddr->sa_data)) |
72b31782 MS |
2896 | return -EADDRNOTAVAIL; |
2897 | ||
2898 | /* synchronized against open : rtnl_lock() held by caller */ | |
2899 | memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); | |
2900 | ||
2901 | if (netif_running(dev)) { | |
932ff279 | 2902 | netif_tx_lock_bh(dev); |
e308a5d8 | 2903 | netif_addr_lock(dev); |
72b31782 MS |
2904 | spin_lock_irq(&np->lock); |
2905 | ||
2906 | /* stop rx engine */ | |
2907 | nv_stop_rx(dev); | |
2908 | ||
2909 | /* set mac address */ | |
2910 | nv_copy_mac_to_hw(dev); | |
2911 | ||
2912 | /* restart rx engine */ | |
2913 | nv_start_rx(dev); | |
2914 | spin_unlock_irq(&np->lock); | |
e308a5d8 | 2915 | netif_addr_unlock(dev); |
932ff279 | 2916 | netif_tx_unlock_bh(dev); |
72b31782 MS |
2917 | } else { |
2918 | nv_copy_mac_to_hw(dev); | |
2919 | } | |
2920 | return 0; | |
2921 | } | |
2922 | ||
1da177e4 LT |
2923 | /* |
2924 | * nv_set_multicast: dev->set_multicast function | |
932ff279 | 2925 | * Called with netif_tx_lock held. |
1da177e4 LT |
2926 | */ |
2927 | static void nv_set_multicast(struct net_device *dev) | |
2928 | { | |
ac9c1897 | 2929 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
2930 | u8 __iomem *base = get_hwbase(dev); |
2931 | u32 addr[2]; | |
2932 | u32 mask[2]; | |
b6d0773f | 2933 | u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX; |
1da177e4 LT |
2934 | |
2935 | memset(addr, 0, sizeof(addr)); | |
2936 | memset(mask, 0, sizeof(mask)); | |
2937 | ||
2938 | if (dev->flags & IFF_PROMISC) { | |
b6d0773f | 2939 | pff |= NVREG_PFF_PROMISC; |
1da177e4 | 2940 | } else { |
b6d0773f | 2941 | pff |= NVREG_PFF_MYADDR; |
1da177e4 | 2942 | |
48e2f183 | 2943 | if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) { |
1da177e4 LT |
2944 | u32 alwaysOff[2]; |
2945 | u32 alwaysOn[2]; | |
2946 | ||
2947 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; | |
2948 | if (dev->flags & IFF_ALLMULTI) { | |
2949 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; | |
2950 | } else { | |
22bedad3 | 2951 | struct netdev_hw_addr *ha; |
1da177e4 | 2952 | |
22bedad3 JP |
2953 | netdev_for_each_mc_addr(ha, dev) { |
2954 | unsigned char *addr = ha->addr; | |
1da177e4 | 2955 | u32 a, b; |
22bedad3 JP |
2956 | |
2957 | a = le32_to_cpu(*(__le32 *) addr); | |
2958 | b = le16_to_cpu(*(__le16 *) (&addr[4])); | |
1da177e4 LT |
2959 | alwaysOn[0] &= a; |
2960 | alwaysOff[0] &= ~a; | |
2961 | alwaysOn[1] &= b; | |
2962 | alwaysOff[1] &= ~b; | |
1da177e4 LT |
2963 | } |
2964 | } | |
2965 | addr[0] = alwaysOn[0]; | |
2966 | addr[1] = alwaysOn[1]; | |
2967 | mask[0] = alwaysOn[0] | alwaysOff[0]; | |
2968 | mask[1] = alwaysOn[1] | alwaysOff[1]; | |
bb9a4fd1 AA |
2969 | } else { |
2970 | mask[0] = NVREG_MCASTMASKA_NONE; | |
2971 | mask[1] = NVREG_MCASTMASKB_NONE; | |
1da177e4 LT |
2972 | } |
2973 | } | |
2974 | addr[0] |= NVREG_MCASTADDRA_FORCE; | |
2975 | pff |= NVREG_PFF_ALWAYS; | |
2976 | spin_lock_irq(&np->lock); | |
2977 | nv_stop_rx(dev); | |
2978 | writel(addr[0], base + NvRegMulticastAddrA); | |
2979 | writel(addr[1], base + NvRegMulticastAddrB); | |
2980 | writel(mask[0], base + NvRegMulticastMaskA); | |
2981 | writel(mask[1], base + NvRegMulticastMaskB); | |
2982 | writel(pff, base + NvRegPacketFilterFlags); | |
1da177e4 LT |
2983 | nv_start_rx(dev); |
2984 | spin_unlock_irq(&np->lock); | |
2985 | } | |
2986 | ||
c7985051 | 2987 | static void nv_update_pause(struct net_device *dev, u32 pause_flags) |
b6d0773f AA |
2988 | { |
2989 | struct fe_priv *np = netdev_priv(dev); | |
2990 | u8 __iomem *base = get_hwbase(dev); | |
2991 | ||
2992 | np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE); | |
2993 | ||
2994 | if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) { | |
2995 | u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX; | |
2996 | if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) { | |
2997 | writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags); | |
2998 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
2999 | } else { | |
3000 | writel(pff, base + NvRegPacketFilterFlags); | |
3001 | } | |
3002 | } | |
3003 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) { | |
3004 | u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX; | |
3005 | if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) { | |
5289b4c4 AA |
3006 | u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1; |
3007 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) | |
3008 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2; | |
9a33e883 | 3009 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) { |
5289b4c4 | 3010 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3; |
9a33e883 AA |
3011 | /* limit the number of tx pause frames to a default of 8 */ |
3012 | writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit); | |
3013 | } | |
5289b4c4 | 3014 | writel(pause_enable, base + NvRegTxPauseFrame); |
b6d0773f AA |
3015 | writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); |
3016 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3017 | } else { | |
3018 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
3019 | writel(regmisc, base + NvRegMisc1); | |
3020 | } | |
3021 | } | |
3022 | } | |
3023 | ||
4ea7f299 AA |
3024 | /** |
3025 | * nv_update_linkspeed: Setup the MAC according to the link partner | |
3026 | * @dev: Network device to be configured | |
3027 | * | |
3028 | * The function queries the PHY and checks if there is a link partner. | |
3029 | * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is | |
3030 | * set to 10 MBit HD. | |
3031 | * | |
3032 | * The function returns 0 if there is no link partner and 1 if there is | |
3033 | * a good link partner. | |
3034 | */ | |
1da177e4 LT |
3035 | static int nv_update_linkspeed(struct net_device *dev) |
3036 | { | |
ac9c1897 | 3037 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3038 | u8 __iomem *base = get_hwbase(dev); |
eb91f61b AA |
3039 | int adv = 0; |
3040 | int lpa = 0; | |
3041 | int adv_lpa, adv_pause, lpa_pause; | |
1da177e4 LT |
3042 | int newls = np->linkspeed; |
3043 | int newdup = np->duplex; | |
3044 | int mii_status; | |
3045 | int retval = 0; | |
9744e218 | 3046 | u32 control_1000, status_1000, phyreg, pause_flags, txreg; |
b2976d23 | 3047 | u32 txrxFlags = 0; |
fd9b558c | 3048 | u32 phy_exp; |
1da177e4 LT |
3049 | |
3050 | /* BMSR_LSTATUS is latched, read it twice: | |
3051 | * we want the current value. | |
3052 | */ | |
3053 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3054 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3055 | ||
3056 | if (!(mii_status & BMSR_LSTATUS)) { | |
1da177e4 LT |
3057 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3058 | newdup = 0; | |
3059 | retval = 0; | |
3060 | goto set_speed; | |
3061 | } | |
3062 | ||
3063 | if (np->autoneg == 0) { | |
1da177e4 LT |
3064 | if (np->fixed_mode & LPA_100FULL) { |
3065 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
3066 | newdup = 1; | |
3067 | } else if (np->fixed_mode & LPA_100HALF) { | |
3068 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
3069 | newdup = 0; | |
3070 | } else if (np->fixed_mode & LPA_10FULL) { | |
3071 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3072 | newdup = 1; | |
3073 | } else { | |
3074 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3075 | newdup = 0; | |
3076 | } | |
3077 | retval = 1; | |
3078 | goto set_speed; | |
3079 | } | |
3080 | /* check auto negotiation is complete */ | |
3081 | if (!(mii_status & BMSR_ANEGCOMPLETE)) { | |
3082 | /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ | |
3083 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3084 | newdup = 0; | |
3085 | retval = 0; | |
1da177e4 LT |
3086 | goto set_speed; |
3087 | } | |
3088 | ||
b6d0773f AA |
3089 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
3090 | lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); | |
b6d0773f | 3091 | |
1da177e4 LT |
3092 | retval = 1; |
3093 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b AA |
3094 | control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
3095 | status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); | |
1da177e4 LT |
3096 | |
3097 | if ((control_1000 & ADVERTISE_1000FULL) && | |
3098 | (status_1000 & LPA_1000FULL)) { | |
1da177e4 LT |
3099 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; |
3100 | newdup = 1; | |
3101 | goto set_speed; | |
3102 | } | |
3103 | } | |
3104 | ||
1da177e4 | 3105 | /* FIXME: handle parallel detection properly */ |
eb91f61b AA |
3106 | adv_lpa = lpa & adv; |
3107 | if (adv_lpa & LPA_100FULL) { | |
1da177e4 LT |
3108 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3109 | newdup = 1; | |
eb91f61b | 3110 | } else if (adv_lpa & LPA_100HALF) { |
1da177e4 LT |
3111 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3112 | newdup = 0; | |
eb91f61b | 3113 | } else if (adv_lpa & LPA_10FULL) { |
1da177e4 LT |
3114 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3115 | newdup = 1; | |
eb91f61b | 3116 | } else if (adv_lpa & LPA_10HALF) { |
1da177e4 LT |
3117 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3118 | newdup = 0; | |
3119 | } else { | |
1da177e4 LT |
3120 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3121 | newdup = 0; | |
3122 | } | |
3123 | ||
3124 | set_speed: | |
3125 | if (np->duplex == newdup && np->linkspeed == newls) | |
3126 | return retval; | |
3127 | ||
1da177e4 LT |
3128 | np->duplex = newdup; |
3129 | np->linkspeed = newls; | |
3130 | ||
b2976d23 AA |
3131 | /* The transmitter and receiver must be restarted for safe update */ |
3132 | if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) { | |
3133 | txrxFlags |= NV_RESTART_TX; | |
3134 | nv_stop_tx(dev); | |
3135 | } | |
3136 | if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { | |
3137 | txrxFlags |= NV_RESTART_RX; | |
3138 | nv_stop_rx(dev); | |
3139 | } | |
3140 | ||
1da177e4 | 3141 | if (np->gigabit == PHY_GIGABIT) { |
a433686c | 3142 | phyreg = readl(base + NvRegSlotTime); |
1da177e4 | 3143 | phyreg &= ~(0x3FF00); |
a433686c AA |
3144 | if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) || |
3145 | ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)) | |
3146 | phyreg |= NVREG_SLOTTIME_10_100_FULL; | |
1da177e4 | 3147 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) |
a433686c AA |
3148 | phyreg |= NVREG_SLOTTIME_1000_FULL; |
3149 | writel(phyreg, base + NvRegSlotTime); | |
1da177e4 LT |
3150 | } |
3151 | ||
3152 | phyreg = readl(base + NvRegPhyInterface); | |
3153 | phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); | |
3154 | if (np->duplex == 0) | |
3155 | phyreg |= PHY_HALF; | |
3156 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) | |
3157 | phyreg |= PHY_100; | |
3158 | else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3159 | phyreg |= PHY_1000; | |
3160 | writel(phyreg, base + NvRegPhyInterface); | |
3161 | ||
fd9b558c | 3162 | phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ |
9744e218 | 3163 | if (phyreg & PHY_RGMII) { |
fd9b558c | 3164 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) { |
9744e218 | 3165 | txreg = NVREG_TX_DEFERRAL_RGMII_1000; |
fd9b558c AA |
3166 | } else { |
3167 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) { | |
3168 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10) | |
3169 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10; | |
3170 | else | |
3171 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100; | |
3172 | } else { | |
3173 | txreg = NVREG_TX_DEFERRAL_RGMII_10_100; | |
3174 | } | |
3175 | } | |
9744e218 | 3176 | } else { |
fd9b558c AA |
3177 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) |
3178 | txreg = NVREG_TX_DEFERRAL_MII_STRETCH; | |
3179 | else | |
3180 | txreg = NVREG_TX_DEFERRAL_DEFAULT; | |
9744e218 AA |
3181 | } |
3182 | writel(txreg, base + NvRegTxDeferral); | |
3183 | ||
95d161cb AA |
3184 | if (np->desc_ver == DESC_VER_1) { |
3185 | txreg = NVREG_TX_WM_DESC1_DEFAULT; | |
3186 | } else { | |
3187 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3188 | txreg = NVREG_TX_WM_DESC2_3_1000; | |
3189 | else | |
3190 | txreg = NVREG_TX_WM_DESC2_3_DEFAULT; | |
3191 | } | |
3192 | writel(txreg, base + NvRegTxWatermark); | |
3193 | ||
78aea4fc | 3194 | writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), |
1da177e4 LT |
3195 | base + NvRegMisc1); |
3196 | pci_push(base); | |
3197 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
3198 | pci_push(base); | |
3199 | ||
b6d0773f AA |
3200 | pause_flags = 0; |
3201 | /* setup pause frame */ | |
eb91f61b | 3202 | if (np->duplex != 0) { |
b6d0773f | 3203 | if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { |
78aea4fc SJ |
3204 | adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
3205 | lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM); | |
b6d0773f AA |
3206 | |
3207 | switch (adv_pause) { | |
f82a9352 | 3208 | case ADVERTISE_PAUSE_CAP: |
b6d0773f AA |
3209 | if (lpa_pause & LPA_PAUSE_CAP) { |
3210 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3211 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3212 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3213 | } | |
3214 | break; | |
f82a9352 | 3215 | case ADVERTISE_PAUSE_ASYM: |
78aea4fc | 3216 | if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM)) |
b6d0773f | 3217 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
b6d0773f | 3218 | break; |
78aea4fc SJ |
3219 | case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM: |
3220 | if (lpa_pause & LPA_PAUSE_CAP) { | |
b6d0773f AA |
3221 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
3222 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3223 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3224 | } | |
3225 | if (lpa_pause == LPA_PAUSE_ASYM) | |
b6d0773f | 3226 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
b6d0773f | 3227 | break; |
f3b197ac | 3228 | } |
eb91f61b | 3229 | } else { |
b6d0773f | 3230 | pause_flags = np->pause_flags; |
eb91f61b AA |
3231 | } |
3232 | } | |
b6d0773f | 3233 | nv_update_pause(dev, pause_flags); |
eb91f61b | 3234 | |
b2976d23 AA |
3235 | if (txrxFlags & NV_RESTART_TX) |
3236 | nv_start_tx(dev); | |
3237 | if (txrxFlags & NV_RESTART_RX) | |
3238 | nv_start_rx(dev); | |
3239 | ||
1da177e4 LT |
3240 | return retval; |
3241 | } | |
3242 | ||
3243 | static void nv_linkchange(struct net_device *dev) | |
3244 | { | |
3245 | if (nv_update_linkspeed(dev)) { | |
4ea7f299 | 3246 | if (!netif_carrier_ok(dev)) { |
1da177e4 | 3247 | netif_carrier_on(dev); |
1d397f36 | 3248 | netdev_info(dev, "link up\n"); |
88d7d8b0 | 3249 | nv_txrx_gate(dev, false); |
4ea7f299 | 3250 | nv_start_rx(dev); |
1da177e4 | 3251 | } |
1da177e4 LT |
3252 | } else { |
3253 | if (netif_carrier_ok(dev)) { | |
3254 | netif_carrier_off(dev); | |
1d397f36 | 3255 | netdev_info(dev, "link down\n"); |
88d7d8b0 | 3256 | nv_txrx_gate(dev, true); |
1da177e4 LT |
3257 | nv_stop_rx(dev); |
3258 | } | |
3259 | } | |
3260 | } | |
3261 | ||
3262 | static void nv_link_irq(struct net_device *dev) | |
3263 | { | |
3264 | u8 __iomem *base = get_hwbase(dev); | |
3265 | u32 miistat; | |
3266 | ||
3267 | miistat = readl(base + NvRegMIIStatus); | |
eb798428 | 3268 | writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus); |
1da177e4 LT |
3269 | |
3270 | if (miistat & (NVREG_MIISTAT_LINKCHANGE)) | |
3271 | nv_linkchange(dev); | |
1da177e4 LT |
3272 | } |
3273 | ||
4db0ee17 AA |
3274 | static void nv_msi_workaround(struct fe_priv *np) |
3275 | { | |
3276 | ||
3277 | /* Need to toggle the msi irq mask within the ethernet device, | |
3278 | * otherwise, future interrupts will not be detected. | |
3279 | */ | |
3280 | if (np->msi_flags & NV_MSI_ENABLED) { | |
3281 | u8 __iomem *base = np->base; | |
3282 | ||
3283 | writel(0, base + NvRegMSIIrqMask); | |
3284 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
3285 | } | |
3286 | } | |
3287 | ||
4145ade2 AA |
3288 | static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work) |
3289 | { | |
3290 | struct fe_priv *np = netdev_priv(dev); | |
3291 | ||
3292 | if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) { | |
3293 | if (total_work > NV_DYNAMIC_THRESHOLD) { | |
3294 | /* transition to poll based interrupts */ | |
3295 | np->quiet_count = 0; | |
3296 | if (np->irqmask != NVREG_IRQMASK_CPU) { | |
3297 | np->irqmask = NVREG_IRQMASK_CPU; | |
3298 | return 1; | |
3299 | } | |
3300 | } else { | |
3301 | if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) { | |
3302 | np->quiet_count++; | |
3303 | } else { | |
3304 | /* reached a period of low activity, switch | |
3305 | to per tx/rx packet interrupts */ | |
3306 | if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) { | |
3307 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
3308 | return 1; | |
3309 | } | |
3310 | } | |
3311 | } | |
3312 | } | |
3313 | return 0; | |
3314 | } | |
3315 | ||
7d12e780 | 3316 | static irqreturn_t nv_nic_irq(int foo, void *data) |
1da177e4 LT |
3317 | { |
3318 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 3319 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3320 | u8 __iomem *base = get_hwbase(dev); |
1da177e4 | 3321 | |
b67874ac AA |
3322 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3323 | np->events = readl(base + NvRegIrqStatus); | |
1b2bb76f | 3324 | writel(np->events, base + NvRegIrqStatus); |
b67874ac AA |
3325 | } else { |
3326 | np->events = readl(base + NvRegMSIXIrqStatus); | |
1b2bb76f | 3327 | writel(np->events, base + NvRegMSIXIrqStatus); |
b67874ac | 3328 | } |
b67874ac AA |
3329 | if (!(np->events & np->irqmask)) |
3330 | return IRQ_NONE; | |
1da177e4 | 3331 | |
b67874ac | 3332 | nv_msi_workaround(np); |
4db0ee17 | 3333 | |
78c29bd9 ED |
3334 | if (napi_schedule_prep(&np->napi)) { |
3335 | /* | |
3336 | * Disable further irq's (msix not enabled with napi) | |
3337 | */ | |
3338 | writel(0, base + NvRegIrqMask); | |
3339 | __napi_schedule(&np->napi); | |
3340 | } | |
f0734ab6 | 3341 | |
b67874ac | 3342 | return IRQ_HANDLED; |
1da177e4 LT |
3343 | } |
3344 | ||
f0734ab6 AA |
3345 | /** |
3346 | * All _optimized functions are used to help increase performance | |
3347 | * (reduce CPU and increase throughput). They use descripter version 3, | |
3348 | * compiler directives, and reduce memory accesses. | |
3349 | */ | |
86b22b0d AA |
3350 | static irqreturn_t nv_nic_irq_optimized(int foo, void *data) |
3351 | { | |
3352 | struct net_device *dev = (struct net_device *) data; | |
3353 | struct fe_priv *np = netdev_priv(dev); | |
3354 | u8 __iomem *base = get_hwbase(dev); | |
86b22b0d | 3355 | |
b67874ac AA |
3356 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3357 | np->events = readl(base + NvRegIrqStatus); | |
1b2bb76f | 3358 | writel(np->events, base + NvRegIrqStatus); |
b67874ac AA |
3359 | } else { |
3360 | np->events = readl(base + NvRegMSIXIrqStatus); | |
1b2bb76f | 3361 | writel(np->events, base + NvRegMSIXIrqStatus); |
b67874ac | 3362 | } |
b67874ac AA |
3363 | if (!(np->events & np->irqmask)) |
3364 | return IRQ_NONE; | |
86b22b0d | 3365 | |
b67874ac | 3366 | nv_msi_workaround(np); |
4db0ee17 | 3367 | |
78c29bd9 ED |
3368 | if (napi_schedule_prep(&np->napi)) { |
3369 | /* | |
3370 | * Disable further irq's (msix not enabled with napi) | |
3371 | */ | |
3372 | writel(0, base + NvRegIrqMask); | |
3373 | __napi_schedule(&np->napi); | |
3374 | } | |
86b22b0d | 3375 | |
b67874ac | 3376 | return IRQ_HANDLED; |
86b22b0d AA |
3377 | } |
3378 | ||
7d12e780 | 3379 | static irqreturn_t nv_nic_irq_tx(int foo, void *data) |
d33a73c8 AA |
3380 | { |
3381 | struct net_device *dev = (struct net_device *) data; | |
3382 | struct fe_priv *np = netdev_priv(dev); | |
3383 | u8 __iomem *base = get_hwbase(dev); | |
3384 | u32 events; | |
3385 | int i; | |
0a07bc64 | 3386 | unsigned long flags; |
d33a73c8 | 3387 | |
78aea4fc | 3388 | for (i = 0;; i++) { |
d33a73c8 AA |
3389 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; |
3390 | writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3391 | if (!(events & np->irqmask)) |
3392 | break; | |
3393 | ||
0a07bc64 | 3394 | spin_lock_irqsave(&np->lock, flags); |
4e16ed1b | 3395 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); |
0a07bc64 | 3396 | spin_unlock_irqrestore(&np->lock, flags); |
f3b197ac | 3397 | |
f0734ab6 | 3398 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3399 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3400 | /* disable interrupts on the nic */ |
3401 | writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); | |
3402 | pci_push(base); | |
3403 | ||
3404 | if (!np->in_shutdown) { | |
3405 | np->nic_poll_irq |= NVREG_IRQ_TX_ALL; | |
3406 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3407 | } | |
0a07bc64 | 3408 | spin_unlock_irqrestore(&np->lock, flags); |
c20ec761 JP |
3409 | netdev_dbg(dev, "%s: too many iterations (%d)\n", |
3410 | __func__, i); | |
d33a73c8 AA |
3411 | break; |
3412 | } | |
3413 | ||
3414 | } | |
d33a73c8 AA |
3415 | |
3416 | return IRQ_RETVAL(i); | |
3417 | } | |
3418 | ||
bea3348e | 3419 | static int nv_napi_poll(struct napi_struct *napi, int budget) |
e27cdba5 | 3420 | { |
bea3348e SH |
3421 | struct fe_priv *np = container_of(napi, struct fe_priv, napi); |
3422 | struct net_device *dev = np->dev; | |
e27cdba5 | 3423 | u8 __iomem *base = get_hwbase(dev); |
d15e9c4d | 3424 | unsigned long flags; |
4145ade2 | 3425 | int retcode; |
78aea4fc | 3426 | int rx_count, tx_work = 0, rx_work = 0; |
e27cdba5 | 3427 | |
81a2e36d | 3428 | do { |
3429 | if (!nv_optimized(np)) { | |
3430 | spin_lock_irqsave(&np->lock, flags); | |
3431 | tx_work += nv_tx_done(dev, np->tx_ring_size); | |
3432 | spin_unlock_irqrestore(&np->lock, flags); | |
f27e6f39 | 3433 | |
d951f725 | 3434 | rx_count = nv_rx_process(dev, budget - rx_work); |
81a2e36d | 3435 | retcode = nv_alloc_rx(dev); |
3436 | } else { | |
3437 | spin_lock_irqsave(&np->lock, flags); | |
3438 | tx_work += nv_tx_done_optimized(dev, np->tx_ring_size); | |
3439 | spin_unlock_irqrestore(&np->lock, flags); | |
f27e6f39 | 3440 | |
d951f725 TH |
3441 | rx_count = nv_rx_process_optimized(dev, |
3442 | budget - rx_work); | |
81a2e36d | 3443 | retcode = nv_alloc_rx_optimized(dev); |
3444 | } | |
3445 | } while (retcode == 0 && | |
3446 | rx_count > 0 && (rx_work += rx_count) < budget); | |
e27cdba5 | 3447 | |
e0379a14 | 3448 | if (retcode) { |
d15e9c4d | 3449 | spin_lock_irqsave(&np->lock, flags); |
e27cdba5 SH |
3450 | if (!np->in_shutdown) |
3451 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
d15e9c4d | 3452 | spin_unlock_irqrestore(&np->lock, flags); |
e27cdba5 SH |
3453 | } |
3454 | ||
4145ade2 AA |
3455 | nv_change_interrupt_mode(dev, tx_work + rx_work); |
3456 | ||
f27e6f39 AA |
3457 | if (unlikely(np->events & NVREG_IRQ_LINK)) { |
3458 | spin_lock_irqsave(&np->lock, flags); | |
3459 | nv_link_irq(dev); | |
3460 | spin_unlock_irqrestore(&np->lock, flags); | |
3461 | } | |
3462 | if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { | |
3463 | spin_lock_irqsave(&np->lock, flags); | |
3464 | nv_linkchange(dev); | |
3465 | spin_unlock_irqrestore(&np->lock, flags); | |
3466 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
3467 | } | |
3468 | if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) { | |
3469 | spin_lock_irqsave(&np->lock, flags); | |
3470 | if (!np->in_shutdown) { | |
3471 | np->nic_poll_irq = np->irqmask; | |
3472 | np->recover_error = 1; | |
3473 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3474 | } | |
3475 | spin_unlock_irqrestore(&np->lock, flags); | |
6c2da9c2 | 3476 | napi_complete(napi); |
4145ade2 | 3477 | return rx_work; |
f27e6f39 AA |
3478 | } |
3479 | ||
4145ade2 | 3480 | if (rx_work < budget) { |
f27e6f39 AA |
3481 | /* re-enable interrupts |
3482 | (msix not enabled in napi) */ | |
6c2da9c2 | 3483 | napi_complete(napi); |
bea3348e | 3484 | |
f27e6f39 | 3485 | writel(np->irqmask, base + NvRegIrqMask); |
e27cdba5 | 3486 | } |
4145ade2 | 3487 | return rx_work; |
e27cdba5 | 3488 | } |
e27cdba5 | 3489 | |
7d12e780 | 3490 | static irqreturn_t nv_nic_irq_rx(int foo, void *data) |
d33a73c8 AA |
3491 | { |
3492 | struct net_device *dev = (struct net_device *) data; | |
3493 | struct fe_priv *np = netdev_priv(dev); | |
3494 | u8 __iomem *base = get_hwbase(dev); | |
3495 | u32 events; | |
3496 | int i; | |
0a07bc64 | 3497 | unsigned long flags; |
d33a73c8 | 3498 | |
78aea4fc | 3499 | for (i = 0;; i++) { |
d33a73c8 AA |
3500 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; |
3501 | writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3502 | if (!(events & np->irqmask)) |
3503 | break; | |
f3b197ac | 3504 | |
bea3348e | 3505 | if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) { |
f0734ab6 AA |
3506 | if (unlikely(nv_alloc_rx_optimized(dev))) { |
3507 | spin_lock_irqsave(&np->lock, flags); | |
3508 | if (!np->in_shutdown) | |
3509 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3510 | spin_unlock_irqrestore(&np->lock, flags); | |
3511 | } | |
d33a73c8 | 3512 | } |
f3b197ac | 3513 | |
f0734ab6 | 3514 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3515 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3516 | /* disable interrupts on the nic */ |
3517 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3518 | pci_push(base); | |
3519 | ||
3520 | if (!np->in_shutdown) { | |
3521 | np->nic_poll_irq |= NVREG_IRQ_RX_ALL; | |
3522 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3523 | } | |
0a07bc64 | 3524 | spin_unlock_irqrestore(&np->lock, flags); |
c20ec761 JP |
3525 | netdev_dbg(dev, "%s: too many iterations (%d)\n", |
3526 | __func__, i); | |
d33a73c8 AA |
3527 | break; |
3528 | } | |
d33a73c8 | 3529 | } |
d33a73c8 AA |
3530 | |
3531 | return IRQ_RETVAL(i); | |
3532 | } | |
3533 | ||
7d12e780 | 3534 | static irqreturn_t nv_nic_irq_other(int foo, void *data) |
d33a73c8 AA |
3535 | { |
3536 | struct net_device *dev = (struct net_device *) data; | |
3537 | struct fe_priv *np = netdev_priv(dev); | |
3538 | u8 __iomem *base = get_hwbase(dev); | |
3539 | u32 events; | |
3540 | int i; | |
0a07bc64 | 3541 | unsigned long flags; |
d33a73c8 | 3542 | |
78aea4fc | 3543 | for (i = 0;; i++) { |
d33a73c8 AA |
3544 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; |
3545 | writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3546 | if (!(events & np->irqmask)) |
3547 | break; | |
f3b197ac | 3548 | |
4e16ed1b AA |
3549 | /* check tx in case we reached max loop limit in tx isr */ |
3550 | spin_lock_irqsave(&np->lock, flags); | |
3551 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); | |
3552 | spin_unlock_irqrestore(&np->lock, flags); | |
3553 | ||
d33a73c8 | 3554 | if (events & NVREG_IRQ_LINK) { |
0a07bc64 | 3555 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3556 | nv_link_irq(dev); |
0a07bc64 | 3557 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3558 | } |
3559 | if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { | |
0a07bc64 | 3560 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3561 | nv_linkchange(dev); |
0a07bc64 | 3562 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3563 | np->link_timeout = jiffies + LINK_TIMEOUT; |
3564 | } | |
c5cf9101 AA |
3565 | if (events & NVREG_IRQ_RECOVER_ERROR) { |
3566 | spin_lock_irq(&np->lock); | |
3567 | /* disable interrupts on the nic */ | |
3568 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3569 | pci_push(base); | |
3570 | ||
3571 | if (!np->in_shutdown) { | |
3572 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3573 | np->recover_error = 1; | |
3574 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3575 | } | |
3576 | spin_unlock_irq(&np->lock); | |
3577 | break; | |
3578 | } | |
f0734ab6 | 3579 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3580 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3581 | /* disable interrupts on the nic */ |
3582 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3583 | pci_push(base); | |
3584 | ||
3585 | if (!np->in_shutdown) { | |
3586 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3587 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3588 | } | |
0a07bc64 | 3589 | spin_unlock_irqrestore(&np->lock, flags); |
c20ec761 JP |
3590 | netdev_dbg(dev, "%s: too many iterations (%d)\n", |
3591 | __func__, i); | |
d33a73c8 AA |
3592 | break; |
3593 | } | |
3594 | ||
3595 | } | |
d33a73c8 AA |
3596 | |
3597 | return IRQ_RETVAL(i); | |
3598 | } | |
3599 | ||
7d12e780 | 3600 | static irqreturn_t nv_nic_irq_test(int foo, void *data) |
9589c77a AA |
3601 | { |
3602 | struct net_device *dev = (struct net_device *) data; | |
3603 | struct fe_priv *np = netdev_priv(dev); | |
3604 | u8 __iomem *base = get_hwbase(dev); | |
3605 | u32 events; | |
3606 | ||
9589c77a AA |
3607 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3608 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
3609 | writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus); | |
3610 | } else { | |
3611 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
3612 | writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); | |
3613 | } | |
3614 | pci_push(base); | |
9589c77a AA |
3615 | if (!(events & NVREG_IRQ_TIMER)) |
3616 | return IRQ_RETVAL(0); | |
3617 | ||
4db0ee17 AA |
3618 | nv_msi_workaround(np); |
3619 | ||
9589c77a AA |
3620 | spin_lock(&np->lock); |
3621 | np->intr_test = 1; | |
3622 | spin_unlock(&np->lock); | |
3623 | ||
9589c77a AA |
3624 | return IRQ_RETVAL(1); |
3625 | } | |
3626 | ||
7a1854b7 AA |
3627 | static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
3628 | { | |
3629 | u8 __iomem *base = get_hwbase(dev); | |
3630 | int i; | |
3631 | u32 msixmap = 0; | |
3632 | ||
3633 | /* Each interrupt bit can be mapped to a MSIX vector (4 bits). | |
3634 | * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents | |
3635 | * the remaining 8 interrupts. | |
3636 | */ | |
3637 | for (i = 0; i < 8; i++) { | |
78aea4fc | 3638 | if ((irqmask >> i) & 0x1) |
7a1854b7 | 3639 | msixmap |= vector << (i << 2); |
7a1854b7 AA |
3640 | } |
3641 | writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); | |
3642 | ||
3643 | msixmap = 0; | |
3644 | for (i = 0; i < 8; i++) { | |
78aea4fc | 3645 | if ((irqmask >> (i + 8)) & 0x1) |
7a1854b7 | 3646 | msixmap |= vector << (i << 2); |
7a1854b7 AA |
3647 | } |
3648 | writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); | |
3649 | } | |
3650 | ||
9589c77a | 3651 | static int nv_request_irq(struct net_device *dev, int intr_test) |
7a1854b7 AA |
3652 | { |
3653 | struct fe_priv *np = get_nvpriv(dev); | |
3654 | u8 __iomem *base = get_hwbase(dev); | |
3655 | int ret = 1; | |
3656 | int i; | |
86b22b0d AA |
3657 | irqreturn_t (*handler)(int foo, void *data); |
3658 | ||
3659 | if (intr_test) { | |
3660 | handler = nv_nic_irq_test; | |
3661 | } else { | |
36b30ea9 | 3662 | if (nv_optimized(np)) |
86b22b0d AA |
3663 | handler = nv_nic_irq_optimized; |
3664 | else | |
3665 | handler = nv_nic_irq; | |
3666 | } | |
7a1854b7 AA |
3667 | |
3668 | if (np->msi_flags & NV_MSI_X_CAPABLE) { | |
78aea4fc | 3669 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) |
7a1854b7 | 3670 | np->msi_x_entry[i].entry = i; |
34cf97eb SJ |
3671 | ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK)); |
3672 | if (ret == 0) { | |
7a1854b7 | 3673 | np->msi_flags |= NV_MSI_X_ENABLED; |
9589c77a | 3674 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { |
7a1854b7 | 3675 | /* Request irq for rx handling */ |
ddb213f0 YL |
3676 | sprintf(np->name_rx, "%s-rx", dev->name); |
3677 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, | |
a0607fd3 | 3678 | nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) { |
1d397f36 JP |
3679 | netdev_info(dev, |
3680 | "request_irq failed for rx %d\n", | |
3681 | ret); | |
7a1854b7 AA |
3682 | pci_disable_msix(np->pci_dev); |
3683 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3684 | goto out_err; | |
3685 | } | |
3686 | /* Request irq for tx handling */ | |
ddb213f0 YL |
3687 | sprintf(np->name_tx, "%s-tx", dev->name); |
3688 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, | |
a0607fd3 | 3689 | nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) { |
1d397f36 JP |
3690 | netdev_info(dev, |
3691 | "request_irq failed for tx %d\n", | |
3692 | ret); | |
7a1854b7 AA |
3693 | pci_disable_msix(np->pci_dev); |
3694 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3695 | goto out_free_rx; | |
3696 | } | |
3697 | /* Request irq for link and timer handling */ | |
ddb213f0 YL |
3698 | sprintf(np->name_other, "%s-other", dev->name); |
3699 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, | |
a0607fd3 | 3700 | nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) { |
1d397f36 JP |
3701 | netdev_info(dev, |
3702 | "request_irq failed for link %d\n", | |
3703 | ret); | |
7a1854b7 AA |
3704 | pci_disable_msix(np->pci_dev); |
3705 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3706 | goto out_free_tx; | |
3707 | } | |
3708 | /* map interrupts to their respective vector */ | |
3709 | writel(0, base + NvRegMSIXMap0); | |
3710 | writel(0, base + NvRegMSIXMap1); | |
3711 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); | |
3712 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); | |
3713 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); | |
3714 | } else { | |
3715 | /* Request irq for all interrupts */ | |
86b22b0d | 3716 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) { |
1d397f36 JP |
3717 | netdev_info(dev, |
3718 | "request_irq failed %d\n", | |
3719 | ret); | |
7a1854b7 AA |
3720 | pci_disable_msix(np->pci_dev); |
3721 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3722 | goto out_err; | |
3723 | } | |
3724 | ||
3725 | /* map interrupts to vector 0 */ | |
3726 | writel(0, base + NvRegMSIXMap0); | |
3727 | writel(0, base + NvRegMSIXMap1); | |
3728 | } | |
3729 | } | |
3730 | } | |
3731 | if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { | |
34cf97eb SJ |
3732 | ret = pci_enable_msi(np->pci_dev); |
3733 | if (ret == 0) { | |
7a1854b7 | 3734 | np->msi_flags |= NV_MSI_ENABLED; |
a7475906 | 3735 | dev->irq = np->pci_dev->irq; |
86b22b0d | 3736 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { |
1d397f36 JP |
3737 | netdev_info(dev, "request_irq failed %d\n", |
3738 | ret); | |
7a1854b7 AA |
3739 | pci_disable_msi(np->pci_dev); |
3740 | np->msi_flags &= ~NV_MSI_ENABLED; | |
a7475906 | 3741 | dev->irq = np->pci_dev->irq; |
7a1854b7 AA |
3742 | goto out_err; |
3743 | } | |
3744 | ||
3745 | /* map interrupts to vector 0 */ | |
3746 | writel(0, base + NvRegMSIMap0); | |
3747 | writel(0, base + NvRegMSIMap1); | |
3748 | /* enable msi vector 0 */ | |
3749 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
3750 | } | |
3751 | } | |
3752 | if (ret != 0) { | |
86b22b0d | 3753 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) |
7a1854b7 | 3754 | goto out_err; |
9589c77a | 3755 | |
7a1854b7 AA |
3756 | } |
3757 | ||
3758 | return 0; | |
3759 | out_free_tx: | |
3760 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); | |
3761 | out_free_rx: | |
3762 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); | |
3763 | out_err: | |
3764 | return 1; | |
3765 | } | |
3766 | ||
3767 | static void nv_free_irq(struct net_device *dev) | |
3768 | { | |
3769 | struct fe_priv *np = get_nvpriv(dev); | |
3770 | int i; | |
3771 | ||
3772 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
78aea4fc | 3773 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) |
7a1854b7 | 3774 | free_irq(np->msi_x_entry[i].vector, dev); |
7a1854b7 AA |
3775 | pci_disable_msix(np->pci_dev); |
3776 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3777 | } else { | |
3778 | free_irq(np->pci_dev->irq, dev); | |
3779 | if (np->msi_flags & NV_MSI_ENABLED) { | |
3780 | pci_disable_msi(np->pci_dev); | |
3781 | np->msi_flags &= ~NV_MSI_ENABLED; | |
3782 | } | |
3783 | } | |
3784 | } | |
3785 | ||
1da177e4 LT |
3786 | static void nv_do_nic_poll(unsigned long data) |
3787 | { | |
3788 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 3789 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3790 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 3791 | u32 mask = 0; |
1da177e4 | 3792 | |
1da177e4 | 3793 | /* |
d33a73c8 | 3794 | * First disable irq(s) and then |
1da177e4 LT |
3795 | * reenable interrupts on the nic, we have to do this before calling |
3796 | * nv_nic_irq because that may decide to do otherwise | |
3797 | */ | |
d33a73c8 | 3798 | |
84b3932b AA |
3799 | if (!using_multi_irqs(dev)) { |
3800 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
8688cfce | 3801 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
84b3932b | 3802 | else |
a7475906 | 3803 | disable_irq_lockdep(np->pci_dev->irq); |
d33a73c8 AA |
3804 | mask = np->irqmask; |
3805 | } else { | |
3806 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
8688cfce | 3807 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
d33a73c8 AA |
3808 | mask |= NVREG_IRQ_RX_ALL; |
3809 | } | |
3810 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
8688cfce | 3811 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
d33a73c8 AA |
3812 | mask |= NVREG_IRQ_TX_ALL; |
3813 | } | |
3814 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
8688cfce | 3815 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
d33a73c8 AA |
3816 | mask |= NVREG_IRQ_OTHER; |
3817 | } | |
3818 | } | |
a7475906 MS |
3819 | /* disable_irq() contains synchronize_irq, thus no irq handler can run now */ |
3820 | ||
c5cf9101 AA |
3821 | if (np->recover_error) { |
3822 | np->recover_error = 0; | |
1d397f36 | 3823 | netdev_info(dev, "MAC in recoverable error state\n"); |
c5cf9101 AA |
3824 | if (netif_running(dev)) { |
3825 | netif_tx_lock_bh(dev); | |
e308a5d8 | 3826 | netif_addr_lock(dev); |
c5cf9101 AA |
3827 | spin_lock(&np->lock); |
3828 | /* stop engines */ | |
36b30ea9 | 3829 | nv_stop_rxtx(dev); |
daa91a9d AA |
3830 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
3831 | nv_mac_reset(dev); | |
c5cf9101 AA |
3832 | nv_txrx_reset(dev); |
3833 | /* drain rx queue */ | |
36b30ea9 | 3834 | nv_drain_rxtx(dev); |
c5cf9101 AA |
3835 | /* reinit driver view of the rx queue */ |
3836 | set_bufsize(dev); | |
3837 | if (nv_init_ring(dev)) { | |
3838 | if (!np->in_shutdown) | |
3839 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3840 | } | |
3841 | /* reinit nic view of the rx queue */ | |
3842 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
3843 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 3844 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
c5cf9101 AA |
3845 | base + NvRegRingSizes); |
3846 | pci_push(base); | |
3847 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
3848 | pci_push(base); | |
daa91a9d AA |
3849 | /* clear interrupts */ |
3850 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
3851 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
3852 | else | |
3853 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
c5cf9101 AA |
3854 | |
3855 | /* restart rx engine */ | |
36b30ea9 | 3856 | nv_start_rxtx(dev); |
c5cf9101 | 3857 | spin_unlock(&np->lock); |
e308a5d8 | 3858 | netif_addr_unlock(dev); |
c5cf9101 AA |
3859 | netif_tx_unlock_bh(dev); |
3860 | } | |
3861 | } | |
3862 | ||
d33a73c8 | 3863 | writel(mask, base + NvRegIrqMask); |
1da177e4 | 3864 | pci_push(base); |
d33a73c8 | 3865 | |
84b3932b | 3866 | if (!using_multi_irqs(dev)) { |
79d30a58 | 3867 | np->nic_poll_irq = 0; |
36b30ea9 | 3868 | if (nv_optimized(np)) |
fcc5f266 AA |
3869 | nv_nic_irq_optimized(0, dev); |
3870 | else | |
3871 | nv_nic_irq(0, dev); | |
84b3932b | 3872 | if (np->msi_flags & NV_MSI_X_ENABLED) |
8688cfce | 3873 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
84b3932b | 3874 | else |
a7475906 | 3875 | enable_irq_lockdep(np->pci_dev->irq); |
d33a73c8 AA |
3876 | } else { |
3877 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
79d30a58 | 3878 | np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL; |
7d12e780 | 3879 | nv_nic_irq_rx(0, dev); |
8688cfce | 3880 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
d33a73c8 AA |
3881 | } |
3882 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
79d30a58 | 3883 | np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL; |
7d12e780 | 3884 | nv_nic_irq_tx(0, dev); |
8688cfce | 3885 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
d33a73c8 AA |
3886 | } |
3887 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
79d30a58 | 3888 | np->nic_poll_irq &= ~NVREG_IRQ_OTHER; |
7d12e780 | 3889 | nv_nic_irq_other(0, dev); |
8688cfce | 3890 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
d33a73c8 AA |
3891 | } |
3892 | } | |
79d30a58 | 3893 | |
1da177e4 LT |
3894 | } |
3895 | ||
2918c35d MS |
3896 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3897 | static void nv_poll_controller(struct net_device *dev) | |
3898 | { | |
3899 | nv_do_nic_poll((unsigned long) dev); | |
3900 | } | |
3901 | #endif | |
3902 | ||
52da3578 AA |
3903 | static void nv_do_stats_poll(unsigned long data) |
3904 | { | |
3905 | struct net_device *dev = (struct net_device *) data; | |
3906 | struct fe_priv *np = netdev_priv(dev); | |
52da3578 | 3907 | |
57fff698 | 3908 | nv_get_hw_stats(dev); |
52da3578 AA |
3909 | |
3910 | if (!np->in_shutdown) | |
bfebbb88 DD |
3911 | mod_timer(&np->stats_poll, |
3912 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 AA |
3913 | } |
3914 | ||
1da177e4 LT |
3915 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
3916 | { | |
ac9c1897 | 3917 | struct fe_priv *np = netdev_priv(dev); |
3f88ce49 | 3918 | strcpy(info->driver, DRV_NAME); |
1da177e4 LT |
3919 | strcpy(info->version, FORCEDETH_VERSION); |
3920 | strcpy(info->bus_info, pci_name(np->pci_dev)); | |
3921 | } | |
3922 | ||
3923 | static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
3924 | { | |
ac9c1897 | 3925 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
3926 | wolinfo->supported = WAKE_MAGIC; |
3927 | ||
3928 | spin_lock_irq(&np->lock); | |
3929 | if (np->wolenabled) | |
3930 | wolinfo->wolopts = WAKE_MAGIC; | |
3931 | spin_unlock_irq(&np->lock); | |
3932 | } | |
3933 | ||
3934 | static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
3935 | { | |
ac9c1897 | 3936 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3937 | u8 __iomem *base = get_hwbase(dev); |
c42d9df9 | 3938 | u32 flags = 0; |
1da177e4 | 3939 | |
1da177e4 | 3940 | if (wolinfo->wolopts == 0) { |
1da177e4 | 3941 | np->wolenabled = 0; |
c42d9df9 | 3942 | } else if (wolinfo->wolopts & WAKE_MAGIC) { |
1da177e4 | 3943 | np->wolenabled = 1; |
c42d9df9 AA |
3944 | flags = NVREG_WAKEUPFLAGS_ENABLE; |
3945 | } | |
3946 | if (netif_running(dev)) { | |
3947 | spin_lock_irq(&np->lock); | |
3948 | writel(flags, base + NvRegWakeUpFlags); | |
3949 | spin_unlock_irq(&np->lock); | |
1da177e4 | 3950 | } |
dba5a68a | 3951 | device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled); |
1da177e4 LT |
3952 | return 0; |
3953 | } | |
3954 | ||
3955 | static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
3956 | { | |
3957 | struct fe_priv *np = netdev_priv(dev); | |
3958 | int adv; | |
3959 | ||
3960 | spin_lock_irq(&np->lock); | |
3961 | ecmd->port = PORT_MII; | |
3962 | if (!netif_running(dev)) { | |
3963 | /* We do not track link speed / duplex setting if the | |
3964 | * interface is disabled. Force a link check */ | |
f9430a01 AA |
3965 | if (nv_update_linkspeed(dev)) { |
3966 | if (!netif_carrier_ok(dev)) | |
3967 | netif_carrier_on(dev); | |
3968 | } else { | |
3969 | if (netif_carrier_ok(dev)) | |
3970 | netif_carrier_off(dev); | |
3971 | } | |
1da177e4 | 3972 | } |
f9430a01 AA |
3973 | |
3974 | if (netif_carrier_ok(dev)) { | |
78aea4fc | 3975 | switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) { |
1da177e4 LT |
3976 | case NVREG_LINKSPEED_10: |
3977 | ecmd->speed = SPEED_10; | |
3978 | break; | |
3979 | case NVREG_LINKSPEED_100: | |
3980 | ecmd->speed = SPEED_100; | |
3981 | break; | |
3982 | case NVREG_LINKSPEED_1000: | |
3983 | ecmd->speed = SPEED_1000; | |
3984 | break; | |
f9430a01 AA |
3985 | } |
3986 | ecmd->duplex = DUPLEX_HALF; | |
3987 | if (np->duplex) | |
3988 | ecmd->duplex = DUPLEX_FULL; | |
3989 | } else { | |
3990 | ecmd->speed = -1; | |
3991 | ecmd->duplex = -1; | |
1da177e4 | 3992 | } |
1da177e4 LT |
3993 | |
3994 | ecmd->autoneg = np->autoneg; | |
3995 | ||
3996 | ecmd->advertising = ADVERTISED_MII; | |
3997 | if (np->autoneg) { | |
3998 | ecmd->advertising |= ADVERTISED_Autoneg; | |
3999 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
f9430a01 AA |
4000 | if (adv & ADVERTISE_10HALF) |
4001 | ecmd->advertising |= ADVERTISED_10baseT_Half; | |
4002 | if (adv & ADVERTISE_10FULL) | |
4003 | ecmd->advertising |= ADVERTISED_10baseT_Full; | |
4004 | if (adv & ADVERTISE_100HALF) | |
4005 | ecmd->advertising |= ADVERTISED_100baseT_Half; | |
4006 | if (adv & ADVERTISE_100FULL) | |
4007 | ecmd->advertising |= ADVERTISED_100baseT_Full; | |
4008 | if (np->gigabit == PHY_GIGABIT) { | |
4009 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); | |
4010 | if (adv & ADVERTISE_1000FULL) | |
4011 | ecmd->advertising |= ADVERTISED_1000baseT_Full; | |
4012 | } | |
1da177e4 | 4013 | } |
1da177e4 LT |
4014 | ecmd->supported = (SUPPORTED_Autoneg | |
4015 | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | | |
4016 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | | |
4017 | SUPPORTED_MII); | |
4018 | if (np->gigabit == PHY_GIGABIT) | |
4019 | ecmd->supported |= SUPPORTED_1000baseT_Full; | |
4020 | ||
4021 | ecmd->phy_address = np->phyaddr; | |
4022 | ecmd->transceiver = XCVR_EXTERNAL; | |
4023 | ||
4024 | /* ignore maxtxpkt, maxrxpkt for now */ | |
4025 | spin_unlock_irq(&np->lock); | |
4026 | return 0; | |
4027 | } | |
4028 | ||
4029 | static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
4030 | { | |
4031 | struct fe_priv *np = netdev_priv(dev); | |
25db0338 | 4032 | u32 speed = ethtool_cmd_speed(ecmd); |
1da177e4 LT |
4033 | |
4034 | if (ecmd->port != PORT_MII) | |
4035 | return -EINVAL; | |
4036 | if (ecmd->transceiver != XCVR_EXTERNAL) | |
4037 | return -EINVAL; | |
4038 | if (ecmd->phy_address != np->phyaddr) { | |
4039 | /* TODO: support switching between multiple phys. Should be | |
4040 | * trivial, but not enabled due to lack of test hardware. */ | |
4041 | return -EINVAL; | |
4042 | } | |
4043 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
4044 | u32 mask; | |
4045 | ||
4046 | mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4047 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; | |
4048 | if (np->gigabit == PHY_GIGABIT) | |
4049 | mask |= ADVERTISED_1000baseT_Full; | |
4050 | ||
4051 | if ((ecmd->advertising & mask) == 0) | |
4052 | return -EINVAL; | |
4053 | ||
4054 | } else if (ecmd->autoneg == AUTONEG_DISABLE) { | |
4055 | /* Note: autonegotiation disable, speed 1000 intentionally | |
25985edc | 4056 | * forbidden - no one should need that. */ |
1da177e4 | 4057 | |
25db0338 | 4058 | if (speed != SPEED_10 && speed != SPEED_100) |
1da177e4 LT |
4059 | return -EINVAL; |
4060 | if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) | |
4061 | return -EINVAL; | |
4062 | } else { | |
4063 | return -EINVAL; | |
4064 | } | |
4065 | ||
f9430a01 AA |
4066 | netif_carrier_off(dev); |
4067 | if (netif_running(dev)) { | |
97bff095 TD |
4068 | unsigned long flags; |
4069 | ||
f9430a01 | 4070 | nv_disable_irq(dev); |
58dfd9c1 | 4071 | netif_tx_lock_bh(dev); |
e308a5d8 | 4072 | netif_addr_lock(dev); |
97bff095 TD |
4073 | /* with plain spinlock lockdep complains */ |
4074 | spin_lock_irqsave(&np->lock, flags); | |
f9430a01 | 4075 | /* stop engines */ |
97bff095 TD |
4076 | /* FIXME: |
4077 | * this can take some time, and interrupts are disabled | |
4078 | * due to spin_lock_irqsave, but let's hope no daemon | |
4079 | * is going to change the settings very often... | |
4080 | * Worst case: | |
4081 | * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX | |
4082 | * + some minor delays, which is up to a second approximately | |
4083 | */ | |
36b30ea9 | 4084 | nv_stop_rxtx(dev); |
97bff095 | 4085 | spin_unlock_irqrestore(&np->lock, flags); |
e308a5d8 | 4086 | netif_addr_unlock(dev); |
58dfd9c1 | 4087 | netif_tx_unlock_bh(dev); |
f9430a01 AA |
4088 | } |
4089 | ||
1da177e4 LT |
4090 | if (ecmd->autoneg == AUTONEG_ENABLE) { |
4091 | int adv, bmcr; | |
4092 | ||
4093 | np->autoneg = 1; | |
4094 | ||
4095 | /* advertise only what has been requested */ | |
4096 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4097 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
1da177e4 LT |
4098 | if (ecmd->advertising & ADVERTISED_10baseT_Half) |
4099 | adv |= ADVERTISE_10HALF; | |
4100 | if (ecmd->advertising & ADVERTISED_10baseT_Full) | |
b6d0773f | 4101 | adv |= ADVERTISE_10FULL; |
1da177e4 LT |
4102 | if (ecmd->advertising & ADVERTISED_100baseT_Half) |
4103 | adv |= ADVERTISE_100HALF; | |
4104 | if (ecmd->advertising & ADVERTISED_100baseT_Full) | |
b6d0773f | 4105 | adv |= ADVERTISE_100FULL; |
25985edc | 4106 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */ |
b6d0773f AA |
4107 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
4108 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4109 | adv |= ADVERTISE_PAUSE_ASYM; | |
1da177e4 LT |
4110 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4111 | ||
4112 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4113 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 LT |
4114 | adv &= ~ADVERTISE_1000FULL; |
4115 | if (ecmd->advertising & ADVERTISED_1000baseT_Full) | |
4116 | adv |= ADVERTISE_1000FULL; | |
eb91f61b | 4117 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4118 | } |
4119 | ||
f9430a01 | 4120 | if (netif_running(dev)) |
1d397f36 | 4121 | netdev_info(dev, "link down\n"); |
1da177e4 | 4122 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4123 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4124 | bmcr |= BMCR_ANENABLE; | |
4125 | /* reset the phy in order for settings to stick, | |
4126 | * and cause autoneg to start */ | |
4127 | if (phy_reset(dev, bmcr)) { | |
1d397f36 | 4128 | netdev_info(dev, "phy reset failed\n"); |
edf7e5ec AA |
4129 | return -EINVAL; |
4130 | } | |
4131 | } else { | |
4132 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4133 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4134 | } | |
1da177e4 LT |
4135 | } else { |
4136 | int adv, bmcr; | |
4137 | ||
4138 | np->autoneg = 0; | |
4139 | ||
4140 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4141 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
25db0338 | 4142 | if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF) |
1da177e4 | 4143 | adv |= ADVERTISE_10HALF; |
25db0338 | 4144 | if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL) |
b6d0773f | 4145 | adv |= ADVERTISE_10FULL; |
25db0338 | 4146 | if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF) |
1da177e4 | 4147 | adv |= ADVERTISE_100HALF; |
25db0338 | 4148 | if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL) |
b6d0773f AA |
4149 | adv |= ADVERTISE_100FULL; |
4150 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
25985edc | 4151 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */ |
b6d0773f AA |
4152 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
4153 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4154 | } | |
4155 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) { | |
4156 | adv |= ADVERTISE_PAUSE_ASYM; | |
4157 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4158 | } | |
1da177e4 LT |
4159 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4160 | np->fixed_mode = adv; | |
4161 | ||
4162 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4163 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 | 4164 | adv &= ~ADVERTISE_1000FULL; |
eb91f61b | 4165 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4166 | } |
4167 | ||
4168 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
f9430a01 AA |
4169 | bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX); |
4170 | if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL)) | |
1da177e4 | 4171 | bmcr |= BMCR_FULLDPLX; |
f9430a01 | 4172 | if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
1da177e4 | 4173 | bmcr |= BMCR_SPEED100; |
f9430a01 | 4174 | if (np->phy_oui == PHY_OUI_MARVELL) { |
edf7e5ec AA |
4175 | /* reset the phy in order for forced mode settings to stick */ |
4176 | if (phy_reset(dev, bmcr)) { | |
1d397f36 | 4177 | netdev_info(dev, "phy reset failed\n"); |
f9430a01 AA |
4178 | return -EINVAL; |
4179 | } | |
edf7e5ec AA |
4180 | } else { |
4181 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4182 | if (netif_running(dev)) { | |
4183 | /* Wait a bit and then reconfigure the nic. */ | |
4184 | udelay(10); | |
4185 | nv_linkchange(dev); | |
4186 | } | |
1da177e4 LT |
4187 | } |
4188 | } | |
f9430a01 AA |
4189 | |
4190 | if (netif_running(dev)) { | |
36b30ea9 | 4191 | nv_start_rxtx(dev); |
f9430a01 AA |
4192 | nv_enable_irq(dev); |
4193 | } | |
1da177e4 LT |
4194 | |
4195 | return 0; | |
4196 | } | |
4197 | ||
dc8216c1 | 4198 | #define FORCEDETH_REGS_VER 1 |
dc8216c1 MS |
4199 | |
4200 | static int nv_get_regs_len(struct net_device *dev) | |
4201 | { | |
86a0f043 AA |
4202 | struct fe_priv *np = netdev_priv(dev); |
4203 | return np->register_size; | |
dc8216c1 MS |
4204 | } |
4205 | ||
4206 | static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) | |
4207 | { | |
ac9c1897 | 4208 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4209 | u8 __iomem *base = get_hwbase(dev); |
4210 | u32 *rbuf = buf; | |
4211 | int i; | |
4212 | ||
4213 | regs->version = FORCEDETH_REGS_VER; | |
4214 | spin_lock_irq(&np->lock); | |
78aea4fc | 4215 | for (i = 0; i <= np->register_size/sizeof(u32); i++) |
dc8216c1 MS |
4216 | rbuf[i] = readl(base + i*sizeof(u32)); |
4217 | spin_unlock_irq(&np->lock); | |
4218 | } | |
4219 | ||
4220 | static int nv_nway_reset(struct net_device *dev) | |
4221 | { | |
ac9c1897 | 4222 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4223 | int ret; |
4224 | ||
dc8216c1 MS |
4225 | if (np->autoneg) { |
4226 | int bmcr; | |
4227 | ||
f9430a01 AA |
4228 | netif_carrier_off(dev); |
4229 | if (netif_running(dev)) { | |
4230 | nv_disable_irq(dev); | |
58dfd9c1 | 4231 | netif_tx_lock_bh(dev); |
e308a5d8 | 4232 | netif_addr_lock(dev); |
f9430a01 AA |
4233 | spin_lock(&np->lock); |
4234 | /* stop engines */ | |
36b30ea9 | 4235 | nv_stop_rxtx(dev); |
f9430a01 | 4236 | spin_unlock(&np->lock); |
e308a5d8 | 4237 | netif_addr_unlock(dev); |
58dfd9c1 | 4238 | netif_tx_unlock_bh(dev); |
1d397f36 | 4239 | netdev_info(dev, "link down\n"); |
f9430a01 AA |
4240 | } |
4241 | ||
dc8216c1 | 4242 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4243 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4244 | bmcr |= BMCR_ANENABLE; | |
4245 | /* reset the phy in order for settings to stick*/ | |
4246 | if (phy_reset(dev, bmcr)) { | |
1d397f36 | 4247 | netdev_info(dev, "phy reset failed\n"); |
edf7e5ec AA |
4248 | return -EINVAL; |
4249 | } | |
4250 | } else { | |
4251 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4252 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4253 | } | |
dc8216c1 | 4254 | |
f9430a01 | 4255 | if (netif_running(dev)) { |
36b30ea9 | 4256 | nv_start_rxtx(dev); |
f9430a01 AA |
4257 | nv_enable_irq(dev); |
4258 | } | |
dc8216c1 MS |
4259 | ret = 0; |
4260 | } else { | |
4261 | ret = -EINVAL; | |
4262 | } | |
dc8216c1 MS |
4263 | |
4264 | return ret; | |
4265 | } | |
4266 | ||
eafa59f6 AA |
4267 | static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
4268 | { | |
4269 | struct fe_priv *np = netdev_priv(dev); | |
4270 | ||
4271 | ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
4272 | ring->rx_mini_max_pending = 0; | |
4273 | ring->rx_jumbo_max_pending = 0; | |
4274 | ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
4275 | ||
4276 | ring->rx_pending = np->rx_ring_size; | |
4277 | ring->rx_mini_pending = 0; | |
4278 | ring->rx_jumbo_pending = 0; | |
4279 | ring->tx_pending = np->tx_ring_size; | |
4280 | } | |
4281 | ||
4282 | static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) | |
4283 | { | |
4284 | struct fe_priv *np = netdev_priv(dev); | |
4285 | u8 __iomem *base = get_hwbase(dev); | |
761fcd9e | 4286 | u8 *rxtx_ring, *rx_skbuff, *tx_skbuff; |
eafa59f6 AA |
4287 | dma_addr_t ring_addr; |
4288 | ||
4289 | if (ring->rx_pending < RX_RING_MIN || | |
4290 | ring->tx_pending < TX_RING_MIN || | |
4291 | ring->rx_mini_pending != 0 || | |
4292 | ring->rx_jumbo_pending != 0 || | |
4293 | (np->desc_ver == DESC_VER_1 && | |
4294 | (ring->rx_pending > RING_MAX_DESC_VER_1 || | |
4295 | ring->tx_pending > RING_MAX_DESC_VER_1)) || | |
4296 | (np->desc_ver != DESC_VER_1 && | |
4297 | (ring->rx_pending > RING_MAX_DESC_VER_2_3 || | |
4298 | ring->tx_pending > RING_MAX_DESC_VER_2_3))) { | |
4299 | return -EINVAL; | |
4300 | } | |
4301 | ||
4302 | /* allocate new rings */ | |
36b30ea9 | 4303 | if (!nv_optimized(np)) { |
eafa59f6 AA |
4304 | rxtx_ring = pci_alloc_consistent(np->pci_dev, |
4305 | sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), | |
4306 | &ring_addr); | |
4307 | } else { | |
4308 | rxtx_ring = pci_alloc_consistent(np->pci_dev, | |
4309 | sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
4310 | &ring_addr); | |
4311 | } | |
761fcd9e AA |
4312 | rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL); |
4313 | tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL); | |
4314 | if (!rxtx_ring || !rx_skbuff || !tx_skbuff) { | |
eafa59f6 | 4315 | /* fall back to old rings */ |
36b30ea9 | 4316 | if (!nv_optimized(np)) { |
f82a9352 | 4317 | if (rxtx_ring) |
eafa59f6 AA |
4318 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), |
4319 | rxtx_ring, ring_addr); | |
4320 | } else { | |
4321 | if (rxtx_ring) | |
4322 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
4323 | rxtx_ring, ring_addr); | |
4324 | } | |
9b03b06b SJ |
4325 | |
4326 | kfree(rx_skbuff); | |
4327 | kfree(tx_skbuff); | |
eafa59f6 AA |
4328 | goto exit; |
4329 | } | |
4330 | ||
4331 | if (netif_running(dev)) { | |
4332 | nv_disable_irq(dev); | |
08d93575 | 4333 | nv_napi_disable(dev); |
58dfd9c1 | 4334 | netif_tx_lock_bh(dev); |
e308a5d8 | 4335 | netif_addr_lock(dev); |
eafa59f6 AA |
4336 | spin_lock(&np->lock); |
4337 | /* stop engines */ | |
36b30ea9 | 4338 | nv_stop_rxtx(dev); |
eafa59f6 AA |
4339 | nv_txrx_reset(dev); |
4340 | /* drain queues */ | |
36b30ea9 | 4341 | nv_drain_rxtx(dev); |
eafa59f6 AA |
4342 | /* delete queues */ |
4343 | free_rings(dev); | |
4344 | } | |
4345 | ||
4346 | /* set new values */ | |
4347 | np->rx_ring_size = ring->rx_pending; | |
4348 | np->tx_ring_size = ring->tx_pending; | |
36b30ea9 JG |
4349 | |
4350 | if (!nv_optimized(np)) { | |
78aea4fc | 4351 | np->rx_ring.orig = (struct ring_desc *)rxtx_ring; |
eafa59f6 AA |
4352 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
4353 | } else { | |
78aea4fc | 4354 | np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring; |
eafa59f6 AA |
4355 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
4356 | } | |
78aea4fc SJ |
4357 | np->rx_skb = (struct nv_skb_map *)rx_skbuff; |
4358 | np->tx_skb = (struct nv_skb_map *)tx_skbuff; | |
eafa59f6 AA |
4359 | np->ring_addr = ring_addr; |
4360 | ||
761fcd9e AA |
4361 | memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); |
4362 | memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); | |
eafa59f6 AA |
4363 | |
4364 | if (netif_running(dev)) { | |
4365 | /* reinit driver view of the queues */ | |
4366 | set_bufsize(dev); | |
4367 | if (nv_init_ring(dev)) { | |
4368 | if (!np->in_shutdown) | |
4369 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4370 | } | |
4371 | ||
4372 | /* reinit nic view of the queues */ | |
4373 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4374 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 4375 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
eafa59f6 AA |
4376 | base + NvRegRingSizes); |
4377 | pci_push(base); | |
4378 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4379 | pci_push(base); | |
4380 | ||
4381 | /* restart engines */ | |
36b30ea9 | 4382 | nv_start_rxtx(dev); |
eafa59f6 | 4383 | spin_unlock(&np->lock); |
e308a5d8 | 4384 | netif_addr_unlock(dev); |
58dfd9c1 | 4385 | netif_tx_unlock_bh(dev); |
08d93575 | 4386 | nv_napi_enable(dev); |
eafa59f6 AA |
4387 | nv_enable_irq(dev); |
4388 | } | |
4389 | return 0; | |
4390 | exit: | |
4391 | return -ENOMEM; | |
4392 | } | |
4393 | ||
b6d0773f AA |
4394 | static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
4395 | { | |
4396 | struct fe_priv *np = netdev_priv(dev); | |
4397 | ||
4398 | pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; | |
4399 | pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; | |
4400 | pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0; | |
4401 | } | |
4402 | ||
4403 | static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) | |
4404 | { | |
4405 | struct fe_priv *np = netdev_priv(dev); | |
4406 | int adv, bmcr; | |
4407 | ||
4408 | if ((!np->autoneg && np->duplex == 0) || | |
4409 | (np->autoneg && !pause->autoneg && np->duplex == 0)) { | |
1d397f36 | 4410 | netdev_info(dev, "can not set pause settings when forced link is in half duplex\n"); |
b6d0773f AA |
4411 | return -EINVAL; |
4412 | } | |
4413 | if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { | |
1d397f36 | 4414 | netdev_info(dev, "hardware does not support tx pause frames\n"); |
b6d0773f AA |
4415 | return -EINVAL; |
4416 | } | |
4417 | ||
4418 | netif_carrier_off(dev); | |
4419 | if (netif_running(dev)) { | |
4420 | nv_disable_irq(dev); | |
58dfd9c1 | 4421 | netif_tx_lock_bh(dev); |
e308a5d8 | 4422 | netif_addr_lock(dev); |
b6d0773f AA |
4423 | spin_lock(&np->lock); |
4424 | /* stop engines */ | |
36b30ea9 | 4425 | nv_stop_rxtx(dev); |
b6d0773f | 4426 | spin_unlock(&np->lock); |
e308a5d8 | 4427 | netif_addr_unlock(dev); |
58dfd9c1 | 4428 | netif_tx_unlock_bh(dev); |
b6d0773f AA |
4429 | } |
4430 | ||
4431 | np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ); | |
4432 | if (pause->rx_pause) | |
4433 | np->pause_flags |= NV_PAUSEFRAME_RX_REQ; | |
4434 | if (pause->tx_pause) | |
4435 | np->pause_flags |= NV_PAUSEFRAME_TX_REQ; | |
4436 | ||
4437 | if (np->autoneg && pause->autoneg) { | |
4438 | np->pause_flags |= NV_PAUSEFRAME_AUTONEG; | |
4439 | ||
4440 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
4441 | adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
25985edc | 4442 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */ |
b6d0773f AA |
4443 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
4444 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4445 | adv |= ADVERTISE_PAUSE_ASYM; | |
4446 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); | |
4447 | ||
4448 | if (netif_running(dev)) | |
1d397f36 | 4449 | netdev_info(dev, "link down\n"); |
b6d0773f AA |
4450 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
4451 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4452 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4453 | } else { | |
4454 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
4455 | if (pause->rx_pause) | |
4456 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4457 | if (pause->tx_pause) | |
4458 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4459 | ||
4460 | if (!netif_running(dev)) | |
4461 | nv_update_linkspeed(dev); | |
4462 | else | |
4463 | nv_update_pause(dev, np->pause_flags); | |
4464 | } | |
4465 | ||
4466 | if (netif_running(dev)) { | |
36b30ea9 | 4467 | nv_start_rxtx(dev); |
b6d0773f AA |
4468 | nv_enable_irq(dev); |
4469 | } | |
4470 | return 0; | |
4471 | } | |
4472 | ||
569e1463 | 4473 | static u32 nv_fix_features(struct net_device *dev, u32 features) |
5ed2616f | 4474 | { |
569e1463 MM |
4475 | /* vlan is dependent on rx checksum offload */ |
4476 | if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX)) | |
4477 | features |= NETIF_F_RXCSUM; | |
4478 | ||
4479 | return features; | |
5ed2616f AA |
4480 | } |
4481 | ||
569e1463 | 4482 | static int nv_set_features(struct net_device *dev, u32 features) |
5ed2616f AA |
4483 | { |
4484 | struct fe_priv *np = netdev_priv(dev); | |
4485 | u8 __iomem *base = get_hwbase(dev); | |
569e1463 | 4486 | u32 changed = dev->features ^ features; |
5ed2616f | 4487 | |
569e1463 MM |
4488 | if (changed & NETIF_F_RXCSUM) { |
4489 | spin_lock_irq(&np->lock); | |
5ed2616f | 4490 | |
569e1463 MM |
4491 | if (features & NETIF_F_RXCSUM) |
4492 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; | |
4493 | else | |
4494 | np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; | |
5ed2616f | 4495 | |
569e1463 MM |
4496 | if (netif_running(dev)) |
4497 | writel(np->txrxctl_bits, base + NvRegTxRxControl); | |
5ed2616f | 4498 | |
569e1463 MM |
4499 | spin_unlock_irq(&np->lock); |
4500 | } | |
5ed2616f | 4501 | |
569e1463 | 4502 | return 0; |
5ed2616f AA |
4503 | } |
4504 | ||
b9f2c044 | 4505 | static int nv_get_sset_count(struct net_device *dev, int sset) |
52da3578 AA |
4506 | { |
4507 | struct fe_priv *np = netdev_priv(dev); | |
4508 | ||
b9f2c044 JG |
4509 | switch (sset) { |
4510 | case ETH_SS_TEST: | |
4511 | if (np->driver_data & DEV_HAS_TEST_EXTENDED) | |
4512 | return NV_TEST_COUNT_EXTENDED; | |
4513 | else | |
4514 | return NV_TEST_COUNT_BASE; | |
4515 | case ETH_SS_STATS: | |
8ed1454a AA |
4516 | if (np->driver_data & DEV_HAS_STATISTICS_V3) |
4517 | return NV_DEV_STATISTICS_V3_COUNT; | |
b9f2c044 JG |
4518 | else if (np->driver_data & DEV_HAS_STATISTICS_V2) |
4519 | return NV_DEV_STATISTICS_V2_COUNT; | |
8ed1454a AA |
4520 | else if (np->driver_data & DEV_HAS_STATISTICS_V1) |
4521 | return NV_DEV_STATISTICS_V1_COUNT; | |
b9f2c044 JG |
4522 | else |
4523 | return 0; | |
4524 | default: | |
4525 | return -EOPNOTSUPP; | |
4526 | } | |
52da3578 AA |
4527 | } |
4528 | ||
4529 | static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer) | |
4530 | { | |
4531 | struct fe_priv *np = netdev_priv(dev); | |
4532 | ||
4533 | /* update stats */ | |
4534 | nv_do_stats_poll((unsigned long)dev); | |
4535 | ||
b9f2c044 | 4536 | memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64)); |
9589c77a AA |
4537 | } |
4538 | ||
4539 | static int nv_link_test(struct net_device *dev) | |
4540 | { | |
4541 | struct fe_priv *np = netdev_priv(dev); | |
4542 | int mii_status; | |
4543 | ||
4544 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4545 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4546 | ||
4547 | /* check phy link status */ | |
4548 | if (!(mii_status & BMSR_LSTATUS)) | |
4549 | return 0; | |
4550 | else | |
4551 | return 1; | |
4552 | } | |
4553 | ||
4554 | static int nv_register_test(struct net_device *dev) | |
4555 | { | |
4556 | u8 __iomem *base = get_hwbase(dev); | |
4557 | int i = 0; | |
4558 | u32 orig_read, new_read; | |
4559 | ||
4560 | do { | |
4561 | orig_read = readl(base + nv_registers_test[i].reg); | |
4562 | ||
4563 | /* xor with mask to toggle bits */ | |
4564 | orig_read ^= nv_registers_test[i].mask; | |
4565 | ||
4566 | writel(orig_read, base + nv_registers_test[i].reg); | |
4567 | ||
4568 | new_read = readl(base + nv_registers_test[i].reg); | |
4569 | ||
4570 | if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask)) | |
4571 | return 0; | |
4572 | ||
4573 | /* restore original value */ | |
4574 | orig_read ^= nv_registers_test[i].mask; | |
4575 | writel(orig_read, base + nv_registers_test[i].reg); | |
4576 | ||
4577 | } while (nv_registers_test[++i].reg != 0); | |
4578 | ||
4579 | return 1; | |
4580 | } | |
4581 | ||
4582 | static int nv_interrupt_test(struct net_device *dev) | |
4583 | { | |
4584 | struct fe_priv *np = netdev_priv(dev); | |
4585 | u8 __iomem *base = get_hwbase(dev); | |
4586 | int ret = 1; | |
4587 | int testcnt; | |
4588 | u32 save_msi_flags, save_poll_interval = 0; | |
4589 | ||
4590 | if (netif_running(dev)) { | |
4591 | /* free current irq */ | |
4592 | nv_free_irq(dev); | |
4593 | save_poll_interval = readl(base+NvRegPollingInterval); | |
4594 | } | |
4595 | ||
4596 | /* flag to test interrupt handler */ | |
4597 | np->intr_test = 0; | |
4598 | ||
4599 | /* setup test irq */ | |
4600 | save_msi_flags = np->msi_flags; | |
4601 | np->msi_flags &= ~NV_MSI_X_VECTORS_MASK; | |
4602 | np->msi_flags |= 0x001; /* setup 1 vector */ | |
4603 | if (nv_request_irq(dev, 1)) | |
4604 | return 0; | |
4605 | ||
4606 | /* setup timer interrupt */ | |
4607 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
4608 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
4609 | ||
4610 | nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
4611 | ||
4612 | /* wait for at least one interrupt */ | |
4613 | msleep(100); | |
4614 | ||
4615 | spin_lock_irq(&np->lock); | |
4616 | ||
4617 | /* flag should be set within ISR */ | |
4618 | testcnt = np->intr_test; | |
4619 | if (!testcnt) | |
4620 | ret = 2; | |
4621 | ||
4622 | nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
4623 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
4624 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
4625 | else | |
4626 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
4627 | ||
4628 | spin_unlock_irq(&np->lock); | |
4629 | ||
4630 | nv_free_irq(dev); | |
4631 | ||
4632 | np->msi_flags = save_msi_flags; | |
4633 | ||
4634 | if (netif_running(dev)) { | |
4635 | writel(save_poll_interval, base + NvRegPollingInterval); | |
4636 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
4637 | /* restore original irq */ | |
4638 | if (nv_request_irq(dev, 0)) | |
4639 | return 0; | |
4640 | } | |
4641 | ||
4642 | return ret; | |
4643 | } | |
4644 | ||
4645 | static int nv_loopback_test(struct net_device *dev) | |
4646 | { | |
4647 | struct fe_priv *np = netdev_priv(dev); | |
4648 | u8 __iomem *base = get_hwbase(dev); | |
4649 | struct sk_buff *tx_skb, *rx_skb; | |
4650 | dma_addr_t test_dma_addr; | |
4651 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); | |
f82a9352 | 4652 | u32 flags; |
9589c77a AA |
4653 | int len, i, pkt_len; |
4654 | u8 *pkt_data; | |
4655 | u32 filter_flags = 0; | |
4656 | u32 misc1_flags = 0; | |
4657 | int ret = 1; | |
4658 | ||
4659 | if (netif_running(dev)) { | |
4660 | nv_disable_irq(dev); | |
4661 | filter_flags = readl(base + NvRegPacketFilterFlags); | |
4662 | misc1_flags = readl(base + NvRegMisc1); | |
4663 | } else { | |
4664 | nv_txrx_reset(dev); | |
4665 | } | |
4666 | ||
4667 | /* reinit driver view of the rx queue */ | |
4668 | set_bufsize(dev); | |
4669 | nv_init_ring(dev); | |
4670 | ||
4671 | /* setup hardware for loopback */ | |
4672 | writel(NVREG_MISC1_FORCE, base + NvRegMisc1); | |
4673 | writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags); | |
4674 | ||
4675 | /* reinit nic view of the rx queue */ | |
4676 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4677 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 4678 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
9589c77a AA |
4679 | base + NvRegRingSizes); |
4680 | pci_push(base); | |
4681 | ||
4682 | /* restart rx engine */ | |
36b30ea9 | 4683 | nv_start_rxtx(dev); |
9589c77a AA |
4684 | |
4685 | /* setup packet for tx */ | |
4686 | pkt_len = ETH_DATA_LEN; | |
4687 | tx_skb = dev_alloc_skb(pkt_len); | |
46798c89 | 4688 | if (!tx_skb) { |
1d397f36 | 4689 | netdev_err(dev, "dev_alloc_skb() failed during loopback test\n"); |
46798c89 JJ |
4690 | ret = 0; |
4691 | goto out; | |
4692 | } | |
8b5be268 ACM |
4693 | test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data, |
4694 | skb_tailroom(tx_skb), | |
4695 | PCI_DMA_FROMDEVICE); | |
9589c77a AA |
4696 | pkt_data = skb_put(tx_skb, pkt_len); |
4697 | for (i = 0; i < pkt_len; i++) | |
4698 | pkt_data[i] = (u8)(i & 0xff); | |
9589c77a | 4699 | |
36b30ea9 | 4700 | if (!nv_optimized(np)) { |
f82a9352 SH |
4701 | np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr); |
4702 | np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); | |
9589c77a | 4703 | } else { |
5bb7ea26 AV |
4704 | np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr)); |
4705 | np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr)); | |
f82a9352 | 4706 | np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); |
9589c77a AA |
4707 | } |
4708 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4709 | pci_push(get_hwbase(dev)); | |
4710 | ||
4711 | msleep(500); | |
4712 | ||
4713 | /* check for rx of the packet */ | |
36b30ea9 | 4714 | if (!nv_optimized(np)) { |
f82a9352 | 4715 | flags = le32_to_cpu(np->rx_ring.orig[0].flaglen); |
9589c77a AA |
4716 | len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); |
4717 | ||
4718 | } else { | |
f82a9352 | 4719 | flags = le32_to_cpu(np->rx_ring.ex[0].flaglen); |
9589c77a AA |
4720 | len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); |
4721 | } | |
4722 | ||
f82a9352 | 4723 | if (flags & NV_RX_AVAIL) { |
9589c77a AA |
4724 | ret = 0; |
4725 | } else if (np->desc_ver == DESC_VER_1) { | |
f82a9352 | 4726 | if (flags & NV_RX_ERROR) |
9589c77a AA |
4727 | ret = 0; |
4728 | } else { | |
78aea4fc | 4729 | if (flags & NV_RX2_ERROR) |
9589c77a | 4730 | ret = 0; |
9589c77a AA |
4731 | } |
4732 | ||
4733 | if (ret) { | |
4734 | if (len != pkt_len) { | |
4735 | ret = 0; | |
9589c77a | 4736 | } else { |
761fcd9e | 4737 | rx_skb = np->rx_skb[0].skb; |
9589c77a AA |
4738 | for (i = 0; i < pkt_len; i++) { |
4739 | if (rx_skb->data[i] != (u8)(i & 0xff)) { | |
4740 | ret = 0; | |
9589c77a AA |
4741 | break; |
4742 | } | |
4743 | } | |
4744 | } | |
9589c77a AA |
4745 | } |
4746 | ||
73a37079 | 4747 | pci_unmap_single(np->pci_dev, test_dma_addr, |
4305b541 | 4748 | (skb_end_pointer(tx_skb) - tx_skb->data), |
9589c77a AA |
4749 | PCI_DMA_TODEVICE); |
4750 | dev_kfree_skb_any(tx_skb); | |
46798c89 | 4751 | out: |
9589c77a | 4752 | /* stop engines */ |
36b30ea9 | 4753 | nv_stop_rxtx(dev); |
9589c77a AA |
4754 | nv_txrx_reset(dev); |
4755 | /* drain rx queue */ | |
36b30ea9 | 4756 | nv_drain_rxtx(dev); |
9589c77a AA |
4757 | |
4758 | if (netif_running(dev)) { | |
4759 | writel(misc1_flags, base + NvRegMisc1); | |
4760 | writel(filter_flags, base + NvRegPacketFilterFlags); | |
4761 | nv_enable_irq(dev); | |
4762 | } | |
4763 | ||
4764 | return ret; | |
4765 | } | |
4766 | ||
4767 | static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer) | |
4768 | { | |
4769 | struct fe_priv *np = netdev_priv(dev); | |
4770 | u8 __iomem *base = get_hwbase(dev); | |
4771 | int result; | |
b9f2c044 | 4772 | memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64)); |
9589c77a AA |
4773 | |
4774 | if (!nv_link_test(dev)) { | |
4775 | test->flags |= ETH_TEST_FL_FAILED; | |
4776 | buffer[0] = 1; | |
4777 | } | |
4778 | ||
4779 | if (test->flags & ETH_TEST_FL_OFFLINE) { | |
4780 | if (netif_running(dev)) { | |
4781 | netif_stop_queue(dev); | |
08d93575 | 4782 | nv_napi_disable(dev); |
58dfd9c1 | 4783 | netif_tx_lock_bh(dev); |
e308a5d8 | 4784 | netif_addr_lock(dev); |
9589c77a AA |
4785 | spin_lock_irq(&np->lock); |
4786 | nv_disable_hw_interrupts(dev, np->irqmask); | |
78aea4fc | 4787 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
9589c77a | 4788 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
78aea4fc | 4789 | else |
9589c77a | 4790 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); |
9589c77a | 4791 | /* stop engines */ |
36b30ea9 | 4792 | nv_stop_rxtx(dev); |
9589c77a AA |
4793 | nv_txrx_reset(dev); |
4794 | /* drain rx queue */ | |
36b30ea9 | 4795 | nv_drain_rxtx(dev); |
9589c77a | 4796 | spin_unlock_irq(&np->lock); |
e308a5d8 | 4797 | netif_addr_unlock(dev); |
58dfd9c1 | 4798 | netif_tx_unlock_bh(dev); |
9589c77a AA |
4799 | } |
4800 | ||
4801 | if (!nv_register_test(dev)) { | |
4802 | test->flags |= ETH_TEST_FL_FAILED; | |
4803 | buffer[1] = 1; | |
4804 | } | |
4805 | ||
4806 | result = nv_interrupt_test(dev); | |
4807 | if (result != 1) { | |
4808 | test->flags |= ETH_TEST_FL_FAILED; | |
4809 | buffer[2] = 1; | |
4810 | } | |
4811 | if (result == 0) { | |
4812 | /* bail out */ | |
4813 | return; | |
4814 | } | |
4815 | ||
4816 | if (!nv_loopback_test(dev)) { | |
4817 | test->flags |= ETH_TEST_FL_FAILED; | |
4818 | buffer[3] = 1; | |
4819 | } | |
4820 | ||
4821 | if (netif_running(dev)) { | |
4822 | /* reinit driver view of the rx queue */ | |
4823 | set_bufsize(dev); | |
4824 | if (nv_init_ring(dev)) { | |
4825 | if (!np->in_shutdown) | |
4826 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4827 | } | |
4828 | /* reinit nic view of the rx queue */ | |
4829 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4830 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 4831 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
9589c77a AA |
4832 | base + NvRegRingSizes); |
4833 | pci_push(base); | |
4834 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4835 | pci_push(base); | |
4836 | /* restart rx engine */ | |
36b30ea9 | 4837 | nv_start_rxtx(dev); |
9589c77a | 4838 | netif_start_queue(dev); |
08d93575 | 4839 | nv_napi_enable(dev); |
9589c77a AA |
4840 | nv_enable_hw_interrupts(dev, np->irqmask); |
4841 | } | |
4842 | } | |
4843 | } | |
4844 | ||
52da3578 AA |
4845 | static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer) |
4846 | { | |
4847 | switch (stringset) { | |
4848 | case ETH_SS_STATS: | |
b9f2c044 | 4849 | memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str)); |
52da3578 | 4850 | break; |
9589c77a | 4851 | case ETH_SS_TEST: |
b9f2c044 | 4852 | memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str)); |
9589c77a | 4853 | break; |
52da3578 AA |
4854 | } |
4855 | } | |
4856 | ||
7282d491 | 4857 | static const struct ethtool_ops ops = { |
1da177e4 LT |
4858 | .get_drvinfo = nv_get_drvinfo, |
4859 | .get_link = ethtool_op_get_link, | |
4860 | .get_wol = nv_get_wol, | |
4861 | .set_wol = nv_set_wol, | |
4862 | .get_settings = nv_get_settings, | |
4863 | .set_settings = nv_set_settings, | |
dc8216c1 MS |
4864 | .get_regs_len = nv_get_regs_len, |
4865 | .get_regs = nv_get_regs, | |
4866 | .nway_reset = nv_nway_reset, | |
eafa59f6 AA |
4867 | .get_ringparam = nv_get_ringparam, |
4868 | .set_ringparam = nv_set_ringparam, | |
b6d0773f AA |
4869 | .get_pauseparam = nv_get_pauseparam, |
4870 | .set_pauseparam = nv_set_pauseparam, | |
52da3578 | 4871 | .get_strings = nv_get_strings, |
52da3578 | 4872 | .get_ethtool_stats = nv_get_ethtool_stats, |
b9f2c044 | 4873 | .get_sset_count = nv_get_sset_count, |
9589c77a | 4874 | .self_test = nv_self_test, |
1da177e4 LT |
4875 | }; |
4876 | ||
ee407b02 AA |
4877 | static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) |
4878 | { | |
4879 | struct fe_priv *np = get_nvpriv(dev); | |
4880 | ||
4881 | spin_lock_irq(&np->lock); | |
4882 | ||
4883 | /* save vlan group */ | |
4884 | np->vlangrp = grp; | |
4885 | ||
4886 | if (grp) { | |
4887 | /* enable vlan on MAC */ | |
4888 | np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS; | |
4889 | } else { | |
4890 | /* disable vlan on MAC */ | |
4891 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; | |
4892 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; | |
4893 | } | |
4894 | ||
4895 | writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4896 | ||
4897 | spin_unlock_irq(&np->lock); | |
25805dcf | 4898 | } |
ee407b02 | 4899 | |
7e680c22 AA |
4900 | /* The mgmt unit and driver use a semaphore to access the phy during init */ |
4901 | static int nv_mgmt_acquire_sema(struct net_device *dev) | |
4902 | { | |
cac1c52c | 4903 | struct fe_priv *np = netdev_priv(dev); |
7e680c22 AA |
4904 | u8 __iomem *base = get_hwbase(dev); |
4905 | int i; | |
4906 | u32 tx_ctrl, mgmt_sema; | |
4907 | ||
4908 | for (i = 0; i < 10; i++) { | |
4909 | mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK; | |
4910 | if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE) | |
4911 | break; | |
4912 | msleep(500); | |
4913 | } | |
4914 | ||
4915 | if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE) | |
4916 | return 0; | |
4917 | ||
4918 | for (i = 0; i < 2; i++) { | |
4919 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
4920 | tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ; | |
4921 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
4922 | ||
4923 | /* verify that semaphore was acquired */ | |
4924 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
4925 | if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) && | |
cac1c52c AA |
4926 | ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) { |
4927 | np->mgmt_sema = 1; | |
7e680c22 | 4928 | return 1; |
78aea4fc | 4929 | } else |
7e680c22 AA |
4930 | udelay(50); |
4931 | } | |
4932 | ||
4933 | return 0; | |
4934 | } | |
4935 | ||
cac1c52c AA |
4936 | static void nv_mgmt_release_sema(struct net_device *dev) |
4937 | { | |
4938 | struct fe_priv *np = netdev_priv(dev); | |
4939 | u8 __iomem *base = get_hwbase(dev); | |
4940 | u32 tx_ctrl; | |
4941 | ||
4942 | if (np->driver_data & DEV_HAS_MGMT_UNIT) { | |
4943 | if (np->mgmt_sema) { | |
4944 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
4945 | tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ; | |
4946 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
4947 | } | |
4948 | } | |
4949 | } | |
4950 | ||
4951 | ||
4952 | static int nv_mgmt_get_version(struct net_device *dev) | |
4953 | { | |
4954 | struct fe_priv *np = netdev_priv(dev); | |
4955 | u8 __iomem *base = get_hwbase(dev); | |
4956 | u32 data_ready = readl(base + NvRegTransmitterControl); | |
4957 | u32 data_ready2 = 0; | |
4958 | unsigned long start; | |
4959 | int ready = 0; | |
4960 | ||
4961 | writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion); | |
4962 | writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl); | |
4963 | start = jiffies; | |
4964 | while (time_before(jiffies, start + 5*HZ)) { | |
4965 | data_ready2 = readl(base + NvRegTransmitterControl); | |
4966 | if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) { | |
4967 | ready = 1; | |
4968 | break; | |
4969 | } | |
4970 | schedule_timeout_uninterruptible(1); | |
4971 | } | |
4972 | ||
4973 | if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR)) | |
4974 | return 0; | |
4975 | ||
4976 | np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION; | |
4977 | ||
4978 | return 1; | |
4979 | } | |
4980 | ||
1da177e4 LT |
4981 | static int nv_open(struct net_device *dev) |
4982 | { | |
ac9c1897 | 4983 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 4984 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 AA |
4985 | int ret = 1; |
4986 | int oom, i; | |
a433686c | 4987 | u32 low; |
1da177e4 | 4988 | |
cb52deba ES |
4989 | /* power up phy */ |
4990 | mii_rw(dev, np->phyaddr, MII_BMCR, | |
4991 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); | |
4992 | ||
88d7d8b0 | 4993 | nv_txrx_gate(dev, false); |
f1489653 | 4994 | /* erase previous misconfiguration */ |
86a0f043 AA |
4995 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
4996 | nv_mac_reset(dev); | |
1da177e4 LT |
4997 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
4998 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
4999 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
5000 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
5001 | writel(0, base + NvRegPacketFilterFlags); |
5002 | ||
5003 | writel(0, base + NvRegTransmitterControl); | |
5004 | writel(0, base + NvRegReceiverControl); | |
5005 | ||
5006 | writel(0, base + NvRegAdapterControl); | |
5007 | ||
eb91f61b AA |
5008 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) |
5009 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
5010 | ||
f1489653 | 5011 | /* initialize descriptor rings */ |
d81c0983 | 5012 | set_bufsize(dev); |
1da177e4 LT |
5013 | oom = nv_init_ring(dev); |
5014 | ||
5015 | writel(0, base + NvRegLinkSpeed); | |
5070d340 | 5016 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
1da177e4 LT |
5017 | nv_txrx_reset(dev); |
5018 | writel(0, base + NvRegUnknownSetupReg6); | |
5019 | ||
5020 | np->in_shutdown = 0; | |
5021 | ||
f1489653 | 5022 | /* give hw rings */ |
0832b25a | 5023 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
78aea4fc | 5024 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
1da177e4 LT |
5025 | base + NvRegRingSizes); |
5026 | ||
1da177e4 | 5027 | writel(np->linkspeed, base + NvRegLinkSpeed); |
95d161cb AA |
5028 | if (np->desc_ver == DESC_VER_1) |
5029 | writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); | |
5030 | else | |
5031 | writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark); | |
8a4ae7f2 | 5032 | writel(np->txrxctl_bits, base + NvRegTxRxControl); |
ee407b02 | 5033 | writel(np->vlanctl_bits, base + NvRegVlanControl); |
1da177e4 | 5034 | pci_push(base); |
8a4ae7f2 | 5035 | writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
344d0dce JP |
5036 | if (reg_delay(dev, NvRegUnknownSetupReg5, |
5037 | NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, | |
5038 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX)) | |
1d397f36 JP |
5039 | netdev_info(dev, |
5040 | "%s: SetupReg5, Bit 31 remained off\n", __func__); | |
1da177e4 | 5041 | |
7e680c22 | 5042 | writel(0, base + NvRegMIIMask); |
1da177e4 | 5043 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
eb798428 | 5044 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 | 5045 | |
1da177e4 LT |
5046 | writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
5047 | writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); | |
5048 | writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); | |
d81c0983 | 5049 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
1da177e4 LT |
5050 | |
5051 | writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); | |
a433686c AA |
5052 | |
5053 | get_random_bytes(&low, sizeof(low)); | |
5054 | low &= NVREG_SLOTTIME_MASK; | |
5055 | if (np->desc_ver == DESC_VER_1) { | |
5056 | writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime); | |
5057 | } else { | |
5058 | if (!(np->driver_data & DEV_HAS_GEAR_MODE)) { | |
5059 | /* setup legacy backoff */ | |
5060 | writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime); | |
5061 | } else { | |
5062 | writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime); | |
5063 | nv_gear_backoff_reseed(dev); | |
5064 | } | |
5065 | } | |
9744e218 AA |
5066 | writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); |
5067 | writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); | |
a971c324 AA |
5068 | if (poll_interval == -1) { |
5069 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) | |
5070 | writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); | |
5071 | else | |
5072 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
78aea4fc | 5073 | } else |
a971c324 | 5074 | writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); |
1da177e4 LT |
5075 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
5076 | writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, | |
5077 | base + NvRegAdapterControl); | |
5078 | writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); | |
7e680c22 | 5079 | writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask); |
c42d9df9 AA |
5080 | if (np->wolenabled) |
5081 | writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); | |
1da177e4 LT |
5082 | |
5083 | i = readl(base + NvRegPowerState); | |
78aea4fc | 5084 | if ((i & NVREG_POWERSTATE_POWEREDUP) == 0) |
1da177e4 LT |
5085 | writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); |
5086 | ||
5087 | pci_push(base); | |
5088 | udelay(10); | |
5089 | writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); | |
5090 | ||
84b3932b | 5091 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 | 5092 | pci_push(base); |
eb798428 | 5093 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 LT |
5094 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
5095 | pci_push(base); | |
5096 | ||
78aea4fc | 5097 | if (nv_request_irq(dev, 0)) |
84b3932b | 5098 | goto out_drain; |
1da177e4 LT |
5099 | |
5100 | /* ask for interrupts */ | |
84b3932b | 5101 | nv_enable_hw_interrupts(dev, np->irqmask); |
1da177e4 LT |
5102 | |
5103 | spin_lock_irq(&np->lock); | |
5104 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); | |
5105 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
5106 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
5107 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
5108 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
5109 | /* One manual link speed update: Interrupts are enabled, future link | |
5110 | * speed changes cause interrupts and are handled by nv_link_irq(). | |
5111 | */ | |
5112 | { | |
5113 | u32 miistat; | |
5114 | miistat = readl(base + NvRegMIIStatus); | |
eb798428 | 5115 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 | 5116 | } |
1b1b3c9b MS |
5117 | /* set linkspeed to invalid value, thus force nv_update_linkspeed |
5118 | * to init hw */ | |
5119 | np->linkspeed = 0; | |
1da177e4 | 5120 | ret = nv_update_linkspeed(dev); |
36b30ea9 | 5121 | nv_start_rxtx(dev); |
1da177e4 | 5122 | netif_start_queue(dev); |
08d93575 | 5123 | nv_napi_enable(dev); |
e27cdba5 | 5124 | |
1da177e4 LT |
5125 | if (ret) { |
5126 | netif_carrier_on(dev); | |
5127 | } else { | |
1d397f36 | 5128 | netdev_info(dev, "no link during initialization\n"); |
1da177e4 LT |
5129 | netif_carrier_off(dev); |
5130 | } | |
5131 | if (oom) | |
5132 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
52da3578 AA |
5133 | |
5134 | /* start statistics timer */ | |
9c662435 | 5135 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
bfebbb88 DD |
5136 | mod_timer(&np->stats_poll, |
5137 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 | 5138 | |
1da177e4 LT |
5139 | spin_unlock_irq(&np->lock); |
5140 | ||
5141 | return 0; | |
5142 | out_drain: | |
36b30ea9 | 5143 | nv_drain_rxtx(dev); |
1da177e4 LT |
5144 | return ret; |
5145 | } | |
5146 | ||
5147 | static int nv_close(struct net_device *dev) | |
5148 | { | |
ac9c1897 | 5149 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
5150 | u8 __iomem *base; |
5151 | ||
5152 | spin_lock_irq(&np->lock); | |
5153 | np->in_shutdown = 1; | |
5154 | spin_unlock_irq(&np->lock); | |
08d93575 | 5155 | nv_napi_disable(dev); |
a7475906 | 5156 | synchronize_irq(np->pci_dev->irq); |
1da177e4 LT |
5157 | |
5158 | del_timer_sync(&np->oom_kick); | |
5159 | del_timer_sync(&np->nic_poll); | |
52da3578 | 5160 | del_timer_sync(&np->stats_poll); |
1da177e4 LT |
5161 | |
5162 | netif_stop_queue(dev); | |
5163 | spin_lock_irq(&np->lock); | |
36b30ea9 | 5164 | nv_stop_rxtx(dev); |
1da177e4 LT |
5165 | nv_txrx_reset(dev); |
5166 | ||
5167 | /* disable interrupts on the nic or we will lock up */ | |
5168 | base = get_hwbase(dev); | |
84b3932b | 5169 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 | 5170 | pci_push(base); |
1da177e4 LT |
5171 | |
5172 | spin_unlock_irq(&np->lock); | |
5173 | ||
84b3932b | 5174 | nv_free_irq(dev); |
1da177e4 | 5175 | |
36b30ea9 | 5176 | nv_drain_rxtx(dev); |
1da177e4 | 5177 | |
5a9a8e32 | 5178 | if (np->wolenabled || !phy_power_down) { |
88d7d8b0 | 5179 | nv_txrx_gate(dev, false); |
2cc49a5c | 5180 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
1da177e4 | 5181 | nv_start_rx(dev); |
cb52deba ES |
5182 | } else { |
5183 | /* power down phy */ | |
5184 | mii_rw(dev, np->phyaddr, MII_BMCR, | |
5185 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); | |
88d7d8b0 | 5186 | nv_txrx_gate(dev, true); |
2cc49a5c | 5187 | } |
1da177e4 LT |
5188 | |
5189 | /* FIXME: power down nic */ | |
5190 | ||
5191 | return 0; | |
5192 | } | |
5193 | ||
b94426bd SH |
5194 | static const struct net_device_ops nv_netdev_ops = { |
5195 | .ndo_open = nv_open, | |
5196 | .ndo_stop = nv_close, | |
5197 | .ndo_get_stats = nv_get_stats, | |
00829823 SH |
5198 | .ndo_start_xmit = nv_start_xmit, |
5199 | .ndo_tx_timeout = nv_tx_timeout, | |
5200 | .ndo_change_mtu = nv_change_mtu, | |
569e1463 MM |
5201 | .ndo_fix_features = nv_fix_features, |
5202 | .ndo_set_features = nv_set_features, | |
00829823 SH |
5203 | .ndo_validate_addr = eth_validate_addr, |
5204 | .ndo_set_mac_address = nv_set_mac_address, | |
5205 | .ndo_set_multicast_list = nv_set_multicast, | |
5206 | .ndo_vlan_rx_register = nv_vlan_rx_register, | |
5207 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5208 | .ndo_poll_controller = nv_poll_controller, | |
5209 | #endif | |
5210 | }; | |
5211 | ||
5212 | static const struct net_device_ops nv_netdev_ops_optimized = { | |
5213 | .ndo_open = nv_open, | |
5214 | .ndo_stop = nv_close, | |
5215 | .ndo_get_stats = nv_get_stats, | |
5216 | .ndo_start_xmit = nv_start_xmit_optimized, | |
b94426bd SH |
5217 | .ndo_tx_timeout = nv_tx_timeout, |
5218 | .ndo_change_mtu = nv_change_mtu, | |
569e1463 MM |
5219 | .ndo_fix_features = nv_fix_features, |
5220 | .ndo_set_features = nv_set_features, | |
b94426bd SH |
5221 | .ndo_validate_addr = eth_validate_addr, |
5222 | .ndo_set_mac_address = nv_set_mac_address, | |
5223 | .ndo_set_multicast_list = nv_set_multicast, | |
5224 | .ndo_vlan_rx_register = nv_vlan_rx_register, | |
5225 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5226 | .ndo_poll_controller = nv_poll_controller, | |
5227 | #endif | |
5228 | }; | |
5229 | ||
1da177e4 LT |
5230 | static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) |
5231 | { | |
5232 | struct net_device *dev; | |
5233 | struct fe_priv *np; | |
5234 | unsigned long addr; | |
5235 | u8 __iomem *base; | |
5236 | int err, i; | |
5070d340 | 5237 | u32 powerstate, txreg; |
7e680c22 AA |
5238 | u32 phystate_orig = 0, phystate; |
5239 | int phyinitialized = 0; | |
3f88ce49 JG |
5240 | static int printed_version; |
5241 | ||
5242 | if (!printed_version++) | |
294a554e JP |
5243 | pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n", |
5244 | FORCEDETH_VERSION); | |
1da177e4 LT |
5245 | |
5246 | dev = alloc_etherdev(sizeof(struct fe_priv)); | |
5247 | err = -ENOMEM; | |
5248 | if (!dev) | |
5249 | goto out; | |
5250 | ||
ac9c1897 | 5251 | np = netdev_priv(dev); |
bea3348e | 5252 | np->dev = dev; |
1da177e4 LT |
5253 | np->pci_dev = pci_dev; |
5254 | spin_lock_init(&np->lock); | |
1da177e4 LT |
5255 | SET_NETDEV_DEV(dev, &pci_dev->dev); |
5256 | ||
5257 | init_timer(&np->oom_kick); | |
5258 | np->oom_kick.data = (unsigned long) dev; | |
c061b18d | 5259 | np->oom_kick.function = nv_do_rx_refill; /* timer handler */ |
1da177e4 LT |
5260 | init_timer(&np->nic_poll); |
5261 | np->nic_poll.data = (unsigned long) dev; | |
c061b18d | 5262 | np->nic_poll.function = nv_do_nic_poll; /* timer handler */ |
52da3578 AA |
5263 | init_timer(&np->stats_poll); |
5264 | np->stats_poll.data = (unsigned long) dev; | |
c061b18d | 5265 | np->stats_poll.function = nv_do_stats_poll; /* timer handler */ |
1da177e4 LT |
5266 | |
5267 | err = pci_enable_device(pci_dev); | |
3f88ce49 | 5268 | if (err) |
1da177e4 | 5269 | goto out_free; |
1da177e4 LT |
5270 | |
5271 | pci_set_master(pci_dev); | |
5272 | ||
5273 | err = pci_request_regions(pci_dev, DRV_NAME); | |
5274 | if (err < 0) | |
5275 | goto out_disable; | |
5276 | ||
9c662435 | 5277 | if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
57fff698 AA |
5278 | np->register_size = NV_PCI_REGSZ_VER3; |
5279 | else if (id->driver_data & DEV_HAS_STATISTICS_V1) | |
86a0f043 AA |
5280 | np->register_size = NV_PCI_REGSZ_VER2; |
5281 | else | |
5282 | np->register_size = NV_PCI_REGSZ_VER1; | |
5283 | ||
1da177e4 LT |
5284 | err = -EINVAL; |
5285 | addr = 0; | |
5286 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1da177e4 | 5287 | if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && |
86a0f043 | 5288 | pci_resource_len(pci_dev, i) >= np->register_size) { |
1da177e4 LT |
5289 | addr = pci_resource_start(pci_dev, i); |
5290 | break; | |
5291 | } | |
5292 | } | |
5293 | if (i == DEVICE_COUNT_RESOURCE) { | |
b2ba08e6 | 5294 | dev_info(&pci_dev->dev, "Couldn't find register window\n"); |
1da177e4 LT |
5295 | goto out_relreg; |
5296 | } | |
5297 | ||
86a0f043 AA |
5298 | /* copy of driver data */ |
5299 | np->driver_data = id->driver_data; | |
9f3f7910 AA |
5300 | /* copy of device id */ |
5301 | np->device_id = id->device; | |
86a0f043 | 5302 | |
1da177e4 | 5303 | /* handle different descriptor versions */ |
ee73362c MS |
5304 | if (id->driver_data & DEV_HAS_HIGH_DMA) { |
5305 | /* packet format 3: supports 40-bit addressing */ | |
5306 | np->desc_ver = DESC_VER_3; | |
84b3932b | 5307 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; |
69fe3fd7 | 5308 | if (dma_64bit) { |
6afd142f | 5309 | if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39))) |
b2ba08e6 JP |
5310 | dev_info(&pci_dev->dev, |
5311 | "64-bit DMA failed, using 32-bit addressing\n"); | |
3f88ce49 | 5312 | else |
69fe3fd7 | 5313 | dev->features |= NETIF_F_HIGHDMA; |
6afd142f | 5314 | if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) { |
b2ba08e6 JP |
5315 | dev_info(&pci_dev->dev, |
5316 | "64-bit DMA (consistent) failed, using 32-bit ring buffers\n"); | |
69fe3fd7 | 5317 | } |
ee73362c MS |
5318 | } |
5319 | } else if (id->driver_data & DEV_HAS_LARGEDESC) { | |
5320 | /* packet format 2: supports jumbo frames */ | |
1da177e4 | 5321 | np->desc_ver = DESC_VER_2; |
8a4ae7f2 | 5322 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; |
ee73362c MS |
5323 | } else { |
5324 | /* original packet format */ | |
5325 | np->desc_ver = DESC_VER_1; | |
8a4ae7f2 | 5326 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; |
d81c0983 | 5327 | } |
ee73362c MS |
5328 | |
5329 | np->pkt_limit = NV_PKTLIMIT_1; | |
5330 | if (id->driver_data & DEV_HAS_LARGEDESC) | |
5331 | np->pkt_limit = NV_PKTLIMIT_2; | |
5332 | ||
8a4ae7f2 MS |
5333 | if (id->driver_data & DEV_HAS_CHECKSUM) { |
5334 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; | |
569e1463 MM |
5335 | dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | |
5336 | NETIF_F_TSO | NETIF_F_RXCSUM; | |
5337 | dev->features |= dev->hw_features; | |
21828163 | 5338 | } |
8a4ae7f2 | 5339 | |
ee407b02 AA |
5340 | np->vlanctl_bits = 0; |
5341 | if (id->driver_data & DEV_HAS_VLAN) { | |
5342 | np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; | |
5343 | dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; | |
ee407b02 AA |
5344 | } |
5345 | ||
b6d0773f | 5346 | np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG; |
5289b4c4 AA |
5347 | if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) || |
5348 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) || | |
5349 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) { | |
b6d0773f | 5350 | np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ; |
eb91f61b | 5351 | } |
f3b197ac | 5352 | |
1da177e4 | 5353 | err = -ENOMEM; |
86a0f043 | 5354 | np->base = ioremap(addr, np->register_size); |
1da177e4 LT |
5355 | if (!np->base) |
5356 | goto out_relreg; | |
5357 | dev->base_addr = (unsigned long)np->base; | |
ee73362c | 5358 | |
1da177e4 | 5359 | dev->irq = pci_dev->irq; |
ee73362c | 5360 | |
eafa59f6 AA |
5361 | np->rx_ring_size = RX_RING_DEFAULT; |
5362 | np->tx_ring_size = TX_RING_DEFAULT; | |
eafa59f6 | 5363 | |
36b30ea9 | 5364 | if (!nv_optimized(np)) { |
ee73362c | 5365 | np->rx_ring.orig = pci_alloc_consistent(pci_dev, |
eafa59f6 | 5366 | sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
5367 | &np->ring_addr); |
5368 | if (!np->rx_ring.orig) | |
5369 | goto out_unmap; | |
eafa59f6 | 5370 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
ee73362c MS |
5371 | } else { |
5372 | np->rx_ring.ex = pci_alloc_consistent(pci_dev, | |
eafa59f6 | 5373 | sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
5374 | &np->ring_addr); |
5375 | if (!np->rx_ring.ex) | |
5376 | goto out_unmap; | |
eafa59f6 AA |
5377 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
5378 | } | |
dd00cc48 YP |
5379 | np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); |
5380 | np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); | |
761fcd9e | 5381 | if (!np->rx_skb || !np->tx_skb) |
eafa59f6 | 5382 | goto out_freering; |
1da177e4 | 5383 | |
36b30ea9 | 5384 | if (!nv_optimized(np)) |
00829823 | 5385 | dev->netdev_ops = &nv_netdev_ops; |
86b22b0d | 5386 | else |
00829823 | 5387 | dev->netdev_ops = &nv_netdev_ops_optimized; |
b94426bd | 5388 | |
bea3348e | 5389 | netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP); |
1da177e4 | 5390 | SET_ETHTOOL_OPS(dev, &ops); |
1da177e4 LT |
5391 | dev->watchdog_timeo = NV_WATCHDOG_TIMEO; |
5392 | ||
5393 | pci_set_drvdata(pci_dev, dev); | |
5394 | ||
5395 | /* read the mac address */ | |
5396 | base = get_hwbase(dev); | |
5397 | np->orig_mac[0] = readl(base + NvRegMacAddrA); | |
5398 | np->orig_mac[1] = readl(base + NvRegMacAddrB); | |
5399 | ||
5070d340 AA |
5400 | /* check the workaround bit for correct mac address order */ |
5401 | txreg = readl(base + NvRegTransmitPoll); | |
a376e79c | 5402 | if (id->driver_data & DEV_HAS_CORRECT_MACADDR) { |
5070d340 AA |
5403 | /* mac address is already in correct order */ |
5404 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5405 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5406 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5407 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5408 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5409 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
a376e79c AA |
5410 | } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) { |
5411 | /* mac address is already in correct order */ | |
5412 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5413 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5414 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5415 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5416 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5417 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
5418 | /* | |
5419 | * Set orig mac address back to the reversed version. | |
5420 | * This flag will be cleared during low power transition. | |
5421 | * Therefore, we should always put back the reversed address. | |
5422 | */ | |
5423 | np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) + | |
5424 | (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24); | |
5425 | np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8); | |
5070d340 AA |
5426 | } else { |
5427 | /* need to reverse mac address to correct order */ | |
5428 | dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; | |
5429 | dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; | |
5430 | dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; | |
5431 | dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; | |
5432 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; | |
5433 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; | |
5070d340 | 5434 | writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
c20ec761 JP |
5435 | dev_dbg(&pci_dev->dev, |
5436 | "%s: set workaround bit for reversed mac addr\n", | |
5437 | __func__); | |
5070d340 | 5438 | } |
c704b856 | 5439 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 5440 | |
c704b856 | 5441 | if (!is_valid_ether_addr(dev->perm_addr)) { |
1da177e4 LT |
5442 | /* |
5443 | * Bad mac address. At least one bios sets the mac address | |
5444 | * to 01:23:45:67:89:ab | |
5445 | */ | |
b2ba08e6 | 5446 | dev_err(&pci_dev->dev, |
c20ec761 | 5447 | "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n", |
78aea4fc | 5448 | dev->dev_addr); |
655a6595 | 5449 | random_ether_addr(dev->dev_addr); |
c20ec761 JP |
5450 | dev_err(&pci_dev->dev, |
5451 | "Using random MAC address: %pM\n", dev->dev_addr); | |
1da177e4 LT |
5452 | } |
5453 | ||
f1489653 AA |
5454 | /* set mac address */ |
5455 | nv_copy_mac_to_hw(dev); | |
5456 | ||
1da177e4 LT |
5457 | /* disable WOL */ |
5458 | writel(0, base + NvRegWakeUpFlags); | |
5459 | np->wolenabled = 0; | |
dba5a68a | 5460 | device_set_wakeup_enable(&pci_dev->dev, false); |
1da177e4 | 5461 | |
86a0f043 | 5462 | if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
86a0f043 AA |
5463 | |
5464 | /* take phy and nic out of low power mode */ | |
5465 | powerstate = readl(base + NvRegPowerState2); | |
5466 | powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; | |
3c2e1c11 | 5467 | if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) && |
44c10138 | 5468 | pci_dev->revision >= 0xA3) |
86a0f043 AA |
5469 | powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; |
5470 | writel(powerstate, base + NvRegPowerState2); | |
5471 | } | |
5472 | ||
78aea4fc | 5473 | if (np->desc_ver == DESC_VER_1) |
ac9c1897 | 5474 | np->tx_flags = NV_TX_VALID; |
78aea4fc | 5475 | else |
ac9c1897 | 5476 | np->tx_flags = NV_TX2_VALID; |
9e184767 AA |
5477 | |
5478 | np->msi_flags = 0; | |
78aea4fc | 5479 | if ((id->driver_data & DEV_HAS_MSI) && msi) |
9e184767 | 5480 | np->msi_flags |= NV_MSI_CAPABLE; |
78aea4fc | 5481 | |
9e184767 AA |
5482 | if ((id->driver_data & DEV_HAS_MSI_X) && msix) { |
5483 | /* msix has had reported issues when modifying irqmask | |
5484 | as in the case of napi, therefore, disable for now | |
5485 | */ | |
0a12761b | 5486 | #if 0 |
9e184767 AA |
5487 | np->msi_flags |= NV_MSI_X_CAPABLE; |
5488 | #endif | |
5489 | } | |
5490 | ||
5491 | if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) { | |
a971c324 | 5492 | np->irqmask = NVREG_IRQMASK_CPU; |
d33a73c8 AA |
5493 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
5494 | np->msi_flags |= 0x0001; | |
9e184767 AA |
5495 | } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC && |
5496 | !(id->driver_data & DEV_NEED_TIMERIRQ)) { | |
5497 | /* start off in throughput mode */ | |
5498 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
5499 | /* remove support for msix mode */ | |
5500 | np->msi_flags &= ~NV_MSI_X_CAPABLE; | |
5501 | } else { | |
5502 | optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; | |
5503 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
5504 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ | |
5505 | np->msi_flags |= 0x0003; | |
d33a73c8 | 5506 | } |
a971c324 | 5507 | |
1da177e4 LT |
5508 | if (id->driver_data & DEV_NEED_TIMERIRQ) |
5509 | np->irqmask |= NVREG_IRQ_TIMER; | |
5510 | if (id->driver_data & DEV_NEED_LINKTIMER) { | |
1da177e4 LT |
5511 | np->need_linktimer = 1; |
5512 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
5513 | } else { | |
1da177e4 LT |
5514 | np->need_linktimer = 0; |
5515 | } | |
5516 | ||
3b446c3e AA |
5517 | /* Limit the number of tx's outstanding for hw bug */ |
5518 | if (id->driver_data & DEV_NEED_TX_LIMIT) { | |
5519 | np->tx_limit = 1; | |
5c659322 | 5520 | if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) && |
3b446c3e AA |
5521 | pci_dev->revision >= 0xA2) |
5522 | np->tx_limit = 0; | |
5523 | } | |
5524 | ||
7e680c22 AA |
5525 | /* clear phy state and temporarily halt phy interrupts */ |
5526 | writel(0, base + NvRegMIIMask); | |
5527 | phystate = readl(base + NvRegAdapterControl); | |
5528 | if (phystate & NVREG_ADAPTCTL_RUNNING) { | |
5529 | phystate_orig = 1; | |
5530 | phystate &= ~NVREG_ADAPTCTL_RUNNING; | |
5531 | writel(phystate, base + NvRegAdapterControl); | |
5532 | } | |
eb798428 | 5533 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
7e680c22 AA |
5534 | |
5535 | if (id->driver_data & DEV_HAS_MGMT_UNIT) { | |
7e680c22 | 5536 | /* management unit running on the mac? */ |
cac1c52c AA |
5537 | if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) && |
5538 | (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) && | |
5539 | nv_mgmt_acquire_sema(dev) && | |
5540 | nv_mgmt_get_version(dev)) { | |
5541 | np->mac_in_use = 1; | |
78aea4fc | 5542 | if (np->mgmt_version > 0) |
cac1c52c | 5543 | np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE; |
cac1c52c AA |
5544 | /* management unit setup the phy already? */ |
5545 | if (np->mac_in_use && | |
5546 | ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == | |
5547 | NVREG_XMITCTL_SYNC_PHY_INIT)) { | |
5548 | /* phy is inited by mgmt unit */ | |
5549 | phyinitialized = 1; | |
cac1c52c AA |
5550 | } else { |
5551 | /* we need to init the phy */ | |
7e680c22 AA |
5552 | } |
5553 | } | |
5554 | } | |
5555 | ||
1da177e4 | 5556 | /* find a suitable phy */ |
7a33e45a | 5557 | for (i = 1; i <= 32; i++) { |
1da177e4 | 5558 | int id1, id2; |
7a33e45a | 5559 | int phyaddr = i & 0x1F; |
1da177e4 LT |
5560 | |
5561 | spin_lock_irq(&np->lock); | |
7a33e45a | 5562 | id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); |
1da177e4 LT |
5563 | spin_unlock_irq(&np->lock); |
5564 | if (id1 < 0 || id1 == 0xffff) | |
5565 | continue; | |
5566 | spin_lock_irq(&np->lock); | |
7a33e45a | 5567 | id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); |
1da177e4 LT |
5568 | spin_unlock_irq(&np->lock); |
5569 | if (id2 < 0 || id2 == 0xffff) | |
5570 | continue; | |
5571 | ||
edf7e5ec | 5572 | np->phy_model = id2 & PHYID2_MODEL_MASK; |
1da177e4 LT |
5573 | id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
5574 | id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; | |
7a33e45a | 5575 | np->phyaddr = phyaddr; |
1da177e4 | 5576 | np->phy_oui = id1 | id2; |
9f3f7910 AA |
5577 | |
5578 | /* Realtek hardcoded phy id1 to all zero's on certain phys */ | |
5579 | if (np->phy_oui == PHY_OUI_REALTEK2) | |
5580 | np->phy_oui = PHY_OUI_REALTEK; | |
5581 | /* Setup phy revision for Realtek */ | |
5582 | if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211) | |
5583 | np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; | |
5584 | ||
1da177e4 LT |
5585 | break; |
5586 | } | |
7a33e45a | 5587 | if (i == 33) { |
b2ba08e6 | 5588 | dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n"); |
eafa59f6 | 5589 | goto out_error; |
1da177e4 | 5590 | } |
f3b197ac | 5591 | |
7e680c22 AA |
5592 | if (!phyinitialized) { |
5593 | /* reset it */ | |
5594 | phy_init(dev); | |
f35723ec AA |
5595 | } else { |
5596 | /* see if it is a gigabit phy */ | |
5597 | u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
78aea4fc | 5598 | if (mii_status & PHY_GIGABIT) |
f35723ec | 5599 | np->gigabit = PHY_GIGABIT; |
7e680c22 | 5600 | } |
1da177e4 LT |
5601 | |
5602 | /* set default link speed settings */ | |
5603 | np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
5604 | np->duplex = 0; | |
5605 | np->autoneg = 1; | |
5606 | ||
5607 | err = register_netdev(dev); | |
5608 | if (err) { | |
b2ba08e6 | 5609 | dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err); |
eafa59f6 | 5610 | goto out_error; |
1da177e4 | 5611 | } |
3f88ce49 | 5612 | |
0d672e9f IV |
5613 | netif_carrier_off(dev); |
5614 | ||
b2ba08e6 JP |
5615 | dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n", |
5616 | dev->name, np->phy_oui, np->phyaddr, dev->dev_addr); | |
5617 | ||
5618 | dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n", | |
5619 | dev->features & NETIF_F_HIGHDMA ? "highdma " : "", | |
5620 | dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ? | |
78aea4fc | 5621 | "csum " : "", |
b2ba08e6 | 5622 | dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ? |
78aea4fc | 5623 | "vlan " : "", |
b2ba08e6 JP |
5624 | id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "", |
5625 | id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "", | |
5626 | id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "", | |
5627 | np->gigabit == PHY_GIGABIT ? "gbit " : "", | |
5628 | np->need_linktimer ? "lnktim " : "", | |
5629 | np->msi_flags & NV_MSI_CAPABLE ? "msi " : "", | |
5630 | np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "", | |
5631 | np->desc_ver); | |
1da177e4 LT |
5632 | |
5633 | return 0; | |
5634 | ||
eafa59f6 | 5635 | out_error: |
7e680c22 AA |
5636 | if (phystate_orig) |
5637 | writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); | |
1da177e4 | 5638 | pci_set_drvdata(pci_dev, NULL); |
eafa59f6 AA |
5639 | out_freering: |
5640 | free_rings(dev); | |
1da177e4 LT |
5641 | out_unmap: |
5642 | iounmap(get_hwbase(dev)); | |
5643 | out_relreg: | |
5644 | pci_release_regions(pci_dev); | |
5645 | out_disable: | |
5646 | pci_disable_device(pci_dev); | |
5647 | out_free: | |
5648 | free_netdev(dev); | |
5649 | out: | |
5650 | return err; | |
5651 | } | |
5652 | ||
9f3f7910 AA |
5653 | static void nv_restore_phy(struct net_device *dev) |
5654 | { | |
5655 | struct fe_priv *np = netdev_priv(dev); | |
5656 | u16 phy_reserved, mii_control; | |
5657 | ||
5658 | if (np->phy_oui == PHY_OUI_REALTEK && | |
5659 | np->phy_model == PHY_MODEL_REALTEK_8201 && | |
5660 | phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | |
5661 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); | |
5662 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); | |
5663 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | |
5664 | phy_reserved |= PHY_REALTEK_INIT8; | |
5665 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); | |
5666 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); | |
5667 | ||
5668 | /* restart auto negotiation */ | |
5669 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
5670 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); | |
5671 | mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); | |
5672 | } | |
5673 | } | |
5674 | ||
f55c21fd | 5675 | static void nv_restore_mac_addr(struct pci_dev *pci_dev) |
1da177e4 LT |
5676 | { |
5677 | struct net_device *dev = pci_get_drvdata(pci_dev); | |
f1489653 AA |
5678 | struct fe_priv *np = netdev_priv(dev); |
5679 | u8 __iomem *base = get_hwbase(dev); | |
1da177e4 | 5680 | |
f1489653 AA |
5681 | /* special op: write back the misordered MAC address - otherwise |
5682 | * the next nv_probe would see a wrong address. | |
5683 | */ | |
5684 | writel(np->orig_mac[0], base + NvRegMacAddrA); | |
5685 | writel(np->orig_mac[1], base + NvRegMacAddrB); |