Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * forcedeth: Ethernet driver for NVIDIA nForce media access controllers. | |
3 | * | |
4 | * Note: This driver is a cleanroom reimplementation based on reverse | |
5 | * engineered documentation written by Carl-Daniel Hailfinger | |
87046e50 | 6 | * and Andrew de Quincey. |
1da177e4 LT |
7 | * |
8 | * NVIDIA, nForce and other NVIDIA marks are trademarks or registered | |
9 | * trademarks of NVIDIA Corporation in the United States and other | |
10 | * countries. | |
11 | * | |
1836098f | 12 | * Copyright (C) 2003,4,5 Manfred Spraul |
1da177e4 LT |
13 | * Copyright (C) 2004 Andrew de Quincey (wol support) |
14 | * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane | |
15 | * IRQ rate fixes, bigendian fixes, cleanups, verification) | |
87046e50 | 16 | * Copyright (c) 2004,5,6 NVIDIA Corporation |
1da177e4 LT |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
31 | * | |
32 | * Changelog: | |
33 | * 0.01: 05 Oct 2003: First release that compiles without warnings. | |
34 | * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs. | |
35 | * Check all PCI BARs for the register window. | |
36 | * udelay added to mii_rw. | |
37 | * 0.03: 06 Oct 2003: Initialize dev->irq. | |
38 | * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks. | |
39 | * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout. | |
40 | * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated, | |
41 | * irq mask updated | |
42 | * 0.07: 14 Oct 2003: Further irq mask updates. | |
43 | * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill | |
44 | * added into irq handler, NULL check for drain_ring. | |
45 | * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the | |
46 | * requested interrupt sources. | |
47 | * 0.10: 20 Oct 2003: First cleanup for release. | |
48 | * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased. | |
49 | * MAC Address init fix, set_multicast cleanup. | |
50 | * 0.12: 23 Oct 2003: Cleanups for release. | |
51 | * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10. | |
52 | * Set link speed correctly. start rx before starting | |
53 | * tx (nv_start_rx sets the link speed). | |
54 | * 0.14: 25 Oct 2003: Nic dependant irq mask. | |
55 | * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during | |
56 | * open. | |
57 | * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size | |
58 | * increased to 1628 bytes. | |
59 | * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from | |
60 | * the tx length. | |
61 | * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats | |
62 | * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac | |
63 | * addresses, really stop rx if already running | |
64 | * in nv_start_rx, clean up a bit. | |
65 | * 0.20: 07 Dec 2003: alloc fixes | |
66 | * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix. | |
67 | * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup | |
68 | * on close. | |
69 | * 0.23: 26 Jan 2004: various small cleanups | |
70 | * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces | |
71 | * 0.25: 09 Mar 2004: wol support | |
72 | * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes | |
73 | * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings, | |
74 | * added CK804/MCP04 device IDs, code fixes | |
75 | * for registers, link status and other minor fixes. | |
76 | * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe | |
77 | * 0.29: 31 Aug 2004: Add backup timer for link change notification. | |
78 | * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset | |
79 | * into nv_close, otherwise reenabling for wol can | |
80 | * cause DMA to kfree'd memory. | |
81 | * 0.31: 14 Nov 2004: ethtool support for getting/setting link | |
4ea7f299 | 82 | * capabilities. |
22c6d143 | 83 | * 0.32: 16 Apr 2005: RX_ERROR4 handling added. |
8f767fc8 MS |
84 | * 0.33: 16 May 2005: Support for MCP51 added. |
85 | * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics. | |
f49d16ef | 86 | * 0.35: 26 Jun 2005: Support for MCP55 added. |
dc8216c1 MS |
87 | * 0.36: 28 Jun 2005: Add jumbo frame support. |
88 | * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list | |
c2dba06d MS |
89 | * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of |
90 | * per-packet flags. | |
4ea7f299 AA |
91 | * 0.39: 18 Jul 2005: Add 64bit descriptor support. |
92 | * 0.40: 19 Jul 2005: Add support for mac address change. | |
93 | * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead | |
b3df9f81 | 94 | * of nv_remove |
4ea7f299 | 95 | * 0.42: 06 Aug 2005: Fix lack of link speed initialization |
1b1b3c9b | 96 | * in the second (and later) nv_open call |
4ea7f299 AA |
97 | * 0.43: 10 Aug 2005: Add support for tx checksum. |
98 | * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation. | |
99 | * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check | |
a971c324 | 100 | * 0.46: 20 Oct 2005: Add irq optimization modes. |
7a33e45a | 101 | * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan. |
1836098f | 102 | * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single |
fa45459e | 103 | * 0.49: 10 Dec 2005: Fix tso for large buffers. |
ee407b02 | 104 | * 0.50: 20 Jan 2006: Add 8021pq tagging support. |
0832b25a | 105 | * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings. |
d33a73c8 | 106 | * 0.52: 20 Jan 2006: Add MSI/MSIX support. |
86a0f043 | 107 | * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset. |
84b3932b | 108 | * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup. |
eb91f61b | 109 | * 0.55: 22 Mar 2006: Add flow control (pause frame). |
ebe611a4 | 110 | * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support. |
5070d340 | 111 | * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections. |
7e680c22 | 112 | * 0.58: 30 Oct 2006: Added support for sideband management unit. |
c5cf9101 | 113 | * 0.59: 30 Oct 2006: Added support for recoverable error. |
1da177e4 LT |
114 | * |
115 | * Known bugs: | |
116 | * We suspect that on some hardware no TX done interrupts are generated. | |
117 | * This means recovery from netif_stop_queue only happens if the hw timer | |
118 | * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) | |
119 | * and the timer is active in the IRQMask, or if a rx packet arrives by chance. | |
120 | * If your hardware reliably generates tx done interrupts, then you can remove | |
121 | * DEV_NEED_TIMERIRQ from the driver_data flags. | |
122 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few | |
123 | * superfluous timer interrupts from the nic. | |
124 | */ | |
e27cdba5 SH |
125 | #ifdef CONFIG_FORCEDETH_NAPI |
126 | #define DRIVERNAPI "-NAPI" | |
127 | #else | |
128 | #define DRIVERNAPI | |
129 | #endif | |
c5cf9101 | 130 | #define FORCEDETH_VERSION "0.59" |
1da177e4 LT |
131 | #define DRV_NAME "forcedeth" |
132 | ||
133 | #include <linux/module.h> | |
134 | #include <linux/types.h> | |
135 | #include <linux/pci.h> | |
136 | #include <linux/interrupt.h> | |
137 | #include <linux/netdevice.h> | |
138 | #include <linux/etherdevice.h> | |
139 | #include <linux/delay.h> | |
140 | #include <linux/spinlock.h> | |
141 | #include <linux/ethtool.h> | |
142 | #include <linux/timer.h> | |
143 | #include <linux/skbuff.h> | |
144 | #include <linux/mii.h> | |
145 | #include <linux/random.h> | |
146 | #include <linux/init.h> | |
22c6d143 | 147 | #include <linux/if_vlan.h> |
910638ae | 148 | #include <linux/dma-mapping.h> |
1da177e4 LT |
149 | |
150 | #include <asm/irq.h> | |
151 | #include <asm/io.h> | |
152 | #include <asm/uaccess.h> | |
153 | #include <asm/system.h> | |
154 | ||
155 | #if 0 | |
156 | #define dprintk printk | |
157 | #else | |
158 | #define dprintk(x...) do { } while (0) | |
159 | #endif | |
160 | ||
161 | ||
162 | /* | |
163 | * Hardware access: | |
164 | */ | |
165 | ||
c2dba06d MS |
166 | #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */ |
167 | #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */ | |
168 | #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */ | |
ee73362c | 169 | #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */ |
8a4ae7f2 | 170 | #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */ |
ee407b02 | 171 | #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */ |
d33a73c8 AA |
172 | #define DEV_HAS_MSI 0x0040 /* device supports MSI */ |
173 | #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */ | |
86a0f043 | 174 | #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */ |
eb91f61b | 175 | #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */ |
52da3578 | 176 | #define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */ |
9589c77a | 177 | #define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */ |
7e680c22 | 178 | #define DEV_HAS_MGMT_UNIT 0x1000 /* device supports management unit */ |
1da177e4 LT |
179 | |
180 | enum { | |
181 | NvRegIrqStatus = 0x000, | |
182 | #define NVREG_IRQSTAT_MIIEVENT 0x040 | |
c5cf9101 | 183 | #define NVREG_IRQSTAT_MASK 0x81ff |
1da177e4 LT |
184 | NvRegIrqMask = 0x004, |
185 | #define NVREG_IRQ_RX_ERROR 0x0001 | |
186 | #define NVREG_IRQ_RX 0x0002 | |
187 | #define NVREG_IRQ_RX_NOBUF 0x0004 | |
188 | #define NVREG_IRQ_TX_ERR 0x0008 | |
c2dba06d | 189 | #define NVREG_IRQ_TX_OK 0x0010 |
1da177e4 LT |
190 | #define NVREG_IRQ_TIMER 0x0020 |
191 | #define NVREG_IRQ_LINK 0x0040 | |
d33a73c8 AA |
192 | #define NVREG_IRQ_RX_FORCED 0x0080 |
193 | #define NVREG_IRQ_TX_FORCED 0x0100 | |
c5cf9101 | 194 | #define NVREG_IRQ_RECOVER_ERROR 0x8000 |
a971c324 AA |
195 | #define NVREG_IRQMASK_THROUGHPUT 0x00df |
196 | #define NVREG_IRQMASK_CPU 0x0040 | |
d33a73c8 AA |
197 | #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
198 | #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) | |
c5cf9101 | 199 | #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR) |
c2dba06d MS |
200 | |
201 | #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \ | |
d33a73c8 | 202 | NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \ |
c5cf9101 | 203 | NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR)) |
1da177e4 LT |
204 | |
205 | NvRegUnknownSetupReg6 = 0x008, | |
206 | #define NVREG_UNKSETUP6_VAL 3 | |
207 | ||
208 | /* | |
209 | * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic | |
210 | * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms | |
211 | */ | |
212 | NvRegPollingInterval = 0x00c, | |
a971c324 AA |
213 | #define NVREG_POLL_DEFAULT_THROUGHPUT 970 |
214 | #define NVREG_POLL_DEFAULT_CPU 13 | |
d33a73c8 AA |
215 | NvRegMSIMap0 = 0x020, |
216 | NvRegMSIMap1 = 0x024, | |
217 | NvRegMSIIrqMask = 0x030, | |
218 | #define NVREG_MSI_VECTOR_0_ENABLED 0x01 | |
1da177e4 | 219 | NvRegMisc1 = 0x080, |
eb91f61b | 220 | #define NVREG_MISC1_PAUSE_TX 0x01 |
1da177e4 LT |
221 | #define NVREG_MISC1_HD 0x02 |
222 | #define NVREG_MISC1_FORCE 0x3b0f3c | |
223 | ||
86a0f043 AA |
224 | NvRegMacReset = 0x3c, |
225 | #define NVREG_MAC_RESET_ASSERT 0x0F3 | |
1da177e4 LT |
226 | NvRegTransmitterControl = 0x084, |
227 | #define NVREG_XMITCTL_START 0x01 | |
7e680c22 AA |
228 | #define NVREG_XMITCTL_MGMT_ST 0x40000000 |
229 | #define NVREG_XMITCTL_SYNC_MASK 0x000f0000 | |
230 | #define NVREG_XMITCTL_SYNC_NOT_READY 0x0 | |
231 | #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000 | |
232 | #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00 | |
233 | #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0 | |
234 | #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000 | |
235 | #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000 | |
236 | #define NVREG_XMITCTL_HOST_LOADED 0x00004000 | |
f35723ec | 237 | #define NVREG_XMITCTL_TX_PATH_EN 0x01000000 |
1da177e4 LT |
238 | NvRegTransmitterStatus = 0x088, |
239 | #define NVREG_XMITSTAT_BUSY 0x01 | |
240 | ||
241 | NvRegPacketFilterFlags = 0x8c, | |
eb91f61b AA |
242 | #define NVREG_PFF_PAUSE_RX 0x08 |
243 | #define NVREG_PFF_ALWAYS 0x7F0000 | |
1da177e4 LT |
244 | #define NVREG_PFF_PROMISC 0x80 |
245 | #define NVREG_PFF_MYADDR 0x20 | |
9589c77a | 246 | #define NVREG_PFF_LOOPBACK 0x10 |
1da177e4 LT |
247 | |
248 | NvRegOffloadConfig = 0x90, | |
249 | #define NVREG_OFFLOAD_HOMEPHY 0x601 | |
250 | #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE | |
251 | NvRegReceiverControl = 0x094, | |
252 | #define NVREG_RCVCTL_START 0x01 | |
f35723ec | 253 | #define NVREG_RCVCTL_RX_PATH_EN 0x01000000 |
1da177e4 LT |
254 | NvRegReceiverStatus = 0x98, |
255 | #define NVREG_RCVSTAT_BUSY 0x01 | |
256 | ||
257 | NvRegRandomSeed = 0x9c, | |
258 | #define NVREG_RNDSEED_MASK 0x00ff | |
259 | #define NVREG_RNDSEED_FORCE 0x7f00 | |
260 | #define NVREG_RNDSEED_FORCE2 0x2d00 | |
261 | #define NVREG_RNDSEED_FORCE3 0x7400 | |
262 | ||
9744e218 AA |
263 | NvRegTxDeferral = 0xA0, |
264 | #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f | |
265 | #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f | |
266 | #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f | |
267 | NvRegRxDeferral = 0xA4, | |
268 | #define NVREG_RX_DEFERRAL_DEFAULT 0x16 | |
1da177e4 LT |
269 | NvRegMacAddrA = 0xA8, |
270 | NvRegMacAddrB = 0xAC, | |
271 | NvRegMulticastAddrA = 0xB0, | |
272 | #define NVREG_MCASTADDRA_FORCE 0x01 | |
273 | NvRegMulticastAddrB = 0xB4, | |
274 | NvRegMulticastMaskA = 0xB8, | |
275 | NvRegMulticastMaskB = 0xBC, | |
276 | ||
277 | NvRegPhyInterface = 0xC0, | |
278 | #define PHY_RGMII 0x10000000 | |
279 | ||
280 | NvRegTxRingPhysAddr = 0x100, | |
281 | NvRegRxRingPhysAddr = 0x104, | |
282 | NvRegRingSizes = 0x108, | |
283 | #define NVREG_RINGSZ_TXSHIFT 0 | |
284 | #define NVREG_RINGSZ_RXSHIFT 16 | |
5070d340 AA |
285 | NvRegTransmitPoll = 0x10c, |
286 | #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000 | |
1da177e4 LT |
287 | NvRegLinkSpeed = 0x110, |
288 | #define NVREG_LINKSPEED_FORCE 0x10000 | |
289 | #define NVREG_LINKSPEED_10 1000 | |
290 | #define NVREG_LINKSPEED_100 100 | |
291 | #define NVREG_LINKSPEED_1000 50 | |
292 | #define NVREG_LINKSPEED_MASK (0xFFF) | |
293 | NvRegUnknownSetupReg5 = 0x130, | |
294 | #define NVREG_UNKSETUP5_BIT31 (1<<31) | |
95d161cb AA |
295 | NvRegTxWatermark = 0x13c, |
296 | #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 | |
297 | #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000 | |
298 | #define NVREG_TX_WM_DESC2_3_1000 0xfe08000 | |
1da177e4 LT |
299 | NvRegTxRxControl = 0x144, |
300 | #define NVREG_TXRXCTL_KICK 0x0001 | |
301 | #define NVREG_TXRXCTL_BIT1 0x0002 | |
302 | #define NVREG_TXRXCTL_BIT2 0x0004 | |
303 | #define NVREG_TXRXCTL_IDLE 0x0008 | |
304 | #define NVREG_TXRXCTL_RESET 0x0010 | |
305 | #define NVREG_TXRXCTL_RXCHECK 0x0400 | |
8a4ae7f2 | 306 | #define NVREG_TXRXCTL_DESC_1 0 |
d2f78412 AA |
307 | #define NVREG_TXRXCTL_DESC_2 0x002100 |
308 | #define NVREG_TXRXCTL_DESC_3 0xc02200 | |
ee407b02 AA |
309 | #define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
310 | #define NVREG_TXRXCTL_VLANINS 0x00080 | |
0832b25a AA |
311 | NvRegTxRingPhysAddrHigh = 0x148, |
312 | NvRegRxRingPhysAddrHigh = 0x14C, | |
eb91f61b AA |
313 | NvRegTxPauseFrame = 0x170, |
314 | #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080 | |
315 | #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030 | |
1da177e4 LT |
316 | NvRegMIIStatus = 0x180, |
317 | #define NVREG_MIISTAT_ERROR 0x0001 | |
318 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 | |
319 | #define NVREG_MIISTAT_MASK 0x000f | |
320 | #define NVREG_MIISTAT_MASK2 0x000f | |
7e680c22 AA |
321 | NvRegMIIMask = 0x184, |
322 | #define NVREG_MII_LINKCHANGE 0x0008 | |
1da177e4 LT |
323 | |
324 | NvRegAdapterControl = 0x188, | |
325 | #define NVREG_ADAPTCTL_START 0x02 | |
326 | #define NVREG_ADAPTCTL_LINKUP 0x04 | |
327 | #define NVREG_ADAPTCTL_PHYVALID 0x40000 | |
328 | #define NVREG_ADAPTCTL_RUNNING 0x100000 | |
329 | #define NVREG_ADAPTCTL_PHYSHIFT 24 | |
330 | NvRegMIISpeed = 0x18c, | |
331 | #define NVREG_MIISPEED_BIT8 (1<<8) | |
332 | #define NVREG_MIIDELAY 5 | |
333 | NvRegMIIControl = 0x190, | |
334 | #define NVREG_MIICTL_INUSE 0x08000 | |
335 | #define NVREG_MIICTL_WRITE 0x00400 | |
336 | #define NVREG_MIICTL_ADDRSHIFT 5 | |
337 | NvRegMIIData = 0x194, | |
338 | NvRegWakeUpFlags = 0x200, | |
339 | #define NVREG_WAKEUPFLAGS_VAL 0x7770 | |
340 | #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 | |
341 | #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 | |
342 | #define NVREG_WAKEUPFLAGS_D3SHIFT 12 | |
343 | #define NVREG_WAKEUPFLAGS_D2SHIFT 8 | |
344 | #define NVREG_WAKEUPFLAGS_D1SHIFT 4 | |
345 | #define NVREG_WAKEUPFLAGS_D0SHIFT 0 | |
346 | #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 | |
347 | #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 | |
348 | #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 | |
349 | #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 | |
350 | ||
351 | NvRegPatternCRC = 0x204, | |
352 | NvRegPatternMask = 0x208, | |
353 | NvRegPowerCap = 0x268, | |
354 | #define NVREG_POWERCAP_D3SUPP (1<<30) | |
355 | #define NVREG_POWERCAP_D2SUPP (1<<26) | |
356 | #define NVREG_POWERCAP_D1SUPP (1<<25) | |
357 | NvRegPowerState = 0x26c, | |
358 | #define NVREG_POWERSTATE_POWEREDUP 0x8000 | |
359 | #define NVREG_POWERSTATE_VALID 0x0100 | |
360 | #define NVREG_POWERSTATE_MASK 0x0003 | |
361 | #define NVREG_POWERSTATE_D0 0x0000 | |
362 | #define NVREG_POWERSTATE_D1 0x0001 | |
363 | #define NVREG_POWERSTATE_D2 0x0002 | |
364 | #define NVREG_POWERSTATE_D3 0x0003 | |
52da3578 AA |
365 | NvRegTxCnt = 0x280, |
366 | NvRegTxZeroReXmt = 0x284, | |
367 | NvRegTxOneReXmt = 0x288, | |
368 | NvRegTxManyReXmt = 0x28c, | |
369 | NvRegTxLateCol = 0x290, | |
370 | NvRegTxUnderflow = 0x294, | |
371 | NvRegTxLossCarrier = 0x298, | |
372 | NvRegTxExcessDef = 0x29c, | |
373 | NvRegTxRetryErr = 0x2a0, | |
374 | NvRegRxFrameErr = 0x2a4, | |
375 | NvRegRxExtraByte = 0x2a8, | |
376 | NvRegRxLateCol = 0x2ac, | |
377 | NvRegRxRunt = 0x2b0, | |
378 | NvRegRxFrameTooLong = 0x2b4, | |
379 | NvRegRxOverflow = 0x2b8, | |
380 | NvRegRxFCSErr = 0x2bc, | |
381 | NvRegRxFrameAlignErr = 0x2c0, | |
382 | NvRegRxLenErr = 0x2c4, | |
383 | NvRegRxUnicast = 0x2c8, | |
384 | NvRegRxMulticast = 0x2cc, | |
385 | NvRegRxBroadcast = 0x2d0, | |
386 | NvRegTxDef = 0x2d4, | |
387 | NvRegTxFrame = 0x2d8, | |
388 | NvRegRxCnt = 0x2dc, | |
389 | NvRegTxPause = 0x2e0, | |
390 | NvRegRxPause = 0x2e4, | |
391 | NvRegRxDropFrame = 0x2e8, | |
ee407b02 AA |
392 | NvRegVlanControl = 0x300, |
393 | #define NVREG_VLANCONTROL_ENABLE 0x2000 | |
d33a73c8 AA |
394 | NvRegMSIXMap0 = 0x3e0, |
395 | NvRegMSIXMap1 = 0x3e4, | |
396 | NvRegMSIXIrqStatus = 0x3f0, | |
86a0f043 AA |
397 | |
398 | NvRegPowerState2 = 0x600, | |
399 | #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11 | |
400 | #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 | |
1da177e4 LT |
401 | }; |
402 | ||
403 | /* Big endian: should work, but is untested */ | |
404 | struct ring_desc { | |
a8bed49e SH |
405 | __le32 buf; |
406 | __le32 flaglen; | |
1da177e4 LT |
407 | }; |
408 | ||
ee73362c | 409 | struct ring_desc_ex { |
a8bed49e SH |
410 | __le32 bufhigh; |
411 | __le32 buflow; | |
412 | __le32 txvlan; | |
413 | __le32 flaglen; | |
ee73362c MS |
414 | }; |
415 | ||
f82a9352 | 416 | union ring_type { |
ee73362c MS |
417 | struct ring_desc* orig; |
418 | struct ring_desc_ex* ex; | |
f82a9352 | 419 | }; |
ee73362c | 420 | |
1da177e4 LT |
421 | #define FLAG_MASK_V1 0xffff0000 |
422 | #define FLAG_MASK_V2 0xffffc000 | |
423 | #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) | |
424 | #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) | |
425 | ||
426 | #define NV_TX_LASTPACKET (1<<16) | |
427 | #define NV_TX_RETRYERROR (1<<19) | |
c2dba06d | 428 | #define NV_TX_FORCED_INTERRUPT (1<<24) |
1da177e4 LT |
429 | #define NV_TX_DEFERRED (1<<26) |
430 | #define NV_TX_CARRIERLOST (1<<27) | |
431 | #define NV_TX_LATECOLLISION (1<<28) | |
432 | #define NV_TX_UNDERFLOW (1<<29) | |
433 | #define NV_TX_ERROR (1<<30) | |
434 | #define NV_TX_VALID (1<<31) | |
435 | ||
436 | #define NV_TX2_LASTPACKET (1<<29) | |
437 | #define NV_TX2_RETRYERROR (1<<18) | |
c2dba06d | 438 | #define NV_TX2_FORCED_INTERRUPT (1<<30) |
1da177e4 LT |
439 | #define NV_TX2_DEFERRED (1<<25) |
440 | #define NV_TX2_CARRIERLOST (1<<26) | |
441 | #define NV_TX2_LATECOLLISION (1<<27) | |
442 | #define NV_TX2_UNDERFLOW (1<<28) | |
443 | /* error and valid are the same for both */ | |
444 | #define NV_TX2_ERROR (1<<30) | |
445 | #define NV_TX2_VALID (1<<31) | |
ac9c1897 AA |
446 | #define NV_TX2_TSO (1<<28) |
447 | #define NV_TX2_TSO_SHIFT 14 | |
fa45459e AA |
448 | #define NV_TX2_TSO_MAX_SHIFT 14 |
449 | #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT) | |
8a4ae7f2 MS |
450 | #define NV_TX2_CHECKSUM_L3 (1<<27) |
451 | #define NV_TX2_CHECKSUM_L4 (1<<26) | |
1da177e4 | 452 | |
ee407b02 AA |
453 | #define NV_TX3_VLAN_TAG_PRESENT (1<<18) |
454 | ||
1da177e4 LT |
455 | #define NV_RX_DESCRIPTORVALID (1<<16) |
456 | #define NV_RX_MISSEDFRAME (1<<17) | |
457 | #define NV_RX_SUBSTRACT1 (1<<18) | |
458 | #define NV_RX_ERROR1 (1<<23) | |
459 | #define NV_RX_ERROR2 (1<<24) | |
460 | #define NV_RX_ERROR3 (1<<25) | |
461 | #define NV_RX_ERROR4 (1<<26) | |
462 | #define NV_RX_CRCERR (1<<27) | |
463 | #define NV_RX_OVERFLOW (1<<28) | |
464 | #define NV_RX_FRAMINGERR (1<<29) | |
465 | #define NV_RX_ERROR (1<<30) | |
466 | #define NV_RX_AVAIL (1<<31) | |
467 | ||
468 | #define NV_RX2_CHECKSUMMASK (0x1C000000) | |
469 | #define NV_RX2_CHECKSUMOK1 (0x10000000) | |
470 | #define NV_RX2_CHECKSUMOK2 (0x14000000) | |
471 | #define NV_RX2_CHECKSUMOK3 (0x18000000) | |
472 | #define NV_RX2_DESCRIPTORVALID (1<<29) | |
473 | #define NV_RX2_SUBSTRACT1 (1<<25) | |
474 | #define NV_RX2_ERROR1 (1<<18) | |
475 | #define NV_RX2_ERROR2 (1<<19) | |
476 | #define NV_RX2_ERROR3 (1<<20) | |
477 | #define NV_RX2_ERROR4 (1<<21) | |
478 | #define NV_RX2_CRCERR (1<<22) | |
479 | #define NV_RX2_OVERFLOW (1<<23) | |
480 | #define NV_RX2_FRAMINGERR (1<<24) | |
481 | /* error and avail are the same for both */ | |
482 | #define NV_RX2_ERROR (1<<30) | |
483 | #define NV_RX2_AVAIL (1<<31) | |
484 | ||
ee407b02 AA |
485 | #define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
486 | #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) | |
487 | ||
1da177e4 | 488 | /* Miscelaneous hardware related defines: */ |
86a0f043 AA |
489 | #define NV_PCI_REGSZ_VER1 0x270 |
490 | #define NV_PCI_REGSZ_VER2 0x604 | |
1da177e4 LT |
491 | |
492 | /* various timeout delays: all in usec */ | |
493 | #define NV_TXRX_RESET_DELAY 4 | |
494 | #define NV_TXSTOP_DELAY1 10 | |
495 | #define NV_TXSTOP_DELAY1MAX 500000 | |
496 | #define NV_TXSTOP_DELAY2 100 | |
497 | #define NV_RXSTOP_DELAY1 10 | |
498 | #define NV_RXSTOP_DELAY1MAX 500000 | |
499 | #define NV_RXSTOP_DELAY2 100 | |
500 | #define NV_SETUP5_DELAY 5 | |
501 | #define NV_SETUP5_DELAYMAX 50000 | |
502 | #define NV_POWERUP_DELAY 5 | |
503 | #define NV_POWERUP_DELAYMAX 5000 | |
504 | #define NV_MIIBUSY_DELAY 50 | |
505 | #define NV_MIIPHY_DELAY 10 | |
506 | #define NV_MIIPHY_DELAYMAX 10000 | |
86a0f043 | 507 | #define NV_MAC_RESET_DELAY 64 |
1da177e4 LT |
508 | |
509 | #define NV_WAKEUPPATTERNS 5 | |
510 | #define NV_WAKEUPMASKENTRIES 4 | |
511 | ||
512 | /* General driver defaults */ | |
513 | #define NV_WATCHDOG_TIMEO (5*HZ) | |
514 | ||
eafa59f6 AA |
515 | #define RX_RING_DEFAULT 128 |
516 | #define TX_RING_DEFAULT 256 | |
517 | #define RX_RING_MIN 128 | |
518 | #define TX_RING_MIN 64 | |
519 | #define RING_MAX_DESC_VER_1 1024 | |
520 | #define RING_MAX_DESC_VER_2_3 16384 | |
1da177e4 LT |
521 | |
522 | /* rx/tx mac addr + type + vlan + align + slack*/ | |
d81c0983 MS |
523 | #define NV_RX_HEADERS (64) |
524 | /* even more slack. */ | |
525 | #define NV_RX_ALLOC_PAD (64) | |
526 | ||
527 | /* maximum mtu size */ | |
528 | #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */ | |
529 | #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */ | |
1da177e4 LT |
530 | |
531 | #define OOM_REFILL (1+HZ/20) | |
532 | #define POLL_WAIT (1+HZ/100) | |
533 | #define LINK_TIMEOUT (3*HZ) | |
52da3578 | 534 | #define STATS_INTERVAL (10*HZ) |
1da177e4 | 535 | |
f3b197ac | 536 | /* |
1da177e4 | 537 | * desc_ver values: |
8a4ae7f2 MS |
538 | * The nic supports three different descriptor types: |
539 | * - DESC_VER_1: Original | |
540 | * - DESC_VER_2: support for jumbo frames. | |
541 | * - DESC_VER_3: 64-bit format. | |
1da177e4 | 542 | */ |
8a4ae7f2 MS |
543 | #define DESC_VER_1 1 |
544 | #define DESC_VER_2 2 | |
545 | #define DESC_VER_3 3 | |
1da177e4 LT |
546 | |
547 | /* PHY defines */ | |
548 | #define PHY_OUI_MARVELL 0x5043 | |
549 | #define PHY_OUI_CICADA 0x03f1 | |
550 | #define PHYID1_OUI_MASK 0x03ff | |
551 | #define PHYID1_OUI_SHFT 6 | |
552 | #define PHYID2_OUI_MASK 0xfc00 | |
553 | #define PHYID2_OUI_SHFT 10 | |
edf7e5ec AA |
554 | #define PHYID2_MODEL_MASK 0x03f0 |
555 | #define PHY_MODEL_MARVELL_E3016 0x220 | |
556 | #define PHY_MARVELL_E3016_INITMASK 0x0300 | |
1da177e4 LT |
557 | #define PHY_INIT1 0x0f000 |
558 | #define PHY_INIT2 0x0e00 | |
559 | #define PHY_INIT3 0x01000 | |
560 | #define PHY_INIT4 0x0200 | |
561 | #define PHY_INIT5 0x0004 | |
562 | #define PHY_INIT6 0x02000 | |
563 | #define PHY_GIGABIT 0x0100 | |
564 | ||
565 | #define PHY_TIMEOUT 0x1 | |
566 | #define PHY_ERROR 0x2 | |
567 | ||
568 | #define PHY_100 0x1 | |
569 | #define PHY_1000 0x2 | |
570 | #define PHY_HALF 0x100 | |
571 | ||
eb91f61b AA |
572 | #define NV_PAUSEFRAME_RX_CAPABLE 0x0001 |
573 | #define NV_PAUSEFRAME_TX_CAPABLE 0x0002 | |
574 | #define NV_PAUSEFRAME_RX_ENABLE 0x0004 | |
575 | #define NV_PAUSEFRAME_TX_ENABLE 0x0008 | |
b6d0773f AA |
576 | #define NV_PAUSEFRAME_RX_REQ 0x0010 |
577 | #define NV_PAUSEFRAME_TX_REQ 0x0020 | |
578 | #define NV_PAUSEFRAME_AUTONEG 0x0040 | |
1da177e4 | 579 | |
d33a73c8 AA |
580 | /* MSI/MSI-X defines */ |
581 | #define NV_MSI_X_MAX_VECTORS 8 | |
582 | #define NV_MSI_X_VECTORS_MASK 0x000f | |
583 | #define NV_MSI_CAPABLE 0x0010 | |
584 | #define NV_MSI_X_CAPABLE 0x0020 | |
585 | #define NV_MSI_ENABLED 0x0040 | |
586 | #define NV_MSI_X_ENABLED 0x0080 | |
587 | ||
588 | #define NV_MSI_X_VECTOR_ALL 0x0 | |
589 | #define NV_MSI_X_VECTOR_RX 0x0 | |
590 | #define NV_MSI_X_VECTOR_TX 0x1 | |
591 | #define NV_MSI_X_VECTOR_OTHER 0x2 | |
1da177e4 | 592 | |
52da3578 AA |
593 | /* statistics */ |
594 | struct nv_ethtool_str { | |
595 | char name[ETH_GSTRING_LEN]; | |
596 | }; | |
597 | ||
598 | static const struct nv_ethtool_str nv_estats_str[] = { | |
599 | { "tx_bytes" }, | |
600 | { "tx_zero_rexmt" }, | |
601 | { "tx_one_rexmt" }, | |
602 | { "tx_many_rexmt" }, | |
603 | { "tx_late_collision" }, | |
604 | { "tx_fifo_errors" }, | |
605 | { "tx_carrier_errors" }, | |
606 | { "tx_excess_deferral" }, | |
607 | { "tx_retry_error" }, | |
608 | { "tx_deferral" }, | |
609 | { "tx_packets" }, | |
610 | { "tx_pause" }, | |
611 | { "rx_frame_error" }, | |
612 | { "rx_extra_byte" }, | |
613 | { "rx_late_collision" }, | |
614 | { "rx_runt" }, | |
615 | { "rx_frame_too_long" }, | |
616 | { "rx_over_errors" }, | |
617 | { "rx_crc_errors" }, | |
618 | { "rx_frame_align_error" }, | |
619 | { "rx_length_error" }, | |
620 | { "rx_unicast" }, | |
621 | { "rx_multicast" }, | |
622 | { "rx_broadcast" }, | |
623 | { "rx_bytes" }, | |
624 | { "rx_pause" }, | |
625 | { "rx_drop_frame" }, | |
626 | { "rx_packets" }, | |
627 | { "rx_errors_total" } | |
628 | }; | |
629 | ||
630 | struct nv_ethtool_stats { | |
631 | u64 tx_bytes; | |
632 | u64 tx_zero_rexmt; | |
633 | u64 tx_one_rexmt; | |
634 | u64 tx_many_rexmt; | |
635 | u64 tx_late_collision; | |
636 | u64 tx_fifo_errors; | |
637 | u64 tx_carrier_errors; | |
638 | u64 tx_excess_deferral; | |
639 | u64 tx_retry_error; | |
640 | u64 tx_deferral; | |
641 | u64 tx_packets; | |
642 | u64 tx_pause; | |
643 | u64 rx_frame_error; | |
644 | u64 rx_extra_byte; | |
645 | u64 rx_late_collision; | |
646 | u64 rx_runt; | |
647 | u64 rx_frame_too_long; | |
648 | u64 rx_over_errors; | |
649 | u64 rx_crc_errors; | |
650 | u64 rx_frame_align_error; | |
651 | u64 rx_length_error; | |
652 | u64 rx_unicast; | |
653 | u64 rx_multicast; | |
654 | u64 rx_broadcast; | |
655 | u64 rx_bytes; | |
656 | u64 rx_pause; | |
657 | u64 rx_drop_frame; | |
658 | u64 rx_packets; | |
659 | u64 rx_errors_total; | |
660 | }; | |
661 | ||
9589c77a AA |
662 | /* diagnostics */ |
663 | #define NV_TEST_COUNT_BASE 3 | |
664 | #define NV_TEST_COUNT_EXTENDED 4 | |
665 | ||
666 | static const struct nv_ethtool_str nv_etests_str[] = { | |
667 | { "link (online/offline)" }, | |
668 | { "register (offline) " }, | |
669 | { "interrupt (offline) " }, | |
670 | { "loopback (offline) " } | |
671 | }; | |
672 | ||
673 | struct register_test { | |
a8bed49e SH |
674 | __le32 reg; |
675 | __le32 mask; | |
9589c77a AA |
676 | }; |
677 | ||
678 | static const struct register_test nv_registers_test[] = { | |
679 | { NvRegUnknownSetupReg6, 0x01 }, | |
680 | { NvRegMisc1, 0x03c }, | |
681 | { NvRegOffloadConfig, 0x03ff }, | |
682 | { NvRegMulticastAddrA, 0xffffffff }, | |
95d161cb | 683 | { NvRegTxWatermark, 0x0ff }, |
9589c77a AA |
684 | { NvRegWakeUpFlags, 0x07777 }, |
685 | { 0,0 } | |
686 | }; | |
687 | ||
761fcd9e AA |
688 | struct nv_skb_map { |
689 | struct sk_buff *skb; | |
690 | dma_addr_t dma; | |
691 | unsigned int dma_len; | |
692 | }; | |
693 | ||
1da177e4 LT |
694 | /* |
695 | * SMP locking: | |
696 | * All hardware access under dev->priv->lock, except the performance | |
697 | * critical parts: | |
698 | * - rx is (pseudo-) lockless: it relies on the single-threading provided | |
699 | * by the arch code for interrupts. | |
932ff279 | 700 | * - tx setup is lockless: it relies on netif_tx_lock. Actual submission |
1da177e4 | 701 | * needs dev->priv->lock :-( |
932ff279 | 702 | * - set_multicast_list: preparation lockless, relies on netif_tx_lock. |
1da177e4 LT |
703 | */ |
704 | ||
705 | /* in dev: base, irq */ | |
706 | struct fe_priv { | |
707 | spinlock_t lock; | |
708 | ||
709 | /* General data: | |
710 | * Locking: spin_lock(&np->lock); */ | |
711 | struct net_device_stats stats; | |
52da3578 | 712 | struct nv_ethtool_stats estats; |
1da177e4 LT |
713 | int in_shutdown; |
714 | u32 linkspeed; | |
715 | int duplex; | |
716 | int autoneg; | |
717 | int fixed_mode; | |
718 | int phyaddr; | |
719 | int wolenabled; | |
720 | unsigned int phy_oui; | |
edf7e5ec | 721 | unsigned int phy_model; |
1da177e4 | 722 | u16 gigabit; |
9589c77a | 723 | int intr_test; |
c5cf9101 | 724 | int recover_error; |
1da177e4 LT |
725 | |
726 | /* General data: RO fields */ | |
727 | dma_addr_t ring_addr; | |
728 | struct pci_dev *pci_dev; | |
729 | u32 orig_mac[2]; | |
730 | u32 irqmask; | |
731 | u32 desc_ver; | |
8a4ae7f2 | 732 | u32 txrxctl_bits; |
ee407b02 | 733 | u32 vlanctl_bits; |
86a0f043 AA |
734 | u32 driver_data; |
735 | u32 register_size; | |
f2ad2d9b | 736 | int rx_csum; |
7e680c22 | 737 | u32 mac_in_use; |
1da177e4 LT |
738 | |
739 | void __iomem *base; | |
740 | ||
741 | /* rx specific fields. | |
742 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
743 | */ | |
761fcd9e AA |
744 | union ring_type get_rx, put_rx, first_rx, last_rx; |
745 | struct nv_skb_map *get_rx_ctx, *put_rx_ctx; | |
746 | struct nv_skb_map *first_rx_ctx, *last_rx_ctx; | |
747 | struct nv_skb_map *rx_skb; | |
748 | ||
f82a9352 | 749 | union ring_type rx_ring; |
1da177e4 | 750 | unsigned int rx_buf_sz; |
d81c0983 | 751 | unsigned int pkt_limit; |
1da177e4 LT |
752 | struct timer_list oom_kick; |
753 | struct timer_list nic_poll; | |
52da3578 | 754 | struct timer_list stats_poll; |
d33a73c8 | 755 | u32 nic_poll_irq; |
eafa59f6 | 756 | int rx_ring_size; |
1da177e4 LT |
757 | |
758 | /* media detection workaround. | |
759 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
760 | */ | |
761 | int need_linktimer; | |
762 | unsigned long link_timeout; | |
763 | /* | |
764 | * tx specific fields. | |
765 | */ | |
761fcd9e AA |
766 | union ring_type get_tx, put_tx, first_tx, last_tx; |
767 | struct nv_skb_map *get_tx_ctx, *put_tx_ctx; | |
768 | struct nv_skb_map *first_tx_ctx, *last_tx_ctx; | |
769 | struct nv_skb_map *tx_skb; | |
770 | ||
f82a9352 | 771 | union ring_type tx_ring; |
1da177e4 | 772 | u32 tx_flags; |
eafa59f6 | 773 | int tx_ring_size; |
aaa37d2d | 774 | int tx_stop; |
ee407b02 AA |
775 | |
776 | /* vlan fields */ | |
777 | struct vlan_group *vlangrp; | |
d33a73c8 AA |
778 | |
779 | /* msi/msi-x fields */ | |
780 | u32 msi_flags; | |
781 | struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; | |
eb91f61b AA |
782 | |
783 | /* flow control */ | |
784 | u32 pause_flags; | |
1da177e4 LT |
785 | }; |
786 | ||
787 | /* | |
788 | * Maximum number of loops until we assume that a bit in the irq mask | |
789 | * is stuck. Overridable with module param. | |
790 | */ | |
791 | static int max_interrupt_work = 5; | |
792 | ||
a971c324 AA |
793 | /* |
794 | * Optimization can be either throuput mode or cpu mode | |
f3b197ac | 795 | * |
a971c324 AA |
796 | * Throughput Mode: Every tx and rx packet will generate an interrupt. |
797 | * CPU Mode: Interrupts are controlled by a timer. | |
798 | */ | |
69fe3fd7 AA |
799 | enum { |
800 | NV_OPTIMIZATION_MODE_THROUGHPUT, | |
801 | NV_OPTIMIZATION_MODE_CPU | |
802 | }; | |
a971c324 AA |
803 | static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; |
804 | ||
805 | /* | |
806 | * Poll interval for timer irq | |
807 | * | |
808 | * This interval determines how frequent an interrupt is generated. | |
809 | * The is value is determined by [(time_in_micro_secs * 100) / (2^10)] | |
810 | * Min = 0, and Max = 65535 | |
811 | */ | |
812 | static int poll_interval = -1; | |
813 | ||
d33a73c8 | 814 | /* |
69fe3fd7 | 815 | * MSI interrupts |
d33a73c8 | 816 | */ |
69fe3fd7 AA |
817 | enum { |
818 | NV_MSI_INT_DISABLED, | |
819 | NV_MSI_INT_ENABLED | |
820 | }; | |
821 | static int msi = NV_MSI_INT_ENABLED; | |
d33a73c8 AA |
822 | |
823 | /* | |
69fe3fd7 | 824 | * MSIX interrupts |
d33a73c8 | 825 | */ |
69fe3fd7 AA |
826 | enum { |
827 | NV_MSIX_INT_DISABLED, | |
828 | NV_MSIX_INT_ENABLED | |
829 | }; | |
830 | static int msix = NV_MSIX_INT_ENABLED; | |
831 | ||
832 | /* | |
833 | * DMA 64bit | |
834 | */ | |
835 | enum { | |
836 | NV_DMA_64BIT_DISABLED, | |
837 | NV_DMA_64BIT_ENABLED | |
838 | }; | |
839 | static int dma_64bit = NV_DMA_64BIT_ENABLED; | |
d33a73c8 | 840 | |
1da177e4 LT |
841 | static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
842 | { | |
843 | return netdev_priv(dev); | |
844 | } | |
845 | ||
846 | static inline u8 __iomem *get_hwbase(struct net_device *dev) | |
847 | { | |
ac9c1897 | 848 | return ((struct fe_priv *)netdev_priv(dev))->base; |
1da177e4 LT |
849 | } |
850 | ||
851 | static inline void pci_push(u8 __iomem *base) | |
852 | { | |
853 | /* force out pending posted writes */ | |
854 | readl(base); | |
855 | } | |
856 | ||
857 | static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) | |
858 | { | |
f82a9352 | 859 | return le32_to_cpu(prd->flaglen) |
1da177e4 LT |
860 | & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); |
861 | } | |
862 | ||
ee73362c MS |
863 | static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v) |
864 | { | |
f82a9352 | 865 | return le32_to_cpu(prd->flaglen) & LEN_MASK_V2; |
ee73362c MS |
866 | } |
867 | ||
1da177e4 LT |
868 | static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
869 | int delay, int delaymax, const char *msg) | |
870 | { | |
871 | u8 __iomem *base = get_hwbase(dev); | |
872 | ||
873 | pci_push(base); | |
874 | do { | |
875 | udelay(delay); | |
876 | delaymax -= delay; | |
877 | if (delaymax < 0) { | |
878 | if (msg) | |
879 | printk(msg); | |
880 | return 1; | |
881 | } | |
882 | } while ((readl(base + offset) & mask) != target); | |
883 | return 0; | |
884 | } | |
885 | ||
0832b25a AA |
886 | #define NV_SETUP_RX_RING 0x01 |
887 | #define NV_SETUP_TX_RING 0x02 | |
888 | ||
889 | static void setup_hw_rings(struct net_device *dev, int rxtx_flags) | |
890 | { | |
891 | struct fe_priv *np = get_nvpriv(dev); | |
892 | u8 __iomem *base = get_hwbase(dev); | |
893 | ||
894 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { | |
895 | if (rxtx_flags & NV_SETUP_RX_RING) { | |
896 | writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr); | |
897 | } | |
898 | if (rxtx_flags & NV_SETUP_TX_RING) { | |
eafa59f6 | 899 | writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
0832b25a AA |
900 | } |
901 | } else { | |
902 | if (rxtx_flags & NV_SETUP_RX_RING) { | |
903 | writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr); | |
904 | writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh); | |
905 | } | |
906 | if (rxtx_flags & NV_SETUP_TX_RING) { | |
eafa59f6 AA |
907 | writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr); |
908 | writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh); | |
0832b25a AA |
909 | } |
910 | } | |
911 | } | |
912 | ||
eafa59f6 AA |
913 | static void free_rings(struct net_device *dev) |
914 | { | |
915 | struct fe_priv *np = get_nvpriv(dev); | |
916 | ||
917 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { | |
f82a9352 | 918 | if (np->rx_ring.orig) |
eafa59f6 AA |
919 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
920 | np->rx_ring.orig, np->ring_addr); | |
921 | } else { | |
922 | if (np->rx_ring.ex) | |
923 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), | |
924 | np->rx_ring.ex, np->ring_addr); | |
925 | } | |
761fcd9e AA |
926 | if (np->rx_skb) |
927 | kfree(np->rx_skb); | |
928 | if (np->tx_skb) | |
929 | kfree(np->tx_skb); | |
eafa59f6 AA |
930 | } |
931 | ||
84b3932b AA |
932 | static int using_multi_irqs(struct net_device *dev) |
933 | { | |
934 | struct fe_priv *np = get_nvpriv(dev); | |
935 | ||
936 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || | |
937 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
938 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) | |
939 | return 0; | |
940 | else | |
941 | return 1; | |
942 | } | |
943 | ||
944 | static void nv_enable_irq(struct net_device *dev) | |
945 | { | |
946 | struct fe_priv *np = get_nvpriv(dev); | |
947 | ||
948 | if (!using_multi_irqs(dev)) { | |
949 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
950 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
951 | else | |
952 | enable_irq(dev->irq); | |
953 | } else { | |
954 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
955 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
956 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
957 | } | |
958 | } | |
959 | ||
960 | static void nv_disable_irq(struct net_device *dev) | |
961 | { | |
962 | struct fe_priv *np = get_nvpriv(dev); | |
963 | ||
964 | if (!using_multi_irqs(dev)) { | |
965 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
966 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
967 | else | |
968 | disable_irq(dev->irq); | |
969 | } else { | |
970 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
971 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
972 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
973 | } | |
974 | } | |
975 | ||
976 | /* In MSIX mode, a write to irqmask behaves as XOR */ | |
977 | static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask) | |
978 | { | |
979 | u8 __iomem *base = get_hwbase(dev); | |
980 | ||
981 | writel(mask, base + NvRegIrqMask); | |
982 | } | |
983 | ||
984 | static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask) | |
985 | { | |
986 | struct fe_priv *np = get_nvpriv(dev); | |
987 | u8 __iomem *base = get_hwbase(dev); | |
988 | ||
989 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
990 | writel(mask, base + NvRegIrqMask); | |
991 | } else { | |
992 | if (np->msi_flags & NV_MSI_ENABLED) | |
993 | writel(0, base + NvRegMSIIrqMask); | |
994 | writel(0, base + NvRegIrqMask); | |
995 | } | |
996 | } | |
997 | ||
1da177e4 LT |
998 | #define MII_READ (-1) |
999 | /* mii_rw: read/write a register on the PHY. | |
1000 | * | |
1001 | * Caller must guarantee serialization | |
1002 | */ | |
1003 | static int mii_rw(struct net_device *dev, int addr, int miireg, int value) | |
1004 | { | |
1005 | u8 __iomem *base = get_hwbase(dev); | |
1006 | u32 reg; | |
1007 | int retval; | |
1008 | ||
1009 | writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); | |
1010 | ||
1011 | reg = readl(base + NvRegMIIControl); | |
1012 | if (reg & NVREG_MIICTL_INUSE) { | |
1013 | writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); | |
1014 | udelay(NV_MIIBUSY_DELAY); | |
1015 | } | |
1016 | ||
1017 | reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; | |
1018 | if (value != MII_READ) { | |
1019 | writel(value, base + NvRegMIIData); | |
1020 | reg |= NVREG_MIICTL_WRITE; | |
1021 | } | |
1022 | writel(reg, base + NvRegMIIControl); | |
1023 | ||
1024 | if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, | |
1025 | NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) { | |
1026 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n", | |
1027 | dev->name, miireg, addr); | |
1028 | retval = -1; | |
1029 | } else if (value != MII_READ) { | |
1030 | /* it was a write operation - fewer failures are detectable */ | |
1031 | dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n", | |
1032 | dev->name, value, miireg, addr); | |
1033 | retval = 0; | |
1034 | } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { | |
1035 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n", | |
1036 | dev->name, miireg, addr); | |
1037 | retval = -1; | |
1038 | } else { | |
1039 | retval = readl(base + NvRegMIIData); | |
1040 | dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n", | |
1041 | dev->name, miireg, addr, retval); | |
1042 | } | |
1043 | ||
1044 | return retval; | |
1045 | } | |
1046 | ||
edf7e5ec | 1047 | static int phy_reset(struct net_device *dev, u32 bmcr_setup) |
1da177e4 | 1048 | { |
ac9c1897 | 1049 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1050 | u32 miicontrol; |
1051 | unsigned int tries = 0; | |
1052 | ||
edf7e5ec | 1053 | miicontrol = BMCR_RESET | bmcr_setup; |
1da177e4 LT |
1054 | if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { |
1055 | return -1; | |
1056 | } | |
1057 | ||
1058 | /* wait for 500ms */ | |
1059 | msleep(500); | |
1060 | ||
1061 | /* must wait till reset is deasserted */ | |
1062 | while (miicontrol & BMCR_RESET) { | |
1063 | msleep(10); | |
1064 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
1065 | /* FIXME: 100 tries seem excessive */ | |
1066 | if (tries++ > 100) | |
1067 | return -1; | |
1068 | } | |
1069 | return 0; | |
1070 | } | |
1071 | ||
1072 | static int phy_init(struct net_device *dev) | |
1073 | { | |
1074 | struct fe_priv *np = get_nvpriv(dev); | |
1075 | u8 __iomem *base = get_hwbase(dev); | |
1076 | u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg; | |
1077 | ||
edf7e5ec AA |
1078 | /* phy errata for E3016 phy */ |
1079 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { | |
1080 | reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
1081 | reg &= ~PHY_MARVELL_E3016_INITMASK; | |
1082 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { | |
1083 | printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev)); | |
1084 | return PHY_ERROR; | |
1085 | } | |
1086 | } | |
1087 | ||
1da177e4 LT |
1088 | /* set advertise register */ |
1089 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 1090 | reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); |
1da177e4 LT |
1091 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
1092 | printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); | |
1093 | return PHY_ERROR; | |
1094 | } | |
1095 | ||
1096 | /* get phy interface type */ | |
1097 | phyinterface = readl(base + NvRegPhyInterface); | |
1098 | ||
1099 | /* see if gigabit phy */ | |
1100 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
1101 | if (mii_status & PHY_GIGABIT) { | |
1102 | np->gigabit = PHY_GIGABIT; | |
eb91f61b | 1103 | mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 LT |
1104 | mii_control_1000 &= ~ADVERTISE_1000HALF; |
1105 | if (phyinterface & PHY_RGMII) | |
1106 | mii_control_1000 |= ADVERTISE_1000FULL; | |
1107 | else | |
1108 | mii_control_1000 &= ~ADVERTISE_1000FULL; | |
1109 | ||
eb91f61b | 1110 | if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { |
1da177e4 LT |
1111 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1112 | return PHY_ERROR; | |
1113 | } | |
1114 | } | |
1115 | else | |
1116 | np->gigabit = 0; | |
1117 | ||
edf7e5ec AA |
1118 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1119 | mii_control |= BMCR_ANENABLE; | |
1120 | ||
1121 | /* reset the phy | |
1122 | * (certain phys need bmcr to be setup with reset) | |
1123 | */ | |
1124 | if (phy_reset(dev, mii_control)) { | |
1da177e4 LT |
1125 | printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); |
1126 | return PHY_ERROR; | |
1127 | } | |
1128 | ||
1129 | /* phy vendor specific configuration */ | |
1130 | if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) { | |
1131 | phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); | |
1132 | phy_reserved &= ~(PHY_INIT1 | PHY_INIT2); | |
1133 | phy_reserved |= (PHY_INIT3 | PHY_INIT4); | |
1134 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { | |
1135 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1136 | return PHY_ERROR; | |
1137 | } | |
1138 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
1139 | phy_reserved |= PHY_INIT5; | |
1140 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { | |
1141 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1142 | return PHY_ERROR; | |
1143 | } | |
1144 | } | |
1145 | if (np->phy_oui == PHY_OUI_CICADA) { | |
1146 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); | |
1147 | phy_reserved |= PHY_INIT6; | |
1148 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { | |
1149 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1150 | return PHY_ERROR; | |
1151 | } | |
1152 | } | |
eb91f61b AA |
1153 | /* some phys clear out pause advertisment on reset, set it back */ |
1154 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); | |
1da177e4 LT |
1155 | |
1156 | /* restart auto negotiation */ | |
1157 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
1158 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); | |
1159 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { | |
1160 | return PHY_ERROR; | |
1161 | } | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | static void nv_start_rx(struct net_device *dev) | |
1167 | { | |
ac9c1897 | 1168 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1169 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1170 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 LT |
1171 | |
1172 | dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); | |
1173 | /* Already running? Stop it. */ | |
f35723ec AA |
1174 | if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { |
1175 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1176 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1177 | pci_push(base); |
1178 | } | |
1179 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
1180 | pci_push(base); | |
f35723ec AA |
1181 | rx_ctrl |= NVREG_RCVCTL_START; |
1182 | if (np->mac_in_use) | |
1183 | rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; | |
1184 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1185 | dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", |
1186 | dev->name, np->duplex, np->linkspeed); | |
1187 | pci_push(base); | |
1188 | } | |
1189 | ||
1190 | static void nv_stop_rx(struct net_device *dev) | |
1191 | { | |
f35723ec | 1192 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1193 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1194 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 LT |
1195 | |
1196 | dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); | |
f35723ec AA |
1197 | if (!np->mac_in_use) |
1198 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1199 | else | |
1200 | rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; | |
1201 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1202 | reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
1203 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, | |
1204 | KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); | |
1205 | ||
1206 | udelay(NV_RXSTOP_DELAY2); | |
f35723ec AA |
1207 | if (!np->mac_in_use) |
1208 | writel(0, base + NvRegLinkSpeed); | |
1da177e4 LT |
1209 | } |
1210 | ||
1211 | static void nv_start_tx(struct net_device *dev) | |
1212 | { | |
f35723ec | 1213 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1214 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1215 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 LT |
1216 | |
1217 | dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); | |
f35723ec AA |
1218 | tx_ctrl |= NVREG_XMITCTL_START; |
1219 | if (np->mac_in_use) | |
1220 | tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; | |
1221 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
1da177e4 LT |
1222 | pci_push(base); |
1223 | } | |
1224 | ||
1225 | static void nv_stop_tx(struct net_device *dev) | |
1226 | { | |
f35723ec | 1227 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1228 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1229 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 LT |
1230 | |
1231 | dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); | |
f35723ec AA |
1232 | if (!np->mac_in_use) |
1233 | tx_ctrl &= ~NVREG_XMITCTL_START; | |
1234 | else | |
1235 | tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; | |
1236 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
1da177e4 LT |
1237 | reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
1238 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, | |
1239 | KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); | |
1240 | ||
1241 | udelay(NV_TXSTOP_DELAY2); | |
f35723ec AA |
1242 | if (!np->mac_in_use) |
1243 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, | |
1244 | base + NvRegTransmitPoll); | |
1da177e4 LT |
1245 | } |
1246 | ||
1247 | static void nv_txrx_reset(struct net_device *dev) | |
1248 | { | |
ac9c1897 | 1249 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1250 | u8 __iomem *base = get_hwbase(dev); |
1251 | ||
1252 | dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); | |
8a4ae7f2 | 1253 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1254 | pci_push(base); |
1255 | udelay(NV_TXRX_RESET_DELAY); | |
8a4ae7f2 | 1256 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1257 | pci_push(base); |
1258 | } | |
1259 | ||
86a0f043 AA |
1260 | static void nv_mac_reset(struct net_device *dev) |
1261 | { | |
1262 | struct fe_priv *np = netdev_priv(dev); | |
1263 | u8 __iomem *base = get_hwbase(dev); | |
1264 | ||
1265 | dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); | |
1266 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); | |
1267 | pci_push(base); | |
1268 | writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); | |
1269 | pci_push(base); | |
1270 | udelay(NV_MAC_RESET_DELAY); | |
1271 | writel(0, base + NvRegMacReset); | |
1272 | pci_push(base); | |
1273 | udelay(NV_MAC_RESET_DELAY); | |
1274 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); | |
1275 | pci_push(base); | |
1276 | } | |
1277 | ||
1da177e4 LT |
1278 | /* |
1279 | * nv_get_stats: dev->get_stats function | |
1280 | * Get latest stats value from the nic. | |
1281 | * Called with read_lock(&dev_base_lock) held for read - | |
1282 | * only synchronized against unregister_netdevice. | |
1283 | */ | |
1284 | static struct net_device_stats *nv_get_stats(struct net_device *dev) | |
1285 | { | |
ac9c1897 | 1286 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1287 | |
1288 | /* It seems that the nic always generates interrupts and doesn't | |
1289 | * accumulate errors internally. Thus the current values in np->stats | |
1290 | * are already up to date. | |
1291 | */ | |
1292 | return &np->stats; | |
1293 | } | |
1294 | ||
1295 | /* | |
1296 | * nv_alloc_rx: fill rx ring entries. | |
1297 | * Return 1 if the allocations for the skbs failed and the | |
1298 | * rx engine is without Available descriptors | |
1299 | */ | |
1300 | static int nv_alloc_rx(struct net_device *dev) | |
1301 | { | |
ac9c1897 | 1302 | struct fe_priv *np = netdev_priv(dev); |
86b22b0d | 1303 | struct ring_desc* less_rx; |
1da177e4 | 1304 | |
86b22b0d AA |
1305 | less_rx = np->get_rx.orig; |
1306 | if (less_rx-- == np->first_rx.orig) | |
1307 | less_rx = np->last_rx.orig; | |
761fcd9e | 1308 | |
86b22b0d AA |
1309 | while (np->put_rx.orig != less_rx) { |
1310 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); | |
1311 | if (skb) { | |
1312 | skb->dev = dev; | |
1313 | np->put_rx_ctx->skb = skb; | |
1314 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data, | |
1315 | skb->end-skb->data, PCI_DMA_FROMDEVICE); | |
1316 | np->put_rx_ctx->dma_len = skb->end-skb->data; | |
1317 | np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma); | |
1318 | wmb(); | |
1319 | np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); | |
b01867cb | 1320 | if (unlikely(np->put_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 1321 | np->put_rx.orig = np->first_rx.orig; |
b01867cb | 1322 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d | 1323 | np->put_rx_ctx = np->first_rx_ctx; |
761fcd9e | 1324 | } else { |
86b22b0d | 1325 | return 1; |
761fcd9e | 1326 | } |
86b22b0d AA |
1327 | } |
1328 | return 0; | |
1329 | } | |
1330 | ||
1331 | static int nv_alloc_rx_optimized(struct net_device *dev) | |
1332 | { | |
1333 | struct fe_priv *np = netdev_priv(dev); | |
1334 | struct ring_desc_ex* less_rx; | |
1335 | ||
1336 | less_rx = np->get_rx.ex; | |
1337 | if (less_rx-- == np->first_rx.ex) | |
1338 | less_rx = np->last_rx.ex; | |
761fcd9e | 1339 | |
86b22b0d AA |
1340 | while (np->put_rx.ex != less_rx) { |
1341 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); | |
0d63fb32 | 1342 | if (skb) { |
1da177e4 | 1343 | skb->dev = dev; |
761fcd9e | 1344 | np->put_rx_ctx->skb = skb; |
0d63fb32 AA |
1345 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data, |
1346 | skb->end-skb->data, PCI_DMA_FROMDEVICE); | |
1347 | np->put_rx_ctx->dma_len = skb->end-skb->data; | |
86b22b0d AA |
1348 | np->put_rx.ex->bufhigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32; |
1349 | np->put_rx.ex->buflow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF; | |
1350 | wmb(); | |
1351 | np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); | |
b01867cb | 1352 | if (unlikely(np->put_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 1353 | np->put_rx.ex = np->first_rx.ex; |
b01867cb | 1354 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
0d63fb32 | 1355 | np->put_rx_ctx = np->first_rx_ctx; |
1da177e4 | 1356 | } else { |
0d63fb32 | 1357 | return 1; |
ee73362c | 1358 | } |
1da177e4 | 1359 | } |
1da177e4 LT |
1360 | return 0; |
1361 | } | |
1362 | ||
e27cdba5 SH |
1363 | /* If rx bufs are exhausted called after 50ms to attempt to refresh */ |
1364 | #ifdef CONFIG_FORCEDETH_NAPI | |
1365 | static void nv_do_rx_refill(unsigned long data) | |
1366 | { | |
1367 | struct net_device *dev = (struct net_device *) data; | |
1368 | ||
1369 | /* Just reschedule NAPI rx processing */ | |
1370 | netif_rx_schedule(dev); | |
1371 | } | |
1372 | #else | |
1da177e4 LT |
1373 | static void nv_do_rx_refill(unsigned long data) |
1374 | { | |
1375 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 1376 | struct fe_priv *np = netdev_priv(dev); |
86b22b0d | 1377 | int retcode; |
1da177e4 | 1378 | |
84b3932b AA |
1379 | if (!using_multi_irqs(dev)) { |
1380 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1381 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1382 | else | |
1383 | disable_irq(dev->irq); | |
d33a73c8 AA |
1384 | } else { |
1385 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1386 | } | |
86b22b0d AA |
1387 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
1388 | retcode = nv_alloc_rx(dev); | |
1389 | else | |
1390 | retcode = nv_alloc_rx_optimized(dev); | |
1391 | if (retcode) { | |
84b3932b | 1392 | spin_lock_irq(&np->lock); |
1da177e4 LT |
1393 | if (!np->in_shutdown) |
1394 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
84b3932b | 1395 | spin_unlock_irq(&np->lock); |
1da177e4 | 1396 | } |
84b3932b AA |
1397 | if (!using_multi_irqs(dev)) { |
1398 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1399 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1400 | else | |
1401 | enable_irq(dev->irq); | |
d33a73c8 AA |
1402 | } else { |
1403 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1404 | } | |
1da177e4 | 1405 | } |
e27cdba5 | 1406 | #endif |
1da177e4 | 1407 | |
f3b197ac | 1408 | static void nv_init_rx(struct net_device *dev) |
1da177e4 | 1409 | { |
ac9c1897 | 1410 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1411 | int i; |
761fcd9e AA |
1412 | np->get_rx = np->put_rx = np->first_rx = np->rx_ring; |
1413 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | |
1414 | np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1]; | |
1415 | else | |
1416 | np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1]; | |
1417 | np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb; | |
1418 | np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1]; | |
1da177e4 | 1419 | |
761fcd9e AA |
1420 | for (i = 0; i < np->rx_ring_size; i++) { |
1421 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { | |
f82a9352 | 1422 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1423 | np->rx_ring.orig[i].buf = 0; |
1424 | } else { | |
f82a9352 | 1425 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1426 | np->rx_ring.ex[i].txvlan = 0; |
1427 | np->rx_ring.ex[i].bufhigh = 0; | |
1428 | np->rx_ring.ex[i].buflow = 0; | |
1429 | } | |
1430 | np->rx_skb[i].skb = NULL; | |
1431 | np->rx_skb[i].dma = 0; | |
1432 | } | |
d81c0983 MS |
1433 | } |
1434 | ||
1435 | static void nv_init_tx(struct net_device *dev) | |
1436 | { | |
ac9c1897 | 1437 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 | 1438 | int i; |
761fcd9e AA |
1439 | np->get_tx = np->put_tx = np->first_tx = np->tx_ring; |
1440 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | |
1441 | np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1]; | |
1442 | else | |
1443 | np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1]; | |
1444 | np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb; | |
1445 | np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1]; | |
d81c0983 | 1446 | |
eafa59f6 | 1447 | for (i = 0; i < np->tx_ring_size; i++) { |
761fcd9e | 1448 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
f82a9352 | 1449 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1450 | np->tx_ring.orig[i].buf = 0; |
1451 | } else { | |
f82a9352 | 1452 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1453 | np->tx_ring.ex[i].txvlan = 0; |
1454 | np->tx_ring.ex[i].bufhigh = 0; | |
1455 | np->tx_ring.ex[i].buflow = 0; | |
1456 | } | |
1457 | np->tx_skb[i].skb = NULL; | |
1458 | np->tx_skb[i].dma = 0; | |
ac9c1897 | 1459 | } |
d81c0983 MS |
1460 | } |
1461 | ||
1462 | static int nv_init_ring(struct net_device *dev) | |
1463 | { | |
86b22b0d AA |
1464 | struct fe_priv *np = netdev_priv(dev); |
1465 | ||
d81c0983 MS |
1466 | nv_init_tx(dev); |
1467 | nv_init_rx(dev); | |
86b22b0d AA |
1468 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
1469 | return nv_alloc_rx(dev); | |
1470 | else | |
1471 | return nv_alloc_rx_optimized(dev); | |
1da177e4 LT |
1472 | } |
1473 | ||
761fcd9e | 1474 | static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb) |
ac9c1897 AA |
1475 | { |
1476 | struct fe_priv *np = netdev_priv(dev); | |
fa45459e | 1477 | |
761fcd9e AA |
1478 | if (tx_skb->dma) { |
1479 | pci_unmap_page(np->pci_dev, tx_skb->dma, | |
1480 | tx_skb->dma_len, | |
fa45459e | 1481 | PCI_DMA_TODEVICE); |
761fcd9e | 1482 | tx_skb->dma = 0; |
fa45459e | 1483 | } |
761fcd9e AA |
1484 | if (tx_skb->skb) { |
1485 | dev_kfree_skb_any(tx_skb->skb); | |
1486 | tx_skb->skb = NULL; | |
fa45459e AA |
1487 | return 1; |
1488 | } else { | |
1489 | return 0; | |
ac9c1897 | 1490 | } |
ac9c1897 AA |
1491 | } |
1492 | ||
1da177e4 LT |
1493 | static void nv_drain_tx(struct net_device *dev) |
1494 | { | |
ac9c1897 AA |
1495 | struct fe_priv *np = netdev_priv(dev); |
1496 | unsigned int i; | |
f3b197ac | 1497 | |
eafa59f6 | 1498 | for (i = 0; i < np->tx_ring_size; i++) { |
761fcd9e | 1499 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
f82a9352 | 1500 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1501 | np->tx_ring.orig[i].buf = 0; |
1502 | } else { | |
f82a9352 | 1503 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1504 | np->tx_ring.ex[i].txvlan = 0; |
1505 | np->tx_ring.ex[i].bufhigh = 0; | |
1506 | np->tx_ring.ex[i].buflow = 0; | |
1507 | } | |
1508 | if (nv_release_txskb(dev, &np->tx_skb[i])) | |
1da177e4 | 1509 | np->stats.tx_dropped++; |
1da177e4 LT |
1510 | } |
1511 | } | |
1512 | ||
1513 | static void nv_drain_rx(struct net_device *dev) | |
1514 | { | |
ac9c1897 | 1515 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1516 | int i; |
761fcd9e | 1517 | |
eafa59f6 | 1518 | for (i = 0; i < np->rx_ring_size; i++) { |
761fcd9e | 1519 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
f82a9352 | 1520 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1521 | np->rx_ring.orig[i].buf = 0; |
1522 | } else { | |
f82a9352 | 1523 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1524 | np->rx_ring.ex[i].txvlan = 0; |
1525 | np->rx_ring.ex[i].bufhigh = 0; | |
1526 | np->rx_ring.ex[i].buflow = 0; | |
1527 | } | |
1da177e4 | 1528 | wmb(); |
761fcd9e AA |
1529 | if (np->rx_skb[i].skb) { |
1530 | pci_unmap_single(np->pci_dev, np->rx_skb[i].dma, | |
1531 | np->rx_skb[i].skb->end-np->rx_skb[i].skb->data, | |
1da177e4 | 1532 | PCI_DMA_FROMDEVICE); |
761fcd9e AA |
1533 | dev_kfree_skb(np->rx_skb[i].skb); |
1534 | np->rx_skb[i].skb = NULL; | |
1da177e4 LT |
1535 | } |
1536 | } | |
1537 | } | |
1538 | ||
1539 | static void drain_ring(struct net_device *dev) | |
1540 | { | |
1541 | nv_drain_tx(dev); | |
1542 | nv_drain_rx(dev); | |
1543 | } | |
1544 | ||
761fcd9e AA |
1545 | static inline u32 nv_get_empty_tx_slots(struct fe_priv *np) |
1546 | { | |
1547 | return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size)); | |
1548 | } | |
1549 | ||
1da177e4 LT |
1550 | /* |
1551 | * nv_start_xmit: dev->hard_start_xmit function | |
932ff279 | 1552 | * Called with netif_tx_lock held. |
1da177e4 LT |
1553 | */ |
1554 | static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1555 | { | |
ac9c1897 | 1556 | struct fe_priv *np = netdev_priv(dev); |
fa45459e | 1557 | u32 tx_flags = 0; |
ac9c1897 AA |
1558 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
1559 | unsigned int fragments = skb_shinfo(skb)->nr_frags; | |
ac9c1897 | 1560 | unsigned int i; |
fa45459e AA |
1561 | u32 offset = 0; |
1562 | u32 bcnt; | |
1563 | u32 size = skb->len-skb->data_len; | |
1564 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
761fcd9e | 1565 | u32 empty_slots; |
86b22b0d AA |
1566 | struct ring_desc* put_tx; |
1567 | struct ring_desc* start_tx; | |
1568 | struct ring_desc* prev_tx; | |
761fcd9e | 1569 | struct nv_skb_map* prev_tx_ctx; |
fa45459e AA |
1570 | |
1571 | /* add fragments to entries count */ | |
1572 | for (i = 0; i < fragments; i++) { | |
1573 | entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + | |
1574 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
1575 | } | |
ac9c1897 | 1576 | |
761fcd9e | 1577 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 1578 | if (unlikely(empty_slots <= entries)) { |
164a86e4 | 1579 | spin_lock_irq(&np->lock); |
ac9c1897 | 1580 | netif_stop_queue(dev); |
aaa37d2d | 1581 | np->tx_stop = 1; |
164a86e4 | 1582 | spin_unlock_irq(&np->lock); |
ac9c1897 AA |
1583 | return NETDEV_TX_BUSY; |
1584 | } | |
1da177e4 | 1585 | |
86b22b0d | 1586 | start_tx = put_tx = np->put_tx.orig; |
761fcd9e | 1587 | |
fa45459e AA |
1588 | /* setup the header buffer */ |
1589 | do { | |
761fcd9e AA |
1590 | prev_tx = put_tx; |
1591 | prev_tx_ctx = np->put_tx_ctx; | |
fa45459e | 1592 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
761fcd9e | 1593 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, |
fa45459e | 1594 | PCI_DMA_TODEVICE); |
761fcd9e | 1595 | np->put_tx_ctx->dma_len = bcnt; |
86b22b0d AA |
1596 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
1597 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 1598 | |
fa45459e AA |
1599 | tx_flags = np->tx_flags; |
1600 | offset += bcnt; | |
1601 | size -= bcnt; | |
445583b8 | 1602 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 1603 | put_tx = np->first_tx.orig; |
445583b8 | 1604 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 1605 | np->put_tx_ctx = np->first_tx_ctx; |
f82a9352 | 1606 | } while (size); |
fa45459e AA |
1607 | |
1608 | /* setup the fragments */ | |
1609 | for (i = 0; i < fragments; i++) { | |
1610 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1611 | u32 size = frag->size; | |
1612 | offset = 0; | |
1613 | ||
1614 | do { | |
761fcd9e AA |
1615 | prev_tx = put_tx; |
1616 | prev_tx_ctx = np->put_tx_ctx; | |
fa45459e | 1617 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
761fcd9e AA |
1618 | np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, |
1619 | PCI_DMA_TODEVICE); | |
1620 | np->put_tx_ctx->dma_len = bcnt; | |
86b22b0d AA |
1621 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
1622 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 1623 | |
fa45459e AA |
1624 | offset += bcnt; |
1625 | size -= bcnt; | |
445583b8 | 1626 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 1627 | put_tx = np->first_tx.orig; |
445583b8 | 1628 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 1629 | np->put_tx_ctx = np->first_tx_ctx; |
fa45459e AA |
1630 | } while (size); |
1631 | } | |
ac9c1897 | 1632 | |
fa45459e | 1633 | /* set last fragment flag */ |
86b22b0d | 1634 | prev_tx->flaglen |= cpu_to_le32(tx_flags_extra); |
ac9c1897 | 1635 | |
761fcd9e AA |
1636 | /* save skb in this slot's context area */ |
1637 | prev_tx_ctx->skb = skb; | |
fa45459e | 1638 | |
89114afd | 1639 | if (skb_is_gso(skb)) |
7967168c | 1640 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); |
ac9c1897 | 1641 | else |
1d39ed56 | 1642 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? |
84fa7933 | 1643 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; |
ac9c1897 | 1644 | |
164a86e4 AA |
1645 | spin_lock_irq(&np->lock); |
1646 | ||
fa45459e | 1647 | /* set tx flags */ |
86b22b0d AA |
1648 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
1649 | np->put_tx.orig = put_tx; | |
1da177e4 | 1650 | |
164a86e4 | 1651 | spin_unlock_irq(&np->lock); |
761fcd9e AA |
1652 | |
1653 | dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n", | |
1654 | dev->name, entries, tx_flags_extra); | |
1da177e4 LT |
1655 | { |
1656 | int j; | |
1657 | for (j=0; j<64; j++) { | |
1658 | if ((j%16) == 0) | |
1659 | dprintk("\n%03x:", j); | |
1660 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | |
1661 | } | |
1662 | dprintk("\n"); | |
1663 | } | |
1664 | ||
1da177e4 | 1665 | dev->trans_start = jiffies; |
8a4ae7f2 | 1666 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
ac9c1897 | 1667 | return NETDEV_TX_OK; |
1da177e4 LT |
1668 | } |
1669 | ||
86b22b0d AA |
1670 | static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev) |
1671 | { | |
1672 | struct fe_priv *np = netdev_priv(dev); | |
1673 | u32 tx_flags = 0; | |
445583b8 | 1674 | u32 tx_flags_extra; |
86b22b0d AA |
1675 | unsigned int fragments = skb_shinfo(skb)->nr_frags; |
1676 | unsigned int i; | |
1677 | u32 offset = 0; | |
1678 | u32 bcnt; | |
1679 | u32 size = skb->len-skb->data_len; | |
1680 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
1681 | u32 empty_slots; | |
86b22b0d AA |
1682 | struct ring_desc_ex* put_tx; |
1683 | struct ring_desc_ex* start_tx; | |
1684 | struct ring_desc_ex* prev_tx; | |
1685 | struct nv_skb_map* prev_tx_ctx; | |
1686 | ||
1687 | /* add fragments to entries count */ | |
1688 | for (i = 0; i < fragments; i++) { | |
1689 | entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + | |
1690 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
1691 | } | |
1692 | ||
1693 | empty_slots = nv_get_empty_tx_slots(np); | |
445583b8 | 1694 | if (unlikely(empty_slots <= entries)) { |
86b22b0d AA |
1695 | spin_lock_irq(&np->lock); |
1696 | netif_stop_queue(dev); | |
aaa37d2d | 1697 | np->tx_stop = 1; |
86b22b0d AA |
1698 | spin_unlock_irq(&np->lock); |
1699 | return NETDEV_TX_BUSY; | |
1700 | } | |
1701 | ||
1702 | start_tx = put_tx = np->put_tx.ex; | |
1703 | ||
1704 | /* setup the header buffer */ | |
1705 | do { | |
1706 | prev_tx = put_tx; | |
1707 | prev_tx_ctx = np->put_tx_ctx; | |
1708 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
1709 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, | |
1710 | PCI_DMA_TODEVICE); | |
1711 | np->put_tx_ctx->dma_len = bcnt; | |
1712 | put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32; | |
1713 | put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF; | |
1714 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 AA |
1715 | |
1716 | tx_flags = NV_TX2_VALID; | |
86b22b0d AA |
1717 | offset += bcnt; |
1718 | size -= bcnt; | |
445583b8 | 1719 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 1720 | put_tx = np->first_tx.ex; |
445583b8 | 1721 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
1722 | np->put_tx_ctx = np->first_tx_ctx; |
1723 | } while (size); | |
1724 | ||
1725 | /* setup the fragments */ | |
1726 | for (i = 0; i < fragments; i++) { | |
1727 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1728 | u32 size = frag->size; | |
1729 | offset = 0; | |
1730 | ||
1731 | do { | |
1732 | prev_tx = put_tx; | |
1733 | prev_tx_ctx = np->put_tx_ctx; | |
1734 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
1735 | np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, | |
1736 | PCI_DMA_TODEVICE); | |
1737 | np->put_tx_ctx->dma_len = bcnt; | |
86b22b0d AA |
1738 | put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32; |
1739 | put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF; | |
1740 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 1741 | |
86b22b0d AA |
1742 | offset += bcnt; |
1743 | size -= bcnt; | |
445583b8 | 1744 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 1745 | put_tx = np->first_tx.ex; |
445583b8 | 1746 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
1747 | np->put_tx_ctx = np->first_tx_ctx; |
1748 | } while (size); | |
1749 | } | |
1750 | ||
1751 | /* set last fragment flag */ | |
445583b8 | 1752 | prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET); |
86b22b0d AA |
1753 | |
1754 | /* save skb in this slot's context area */ | |
1755 | prev_tx_ctx->skb = skb; | |
1756 | ||
1757 | if (skb_is_gso(skb)) | |
1758 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); | |
1759 | else | |
1760 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? | |
1761 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; | |
1762 | ||
1763 | /* vlan tag */ | |
445583b8 AA |
1764 | if (likely(!np->vlangrp)) { |
1765 | start_tx->txvlan = 0; | |
1766 | } else { | |
1767 | if (vlan_tx_tag_present(skb)) | |
1768 | start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb)); | |
1769 | else | |
1770 | start_tx->txvlan = 0; | |
86b22b0d AA |
1771 | } |
1772 | ||
1773 | spin_lock_irq(&np->lock); | |
1774 | ||
1775 | /* set tx flags */ | |
86b22b0d AA |
1776 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
1777 | np->put_tx.ex = put_tx; | |
1778 | ||
1779 | spin_unlock_irq(&np->lock); | |
1780 | ||
1781 | dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n", | |
1782 | dev->name, entries, tx_flags_extra); | |
1783 | { | |
1784 | int j; | |
1785 | for (j=0; j<64; j++) { | |
1786 | if ((j%16) == 0) | |
1787 | dprintk("\n%03x:", j); | |
1788 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | |
1789 | } | |
1790 | dprintk("\n"); | |
1791 | } | |
1792 | ||
1793 | dev->trans_start = jiffies; | |
1794 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
86b22b0d AA |
1795 | return NETDEV_TX_OK; |
1796 | } | |
1797 | ||
1da177e4 LT |
1798 | /* |
1799 | * nv_tx_done: check for completed packets, release the skbs. | |
1800 | * | |
1801 | * Caller must own np->lock. | |
1802 | */ | |
1803 | static void nv_tx_done(struct net_device *dev) | |
1804 | { | |
ac9c1897 | 1805 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 1806 | u32 flags; |
aaa37d2d | 1807 | struct ring_desc* orig_get_tx = np->get_tx.orig; |
1da177e4 | 1808 | |
445583b8 AA |
1809 | while ((np->get_tx.orig != np->put_tx.orig) && |
1810 | !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) { | |
1da177e4 | 1811 | |
761fcd9e AA |
1812 | dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n", |
1813 | dev->name, flags); | |
445583b8 AA |
1814 | |
1815 | pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma, | |
1816 | np->get_tx_ctx->dma_len, | |
1817 | PCI_DMA_TODEVICE); | |
1818 | np->get_tx_ctx->dma = 0; | |
1819 | ||
1da177e4 | 1820 | if (np->desc_ver == DESC_VER_1) { |
f82a9352 | 1821 | if (flags & NV_TX_LASTPACKET) { |
445583b8 | 1822 | if (flags & NV_TX_ERROR) { |
f82a9352 | 1823 | if (flags & NV_TX_UNDERFLOW) |
ac9c1897 | 1824 | np->stats.tx_fifo_errors++; |
f82a9352 | 1825 | if (flags & NV_TX_CARRIERLOST) |
ac9c1897 AA |
1826 | np->stats.tx_carrier_errors++; |
1827 | np->stats.tx_errors++; | |
1828 | } else { | |
1829 | np->stats.tx_packets++; | |
445583b8 | 1830 | np->stats.tx_bytes += np->get_tx_ctx->skb->len; |
ac9c1897 | 1831 | } |
445583b8 AA |
1832 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
1833 | np->get_tx_ctx->skb = NULL; | |
1da177e4 LT |
1834 | } |
1835 | } else { | |
f82a9352 | 1836 | if (flags & NV_TX2_LASTPACKET) { |
445583b8 | 1837 | if (flags & NV_TX2_ERROR) { |
f82a9352 | 1838 | if (flags & NV_TX2_UNDERFLOW) |
ac9c1897 | 1839 | np->stats.tx_fifo_errors++; |
f82a9352 | 1840 | if (flags & NV_TX2_CARRIERLOST) |
ac9c1897 AA |
1841 | np->stats.tx_carrier_errors++; |
1842 | np->stats.tx_errors++; | |
1843 | } else { | |
1844 | np->stats.tx_packets++; | |
445583b8 | 1845 | np->stats.tx_bytes += np->get_tx_ctx->skb->len; |
f3b197ac | 1846 | } |
445583b8 AA |
1847 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
1848 | np->get_tx_ctx->skb = NULL; | |
1da177e4 LT |
1849 | } |
1850 | } | |
445583b8 | 1851 | if (unlikely(np->get_tx.orig++ == np->last_tx.orig)) |
86b22b0d | 1852 | np->get_tx.orig = np->first_tx.orig; |
445583b8 | 1853 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
1854 | np->get_tx_ctx = np->first_tx_ctx; |
1855 | } | |
445583b8 | 1856 | if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) { |
aaa37d2d | 1857 | np->tx_stop = 0; |
86b22b0d | 1858 | netif_wake_queue(dev); |
aaa37d2d | 1859 | } |
86b22b0d AA |
1860 | } |
1861 | ||
1862 | static void nv_tx_done_optimized(struct net_device *dev) | |
1863 | { | |
1864 | struct fe_priv *np = netdev_priv(dev); | |
1865 | u32 flags; | |
aaa37d2d | 1866 | struct ring_desc_ex* orig_get_tx = np->get_tx.ex; |
86b22b0d | 1867 | |
445583b8 AA |
1868 | while ((np->get_tx.ex != np->put_tx.ex) && |
1869 | !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID)) { | |
86b22b0d AA |
1870 | |
1871 | dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n", | |
1872 | dev->name, flags); | |
445583b8 AA |
1873 | |
1874 | pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma, | |
1875 | np->get_tx_ctx->dma_len, | |
1876 | PCI_DMA_TODEVICE); | |
1877 | np->get_tx_ctx->dma = 0; | |
1878 | ||
86b22b0d | 1879 | if (flags & NV_TX2_LASTPACKET) { |
445583b8 | 1880 | if (flags & NV_TX2_ERROR) { |
86b22b0d AA |
1881 | if (flags & NV_TX2_UNDERFLOW) |
1882 | np->stats.tx_fifo_errors++; | |
1883 | if (flags & NV_TX2_CARRIERLOST) | |
1884 | np->stats.tx_carrier_errors++; | |
1885 | np->stats.tx_errors++; | |
1886 | } else { | |
1887 | np->stats.tx_packets++; | |
445583b8 | 1888 | np->stats.tx_bytes += np->get_tx_ctx->skb->len; |
86b22b0d | 1889 | } |
445583b8 AA |
1890 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
1891 | np->get_tx_ctx->skb = NULL; | |
761fcd9e | 1892 | } |
445583b8 | 1893 | if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) |
86b22b0d | 1894 | np->get_tx.ex = np->first_tx.ex; |
445583b8 | 1895 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 1896 | np->get_tx_ctx = np->first_tx_ctx; |
1da177e4 | 1897 | } |
445583b8 | 1898 | if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) { |
aaa37d2d | 1899 | np->tx_stop = 0; |
1da177e4 | 1900 | netif_wake_queue(dev); |
aaa37d2d | 1901 | } |
1da177e4 LT |
1902 | } |
1903 | ||
1904 | /* | |
1905 | * nv_tx_timeout: dev->tx_timeout function | |
932ff279 | 1906 | * Called with netif_tx_lock held. |
1da177e4 LT |
1907 | */ |
1908 | static void nv_tx_timeout(struct net_device *dev) | |
1909 | { | |
ac9c1897 | 1910 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1911 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 AA |
1912 | u32 status; |
1913 | ||
1914 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1915 | status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
1916 | else | |
1917 | status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
1da177e4 | 1918 | |
d33a73c8 | 1919 | printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status); |
1da177e4 | 1920 | |
c2dba06d MS |
1921 | { |
1922 | int i; | |
1923 | ||
761fcd9e AA |
1924 | printk(KERN_INFO "%s: Ring at %lx\n", |
1925 | dev->name, (unsigned long)np->ring_addr); | |
c2dba06d | 1926 | printk(KERN_INFO "%s: Dumping tx registers\n", dev->name); |
86a0f043 | 1927 | for (i=0;i<=np->register_size;i+= 32) { |
c2dba06d MS |
1928 | printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", |
1929 | i, | |
1930 | readl(base + i + 0), readl(base + i + 4), | |
1931 | readl(base + i + 8), readl(base + i + 12), | |
1932 | readl(base + i + 16), readl(base + i + 20), | |
1933 | readl(base + i + 24), readl(base + i + 28)); | |
1934 | } | |
1935 | printk(KERN_INFO "%s: Dumping tx ring\n", dev->name); | |
eafa59f6 | 1936 | for (i=0;i<np->tx_ring_size;i+= 4) { |
ee73362c MS |
1937 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
1938 | printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", | |
f3b197ac | 1939 | i, |
f82a9352 SH |
1940 | le32_to_cpu(np->tx_ring.orig[i].buf), |
1941 | le32_to_cpu(np->tx_ring.orig[i].flaglen), | |
1942 | le32_to_cpu(np->tx_ring.orig[i+1].buf), | |
1943 | le32_to_cpu(np->tx_ring.orig[i+1].flaglen), | |
1944 | le32_to_cpu(np->tx_ring.orig[i+2].buf), | |
1945 | le32_to_cpu(np->tx_ring.orig[i+2].flaglen), | |
1946 | le32_to_cpu(np->tx_ring.orig[i+3].buf), | |
1947 | le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); | |
ee73362c MS |
1948 | } else { |
1949 | printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", | |
f3b197ac | 1950 | i, |
f82a9352 SH |
1951 | le32_to_cpu(np->tx_ring.ex[i].bufhigh), |
1952 | le32_to_cpu(np->tx_ring.ex[i].buflow), | |
1953 | le32_to_cpu(np->tx_ring.ex[i].flaglen), | |
1954 | le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), | |
1955 | le32_to_cpu(np->tx_ring.ex[i+1].buflow), | |
1956 | le32_to_cpu(np->tx_ring.ex[i+1].flaglen), | |
1957 | le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), | |
1958 | le32_to_cpu(np->tx_ring.ex[i+2].buflow), | |
1959 | le32_to_cpu(np->tx_ring.ex[i+2].flaglen), | |
1960 | le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), | |
1961 | le32_to_cpu(np->tx_ring.ex[i+3].buflow), | |
1962 | le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); | |
ee73362c | 1963 | } |
c2dba06d MS |
1964 | } |
1965 | } | |
1966 | ||
1da177e4 LT |
1967 | spin_lock_irq(&np->lock); |
1968 | ||
1969 | /* 1) stop tx engine */ | |
1970 | nv_stop_tx(dev); | |
1971 | ||
1972 | /* 2) check that the packets were not sent already: */ | |
86b22b0d AA |
1973 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
1974 | nv_tx_done(dev); | |
1975 | else | |
1976 | nv_tx_done_optimized(dev); | |
1da177e4 LT |
1977 | |
1978 | /* 3) if there are dead entries: clear everything */ | |
761fcd9e | 1979 | if (np->get_tx_ctx != np->put_tx_ctx) { |
1da177e4 LT |
1980 | printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name); |
1981 | nv_drain_tx(dev); | |
761fcd9e | 1982 | nv_init_tx(dev); |
0832b25a | 1983 | setup_hw_rings(dev, NV_SETUP_TX_RING); |
1da177e4 LT |
1984 | netif_wake_queue(dev); |
1985 | } | |
1986 | ||
1987 | /* 4) restart tx engine */ | |
1988 | nv_start_tx(dev); | |
1989 | spin_unlock_irq(&np->lock); | |
1990 | } | |
1991 | ||
22c6d143 MS |
1992 | /* |
1993 | * Called when the nic notices a mismatch between the actual data len on the | |
1994 | * wire and the len indicated in the 802 header | |
1995 | */ | |
1996 | static int nv_getlen(struct net_device *dev, void *packet, int datalen) | |
1997 | { | |
1998 | int hdrlen; /* length of the 802 header */ | |
1999 | int protolen; /* length as stored in the proto field */ | |
2000 | ||
2001 | /* 1) calculate len according to header */ | |
f82a9352 | 2002 | if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) { |
22c6d143 MS |
2003 | protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto ); |
2004 | hdrlen = VLAN_HLEN; | |
2005 | } else { | |
2006 | protolen = ntohs( ((struct ethhdr *)packet)->h_proto); | |
2007 | hdrlen = ETH_HLEN; | |
2008 | } | |
2009 | dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n", | |
2010 | dev->name, datalen, protolen, hdrlen); | |
2011 | if (protolen > ETH_DATA_LEN) | |
2012 | return datalen; /* Value in proto field not a len, no checks possible */ | |
2013 | ||
2014 | protolen += hdrlen; | |
2015 | /* consistency checks: */ | |
2016 | if (datalen > ETH_ZLEN) { | |
2017 | if (datalen >= protolen) { | |
2018 | /* more data on wire than in 802 header, trim of | |
2019 | * additional data. | |
2020 | */ | |
2021 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | |
2022 | dev->name, protolen); | |
2023 | return protolen; | |
2024 | } else { | |
2025 | /* less data on wire than mentioned in header. | |
2026 | * Discard the packet. | |
2027 | */ | |
2028 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n", | |
2029 | dev->name); | |
2030 | return -1; | |
2031 | } | |
2032 | } else { | |
2033 | /* short packet. Accept only if 802 values are also short */ | |
2034 | if (protolen > ETH_ZLEN) { | |
2035 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n", | |
2036 | dev->name); | |
2037 | return -1; | |
2038 | } | |
2039 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | |
2040 | dev->name, datalen); | |
2041 | return datalen; | |
2042 | } | |
2043 | } | |
2044 | ||
e27cdba5 | 2045 | static int nv_rx_process(struct net_device *dev, int limit) |
1da177e4 | 2046 | { |
ac9c1897 | 2047 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2048 | u32 flags; |
b01867cb AA |
2049 | u32 rx_processed_cnt = 0; |
2050 | struct sk_buff *skb; | |
2051 | int len; | |
1da177e4 | 2052 | |
b01867cb AA |
2053 | while((np->get_rx.orig != np->put_rx.orig) && |
2054 | !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) && | |
2055 | (rx_processed_cnt++ < limit)) { | |
1da177e4 | 2056 | |
761fcd9e AA |
2057 | dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n", |
2058 | dev->name, flags); | |
1da177e4 | 2059 | |
1da177e4 LT |
2060 | /* |
2061 | * the packet is for us - immediately tear down the pci mapping. | |
2062 | * TODO: check if a prefetch of the first cacheline improves | |
2063 | * the performance. | |
2064 | */ | |
761fcd9e AA |
2065 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, |
2066 | np->get_rx_ctx->dma_len, | |
1da177e4 | 2067 | PCI_DMA_FROMDEVICE); |
0d63fb32 AA |
2068 | skb = np->get_rx_ctx->skb; |
2069 | np->get_rx_ctx->skb = NULL; | |
1da177e4 LT |
2070 | |
2071 | { | |
2072 | int j; | |
f82a9352 | 2073 | dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags); |
1da177e4 LT |
2074 | for (j=0; j<64; j++) { |
2075 | if ((j%16) == 0) | |
2076 | dprintk("\n%03x:", j); | |
0d63fb32 | 2077 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); |
1da177e4 LT |
2078 | } |
2079 | dprintk("\n"); | |
2080 | } | |
2081 | /* look at what we actually got: */ | |
2082 | if (np->desc_ver == DESC_VER_1) { | |
b01867cb AA |
2083 | if (likely(flags & NV_RX_DESCRIPTORVALID)) { |
2084 | len = flags & LEN_MASK_V1; | |
2085 | if (unlikely(flags & NV_RX_ERROR)) { | |
2086 | if (flags & NV_RX_ERROR4) { | |
2087 | len = nv_getlen(dev, skb->data, len); | |
2088 | if (len < 0) { | |
2089 | np->stats.rx_errors++; | |
2090 | dev_kfree_skb(skb); | |
2091 | goto next_pkt; | |
2092 | } | |
2093 | } | |
2094 | /* framing errors are soft errors */ | |
2095 | else if (flags & NV_RX_FRAMINGERR) { | |
2096 | if (flags & NV_RX_SUBSTRACT1) { | |
2097 | len--; | |
2098 | } | |
2099 | } | |
2100 | /* the rest are hard errors */ | |
2101 | else { | |
2102 | if (flags & NV_RX_MISSEDFRAME) | |
2103 | np->stats.rx_missed_errors++; | |
2104 | if (flags & NV_RX_CRCERR) | |
2105 | np->stats.rx_crc_errors++; | |
2106 | if (flags & NV_RX_OVERFLOW) | |
2107 | np->stats.rx_over_errors++; | |
a971c324 | 2108 | np->stats.rx_errors++; |
0d63fb32 | 2109 | dev_kfree_skb(skb); |
a971c324 AA |
2110 | goto next_pkt; |
2111 | } | |
2112 | } | |
b01867cb | 2113 | } else { |
0d63fb32 | 2114 | dev_kfree_skb(skb); |
1da177e4 | 2115 | goto next_pkt; |
0d63fb32 | 2116 | } |
b01867cb AA |
2117 | } else { |
2118 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { | |
2119 | len = flags & LEN_MASK_V2; | |
2120 | if (unlikely(flags & NV_RX2_ERROR)) { | |
2121 | if (flags & NV_RX2_ERROR4) { | |
2122 | len = nv_getlen(dev, skb->data, len); | |
2123 | if (len < 0) { | |
2124 | np->stats.rx_errors++; | |
2125 | dev_kfree_skb(skb); | |
2126 | goto next_pkt; | |
2127 | } | |
2128 | } | |
2129 | /* framing errors are soft errors */ | |
2130 | else if (flags & NV_RX2_FRAMINGERR) { | |
2131 | if (flags & NV_RX2_SUBSTRACT1) { | |
2132 | len--; | |
2133 | } | |
2134 | } | |
2135 | /* the rest are hard errors */ | |
2136 | else { | |
2137 | if (flags & NV_RX2_CRCERR) | |
2138 | np->stats.rx_crc_errors++; | |
2139 | if (flags & NV_RX2_OVERFLOW) | |
2140 | np->stats.rx_over_errors++; | |
a971c324 | 2141 | np->stats.rx_errors++; |
0d63fb32 | 2142 | dev_kfree_skb(skb); |
a971c324 AA |
2143 | goto next_pkt; |
2144 | } | |
2145 | } | |
b01867cb | 2146 | if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ { |
0d63fb32 | 2147 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
5ed2616f | 2148 | } else { |
b01867cb AA |
2149 | if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 || |
2150 | (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) { | |
2151 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
2152 | } | |
5ed2616f | 2153 | } |
b01867cb AA |
2154 | } else { |
2155 | dev_kfree_skb(skb); | |
2156 | goto next_pkt; | |
1da177e4 LT |
2157 | } |
2158 | } | |
2159 | /* got a valid packet - forward it to the network core */ | |
1da177e4 LT |
2160 | skb_put(skb, len); |
2161 | skb->protocol = eth_type_trans(skb, dev); | |
761fcd9e AA |
2162 | dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n", |
2163 | dev->name, len, skb->protocol); | |
e27cdba5 | 2164 | #ifdef CONFIG_FORCEDETH_NAPI |
b01867cb | 2165 | netif_receive_skb(skb); |
e27cdba5 | 2166 | #else |
b01867cb | 2167 | netif_rx(skb); |
e27cdba5 | 2168 | #endif |
1da177e4 LT |
2169 | dev->last_rx = jiffies; |
2170 | np->stats.rx_packets++; | |
2171 | np->stats.rx_bytes += len; | |
2172 | next_pkt: | |
b01867cb | 2173 | if (unlikely(np->get_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 2174 | np->get_rx.orig = np->first_rx.orig; |
b01867cb | 2175 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d AA |
2176 | np->get_rx_ctx = np->first_rx_ctx; |
2177 | } | |
2178 | ||
b01867cb | 2179 | return rx_processed_cnt; |
86b22b0d AA |
2180 | } |
2181 | ||
2182 | static int nv_rx_process_optimized(struct net_device *dev, int limit) | |
2183 | { | |
2184 | struct fe_priv *np = netdev_priv(dev); | |
2185 | u32 flags; | |
2186 | u32 vlanflags = 0; | |
b01867cb AA |
2187 | u32 rx_processed_cnt = 0; |
2188 | struct sk_buff *skb; | |
2189 | int len; | |
86b22b0d | 2190 | |
b01867cb AA |
2191 | while((np->get_rx.ex != np->put_rx.ex) && |
2192 | !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) && | |
2193 | (rx_processed_cnt++ < limit)) { | |
86b22b0d AA |
2194 | |
2195 | dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n", | |
2196 | dev->name, flags); | |
2197 | ||
86b22b0d AA |
2198 | /* |
2199 | * the packet is for us - immediately tear down the pci mapping. | |
2200 | * TODO: check if a prefetch of the first cacheline improves | |
2201 | * the performance. | |
2202 | */ | |
2203 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, | |
2204 | np->get_rx_ctx->dma_len, | |
2205 | PCI_DMA_FROMDEVICE); | |
2206 | skb = np->get_rx_ctx->skb; | |
2207 | np->get_rx_ctx->skb = NULL; | |
2208 | ||
2209 | { | |
2210 | int j; | |
2211 | dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags); | |
2212 | for (j=0; j<64; j++) { | |
2213 | if ((j%16) == 0) | |
2214 | dprintk("\n%03x:", j); | |
2215 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | |
2216 | } | |
2217 | dprintk("\n"); | |
761fcd9e | 2218 | } |
86b22b0d | 2219 | /* look at what we actually got: */ |
b01867cb AA |
2220 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { |
2221 | len = flags & LEN_MASK_V2; | |
2222 | if (unlikely(flags & NV_RX2_ERROR)) { | |
2223 | if (flags & NV_RX2_ERROR4) { | |
2224 | len = nv_getlen(dev, skb->data, len); | |
2225 | if (len < 0) { | |
2226 | np->stats.rx_errors++; | |
2227 | dev_kfree_skb(skb); | |
2228 | goto next_pkt; | |
2229 | } | |
2230 | } | |
2231 | /* framing errors are soft errors */ | |
2232 | else if (flags & NV_RX2_FRAMINGERR) { | |
2233 | if (flags & NV_RX2_SUBSTRACT1) { | |
2234 | len--; | |
2235 | } | |
2236 | } | |
2237 | /* the rest are hard errors */ | |
2238 | else { | |
2239 | if (flags & NV_RX2_CRCERR) | |
2240 | np->stats.rx_crc_errors++; | |
2241 | if (flags & NV_RX2_OVERFLOW) | |
2242 | np->stats.rx_over_errors++; | |
86b22b0d AA |
2243 | np->stats.rx_errors++; |
2244 | dev_kfree_skb(skb); | |
2245 | goto next_pkt; | |
2246 | } | |
2247 | } | |
b01867cb AA |
2248 | |
2249 | if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ { | |
86b22b0d AA |
2250 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2251 | } else { | |
b01867cb AA |
2252 | if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 || |
2253 | (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) { | |
2254 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
2255 | } | |
86b22b0d | 2256 | } |
b01867cb AA |
2257 | |
2258 | /* got a valid packet - forward it to the network core */ | |
2259 | skb_put(skb, len); | |
2260 | skb->protocol = eth_type_trans(skb, dev); | |
2261 | prefetch(skb->data); | |
2262 | ||
2263 | dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n", | |
2264 | dev->name, len, skb->protocol); | |
2265 | ||
2266 | if (likely(!np->vlangrp)) { | |
86b22b0d | 2267 | #ifdef CONFIG_FORCEDETH_NAPI |
b01867cb | 2268 | netif_receive_skb(skb); |
86b22b0d | 2269 | #else |
b01867cb | 2270 | netif_rx(skb); |
86b22b0d | 2271 | #endif |
b01867cb AA |
2272 | } else { |
2273 | vlanflags = le32_to_cpu(np->get_rx.ex->buflow); | |
2274 | if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) { | |
2275 | #ifdef CONFIG_FORCEDETH_NAPI | |
2276 | vlan_hwaccel_receive_skb(skb, np->vlangrp, | |
2277 | vlanflags & NV_RX3_VLAN_TAG_MASK); | |
2278 | #else | |
2279 | vlan_hwaccel_rx(skb, np->vlangrp, | |
2280 | vlanflags & NV_RX3_VLAN_TAG_MASK); | |
2281 | #endif | |
2282 | } else { | |
2283 | #ifdef CONFIG_FORCEDETH_NAPI | |
2284 | netif_receive_skb(skb); | |
2285 | #else | |
2286 | netif_rx(skb); | |
2287 | #endif | |
2288 | } | |
2289 | } | |
2290 | ||
2291 | dev->last_rx = jiffies; | |
2292 | np->stats.rx_packets++; | |
2293 | np->stats.rx_bytes += len; | |
2294 | } else { | |
2295 | dev_kfree_skb(skb); | |
2296 | } | |
86b22b0d | 2297 | next_pkt: |
b01867cb | 2298 | if (unlikely(np->get_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 2299 | np->get_rx.ex = np->first_rx.ex; |
b01867cb | 2300 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
761fcd9e | 2301 | np->get_rx_ctx = np->first_rx_ctx; |
1da177e4 | 2302 | } |
e27cdba5 | 2303 | |
b01867cb | 2304 | return rx_processed_cnt; |
1da177e4 LT |
2305 | } |
2306 | ||
d81c0983 MS |
2307 | static void set_bufsize(struct net_device *dev) |
2308 | { | |
2309 | struct fe_priv *np = netdev_priv(dev); | |
2310 | ||
2311 | if (dev->mtu <= ETH_DATA_LEN) | |
2312 | np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; | |
2313 | else | |
2314 | np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; | |
2315 | } | |
2316 | ||
1da177e4 LT |
2317 | /* |
2318 | * nv_change_mtu: dev->change_mtu function | |
2319 | * Called with dev_base_lock held for read. | |
2320 | */ | |
2321 | static int nv_change_mtu(struct net_device *dev, int new_mtu) | |
2322 | { | |
ac9c1897 | 2323 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 MS |
2324 | int old_mtu; |
2325 | ||
2326 | if (new_mtu < 64 || new_mtu > np->pkt_limit) | |
1da177e4 | 2327 | return -EINVAL; |
d81c0983 MS |
2328 | |
2329 | old_mtu = dev->mtu; | |
1da177e4 | 2330 | dev->mtu = new_mtu; |
d81c0983 MS |
2331 | |
2332 | /* return early if the buffer sizes will not change */ | |
2333 | if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) | |
2334 | return 0; | |
2335 | if (old_mtu == new_mtu) | |
2336 | return 0; | |
2337 | ||
2338 | /* synchronized against open : rtnl_lock() held by caller */ | |
2339 | if (netif_running(dev)) { | |
25097d4b | 2340 | u8 __iomem *base = get_hwbase(dev); |
d81c0983 MS |
2341 | /* |
2342 | * It seems that the nic preloads valid ring entries into an | |
2343 | * internal buffer. The procedure for flushing everything is | |
2344 | * guessed, there is probably a simpler approach. | |
2345 | * Changing the MTU is a rare event, it shouldn't matter. | |
2346 | */ | |
84b3932b | 2347 | nv_disable_irq(dev); |
932ff279 | 2348 | netif_tx_lock_bh(dev); |
d81c0983 MS |
2349 | spin_lock(&np->lock); |
2350 | /* stop engines */ | |
2351 | nv_stop_rx(dev); | |
2352 | nv_stop_tx(dev); | |
2353 | nv_txrx_reset(dev); | |
2354 | /* drain rx queue */ | |
2355 | nv_drain_rx(dev); | |
2356 | nv_drain_tx(dev); | |
2357 | /* reinit driver view of the rx queue */ | |
d81c0983 | 2358 | set_bufsize(dev); |
eafa59f6 | 2359 | if (nv_init_ring(dev)) { |
d81c0983 MS |
2360 | if (!np->in_shutdown) |
2361 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
2362 | } | |
2363 | /* reinit nic view of the rx queue */ | |
2364 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
0832b25a | 2365 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
eafa59f6 | 2366 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
d81c0983 MS |
2367 | base + NvRegRingSizes); |
2368 | pci_push(base); | |
8a4ae7f2 | 2369 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
d81c0983 MS |
2370 | pci_push(base); |
2371 | ||
2372 | /* restart rx engine */ | |
2373 | nv_start_rx(dev); | |
2374 | nv_start_tx(dev); | |
2375 | spin_unlock(&np->lock); | |
932ff279 | 2376 | netif_tx_unlock_bh(dev); |
84b3932b | 2377 | nv_enable_irq(dev); |
d81c0983 | 2378 | } |
1da177e4 LT |
2379 | return 0; |
2380 | } | |
2381 | ||
72b31782 MS |
2382 | static void nv_copy_mac_to_hw(struct net_device *dev) |
2383 | { | |
25097d4b | 2384 | u8 __iomem *base = get_hwbase(dev); |
72b31782 MS |
2385 | u32 mac[2]; |
2386 | ||
2387 | mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + | |
2388 | (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); | |
2389 | mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); | |
2390 | ||
2391 | writel(mac[0], base + NvRegMacAddrA); | |
2392 | writel(mac[1], base + NvRegMacAddrB); | |
2393 | } | |
2394 | ||
2395 | /* | |
2396 | * nv_set_mac_address: dev->set_mac_address function | |
2397 | * Called with rtnl_lock() held. | |
2398 | */ | |
2399 | static int nv_set_mac_address(struct net_device *dev, void *addr) | |
2400 | { | |
ac9c1897 | 2401 | struct fe_priv *np = netdev_priv(dev); |
72b31782 MS |
2402 | struct sockaddr *macaddr = (struct sockaddr*)addr; |
2403 | ||
f82a9352 | 2404 | if (!is_valid_ether_addr(macaddr->sa_data)) |
72b31782 MS |
2405 | return -EADDRNOTAVAIL; |
2406 | ||
2407 | /* synchronized against open : rtnl_lock() held by caller */ | |
2408 | memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); | |
2409 | ||
2410 | if (netif_running(dev)) { | |
932ff279 | 2411 | netif_tx_lock_bh(dev); |
72b31782 MS |
2412 | spin_lock_irq(&np->lock); |
2413 | ||
2414 | /* stop rx engine */ | |
2415 | nv_stop_rx(dev); | |
2416 | ||
2417 | /* set mac address */ | |
2418 | nv_copy_mac_to_hw(dev); | |
2419 | ||
2420 | /* restart rx engine */ | |
2421 | nv_start_rx(dev); | |
2422 | spin_unlock_irq(&np->lock); | |
932ff279 | 2423 | netif_tx_unlock_bh(dev); |
72b31782 MS |
2424 | } else { |
2425 | nv_copy_mac_to_hw(dev); | |
2426 | } | |
2427 | return 0; | |
2428 | } | |
2429 | ||
1da177e4 LT |
2430 | /* |
2431 | * nv_set_multicast: dev->set_multicast function | |
932ff279 | 2432 | * Called with netif_tx_lock held. |
1da177e4 LT |
2433 | */ |
2434 | static void nv_set_multicast(struct net_device *dev) | |
2435 | { | |
ac9c1897 | 2436 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
2437 | u8 __iomem *base = get_hwbase(dev); |
2438 | u32 addr[2]; | |
2439 | u32 mask[2]; | |
b6d0773f | 2440 | u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX; |
1da177e4 LT |
2441 | |
2442 | memset(addr, 0, sizeof(addr)); | |
2443 | memset(mask, 0, sizeof(mask)); | |
2444 | ||
2445 | if (dev->flags & IFF_PROMISC) { | |
b6d0773f | 2446 | pff |= NVREG_PFF_PROMISC; |
1da177e4 | 2447 | } else { |
b6d0773f | 2448 | pff |= NVREG_PFF_MYADDR; |
1da177e4 LT |
2449 | |
2450 | if (dev->flags & IFF_ALLMULTI || dev->mc_list) { | |
2451 | u32 alwaysOff[2]; | |
2452 | u32 alwaysOn[2]; | |
2453 | ||
2454 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; | |
2455 | if (dev->flags & IFF_ALLMULTI) { | |
2456 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; | |
2457 | } else { | |
2458 | struct dev_mc_list *walk; | |
2459 | ||
2460 | walk = dev->mc_list; | |
2461 | while (walk != NULL) { | |
2462 | u32 a, b; | |
2463 | a = le32_to_cpu(*(u32 *) walk->dmi_addr); | |
2464 | b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4])); | |
2465 | alwaysOn[0] &= a; | |
2466 | alwaysOff[0] &= ~a; | |
2467 | alwaysOn[1] &= b; | |
2468 | alwaysOff[1] &= ~b; | |
2469 | walk = walk->next; | |
2470 | } | |
2471 | } | |
2472 | addr[0] = alwaysOn[0]; | |
2473 | addr[1] = alwaysOn[1]; | |
2474 | mask[0] = alwaysOn[0] | alwaysOff[0]; | |
2475 | mask[1] = alwaysOn[1] | alwaysOff[1]; | |
2476 | } | |
2477 | } | |
2478 | addr[0] |= NVREG_MCASTADDRA_FORCE; | |
2479 | pff |= NVREG_PFF_ALWAYS; | |
2480 | spin_lock_irq(&np->lock); | |
2481 | nv_stop_rx(dev); | |
2482 | writel(addr[0], base + NvRegMulticastAddrA); | |
2483 | writel(addr[1], base + NvRegMulticastAddrB); | |
2484 | writel(mask[0], base + NvRegMulticastMaskA); | |
2485 | writel(mask[1], base + NvRegMulticastMaskB); | |
2486 | writel(pff, base + NvRegPacketFilterFlags); | |
2487 | dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n", | |
2488 | dev->name); | |
2489 | nv_start_rx(dev); | |
2490 | spin_unlock_irq(&np->lock); | |
2491 | } | |
2492 | ||
c7985051 | 2493 | static void nv_update_pause(struct net_device *dev, u32 pause_flags) |
b6d0773f AA |
2494 | { |
2495 | struct fe_priv *np = netdev_priv(dev); | |
2496 | u8 __iomem *base = get_hwbase(dev); | |
2497 | ||
2498 | np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE); | |
2499 | ||
2500 | if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) { | |
2501 | u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX; | |
2502 | if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) { | |
2503 | writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags); | |
2504 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
2505 | } else { | |
2506 | writel(pff, base + NvRegPacketFilterFlags); | |
2507 | } | |
2508 | } | |
2509 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) { | |
2510 | u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX; | |
2511 | if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) { | |
2512 | writel(NVREG_TX_PAUSEFRAME_ENABLE, base + NvRegTxPauseFrame); | |
2513 | writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); | |
2514 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
2515 | } else { | |
2516 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
2517 | writel(regmisc, base + NvRegMisc1); | |
2518 | } | |
2519 | } | |
2520 | } | |
2521 | ||
4ea7f299 AA |
2522 | /** |
2523 | * nv_update_linkspeed: Setup the MAC according to the link partner | |
2524 | * @dev: Network device to be configured | |
2525 | * | |
2526 | * The function queries the PHY and checks if there is a link partner. | |
2527 | * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is | |
2528 | * set to 10 MBit HD. | |
2529 | * | |
2530 | * The function returns 0 if there is no link partner and 1 if there is | |
2531 | * a good link partner. | |
2532 | */ | |
1da177e4 LT |
2533 | static int nv_update_linkspeed(struct net_device *dev) |
2534 | { | |
ac9c1897 | 2535 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2536 | u8 __iomem *base = get_hwbase(dev); |
eb91f61b AA |
2537 | int adv = 0; |
2538 | int lpa = 0; | |
2539 | int adv_lpa, adv_pause, lpa_pause; | |
1da177e4 LT |
2540 | int newls = np->linkspeed; |
2541 | int newdup = np->duplex; | |
2542 | int mii_status; | |
2543 | int retval = 0; | |
9744e218 | 2544 | u32 control_1000, status_1000, phyreg, pause_flags, txreg; |
1da177e4 LT |
2545 | |
2546 | /* BMSR_LSTATUS is latched, read it twice: | |
2547 | * we want the current value. | |
2548 | */ | |
2549 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
2550 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
2551 | ||
2552 | if (!(mii_status & BMSR_LSTATUS)) { | |
2553 | dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n", | |
2554 | dev->name); | |
2555 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
2556 | newdup = 0; | |
2557 | retval = 0; | |
2558 | goto set_speed; | |
2559 | } | |
2560 | ||
2561 | if (np->autoneg == 0) { | |
2562 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n", | |
2563 | dev->name, np->fixed_mode); | |
2564 | if (np->fixed_mode & LPA_100FULL) { | |
2565 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
2566 | newdup = 1; | |
2567 | } else if (np->fixed_mode & LPA_100HALF) { | |
2568 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
2569 | newdup = 0; | |
2570 | } else if (np->fixed_mode & LPA_10FULL) { | |
2571 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
2572 | newdup = 1; | |
2573 | } else { | |
2574 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
2575 | newdup = 0; | |
2576 | } | |
2577 | retval = 1; | |
2578 | goto set_speed; | |
2579 | } | |
2580 | /* check auto negotiation is complete */ | |
2581 | if (!(mii_status & BMSR_ANEGCOMPLETE)) { | |
2582 | /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ | |
2583 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
2584 | newdup = 0; | |
2585 | retval = 0; | |
2586 | dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name); | |
2587 | goto set_speed; | |
2588 | } | |
2589 | ||
b6d0773f AA |
2590 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
2591 | lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); | |
2592 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", | |
2593 | dev->name, adv, lpa); | |
2594 | ||
1da177e4 LT |
2595 | retval = 1; |
2596 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b AA |
2597 | control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
2598 | status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); | |
1da177e4 LT |
2599 | |
2600 | if ((control_1000 & ADVERTISE_1000FULL) && | |
2601 | (status_1000 & LPA_1000FULL)) { | |
2602 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n", | |
2603 | dev->name); | |
2604 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; | |
2605 | newdup = 1; | |
2606 | goto set_speed; | |
2607 | } | |
2608 | } | |
2609 | ||
1da177e4 | 2610 | /* FIXME: handle parallel detection properly */ |
eb91f61b AA |
2611 | adv_lpa = lpa & adv; |
2612 | if (adv_lpa & LPA_100FULL) { | |
1da177e4 LT |
2613 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
2614 | newdup = 1; | |
eb91f61b | 2615 | } else if (adv_lpa & LPA_100HALF) { |
1da177e4 LT |
2616 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
2617 | newdup = 0; | |
eb91f61b | 2618 | } else if (adv_lpa & LPA_10FULL) { |
1da177e4 LT |
2619 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
2620 | newdup = 1; | |
eb91f61b | 2621 | } else if (adv_lpa & LPA_10HALF) { |
1da177e4 LT |
2622 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
2623 | newdup = 0; | |
2624 | } else { | |
eb91f61b | 2625 | dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa); |
1da177e4 LT |
2626 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
2627 | newdup = 0; | |
2628 | } | |
2629 | ||
2630 | set_speed: | |
2631 | if (np->duplex == newdup && np->linkspeed == newls) | |
2632 | return retval; | |
2633 | ||
2634 | dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n", | |
2635 | dev->name, np->linkspeed, np->duplex, newls, newdup); | |
2636 | ||
2637 | np->duplex = newdup; | |
2638 | np->linkspeed = newls; | |
2639 | ||
2640 | if (np->gigabit == PHY_GIGABIT) { | |
2641 | phyreg = readl(base + NvRegRandomSeed); | |
2642 | phyreg &= ~(0x3FF00); | |
2643 | if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) | |
2644 | phyreg |= NVREG_RNDSEED_FORCE3; | |
2645 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) | |
2646 | phyreg |= NVREG_RNDSEED_FORCE2; | |
2647 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) | |
2648 | phyreg |= NVREG_RNDSEED_FORCE; | |
2649 | writel(phyreg, base + NvRegRandomSeed); | |
2650 | } | |
2651 | ||
2652 | phyreg = readl(base + NvRegPhyInterface); | |
2653 | phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); | |
2654 | if (np->duplex == 0) | |
2655 | phyreg |= PHY_HALF; | |
2656 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) | |
2657 | phyreg |= PHY_100; | |
2658 | else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
2659 | phyreg |= PHY_1000; | |
2660 | writel(phyreg, base + NvRegPhyInterface); | |
2661 | ||
9744e218 AA |
2662 | if (phyreg & PHY_RGMII) { |
2663 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
2664 | txreg = NVREG_TX_DEFERRAL_RGMII_1000; | |
2665 | else | |
2666 | txreg = NVREG_TX_DEFERRAL_RGMII_10_100; | |
2667 | } else { | |
2668 | txreg = NVREG_TX_DEFERRAL_DEFAULT; | |
2669 | } | |
2670 | writel(txreg, base + NvRegTxDeferral); | |
2671 | ||
95d161cb AA |
2672 | if (np->desc_ver == DESC_VER_1) { |
2673 | txreg = NVREG_TX_WM_DESC1_DEFAULT; | |
2674 | } else { | |
2675 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
2676 | txreg = NVREG_TX_WM_DESC2_3_1000; | |
2677 | else | |
2678 | txreg = NVREG_TX_WM_DESC2_3_DEFAULT; | |
2679 | } | |
2680 | writel(txreg, base + NvRegTxWatermark); | |
2681 | ||
1da177e4 LT |
2682 | writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), |
2683 | base + NvRegMisc1); | |
2684 | pci_push(base); | |
2685 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
2686 | pci_push(base); | |
2687 | ||
b6d0773f AA |
2688 | pause_flags = 0; |
2689 | /* setup pause frame */ | |
eb91f61b | 2690 | if (np->duplex != 0) { |
b6d0773f AA |
2691 | if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { |
2692 | adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM); | |
2693 | lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM); | |
2694 | ||
2695 | switch (adv_pause) { | |
f82a9352 | 2696 | case ADVERTISE_PAUSE_CAP: |
b6d0773f AA |
2697 | if (lpa_pause & LPA_PAUSE_CAP) { |
2698 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
2699 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
2700 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
2701 | } | |
2702 | break; | |
f82a9352 | 2703 | case ADVERTISE_PAUSE_ASYM: |
b6d0773f AA |
2704 | if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM)) |
2705 | { | |
2706 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
2707 | } | |
2708 | break; | |
f82a9352 | 2709 | case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM: |
b6d0773f AA |
2710 | if (lpa_pause & LPA_PAUSE_CAP) |
2711 | { | |
2712 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
2713 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
2714 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
2715 | } | |
2716 | if (lpa_pause == LPA_PAUSE_ASYM) | |
2717 | { | |
2718 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
2719 | } | |
2720 | break; | |
f3b197ac | 2721 | } |
eb91f61b | 2722 | } else { |
b6d0773f | 2723 | pause_flags = np->pause_flags; |
eb91f61b AA |
2724 | } |
2725 | } | |
b6d0773f | 2726 | nv_update_pause(dev, pause_flags); |
eb91f61b | 2727 | |
1da177e4 LT |
2728 | return retval; |
2729 | } | |
2730 | ||
2731 | static void nv_linkchange(struct net_device *dev) | |
2732 | { | |
2733 | if (nv_update_linkspeed(dev)) { | |
4ea7f299 | 2734 | if (!netif_carrier_ok(dev)) { |
1da177e4 LT |
2735 | netif_carrier_on(dev); |
2736 | printk(KERN_INFO "%s: link up.\n", dev->name); | |
4ea7f299 | 2737 | nv_start_rx(dev); |
1da177e4 | 2738 | } |
1da177e4 LT |
2739 | } else { |
2740 | if (netif_carrier_ok(dev)) { | |
2741 | netif_carrier_off(dev); | |
2742 | printk(KERN_INFO "%s: link down.\n", dev->name); | |
2743 | nv_stop_rx(dev); | |
2744 | } | |
2745 | } | |
2746 | } | |
2747 | ||
2748 | static void nv_link_irq(struct net_device *dev) | |
2749 | { | |
2750 | u8 __iomem *base = get_hwbase(dev); | |
2751 | u32 miistat; | |
2752 | ||
2753 | miistat = readl(base + NvRegMIIStatus); | |
2754 | writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); | |
2755 | dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat); | |
2756 | ||
2757 | if (miistat & (NVREG_MIISTAT_LINKCHANGE)) | |
2758 | nv_linkchange(dev); | |
2759 | dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name); | |
2760 | } | |
2761 | ||
7d12e780 | 2762 | static irqreturn_t nv_nic_irq(int foo, void *data) |
1da177e4 LT |
2763 | { |
2764 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 2765 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
2766 | u8 __iomem *base = get_hwbase(dev); |
2767 | u32 events; | |
2768 | int i; | |
2769 | ||
2770 | dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name); | |
2771 | ||
2772 | for (i=0; ; i++) { | |
d33a73c8 AA |
2773 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
2774 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
2775 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
2776 | } else { | |
2777 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
2778 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
2779 | } | |
1da177e4 LT |
2780 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
2781 | if (!(events & np->irqmask)) | |
2782 | break; | |
2783 | ||
a971c324 AA |
2784 | spin_lock(&np->lock); |
2785 | nv_tx_done(dev); | |
2786 | spin_unlock(&np->lock); | |
f3b197ac | 2787 | |
f0734ab6 AA |
2788 | #ifdef CONFIG_FORCEDETH_NAPI |
2789 | if (events & NVREG_IRQ_RX_ALL) { | |
2790 | netif_rx_schedule(dev); | |
2791 | ||
2792 | /* Disable furthur receive irq's */ | |
2793 | spin_lock(&np->lock); | |
2794 | np->irqmask &= ~NVREG_IRQ_RX_ALL; | |
2795 | ||
2796 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
2797 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
2798 | else | |
2799 | writel(np->irqmask, base + NvRegIrqMask); | |
2800 | spin_unlock(&np->lock); | |
2801 | } | |
2802 | #else | |
2803 | if (nv_rx_process(dev, dev->weight)) { | |
2804 | if (unlikely(nv_alloc_rx(dev))) { | |
2805 | spin_lock(&np->lock); | |
2806 | if (!np->in_shutdown) | |
2807 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
2808 | spin_unlock(&np->lock); | |
2809 | } | |
2810 | } | |
2811 | #endif | |
2812 | if (unlikely(events & NVREG_IRQ_LINK)) { | |
1da177e4 LT |
2813 | spin_lock(&np->lock); |
2814 | nv_link_irq(dev); | |
2815 | spin_unlock(&np->lock); | |
2816 | } | |
f0734ab6 | 2817 | if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { |
1da177e4 LT |
2818 | spin_lock(&np->lock); |
2819 | nv_linkchange(dev); | |
2820 | spin_unlock(&np->lock); | |
2821 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
2822 | } | |
f0734ab6 | 2823 | if (unlikely(events & (NVREG_IRQ_TX_ERR))) { |
1da177e4 LT |
2824 | dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
2825 | dev->name, events); | |
2826 | } | |
f0734ab6 | 2827 | if (unlikely(events & (NVREG_IRQ_UNKNOWN))) { |
1da177e4 LT |
2828 | printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
2829 | dev->name, events); | |
2830 | } | |
c5cf9101 AA |
2831 | if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) { |
2832 | spin_lock(&np->lock); | |
2833 | /* disable interrupts on the nic */ | |
2834 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
2835 | writel(0, base + NvRegIrqMask); | |
2836 | else | |
2837 | writel(np->irqmask, base + NvRegIrqMask); | |
2838 | pci_push(base); | |
2839 | ||
2840 | if (!np->in_shutdown) { | |
2841 | np->nic_poll_irq = np->irqmask; | |
2842 | np->recover_error = 1; | |
2843 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
2844 | } | |
2845 | spin_unlock(&np->lock); | |
2846 | break; | |
2847 | } | |
f0734ab6 | 2848 | if (unlikely(i > max_interrupt_work)) { |
1da177e4 LT |
2849 | spin_lock(&np->lock); |
2850 | /* disable interrupts on the nic */ | |
d33a73c8 AA |
2851 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
2852 | writel(0, base + NvRegIrqMask); | |
2853 | else | |
2854 | writel(np->irqmask, base + NvRegIrqMask); | |
1da177e4 LT |
2855 | pci_push(base); |
2856 | ||
d33a73c8 AA |
2857 | if (!np->in_shutdown) { |
2858 | np->nic_poll_irq = np->irqmask; | |
1da177e4 | 2859 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
d33a73c8 | 2860 | } |
1da177e4 LT |
2861 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i); |
2862 | spin_unlock(&np->lock); | |
2863 | break; | |
2864 | } | |
2865 | ||
2866 | } | |
2867 | dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name); | |
2868 | ||
2869 | return IRQ_RETVAL(i); | |
2870 | } | |
2871 | ||
f0734ab6 AA |
2872 | #define TX_WORK_PER_LOOP 64 |
2873 | #define RX_WORK_PER_LOOP 64 | |
2874 | /** | |
2875 | * All _optimized functions are used to help increase performance | |
2876 | * (reduce CPU and increase throughput). They use descripter version 3, | |
2877 | * compiler directives, and reduce memory accesses. | |
2878 | */ | |
86b22b0d AA |
2879 | static irqreturn_t nv_nic_irq_optimized(int foo, void *data) |
2880 | { | |
2881 | struct net_device *dev = (struct net_device *) data; | |
2882 | struct fe_priv *np = netdev_priv(dev); | |
2883 | u8 __iomem *base = get_hwbase(dev); | |
2884 | u32 events; | |
2885 | int i; | |
2886 | ||
2887 | dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name); | |
2888 | ||
2889 | for (i=0; ; i++) { | |
2890 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | |
2891 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
2892 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
2893 | } else { | |
2894 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
2895 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
2896 | } | |
86b22b0d AA |
2897 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
2898 | if (!(events & np->irqmask)) | |
2899 | break; | |
2900 | ||
2901 | spin_lock(&np->lock); | |
2902 | nv_tx_done_optimized(dev); | |
2903 | spin_unlock(&np->lock); | |
2904 | ||
f0734ab6 AA |
2905 | #ifdef CONFIG_FORCEDETH_NAPI |
2906 | if (events & NVREG_IRQ_RX_ALL) { | |
2907 | netif_rx_schedule(dev); | |
2908 | ||
2909 | /* Disable furthur receive irq's */ | |
2910 | spin_lock(&np->lock); | |
2911 | np->irqmask &= ~NVREG_IRQ_RX_ALL; | |
2912 | ||
2913 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
2914 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
2915 | else | |
2916 | writel(np->irqmask, base + NvRegIrqMask); | |
2917 | spin_unlock(&np->lock); | |
2918 | } | |
2919 | #else | |
2920 | if (nv_rx_process_optimized(dev, dev->weight)) { | |
2921 | if (unlikely(nv_alloc_rx_optimized(dev))) { | |
2922 | spin_lock(&np->lock); | |
2923 | if (!np->in_shutdown) | |
2924 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
2925 | spin_unlock(&np->lock); | |
2926 | } | |
2927 | } | |
2928 | #endif | |
2929 | if (unlikely(events & NVREG_IRQ_LINK)) { | |
86b22b0d AA |
2930 | spin_lock(&np->lock); |
2931 | nv_link_irq(dev); | |
2932 | spin_unlock(&np->lock); | |
2933 | } | |
f0734ab6 | 2934 | if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { |
86b22b0d AA |
2935 | spin_lock(&np->lock); |
2936 | nv_linkchange(dev); | |
2937 | spin_unlock(&np->lock); | |
2938 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
2939 | } | |
f0734ab6 | 2940 | if (unlikely(events & (NVREG_IRQ_TX_ERR))) { |
86b22b0d AA |
2941 | dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
2942 | dev->name, events); | |
2943 | } | |
f0734ab6 | 2944 | if (unlikely(events & (NVREG_IRQ_UNKNOWN))) { |
86b22b0d AA |
2945 | printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
2946 | dev->name, events); | |
2947 | } | |
2948 | if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) { | |
2949 | spin_lock(&np->lock); | |
2950 | /* disable interrupts on the nic */ | |
2951 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
2952 | writel(0, base + NvRegIrqMask); | |
2953 | else | |
2954 | writel(np->irqmask, base + NvRegIrqMask); | |
2955 | pci_push(base); | |
2956 | ||
2957 | if (!np->in_shutdown) { | |
2958 | np->nic_poll_irq = np->irqmask; | |
2959 | np->recover_error = 1; | |
2960 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
2961 | } | |
2962 | spin_unlock(&np->lock); | |
2963 | break; | |
2964 | } | |
2965 | ||
f0734ab6 | 2966 | if (unlikely(i > max_interrupt_work)) { |
86b22b0d AA |
2967 | spin_lock(&np->lock); |
2968 | /* disable interrupts on the nic */ | |
2969 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
2970 | writel(0, base + NvRegIrqMask); | |
2971 | else | |
2972 | writel(np->irqmask, base + NvRegIrqMask); | |
2973 | pci_push(base); | |
2974 | ||
2975 | if (!np->in_shutdown) { | |
2976 | np->nic_poll_irq = np->irqmask; | |
2977 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
2978 | } | |
2979 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i); | |
2980 | spin_unlock(&np->lock); | |
2981 | break; | |
2982 | } | |
2983 | ||
2984 | } | |
2985 | dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name); | |
2986 | ||
2987 | return IRQ_RETVAL(i); | |
2988 | } | |
2989 | ||
7d12e780 | 2990 | static irqreturn_t nv_nic_irq_tx(int foo, void *data) |
d33a73c8 AA |
2991 | { |
2992 | struct net_device *dev = (struct net_device *) data; | |
2993 | struct fe_priv *np = netdev_priv(dev); | |
2994 | u8 __iomem *base = get_hwbase(dev); | |
2995 | u32 events; | |
2996 | int i; | |
0a07bc64 | 2997 | unsigned long flags; |
d33a73c8 AA |
2998 | |
2999 | dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name); | |
3000 | ||
3001 | for (i=0; ; i++) { | |
3002 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; | |
3003 | writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3004 | dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events); |
3005 | if (!(events & np->irqmask)) | |
3006 | break; | |
3007 | ||
0a07bc64 | 3008 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 3009 | nv_tx_done_optimized(dev); |
0a07bc64 | 3010 | spin_unlock_irqrestore(&np->lock, flags); |
f3b197ac | 3011 | |
f0734ab6 | 3012 | if (unlikely(events & (NVREG_IRQ_TX_ERR))) { |
d33a73c8 AA |
3013 | dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
3014 | dev->name, events); | |
3015 | } | |
f0734ab6 | 3016 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3017 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3018 | /* disable interrupts on the nic */ |
3019 | writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); | |
3020 | pci_push(base); | |
3021 | ||
3022 | if (!np->in_shutdown) { | |
3023 | np->nic_poll_irq |= NVREG_IRQ_TX_ALL; | |
3024 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3025 | } | |
3026 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i); | |
0a07bc64 | 3027 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3028 | break; |
3029 | } | |
3030 | ||
3031 | } | |
3032 | dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name); | |
3033 | ||
3034 | return IRQ_RETVAL(i); | |
3035 | } | |
3036 | ||
e27cdba5 SH |
3037 | #ifdef CONFIG_FORCEDETH_NAPI |
3038 | static int nv_napi_poll(struct net_device *dev, int *budget) | |
3039 | { | |
3040 | int pkts, limit = min(*budget, dev->quota); | |
3041 | struct fe_priv *np = netdev_priv(dev); | |
3042 | u8 __iomem *base = get_hwbase(dev); | |
d15e9c4d | 3043 | unsigned long flags; |
e27cdba5 | 3044 | |
86b22b0d AA |
3045 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
3046 | pkts = nv_rx_process(dev, limit); | |
3047 | else | |
3048 | pkts = nv_rx_process_optimized(dev, limit); | |
e27cdba5 SH |
3049 | |
3050 | if (nv_alloc_rx(dev)) { | |
d15e9c4d | 3051 | spin_lock_irqsave(&np->lock, flags); |
e27cdba5 SH |
3052 | if (!np->in_shutdown) |
3053 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
d15e9c4d | 3054 | spin_unlock_irqrestore(&np->lock, flags); |
e27cdba5 SH |
3055 | } |
3056 | ||
3057 | if (pkts < limit) { | |
3058 | /* all done, no more packets present */ | |
3059 | netif_rx_complete(dev); | |
3060 | ||
3061 | /* re-enable receive interrupts */ | |
d15e9c4d FR |
3062 | spin_lock_irqsave(&np->lock, flags); |
3063 | ||
e27cdba5 SH |
3064 | np->irqmask |= NVREG_IRQ_RX_ALL; |
3065 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
3066 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3067 | else | |
3068 | writel(np->irqmask, base + NvRegIrqMask); | |
d15e9c4d FR |
3069 | |
3070 | spin_unlock_irqrestore(&np->lock, flags); | |
e27cdba5 SH |
3071 | return 0; |
3072 | } else { | |
3073 | /* used up our quantum, so reschedule */ | |
3074 | dev->quota -= pkts; | |
3075 | *budget -= pkts; | |
3076 | return 1; | |
3077 | } | |
3078 | } | |
3079 | #endif | |
3080 | ||
3081 | #ifdef CONFIG_FORCEDETH_NAPI | |
7d12e780 | 3082 | static irqreturn_t nv_nic_irq_rx(int foo, void *data) |
e27cdba5 SH |
3083 | { |
3084 | struct net_device *dev = (struct net_device *) data; | |
3085 | u8 __iomem *base = get_hwbase(dev); | |
3086 | u32 events; | |
3087 | ||
3088 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; | |
3089 | writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); | |
3090 | ||
3091 | if (events) { | |
3092 | netif_rx_schedule(dev); | |
3093 | /* disable receive interrupts on the nic */ | |
3094 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3095 | pci_push(base); | |
3096 | } | |
3097 | return IRQ_HANDLED; | |
3098 | } | |
3099 | #else | |
7d12e780 | 3100 | static irqreturn_t nv_nic_irq_rx(int foo, void *data) |
d33a73c8 AA |
3101 | { |
3102 | struct net_device *dev = (struct net_device *) data; | |
3103 | struct fe_priv *np = netdev_priv(dev); | |
3104 | u8 __iomem *base = get_hwbase(dev); | |
3105 | u32 events; | |
3106 | int i; | |
0a07bc64 | 3107 | unsigned long flags; |
d33a73c8 AA |
3108 | |
3109 | dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name); | |
3110 | ||
3111 | for (i=0; ; i++) { | |
3112 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; | |
3113 | writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3114 | dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events); |
3115 | if (!(events & np->irqmask)) | |
3116 | break; | |
f3b197ac | 3117 | |
f0734ab6 AA |
3118 | if (nv_rx_process_optimized(dev, dev->weight)) { |
3119 | if (unlikely(nv_alloc_rx_optimized(dev))) { | |
3120 | spin_lock_irqsave(&np->lock, flags); | |
3121 | if (!np->in_shutdown) | |
3122 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3123 | spin_unlock_irqrestore(&np->lock, flags); | |
3124 | } | |
d33a73c8 | 3125 | } |
f3b197ac | 3126 | |
f0734ab6 | 3127 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3128 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3129 | /* disable interrupts on the nic */ |
3130 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3131 | pci_push(base); | |
3132 | ||
3133 | if (!np->in_shutdown) { | |
3134 | np->nic_poll_irq |= NVREG_IRQ_RX_ALL; | |
3135 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3136 | } | |
3137 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i); | |
0a07bc64 | 3138 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3139 | break; |
3140 | } | |
d33a73c8 AA |
3141 | } |
3142 | dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name); | |
3143 | ||
3144 | return IRQ_RETVAL(i); | |
3145 | } | |
e27cdba5 | 3146 | #endif |
d33a73c8 | 3147 | |
7d12e780 | 3148 | static irqreturn_t nv_nic_irq_other(int foo, void *data) |
d33a73c8 AA |
3149 | { |
3150 | struct net_device *dev = (struct net_device *) data; | |
3151 | struct fe_priv *np = netdev_priv(dev); | |
3152 | u8 __iomem *base = get_hwbase(dev); | |
3153 | u32 events; | |
3154 | int i; | |
0a07bc64 | 3155 | unsigned long flags; |
d33a73c8 AA |
3156 | |
3157 | dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name); | |
3158 | ||
3159 | for (i=0; ; i++) { | |
3160 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; | |
3161 | writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3162 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
3163 | if (!(events & np->irqmask)) | |
3164 | break; | |
f3b197ac | 3165 | |
d33a73c8 | 3166 | if (events & NVREG_IRQ_LINK) { |
0a07bc64 | 3167 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3168 | nv_link_irq(dev); |
0a07bc64 | 3169 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3170 | } |
3171 | if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { | |
0a07bc64 | 3172 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3173 | nv_linkchange(dev); |
0a07bc64 | 3174 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3175 | np->link_timeout = jiffies + LINK_TIMEOUT; |
3176 | } | |
c5cf9101 AA |
3177 | if (events & NVREG_IRQ_RECOVER_ERROR) { |
3178 | spin_lock_irq(&np->lock); | |
3179 | /* disable interrupts on the nic */ | |
3180 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3181 | pci_push(base); | |
3182 | ||
3183 | if (!np->in_shutdown) { | |
3184 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3185 | np->recover_error = 1; | |
3186 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3187 | } | |
3188 | spin_unlock_irq(&np->lock); | |
3189 | break; | |
3190 | } | |
d33a73c8 AA |
3191 | if (events & (NVREG_IRQ_UNKNOWN)) { |
3192 | printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", | |
3193 | dev->name, events); | |
3194 | } | |
f0734ab6 | 3195 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3196 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3197 | /* disable interrupts on the nic */ |
3198 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3199 | pci_push(base); | |
3200 | ||
3201 | if (!np->in_shutdown) { | |
3202 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3203 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3204 | } | |
3205 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i); | |
0a07bc64 | 3206 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3207 | break; |
3208 | } | |
3209 | ||
3210 | } | |
3211 | dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name); | |
3212 | ||
3213 | return IRQ_RETVAL(i); | |
3214 | } | |
3215 | ||
7d12e780 | 3216 | static irqreturn_t nv_nic_irq_test(int foo, void *data) |
9589c77a AA |
3217 | { |
3218 | struct net_device *dev = (struct net_device *) data; | |
3219 | struct fe_priv *np = netdev_priv(dev); | |
3220 | u8 __iomem *base = get_hwbase(dev); | |
3221 | u32 events; | |
3222 | ||
3223 | dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name); | |
3224 | ||
3225 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | |
3226 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
3227 | writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus); | |
3228 | } else { | |
3229 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
3230 | writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); | |
3231 | } | |
3232 | pci_push(base); | |
3233 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); | |
3234 | if (!(events & NVREG_IRQ_TIMER)) | |
3235 | return IRQ_RETVAL(0); | |
3236 | ||
3237 | spin_lock(&np->lock); | |
3238 | np->intr_test = 1; | |
3239 | spin_unlock(&np->lock); | |
3240 | ||
3241 | dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name); | |
3242 | ||
3243 | return IRQ_RETVAL(1); | |
3244 | } | |
3245 | ||
7a1854b7 AA |
3246 | static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
3247 | { | |
3248 | u8 __iomem *base = get_hwbase(dev); | |
3249 | int i; | |
3250 | u32 msixmap = 0; | |
3251 | ||
3252 | /* Each interrupt bit can be mapped to a MSIX vector (4 bits). | |
3253 | * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents | |
3254 | * the remaining 8 interrupts. | |
3255 | */ | |
3256 | for (i = 0; i < 8; i++) { | |
3257 | if ((irqmask >> i) & 0x1) { | |
3258 | msixmap |= vector << (i << 2); | |
3259 | } | |
3260 | } | |
3261 | writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); | |
3262 | ||
3263 | msixmap = 0; | |
3264 | for (i = 0; i < 8; i++) { | |
3265 | if ((irqmask >> (i + 8)) & 0x1) { | |
3266 | msixmap |= vector << (i << 2); | |
3267 | } | |
3268 | } | |
3269 | writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); | |
3270 | } | |
3271 | ||
9589c77a | 3272 | static int nv_request_irq(struct net_device *dev, int intr_test) |
7a1854b7 AA |
3273 | { |
3274 | struct fe_priv *np = get_nvpriv(dev); | |
3275 | u8 __iomem *base = get_hwbase(dev); | |
3276 | int ret = 1; | |
3277 | int i; | |
86b22b0d AA |
3278 | irqreturn_t (*handler)(int foo, void *data); |
3279 | ||
3280 | if (intr_test) { | |
3281 | handler = nv_nic_irq_test; | |
3282 | } else { | |
3283 | if (np->desc_ver == DESC_VER_3) | |
3284 | handler = nv_nic_irq_optimized; | |
3285 | else | |
3286 | handler = nv_nic_irq; | |
3287 | } | |
7a1854b7 AA |
3288 | |
3289 | if (np->msi_flags & NV_MSI_X_CAPABLE) { | |
3290 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { | |
3291 | np->msi_x_entry[i].entry = i; | |
3292 | } | |
3293 | if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) { | |
3294 | np->msi_flags |= NV_MSI_X_ENABLED; | |
9589c77a | 3295 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { |
7a1854b7 | 3296 | /* Request irq for rx handling */ |
1fb9df5d | 3297 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3298 | printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); |
3299 | pci_disable_msix(np->pci_dev); | |
3300 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3301 | goto out_err; | |
3302 | } | |
3303 | /* Request irq for tx handling */ | |
1fb9df5d | 3304 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3305 | printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); |
3306 | pci_disable_msix(np->pci_dev); | |
3307 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3308 | goto out_free_rx; | |
3309 | } | |
3310 | /* Request irq for link and timer handling */ | |
1fb9df5d | 3311 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3312 | printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); |
3313 | pci_disable_msix(np->pci_dev); | |
3314 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3315 | goto out_free_tx; | |
3316 | } | |
3317 | /* map interrupts to their respective vector */ | |
3318 | writel(0, base + NvRegMSIXMap0); | |
3319 | writel(0, base + NvRegMSIXMap1); | |
3320 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); | |
3321 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); | |
3322 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); | |
3323 | } else { | |
3324 | /* Request irq for all interrupts */ | |
86b22b0d | 3325 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3326 | printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
3327 | pci_disable_msix(np->pci_dev); | |
3328 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3329 | goto out_err; | |
3330 | } | |
3331 | ||
3332 | /* map interrupts to vector 0 */ | |
3333 | writel(0, base + NvRegMSIXMap0); | |
3334 | writel(0, base + NvRegMSIXMap1); | |
3335 | } | |
3336 | } | |
3337 | } | |
3338 | if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { | |
3339 | if ((ret = pci_enable_msi(np->pci_dev)) == 0) { | |
3340 | np->msi_flags |= NV_MSI_ENABLED; | |
86b22b0d | 3341 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3342 | printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
3343 | pci_disable_msi(np->pci_dev); | |
3344 | np->msi_flags &= ~NV_MSI_ENABLED; | |
3345 | goto out_err; | |
3346 | } | |
3347 | ||
3348 | /* map interrupts to vector 0 */ | |
3349 | writel(0, base + NvRegMSIMap0); | |
3350 | writel(0, base + NvRegMSIMap1); | |
3351 | /* enable msi vector 0 */ | |
3352 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
3353 | } | |
3354 | } | |
3355 | if (ret != 0) { | |
86b22b0d | 3356 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) |
7a1854b7 | 3357 | goto out_err; |
9589c77a | 3358 | |
7a1854b7 AA |
3359 | } |
3360 | ||
3361 | return 0; | |
3362 | out_free_tx: | |
3363 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); | |
3364 | out_free_rx: | |
3365 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); | |
3366 | out_err: | |
3367 | return 1; | |
3368 | } | |
3369 | ||
3370 | static void nv_free_irq(struct net_device *dev) | |
3371 | { | |
3372 | struct fe_priv *np = get_nvpriv(dev); | |
3373 | int i; | |
3374 | ||
3375 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
3376 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { | |
3377 | free_irq(np->msi_x_entry[i].vector, dev); | |
3378 | } | |
3379 | pci_disable_msix(np->pci_dev); | |
3380 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3381 | } else { | |
3382 | free_irq(np->pci_dev->irq, dev); | |
3383 | if (np->msi_flags & NV_MSI_ENABLED) { | |
3384 | pci_disable_msi(np->pci_dev); | |
3385 | np->msi_flags &= ~NV_MSI_ENABLED; | |
3386 | } | |
3387 | } | |
3388 | } | |
3389 | ||
1da177e4 LT |
3390 | static void nv_do_nic_poll(unsigned long data) |
3391 | { | |
3392 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 3393 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3394 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 3395 | u32 mask = 0; |
1da177e4 | 3396 | |
1da177e4 | 3397 | /* |
d33a73c8 | 3398 | * First disable irq(s) and then |
1da177e4 LT |
3399 | * reenable interrupts on the nic, we have to do this before calling |
3400 | * nv_nic_irq because that may decide to do otherwise | |
3401 | */ | |
d33a73c8 | 3402 | |
84b3932b AA |
3403 | if (!using_multi_irqs(dev)) { |
3404 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
8688cfce | 3405 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
84b3932b | 3406 | else |
8688cfce | 3407 | disable_irq_lockdep(dev->irq); |
d33a73c8 AA |
3408 | mask = np->irqmask; |
3409 | } else { | |
3410 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
8688cfce | 3411 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
d33a73c8 AA |
3412 | mask |= NVREG_IRQ_RX_ALL; |
3413 | } | |
3414 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
8688cfce | 3415 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
d33a73c8 AA |
3416 | mask |= NVREG_IRQ_TX_ALL; |
3417 | } | |
3418 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
8688cfce | 3419 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
d33a73c8 AA |
3420 | mask |= NVREG_IRQ_OTHER; |
3421 | } | |
3422 | } | |
3423 | np->nic_poll_irq = 0; | |
3424 | ||
c5cf9101 AA |
3425 | if (np->recover_error) { |
3426 | np->recover_error = 0; | |
3427 | printk(KERN_INFO "forcedeth: MAC in recoverable error state\n"); | |
3428 | if (netif_running(dev)) { | |
3429 | netif_tx_lock_bh(dev); | |
3430 | spin_lock(&np->lock); | |
3431 | /* stop engines */ | |
3432 | nv_stop_rx(dev); | |
3433 | nv_stop_tx(dev); | |
3434 | nv_txrx_reset(dev); | |
3435 | /* drain rx queue */ | |
3436 | nv_drain_rx(dev); | |
3437 | nv_drain_tx(dev); | |
3438 | /* reinit driver view of the rx queue */ | |
3439 | set_bufsize(dev); | |
3440 | if (nv_init_ring(dev)) { | |
3441 | if (!np->in_shutdown) | |
3442 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3443 | } | |
3444 | /* reinit nic view of the rx queue */ | |
3445 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
3446 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
3447 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | |
3448 | base + NvRegRingSizes); | |
3449 | pci_push(base); | |
3450 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
3451 | pci_push(base); | |
3452 | ||
3453 | /* restart rx engine */ | |
3454 | nv_start_rx(dev); | |
3455 | nv_start_tx(dev); | |
3456 | spin_unlock(&np->lock); | |
3457 | netif_tx_unlock_bh(dev); | |
3458 | } | |
3459 | } | |
3460 | ||
d33a73c8 | 3461 | /* FIXME: Do we need synchronize_irq(dev->irq) here? */ |
f3b197ac | 3462 | |
d33a73c8 | 3463 | writel(mask, base + NvRegIrqMask); |
1da177e4 | 3464 | pci_push(base); |
d33a73c8 | 3465 | |
84b3932b | 3466 | if (!using_multi_irqs(dev)) { |
7d12e780 | 3467 | nv_nic_irq(0, dev); |
84b3932b | 3468 | if (np->msi_flags & NV_MSI_X_ENABLED) |
8688cfce | 3469 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
84b3932b | 3470 | else |
8688cfce | 3471 | enable_irq_lockdep(dev->irq); |
d33a73c8 AA |
3472 | } else { |
3473 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
7d12e780 | 3474 | nv_nic_irq_rx(0, dev); |
8688cfce | 3475 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
d33a73c8 AA |
3476 | } |
3477 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
7d12e780 | 3478 | nv_nic_irq_tx(0, dev); |
8688cfce | 3479 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
d33a73c8 AA |
3480 | } |
3481 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
7d12e780 | 3482 | nv_nic_irq_other(0, dev); |
8688cfce | 3483 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
d33a73c8 AA |
3484 | } |
3485 | } | |
1da177e4 LT |
3486 | } |
3487 | ||
2918c35d MS |
3488 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3489 | static void nv_poll_controller(struct net_device *dev) | |
3490 | { | |
3491 | nv_do_nic_poll((unsigned long) dev); | |
3492 | } | |
3493 | #endif | |
3494 | ||
52da3578 AA |
3495 | static void nv_do_stats_poll(unsigned long data) |
3496 | { | |
3497 | struct net_device *dev = (struct net_device *) data; | |
3498 | struct fe_priv *np = netdev_priv(dev); | |
3499 | u8 __iomem *base = get_hwbase(dev); | |
3500 | ||
3501 | np->estats.tx_bytes += readl(base + NvRegTxCnt); | |
3502 | np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); | |
3503 | np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); | |
3504 | np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); | |
3505 | np->estats.tx_late_collision += readl(base + NvRegTxLateCol); | |
3506 | np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); | |
3507 | np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); | |
3508 | np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); | |
3509 | np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); | |
3510 | np->estats.tx_deferral += readl(base + NvRegTxDef); | |
3511 | np->estats.tx_packets += readl(base + NvRegTxFrame); | |
3512 | np->estats.tx_pause += readl(base + NvRegTxPause); | |
3513 | np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); | |
3514 | np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); | |
3515 | np->estats.rx_late_collision += readl(base + NvRegRxLateCol); | |
3516 | np->estats.rx_runt += readl(base + NvRegRxRunt); | |
3517 | np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); | |
3518 | np->estats.rx_over_errors += readl(base + NvRegRxOverflow); | |
3519 | np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); | |
3520 | np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); | |
3521 | np->estats.rx_length_error += readl(base + NvRegRxLenErr); | |
3522 | np->estats.rx_unicast += readl(base + NvRegRxUnicast); | |
3523 | np->estats.rx_multicast += readl(base + NvRegRxMulticast); | |
3524 | np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); | |
3525 | np->estats.rx_bytes += readl(base + NvRegRxCnt); | |
3526 | np->estats.rx_pause += readl(base + NvRegRxPause); | |
3527 | np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); | |
3528 | np->estats.rx_packets = | |
3529 | np->estats.rx_unicast + | |
3530 | np->estats.rx_multicast + | |
3531 | np->estats.rx_broadcast; | |
3532 | np->estats.rx_errors_total = | |
3533 | np->estats.rx_crc_errors + | |
3534 | np->estats.rx_over_errors + | |
3535 | np->estats.rx_frame_error + | |
3536 | (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) + | |
3537 | np->estats.rx_late_collision + | |
3538 | np->estats.rx_runt + | |
3539 | np->estats.rx_frame_too_long; | |
3540 | ||
3541 | if (!np->in_shutdown) | |
3542 | mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL); | |
3543 | } | |
3544 | ||
1da177e4 LT |
3545 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
3546 | { | |
ac9c1897 | 3547 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
3548 | strcpy(info->driver, "forcedeth"); |
3549 | strcpy(info->version, FORCEDETH_VERSION); | |
3550 | strcpy(info->bus_info, pci_name(np->pci_dev)); | |
3551 | } | |
3552 | ||
3553 | static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
3554 | { | |
ac9c1897 | 3555 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
3556 | wolinfo->supported = WAKE_MAGIC; |
3557 | ||
3558 | spin_lock_irq(&np->lock); | |
3559 | if (np->wolenabled) | |
3560 | wolinfo->wolopts = WAKE_MAGIC; | |
3561 | spin_unlock_irq(&np->lock); | |
3562 | } | |
3563 | ||
3564 | static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
3565 | { | |
ac9c1897 | 3566 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3567 | u8 __iomem *base = get_hwbase(dev); |
c42d9df9 | 3568 | u32 flags = 0; |
1da177e4 | 3569 | |
1da177e4 | 3570 | if (wolinfo->wolopts == 0) { |
1da177e4 | 3571 | np->wolenabled = 0; |
c42d9df9 | 3572 | } else if (wolinfo->wolopts & WAKE_MAGIC) { |
1da177e4 | 3573 | np->wolenabled = 1; |
c42d9df9 AA |
3574 | flags = NVREG_WAKEUPFLAGS_ENABLE; |
3575 | } | |
3576 | if (netif_running(dev)) { | |
3577 | spin_lock_irq(&np->lock); | |
3578 | writel(flags, base + NvRegWakeUpFlags); | |
3579 | spin_unlock_irq(&np->lock); | |
1da177e4 | 3580 | } |
1da177e4 LT |
3581 | return 0; |
3582 | } | |
3583 | ||
3584 | static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
3585 | { | |
3586 | struct fe_priv *np = netdev_priv(dev); | |
3587 | int adv; | |
3588 | ||
3589 | spin_lock_irq(&np->lock); | |
3590 | ecmd->port = PORT_MII; | |
3591 | if (!netif_running(dev)) { | |
3592 | /* We do not track link speed / duplex setting if the | |
3593 | * interface is disabled. Force a link check */ | |
f9430a01 AA |
3594 | if (nv_update_linkspeed(dev)) { |
3595 | if (!netif_carrier_ok(dev)) | |
3596 | netif_carrier_on(dev); | |
3597 | } else { | |
3598 | if (netif_carrier_ok(dev)) | |
3599 | netif_carrier_off(dev); | |
3600 | } | |
1da177e4 | 3601 | } |
f9430a01 AA |
3602 | |
3603 | if (netif_carrier_ok(dev)) { | |
3604 | switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) { | |
1da177e4 LT |
3605 | case NVREG_LINKSPEED_10: |
3606 | ecmd->speed = SPEED_10; | |
3607 | break; | |
3608 | case NVREG_LINKSPEED_100: | |
3609 | ecmd->speed = SPEED_100; | |
3610 | break; | |
3611 | case NVREG_LINKSPEED_1000: | |
3612 | ecmd->speed = SPEED_1000; | |
3613 | break; | |
f9430a01 AA |
3614 | } |
3615 | ecmd->duplex = DUPLEX_HALF; | |
3616 | if (np->duplex) | |
3617 | ecmd->duplex = DUPLEX_FULL; | |
3618 | } else { | |
3619 | ecmd->speed = -1; | |
3620 | ecmd->duplex = -1; | |
1da177e4 | 3621 | } |
1da177e4 LT |
3622 | |
3623 | ecmd->autoneg = np->autoneg; | |
3624 | ||
3625 | ecmd->advertising = ADVERTISED_MII; | |
3626 | if (np->autoneg) { | |
3627 | ecmd->advertising |= ADVERTISED_Autoneg; | |
3628 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
f9430a01 AA |
3629 | if (adv & ADVERTISE_10HALF) |
3630 | ecmd->advertising |= ADVERTISED_10baseT_Half; | |
3631 | if (adv & ADVERTISE_10FULL) | |
3632 | ecmd->advertising |= ADVERTISED_10baseT_Full; | |
3633 | if (adv & ADVERTISE_100HALF) | |
3634 | ecmd->advertising |= ADVERTISED_100baseT_Half; | |
3635 | if (adv & ADVERTISE_100FULL) | |
3636 | ecmd->advertising |= ADVERTISED_100baseT_Full; | |
3637 | if (np->gigabit == PHY_GIGABIT) { | |
3638 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); | |
3639 | if (adv & ADVERTISE_1000FULL) | |
3640 | ecmd->advertising |= ADVERTISED_1000baseT_Full; | |
3641 | } | |
1da177e4 | 3642 | } |
1da177e4 LT |
3643 | ecmd->supported = (SUPPORTED_Autoneg | |
3644 | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | | |
3645 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | | |
3646 | SUPPORTED_MII); | |
3647 | if (np->gigabit == PHY_GIGABIT) | |
3648 | ecmd->supported |= SUPPORTED_1000baseT_Full; | |
3649 | ||
3650 | ecmd->phy_address = np->phyaddr; | |
3651 | ecmd->transceiver = XCVR_EXTERNAL; | |
3652 | ||
3653 | /* ignore maxtxpkt, maxrxpkt for now */ | |
3654 | spin_unlock_irq(&np->lock); | |
3655 | return 0; | |
3656 | } | |
3657 | ||
3658 | static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
3659 | { | |
3660 | struct fe_priv *np = netdev_priv(dev); | |
3661 | ||
3662 | if (ecmd->port != PORT_MII) | |
3663 | return -EINVAL; | |
3664 | if (ecmd->transceiver != XCVR_EXTERNAL) | |
3665 | return -EINVAL; | |
3666 | if (ecmd->phy_address != np->phyaddr) { | |
3667 | /* TODO: support switching between multiple phys. Should be | |
3668 | * trivial, but not enabled due to lack of test hardware. */ | |
3669 | return -EINVAL; | |
3670 | } | |
3671 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
3672 | u32 mask; | |
3673 | ||
3674 | mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
3675 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; | |
3676 | if (np->gigabit == PHY_GIGABIT) | |
3677 | mask |= ADVERTISED_1000baseT_Full; | |
3678 | ||
3679 | if ((ecmd->advertising & mask) == 0) | |
3680 | return -EINVAL; | |
3681 | ||
3682 | } else if (ecmd->autoneg == AUTONEG_DISABLE) { | |
3683 | /* Note: autonegotiation disable, speed 1000 intentionally | |
3684 | * forbidden - noone should need that. */ | |
3685 | ||
3686 | if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) | |
3687 | return -EINVAL; | |
3688 | if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) | |
3689 | return -EINVAL; | |
3690 | } else { | |
3691 | return -EINVAL; | |
3692 | } | |
3693 | ||
f9430a01 AA |
3694 | netif_carrier_off(dev); |
3695 | if (netif_running(dev)) { | |
3696 | nv_disable_irq(dev); | |
58dfd9c1 | 3697 | netif_tx_lock_bh(dev); |
f9430a01 AA |
3698 | spin_lock(&np->lock); |
3699 | /* stop engines */ | |
3700 | nv_stop_rx(dev); | |
3701 | nv_stop_tx(dev); | |
3702 | spin_unlock(&np->lock); | |
58dfd9c1 | 3703 | netif_tx_unlock_bh(dev); |
f9430a01 AA |
3704 | } |
3705 | ||
1da177e4 LT |
3706 | if (ecmd->autoneg == AUTONEG_ENABLE) { |
3707 | int adv, bmcr; | |
3708 | ||
3709 | np->autoneg = 1; | |
3710 | ||
3711 | /* advertise only what has been requested */ | |
3712 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 3713 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
1da177e4 LT |
3714 | if (ecmd->advertising & ADVERTISED_10baseT_Half) |
3715 | adv |= ADVERTISE_10HALF; | |
3716 | if (ecmd->advertising & ADVERTISED_10baseT_Full) | |
b6d0773f | 3717 | adv |= ADVERTISE_10FULL; |
1da177e4 LT |
3718 | if (ecmd->advertising & ADVERTISED_100baseT_Half) |
3719 | adv |= ADVERTISE_100HALF; | |
3720 | if (ecmd->advertising & ADVERTISED_100baseT_Full) | |
b6d0773f AA |
3721 | adv |= ADVERTISE_100FULL; |
3722 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ | |
3723 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
3724 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3725 | adv |= ADVERTISE_PAUSE_ASYM; | |
1da177e4 LT |
3726 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
3727 | ||
3728 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 3729 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 LT |
3730 | adv &= ~ADVERTISE_1000FULL; |
3731 | if (ecmd->advertising & ADVERTISED_1000baseT_Full) | |
3732 | adv |= ADVERTISE_1000FULL; | |
eb91f61b | 3733 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
3734 | } |
3735 | ||
f9430a01 AA |
3736 | if (netif_running(dev)) |
3737 | printk(KERN_INFO "%s: link down.\n", dev->name); | |
1da177e4 | 3738 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
3739 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
3740 | bmcr |= BMCR_ANENABLE; | |
3741 | /* reset the phy in order for settings to stick, | |
3742 | * and cause autoneg to start */ | |
3743 | if (phy_reset(dev, bmcr)) { | |
3744 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); | |
3745 | return -EINVAL; | |
3746 | } | |
3747 | } else { | |
3748 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
3749 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
3750 | } | |
1da177e4 LT |
3751 | } else { |
3752 | int adv, bmcr; | |
3753 | ||
3754 | np->autoneg = 0; | |
3755 | ||
3756 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 3757 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
1da177e4 LT |
3758 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF) |
3759 | adv |= ADVERTISE_10HALF; | |
3760 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL) | |
b6d0773f | 3761 | adv |= ADVERTISE_10FULL; |
1da177e4 LT |
3762 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF) |
3763 | adv |= ADVERTISE_100HALF; | |
3764 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL) | |
b6d0773f AA |
3765 | adv |= ADVERTISE_100FULL; |
3766 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
3767 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */ | |
3768 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
3769 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3770 | } | |
3771 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) { | |
3772 | adv |= ADVERTISE_PAUSE_ASYM; | |
3773 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3774 | } | |
1da177e4 LT |
3775 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
3776 | np->fixed_mode = adv; | |
3777 | ||
3778 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 3779 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 | 3780 | adv &= ~ADVERTISE_1000FULL; |
eb91f61b | 3781 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
3782 | } |
3783 | ||
3784 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
f9430a01 AA |
3785 | bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX); |
3786 | if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL)) | |
1da177e4 | 3787 | bmcr |= BMCR_FULLDPLX; |
f9430a01 | 3788 | if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
1da177e4 | 3789 | bmcr |= BMCR_SPEED100; |
f9430a01 | 3790 | if (np->phy_oui == PHY_OUI_MARVELL) { |
edf7e5ec AA |
3791 | /* reset the phy in order for forced mode settings to stick */ |
3792 | if (phy_reset(dev, bmcr)) { | |
f9430a01 AA |
3793 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); |
3794 | return -EINVAL; | |
3795 | } | |
edf7e5ec AA |
3796 | } else { |
3797 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
3798 | if (netif_running(dev)) { | |
3799 | /* Wait a bit and then reconfigure the nic. */ | |
3800 | udelay(10); | |
3801 | nv_linkchange(dev); | |
3802 | } | |
1da177e4 LT |
3803 | } |
3804 | } | |
f9430a01 AA |
3805 | |
3806 | if (netif_running(dev)) { | |
3807 | nv_start_rx(dev); | |
3808 | nv_start_tx(dev); | |
3809 | nv_enable_irq(dev); | |
3810 | } | |
1da177e4 LT |
3811 | |
3812 | return 0; | |
3813 | } | |
3814 | ||
dc8216c1 | 3815 | #define FORCEDETH_REGS_VER 1 |
dc8216c1 MS |
3816 | |
3817 | static int nv_get_regs_len(struct net_device *dev) | |
3818 | { | |
86a0f043 AA |
3819 | struct fe_priv *np = netdev_priv(dev); |
3820 | return np->register_size; | |
dc8216c1 MS |
3821 | } |
3822 | ||
3823 | static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) | |
3824 | { | |
ac9c1897 | 3825 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
3826 | u8 __iomem *base = get_hwbase(dev); |
3827 | u32 *rbuf = buf; | |
3828 | int i; | |
3829 | ||
3830 | regs->version = FORCEDETH_REGS_VER; | |
3831 | spin_lock_irq(&np->lock); | |
86a0f043 | 3832 | for (i = 0;i <= np->register_size/sizeof(u32); i++) |
dc8216c1 MS |
3833 | rbuf[i] = readl(base + i*sizeof(u32)); |
3834 | spin_unlock_irq(&np->lock); | |
3835 | } | |
3836 | ||
3837 | static int nv_nway_reset(struct net_device *dev) | |
3838 | { | |
ac9c1897 | 3839 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
3840 | int ret; |
3841 | ||
dc8216c1 MS |
3842 | if (np->autoneg) { |
3843 | int bmcr; | |
3844 | ||
f9430a01 AA |
3845 | netif_carrier_off(dev); |
3846 | if (netif_running(dev)) { | |
3847 | nv_disable_irq(dev); | |
58dfd9c1 | 3848 | netif_tx_lock_bh(dev); |
f9430a01 AA |
3849 | spin_lock(&np->lock); |
3850 | /* stop engines */ | |
3851 | nv_stop_rx(dev); | |
3852 | nv_stop_tx(dev); | |
3853 | spin_unlock(&np->lock); | |
58dfd9c1 | 3854 | netif_tx_unlock_bh(dev); |
f9430a01 AA |
3855 | printk(KERN_INFO "%s: link down.\n", dev->name); |
3856 | } | |
3857 | ||
dc8216c1 | 3858 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
3859 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
3860 | bmcr |= BMCR_ANENABLE; | |
3861 | /* reset the phy in order for settings to stick*/ | |
3862 | if (phy_reset(dev, bmcr)) { | |
3863 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); | |
3864 | return -EINVAL; | |
3865 | } | |
3866 | } else { | |
3867 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
3868 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
3869 | } | |
dc8216c1 | 3870 | |
f9430a01 AA |
3871 | if (netif_running(dev)) { |
3872 | nv_start_rx(dev); | |
3873 | nv_start_tx(dev); | |
3874 | nv_enable_irq(dev); | |
3875 | } | |
dc8216c1 MS |
3876 | ret = 0; |
3877 | } else { | |
3878 | ret = -EINVAL; | |
3879 | } | |
dc8216c1 MS |
3880 | |
3881 | return ret; | |
3882 | } | |
3883 | ||
0674d594 ZA |
3884 | static int nv_set_tso(struct net_device *dev, u32 value) |
3885 | { | |
3886 | struct fe_priv *np = netdev_priv(dev); | |
3887 | ||
3888 | if ((np->driver_data & DEV_HAS_CHECKSUM)) | |
3889 | return ethtool_op_set_tso(dev, value); | |
3890 | else | |
6a78814f | 3891 | return -EOPNOTSUPP; |
0674d594 | 3892 | } |
0674d594 | 3893 | |
eafa59f6 AA |
3894 | static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
3895 | { | |
3896 | struct fe_priv *np = netdev_priv(dev); | |
3897 | ||
3898 | ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
3899 | ring->rx_mini_max_pending = 0; | |
3900 | ring->rx_jumbo_max_pending = 0; | |
3901 | ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
3902 | ||
3903 | ring->rx_pending = np->rx_ring_size; | |
3904 | ring->rx_mini_pending = 0; | |
3905 | ring->rx_jumbo_pending = 0; | |
3906 | ring->tx_pending = np->tx_ring_size; | |
3907 | } | |
3908 | ||
3909 | static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) | |
3910 | { | |
3911 | struct fe_priv *np = netdev_priv(dev); | |
3912 | u8 __iomem *base = get_hwbase(dev); | |
761fcd9e | 3913 | u8 *rxtx_ring, *rx_skbuff, *tx_skbuff; |
eafa59f6 AA |
3914 | dma_addr_t ring_addr; |
3915 | ||
3916 | if (ring->rx_pending < RX_RING_MIN || | |
3917 | ring->tx_pending < TX_RING_MIN || | |
3918 | ring->rx_mini_pending != 0 || | |
3919 | ring->rx_jumbo_pending != 0 || | |
3920 | (np->desc_ver == DESC_VER_1 && | |
3921 | (ring->rx_pending > RING_MAX_DESC_VER_1 || | |
3922 | ring->tx_pending > RING_MAX_DESC_VER_1)) || | |
3923 | (np->desc_ver != DESC_VER_1 && | |
3924 | (ring->rx_pending > RING_MAX_DESC_VER_2_3 || | |
3925 | ring->tx_pending > RING_MAX_DESC_VER_2_3))) { | |
3926 | return -EINVAL; | |
3927 | } | |
3928 | ||
3929 | /* allocate new rings */ | |
3930 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { | |
3931 | rxtx_ring = pci_alloc_consistent(np->pci_dev, | |
3932 | sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), | |
3933 | &ring_addr); | |
3934 | } else { | |
3935 | rxtx_ring = pci_alloc_consistent(np->pci_dev, | |
3936 | sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
3937 | &ring_addr); | |
3938 | } | |
761fcd9e AA |
3939 | rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL); |
3940 | tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL); | |
3941 | if (!rxtx_ring || !rx_skbuff || !tx_skbuff) { | |
eafa59f6 AA |
3942 | /* fall back to old rings */ |
3943 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { | |
f82a9352 | 3944 | if (rxtx_ring) |
eafa59f6 AA |
3945 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), |
3946 | rxtx_ring, ring_addr); | |
3947 | } else { | |
3948 | if (rxtx_ring) | |
3949 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
3950 | rxtx_ring, ring_addr); | |
3951 | } | |
3952 | if (rx_skbuff) | |
3953 | kfree(rx_skbuff); | |
eafa59f6 AA |
3954 | if (tx_skbuff) |
3955 | kfree(tx_skbuff); | |
eafa59f6 AA |
3956 | goto exit; |
3957 | } | |
3958 | ||
3959 | if (netif_running(dev)) { | |
3960 | nv_disable_irq(dev); | |
58dfd9c1 | 3961 | netif_tx_lock_bh(dev); |
eafa59f6 AA |
3962 | spin_lock(&np->lock); |
3963 | /* stop engines */ | |
3964 | nv_stop_rx(dev); | |
3965 | nv_stop_tx(dev); | |
3966 | nv_txrx_reset(dev); | |
3967 | /* drain queues */ | |
3968 | nv_drain_rx(dev); | |
3969 | nv_drain_tx(dev); | |
3970 | /* delete queues */ | |
3971 | free_rings(dev); | |
3972 | } | |
3973 | ||
3974 | /* set new values */ | |
3975 | np->rx_ring_size = ring->rx_pending; | |
3976 | np->tx_ring_size = ring->tx_pending; | |
eafa59f6 AA |
3977 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
3978 | np->rx_ring.orig = (struct ring_desc*)rxtx_ring; | |
3979 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; | |
3980 | } else { | |
3981 | np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring; | |
3982 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; | |
3983 | } | |
761fcd9e AA |
3984 | np->rx_skb = (struct nv_skb_map*)rx_skbuff; |
3985 | np->tx_skb = (struct nv_skb_map*)tx_skbuff; | |
eafa59f6 AA |
3986 | np->ring_addr = ring_addr; |
3987 | ||
761fcd9e AA |
3988 | memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); |
3989 | memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); | |
eafa59f6 AA |
3990 | |
3991 | if (netif_running(dev)) { | |
3992 | /* reinit driver view of the queues */ | |
3993 | set_bufsize(dev); | |
3994 | if (nv_init_ring(dev)) { | |
3995 | if (!np->in_shutdown) | |
3996 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3997 | } | |
3998 | ||
3999 | /* reinit nic view of the queues */ | |
4000 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4001 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
4002 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | |
4003 | base + NvRegRingSizes); | |
4004 | pci_push(base); | |
4005 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4006 | pci_push(base); | |
4007 | ||
4008 | /* restart engines */ | |
4009 | nv_start_rx(dev); | |
4010 | nv_start_tx(dev); | |
4011 | spin_unlock(&np->lock); | |
58dfd9c1 | 4012 | netif_tx_unlock_bh(dev); |
eafa59f6 AA |
4013 | nv_enable_irq(dev); |
4014 | } | |
4015 | return 0; | |
4016 | exit: | |
4017 | return -ENOMEM; | |
4018 | } | |
4019 | ||
b6d0773f AA |
4020 | static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
4021 | { | |
4022 | struct fe_priv *np = netdev_priv(dev); | |
4023 | ||
4024 | pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; | |
4025 | pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; | |
4026 | pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0; | |
4027 | } | |
4028 | ||
4029 | static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) | |
4030 | { | |
4031 | struct fe_priv *np = netdev_priv(dev); | |
4032 | int adv, bmcr; | |
4033 | ||
4034 | if ((!np->autoneg && np->duplex == 0) || | |
4035 | (np->autoneg && !pause->autoneg && np->duplex == 0)) { | |
4036 | printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n", | |
4037 | dev->name); | |
4038 | return -EINVAL; | |
4039 | } | |
4040 | if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { | |
4041 | printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name); | |
4042 | return -EINVAL; | |
4043 | } | |
4044 | ||
4045 | netif_carrier_off(dev); | |
4046 | if (netif_running(dev)) { | |
4047 | nv_disable_irq(dev); | |
58dfd9c1 | 4048 | netif_tx_lock_bh(dev); |
b6d0773f AA |
4049 | spin_lock(&np->lock); |
4050 | /* stop engines */ | |
4051 | nv_stop_rx(dev); | |
4052 | nv_stop_tx(dev); | |
4053 | spin_unlock(&np->lock); | |
58dfd9c1 | 4054 | netif_tx_unlock_bh(dev); |
b6d0773f AA |
4055 | } |
4056 | ||
4057 | np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ); | |
4058 | if (pause->rx_pause) | |
4059 | np->pause_flags |= NV_PAUSEFRAME_RX_REQ; | |
4060 | if (pause->tx_pause) | |
4061 | np->pause_flags |= NV_PAUSEFRAME_TX_REQ; | |
4062 | ||
4063 | if (np->autoneg && pause->autoneg) { | |
4064 | np->pause_flags |= NV_PAUSEFRAME_AUTONEG; | |
4065 | ||
4066 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
4067 | adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
4068 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ | |
4069 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
4070 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4071 | adv |= ADVERTISE_PAUSE_ASYM; | |
4072 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); | |
4073 | ||
4074 | if (netif_running(dev)) | |
4075 | printk(KERN_INFO "%s: link down.\n", dev->name); | |
4076 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
4077 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4078 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4079 | } else { | |
4080 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
4081 | if (pause->rx_pause) | |
4082 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4083 | if (pause->tx_pause) | |
4084 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4085 | ||
4086 | if (!netif_running(dev)) | |
4087 | nv_update_linkspeed(dev); | |
4088 | else | |
4089 | nv_update_pause(dev, np->pause_flags); | |
4090 | } | |
4091 | ||
4092 | if (netif_running(dev)) { | |
4093 | nv_start_rx(dev); | |
4094 | nv_start_tx(dev); | |
4095 | nv_enable_irq(dev); | |
4096 | } | |
4097 | return 0; | |
4098 | } | |
4099 | ||
5ed2616f AA |
4100 | static u32 nv_get_rx_csum(struct net_device *dev) |
4101 | { | |
4102 | struct fe_priv *np = netdev_priv(dev); | |
f2ad2d9b | 4103 | return (np->rx_csum) != 0; |
5ed2616f AA |
4104 | } |
4105 | ||
4106 | static int nv_set_rx_csum(struct net_device *dev, u32 data) | |
4107 | { | |
4108 | struct fe_priv *np = netdev_priv(dev); | |
4109 | u8 __iomem *base = get_hwbase(dev); | |
4110 | int retcode = 0; | |
4111 | ||
4112 | if (np->driver_data & DEV_HAS_CHECKSUM) { | |
5ed2616f | 4113 | if (data) { |
f2ad2d9b | 4114 | np->rx_csum = 1; |
5ed2616f | 4115 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
5ed2616f | 4116 | } else { |
f2ad2d9b AA |
4117 | np->rx_csum = 0; |
4118 | /* vlan is dependent on rx checksum offload */ | |
4119 | if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) | |
4120 | np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; | |
5ed2616f | 4121 | } |
5ed2616f AA |
4122 | if (netif_running(dev)) { |
4123 | spin_lock_irq(&np->lock); | |
4124 | writel(np->txrxctl_bits, base + NvRegTxRxControl); | |
4125 | spin_unlock_irq(&np->lock); | |
4126 | } | |
4127 | } else { | |
4128 | return -EINVAL; | |
4129 | } | |
4130 | ||
4131 | return retcode; | |
4132 | } | |
4133 | ||
4134 | static int nv_set_tx_csum(struct net_device *dev, u32 data) | |
4135 | { | |
4136 | struct fe_priv *np = netdev_priv(dev); | |
4137 | ||
4138 | if (np->driver_data & DEV_HAS_CHECKSUM) | |
4139 | return ethtool_op_set_tx_hw_csum(dev, data); | |
4140 | else | |
4141 | return -EOPNOTSUPP; | |
4142 | } | |
4143 | ||
4144 | static int nv_set_sg(struct net_device *dev, u32 data) | |
4145 | { | |
4146 | struct fe_priv *np = netdev_priv(dev); | |
4147 | ||
4148 | if (np->driver_data & DEV_HAS_CHECKSUM) | |
4149 | return ethtool_op_set_sg(dev, data); | |
4150 | else | |
4151 | return -EOPNOTSUPP; | |
4152 | } | |
4153 | ||
52da3578 AA |
4154 | static int nv_get_stats_count(struct net_device *dev) |
4155 | { | |
4156 | struct fe_priv *np = netdev_priv(dev); | |
4157 | ||
4158 | if (np->driver_data & DEV_HAS_STATISTICS) | |
f82a9352 | 4159 | return sizeof(struct nv_ethtool_stats)/sizeof(u64); |
52da3578 AA |
4160 | else |
4161 | return 0; | |
4162 | } | |
4163 | ||
4164 | static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer) | |
4165 | { | |
4166 | struct fe_priv *np = netdev_priv(dev); | |
4167 | ||
4168 | /* update stats */ | |
4169 | nv_do_stats_poll((unsigned long)dev); | |
4170 | ||
4171 | memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64)); | |
4172 | } | |
4173 | ||
9589c77a AA |
4174 | static int nv_self_test_count(struct net_device *dev) |
4175 | { | |
4176 | struct fe_priv *np = netdev_priv(dev); | |
4177 | ||
4178 | if (np->driver_data & DEV_HAS_TEST_EXTENDED) | |
4179 | return NV_TEST_COUNT_EXTENDED; | |
4180 | else | |
4181 | return NV_TEST_COUNT_BASE; | |
4182 | } | |
4183 | ||
4184 | static int nv_link_test(struct net_device *dev) | |
4185 | { | |
4186 | struct fe_priv *np = netdev_priv(dev); | |
4187 | int mii_status; | |
4188 | ||
4189 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4190 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4191 | ||
4192 | /* check phy link status */ | |
4193 | if (!(mii_status & BMSR_LSTATUS)) | |
4194 | return 0; | |
4195 | else | |
4196 | return 1; | |
4197 | } | |
4198 | ||
4199 | static int nv_register_test(struct net_device *dev) | |
4200 | { | |
4201 | u8 __iomem *base = get_hwbase(dev); | |
4202 | int i = 0; | |
4203 | u32 orig_read, new_read; | |
4204 | ||
4205 | do { | |
4206 | orig_read = readl(base + nv_registers_test[i].reg); | |
4207 | ||
4208 | /* xor with mask to toggle bits */ | |
4209 | orig_read ^= nv_registers_test[i].mask; | |
4210 | ||
4211 | writel(orig_read, base + nv_registers_test[i].reg); | |
4212 | ||
4213 | new_read = readl(base + nv_registers_test[i].reg); | |
4214 | ||
4215 | if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask)) | |
4216 | return 0; | |
4217 | ||
4218 | /* restore original value */ | |
4219 | orig_read ^= nv_registers_test[i].mask; | |
4220 | writel(orig_read, base + nv_registers_test[i].reg); | |
4221 | ||
4222 | } while (nv_registers_test[++i].reg != 0); | |
4223 | ||
4224 | return 1; | |
4225 | } | |
4226 | ||
4227 | static int nv_interrupt_test(struct net_device *dev) | |
4228 | { | |
4229 | struct fe_priv *np = netdev_priv(dev); | |
4230 | u8 __iomem *base = get_hwbase(dev); | |
4231 | int ret = 1; | |
4232 | int testcnt; | |
4233 | u32 save_msi_flags, save_poll_interval = 0; | |
4234 | ||
4235 | if (netif_running(dev)) { | |
4236 | /* free current irq */ | |
4237 | nv_free_irq(dev); | |
4238 | save_poll_interval = readl(base+NvRegPollingInterval); | |
4239 | } | |
4240 | ||
4241 | /* flag to test interrupt handler */ | |
4242 | np->intr_test = 0; | |
4243 | ||
4244 | /* setup test irq */ | |
4245 | save_msi_flags = np->msi_flags; | |
4246 | np->msi_flags &= ~NV_MSI_X_VECTORS_MASK; | |
4247 | np->msi_flags |= 0x001; /* setup 1 vector */ | |
4248 | if (nv_request_irq(dev, 1)) | |
4249 | return 0; | |
4250 | ||
4251 | /* setup timer interrupt */ | |
4252 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
4253 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
4254 | ||
4255 | nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
4256 | ||
4257 | /* wait for at least one interrupt */ | |
4258 | msleep(100); | |
4259 | ||
4260 | spin_lock_irq(&np->lock); | |
4261 | ||
4262 | /* flag should be set within ISR */ | |
4263 | testcnt = np->intr_test; | |
4264 | if (!testcnt) | |
4265 | ret = 2; | |
4266 | ||
4267 | nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
4268 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
4269 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
4270 | else | |
4271 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
4272 | ||
4273 | spin_unlock_irq(&np->lock); | |
4274 | ||
4275 | nv_free_irq(dev); | |
4276 | ||
4277 | np->msi_flags = save_msi_flags; | |
4278 | ||
4279 | if (netif_running(dev)) { | |
4280 | writel(save_poll_interval, base + NvRegPollingInterval); | |
4281 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
4282 | /* restore original irq */ | |
4283 | if (nv_request_irq(dev, 0)) | |
4284 | return 0; | |
4285 | } | |
4286 | ||
4287 | return ret; | |
4288 | } | |
4289 | ||
4290 | static int nv_loopback_test(struct net_device *dev) | |
4291 | { | |
4292 | struct fe_priv *np = netdev_priv(dev); | |
4293 | u8 __iomem *base = get_hwbase(dev); | |
4294 | struct sk_buff *tx_skb, *rx_skb; | |
4295 | dma_addr_t test_dma_addr; | |
4296 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); | |
f82a9352 | 4297 | u32 flags; |
9589c77a AA |
4298 | int len, i, pkt_len; |
4299 | u8 *pkt_data; | |
4300 | u32 filter_flags = 0; | |
4301 | u32 misc1_flags = 0; | |
4302 | int ret = 1; | |
4303 | ||
4304 | if (netif_running(dev)) { | |
4305 | nv_disable_irq(dev); | |
4306 | filter_flags = readl(base + NvRegPacketFilterFlags); | |
4307 | misc1_flags = readl(base + NvRegMisc1); | |
4308 | } else { | |
4309 | nv_txrx_reset(dev); | |
4310 | } | |
4311 | ||
4312 | /* reinit driver view of the rx queue */ | |
4313 | set_bufsize(dev); | |
4314 | nv_init_ring(dev); | |
4315 | ||
4316 | /* setup hardware for loopback */ | |
4317 | writel(NVREG_MISC1_FORCE, base + NvRegMisc1); | |
4318 | writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags); | |
4319 | ||
4320 | /* reinit nic view of the rx queue */ | |
4321 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4322 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
4323 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | |
4324 | base + NvRegRingSizes); | |
4325 | pci_push(base); | |
4326 | ||
4327 | /* restart rx engine */ | |
4328 | nv_start_rx(dev); | |
4329 | nv_start_tx(dev); | |
4330 | ||
4331 | /* setup packet for tx */ | |
4332 | pkt_len = ETH_DATA_LEN; | |
4333 | tx_skb = dev_alloc_skb(pkt_len); | |
46798c89 JJ |
4334 | if (!tx_skb) { |
4335 | printk(KERN_ERR "dev_alloc_skb() failed during loopback test" | |
4336 | " of %s\n", dev->name); | |
4337 | ret = 0; | |
4338 | goto out; | |
4339 | } | |
9589c77a AA |
4340 | pkt_data = skb_put(tx_skb, pkt_len); |
4341 | for (i = 0; i < pkt_len; i++) | |
4342 | pkt_data[i] = (u8)(i & 0xff); | |
4343 | test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data, | |
4344 | tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE); | |
4345 | ||
4346 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { | |
f82a9352 SH |
4347 | np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr); |
4348 | np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); | |
9589c77a | 4349 | } else { |
f82a9352 SH |
4350 | np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32; |
4351 | np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF; | |
4352 | np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); | |
9589c77a AA |
4353 | } |
4354 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4355 | pci_push(get_hwbase(dev)); | |
4356 | ||
4357 | msleep(500); | |
4358 | ||
4359 | /* check for rx of the packet */ | |
4360 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { | |
f82a9352 | 4361 | flags = le32_to_cpu(np->rx_ring.orig[0].flaglen); |
9589c77a AA |
4362 | len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); |
4363 | ||
4364 | } else { | |
f82a9352 | 4365 | flags = le32_to_cpu(np->rx_ring.ex[0].flaglen); |
9589c77a AA |
4366 | len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); |
4367 | } | |
4368 | ||
f82a9352 | 4369 | if (flags & NV_RX_AVAIL) { |
9589c77a AA |
4370 | ret = 0; |
4371 | } else if (np->desc_ver == DESC_VER_1) { | |
f82a9352 | 4372 | if (flags & NV_RX_ERROR) |
9589c77a AA |
4373 | ret = 0; |
4374 | } else { | |
f82a9352 | 4375 | if (flags & NV_RX2_ERROR) { |
9589c77a AA |
4376 | ret = 0; |
4377 | } | |
4378 | } | |
4379 | ||
4380 | if (ret) { | |
4381 | if (len != pkt_len) { | |
4382 | ret = 0; | |
4383 | dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n", | |
4384 | dev->name, len, pkt_len); | |
4385 | } else { | |
761fcd9e | 4386 | rx_skb = np->rx_skb[0].skb; |
9589c77a AA |
4387 | for (i = 0; i < pkt_len; i++) { |
4388 | if (rx_skb->data[i] != (u8)(i & 0xff)) { | |
4389 | ret = 0; | |
4390 | dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n", | |
4391 | dev->name, i); | |
4392 | break; | |
4393 | } | |
4394 | } | |
4395 | } | |
4396 | } else { | |
4397 | dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name); | |
4398 | } | |
4399 | ||
4400 | pci_unmap_page(np->pci_dev, test_dma_addr, | |
4401 | tx_skb->end-tx_skb->data, | |
4402 | PCI_DMA_TODEVICE); | |
4403 | dev_kfree_skb_any(tx_skb); | |
46798c89 | 4404 | out: |
9589c77a AA |
4405 | /* stop engines */ |
4406 | nv_stop_rx(dev); | |
4407 | nv_stop_tx(dev); | |
4408 | nv_txrx_reset(dev); | |
4409 | /* drain rx queue */ | |
4410 | nv_drain_rx(dev); | |
4411 | nv_drain_tx(dev); | |
4412 | ||
4413 | if (netif_running(dev)) { | |
4414 | writel(misc1_flags, base + NvRegMisc1); | |
4415 | writel(filter_flags, base + NvRegPacketFilterFlags); | |
4416 | nv_enable_irq(dev); | |
4417 | } | |
4418 | ||
4419 | return ret; | |
4420 | } | |
4421 | ||
4422 | static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer) | |
4423 | { | |
4424 | struct fe_priv *np = netdev_priv(dev); | |
4425 | u8 __iomem *base = get_hwbase(dev); | |
4426 | int result; | |
4427 | memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64)); | |
4428 | ||
4429 | if (!nv_link_test(dev)) { | |
4430 | test->flags |= ETH_TEST_FL_FAILED; | |
4431 | buffer[0] = 1; | |
4432 | } | |
4433 | ||
4434 | if (test->flags & ETH_TEST_FL_OFFLINE) { | |
4435 | if (netif_running(dev)) { | |
4436 | netif_stop_queue(dev); | |
e27cdba5 | 4437 | netif_poll_disable(dev); |
58dfd9c1 | 4438 | netif_tx_lock_bh(dev); |
9589c77a AA |
4439 | spin_lock_irq(&np->lock); |
4440 | nv_disable_hw_interrupts(dev, np->irqmask); | |
4441 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | |
4442 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
4443 | } else { | |
4444 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
4445 | } | |
4446 | /* stop engines */ | |
4447 | nv_stop_rx(dev); | |
4448 | nv_stop_tx(dev); | |
4449 | nv_txrx_reset(dev); | |
4450 | /* drain rx queue */ | |
4451 | nv_drain_rx(dev); | |
4452 | nv_drain_tx(dev); | |
4453 | spin_unlock_irq(&np->lock); | |
58dfd9c1 | 4454 | netif_tx_unlock_bh(dev); |
9589c77a AA |
4455 | } |
4456 | ||
4457 | if (!nv_register_test(dev)) { | |
4458 | test->flags |= ETH_TEST_FL_FAILED; | |
4459 | buffer[1] = 1; | |
4460 | } | |
4461 | ||
4462 | result = nv_interrupt_test(dev); | |
4463 | if (result != 1) { | |
4464 | test->flags |= ETH_TEST_FL_FAILED; | |
4465 | buffer[2] = 1; | |
4466 | } | |
4467 | if (result == 0) { | |
4468 | /* bail out */ | |
4469 | return; | |
4470 | } | |
4471 | ||
4472 | if (!nv_loopback_test(dev)) { | |
4473 | test->flags |= ETH_TEST_FL_FAILED; | |
4474 | buffer[3] = 1; | |
4475 | } | |
4476 | ||
4477 | if (netif_running(dev)) { | |
4478 | /* reinit driver view of the rx queue */ | |
4479 | set_bufsize(dev); | |
4480 | if (nv_init_ring(dev)) { | |
4481 | if (!np->in_shutdown) | |
4482 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4483 | } | |
4484 | /* reinit nic view of the rx queue */ | |
4485 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4486 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
4487 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | |
4488 | base + NvRegRingSizes); | |
4489 | pci_push(base); | |
4490 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4491 | pci_push(base); | |
4492 | /* restart rx engine */ | |
4493 | nv_start_rx(dev); | |
4494 | nv_start_tx(dev); | |
4495 | netif_start_queue(dev); | |
e27cdba5 | 4496 | netif_poll_enable(dev); |
9589c77a AA |
4497 | nv_enable_hw_interrupts(dev, np->irqmask); |
4498 | } | |
4499 | } | |
4500 | } | |
4501 | ||
52da3578 AA |
4502 | static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer) |
4503 | { | |
4504 | switch (stringset) { | |
4505 | case ETH_SS_STATS: | |
4506 | memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str)); | |
4507 | break; | |
9589c77a AA |
4508 | case ETH_SS_TEST: |
4509 | memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str)); | |
4510 | break; | |
52da3578 AA |
4511 | } |
4512 | } | |
4513 | ||
7282d491 | 4514 | static const struct ethtool_ops ops = { |
1da177e4 LT |
4515 | .get_drvinfo = nv_get_drvinfo, |
4516 | .get_link = ethtool_op_get_link, | |
4517 | .get_wol = nv_get_wol, | |
4518 | .set_wol = nv_set_wol, | |
4519 | .get_settings = nv_get_settings, | |
4520 | .set_settings = nv_set_settings, | |
dc8216c1 MS |
4521 | .get_regs_len = nv_get_regs_len, |
4522 | .get_regs = nv_get_regs, | |
4523 | .nway_reset = nv_nway_reset, | |
c704b856 | 4524 | .get_perm_addr = ethtool_op_get_perm_addr, |
0674d594 | 4525 | .get_tso = ethtool_op_get_tso, |
6a78814f | 4526 | .set_tso = nv_set_tso, |
eafa59f6 AA |
4527 | .get_ringparam = nv_get_ringparam, |
4528 | .set_ringparam = nv_set_ringparam, | |
b6d0773f AA |
4529 | .get_pauseparam = nv_get_pauseparam, |
4530 | .set_pauseparam = nv_set_pauseparam, | |
5ed2616f AA |
4531 | .get_rx_csum = nv_get_rx_csum, |
4532 | .set_rx_csum = nv_set_rx_csum, | |
4533 | .get_tx_csum = ethtool_op_get_tx_csum, | |
4534 | .set_tx_csum = nv_set_tx_csum, | |
4535 | .get_sg = ethtool_op_get_sg, | |
4536 | .set_sg = nv_set_sg, | |
52da3578 AA |
4537 | .get_strings = nv_get_strings, |
4538 | .get_stats_count = nv_get_stats_count, | |
4539 | .get_ethtool_stats = nv_get_ethtool_stats, | |
9589c77a AA |
4540 | .self_test_count = nv_self_test_count, |
4541 | .self_test = nv_self_test, | |
1da177e4 LT |
4542 | }; |
4543 | ||
ee407b02 AA |
4544 | static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) |
4545 | { | |
4546 | struct fe_priv *np = get_nvpriv(dev); | |
4547 | ||
4548 | spin_lock_irq(&np->lock); | |
4549 | ||
4550 | /* save vlan group */ | |
4551 | np->vlangrp = grp; | |
4552 | ||
4553 | if (grp) { | |
4554 | /* enable vlan on MAC */ | |
4555 | np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS; | |
4556 | } else { | |
4557 | /* disable vlan on MAC */ | |
4558 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; | |
4559 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; | |
4560 | } | |
4561 | ||
4562 | writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4563 | ||
4564 | spin_unlock_irq(&np->lock); | |
4565 | }; | |
4566 | ||
4567 | static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |
4568 | { | |
4569 | /* nothing to do */ | |
4570 | }; | |
4571 | ||
7e680c22 AA |
4572 | /* The mgmt unit and driver use a semaphore to access the phy during init */ |
4573 | static int nv_mgmt_acquire_sema(struct net_device *dev) | |
4574 | { | |
4575 | u8 __iomem *base = get_hwbase(dev); | |
4576 | int i; | |
4577 | u32 tx_ctrl, mgmt_sema; | |
4578 | ||
4579 | for (i = 0; i < 10; i++) { | |
4580 | mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK; | |
4581 | if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE) | |
4582 | break; | |
4583 | msleep(500); | |
4584 | } | |
4585 | ||
4586 | if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE) | |
4587 | return 0; | |
4588 | ||
4589 | for (i = 0; i < 2; i++) { | |
4590 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
4591 | tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ; | |
4592 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
4593 | ||
4594 | /* verify that semaphore was acquired */ | |
4595 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
4596 | if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) && | |
4597 | ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) | |
4598 | return 1; | |
4599 | else | |
4600 | udelay(50); | |
4601 | } | |
4602 | ||
4603 | return 0; | |
4604 | } | |
4605 | ||
1da177e4 LT |
4606 | static int nv_open(struct net_device *dev) |
4607 | { | |
ac9c1897 | 4608 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 4609 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 AA |
4610 | int ret = 1; |
4611 | int oom, i; | |
1da177e4 LT |
4612 | |
4613 | dprintk(KERN_DEBUG "nv_open: begin\n"); | |
4614 | ||
f1489653 | 4615 | /* erase previous misconfiguration */ |
86a0f043 AA |
4616 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
4617 | nv_mac_reset(dev); | |
1da177e4 LT |
4618 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
4619 | writel(0, base + NvRegMulticastAddrB); | |
4620 | writel(0, base + NvRegMulticastMaskA); | |
4621 | writel(0, base + NvRegMulticastMaskB); | |
4622 | writel(0, base + NvRegPacketFilterFlags); | |
4623 | ||
4624 | writel(0, base + NvRegTransmitterControl); | |
4625 | writel(0, base + NvRegReceiverControl); | |
4626 | ||
4627 | writel(0, base + NvRegAdapterControl); | |
4628 | ||
eb91f61b AA |
4629 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) |
4630 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
4631 | ||
f1489653 | 4632 | /* initialize descriptor rings */ |
d81c0983 | 4633 | set_bufsize(dev); |
1da177e4 LT |
4634 | oom = nv_init_ring(dev); |
4635 | ||
4636 | writel(0, base + NvRegLinkSpeed); | |
5070d340 | 4637 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
1da177e4 LT |
4638 | nv_txrx_reset(dev); |
4639 | writel(0, base + NvRegUnknownSetupReg6); | |
4640 | ||
4641 | np->in_shutdown = 0; | |
4642 | ||
f1489653 | 4643 | /* give hw rings */ |
0832b25a | 4644 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
eafa59f6 | 4645 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
1da177e4 LT |
4646 | base + NvRegRingSizes); |
4647 | ||
1da177e4 | 4648 | writel(np->linkspeed, base + NvRegLinkSpeed); |
95d161cb AA |
4649 | if (np->desc_ver == DESC_VER_1) |
4650 | writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); | |
4651 | else | |
4652 | writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark); | |
8a4ae7f2 | 4653 | writel(np->txrxctl_bits, base + NvRegTxRxControl); |
ee407b02 | 4654 | writel(np->vlanctl_bits, base + NvRegVlanControl); |
1da177e4 | 4655 | pci_push(base); |
8a4ae7f2 | 4656 | writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
4657 | reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, |
4658 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, | |
4659 | KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); | |
4660 | ||
7e680c22 | 4661 | writel(0, base + NvRegMIIMask); |
1da177e4 LT |
4662 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
4663 | writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); | |
4664 | ||
1da177e4 LT |
4665 | writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
4666 | writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); | |
4667 | writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); | |
d81c0983 | 4668 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
1da177e4 LT |
4669 | |
4670 | writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); | |
4671 | get_random_bytes(&i, sizeof(i)); | |
4672 | writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed); | |
9744e218 AA |
4673 | writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); |
4674 | writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); | |
a971c324 AA |
4675 | if (poll_interval == -1) { |
4676 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) | |
4677 | writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); | |
4678 | else | |
4679 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
4680 | } | |
4681 | else | |
4682 | writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); | |
1da177e4 LT |
4683 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
4684 | writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, | |
4685 | base + NvRegAdapterControl); | |
4686 | writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); | |
7e680c22 | 4687 | writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask); |
c42d9df9 AA |
4688 | if (np->wolenabled) |
4689 | writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); | |
1da177e4 LT |
4690 | |
4691 | i = readl(base + NvRegPowerState); | |
4692 | if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0) | |
4693 | writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); | |
4694 | ||
4695 | pci_push(base); | |
4696 | udelay(10); | |
4697 | writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); | |
4698 | ||
84b3932b | 4699 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 LT |
4700 | pci_push(base); |
4701 | writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); | |
4702 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
4703 | pci_push(base); | |
4704 | ||
9589c77a | 4705 | if (nv_request_irq(dev, 0)) { |
84b3932b | 4706 | goto out_drain; |
d33a73c8 | 4707 | } |
1da177e4 LT |
4708 | |
4709 | /* ask for interrupts */ | |
84b3932b | 4710 | nv_enable_hw_interrupts(dev, np->irqmask); |
1da177e4 LT |
4711 | |
4712 | spin_lock_irq(&np->lock); | |
4713 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); | |
4714 | writel(0, base + NvRegMulticastAddrB); | |
4715 | writel(0, base + NvRegMulticastMaskA); | |
4716 | writel(0, base + NvRegMulticastMaskB); | |
4717 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); | |
4718 | /* One manual link speed update: Interrupts are enabled, future link | |
4719 | * speed changes cause interrupts and are handled by nv_link_irq(). | |
4720 | */ | |
4721 | { | |
4722 | u32 miistat; | |
4723 | miistat = readl(base + NvRegMIIStatus); | |
4724 | writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); | |
4725 | dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat); | |
4726 | } | |
1b1b3c9b MS |
4727 | /* set linkspeed to invalid value, thus force nv_update_linkspeed |
4728 | * to init hw */ | |
4729 | np->linkspeed = 0; | |
1da177e4 LT |
4730 | ret = nv_update_linkspeed(dev); |
4731 | nv_start_rx(dev); | |
4732 | nv_start_tx(dev); | |
4733 | netif_start_queue(dev); | |
e27cdba5 SH |
4734 | netif_poll_enable(dev); |
4735 | ||
1da177e4 LT |
4736 | if (ret) { |
4737 | netif_carrier_on(dev); | |
4738 | } else { | |
4739 | printk("%s: no link during initialization.\n", dev->name); | |
4740 | netif_carrier_off(dev); | |
4741 | } | |
4742 | if (oom) | |
4743 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
52da3578 AA |
4744 | |
4745 | /* start statistics timer */ | |
4746 | if (np->driver_data & DEV_HAS_STATISTICS) | |
4747 | mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL); | |
4748 | ||
1da177e4 LT |
4749 | spin_unlock_irq(&np->lock); |
4750 | ||
4751 | return 0; | |
4752 | out_drain: | |
4753 | drain_ring(dev); | |
4754 | return ret; | |
4755 | } | |
4756 | ||
4757 | static int nv_close(struct net_device *dev) | |
4758 | { | |
ac9c1897 | 4759 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
4760 | u8 __iomem *base; |
4761 | ||
4762 | spin_lock_irq(&np->lock); | |
4763 | np->in_shutdown = 1; | |
4764 | spin_unlock_irq(&np->lock); | |
e27cdba5 | 4765 | netif_poll_disable(dev); |
1da177e4 LT |
4766 | synchronize_irq(dev->irq); |
4767 | ||
4768 | del_timer_sync(&np->oom_kick); | |
4769 | del_timer_sync(&np->nic_poll); | |
52da3578 | 4770 | del_timer_sync(&np->stats_poll); |
1da177e4 LT |
4771 | |
4772 | netif_stop_queue(dev); | |
4773 | spin_lock_irq(&np->lock); | |
4774 | nv_stop_tx(dev); | |
4775 | nv_stop_rx(dev); | |
4776 | nv_txrx_reset(dev); | |
4777 | ||
4778 | /* disable interrupts on the nic or we will lock up */ | |
4779 | base = get_hwbase(dev); | |
84b3932b | 4780 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 LT |
4781 | pci_push(base); |
4782 | dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name); | |
4783 | ||
4784 | spin_unlock_irq(&np->lock); | |
4785 | ||
84b3932b | 4786 | nv_free_irq(dev); |
1da177e4 LT |
4787 | |
4788 | drain_ring(dev); | |
4789 | ||
4790 | if (np->wolenabled) | |
4791 | nv_start_rx(dev); | |
4792 | ||
4793 | /* FIXME: power down nic */ | |
4794 | ||
4795 | return 0; | |
4796 | } | |
4797 | ||
4798 | static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) | |
4799 | { | |
4800 | struct net_device *dev; | |
4801 | struct fe_priv *np; | |
4802 | unsigned long addr; | |
4803 | u8 __iomem *base; | |
4804 | int err, i; | |
5070d340 | 4805 | u32 powerstate, txreg; |
7e680c22 AA |
4806 | u32 phystate_orig = 0, phystate; |
4807 | int phyinitialized = 0; | |
1da177e4 LT |
4808 | |
4809 | dev = alloc_etherdev(sizeof(struct fe_priv)); | |
4810 | err = -ENOMEM; | |
4811 | if (!dev) | |
4812 | goto out; | |
4813 | ||
ac9c1897 | 4814 | np = netdev_priv(dev); |
1da177e4 LT |
4815 | np->pci_dev = pci_dev; |
4816 | spin_lock_init(&np->lock); | |
4817 | SET_MODULE_OWNER(dev); | |
4818 | SET_NETDEV_DEV(dev, &pci_dev->dev); | |
4819 | ||
4820 | init_timer(&np->oom_kick); | |
4821 | np->oom_kick.data = (unsigned long) dev; | |
4822 | np->oom_kick.function = &nv_do_rx_refill; /* timer handler */ | |
4823 | init_timer(&np->nic_poll); | |
4824 | np->nic_poll.data = (unsigned long) dev; | |
4825 | np->nic_poll.function = &nv_do_nic_poll; /* timer handler */ | |
52da3578 AA |
4826 | init_timer(&np->stats_poll); |
4827 | np->stats_poll.data = (unsigned long) dev; | |
4828 | np->stats_poll.function = &nv_do_stats_poll; /* timer handler */ | |
1da177e4 LT |
4829 | |
4830 | err = pci_enable_device(pci_dev); | |
4831 | if (err) { | |
4832 | printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n", | |
4833 | err, pci_name(pci_dev)); | |
4834 | goto out_free; | |
4835 | } | |
4836 | ||
4837 | pci_set_master(pci_dev); | |
4838 | ||
4839 | err = pci_request_regions(pci_dev, DRV_NAME); | |
4840 | if (err < 0) | |
4841 | goto out_disable; | |
4842 | ||
52da3578 | 4843 | if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS)) |
86a0f043 AA |
4844 | np->register_size = NV_PCI_REGSZ_VER2; |
4845 | else | |
4846 | np->register_size = NV_PCI_REGSZ_VER1; | |
4847 | ||
1da177e4 LT |
4848 | err = -EINVAL; |
4849 | addr = 0; | |
4850 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
4851 | dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n", | |
4852 | pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i), | |
4853 | pci_resource_len(pci_dev, i), | |
4854 | pci_resource_flags(pci_dev, i)); | |
4855 | if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && | |
86a0f043 | 4856 | pci_resource_len(pci_dev, i) >= np->register_size) { |
1da177e4 LT |
4857 | addr = pci_resource_start(pci_dev, i); |
4858 | break; | |
4859 | } | |
4860 | } | |
4861 | if (i == DEVICE_COUNT_RESOURCE) { | |
4862 | printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n", | |
4863 | pci_name(pci_dev)); | |
4864 | goto out_relreg; | |
4865 | } | |
4866 | ||
86a0f043 AA |
4867 | /* copy of driver data */ |
4868 | np->driver_data = id->driver_data; | |
4869 | ||
1da177e4 | 4870 | /* handle different descriptor versions */ |
ee73362c MS |
4871 | if (id->driver_data & DEV_HAS_HIGH_DMA) { |
4872 | /* packet format 3: supports 40-bit addressing */ | |
4873 | np->desc_ver = DESC_VER_3; | |
84b3932b | 4874 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; |
69fe3fd7 AA |
4875 | if (dma_64bit) { |
4876 | if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) { | |
4877 | printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n", | |
4878 | pci_name(pci_dev)); | |
4879 | } else { | |
4880 | dev->features |= NETIF_F_HIGHDMA; | |
4881 | printk(KERN_INFO "forcedeth: using HIGHDMA\n"); | |
4882 | } | |
4883 | if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) { | |
4884 | printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n", | |
4885 | pci_name(pci_dev)); | |
4886 | } | |
ee73362c MS |
4887 | } |
4888 | } else if (id->driver_data & DEV_HAS_LARGEDESC) { | |
4889 | /* packet format 2: supports jumbo frames */ | |
1da177e4 | 4890 | np->desc_ver = DESC_VER_2; |
8a4ae7f2 | 4891 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; |
ee73362c MS |
4892 | } else { |
4893 | /* original packet format */ | |
4894 | np->desc_ver = DESC_VER_1; | |
8a4ae7f2 | 4895 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; |
d81c0983 | 4896 | } |
ee73362c MS |
4897 | |
4898 | np->pkt_limit = NV_PKTLIMIT_1; | |
4899 | if (id->driver_data & DEV_HAS_LARGEDESC) | |
4900 | np->pkt_limit = NV_PKTLIMIT_2; | |
4901 | ||
8a4ae7f2 | 4902 | if (id->driver_data & DEV_HAS_CHECKSUM) { |
f2ad2d9b | 4903 | np->rx_csum = 1; |
8a4ae7f2 | 4904 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
ac9c1897 | 4905 | dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; |
fa45459e | 4906 | dev->features |= NETIF_F_TSO; |
ac9c1897 | 4907 | } |
8a4ae7f2 | 4908 | |
ee407b02 AA |
4909 | np->vlanctl_bits = 0; |
4910 | if (id->driver_data & DEV_HAS_VLAN) { | |
4911 | np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; | |
4912 | dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; | |
4913 | dev->vlan_rx_register = nv_vlan_rx_register; | |
4914 | dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid; | |
4915 | } | |
4916 | ||
d33a73c8 | 4917 | np->msi_flags = 0; |
69fe3fd7 | 4918 | if ((id->driver_data & DEV_HAS_MSI) && msi) { |
d33a73c8 AA |
4919 | np->msi_flags |= NV_MSI_CAPABLE; |
4920 | } | |
69fe3fd7 | 4921 | if ((id->driver_data & DEV_HAS_MSI_X) && msix) { |
d33a73c8 AA |
4922 | np->msi_flags |= NV_MSI_X_CAPABLE; |
4923 | } | |
4924 | ||
b6d0773f | 4925 | np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG; |
eb91f61b | 4926 | if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) { |
b6d0773f | 4927 | np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ; |
eb91f61b | 4928 | } |
f3b197ac | 4929 | |
eb91f61b | 4930 | |
1da177e4 | 4931 | err = -ENOMEM; |
86a0f043 | 4932 | np->base = ioremap(addr, np->register_size); |
1da177e4 LT |
4933 | if (!np->base) |
4934 | goto out_relreg; | |
4935 | dev->base_addr = (unsigned long)np->base; | |
ee73362c | 4936 | |
1da177e4 | 4937 | dev->irq = pci_dev->irq; |
ee73362c | 4938 | |
eafa59f6 AA |
4939 | np->rx_ring_size = RX_RING_DEFAULT; |
4940 | np->tx_ring_size = TX_RING_DEFAULT; | |
eafa59f6 | 4941 | |
ee73362c MS |
4942 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
4943 | np->rx_ring.orig = pci_alloc_consistent(pci_dev, | |
eafa59f6 | 4944 | sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
4945 | &np->ring_addr); |
4946 | if (!np->rx_ring.orig) | |
4947 | goto out_unmap; | |
eafa59f6 | 4948 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
ee73362c MS |
4949 | } else { |
4950 | np->rx_ring.ex = pci_alloc_consistent(pci_dev, | |
eafa59f6 | 4951 | sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
4952 | &np->ring_addr); |
4953 | if (!np->rx_ring.ex) | |
4954 | goto out_unmap; | |
eafa59f6 AA |
4955 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
4956 | } | |
761fcd9e AA |
4957 | np->rx_skb = kmalloc(sizeof(struct nv_skb_map) * np->rx_ring_size, GFP_KERNEL); |
4958 | np->tx_skb = kmalloc(sizeof(struct nv_skb_map) * np->tx_ring_size, GFP_KERNEL); | |
4959 | if (!np->rx_skb || !np->tx_skb) | |
eafa59f6 | 4960 | goto out_freering; |
761fcd9e AA |
4961 | memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); |
4962 | memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); | |
1da177e4 LT |
4963 | |
4964 | dev->open = nv_open; | |
4965 | dev->stop = nv_close; | |
86b22b0d AA |
4966 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
4967 | dev->hard_start_xmit = nv_start_xmit; | |
4968 | else | |
4969 | dev->hard_start_xmit = nv_start_xmit_optimized; | |
1da177e4 LT |
4970 | dev->get_stats = nv_get_stats; |
4971 | dev->change_mtu = nv_change_mtu; | |
72b31782 | 4972 | dev->set_mac_address = nv_set_mac_address; |
1da177e4 | 4973 | dev->set_multicast_list = nv_set_multicast; |
2918c35d MS |
4974 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4975 | dev->poll_controller = nv_poll_controller; | |
e27cdba5 | 4976 | #endif |
f0734ab6 | 4977 | dev->weight = RX_WORK_PER_LOOP; |
e27cdba5 SH |
4978 | #ifdef CONFIG_FORCEDETH_NAPI |
4979 | dev->poll = nv_napi_poll; | |
2918c35d | 4980 | #endif |
1da177e4 LT |
4981 | SET_ETHTOOL_OPS(dev, &ops); |
4982 | dev->tx_timeout = nv_tx_timeout; | |
4983 | dev->watchdog_timeo = NV_WATCHDOG_TIMEO; | |
4984 | ||
4985 | pci_set_drvdata(pci_dev, dev); | |
4986 | ||
4987 | /* read the mac address */ | |
4988 | base = get_hwbase(dev); | |
4989 | np->orig_mac[0] = readl(base + NvRegMacAddrA); | |
4990 | np->orig_mac[1] = readl(base + NvRegMacAddrB); | |
4991 | ||
5070d340 AA |
4992 | /* check the workaround bit for correct mac address order */ |
4993 | txreg = readl(base + NvRegTransmitPoll); | |
4994 | if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) { | |
4995 | /* mac address is already in correct order */ | |
4996 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
4997 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
4998 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
4999 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5000 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5001 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
5002 | } else { | |
5003 | /* need to reverse mac address to correct order */ | |
5004 | dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; | |
5005 | dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; | |
5006 | dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; | |
5007 | dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; | |
5008 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; | |
5009 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; | |
5010 | /* set permanent address to be correct aswell */ | |
5011 | np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + | |
5012 | (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); | |
5013 | np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); | |
5014 | writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); | |
5015 | } | |
c704b856 | 5016 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 5017 | |
c704b856 | 5018 | if (!is_valid_ether_addr(dev->perm_addr)) { |
1da177e4 LT |
5019 | /* |
5020 | * Bad mac address. At least one bios sets the mac address | |
5021 | * to 01:23:45:67:89:ab | |
5022 | */ | |
5023 | printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n", | |
5024 | pci_name(pci_dev), | |
5025 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
5026 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
5027 | printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n"); | |
5028 | dev->dev_addr[0] = 0x00; | |
5029 | dev->dev_addr[1] = 0x00; | |
5030 | dev->dev_addr[2] = 0x6c; | |
5031 | get_random_bytes(&dev->dev_addr[3], 3); | |
5032 | } | |
5033 | ||
5034 | dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev), | |
5035 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
5036 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
5037 | ||
f1489653 AA |
5038 | /* set mac address */ |
5039 | nv_copy_mac_to_hw(dev); | |
5040 | ||
1da177e4 LT |
5041 | /* disable WOL */ |
5042 | writel(0, base + NvRegWakeUpFlags); | |
5043 | np->wolenabled = 0; | |
5044 | ||
86a0f043 AA |
5045 | if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
5046 | u8 revision_id; | |
5047 | pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id); | |
5048 | ||
5049 | /* take phy and nic out of low power mode */ | |
5050 | powerstate = readl(base + NvRegPowerState2); | |
5051 | powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; | |
5052 | if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 || | |
5053 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) && | |
5054 | revision_id >= 0xA3) | |
5055 | powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; | |
5056 | writel(powerstate, base + NvRegPowerState2); | |
5057 | } | |
5058 | ||
1da177e4 | 5059 | if (np->desc_ver == DESC_VER_1) { |
ac9c1897 | 5060 | np->tx_flags = NV_TX_VALID; |
1da177e4 | 5061 | } else { |
ac9c1897 | 5062 | np->tx_flags = NV_TX2_VALID; |
1da177e4 | 5063 | } |
d33a73c8 | 5064 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) { |
a971c324 | 5065 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; |
d33a73c8 AA |
5066 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
5067 | np->msi_flags |= 0x0003; | |
5068 | } else { | |
a971c324 | 5069 | np->irqmask = NVREG_IRQMASK_CPU; |
d33a73c8 AA |
5070 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
5071 | np->msi_flags |= 0x0001; | |
5072 | } | |
a971c324 | 5073 | |
1da177e4 LT |
5074 | if (id->driver_data & DEV_NEED_TIMERIRQ) |
5075 | np->irqmask |= NVREG_IRQ_TIMER; | |
5076 | if (id->driver_data & DEV_NEED_LINKTIMER) { | |
5077 | dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev)); | |
5078 | np->need_linktimer = 1; | |
5079 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
5080 | } else { | |
5081 | dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev)); | |
5082 | np->need_linktimer = 0; | |
5083 | } | |
5084 | ||
7e680c22 AA |
5085 | /* clear phy state and temporarily halt phy interrupts */ |
5086 | writel(0, base + NvRegMIIMask); | |
5087 | phystate = readl(base + NvRegAdapterControl); | |
5088 | if (phystate & NVREG_ADAPTCTL_RUNNING) { | |
5089 | phystate_orig = 1; | |
5090 | phystate &= ~NVREG_ADAPTCTL_RUNNING; | |
5091 | writel(phystate, base + NvRegAdapterControl); | |
5092 | } | |
5093 | writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); | |
5094 | ||
5095 | if (id->driver_data & DEV_HAS_MGMT_UNIT) { | |
7e680c22 | 5096 | /* management unit running on the mac? */ |
f35723ec AA |
5097 | if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) { |
5098 | np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST; | |
5099 | dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use); | |
5100 | for (i = 0; i < 5000; i++) { | |
5101 | msleep(1); | |
5102 | if (nv_mgmt_acquire_sema(dev)) { | |
5103 | /* management unit setup the phy already? */ | |
5104 | if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == | |
5105 | NVREG_XMITCTL_SYNC_PHY_INIT) { | |
5106 | /* phy is inited by mgmt unit */ | |
5107 | phyinitialized = 1; | |
5108 | dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev)); | |
5109 | } else { | |
5110 | /* we need to init the phy */ | |
7e680c22 | 5111 | } |
f35723ec | 5112 | break; |
7e680c22 | 5113 | } |
7e680c22 AA |
5114 | } |
5115 | } | |
5116 | } | |
5117 | ||
1da177e4 | 5118 | /* find a suitable phy */ |
7a33e45a | 5119 | for (i = 1; i <= 32; i++) { |
1da177e4 | 5120 | int id1, id2; |
7a33e45a | 5121 | int phyaddr = i & 0x1F; |
1da177e4 LT |
5122 | |
5123 | spin_lock_irq(&np->lock); | |
7a33e45a | 5124 | id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); |
1da177e4 LT |
5125 | spin_unlock_irq(&np->lock); |
5126 | if (id1 < 0 || id1 == 0xffff) | |
5127 | continue; | |
5128 | spin_lock_irq(&np->lock); | |
7a33e45a | 5129 | id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); |
1da177e4 LT |
5130 | spin_unlock_irq(&np->lock); |
5131 | if (id2 < 0 || id2 == 0xffff) | |
5132 | continue; | |
5133 | ||
edf7e5ec | 5134 | np->phy_model = id2 & PHYID2_MODEL_MASK; |
1da177e4 LT |
5135 | id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
5136 | id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; | |
5137 | dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n", | |
7a33e45a AA |
5138 | pci_name(pci_dev), id1, id2, phyaddr); |
5139 | np->phyaddr = phyaddr; | |
1da177e4 LT |
5140 | np->phy_oui = id1 | id2; |
5141 | break; | |
5142 | } | |
7a33e45a | 5143 | if (i == 33) { |
1da177e4 | 5144 | printk(KERN_INFO "%s: open: Could not find a valid PHY.\n", |
7a33e45a | 5145 | pci_name(pci_dev)); |
eafa59f6 | 5146 | goto out_error; |
1da177e4 | 5147 | } |
f3b197ac | 5148 | |
7e680c22 AA |
5149 | if (!phyinitialized) { |
5150 | /* reset it */ | |
5151 | phy_init(dev); | |
f35723ec AA |
5152 | } else { |
5153 | /* see if it is a gigabit phy */ | |
5154 | u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
5155 | if (mii_status & PHY_GIGABIT) { | |
5156 | np->gigabit = PHY_GIGABIT; | |
5157 | } | |
7e680c22 | 5158 | } |
1da177e4 LT |
5159 | |
5160 | /* set default link speed settings */ | |
5161 | np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
5162 | np->duplex = 0; | |
5163 | np->autoneg = 1; | |
5164 | ||
5165 | err = register_netdev(dev); | |
5166 | if (err) { | |
5167 | printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err); | |
eafa59f6 | 5168 | goto out_error; |
1da177e4 LT |
5169 | } |
5170 | printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n", | |
5171 | dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device, | |
5172 | pci_name(pci_dev)); | |
5173 | ||
5174 | return 0; | |
5175 | ||
eafa59f6 | 5176 | out_error: |
7e680c22 AA |
5177 | if (phystate_orig) |
5178 | writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); | |
1da177e4 | 5179 | pci_set_drvdata(pci_dev, NULL); |
eafa59f6 AA |
5180 | out_freering: |
5181 | free_rings(dev); | |
1da177e4 LT |
5182 | out_unmap: |
5183 | iounmap(get_hwbase(dev)); | |
5184 | out_relreg: | |
5185 | pci_release_regions(pci_dev); | |
5186 | out_disable: | |
5187 | pci_disable_device(pci_dev); | |
5188 | out_free: | |
5189 | free_netdev(dev); | |
5190 | out: | |
5191 | return err; | |
5192 | } | |
5193 | ||
5194 | static void __devexit nv_remove(struct pci_dev *pci_dev) | |
5195 | { | |
5196 | struct net_device *dev = pci_get_drvdata(pci_dev); | |
f1489653 AA |
5197 | struct fe_priv *np = netdev_priv(dev); |
5198 | u8 __iomem *base = get_hwbase(dev); | |
1da177e4 LT |
5199 | |
5200 | unregister_netdev(dev); | |
5201 | ||
f1489653 AA |
5202 | /* special op: write back the misordered MAC address - otherwise |
5203 | * the next nv_probe would see a wrong address. | |
5204 | */ | |
5205 | writel(np->orig_mac[0], base + NvRegMacAddrA); | |
5206 | writel(np->orig_mac[1], base + NvRegMacAddrB); | |
5207 | ||
1da177e4 | 5208 | /* free all structures */ |
eafa59f6 | 5209 | free_rings(dev); |
1da177e4 LT |
5210 | iounmap(get_hwbase(dev)); |
5211 | pci_release_regions(pci_dev); | |
5212 | pci_disable_device(pci_dev); | |
5213 | free_netdev(dev); | |
5214 | pci_set_drvdata(pci_dev, NULL); | |
5215 | } | |
5216 | ||
a189317f FR |
5217 | #ifdef CONFIG_PM |
5218 | static int nv_suspend(struct pci_dev *pdev, pm_message_t state) | |
5219 | { | |
5220 | struct net_device *dev = pci_get_drvdata(pdev); | |
5221 | struct fe_priv *np = netdev_priv(dev); | |
5222 | ||
5223 | if (!netif_running(dev)) | |
5224 | goto out; | |
5225 | ||
5226 | netif_device_detach(dev); | |
5227 | ||
5228 | // Gross. | |
5229 | nv_close(dev); | |
5230 | ||
5231 | pci_save_state(pdev); | |
5232 | pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled); | |
5233 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
5234 | out: | |
5235 | return 0; | |
5236 | } | |
5237 | ||
5238 | static int nv_resume(struct pci_dev *pdev) | |
5239 | { | |
5240 | struct net_device *dev = pci_get_drvdata(pdev); | |
5241 | int rc = 0; | |
5242 | ||
5243 | if (!netif_running(dev)) | |
5244 | goto out; | |
5245 | ||
5246 | netif_device_attach(dev); | |
5247 | ||
5248 | pci_set_power_state(pdev, PCI_D0); | |
5249 | pci_restore_state(pdev); | |
5250 | pci_enable_wake(pdev, PCI_D0, 0); | |
5251 | ||
5252 | rc = nv_open(dev); | |
5253 | out: | |
5254 | return rc; | |
5255 | } | |
5256 | #else | |
5257 | #define nv_suspend NULL | |
5258 | #define nv_resume NULL | |
5259 | #endif /* CONFIG_PM */ | |
5260 | ||
1da177e4 LT |
5261 | static struct pci_device_id pci_tbl[] = { |
5262 | { /* nForce Ethernet Controller */ | |
dc8216c1 | 5263 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1), |
c2dba06d | 5264 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
5265 | }, |
5266 | { /* nForce2 Ethernet Controller */ | |
dc8216c1 | 5267 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2), |
c2dba06d | 5268 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
5269 | }, |
5270 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 5271 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3), |
c2dba06d | 5272 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
5273 | }, |
5274 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 5275 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4), |
8a4ae7f2 | 5276 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
5277 | }, |
5278 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 5279 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5), |
8a4ae7f2 | 5280 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
5281 | }, |
5282 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 5283 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6), |
8a4ae7f2 | 5284 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
5285 | }, |
5286 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 5287 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7), |
8a4ae7f2 | 5288 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
5289 | }, |
5290 | { /* CK804 Ethernet Controller */ | |
dc8216c1 | 5291 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8), |
8a4ae7f2 | 5292 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
1da177e4 LT |
5293 | }, |
5294 | { /* CK804 Ethernet Controller */ | |
dc8216c1 | 5295 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9), |
8a4ae7f2 | 5296 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
1da177e4 LT |
5297 | }, |
5298 | { /* MCP04 Ethernet Controller */ | |
dc8216c1 | 5299 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10), |
8a4ae7f2 | 5300 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
1da177e4 LT |
5301 | }, |
5302 | { /* MCP04 Ethernet Controller */ | |
dc8216c1 | 5303 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11), |
8a4ae7f2 | 5304 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
1da177e4 | 5305 | }, |
9992d4aa | 5306 | { /* MCP51 Ethernet Controller */ |
dc8216c1 | 5307 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12), |
86a0f043 | 5308 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL, |
9992d4aa MS |
5309 | }, |
5310 | { /* MCP51 Ethernet Controller */ | |
dc8216c1 | 5311 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13), |
86a0f043 | 5312 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL, |
9992d4aa | 5313 | }, |
f49d16ef | 5314 | { /* MCP55 Ethernet Controller */ |
dc8216c1 | 5315 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), |
7e680c22 | 5316 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
f49d16ef MS |
5317 | }, |
5318 | { /* MCP55 Ethernet Controller */ | |
dc8216c1 | 5319 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), |
7e680c22 | 5320 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
f49d16ef | 5321 | }, |
c99ce7ee AA |
5322 | { /* MCP61 Ethernet Controller */ |
5323 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16), | |
7e680c22 | 5324 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
c99ce7ee AA |
5325 | }, |
5326 | { /* MCP61 Ethernet Controller */ | |
5327 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17), | |
7e680c22 | 5328 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
c99ce7ee AA |
5329 | }, |
5330 | { /* MCP61 Ethernet Controller */ | |
5331 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18), | |
7e680c22 | 5332 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
c99ce7ee AA |
5333 | }, |
5334 | { /* MCP61 Ethernet Controller */ | |
5335 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19), | |
7e680c22 | 5336 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
c99ce7ee AA |
5337 | }, |
5338 | { /* MCP65 Ethernet Controller */ | |
5339 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20), | |
7e680c22 | 5340 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
c99ce7ee AA |
5341 | }, |
5342 | { /* MCP65 Ethernet Controller */ | |
5343 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21), | |
7e680c22 | 5344 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
c99ce7ee AA |
5345 | }, |
5346 | { /* MCP65 Ethernet Controller */ | |
5347 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22), | |
7e680c22 | 5348 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
c99ce7ee AA |
5349 | }, |
5350 | { /* MCP65 Ethernet Controller */ | |
5351 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23), | |
7e680c22 | 5352 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
c99ce7ee | 5353 | }, |
f4344848 AA |
5354 | { /* MCP67 Ethernet Controller */ |
5355 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24), | |
5356 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, | |
5357 | }, | |
5358 | { /* MCP67 Ethernet Controller */ | |
5359 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25), | |
5360 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, | |
5361 | }, | |
5362 | { /* MCP67 Ethernet Controller */ | |
5363 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26), | |
5364 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, | |
5365 | }, | |
5366 | { /* MCP67 Ethernet Controller */ | |
5367 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27), | |
5368 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, | |
5369 | }, | |
1da177e4 LT |
5370 | {0,}, |
5371 | }; | |
5372 | ||
5373 | static struct pci_driver driver = { | |
5374 | .name = "forcedeth", | |
5375 | .id_table = pci_tbl, | |
5376 | .probe = nv_probe, | |
5377 | .remove = __devexit_p(nv_remove), | |
a189317f FR |
5378 | .suspend = nv_suspend, |
5379 | .resume = nv_resume, | |
1da177e4 LT |
5380 | }; |
5381 | ||
1da177e4 LT |
5382 | static int __init init_nic(void) |
5383 | { | |
5384 | printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION); | |
29917620 | 5385 | return pci_register_driver(&driver); |
1da177e4 LT |
5386 | } |
5387 | ||
5388 | static void __exit exit_nic(void) | |
5389 | { | |
5390 | pci_unregister_driver(&driver); | |
5391 | } | |
5392 | ||
5393 | module_param(max_interrupt_work, int, 0); | |
5394 | MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt"); | |
a971c324 AA |
5395 | module_param(optimization_mode, int, 0); |
5396 | MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer."); | |
5397 | module_param(poll_interval, int, 0); | |
5398 | MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535."); | |
69fe3fd7 AA |
5399 | module_param(msi, int, 0); |
5400 | MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0."); | |
5401 | module_param(msix, int, 0); | |
5402 | MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0."); | |
5403 | module_param(dma_64bit, int, 0); | |
5404 | MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0."); | |
1da177e4 LT |
5405 | |
5406 | MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>"); | |
5407 | MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver"); | |
5408 | MODULE_LICENSE("GPL"); | |
5409 | ||
5410 | MODULE_DEVICE_TABLE(pci, pci_tbl); | |
5411 | ||
5412 | module_init(init_nic); | |
5413 | module_exit(exit_nic); |