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1577ecef AF |
1 | /* |
2 | * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation | |
3 | * Provides Bus interface for MIIM regs | |
4 | * | |
5 | * Author: Andy Fleming <afleming@freescale.com> | |
6 | * | |
7 | * Copyright (c) 2002-2004,2008 Freescale Semiconductor, Inc. | |
8 | * | |
9 | * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips) | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/unistd.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/netdevice.h> | |
27 | #include <linux/etherdevice.h> | |
28 | #include <linux/skbuff.h> | |
29 | #include <linux/spinlock.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/crc32.h> | |
34 | #include <linux/mii.h> | |
35 | #include <linux/phy.h> | |
36 | #include <linux/of.h> | |
324931ba | 37 | #include <linux/of_mdio.h> |
1577ecef AF |
38 | #include <linux/of_platform.h> |
39 | ||
40 | #include <asm/io.h> | |
41 | #include <asm/irq.h> | |
42 | #include <asm/uaccess.h> | |
43 | #include <asm/ucc.h> | |
44 | ||
45 | #include "gianfar.h" | |
46 | #include "fsl_pq_mdio.h" | |
47 | ||
48 | /* | |
49 | * Write value to the PHY at mii_id at register regnum, | |
50 | * on the bus attached to the local interface, which may be different from the | |
51 | * generic mdio bus (tied to a single interface), waiting until the write is | |
52 | * done before returning. This is helpful in programming interfaces like | |
53 | * the TBI which control interfaces like onchip SERDES and are always tied to | |
54 | * the local mdio pins, which may not be the same as system mdio bus, used for | |
55 | * controlling the external PHYs, for example. | |
56 | */ | |
57 | int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id, | |
58 | int regnum, u16 value) | |
59 | { | |
60 | /* Set the PHY address and the register address we want to write */ | |
61 | out_be32(®s->miimadd, (mii_id << 8) | regnum); | |
62 | ||
63 | /* Write out the value we want */ | |
64 | out_be32(®s->miimcon, value); | |
65 | ||
66 | /* Wait for the transaction to finish */ | |
67 | while (in_be32(®s->miimind) & MIIMIND_BUSY) | |
68 | cpu_relax(); | |
69 | ||
70 | return 0; | |
71 | } | |
72 | ||
73 | /* | |
74 | * Read the bus for PHY at addr mii_id, register regnum, and | |
75 | * return the value. Clears miimcom first. All PHY operation | |
76 | * done on the bus attached to the local interface, | |
77 | * which may be different from the generic mdio bus | |
78 | * This is helpful in programming interfaces like | |
79 | * the TBI which, in turn, control interfaces like onchip SERDES | |
80 | * and are always tied to the local mdio pins, which may not be the | |
81 | * same as system mdio bus, used for controlling the external PHYs, for eg. | |
82 | */ | |
83 | int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs, | |
84 | int mii_id, int regnum) | |
85 | { | |
86 | u16 value; | |
87 | ||
88 | /* Set the PHY address and the register address we want to read */ | |
89 | out_be32(®s->miimadd, (mii_id << 8) | regnum); | |
90 | ||
91 | /* Clear miimcom, and then initiate a read */ | |
92 | out_be32(®s->miimcom, 0); | |
93 | out_be32(®s->miimcom, MII_READ_COMMAND); | |
94 | ||
95 | /* Wait for the transaction to finish */ | |
96 | while (in_be32(®s->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY)) | |
97 | cpu_relax(); | |
98 | ||
99 | /* Grab the value of the register from miimstat */ | |
100 | value = in_be32(®s->miimstat); | |
101 | ||
102 | return value; | |
103 | } | |
104 | ||
105 | /* | |
106 | * Write value to the PHY at mii_id at register regnum, | |
107 | * on the bus, waiting until the write is done before returning. | |
108 | */ | |
109 | int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value) | |
110 | { | |
111 | struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv; | |
112 | ||
113 | /* Write to the local MII regs */ | |
114 | return(fsl_pq_local_mdio_write(regs, mii_id, regnum, value)); | |
115 | } | |
116 | ||
117 | /* | |
118 | * Read the bus for PHY at addr mii_id, register regnum, and | |
119 | * return the value. Clears miimcom first. | |
120 | */ | |
121 | int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum) | |
122 | { | |
123 | struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv; | |
124 | ||
125 | /* Read the local MII regs */ | |
126 | return(fsl_pq_local_mdio_read(regs, mii_id, regnum)); | |
127 | } | |
128 | ||
129 | /* Reset the MIIM registers, and wait for the bus to free */ | |
130 | static int fsl_pq_mdio_reset(struct mii_bus *bus) | |
131 | { | |
132 | struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv; | |
508827ff | 133 | int timeout = PHY_INIT_TIMEOUT; |
1577ecef AF |
134 | |
135 | mutex_lock(&bus->mdio_lock); | |
136 | ||
137 | /* Reset the management interface */ | |
138 | out_be32(®s->miimcfg, MIIMCFG_RESET); | |
139 | ||
140 | /* Setup the MII Mgmt clock speed */ | |
141 | out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE); | |
142 | ||
143 | /* Wait until the bus is free */ | |
144 | while ((in_be32(®s->miimind) & MIIMIND_BUSY) && timeout--) | |
145 | cpu_relax(); | |
146 | ||
147 | mutex_unlock(&bus->mdio_lock); | |
148 | ||
508827ff | 149 | if (timeout < 0) { |
1577ecef AF |
150 | printk(KERN_ERR "%s: The MII Bus is stuck!\n", |
151 | bus->name); | |
152 | return -EBUSY; | |
153 | } | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
1577ecef AF |
158 | void fsl_pq_mdio_bus_name(char *name, struct device_node *np) |
159 | { | |
18f27383 AV |
160 | const u32 *addr; |
161 | u64 taddr = OF_BAD_ADDR; | |
1577ecef | 162 | |
18f27383 AV |
163 | addr = of_get_address(np, 0, NULL, NULL); |
164 | if (addr) | |
165 | taddr = of_translate_address(np, addr); | |
1577ecef | 166 | |
18f27383 AV |
167 | snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name, |
168 | (unsigned long long)taddr); | |
1577ecef | 169 | } |
b6bc978b | 170 | EXPORT_SYMBOL_GPL(fsl_pq_mdio_bus_name); |
1577ecef AF |
171 | |
172 | /* Scan the bus in reverse, looking for an empty spot */ | |
173 | static int fsl_pq_mdio_find_free(struct mii_bus *new_bus) | |
174 | { | |
175 | int i; | |
176 | ||
177 | for (i = PHY_MAX_ADDR; i > 0; i--) { | |
178 | u32 phy_id; | |
179 | ||
180 | if (get_phy_id(new_bus, i, &phy_id)) | |
181 | return -1; | |
182 | ||
183 | if (phy_id == 0xffffffff) | |
184 | break; | |
185 | } | |
186 | ||
187 | return i; | |
188 | } | |
189 | ||
190 | ||
e2a61fa3 | 191 | #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE) |
1577ecef AF |
192 | static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs) |
193 | { | |
194 | struct gfar __iomem *enet_regs; | |
195 | ||
196 | /* | |
197 | * This is mildly evil, but so is our hardware for doing this. | |
198 | * Also, we have to cast back to struct gfar because of | |
199 | * definition weirdness done in gianfar.h. | |
200 | */ | |
201 | enet_regs = (struct gfar __iomem *) | |
202 | ((char __iomem *)regs - offsetof(struct gfar, gfar_mii_regs)); | |
203 | ||
204 | return &enet_regs->tbipa; | |
205 | } | |
206 | #endif | |
207 | ||
208 | ||
e2a61fa3 | 209 | #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE) |
1577ecef AF |
210 | static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id) |
211 | { | |
212 | struct device_node *np = NULL; | |
213 | int err = 0; | |
214 | ||
215 | for_each_compatible_node(np, NULL, "ucc_geth") { | |
216 | struct resource tempres; | |
217 | ||
218 | err = of_address_to_resource(np, 0, &tempres); | |
219 | if (err) | |
220 | continue; | |
221 | ||
222 | /* if our mdio regs fall within this UCC regs range */ | |
223 | if ((start >= tempres.start) && (end <= tempres.end)) { | |
224 | /* Find the id of the UCC */ | |
225 | const u32 *id; | |
226 | ||
227 | id = of_get_property(np, "cell-index", NULL); | |
228 | if (!id) { | |
229 | id = of_get_property(np, "device-id", NULL); | |
230 | if (!id) | |
231 | continue; | |
232 | } | |
233 | ||
234 | *ucc_id = *id; | |
235 | ||
236 | return 0; | |
237 | } | |
238 | } | |
239 | ||
240 | if (err) | |
241 | return err; | |
242 | else | |
243 | return -EINVAL; | |
244 | } | |
245 | #endif | |
246 | ||
247 | ||
248 | static int fsl_pq_mdio_probe(struct of_device *ofdev, | |
249 | const struct of_device_id *match) | |
250 | { | |
251 | struct device_node *np = ofdev->node; | |
252 | struct device_node *tbi; | |
253 | struct fsl_pq_mdio __iomem *regs; | |
254 | u32 __iomem *tbipa; | |
255 | struct mii_bus *new_bus; | |
256 | int tbiaddr = -1; | |
257 | u64 addr, size; | |
258 | int err = 0; | |
259 | ||
260 | new_bus = mdiobus_alloc(); | |
261 | if (NULL == new_bus) | |
262 | return -ENOMEM; | |
263 | ||
264 | new_bus->name = "Freescale PowerQUICC MII Bus", | |
265 | new_bus->read = &fsl_pq_mdio_read, | |
266 | new_bus->write = &fsl_pq_mdio_write, | |
267 | new_bus->reset = &fsl_pq_mdio_reset, | |
268 | fsl_pq_mdio_bus_name(new_bus->id, np); | |
269 | ||
270 | /* Set the PHY base address */ | |
271 | addr = of_translate_address(np, of_get_address(np, 0, &size, NULL)); | |
272 | regs = ioremap(addr, size); | |
273 | ||
274 | if (NULL == regs) { | |
275 | err = -ENOMEM; | |
276 | goto err_free_bus; | |
277 | } | |
278 | ||
279 | new_bus->priv = (void __force *)regs; | |
280 | ||
324931ba | 281 | new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); |
1577ecef AF |
282 | |
283 | if (NULL == new_bus->irq) { | |
284 | err = -ENOMEM; | |
285 | goto err_unmap_regs; | |
286 | } | |
287 | ||
288 | new_bus->parent = &ofdev->dev; | |
289 | dev_set_drvdata(&ofdev->dev, new_bus); | |
290 | ||
291 | if (of_device_is_compatible(np, "fsl,gianfar-mdio") || | |
30196845 | 292 | of_device_is_compatible(np, "fsl,gianfar-tbi") || |
1577ecef | 293 | of_device_is_compatible(np, "gianfar")) { |
e2a61fa3 | 294 | #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE) |
1577ecef AF |
295 | tbipa = get_gfar_tbipa(regs); |
296 | #else | |
297 | err = -ENODEV; | |
298 | goto err_free_irqs; | |
299 | #endif | |
300 | } else if (of_device_is_compatible(np, "fsl,ucc-mdio") || | |
301 | of_device_is_compatible(np, "ucc_geth_phy")) { | |
e2a61fa3 | 302 | #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE) |
1577ecef | 303 | u32 id; |
fbcc0e2c | 304 | static u32 mii_mng_master; |
1577ecef AF |
305 | |
306 | tbipa = ®s->utbipar; | |
307 | ||
308 | if ((err = get_ucc_id_for_range(addr, addr + size, &id))) | |
309 | goto err_free_irqs; | |
310 | ||
fbcc0e2c HW |
311 | if (!mii_mng_master) { |
312 | mii_mng_master = id; | |
313 | ucc_set_qe_mux_mii_mng(id - 1); | |
314 | } | |
1577ecef AF |
315 | #else |
316 | err = -ENODEV; | |
317 | goto err_free_irqs; | |
318 | #endif | |
319 | } else { | |
320 | err = -ENODEV; | |
321 | goto err_free_irqs; | |
322 | } | |
323 | ||
324 | for_each_child_of_node(np, tbi) { | |
325 | if (!strncmp(tbi->type, "tbi-phy", 8)) | |
326 | break; | |
327 | } | |
328 | ||
329 | if (tbi) { | |
330 | const u32 *prop = of_get_property(tbi, "reg", NULL); | |
331 | ||
332 | if (prop) | |
333 | tbiaddr = *prop; | |
334 | } | |
335 | ||
336 | if (tbiaddr == -1) { | |
337 | out_be32(tbipa, 0); | |
338 | ||
339 | tbiaddr = fsl_pq_mdio_find_free(new_bus); | |
340 | } | |
341 | ||
342 | /* | |
343 | * We define TBIPA at 0 to be illegal, opting to fail for boards that | |
344 | * have PHYs at 1-31, rather than change tbipa and rescan. | |
345 | */ | |
346 | if (tbiaddr == 0) { | |
347 | err = -EBUSY; | |
348 | ||
349 | goto err_free_irqs; | |
350 | } | |
351 | ||
352 | out_be32(tbipa, tbiaddr); | |
353 | ||
324931ba | 354 | err = of_mdiobus_register(new_bus, np); |
1577ecef AF |
355 | if (err) { |
356 | printk (KERN_ERR "%s: Cannot register as MDIO bus\n", | |
357 | new_bus->name); | |
358 | goto err_free_irqs; | |
359 | } | |
360 | ||
361 | return 0; | |
362 | ||
363 | err_free_irqs: | |
364 | kfree(new_bus->irq); | |
365 | err_unmap_regs: | |
366 | iounmap(regs); | |
367 | err_free_bus: | |
368 | kfree(new_bus); | |
369 | ||
370 | return err; | |
371 | } | |
372 | ||
373 | ||
374 | static int fsl_pq_mdio_remove(struct of_device *ofdev) | |
375 | { | |
376 | struct device *device = &ofdev->dev; | |
377 | struct mii_bus *bus = dev_get_drvdata(device); | |
378 | ||
379 | mdiobus_unregister(bus); | |
380 | ||
381 | dev_set_drvdata(device, NULL); | |
382 | ||
383 | iounmap((void __iomem *)bus->priv); | |
384 | bus->priv = NULL; | |
385 | mdiobus_free(bus); | |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
390 | static struct of_device_id fsl_pq_mdio_match[] = { | |
391 | { | |
392 | .type = "mdio", | |
393 | .compatible = "ucc_geth_phy", | |
394 | }, | |
395 | { | |
396 | .type = "mdio", | |
397 | .compatible = "gianfar", | |
398 | }, | |
399 | { | |
400 | .compatible = "fsl,ucc-mdio", | |
401 | }, | |
402 | { | |
403 | .compatible = "fsl,gianfar-tbi", | |
404 | }, | |
405 | { | |
406 | .compatible = "fsl,gianfar-mdio", | |
407 | }, | |
408 | {}, | |
409 | }; | |
410 | ||
411 | static struct of_platform_driver fsl_pq_mdio_driver = { | |
412 | .name = "fsl-pq_mdio", | |
413 | .probe = fsl_pq_mdio_probe, | |
414 | .remove = fsl_pq_mdio_remove, | |
415 | .match_table = fsl_pq_mdio_match, | |
416 | }; | |
417 | ||
418 | int __init fsl_pq_mdio_init(void) | |
419 | { | |
420 | return of_register_platform_driver(&fsl_pq_mdio_driver); | |
421 | } | |
434e7b0d | 422 | module_init(fsl_pq_mdio_init); |
1577ecef AF |
423 | |
424 | void fsl_pq_mdio_exit(void) | |
425 | { | |
426 | of_unregister_platform_driver(&fsl_pq_mdio_driver); | |
427 | } | |
1577ecef | 428 | module_exit(fsl_pq_mdio_exit); |