projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 8d77c036 PYC |
1 | /* |
| 2 | * Faraday FTMAC100 10/100 Ethernet | |
| 3 | * | |
| 4 | * (C) Copyright 2009-2011 Faraday Technology | |
| 5 | * Po-Yu Chuang <ratbert@faraday-tech.com> | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License as published by | |
| 9 | * the Free Software Foundation; either version 2 of the License, or | |
| 10 | * (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 20 | */ | |
| 21 | ||
| 22 | #ifndef __FTMAC100_H | |
| 23 | #define __FTMAC100_H | |
| 24 | ||
| 25 | #define FTMAC100_OFFSET_ISR 0x00 | |
| 26 | #define FTMAC100_OFFSET_IMR 0x04 | |
| 27 | #define FTMAC100_OFFSET_MAC_MADR 0x08 | |
| 28 | #define FTMAC100_OFFSET_MAC_LADR 0x0c | |
| 29 | #define FTMAC100_OFFSET_MAHT0 0x10 | |
| 30 | #define FTMAC100_OFFSET_MAHT1 0x14 | |
| 31 | #define FTMAC100_OFFSET_TXPD 0x18 | |
| 32 | #define FTMAC100_OFFSET_RXPD 0x1c | |
| 33 | #define FTMAC100_OFFSET_TXR_BADR 0x20 | |
| 34 | #define FTMAC100_OFFSET_RXR_BADR 0x24 | |
| 35 | #define FTMAC100_OFFSET_ITC 0x28 | |
| 36 | #define FTMAC100_OFFSET_APTC 0x2c | |
| 37 | #define FTMAC100_OFFSET_DBLAC 0x30 | |
| 38 | #define FTMAC100_OFFSET_MACCR 0x88 | |
| 39 | #define FTMAC100_OFFSET_MACSR 0x8c | |
| 40 | #define FTMAC100_OFFSET_PHYCR 0x90 | |
| 41 | #define FTMAC100_OFFSET_PHYWDATA 0x94 | |
| 42 | #define FTMAC100_OFFSET_FCR 0x98 | |
| 43 | #define FTMAC100_OFFSET_BPR 0x9c | |
| 44 | #define FTMAC100_OFFSET_TS 0xc4 | |
| 45 | #define FTMAC100_OFFSET_DMAFIFOS 0xc8 | |
| 46 | #define FTMAC100_OFFSET_TM 0xcc | |
| 47 | #define FTMAC100_OFFSET_TX_MCOL_SCOL 0xd4 | |
| 48 | #define FTMAC100_OFFSET_RPF_AEP 0xd8 | |
| 49 | #define FTMAC100_OFFSET_XM_PG 0xdc | |
| 50 | #define FTMAC100_OFFSET_RUNT_TLCC 0xe0 | |
| 51 | #define FTMAC100_OFFSET_CRCER_FTL 0xe4 | |
| 52 | #define FTMAC100_OFFSET_RLC_RCC 0xe8 | |
| 53 | #define FTMAC100_OFFSET_BROC 0xec | |
| 54 | #define FTMAC100_OFFSET_MULCA 0xf0 | |
| 55 | #define FTMAC100_OFFSET_RP 0xf4 | |
| 56 | #define FTMAC100_OFFSET_XP 0xf8 | |
| 57 | ||
| 58 | /* | |
| 59 | * Interrupt status register & interrupt mask register | |
| 60 | */ | |
| 61 | #define FTMAC100_INT_RPKT_FINISH (1 << 0) | |
| 62 | #define FTMAC100_INT_NORXBUF (1 << 1) | |
| 63 | #define FTMAC100_INT_XPKT_FINISH (1 << 2) | |
| 64 | #define FTMAC100_INT_NOTXBUF (1 << 3) | |
| 65 | #define FTMAC100_INT_XPKT_OK (1 << 4) | |
| 66 | #define FTMAC100_INT_XPKT_LOST (1 << 5) | |
| 67 | #define FTMAC100_INT_RPKT_SAV (1 << 6) | |
| 68 | #define FTMAC100_INT_RPKT_LOST (1 << 7) | |
| 69 | #define FTMAC100_INT_AHB_ERR (1 << 8) | |
| 70 | #define FTMAC100_INT_PHYSTS_CHG (1 << 9) | |
| 71 | ||
| 72 | /* | |
| 73 | * Interrupt timer control register | |
| 74 | */ | |
| 75 | #define FTMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) | |
| 76 | #define FTMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) | |
| 77 | #define FTMAC100_ITC_RXINT_TIME_SEL (1 << 7) | |
| 78 | #define FTMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) | |
| 79 | #define FTMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) | |
| 80 | #define FTMAC100_ITC_TXINT_TIME_SEL (1 << 15) | |
| 81 | ||
| 82 | /* | |
| 83 | * Automatic polling timer control register | |
| 84 | */ | |
| 85 | #define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) | |
| 86 | #define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) | |
| 87 | #define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) | |
| 88 | #define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) | |
| 89 | ||
| 90 | /* | |
| 91 | * DMA burst length and arbitration control register | |
| 92 | */ | |
| 93 | #define FTMAC100_DBLAC_INCR4_EN (1 << 0) | |
| 94 | #define FTMAC100_DBLAC_INCR8_EN (1 << 1) | |
| 95 | #define FTMAC100_DBLAC_INCR16_EN (1 << 2) | |
| 96 | #define FTMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 3) | |
| 97 | #define FTMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 6) | |
| 98 | #define FTMAC100_DBLAC_RX_THR_EN (1 << 9) | |
| 99 | ||
| 100 | /* | |
| 101 | * MAC control register | |
| 102 | */ | |
| 103 | #define FTMAC100_MACCR_XDMA_EN (1 << 0) | |
| 104 | #define FTMAC100_MACCR_RDMA_EN (1 << 1) | |
| 105 | #define FTMAC100_MACCR_SW_RST (1 << 2) | |
| 106 | #define FTMAC100_MACCR_LOOP_EN (1 << 3) | |
| 107 | #define FTMAC100_MACCR_CRC_DIS (1 << 4) | |
| 108 | #define FTMAC100_MACCR_XMT_EN (1 << 5) | |
| 109 | #define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6) | |
| 110 | #define FTMAC100_MACCR_RCV_EN (1 << 8) | |
| 111 | #define FTMAC100_MACCR_HT_MULTI_EN (1 << 9) | |
| 112 | #define FTMAC100_MACCR_RX_RUNT (1 << 10) | |
| 113 | #define FTMAC100_MACCR_RX_FTL (1 << 11) | |
| 114 | #define FTMAC100_MACCR_RCV_ALL (1 << 12) | |
| 115 | #define FTMAC100_MACCR_CRC_APD (1 << 14) | |
| 116 | #define FTMAC100_MACCR_FULLDUP (1 << 15) | |
| 117 | #define FTMAC100_MACCR_RX_MULTIPKT (1 << 16) | |
| 118 | #define FTMAC100_MACCR_RX_BROADPKT (1 << 17) | |
| 119 | ||
| 120 | /* | |
| 121 | * PHY control register | |
| 122 | */ | |
| 123 | #define FTMAC100_PHYCR_MIIRDATA 0xffff | |
| 124 | #define FTMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) | |
| 125 | #define FTMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) | |
| 126 | #define FTMAC100_PHYCR_MIIRD (1 << 26) | |
| 127 | #define FTMAC100_PHYCR_MIIWR (1 << 27) | |
| 128 | ||
| 129 | /* | |
| 130 | * PHY write data register | |
| 131 | */ | |
| 132 | #define FTMAC100_PHYWDATA_MIIWDATA(x) ((x) & 0xffff) | |
| 133 | ||
| 134 | /* | |
| 135 | * Transmit descriptor, aligned to 16 bytes | |
| 136 | */ | |
| 137 | struct ftmac100_txdes { | |
| 138 | unsigned int txdes0; | |
| 139 | unsigned int txdes1; | |
| 140 | unsigned int txdes2; /* TXBUF_BADR */ | |
| 141 | unsigned int txdes3; /* not used by HW */ | |
| 142 | } __attribute__ ((aligned(16))); | |
| 143 | ||
| 144 | #define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0) | |
| 145 | #define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1) | |
| 146 | #define FTMAC100_TXDES0_TXDMA_OWN (1 << 31) | |
| 147 | ||
| 148 | #define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff) | |
| 149 | #define FTMAC100_TXDES1_LTS (1 << 27) | |
| 150 | #define FTMAC100_TXDES1_FTS (1 << 28) | |
| 151 | #define FTMAC100_TXDES1_TX2FIC (1 << 29) | |
| 152 | #define FTMAC100_TXDES1_TXIC (1 << 30) | |
| 153 | #define FTMAC100_TXDES1_EDOTR (1 << 31) | |
| 154 | ||
| 155 | /* | |
| 156 | * Receive descriptor, aligned to 16 bytes | |
| 157 | */ | |
| 158 | struct ftmac100_rxdes { | |
| 159 | unsigned int rxdes0; | |
| 160 | unsigned int rxdes1; | |
| 161 | unsigned int rxdes2; /* RXBUF_BADR */ | |
| 162 | unsigned int rxdes3; /* not used by HW */ | |
| 163 | } __attribute__ ((aligned(16))); | |
| 164 | ||
| 165 | #define FTMAC100_RXDES0_RFL 0x7ff | |
| 166 | #define FTMAC100_RXDES0_MULTICAST (1 << 16) | |
| 167 | #define FTMAC100_RXDES0_BROADCAST (1 << 17) | |
| 168 | #define FTMAC100_RXDES0_RX_ERR (1 << 18) | |
| 169 | #define FTMAC100_RXDES0_CRC_ERR (1 << 19) | |
| 170 | #define FTMAC100_RXDES0_FTL (1 << 20) | |
| 171 | #define FTMAC100_RXDES0_RUNT (1 << 21) | |
| 172 | #define FTMAC100_RXDES0_RX_ODD_NB (1 << 22) | |
| 173 | #define FTMAC100_RXDES0_LRS (1 << 28) | |
| 174 | #define FTMAC100_RXDES0_FRS (1 << 29) | |
| 175 | #define FTMAC100_RXDES0_RXDMA_OWN (1 << 31) | |
| 176 | ||
| 177 | #define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff) | |
| 178 | #define FTMAC100_RXDES1_EDORR (1 << 31) | |
| 179 | ||
| 180 | #endif /* __FTMAC100_H */ |