Commit | Line | Data |
---|---|---|
0bbaf069 | 1 | /* |
1da177e4 LT |
2 | * drivers/net/gianfar.c |
3 | * | |
4 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
5 | * This driver is designed for the non-CPM ethernet controllers |
6 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
7 | * Based on 8260_io/fcc_enet.c |
8 | * | |
9 | * Author: Andy Fleming | |
4c8d3d99 | 10 | * Maintainer: Kumar Gala |
1da177e4 | 11 | * |
e8a2b6a4 | 12 | * Copyright (c) 2002-2006 Freescale Semiconductor, Inc. |
538cc7ee | 13 | * Copyright (c) 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
1da177e4 | 64 | #include <linux/kernel.h> |
1da177e4 LT |
65 | #include <linux/string.h> |
66 | #include <linux/errno.h> | |
bb40dcbb | 67 | #include <linux/unistd.h> |
1da177e4 LT |
68 | #include <linux/slab.h> |
69 | #include <linux/interrupt.h> | |
70 | #include <linux/init.h> | |
71 | #include <linux/delay.h> | |
72 | #include <linux/netdevice.h> | |
73 | #include <linux/etherdevice.h> | |
74 | #include <linux/skbuff.h> | |
0bbaf069 | 75 | #include <linux/if_vlan.h> |
1da177e4 LT |
76 | #include <linux/spinlock.h> |
77 | #include <linux/mm.h> | |
fe192a49 | 78 | #include <linux/of_mdio.h> |
b31a1d8b | 79 | #include <linux/of_platform.h> |
0bbaf069 KG |
80 | #include <linux/ip.h> |
81 | #include <linux/tcp.h> | |
82 | #include <linux/udp.h> | |
9c07b884 | 83 | #include <linux/in.h> |
1da177e4 LT |
84 | |
85 | #include <asm/io.h> | |
86 | #include <asm/irq.h> | |
87 | #include <asm/uaccess.h> | |
88 | #include <linux/module.h> | |
1da177e4 LT |
89 | #include <linux/dma-mapping.h> |
90 | #include <linux/crc32.h> | |
bb40dcbb AF |
91 | #include <linux/mii.h> |
92 | #include <linux/phy.h> | |
b31a1d8b AF |
93 | #include <linux/phy_fixed.h> |
94 | #include <linux/of.h> | |
1da177e4 LT |
95 | |
96 | #include "gianfar.h" | |
1577ecef | 97 | #include "fsl_pq_mdio.h" |
1da177e4 LT |
98 | |
99 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 LT |
100 | #undef BRIEF_GFAR_ERRORS |
101 | #undef VERBOSE_GFAR_ERRORS | |
102 | ||
1da177e4 | 103 | const char gfar_driver_name[] = "Gianfar Ethernet"; |
7f7f5316 | 104 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 105 | |
1da177e4 LT |
106 | static int gfar_enet_open(struct net_device *dev); |
107 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 108 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
109 | static void gfar_timeout(struct net_device *dev); |
110 | static int gfar_close(struct net_device *dev); | |
815b97c6 AF |
111 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
112 | static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp, | |
113 | struct sk_buff *skb); | |
1da177e4 LT |
114 | static int gfar_set_mac_address(struct net_device *dev); |
115 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
116 | static irqreturn_t gfar_error(int irq, void *dev_id); |
117 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
118 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
119 | static void adjust_link(struct net_device *dev); |
120 | static void init_registers(struct net_device *dev); | |
121 | static int init_phy(struct net_device *dev); | |
b31a1d8b AF |
122 | static int gfar_probe(struct of_device *ofdev, |
123 | const struct of_device_id *match); | |
124 | static int gfar_remove(struct of_device *ofdev); | |
bb40dcbb | 125 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
126 | static void gfar_set_multi(struct net_device *dev); |
127 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 128 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 129 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
130 | #ifdef CONFIG_NET_POLL_CONTROLLER |
131 | static void gfar_netpoll(struct net_device *dev); | |
132 | #endif | |
0bbaf069 | 133 | int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit); |
f162b9d5 | 134 | static int gfar_clean_tx_ring(struct net_device *dev); |
2c2db48a DH |
135 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
136 | int amount_pull); | |
0bbaf069 KG |
137 | static void gfar_vlan_rx_register(struct net_device *netdev, |
138 | struct vlan_group *grp); | |
7f7f5316 | 139 | void gfar_halt(struct net_device *dev); |
d87eb127 | 140 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
141 | void gfar_start(struct net_device *dev); |
142 | static void gfar_clear_exact_match(struct net_device *dev); | |
143 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr); | |
26ccfc37 | 144 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 145 | |
1da177e4 LT |
146 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
147 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
148 | MODULE_LICENSE("GPL"); | |
149 | ||
26ccfc37 AF |
150 | static const struct net_device_ops gfar_netdev_ops = { |
151 | .ndo_open = gfar_enet_open, | |
152 | .ndo_start_xmit = gfar_start_xmit, | |
153 | .ndo_stop = gfar_close, | |
154 | .ndo_change_mtu = gfar_change_mtu, | |
155 | .ndo_set_multicast_list = gfar_set_multi, | |
156 | .ndo_tx_timeout = gfar_timeout, | |
157 | .ndo_do_ioctl = gfar_ioctl, | |
158 | .ndo_vlan_rx_register = gfar_vlan_rx_register, | |
240c102d BH |
159 | .ndo_set_mac_address = eth_mac_addr, |
160 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
161 | #ifdef CONFIG_NET_POLL_CONTROLLER |
162 | .ndo_poll_controller = gfar_netpoll, | |
163 | #endif | |
164 | }; | |
165 | ||
7f7f5316 AF |
166 | /* Returns 1 if incoming frames use an FCB */ |
167 | static inline int gfar_uses_fcb(struct gfar_private *priv) | |
0bbaf069 | 168 | { |
77ecaf2d | 169 | return priv->vlgrp || priv->rx_csum_enable; |
0bbaf069 | 170 | } |
bb40dcbb | 171 | |
b31a1d8b AF |
172 | static int gfar_of_init(struct net_device *dev) |
173 | { | |
b31a1d8b AF |
174 | const char *model; |
175 | const char *ctype; | |
176 | const void *mac_addr; | |
b31a1d8b AF |
177 | u64 addr, size; |
178 | int err = 0; | |
179 | struct gfar_private *priv = netdev_priv(dev); | |
180 | struct device_node *np = priv->node; | |
4d7902f2 AF |
181 | const u32 *stash; |
182 | const u32 *stash_len; | |
183 | const u32 *stash_idx; | |
b31a1d8b AF |
184 | |
185 | if (!np || !of_device_is_available(np)) | |
186 | return -ENODEV; | |
187 | ||
188 | /* get a pointer to the register memory */ | |
189 | addr = of_translate_address(np, of_get_address(np, 0, &size, NULL)); | |
190 | priv->regs = ioremap(addr, size); | |
191 | ||
192 | if (priv->regs == NULL) | |
193 | return -ENOMEM; | |
194 | ||
195 | priv->interruptTransmit = irq_of_parse_and_map(np, 0); | |
196 | ||
197 | model = of_get_property(np, "model", NULL); | |
198 | ||
199 | /* If we aren't the FEC we have multiple interrupts */ | |
200 | if (model && strcasecmp(model, "FEC")) { | |
201 | priv->interruptReceive = irq_of_parse_and_map(np, 1); | |
202 | ||
203 | priv->interruptError = irq_of_parse_and_map(np, 2); | |
204 | ||
205 | if (priv->interruptTransmit < 0 || | |
206 | priv->interruptReceive < 0 || | |
207 | priv->interruptError < 0) { | |
208 | err = -EINVAL; | |
209 | goto err_out; | |
210 | } | |
211 | } | |
212 | ||
4d7902f2 AF |
213 | stash = of_get_property(np, "bd-stash", NULL); |
214 | ||
215 | if(stash) { | |
216 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; | |
217 | priv->bd_stash_en = 1; | |
218 | } | |
219 | ||
220 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
221 | ||
222 | if (stash_len) | |
223 | priv->rx_stash_size = *stash_len; | |
224 | ||
225 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
226 | ||
227 | if (stash_idx) | |
228 | priv->rx_stash_index = *stash_idx; | |
229 | ||
230 | if (stash_len || stash_idx) | |
231 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
232 | ||
b31a1d8b AF |
233 | mac_addr = of_get_mac_address(np); |
234 | if (mac_addr) | |
235 | memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN); | |
236 | ||
237 | if (model && !strcasecmp(model, "TSEC")) | |
238 | priv->device_flags = | |
239 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
240 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
241 | FSL_GIANFAR_DEV_HAS_RMON | | |
242 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
243 | if (model && !strcasecmp(model, "eTSEC")) | |
244 | priv->device_flags = | |
245 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
246 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
247 | FSL_GIANFAR_DEV_HAS_RMON | | |
248 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
2c2db48a | 249 | FSL_GIANFAR_DEV_HAS_PADDING | |
b31a1d8b AF |
250 | FSL_GIANFAR_DEV_HAS_CSUM | |
251 | FSL_GIANFAR_DEV_HAS_VLAN | | |
252 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
253 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH; | |
254 | ||
255 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
256 | ||
257 | /* We only care about rgmii-id. The rest are autodetected */ | |
258 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
259 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
260 | else | |
261 | priv->interface = PHY_INTERFACE_MODE_MII; | |
262 | ||
263 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
264 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
265 | ||
fe192a49 GL |
266 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
267 | if (!priv->phy_node) { | |
b31a1d8b AF |
268 | u32 *fixed_link; |
269 | ||
270 | fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL); | |
271 | if (!fixed_link) { | |
272 | err = -ENODEV; | |
273 | goto err_out; | |
274 | } | |
b31a1d8b AF |
275 | } |
276 | ||
277 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 278 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
279 | |
280 | return 0; | |
281 | ||
282 | err_out: | |
283 | iounmap(priv->regs); | |
284 | return err; | |
285 | } | |
286 | ||
0faac9f7 CW |
287 | /* Ioctl MII Interface */ |
288 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
289 | { | |
290 | struct gfar_private *priv = netdev_priv(dev); | |
291 | ||
292 | if (!netif_running(dev)) | |
293 | return -EINVAL; | |
294 | ||
295 | if (!priv->phydev) | |
296 | return -ENODEV; | |
297 | ||
298 | return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); | |
299 | } | |
300 | ||
bb40dcbb AF |
301 | /* Set up the ethernet device structure, private data, |
302 | * and anything else we need before we start */ | |
b31a1d8b AF |
303 | static int gfar_probe(struct of_device *ofdev, |
304 | const struct of_device_id *match) | |
1da177e4 LT |
305 | { |
306 | u32 tempval; | |
307 | struct net_device *dev = NULL; | |
308 | struct gfar_private *priv = NULL; | |
b31a1d8b | 309 | DECLARE_MAC_BUF(mac); |
c50a5d9a DH |
310 | int err = 0; |
311 | int len_devname; | |
1da177e4 LT |
312 | |
313 | /* Create an ethernet device instance */ | |
314 | dev = alloc_etherdev(sizeof (*priv)); | |
315 | ||
bb40dcbb | 316 | if (NULL == dev) |
1da177e4 LT |
317 | return -ENOMEM; |
318 | ||
319 | priv = netdev_priv(dev); | |
4826857f KG |
320 | priv->ndev = dev; |
321 | priv->ofdev = ofdev; | |
b31a1d8b | 322 | priv->node = ofdev->node; |
4826857f | 323 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 324 | |
b31a1d8b | 325 | err = gfar_of_init(dev); |
1da177e4 | 326 | |
b31a1d8b | 327 | if (err) |
1da177e4 | 328 | goto regs_fail; |
1da177e4 | 329 | |
fef6108d AF |
330 | spin_lock_init(&priv->txlock); |
331 | spin_lock_init(&priv->rxlock); | |
d87eb127 | 332 | spin_lock_init(&priv->bflock); |
ab939905 | 333 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 334 | |
b31a1d8b | 335 | dev_set_drvdata(&ofdev->dev, priv); |
1da177e4 LT |
336 | |
337 | /* Stop the DMA engine now, in case it was running before */ | |
338 | /* (The firmware could have used it, and left it running). */ | |
257d938a | 339 | gfar_halt(dev); |
1da177e4 LT |
340 | |
341 | /* Reset MAC layer */ | |
342 | gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); | |
343 | ||
b98ac702 AF |
344 | /* We need to delay at least 3 TX clocks */ |
345 | udelay(2); | |
346 | ||
1da177e4 LT |
347 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
348 | gfar_write(&priv->regs->maccfg1, tempval); | |
349 | ||
350 | /* Initialize MACCFG2. */ | |
351 | gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS); | |
352 | ||
353 | /* Initialize ECNTRL */ | |
354 | gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS); | |
355 | ||
1da177e4 LT |
356 | /* Set the dev->base_addr to the gfar reg region */ |
357 | dev->base_addr = (unsigned long) (priv->regs); | |
358 | ||
b31a1d8b | 359 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 LT |
360 | |
361 | /* Fill in the dev structure */ | |
1da177e4 | 362 | dev->watchdog_timeo = TX_TIMEOUT; |
bea3348e | 363 | netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT); |
1da177e4 | 364 | dev->mtu = 1500; |
1da177e4 | 365 | |
26ccfc37 | 366 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
367 | dev->ethtool_ops = &gfar_ethtool_ops; |
368 | ||
b31a1d8b | 369 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
0bbaf069 | 370 | priv->rx_csum_enable = 1; |
4669bc90 | 371 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA; |
0bbaf069 KG |
372 | } else |
373 | priv->rx_csum_enable = 0; | |
374 | ||
375 | priv->vlgrp = NULL; | |
1da177e4 | 376 | |
26ccfc37 | 377 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) |
0bbaf069 | 378 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
0bbaf069 | 379 | |
b31a1d8b | 380 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
381 | priv->extended_hash = 1; |
382 | priv->hash_width = 9; | |
383 | ||
384 | priv->hash_regs[0] = &priv->regs->igaddr0; | |
385 | priv->hash_regs[1] = &priv->regs->igaddr1; | |
386 | priv->hash_regs[2] = &priv->regs->igaddr2; | |
387 | priv->hash_regs[3] = &priv->regs->igaddr3; | |
388 | priv->hash_regs[4] = &priv->regs->igaddr4; | |
389 | priv->hash_regs[5] = &priv->regs->igaddr5; | |
390 | priv->hash_regs[6] = &priv->regs->igaddr6; | |
391 | priv->hash_regs[7] = &priv->regs->igaddr7; | |
392 | priv->hash_regs[8] = &priv->regs->gaddr0; | |
393 | priv->hash_regs[9] = &priv->regs->gaddr1; | |
394 | priv->hash_regs[10] = &priv->regs->gaddr2; | |
395 | priv->hash_regs[11] = &priv->regs->gaddr3; | |
396 | priv->hash_regs[12] = &priv->regs->gaddr4; | |
397 | priv->hash_regs[13] = &priv->regs->gaddr5; | |
398 | priv->hash_regs[14] = &priv->regs->gaddr6; | |
399 | priv->hash_regs[15] = &priv->regs->gaddr7; | |
400 | ||
401 | } else { | |
402 | priv->extended_hash = 0; | |
403 | priv->hash_width = 8; | |
404 | ||
405 | priv->hash_regs[0] = &priv->regs->gaddr0; | |
1577ecef | 406 | priv->hash_regs[1] = &priv->regs->gaddr1; |
0bbaf069 KG |
407 | priv->hash_regs[2] = &priv->regs->gaddr2; |
408 | priv->hash_regs[3] = &priv->regs->gaddr3; | |
409 | priv->hash_regs[4] = &priv->regs->gaddr4; | |
410 | priv->hash_regs[5] = &priv->regs->gaddr5; | |
411 | priv->hash_regs[6] = &priv->regs->gaddr6; | |
412 | priv->hash_regs[7] = &priv->regs->gaddr7; | |
413 | } | |
414 | ||
b31a1d8b | 415 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
416 | priv->padding = DEFAULT_PADDING; |
417 | else | |
418 | priv->padding = 0; | |
419 | ||
0bbaf069 KG |
420 | if (dev->features & NETIF_F_IP_CSUM) |
421 | dev->hard_header_len += GMAC_FCB_LEN; | |
1da177e4 LT |
422 | |
423 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; | |
1da177e4 LT |
424 | priv->tx_ring_size = DEFAULT_TX_RING_SIZE; |
425 | priv->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
4669bc90 | 426 | priv->num_txbdfree = DEFAULT_TX_RING_SIZE; |
1da177e4 LT |
427 | |
428 | priv->txcoalescing = DEFAULT_TX_COALESCE; | |
b46a8454 | 429 | priv->txic = DEFAULT_TXIC; |
1da177e4 | 430 | priv->rxcoalescing = DEFAULT_RX_COALESCE; |
b46a8454 | 431 | priv->rxic = DEFAULT_RXIC; |
1da177e4 | 432 | |
0bbaf069 KG |
433 | /* Enable most messages by default */ |
434 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
435 | ||
d3eab82b TP |
436 | /* Carrier starts down, phylib will bring it up */ |
437 | netif_carrier_off(dev); | |
438 | ||
1da177e4 LT |
439 | err = register_netdev(dev); |
440 | ||
441 | if (err) { | |
442 | printk(KERN_ERR "%s: Cannot register net device, aborting.\n", | |
443 | dev->name); | |
444 | goto register_fail; | |
445 | } | |
446 | ||
2884e5cc AV |
447 | device_init_wakeup(&dev->dev, |
448 | priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
449 | ||
c50a5d9a DH |
450 | /* fill out IRQ number and name fields */ |
451 | len_devname = strlen(dev->name); | |
452 | strncpy(&priv->int_name_tx[0], dev->name, len_devname); | |
453 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { | |
454 | strncpy(&priv->int_name_tx[len_devname], | |
455 | "_tx", sizeof("_tx") + 1); | |
456 | ||
457 | strncpy(&priv->int_name_rx[0], dev->name, len_devname); | |
458 | strncpy(&priv->int_name_rx[len_devname], | |
459 | "_rx", sizeof("_rx") + 1); | |
460 | ||
461 | strncpy(&priv->int_name_er[0], dev->name, len_devname); | |
462 | strncpy(&priv->int_name_er[len_devname], | |
463 | "_er", sizeof("_er") + 1); | |
464 | } else | |
465 | priv->int_name_tx[len_devname] = '\0'; | |
466 | ||
7f7f5316 AF |
467 | /* Create all the sysfs files */ |
468 | gfar_init_sysfs(dev); | |
469 | ||
1da177e4 | 470 | /* Print out the device info */ |
e174961c | 471 | printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr); |
1da177e4 LT |
472 | |
473 | /* Even more device info helps when determining which kernel */ | |
7f7f5316 | 474 | /* provided which set of benchmarks. */ |
1da177e4 | 475 | printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name); |
1da177e4 LT |
476 | printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n", |
477 | dev->name, priv->rx_ring_size, priv->tx_ring_size); | |
478 | ||
479 | return 0; | |
480 | ||
481 | register_fail: | |
cc8c6e37 | 482 | iounmap(priv->regs); |
1da177e4 | 483 | regs_fail: |
fe192a49 GL |
484 | if (priv->phy_node) |
485 | of_node_put(priv->phy_node); | |
486 | if (priv->tbi_node) | |
487 | of_node_put(priv->tbi_node); | |
1da177e4 | 488 | free_netdev(dev); |
bb40dcbb | 489 | return err; |
1da177e4 LT |
490 | } |
491 | ||
b31a1d8b | 492 | static int gfar_remove(struct of_device *ofdev) |
1da177e4 | 493 | { |
b31a1d8b | 494 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 495 | |
fe192a49 GL |
496 | if (priv->phy_node) |
497 | of_node_put(priv->phy_node); | |
498 | if (priv->tbi_node) | |
499 | of_node_put(priv->tbi_node); | |
500 | ||
b31a1d8b | 501 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 502 | |
cc8c6e37 | 503 | iounmap(priv->regs); |
4826857f | 504 | free_netdev(priv->ndev); |
1da177e4 LT |
505 | |
506 | return 0; | |
507 | } | |
508 | ||
d87eb127 | 509 | #ifdef CONFIG_PM |
b31a1d8b | 510 | static int gfar_suspend(struct of_device *ofdev, pm_message_t state) |
d87eb127 | 511 | { |
b31a1d8b | 512 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
29ded5f7 | 513 | struct net_device *dev = priv->ndev; |
d87eb127 SW |
514 | unsigned long flags; |
515 | u32 tempval; | |
516 | ||
517 | int magic_packet = priv->wol_en && | |
b31a1d8b | 518 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 SW |
519 | |
520 | netif_device_detach(dev); | |
521 | ||
522 | if (netif_running(dev)) { | |
523 | spin_lock_irqsave(&priv->txlock, flags); | |
524 | spin_lock(&priv->rxlock); | |
525 | ||
526 | gfar_halt_nodisable(dev); | |
527 | ||
528 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
529 | tempval = gfar_read(&priv->regs->maccfg1); | |
530 | ||
531 | tempval &= ~MACCFG1_TX_EN; | |
532 | ||
533 | if (!magic_packet) | |
534 | tempval &= ~MACCFG1_RX_EN; | |
535 | ||
536 | gfar_write(&priv->regs->maccfg1, tempval); | |
537 | ||
538 | spin_unlock(&priv->rxlock); | |
539 | spin_unlock_irqrestore(&priv->txlock, flags); | |
540 | ||
d87eb127 | 541 | napi_disable(&priv->napi); |
d87eb127 SW |
542 | |
543 | if (magic_packet) { | |
544 | /* Enable interrupt on Magic Packet */ | |
545 | gfar_write(&priv->regs->imask, IMASK_MAG); | |
546 | ||
547 | /* Enable Magic Packet mode */ | |
548 | tempval = gfar_read(&priv->regs->maccfg2); | |
549 | tempval |= MACCFG2_MPEN; | |
550 | gfar_write(&priv->regs->maccfg2, tempval); | |
551 | } else { | |
552 | phy_stop(priv->phydev); | |
553 | } | |
554 | } | |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
b31a1d8b | 559 | static int gfar_resume(struct of_device *ofdev) |
d87eb127 | 560 | { |
b31a1d8b | 561 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
29ded5f7 | 562 | struct net_device *dev = priv->ndev; |
d87eb127 SW |
563 | unsigned long flags; |
564 | u32 tempval; | |
565 | int magic_packet = priv->wol_en && | |
b31a1d8b | 566 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 SW |
567 | |
568 | if (!netif_running(dev)) { | |
569 | netif_device_attach(dev); | |
570 | return 0; | |
571 | } | |
572 | ||
573 | if (!magic_packet && priv->phydev) | |
574 | phy_start(priv->phydev); | |
575 | ||
576 | /* Disable Magic Packet mode, in case something | |
577 | * else woke us up. | |
578 | */ | |
579 | ||
580 | spin_lock_irqsave(&priv->txlock, flags); | |
581 | spin_lock(&priv->rxlock); | |
582 | ||
583 | tempval = gfar_read(&priv->regs->maccfg2); | |
584 | tempval &= ~MACCFG2_MPEN; | |
585 | gfar_write(&priv->regs->maccfg2, tempval); | |
586 | ||
587 | gfar_start(dev); | |
588 | ||
589 | spin_unlock(&priv->rxlock); | |
590 | spin_unlock_irqrestore(&priv->txlock, flags); | |
591 | ||
592 | netif_device_attach(dev); | |
593 | ||
d87eb127 | 594 | napi_enable(&priv->napi); |
d87eb127 SW |
595 | |
596 | return 0; | |
597 | } | |
598 | #else | |
599 | #define gfar_suspend NULL | |
600 | #define gfar_resume NULL | |
601 | #endif | |
1da177e4 | 602 | |
e8a2b6a4 AF |
603 | /* Reads the controller's registers to determine what interface |
604 | * connects it to the PHY. | |
605 | */ | |
606 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
607 | { | |
608 | struct gfar_private *priv = netdev_priv(dev); | |
609 | u32 ecntrl = gfar_read(&priv->regs->ecntrl); | |
610 | ||
611 | if (ecntrl & ECNTRL_SGMII_MODE) | |
612 | return PHY_INTERFACE_MODE_SGMII; | |
613 | ||
614 | if (ecntrl & ECNTRL_TBI_MODE) { | |
615 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
616 | return PHY_INTERFACE_MODE_RTBI; | |
617 | else | |
618 | return PHY_INTERFACE_MODE_TBI; | |
619 | } | |
620 | ||
621 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
622 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) | |
623 | return PHY_INTERFACE_MODE_RMII; | |
7132ab7f | 624 | else { |
b31a1d8b | 625 | phy_interface_t interface = priv->interface; |
7132ab7f AF |
626 | |
627 | /* | |
628 | * This isn't autodetected right now, so it must | |
629 | * be set by the device tree or platform code. | |
630 | */ | |
631 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
632 | return PHY_INTERFACE_MODE_RGMII_ID; | |
633 | ||
e8a2b6a4 | 634 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 635 | } |
e8a2b6a4 AF |
636 | } |
637 | ||
b31a1d8b | 638 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
639 | return PHY_INTERFACE_MODE_GMII; |
640 | ||
641 | return PHY_INTERFACE_MODE_MII; | |
642 | } | |
643 | ||
644 | ||
bb40dcbb AF |
645 | /* Initializes driver's PHY state, and attaches to the PHY. |
646 | * Returns 0 on success. | |
1da177e4 LT |
647 | */ |
648 | static int init_phy(struct net_device *dev) | |
649 | { | |
650 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 651 | uint gigabit_support = |
b31a1d8b | 652 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb | 653 | SUPPORTED_1000baseT_Full : 0; |
e8a2b6a4 | 654 | phy_interface_t interface; |
1da177e4 LT |
655 | |
656 | priv->oldlink = 0; | |
657 | priv->oldspeed = 0; | |
658 | priv->oldduplex = -1; | |
659 | ||
e8a2b6a4 AF |
660 | interface = gfar_get_interface(dev); |
661 | ||
fe192a49 GL |
662 | if (priv->phy_node) { |
663 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, | |
664 | 0, interface); | |
665 | if (!priv->phydev) { | |
666 | dev_err(&dev->dev, "error: Could not attach to PHY\n"); | |
667 | return -ENODEV; | |
668 | } | |
669 | } | |
1da177e4 | 670 | |
d3c12873 KJ |
671 | if (interface == PHY_INTERFACE_MODE_SGMII) |
672 | gfar_configure_serdes(dev); | |
673 | ||
bb40dcbb | 674 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
675 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
676 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
677 | |
678 | return 0; | |
1da177e4 LT |
679 | } |
680 | ||
d0313587 PG |
681 | /* |
682 | * Initialize TBI PHY interface for communicating with the | |
683 | * SERDES lynx PHY on the chip. We communicate with this PHY | |
684 | * through the MDIO bus on each controller, treating it as a | |
685 | * "normal" PHY at the address found in the TBIPA register. We assume | |
686 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
687 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
688 | * value doesn't matter, as there are no other PHYs on the bus. | |
689 | */ | |
d3c12873 KJ |
690 | static void gfar_configure_serdes(struct net_device *dev) |
691 | { | |
692 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
693 | struct phy_device *tbiphy; |
694 | ||
695 | if (!priv->tbi_node) { | |
696 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
697 | "device tree specify a tbi-handle\n"); | |
698 | return; | |
699 | } | |
c132419e | 700 | |
fe192a49 GL |
701 | tbiphy = of_phy_find_device(priv->tbi_node); |
702 | if (!tbiphy) { | |
703 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
704 | return; |
705 | } | |
d3c12873 | 706 | |
b31a1d8b AF |
707 | /* |
708 | * If the link is already up, we must already be ok, and don't need to | |
bdb59f94 TP |
709 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
710 | * everything for us? Resetting it takes the link down and requires | |
711 | * several seconds for it to come back. | |
712 | */ | |
fe192a49 | 713 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 714 | return; |
d3c12873 | 715 | |
d0313587 | 716 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 717 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 718 | |
fe192a49 | 719 | phy_write(tbiphy, MII_ADVERTISE, |
d3c12873 KJ |
720 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
721 | ADVERTISE_1000XPSE_ASYM); | |
722 | ||
fe192a49 | 723 | phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE | |
d3c12873 KJ |
724 | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000); |
725 | } | |
726 | ||
1da177e4 LT |
727 | static void init_registers(struct net_device *dev) |
728 | { | |
729 | struct gfar_private *priv = netdev_priv(dev); | |
730 | ||
731 | /* Clear IEVENT */ | |
732 | gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR); | |
733 | ||
734 | /* Initialize IMASK */ | |
735 | gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR); | |
736 | ||
737 | /* Init hash registers to zero */ | |
0bbaf069 KG |
738 | gfar_write(&priv->regs->igaddr0, 0); |
739 | gfar_write(&priv->regs->igaddr1, 0); | |
740 | gfar_write(&priv->regs->igaddr2, 0); | |
741 | gfar_write(&priv->regs->igaddr3, 0); | |
742 | gfar_write(&priv->regs->igaddr4, 0); | |
743 | gfar_write(&priv->regs->igaddr5, 0); | |
744 | gfar_write(&priv->regs->igaddr6, 0); | |
745 | gfar_write(&priv->regs->igaddr7, 0); | |
1da177e4 LT |
746 | |
747 | gfar_write(&priv->regs->gaddr0, 0); | |
748 | gfar_write(&priv->regs->gaddr1, 0); | |
749 | gfar_write(&priv->regs->gaddr2, 0); | |
750 | gfar_write(&priv->regs->gaddr3, 0); | |
751 | gfar_write(&priv->regs->gaddr4, 0); | |
752 | gfar_write(&priv->regs->gaddr5, 0); | |
753 | gfar_write(&priv->regs->gaddr6, 0); | |
754 | gfar_write(&priv->regs->gaddr7, 0); | |
755 | ||
1da177e4 | 756 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 757 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
cc8c6e37 | 758 | memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
759 | |
760 | /* Mask off the CAM interrupts */ | |
761 | gfar_write(&priv->regs->rmon.cam1, 0xffffffff); | |
762 | gfar_write(&priv->regs->rmon.cam2, 0xffffffff); | |
763 | } | |
764 | ||
765 | /* Initialize the max receive buffer length */ | |
766 | gfar_write(&priv->regs->mrblr, priv->rx_buffer_size); | |
767 | ||
1da177e4 LT |
768 | /* Initialize the Minimum Frame Length Register */ |
769 | gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS); | |
1da177e4 LT |
770 | } |
771 | ||
0bbaf069 KG |
772 | |
773 | /* Halt the receive and transmit queues */ | |
d87eb127 | 774 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
775 | { |
776 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 777 | struct gfar __iomem *regs = priv->regs; |
1da177e4 LT |
778 | u32 tempval; |
779 | ||
1da177e4 LT |
780 | /* Mask all interrupts */ |
781 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
782 | ||
783 | /* Clear all interrupts */ | |
784 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
785 | ||
786 | /* Stop the DMA, and wait for it to stop */ | |
787 | tempval = gfar_read(&priv->regs->dmactrl); | |
788 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) | |
789 | != (DMACTRL_GRS | DMACTRL_GTS)) { | |
790 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); | |
791 | gfar_write(&priv->regs->dmactrl, tempval); | |
792 | ||
793 | while (!(gfar_read(&priv->regs->ievent) & | |
794 | (IEVENT_GRSC | IEVENT_GTSC))) | |
795 | cpu_relax(); | |
796 | } | |
d87eb127 | 797 | } |
d87eb127 SW |
798 | |
799 | /* Halt the receive and transmit queues */ | |
800 | void gfar_halt(struct net_device *dev) | |
801 | { | |
802 | struct gfar_private *priv = netdev_priv(dev); | |
803 | struct gfar __iomem *regs = priv->regs; | |
804 | u32 tempval; | |
1da177e4 | 805 | |
2a54adc3 SW |
806 | gfar_halt_nodisable(dev); |
807 | ||
1da177e4 LT |
808 | /* Disable Rx and Tx */ |
809 | tempval = gfar_read(®s->maccfg1); | |
810 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
811 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
812 | } |
813 | ||
814 | void stop_gfar(struct net_device *dev) | |
815 | { | |
816 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 817 | struct gfar __iomem *regs = priv->regs; |
0bbaf069 KG |
818 | unsigned long flags; |
819 | ||
bb40dcbb AF |
820 | phy_stop(priv->phydev); |
821 | ||
0bbaf069 | 822 | /* Lock it down */ |
fef6108d AF |
823 | spin_lock_irqsave(&priv->txlock, flags); |
824 | spin_lock(&priv->rxlock); | |
0bbaf069 | 825 | |
0bbaf069 | 826 | gfar_halt(dev); |
1da177e4 | 827 | |
fef6108d AF |
828 | spin_unlock(&priv->rxlock); |
829 | spin_unlock_irqrestore(&priv->txlock, flags); | |
1da177e4 LT |
830 | |
831 | /* Free the IRQs */ | |
b31a1d8b | 832 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
1da177e4 LT |
833 | free_irq(priv->interruptError, dev); |
834 | free_irq(priv->interruptTransmit, dev); | |
835 | free_irq(priv->interruptReceive, dev); | |
836 | } else { | |
1577ecef | 837 | free_irq(priv->interruptTransmit, dev); |
1da177e4 LT |
838 | } |
839 | ||
840 | free_skb_resources(priv); | |
841 | ||
4826857f | 842 | dma_free_coherent(&priv->ofdev->dev, |
1da177e4 LT |
843 | sizeof(struct txbd8)*priv->tx_ring_size |
844 | + sizeof(struct rxbd8)*priv->rx_ring_size, | |
845 | priv->tx_bd_base, | |
0bbaf069 | 846 | gfar_read(®s->tbase0)); |
1da177e4 LT |
847 | } |
848 | ||
849 | /* If there are any tx skbs or rx skbs still around, free them. | |
850 | * Then free tx_skbuff and rx_skbuff */ | |
bb40dcbb | 851 | static void free_skb_resources(struct gfar_private *priv) |
1da177e4 LT |
852 | { |
853 | struct rxbd8 *rxbdp; | |
854 | struct txbd8 *txbdp; | |
4669bc90 | 855 | int i, j; |
1da177e4 LT |
856 | |
857 | /* Go through all the buffer descriptors and free their data buffers */ | |
858 | txbdp = priv->tx_bd_base; | |
859 | ||
860 | for (i = 0; i < priv->tx_ring_size; i++) { | |
4669bc90 DH |
861 | if (!priv->tx_skbuff[i]) |
862 | continue; | |
1da177e4 | 863 | |
4826857f | 864 | dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 DH |
865 | txbdp->length, DMA_TO_DEVICE); |
866 | txbdp->lstatus = 0; | |
867 | for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) { | |
868 | txbdp++; | |
4826857f | 869 | dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 | 870 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 871 | } |
ad5da7ab | 872 | txbdp++; |
4669bc90 DH |
873 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
874 | priv->tx_skbuff[i] = NULL; | |
1da177e4 LT |
875 | } |
876 | ||
877 | kfree(priv->tx_skbuff); | |
878 | ||
879 | rxbdp = priv->rx_bd_base; | |
880 | ||
881 | /* rx_skbuff is not guaranteed to be allocated, so only | |
882 | * free it and its contents if it is allocated */ | |
883 | if(priv->rx_skbuff != NULL) { | |
884 | for (i = 0; i < priv->rx_ring_size; i++) { | |
885 | if (priv->rx_skbuff[i]) { | |
4826857f | 886 | dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr, |
7f7f5316 | 887 | priv->rx_buffer_size, |
1da177e4 LT |
888 | DMA_FROM_DEVICE); |
889 | ||
890 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
891 | priv->rx_skbuff[i] = NULL; | |
892 | } | |
893 | ||
5a5efed4 | 894 | rxbdp->lstatus = 0; |
1da177e4 LT |
895 | rxbdp->bufPtr = 0; |
896 | ||
897 | rxbdp++; | |
898 | } | |
899 | ||
900 | kfree(priv->rx_skbuff); | |
901 | } | |
902 | } | |
903 | ||
0bbaf069 KG |
904 | void gfar_start(struct net_device *dev) |
905 | { | |
906 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 907 | struct gfar __iomem *regs = priv->regs; |
0bbaf069 KG |
908 | u32 tempval; |
909 | ||
910 | /* Enable Rx and Tx in MACCFG1 */ | |
911 | tempval = gfar_read(®s->maccfg1); | |
912 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
913 | gfar_write(®s->maccfg1, tempval); | |
914 | ||
915 | /* Initialize DMACTRL to have WWR and WOP */ | |
916 | tempval = gfar_read(&priv->regs->dmactrl); | |
917 | tempval |= DMACTRL_INIT_SETTINGS; | |
918 | gfar_write(&priv->regs->dmactrl, tempval); | |
919 | ||
0bbaf069 KG |
920 | /* Make sure we aren't stopped */ |
921 | tempval = gfar_read(&priv->regs->dmactrl); | |
922 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); | |
923 | gfar_write(&priv->regs->dmactrl, tempval); | |
924 | ||
fef6108d AF |
925 | /* Clear THLT/RHLT, so that the DMA starts polling now */ |
926 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT); | |
927 | gfar_write(®s->rstat, RSTAT_CLEAR_RHALT); | |
928 | ||
0bbaf069 KG |
929 | /* Unmask the interrupts we look for */ |
930 | gfar_write(®s->imask, IMASK_DEFAULT); | |
12dea57b DH |
931 | |
932 | dev->trans_start = jiffies; | |
0bbaf069 KG |
933 | } |
934 | ||
1da177e4 LT |
935 | /* Bring the controller up and running */ |
936 | int startup_gfar(struct net_device *dev) | |
937 | { | |
938 | struct txbd8 *txbdp; | |
939 | struct rxbd8 *rxbdp; | |
f9663aea | 940 | dma_addr_t addr = 0; |
1da177e4 LT |
941 | unsigned long vaddr; |
942 | int i; | |
943 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 944 | struct gfar __iomem *regs = priv->regs; |
1da177e4 | 945 | int err = 0; |
0bbaf069 | 946 | u32 rctrl = 0; |
7f7f5316 | 947 | u32 attrs = 0; |
1da177e4 LT |
948 | |
949 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
950 | ||
951 | /* Allocate memory for the buffer descriptors */ | |
4826857f | 952 | vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev, |
1da177e4 LT |
953 | sizeof (struct txbd8) * priv->tx_ring_size + |
954 | sizeof (struct rxbd8) * priv->rx_ring_size, | |
955 | &addr, GFP_KERNEL); | |
956 | ||
957 | if (vaddr == 0) { | |
0bbaf069 KG |
958 | if (netif_msg_ifup(priv)) |
959 | printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n", | |
960 | dev->name); | |
1da177e4 LT |
961 | return -ENOMEM; |
962 | } | |
963 | ||
964 | priv->tx_bd_base = (struct txbd8 *) vaddr; | |
965 | ||
966 | /* enet DMA only understands physical addresses */ | |
0bbaf069 | 967 | gfar_write(®s->tbase0, addr); |
1da177e4 LT |
968 | |
969 | /* Start the rx descriptor ring where the tx ring leaves off */ | |
970 | addr = addr + sizeof (struct txbd8) * priv->tx_ring_size; | |
971 | vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size; | |
972 | priv->rx_bd_base = (struct rxbd8 *) vaddr; | |
0bbaf069 | 973 | gfar_write(®s->rbase0, addr); |
1da177e4 LT |
974 | |
975 | /* Setup the skbuff rings */ | |
976 | priv->tx_skbuff = | |
977 | (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) * | |
978 | priv->tx_ring_size, GFP_KERNEL); | |
979 | ||
bb40dcbb | 980 | if (NULL == priv->tx_skbuff) { |
0bbaf069 KG |
981 | if (netif_msg_ifup(priv)) |
982 | printk(KERN_ERR "%s: Could not allocate tx_skbuff\n", | |
983 | dev->name); | |
1da177e4 LT |
984 | err = -ENOMEM; |
985 | goto tx_skb_fail; | |
986 | } | |
987 | ||
988 | for (i = 0; i < priv->tx_ring_size; i++) | |
989 | priv->tx_skbuff[i] = NULL; | |
990 | ||
991 | priv->rx_skbuff = | |
992 | (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) * | |
993 | priv->rx_ring_size, GFP_KERNEL); | |
994 | ||
bb40dcbb | 995 | if (NULL == priv->rx_skbuff) { |
0bbaf069 KG |
996 | if (netif_msg_ifup(priv)) |
997 | printk(KERN_ERR "%s: Could not allocate rx_skbuff\n", | |
998 | dev->name); | |
1da177e4 LT |
999 | err = -ENOMEM; |
1000 | goto rx_skb_fail; | |
1001 | } | |
1002 | ||
1003 | for (i = 0; i < priv->rx_ring_size; i++) | |
1004 | priv->rx_skbuff[i] = NULL; | |
1005 | ||
1006 | /* Initialize some variables in our dev structure */ | |
4669bc90 | 1007 | priv->num_txbdfree = priv->tx_ring_size; |
1da177e4 LT |
1008 | priv->dirty_tx = priv->cur_tx = priv->tx_bd_base; |
1009 | priv->cur_rx = priv->rx_bd_base; | |
1010 | priv->skb_curtx = priv->skb_dirtytx = 0; | |
1011 | priv->skb_currx = 0; | |
1012 | ||
1013 | /* Initialize Transmit Descriptor Ring */ | |
1014 | txbdp = priv->tx_bd_base; | |
1015 | for (i = 0; i < priv->tx_ring_size; i++) { | |
5a5efed4 | 1016 | txbdp->lstatus = 0; |
1da177e4 LT |
1017 | txbdp->bufPtr = 0; |
1018 | txbdp++; | |
1019 | } | |
1020 | ||
1021 | /* Set the last descriptor in the ring to indicate wrap */ | |
1022 | txbdp--; | |
1023 | txbdp->status |= TXBD_WRAP; | |
1024 | ||
1025 | rxbdp = priv->rx_bd_base; | |
1026 | for (i = 0; i < priv->rx_ring_size; i++) { | |
815b97c6 | 1027 | struct sk_buff *skb; |
1da177e4 | 1028 | |
815b97c6 | 1029 | skb = gfar_new_skb(dev); |
1da177e4 | 1030 | |
815b97c6 AF |
1031 | if (!skb) { |
1032 | printk(KERN_ERR "%s: Can't allocate RX buffers\n", | |
1033 | dev->name); | |
1034 | ||
1035 | goto err_rxalloc_fail; | |
1036 | } | |
1da177e4 LT |
1037 | |
1038 | priv->rx_skbuff[i] = skb; | |
1039 | ||
815b97c6 AF |
1040 | gfar_new_rxbdp(dev, rxbdp, skb); |
1041 | ||
1da177e4 LT |
1042 | rxbdp++; |
1043 | } | |
1044 | ||
1045 | /* Set the last descriptor in the ring to wrap */ | |
1046 | rxbdp--; | |
1047 | rxbdp->status |= RXBD_WRAP; | |
1048 | ||
1049 | /* If the device has multiple interrupts, register for | |
1050 | * them. Otherwise, only register for the one */ | |
b31a1d8b | 1051 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1052 | /* Install our interrupt handlers for Error, |
1da177e4 LT |
1053 | * Transmit, and Receive */ |
1054 | if (request_irq(priv->interruptError, gfar_error, | |
c50a5d9a | 1055 | 0, priv->int_name_er, dev) < 0) { |
0bbaf069 KG |
1056 | if (netif_msg_intr(priv)) |
1057 | printk(KERN_ERR "%s: Can't get IRQ %d\n", | |
1058 | dev->name, priv->interruptError); | |
1da177e4 LT |
1059 | |
1060 | err = -1; | |
1061 | goto err_irq_fail; | |
1062 | } | |
1063 | ||
1064 | if (request_irq(priv->interruptTransmit, gfar_transmit, | |
c50a5d9a | 1065 | 0, priv->int_name_tx, dev) < 0) { |
0bbaf069 KG |
1066 | if (netif_msg_intr(priv)) |
1067 | printk(KERN_ERR "%s: Can't get IRQ %d\n", | |
1068 | dev->name, priv->interruptTransmit); | |
1da177e4 LT |
1069 | |
1070 | err = -1; | |
1071 | ||
1072 | goto tx_irq_fail; | |
1073 | } | |
1074 | ||
1075 | if (request_irq(priv->interruptReceive, gfar_receive, | |
c50a5d9a | 1076 | 0, priv->int_name_rx, dev) < 0) { |
0bbaf069 KG |
1077 | if (netif_msg_intr(priv)) |
1078 | printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n", | |
1079 | dev->name, priv->interruptReceive); | |
1da177e4 LT |
1080 | |
1081 | err = -1; | |
1082 | goto rx_irq_fail; | |
1083 | } | |
1084 | } else { | |
1085 | if (request_irq(priv->interruptTransmit, gfar_interrupt, | |
c50a5d9a | 1086 | 0, priv->int_name_tx, dev) < 0) { |
0bbaf069 KG |
1087 | if (netif_msg_intr(priv)) |
1088 | printk(KERN_ERR "%s: Can't get IRQ %d\n", | |
c50a5d9a | 1089 | dev->name, priv->interruptTransmit); |
1da177e4 LT |
1090 | |
1091 | err = -1; | |
1092 | goto err_irq_fail; | |
1093 | } | |
1094 | } | |
1095 | ||
bb40dcbb | 1096 | phy_start(priv->phydev); |
1da177e4 LT |
1097 | |
1098 | /* Configure the coalescing support */ | |
b46a8454 | 1099 | gfar_write(®s->txic, 0); |
1da177e4 | 1100 | if (priv->txcoalescing) |
b46a8454 | 1101 | gfar_write(®s->txic, priv->txic); |
1da177e4 | 1102 | |
b46a8454 | 1103 | gfar_write(®s->rxic, 0); |
1da177e4 | 1104 | if (priv->rxcoalescing) |
b46a8454 | 1105 | gfar_write(®s->rxic, priv->rxic); |
1da177e4 | 1106 | |
0bbaf069 KG |
1107 | if (priv->rx_csum_enable) |
1108 | rctrl |= RCTRL_CHECKSUMMING; | |
1da177e4 | 1109 | |
7f7f5316 | 1110 | if (priv->extended_hash) { |
0bbaf069 | 1111 | rctrl |= RCTRL_EXTHASH; |
1da177e4 | 1112 | |
7f7f5316 AF |
1113 | gfar_clear_exact_match(dev); |
1114 | rctrl |= RCTRL_EMEN; | |
1115 | } | |
1116 | ||
7f7f5316 AF |
1117 | if (priv->padding) { |
1118 | rctrl &= ~RCTRL_PAL_MASK; | |
1119 | rctrl |= RCTRL_PADDING(priv->padding); | |
1120 | } | |
1121 | ||
0bbaf069 KG |
1122 | /* Init rctrl based on our settings */ |
1123 | gfar_write(&priv->regs->rctrl, rctrl); | |
1da177e4 | 1124 | |
0bbaf069 KG |
1125 | if (dev->features & NETIF_F_IP_CSUM) |
1126 | gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM); | |
1da177e4 | 1127 | |
7f7f5316 AF |
1128 | /* Set the extraction length and index */ |
1129 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
1130 | ATTRELI_EI(priv->rx_stash_index); | |
1131 | ||
1132 | gfar_write(&priv->regs->attreli, attrs); | |
1133 | ||
1134 | /* Start with defaults, and add stashing or locking | |
1135 | * depending on the approprate variables */ | |
1136 | attrs = ATTR_INIT_SETTINGS; | |
1137 | ||
1138 | if (priv->bd_stash_en) | |
1139 | attrs |= ATTR_BDSTASH; | |
1140 | ||
1141 | if (priv->rx_stash_size != 0) | |
1142 | attrs |= ATTR_BUFSTASH; | |
1143 | ||
1144 | gfar_write(&priv->regs->attr, attrs); | |
1145 | ||
1146 | gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold); | |
1147 | gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve); | |
1148 | gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
1149 | ||
1150 | /* Start the controller */ | |
0bbaf069 | 1151 | gfar_start(dev); |
1da177e4 LT |
1152 | |
1153 | return 0; | |
1154 | ||
1155 | rx_irq_fail: | |
1156 | free_irq(priv->interruptTransmit, dev); | |
1157 | tx_irq_fail: | |
1158 | free_irq(priv->interruptError, dev); | |
1159 | err_irq_fail: | |
7d2e3cb7 | 1160 | err_rxalloc_fail: |
1da177e4 LT |
1161 | rx_skb_fail: |
1162 | free_skb_resources(priv); | |
1163 | tx_skb_fail: | |
4826857f | 1164 | dma_free_coherent(&priv->ofdev->dev, |
1da177e4 LT |
1165 | sizeof(struct txbd8)*priv->tx_ring_size |
1166 | + sizeof(struct rxbd8)*priv->rx_ring_size, | |
1167 | priv->tx_bd_base, | |
0bbaf069 | 1168 | gfar_read(®s->tbase0)); |
1da177e4 | 1169 | |
1da177e4 LT |
1170 | return err; |
1171 | } | |
1172 | ||
1173 | /* Called when something needs to use the ethernet device */ | |
1174 | /* Returns 0 for success. */ | |
1175 | static int gfar_enet_open(struct net_device *dev) | |
1176 | { | |
94e8cc35 | 1177 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1178 | int err; |
1179 | ||
bea3348e SH |
1180 | napi_enable(&priv->napi); |
1181 | ||
0fd56bb5 AF |
1182 | skb_queue_head_init(&priv->rx_recycle); |
1183 | ||
1da177e4 LT |
1184 | /* Initialize a bunch of registers */ |
1185 | init_registers(dev); | |
1186 | ||
1187 | gfar_set_mac_address(dev); | |
1188 | ||
1189 | err = init_phy(dev); | |
1190 | ||
bea3348e SH |
1191 | if(err) { |
1192 | napi_disable(&priv->napi); | |
1da177e4 | 1193 | return err; |
bea3348e | 1194 | } |
1da177e4 LT |
1195 | |
1196 | err = startup_gfar(dev); | |
db0e8e3f | 1197 | if (err) { |
bea3348e | 1198 | napi_disable(&priv->napi); |
db0e8e3f AV |
1199 | return err; |
1200 | } | |
1da177e4 LT |
1201 | |
1202 | netif_start_queue(dev); | |
1203 | ||
2884e5cc AV |
1204 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1205 | ||
1da177e4 LT |
1206 | return err; |
1207 | } | |
1208 | ||
54dc79fe | 1209 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 1210 | { |
54dc79fe | 1211 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
1212 | |
1213 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 1214 | |
0bbaf069 KG |
1215 | return fcb; |
1216 | } | |
1217 | ||
1218 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb) | |
1219 | { | |
7f7f5316 | 1220 | u8 flags = 0; |
0bbaf069 KG |
1221 | |
1222 | /* If we're here, it's a IP packet with a TCP or UDP | |
1223 | * payload. We set it to checksum, using a pseudo-header | |
1224 | * we provide | |
1225 | */ | |
7f7f5316 | 1226 | flags = TXFCB_DEFAULT; |
0bbaf069 | 1227 | |
7f7f5316 AF |
1228 | /* Tell the controller what the protocol is */ |
1229 | /* And provide the already calculated phcs */ | |
eddc9ec5 | 1230 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 1231 | flags |= TXFCB_UDP; |
4bedb452 | 1232 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 1233 | } else |
8da32de5 | 1234 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
1235 | |
1236 | /* l3os is the distance between the start of the | |
1237 | * frame (skb->data) and the start of the IP hdr. | |
1238 | * l4os is the distance between the start of the | |
1239 | * l3 hdr and the l4 hdr */ | |
bbe735e4 | 1240 | fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN); |
cfe1fc77 | 1241 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 1242 | |
7f7f5316 | 1243 | fcb->flags = flags; |
0bbaf069 KG |
1244 | } |
1245 | ||
7f7f5316 | 1246 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 1247 | { |
7f7f5316 | 1248 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
1249 | fcb->vlctl = vlan_tx_tag_get(skb); |
1250 | } | |
1251 | ||
4669bc90 DH |
1252 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
1253 | struct txbd8 *base, int ring_size) | |
1254 | { | |
1255 | struct txbd8 *new_bd = bdp + stride; | |
1256 | ||
1257 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
1258 | } | |
1259 | ||
1260 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
1261 | int ring_size) | |
1262 | { | |
1263 | return skip_txbd(bdp, 1, base, ring_size); | |
1264 | } | |
1265 | ||
1da177e4 LT |
1266 | /* This is called by the kernel when a frame is ready for transmission. */ |
1267 | /* It is pointed to by the dev->hard_start_xmit function pointer */ | |
1268 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1269 | { | |
1270 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1271 | struct txfcb *fcb = NULL; |
4669bc90 | 1272 | struct txbd8 *txbdp, *txbdp_start, *base; |
5a5efed4 | 1273 | u32 lstatus; |
4669bc90 DH |
1274 | int i; |
1275 | u32 bufaddr; | |
fef6108d | 1276 | unsigned long flags; |
4669bc90 DH |
1277 | unsigned int nr_frags, length; |
1278 | ||
1279 | base = priv->tx_bd_base; | |
1280 | ||
5b28beaf LY |
1281 | /* make space for additional header when fcb is needed */ |
1282 | if (((skb->ip_summed == CHECKSUM_PARTIAL) || | |
1283 | (priv->vlgrp && vlan_tx_tag_present(skb))) && | |
1284 | (skb_headroom(skb) < GMAC_FCB_LEN)) { | |
54dc79fe SH |
1285 | struct sk_buff *skb_new; |
1286 | ||
1287 | skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN); | |
1288 | if (!skb_new) { | |
1289 | dev->stats.tx_errors++; | |
bd14ba84 | 1290 | kfree_skb(skb); |
54dc79fe SH |
1291 | return NETDEV_TX_OK; |
1292 | } | |
1293 | kfree_skb(skb); | |
1294 | skb = skb_new; | |
1295 | } | |
1296 | ||
4669bc90 DH |
1297 | /* total number of fragments in the SKB */ |
1298 | nr_frags = skb_shinfo(skb)->nr_frags; | |
1299 | ||
1300 | spin_lock_irqsave(&priv->txlock, flags); | |
1301 | ||
1302 | /* check if there is space to queue this packet */ | |
7958a453 | 1303 | if ((nr_frags+1) > priv->num_txbdfree) { |
4669bc90 DH |
1304 | /* no space, stop the queue */ |
1305 | netif_stop_queue(dev); | |
1306 | dev->stats.tx_fifo_errors++; | |
1307 | spin_unlock_irqrestore(&priv->txlock, flags); | |
1308 | return NETDEV_TX_BUSY; | |
1309 | } | |
1da177e4 LT |
1310 | |
1311 | /* Update transmit stats */ | |
09f75cd7 | 1312 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 1313 | |
4669bc90 | 1314 | txbdp = txbdp_start = priv->cur_tx; |
1da177e4 | 1315 | |
4669bc90 DH |
1316 | if (nr_frags == 0) { |
1317 | lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1318 | } else { | |
1319 | /* Place the fragment addresses and lengths into the TxBDs */ | |
1320 | for (i = 0; i < nr_frags; i++) { | |
1321 | /* Point at the next BD, wrapping as needed */ | |
1322 | txbdp = next_txbd(txbdp, base, priv->tx_ring_size); | |
1323 | ||
1324 | length = skb_shinfo(skb)->frags[i].size; | |
1325 | ||
1326 | lstatus = txbdp->lstatus | length | | |
1327 | BD_LFLAG(TXBD_READY); | |
1328 | ||
1329 | /* Handle the last BD specially */ | |
1330 | if (i == nr_frags - 1) | |
1331 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 1332 | |
4826857f | 1333 | bufaddr = dma_map_page(&priv->ofdev->dev, |
4669bc90 DH |
1334 | skb_shinfo(skb)->frags[i].page, |
1335 | skb_shinfo(skb)->frags[i].page_offset, | |
1336 | length, | |
1337 | DMA_TO_DEVICE); | |
1338 | ||
1339 | /* set the TxBD length and buffer pointer */ | |
1340 | txbdp->bufPtr = bufaddr; | |
1341 | txbdp->lstatus = lstatus; | |
1342 | } | |
1343 | ||
1344 | lstatus = txbdp_start->lstatus; | |
1345 | } | |
1da177e4 | 1346 | |
0bbaf069 | 1347 | /* Set up checksumming */ |
12dea57b | 1348 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
54dc79fe SH |
1349 | fcb = gfar_add_fcb(skb); |
1350 | lstatus |= BD_LFLAG(TXBD_TOE); | |
1351 | gfar_tx_checksum(skb, fcb); | |
0bbaf069 KG |
1352 | } |
1353 | ||
77ecaf2d | 1354 | if (priv->vlgrp && vlan_tx_tag_present(skb)) { |
54dc79fe SH |
1355 | if (unlikely(NULL == fcb)) { |
1356 | fcb = gfar_add_fcb(skb); | |
5a5efed4 | 1357 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 1358 | } |
54dc79fe SH |
1359 | |
1360 | gfar_tx_vlan(skb, fcb); | |
0bbaf069 KG |
1361 | } |
1362 | ||
4669bc90 | 1363 | /* setup the TxBD length and buffer pointer for the first BD */ |
1da177e4 | 1364 | priv->tx_skbuff[priv->skb_curtx] = skb; |
4826857f | 1365 | txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
4669bc90 | 1366 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 1367 | |
4669bc90 | 1368 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); |
1da177e4 | 1369 | |
4669bc90 DH |
1370 | /* |
1371 | * The powerpc-specific eieio() is used, as wmb() has too strong | |
3b6330ce SW |
1372 | * semantics (it requires synchronization between cacheable and |
1373 | * uncacheable mappings, which eieio doesn't provide and which we | |
1374 | * don't need), thus requiring a more expensive sync instruction. At | |
1375 | * some point, the set of architecture-independent barrier functions | |
1376 | * should be expanded to include weaker barriers. | |
1377 | */ | |
3b6330ce | 1378 | eieio(); |
7f7f5316 | 1379 | |
4669bc90 DH |
1380 | txbdp_start->lstatus = lstatus; |
1381 | ||
1382 | /* Update the current skb pointer to the next entry we will use | |
1383 | * (wrapping if necessary) */ | |
1384 | priv->skb_curtx = (priv->skb_curtx + 1) & | |
1385 | TX_RING_MOD_MASK(priv->tx_ring_size); | |
1386 | ||
1387 | priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size); | |
1388 | ||
1389 | /* reduce TxBD free count */ | |
1390 | priv->num_txbdfree -= (nr_frags + 1); | |
1391 | ||
1392 | dev->trans_start = jiffies; | |
1da177e4 LT |
1393 | |
1394 | /* If the next BD still needs to be cleaned up, then the bds | |
1395 | are full. We need to tell the kernel to stop sending us stuff. */ | |
4669bc90 | 1396 | if (!priv->num_txbdfree) { |
1da177e4 LT |
1397 | netif_stop_queue(dev); |
1398 | ||
09f75cd7 | 1399 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
1400 | } |
1401 | ||
1da177e4 LT |
1402 | /* Tell the DMA to go go go */ |
1403 | gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT); | |
1404 | ||
1405 | /* Unlock priv */ | |
fef6108d | 1406 | spin_unlock_irqrestore(&priv->txlock, flags); |
1da177e4 | 1407 | |
54dc79fe | 1408 | return NETDEV_TX_OK; |
1da177e4 LT |
1409 | } |
1410 | ||
1411 | /* Stops the kernel queue, and halts the controller */ | |
1412 | static int gfar_close(struct net_device *dev) | |
1413 | { | |
1414 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e SH |
1415 | |
1416 | napi_disable(&priv->napi); | |
1417 | ||
0fd56bb5 | 1418 | skb_queue_purge(&priv->rx_recycle); |
ab939905 | 1419 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
1420 | stop_gfar(dev); |
1421 | ||
bb40dcbb AF |
1422 | /* Disconnect from the PHY */ |
1423 | phy_disconnect(priv->phydev); | |
1424 | priv->phydev = NULL; | |
1da177e4 LT |
1425 | |
1426 | netif_stop_queue(dev); | |
1427 | ||
1428 | return 0; | |
1429 | } | |
1430 | ||
1da177e4 | 1431 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 1432 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 1433 | { |
7f7f5316 | 1434 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
1435 | |
1436 | return 0; | |
1437 | } | |
1438 | ||
1439 | ||
0bbaf069 KG |
1440 | /* Enables and disables VLAN insertion/extraction */ |
1441 | static void gfar_vlan_rx_register(struct net_device *dev, | |
1442 | struct vlan_group *grp) | |
1443 | { | |
1444 | struct gfar_private *priv = netdev_priv(dev); | |
1445 | unsigned long flags; | |
1446 | u32 tempval; | |
1447 | ||
fef6108d | 1448 | spin_lock_irqsave(&priv->rxlock, flags); |
0bbaf069 | 1449 | |
cd1f55a5 | 1450 | priv->vlgrp = grp; |
0bbaf069 KG |
1451 | |
1452 | if (grp) { | |
1453 | /* Enable VLAN tag insertion */ | |
1454 | tempval = gfar_read(&priv->regs->tctrl); | |
1455 | tempval |= TCTRL_VLINS; | |
1456 | ||
1457 | gfar_write(&priv->regs->tctrl, tempval); | |
6aa20a22 | 1458 | |
0bbaf069 KG |
1459 | /* Enable VLAN tag extraction */ |
1460 | tempval = gfar_read(&priv->regs->rctrl); | |
1461 | tempval |= RCTRL_VLEX; | |
77ecaf2d | 1462 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); |
0bbaf069 KG |
1463 | gfar_write(&priv->regs->rctrl, tempval); |
1464 | } else { | |
1465 | /* Disable VLAN tag insertion */ | |
1466 | tempval = gfar_read(&priv->regs->tctrl); | |
1467 | tempval &= ~TCTRL_VLINS; | |
1468 | gfar_write(&priv->regs->tctrl, tempval); | |
1469 | ||
1470 | /* Disable VLAN tag extraction */ | |
1471 | tempval = gfar_read(&priv->regs->rctrl); | |
1472 | tempval &= ~RCTRL_VLEX; | |
77ecaf2d DH |
1473 | /* If parse is no longer required, then disable parser */ |
1474 | if (tempval & RCTRL_REQ_PARSER) | |
1475 | tempval |= RCTRL_PRSDEP_INIT; | |
1476 | else | |
1477 | tempval &= ~RCTRL_PRSDEP_INIT; | |
0bbaf069 KG |
1478 | gfar_write(&priv->regs->rctrl, tempval); |
1479 | } | |
1480 | ||
77ecaf2d DH |
1481 | gfar_change_mtu(dev, dev->mtu); |
1482 | ||
fef6108d | 1483 | spin_unlock_irqrestore(&priv->rxlock, flags); |
0bbaf069 KG |
1484 | } |
1485 | ||
1da177e4 LT |
1486 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
1487 | { | |
1488 | int tempsize, tempval; | |
1489 | struct gfar_private *priv = netdev_priv(dev); | |
1490 | int oldsize = priv->rx_buffer_size; | |
0bbaf069 KG |
1491 | int frame_size = new_mtu + ETH_HLEN; |
1492 | ||
77ecaf2d | 1493 | if (priv->vlgrp) |
faa89577 | 1494 | frame_size += VLAN_HLEN; |
0bbaf069 | 1495 | |
1da177e4 | 1496 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
0bbaf069 KG |
1497 | if (netif_msg_drv(priv)) |
1498 | printk(KERN_ERR "%s: Invalid MTU setting\n", | |
1499 | dev->name); | |
1da177e4 LT |
1500 | return -EINVAL; |
1501 | } | |
1502 | ||
77ecaf2d DH |
1503 | if (gfar_uses_fcb(priv)) |
1504 | frame_size += GMAC_FCB_LEN; | |
1505 | ||
1506 | frame_size += priv->padding; | |
1507 | ||
1da177e4 LT |
1508 | tempsize = |
1509 | (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + | |
1510 | INCREMENTAL_BUFFER_SIZE; | |
1511 | ||
1512 | /* Only stop and start the controller if it isn't already | |
7f7f5316 | 1513 | * stopped, and we changed something */ |
1da177e4 LT |
1514 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
1515 | stop_gfar(dev); | |
1516 | ||
1517 | priv->rx_buffer_size = tempsize; | |
1518 | ||
1519 | dev->mtu = new_mtu; | |
1520 | ||
1521 | gfar_write(&priv->regs->mrblr, priv->rx_buffer_size); | |
1522 | gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size); | |
1523 | ||
1524 | /* If the mtu is larger than the max size for standard | |
1525 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
1526 | * to allow huge frames, and to check the length */ | |
1527 | tempval = gfar_read(&priv->regs->maccfg2); | |
1528 | ||
1529 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE) | |
1530 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
1531 | else | |
1532 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
1533 | ||
1534 | gfar_write(&priv->regs->maccfg2, tempval); | |
1535 | ||
1536 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
1537 | startup_gfar(dev); | |
1538 | ||
1539 | return 0; | |
1540 | } | |
1541 | ||
ab939905 | 1542 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
1543 | * transmitted after a set amount of time. |
1544 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
1545 | * starting over will fix the problem. |
1546 | */ | |
1547 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 1548 | { |
ab939905 SS |
1549 | struct gfar_private *priv = container_of(work, struct gfar_private, |
1550 | reset_task); | |
4826857f | 1551 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
1552 | |
1553 | if (dev->flags & IFF_UP) { | |
cbea2707 | 1554 | netif_stop_queue(dev); |
1da177e4 LT |
1555 | stop_gfar(dev); |
1556 | startup_gfar(dev); | |
cbea2707 | 1557 | netif_start_queue(dev); |
1da177e4 LT |
1558 | } |
1559 | ||
263ba320 | 1560 | netif_tx_schedule_all(dev); |
1da177e4 LT |
1561 | } |
1562 | ||
ab939905 SS |
1563 | static void gfar_timeout(struct net_device *dev) |
1564 | { | |
1565 | struct gfar_private *priv = netdev_priv(dev); | |
1566 | ||
1567 | dev->stats.tx_errors++; | |
1568 | schedule_work(&priv->reset_task); | |
1569 | } | |
1570 | ||
1da177e4 | 1571 | /* Interrupt Handler for Transmit complete */ |
f162b9d5 | 1572 | static int gfar_clean_tx_ring(struct net_device *dev) |
1da177e4 | 1573 | { |
d080cd63 | 1574 | struct gfar_private *priv = netdev_priv(dev); |
4669bc90 DH |
1575 | struct txbd8 *bdp; |
1576 | struct txbd8 *lbdp = NULL; | |
1577 | struct txbd8 *base = priv->tx_bd_base; | |
1578 | struct sk_buff *skb; | |
1579 | int skb_dirtytx; | |
1580 | int tx_ring_size = priv->tx_ring_size; | |
1581 | int frags = 0; | |
1582 | int i; | |
d080cd63 | 1583 | int howmany = 0; |
4669bc90 | 1584 | u32 lstatus; |
1da177e4 | 1585 | |
1da177e4 | 1586 | bdp = priv->dirty_tx; |
4669bc90 | 1587 | skb_dirtytx = priv->skb_dirtytx; |
1da177e4 | 1588 | |
4669bc90 DH |
1589 | while ((skb = priv->tx_skbuff[skb_dirtytx])) { |
1590 | frags = skb_shinfo(skb)->nr_frags; | |
1591 | lbdp = skip_txbd(bdp, frags, base, tx_ring_size); | |
1da177e4 | 1592 | |
4669bc90 | 1593 | lstatus = lbdp->lstatus; |
1da177e4 | 1594 | |
4669bc90 DH |
1595 | /* Only clean completed frames */ |
1596 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
1597 | (lstatus & BD_LENGTH_MASK)) | |
1598 | break; | |
1599 | ||
4826857f | 1600 | dma_unmap_single(&priv->ofdev->dev, |
4669bc90 DH |
1601 | bdp->bufPtr, |
1602 | bdp->length, | |
1603 | DMA_TO_DEVICE); | |
81183059 | 1604 | |
4669bc90 DH |
1605 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
1606 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 1607 | |
4669bc90 | 1608 | for (i = 0; i < frags; i++) { |
4826857f | 1609 | dma_unmap_page(&priv->ofdev->dev, |
4669bc90 DH |
1610 | bdp->bufPtr, |
1611 | bdp->length, | |
1612 | DMA_TO_DEVICE); | |
1613 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
1614 | bdp = next_txbd(bdp, base, tx_ring_size); | |
1615 | } | |
1da177e4 | 1616 | |
0fd56bb5 AF |
1617 | /* |
1618 | * If there's room in the queue (limit it to rx_buffer_size) | |
1619 | * we add this skb back into the pool, if it's the right size | |
1620 | */ | |
1621 | if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size && | |
1622 | skb_recycle_check(skb, priv->rx_buffer_size + | |
1623 | RXBUF_ALIGNMENT)) | |
1624 | __skb_queue_head(&priv->rx_recycle, skb); | |
1625 | else | |
1626 | dev_kfree_skb_any(skb); | |
1627 | ||
4669bc90 | 1628 | priv->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 1629 | |
4669bc90 DH |
1630 | skb_dirtytx = (skb_dirtytx + 1) & |
1631 | TX_RING_MOD_MASK(tx_ring_size); | |
1632 | ||
1633 | howmany++; | |
1634 | priv->num_txbdfree += frags + 1; | |
1635 | } | |
1da177e4 | 1636 | |
4669bc90 DH |
1637 | /* If we freed a buffer, we can restart transmission, if necessary */ |
1638 | if (netif_queue_stopped(dev) && priv->num_txbdfree) | |
1639 | netif_wake_queue(dev); | |
1da177e4 | 1640 | |
4669bc90 DH |
1641 | /* Update dirty indicators */ |
1642 | priv->skb_dirtytx = skb_dirtytx; | |
1643 | priv->dirty_tx = bdp; | |
1da177e4 | 1644 | |
d080cd63 DH |
1645 | dev->stats.tx_packets += howmany; |
1646 | ||
1647 | return howmany; | |
1648 | } | |
1649 | ||
8c7396ae | 1650 | static void gfar_schedule_cleanup(struct net_device *dev) |
d080cd63 | 1651 | { |
d080cd63 | 1652 | struct gfar_private *priv = netdev_priv(dev); |
a6d0b91a AV |
1653 | unsigned long flags; |
1654 | ||
1655 | spin_lock_irqsave(&priv->txlock, flags); | |
1656 | spin_lock(&priv->rxlock); | |
1657 | ||
288379f0 | 1658 | if (napi_schedule_prep(&priv->napi)) { |
8c7396ae | 1659 | gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED); |
288379f0 | 1660 | __napi_schedule(&priv->napi); |
8707bdd4 JP |
1661 | } else { |
1662 | /* | |
1663 | * Clear IEVENT, so interrupts aren't called again | |
1664 | * because of the packets that have already arrived. | |
1665 | */ | |
1666 | gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK); | |
2f448911 | 1667 | } |
a6d0b91a AV |
1668 | |
1669 | spin_unlock(&priv->rxlock); | |
1670 | spin_unlock_irqrestore(&priv->txlock, flags); | |
8c7396ae | 1671 | } |
1da177e4 | 1672 | |
8c7396ae DH |
1673 | /* Interrupt Handler for Transmit complete */ |
1674 | static irqreturn_t gfar_transmit(int irq, void *dev_id) | |
1675 | { | |
1676 | gfar_schedule_cleanup((struct net_device *)dev_id); | |
1da177e4 LT |
1677 | return IRQ_HANDLED; |
1678 | } | |
1679 | ||
815b97c6 AF |
1680 | static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp, |
1681 | struct sk_buff *skb) | |
1682 | { | |
1683 | struct gfar_private *priv = netdev_priv(dev); | |
5a5efed4 | 1684 | u32 lstatus; |
815b97c6 | 1685 | |
4826857f | 1686 | bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
815b97c6 AF |
1687 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
1688 | ||
5a5efed4 | 1689 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); |
815b97c6 AF |
1690 | |
1691 | if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1) | |
5a5efed4 | 1692 | lstatus |= BD_LFLAG(RXBD_WRAP); |
815b97c6 AF |
1693 | |
1694 | eieio(); | |
1695 | ||
5a5efed4 | 1696 | bdp->lstatus = lstatus; |
815b97c6 AF |
1697 | } |
1698 | ||
1699 | ||
1700 | struct sk_buff * gfar_new_skb(struct net_device *dev) | |
1da177e4 | 1701 | { |
7f7f5316 | 1702 | unsigned int alignamount; |
1da177e4 LT |
1703 | struct gfar_private *priv = netdev_priv(dev); |
1704 | struct sk_buff *skb = NULL; | |
1da177e4 | 1705 | |
0fd56bb5 AF |
1706 | skb = __skb_dequeue(&priv->rx_recycle); |
1707 | if (!skb) | |
1708 | skb = netdev_alloc_skb(dev, | |
1709 | priv->rx_buffer_size + RXBUF_ALIGNMENT); | |
1da177e4 | 1710 | |
815b97c6 | 1711 | if (!skb) |
1da177e4 LT |
1712 | return NULL; |
1713 | ||
7f7f5316 | 1714 | alignamount = RXBUF_ALIGNMENT - |
bea3348e | 1715 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)); |
7f7f5316 | 1716 | |
1da177e4 LT |
1717 | /* We need the data buffer to be aligned properly. We will reserve |
1718 | * as many bytes as needed to align the data properly | |
1719 | */ | |
7f7f5316 | 1720 | skb_reserve(skb, alignamount); |
1da177e4 | 1721 | |
1da177e4 LT |
1722 | return skb; |
1723 | } | |
1724 | ||
298e1a9e | 1725 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 1726 | { |
298e1a9e | 1727 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 1728 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
1729 | struct gfar_extra_stats *estats = &priv->extra_stats; |
1730 | ||
1731 | /* If the packet was truncated, none of the other errors | |
1732 | * matter */ | |
1733 | if (status & RXBD_TRUNCATED) { | |
1734 | stats->rx_length_errors++; | |
1735 | ||
1736 | estats->rx_trunc++; | |
1737 | ||
1738 | return; | |
1739 | } | |
1740 | /* Count the errors, if there were any */ | |
1741 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
1742 | stats->rx_length_errors++; | |
1743 | ||
1744 | if (status & RXBD_LARGE) | |
1745 | estats->rx_large++; | |
1746 | else | |
1747 | estats->rx_short++; | |
1748 | } | |
1749 | if (status & RXBD_NONOCTET) { | |
1750 | stats->rx_frame_errors++; | |
1751 | estats->rx_nonoctet++; | |
1752 | } | |
1753 | if (status & RXBD_CRCERR) { | |
1754 | estats->rx_crcerr++; | |
1755 | stats->rx_crc_errors++; | |
1756 | } | |
1757 | if (status & RXBD_OVERRUN) { | |
1758 | estats->rx_overrun++; | |
1759 | stats->rx_crc_errors++; | |
1760 | } | |
1761 | } | |
1762 | ||
7d12e780 | 1763 | irqreturn_t gfar_receive(int irq, void *dev_id) |
1da177e4 | 1764 | { |
8c7396ae | 1765 | gfar_schedule_cleanup((struct net_device *)dev_id); |
1da177e4 LT |
1766 | return IRQ_HANDLED; |
1767 | } | |
1768 | ||
0bbaf069 KG |
1769 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
1770 | { | |
1771 | /* If valid headers were found, and valid sums | |
1772 | * were verified, then we tell the kernel that no | |
1773 | * checksumming is necessary. Otherwise, it is */ | |
7f7f5316 | 1774 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
1775 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
1776 | else | |
1777 | skb->ip_summed = CHECKSUM_NONE; | |
1778 | } | |
1779 | ||
1780 | ||
1da177e4 LT |
1781 | /* gfar_process_frame() -- handle one incoming packet if skb |
1782 | * isn't NULL. */ | |
1783 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, | |
2c2db48a | 1784 | int amount_pull) |
1da177e4 LT |
1785 | { |
1786 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1787 | struct rxfcb *fcb = NULL; |
1da177e4 | 1788 | |
2c2db48a | 1789 | int ret; |
1da177e4 | 1790 | |
2c2db48a DH |
1791 | /* fcb is at the beginning if exists */ |
1792 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 1793 | |
2c2db48a DH |
1794 | /* Remove the FCB from the skb */ |
1795 | /* Remove the padded bytes, if there are any */ | |
1796 | if (amount_pull) | |
1797 | skb_pull(skb, amount_pull); | |
0bbaf069 | 1798 | |
2c2db48a DH |
1799 | if (priv->rx_csum_enable) |
1800 | gfar_rx_checksum(skb, fcb); | |
0bbaf069 | 1801 | |
2c2db48a DH |
1802 | /* Tell the skb what kind of packet this is */ |
1803 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 1804 | |
2c2db48a DH |
1805 | /* Send the packet up the stack */ |
1806 | if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) | |
1807 | ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl); | |
1808 | else | |
1809 | ret = netif_receive_skb(skb); | |
0bbaf069 | 1810 | |
2c2db48a DH |
1811 | if (NET_RX_DROP == ret) |
1812 | priv->extra_stats.kernel_dropped++; | |
1da177e4 LT |
1813 | |
1814 | return 0; | |
1815 | } | |
1816 | ||
1817 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
0bbaf069 | 1818 | * until the budget/quota has been reached. Returns the number |
1da177e4 LT |
1819 | * of frames handled |
1820 | */ | |
0bbaf069 | 1821 | int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit) |
1da177e4 | 1822 | { |
31de198b | 1823 | struct rxbd8 *bdp, *base; |
1da177e4 | 1824 | struct sk_buff *skb; |
2c2db48a DH |
1825 | int pkt_len; |
1826 | int amount_pull; | |
1da177e4 LT |
1827 | int howmany = 0; |
1828 | struct gfar_private *priv = netdev_priv(dev); | |
1829 | ||
1830 | /* Get the first full descriptor */ | |
1831 | bdp = priv->cur_rx; | |
31de198b | 1832 | base = priv->rx_bd_base; |
1da177e4 | 1833 | |
2c2db48a DH |
1834 | amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) + |
1835 | priv->padding; | |
1836 | ||
1da177e4 | 1837 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 1838 | struct sk_buff *newskb; |
3b6330ce | 1839 | rmb(); |
815b97c6 AF |
1840 | |
1841 | /* Add another skb for the future */ | |
1842 | newskb = gfar_new_skb(dev); | |
1843 | ||
1da177e4 LT |
1844 | skb = priv->rx_skbuff[priv->skb_currx]; |
1845 | ||
4826857f | 1846 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, |
81183059 AF |
1847 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
1848 | ||
815b97c6 AF |
1849 | /* We drop the frame if we failed to allocate a new buffer */ |
1850 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
1851 | bdp->status & RXBD_ERR)) { | |
1852 | count_errors(bdp->status, dev); | |
1853 | ||
1854 | if (unlikely(!newskb)) | |
1855 | newskb = skb; | |
4e2fd555 LB |
1856 | else if (skb) { |
1857 | /* | |
1858 | * We need to reset ->data to what it | |
1859 | * was before gfar_new_skb() re-aligned | |
1860 | * it to an RXBUF_ALIGNMENT boundary | |
1861 | * before we put the skb back on the | |
1862 | * recycle list. | |
1863 | */ | |
1864 | skb->data = skb->head + NET_SKB_PAD; | |
0fd56bb5 | 1865 | __skb_queue_head(&priv->rx_recycle, skb); |
4e2fd555 | 1866 | } |
815b97c6 | 1867 | } else { |
1da177e4 | 1868 | /* Increment the number of packets */ |
09f75cd7 | 1869 | dev->stats.rx_packets++; |
1da177e4 LT |
1870 | howmany++; |
1871 | ||
2c2db48a DH |
1872 | if (likely(skb)) { |
1873 | pkt_len = bdp->length - ETH_FCS_LEN; | |
1874 | /* Remove the FCS from the packet length */ | |
1875 | skb_put(skb, pkt_len); | |
1876 | dev->stats.rx_bytes += pkt_len; | |
1da177e4 | 1877 | |
1577ecef AF |
1878 | if (in_irq() || irqs_disabled()) |
1879 | printk("Interrupt problem!\n"); | |
2c2db48a DH |
1880 | gfar_process_frame(dev, skb, amount_pull); |
1881 | ||
1882 | } else { | |
1883 | if (netif_msg_rx_err(priv)) | |
1884 | printk(KERN_WARNING | |
1885 | "%s: Missing skb!\n", dev->name); | |
1886 | dev->stats.rx_dropped++; | |
1887 | priv->extra_stats.rx_skbmissing++; | |
1888 | } | |
1da177e4 | 1889 | |
1da177e4 LT |
1890 | } |
1891 | ||
815b97c6 | 1892 | priv->rx_skbuff[priv->skb_currx] = newskb; |
1da177e4 | 1893 | |
815b97c6 AF |
1894 | /* Setup the new bdp */ |
1895 | gfar_new_rxbdp(dev, bdp, newskb); | |
1da177e4 LT |
1896 | |
1897 | /* Update to the next pointer */ | |
31de198b | 1898 | bdp = next_bd(bdp, base, priv->rx_ring_size); |
1da177e4 LT |
1899 | |
1900 | /* update to point at the next skb */ | |
1901 | priv->skb_currx = | |
815b97c6 AF |
1902 | (priv->skb_currx + 1) & |
1903 | RX_RING_MOD_MASK(priv->rx_ring_size); | |
1da177e4 LT |
1904 | } |
1905 | ||
1906 | /* Update the current rxbd pointer to be the next one */ | |
1907 | priv->cur_rx = bdp; | |
1908 | ||
1da177e4 LT |
1909 | return howmany; |
1910 | } | |
1911 | ||
bea3348e | 1912 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 1913 | { |
bea3348e | 1914 | struct gfar_private *priv = container_of(napi, struct gfar_private, napi); |
4826857f | 1915 | struct net_device *dev = priv->ndev; |
42199884 AF |
1916 | int tx_cleaned = 0; |
1917 | int rx_cleaned = 0; | |
d080cd63 DH |
1918 | unsigned long flags; |
1919 | ||
8c7396ae DH |
1920 | /* Clear IEVENT, so interrupts aren't called again |
1921 | * because of the packets that have already arrived */ | |
1922 | gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK); | |
1923 | ||
d080cd63 DH |
1924 | /* If we fail to get the lock, don't bother with the TX BDs */ |
1925 | if (spin_trylock_irqsave(&priv->txlock, flags)) { | |
42199884 | 1926 | tx_cleaned = gfar_clean_tx_ring(dev); |
d080cd63 DH |
1927 | spin_unlock_irqrestore(&priv->txlock, flags); |
1928 | } | |
1da177e4 | 1929 | |
42199884 | 1930 | rx_cleaned = gfar_clean_rx_ring(dev, budget); |
1da177e4 | 1931 | |
42199884 AF |
1932 | if (tx_cleaned) |
1933 | return budget; | |
1934 | ||
1935 | if (rx_cleaned < budget) { | |
288379f0 | 1936 | napi_complete(napi); |
1da177e4 LT |
1937 | |
1938 | /* Clear the halt bit in RSTAT */ | |
1939 | gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT); | |
1940 | ||
1941 | gfar_write(&priv->regs->imask, IMASK_DEFAULT); | |
1942 | ||
1943 | /* If we are coalescing interrupts, update the timer */ | |
1944 | /* Otherwise, clear it */ | |
2f448911 AF |
1945 | if (likely(priv->rxcoalescing)) { |
1946 | gfar_write(&priv->regs->rxic, 0); | |
b46a8454 | 1947 | gfar_write(&priv->regs->rxic, priv->rxic); |
2f448911 | 1948 | } |
8c7396ae DH |
1949 | if (likely(priv->txcoalescing)) { |
1950 | gfar_write(&priv->regs->txic, 0); | |
1951 | gfar_write(&priv->regs->txic, priv->txic); | |
1952 | } | |
1da177e4 LT |
1953 | } |
1954 | ||
42199884 | 1955 | return rx_cleaned; |
1da177e4 | 1956 | } |
1da177e4 | 1957 | |
f2d71c2d VW |
1958 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1959 | /* | |
1960 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1961 | * without having to re-enable interrupts. It's not called while | |
1962 | * the interrupt routine is executing. | |
1963 | */ | |
1964 | static void gfar_netpoll(struct net_device *dev) | |
1965 | { | |
1966 | struct gfar_private *priv = netdev_priv(dev); | |
1967 | ||
1968 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 1969 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
f2d71c2d VW |
1970 | disable_irq(priv->interruptTransmit); |
1971 | disable_irq(priv->interruptReceive); | |
1972 | disable_irq(priv->interruptError); | |
1973 | gfar_interrupt(priv->interruptTransmit, dev); | |
1974 | enable_irq(priv->interruptError); | |
1975 | enable_irq(priv->interruptReceive); | |
1976 | enable_irq(priv->interruptTransmit); | |
1977 | } else { | |
1978 | disable_irq(priv->interruptTransmit); | |
1979 | gfar_interrupt(priv->interruptTransmit, dev); | |
1980 | enable_irq(priv->interruptTransmit); | |
1981 | } | |
1982 | } | |
1983 | #endif | |
1984 | ||
1da177e4 | 1985 | /* The interrupt handler for devices with one interrupt */ |
7d12e780 | 1986 | static irqreturn_t gfar_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1987 | { |
1988 | struct net_device *dev = dev_id; | |
1989 | struct gfar_private *priv = netdev_priv(dev); | |
1990 | ||
1991 | /* Save ievent for future reference */ | |
1992 | u32 events = gfar_read(&priv->regs->ievent); | |
1993 | ||
1da177e4 | 1994 | /* Check for reception */ |
538cc7ee | 1995 | if (events & IEVENT_RX_MASK) |
7d12e780 | 1996 | gfar_receive(irq, dev_id); |
1da177e4 LT |
1997 | |
1998 | /* Check for transmit completion */ | |
538cc7ee | 1999 | if (events & IEVENT_TX_MASK) |
7d12e780 | 2000 | gfar_transmit(irq, dev_id); |
1da177e4 | 2001 | |
538cc7ee SS |
2002 | /* Check for errors */ |
2003 | if (events & IEVENT_ERR_MASK) | |
2004 | gfar_error(irq, dev_id); | |
1da177e4 LT |
2005 | |
2006 | return IRQ_HANDLED; | |
2007 | } | |
2008 | ||
1da177e4 LT |
2009 | /* Called every time the controller might need to be made |
2010 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 2011 | * information through variables in the phydev structure, and this |
1da177e4 LT |
2012 | * function converts those variables into the appropriate |
2013 | * register values, and can bring down the device if needed. | |
2014 | */ | |
2015 | static void adjust_link(struct net_device *dev) | |
2016 | { | |
2017 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 2018 | struct gfar __iomem *regs = priv->regs; |
bb40dcbb AF |
2019 | unsigned long flags; |
2020 | struct phy_device *phydev = priv->phydev; | |
2021 | int new_state = 0; | |
2022 | ||
fef6108d | 2023 | spin_lock_irqsave(&priv->txlock, flags); |
bb40dcbb AF |
2024 | if (phydev->link) { |
2025 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 2026 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 2027 | |
1da177e4 LT |
2028 | /* Now we make sure that we can be in full duplex mode. |
2029 | * If not, we operate in half-duplex mode. */ | |
bb40dcbb AF |
2030 | if (phydev->duplex != priv->oldduplex) { |
2031 | new_state = 1; | |
2032 | if (!(phydev->duplex)) | |
1da177e4 | 2033 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 2034 | else |
1da177e4 | 2035 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 2036 | |
bb40dcbb | 2037 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
2038 | } |
2039 | ||
bb40dcbb AF |
2040 | if (phydev->speed != priv->oldspeed) { |
2041 | new_state = 1; | |
2042 | switch (phydev->speed) { | |
1da177e4 | 2043 | case 1000: |
1da177e4 LT |
2044 | tempval = |
2045 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
2046 | |
2047 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2048 | break; |
2049 | case 100: | |
2050 | case 10: | |
1da177e4 LT |
2051 | tempval = |
2052 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
2053 | |
2054 | /* Reduced mode distinguishes | |
2055 | * between 10 and 100 */ | |
2056 | if (phydev->speed == SPEED_100) | |
2057 | ecntrl |= ECNTRL_R100; | |
2058 | else | |
2059 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2060 | break; |
2061 | default: | |
0bbaf069 KG |
2062 | if (netif_msg_link(priv)) |
2063 | printk(KERN_WARNING | |
bb40dcbb AF |
2064 | "%s: Ack! Speed (%d) is not 10/100/1000!\n", |
2065 | dev->name, phydev->speed); | |
1da177e4 LT |
2066 | break; |
2067 | } | |
2068 | ||
bb40dcbb | 2069 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
2070 | } |
2071 | ||
bb40dcbb | 2072 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 2073 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 2074 | |
1da177e4 | 2075 | if (!priv->oldlink) { |
bb40dcbb | 2076 | new_state = 1; |
1da177e4 | 2077 | priv->oldlink = 1; |
1da177e4 | 2078 | } |
bb40dcbb AF |
2079 | } else if (priv->oldlink) { |
2080 | new_state = 1; | |
2081 | priv->oldlink = 0; | |
2082 | priv->oldspeed = 0; | |
2083 | priv->oldduplex = -1; | |
1da177e4 | 2084 | } |
1da177e4 | 2085 | |
bb40dcbb AF |
2086 | if (new_state && netif_msg_link(priv)) |
2087 | phy_print_status(phydev); | |
2088 | ||
fef6108d | 2089 | spin_unlock_irqrestore(&priv->txlock, flags); |
bb40dcbb | 2090 | } |
1da177e4 LT |
2091 | |
2092 | /* Update the hash table based on the current list of multicast | |
2093 | * addresses we subscribe to. Also, change the promiscuity of | |
2094 | * the device based on the flags (this function is called | |
2095 | * whenever dev->flags is changed */ | |
2096 | static void gfar_set_multi(struct net_device *dev) | |
2097 | { | |
2098 | struct dev_mc_list *mc_ptr; | |
2099 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 2100 | struct gfar __iomem *regs = priv->regs; |
1da177e4 LT |
2101 | u32 tempval; |
2102 | ||
2103 | if(dev->flags & IFF_PROMISC) { | |
1da177e4 LT |
2104 | /* Set RCTRL to PROM */ |
2105 | tempval = gfar_read(®s->rctrl); | |
2106 | tempval |= RCTRL_PROM; | |
2107 | gfar_write(®s->rctrl, tempval); | |
2108 | } else { | |
2109 | /* Set RCTRL to not PROM */ | |
2110 | tempval = gfar_read(®s->rctrl); | |
2111 | tempval &= ~(RCTRL_PROM); | |
2112 | gfar_write(®s->rctrl, tempval); | |
2113 | } | |
6aa20a22 | 2114 | |
1da177e4 LT |
2115 | if(dev->flags & IFF_ALLMULTI) { |
2116 | /* Set the hash to rx all multicast frames */ | |
0bbaf069 KG |
2117 | gfar_write(®s->igaddr0, 0xffffffff); |
2118 | gfar_write(®s->igaddr1, 0xffffffff); | |
2119 | gfar_write(®s->igaddr2, 0xffffffff); | |
2120 | gfar_write(®s->igaddr3, 0xffffffff); | |
2121 | gfar_write(®s->igaddr4, 0xffffffff); | |
2122 | gfar_write(®s->igaddr5, 0xffffffff); | |
2123 | gfar_write(®s->igaddr6, 0xffffffff); | |
2124 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
2125 | gfar_write(®s->gaddr0, 0xffffffff); |
2126 | gfar_write(®s->gaddr1, 0xffffffff); | |
2127 | gfar_write(®s->gaddr2, 0xffffffff); | |
2128 | gfar_write(®s->gaddr3, 0xffffffff); | |
2129 | gfar_write(®s->gaddr4, 0xffffffff); | |
2130 | gfar_write(®s->gaddr5, 0xffffffff); | |
2131 | gfar_write(®s->gaddr6, 0xffffffff); | |
2132 | gfar_write(®s->gaddr7, 0xffffffff); | |
2133 | } else { | |
7f7f5316 AF |
2134 | int em_num; |
2135 | int idx; | |
2136 | ||
1da177e4 | 2137 | /* zero out the hash */ |
0bbaf069 KG |
2138 | gfar_write(®s->igaddr0, 0x0); |
2139 | gfar_write(®s->igaddr1, 0x0); | |
2140 | gfar_write(®s->igaddr2, 0x0); | |
2141 | gfar_write(®s->igaddr3, 0x0); | |
2142 | gfar_write(®s->igaddr4, 0x0); | |
2143 | gfar_write(®s->igaddr5, 0x0); | |
2144 | gfar_write(®s->igaddr6, 0x0); | |
2145 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
2146 | gfar_write(®s->gaddr0, 0x0); |
2147 | gfar_write(®s->gaddr1, 0x0); | |
2148 | gfar_write(®s->gaddr2, 0x0); | |
2149 | gfar_write(®s->gaddr3, 0x0); | |
2150 | gfar_write(®s->gaddr4, 0x0); | |
2151 | gfar_write(®s->gaddr5, 0x0); | |
2152 | gfar_write(®s->gaddr6, 0x0); | |
2153 | gfar_write(®s->gaddr7, 0x0); | |
2154 | ||
7f7f5316 AF |
2155 | /* If we have extended hash tables, we need to |
2156 | * clear the exact match registers to prepare for | |
2157 | * setting them */ | |
2158 | if (priv->extended_hash) { | |
2159 | em_num = GFAR_EM_NUM + 1; | |
2160 | gfar_clear_exact_match(dev); | |
2161 | idx = 1; | |
2162 | } else { | |
2163 | idx = 0; | |
2164 | em_num = 0; | |
2165 | } | |
2166 | ||
1da177e4 LT |
2167 | if(dev->mc_count == 0) |
2168 | return; | |
2169 | ||
2170 | /* Parse the list, and set the appropriate bits */ | |
2171 | for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) { | |
7f7f5316 AF |
2172 | if (idx < em_num) { |
2173 | gfar_set_mac_for_addr(dev, idx, | |
2174 | mc_ptr->dmi_addr); | |
2175 | idx++; | |
2176 | } else | |
2177 | gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr); | |
1da177e4 LT |
2178 | } |
2179 | } | |
2180 | ||
2181 | return; | |
2182 | } | |
2183 | ||
7f7f5316 AF |
2184 | |
2185 | /* Clears each of the exact match registers to zero, so they | |
2186 | * don't interfere with normal reception */ | |
2187 | static void gfar_clear_exact_match(struct net_device *dev) | |
2188 | { | |
2189 | int idx; | |
2190 | u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0}; | |
2191 | ||
2192 | for(idx = 1;idx < GFAR_EM_NUM + 1;idx++) | |
2193 | gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr); | |
2194 | } | |
2195 | ||
1da177e4 LT |
2196 | /* Set the appropriate hash bit for the given addr */ |
2197 | /* The algorithm works like so: | |
2198 | * 1) Take the Destination Address (ie the multicast address), and | |
2199 | * do a CRC on it (little endian), and reverse the bits of the | |
2200 | * result. | |
2201 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
2202 | * table. The table is controlled through 8 32-bit registers: | |
2203 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
2204 | * gaddr7. This means that the 3 most significant bits in the | |
2205 | * hash index which gaddr register to use, and the 5 other bits | |
2206 | * indicate which bit (assuming an IBM numbering scheme, which | |
2207 | * for PowerPC (tm) is usually the case) in the register holds | |
2208 | * the entry. */ | |
2209 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) | |
2210 | { | |
2211 | u32 tempval; | |
2212 | struct gfar_private *priv = netdev_priv(dev); | |
1da177e4 | 2213 | u32 result = ether_crc(MAC_ADDR_LEN, addr); |
0bbaf069 KG |
2214 | int width = priv->hash_width; |
2215 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
2216 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
2217 | u32 value = (1 << (31-whichbit)); |
2218 | ||
0bbaf069 | 2219 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 2220 | tempval |= value; |
0bbaf069 | 2221 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
2222 | |
2223 | return; | |
2224 | } | |
2225 | ||
7f7f5316 AF |
2226 | |
2227 | /* There are multiple MAC Address register pairs on some controllers | |
2228 | * This function sets the numth pair to a given address | |
2229 | */ | |
2230 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr) | |
2231 | { | |
2232 | struct gfar_private *priv = netdev_priv(dev); | |
2233 | int idx; | |
2234 | char tmpbuf[MAC_ADDR_LEN]; | |
2235 | u32 tempval; | |
cc8c6e37 | 2236 | u32 __iomem *macptr = &priv->regs->macstnaddr1; |
7f7f5316 AF |
2237 | |
2238 | macptr += num*2; | |
2239 | ||
2240 | /* Now copy it into the mac registers backwards, cuz */ | |
2241 | /* little endian is silly */ | |
2242 | for (idx = 0; idx < MAC_ADDR_LEN; idx++) | |
2243 | tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx]; | |
2244 | ||
2245 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
2246 | ||
2247 | tempval = *((u32 *) (tmpbuf + 4)); | |
2248 | ||
2249 | gfar_write(macptr+1, tempval); | |
2250 | } | |
2251 | ||
1da177e4 | 2252 | /* GFAR error interrupt handler */ |
7d12e780 | 2253 | static irqreturn_t gfar_error(int irq, void *dev_id) |
1da177e4 LT |
2254 | { |
2255 | struct net_device *dev = dev_id; | |
2256 | struct gfar_private *priv = netdev_priv(dev); | |
2257 | ||
2258 | /* Save ievent for future reference */ | |
2259 | u32 events = gfar_read(&priv->regs->ievent); | |
2260 | ||
2261 | /* Clear IEVENT */ | |
d87eb127 SW |
2262 | gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK); |
2263 | ||
2264 | /* Magic Packet is not an error. */ | |
b31a1d8b | 2265 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
2266 | (events & IEVENT_MAG)) |
2267 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
2268 | |
2269 | /* Hmm... */ | |
0bbaf069 KG |
2270 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
2271 | printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
538cc7ee | 2272 | dev->name, events, gfar_read(&priv->regs->imask)); |
1da177e4 LT |
2273 | |
2274 | /* Update the error counters */ | |
2275 | if (events & IEVENT_TXE) { | |
09f75cd7 | 2276 | dev->stats.tx_errors++; |
1da177e4 LT |
2277 | |
2278 | if (events & IEVENT_LC) | |
09f75cd7 | 2279 | dev->stats.tx_window_errors++; |
1da177e4 | 2280 | if (events & IEVENT_CRL) |
09f75cd7 | 2281 | dev->stats.tx_aborted_errors++; |
1da177e4 | 2282 | if (events & IEVENT_XFUN) { |
0bbaf069 | 2283 | if (netif_msg_tx_err(priv)) |
538cc7ee SS |
2284 | printk(KERN_DEBUG "%s: TX FIFO underrun, " |
2285 | "packet dropped.\n", dev->name); | |
09f75cd7 | 2286 | dev->stats.tx_dropped++; |
1da177e4 LT |
2287 | priv->extra_stats.tx_underrun++; |
2288 | ||
2289 | /* Reactivate the Tx Queues */ | |
2290 | gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT); | |
2291 | } | |
0bbaf069 KG |
2292 | if (netif_msg_tx_err(priv)) |
2293 | printk(KERN_DEBUG "%s: Transmit Error\n", dev->name); | |
1da177e4 LT |
2294 | } |
2295 | if (events & IEVENT_BSY) { | |
09f75cd7 | 2296 | dev->stats.rx_errors++; |
1da177e4 LT |
2297 | priv->extra_stats.rx_bsy++; |
2298 | ||
7d12e780 | 2299 | gfar_receive(irq, dev_id); |
1da177e4 | 2300 | |
0bbaf069 | 2301 | if (netif_msg_rx_err(priv)) |
538cc7ee SS |
2302 | printk(KERN_DEBUG "%s: busy error (rstat: %x)\n", |
2303 | dev->name, gfar_read(&priv->regs->rstat)); | |
1da177e4 LT |
2304 | } |
2305 | if (events & IEVENT_BABR) { | |
09f75cd7 | 2306 | dev->stats.rx_errors++; |
1da177e4 LT |
2307 | priv->extra_stats.rx_babr++; |
2308 | ||
0bbaf069 | 2309 | if (netif_msg_rx_err(priv)) |
538cc7ee | 2310 | printk(KERN_DEBUG "%s: babbling RX error\n", dev->name); |
1da177e4 LT |
2311 | } |
2312 | if (events & IEVENT_EBERR) { | |
2313 | priv->extra_stats.eberr++; | |
0bbaf069 | 2314 | if (netif_msg_rx_err(priv)) |
538cc7ee | 2315 | printk(KERN_DEBUG "%s: bus error\n", dev->name); |
1da177e4 | 2316 | } |
0bbaf069 | 2317 | if ((events & IEVENT_RXC) && netif_msg_rx_status(priv)) |
538cc7ee | 2318 | printk(KERN_DEBUG "%s: control frame\n", dev->name); |
1da177e4 LT |
2319 | |
2320 | if (events & IEVENT_BABT) { | |
2321 | priv->extra_stats.tx_babt++; | |
0bbaf069 | 2322 | if (netif_msg_tx_err(priv)) |
538cc7ee | 2323 | printk(KERN_DEBUG "%s: babbling TX error\n", dev->name); |
1da177e4 LT |
2324 | } |
2325 | return IRQ_HANDLED; | |
2326 | } | |
2327 | ||
72abb461 KS |
2328 | /* work with hotplug and coldplug */ |
2329 | MODULE_ALIAS("platform:fsl-gianfar"); | |
2330 | ||
b31a1d8b AF |
2331 | static struct of_device_id gfar_match[] = |
2332 | { | |
2333 | { | |
2334 | .type = "network", | |
2335 | .compatible = "gianfar", | |
2336 | }, | |
2337 | {}, | |
2338 | }; | |
2339 | ||
1da177e4 | 2340 | /* Structure for a device driver */ |
b31a1d8b AF |
2341 | static struct of_platform_driver gfar_driver = { |
2342 | .name = "fsl-gianfar", | |
2343 | .match_table = gfar_match, | |
2344 | ||
1da177e4 LT |
2345 | .probe = gfar_probe, |
2346 | .remove = gfar_remove, | |
d87eb127 SW |
2347 | .suspend = gfar_suspend, |
2348 | .resume = gfar_resume, | |
1da177e4 LT |
2349 | }; |
2350 | ||
2351 | static int __init gfar_init(void) | |
2352 | { | |
1577ecef | 2353 | return of_register_platform_driver(&gfar_driver); |
1da177e4 LT |
2354 | } |
2355 | ||
2356 | static void __exit gfar_exit(void) | |
2357 | { | |
b31a1d8b | 2358 | of_unregister_platform_driver(&gfar_driver); |
1da177e4 LT |
2359 | } |
2360 | ||
2361 | module_init(gfar_init); | |
2362 | module_exit(gfar_exit); | |
2363 |