Merge git://git.kernel.org/pub/scm/linux/kernel/git/viro/audit-current
[deliverable/linux.git] / drivers / net / hamachi.c
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1/* hamachi.c: A Packet Engines GNIC-II Gigabit Ethernet driver for Linux. */
2/*
3 Written 1998-2000 by Donald Becker.
4 Updates 2000 by Keith Underwood.
5
6aa20a22 6 This software may be used and distributed according to the terms of
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7 the GNU General Public License (GPL), incorporated herein by reference.
8 Drivers based on or derived from this code fall under the GPL and must
9 retain the authorship, copyright and license notice. This file is not
10 a complete program and may only be used when the entire operating
11 system is licensed under the GPL.
12
13 The author may be reached as becker@scyld.com, or C/O
14 Scyld Computing Corporation
15 410 Severn Ave., Suite 210
16 Annapolis MD 21403
17
18 This driver is for the Packet Engines GNIC-II PCI Gigabit Ethernet
19 adapter.
20
21 Support and updates available at
22 http://www.scyld.com/network/hamachi.html
03a8c661 23 [link no longer provides useful info -jgarzik]
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24 or
25 http://www.parl.clemson.edu/~keithu/hamachi.html
26
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27*/
28
29#define DRV_NAME "hamachi"
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30#define DRV_VERSION "2.1"
31#define DRV_RELDATE "Sept 11, 2006"
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32
33
34/* A few user-configurable values. */
35
36static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
37#define final_version
38#define hamachi_debug debug
39/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
40static int max_interrupt_work = 40;
41static int mtu;
42/* Default values selected by testing on a dual processor PIII-450 */
43/* These six interrupt control parameters may be set directly when loading the
44 * module, or through the rx_params and tx_params variables
45 */
46static int max_rx_latency = 0x11;
47static int max_rx_gap = 0x05;
48static int min_rx_pkt = 0x18;
6aa20a22 49static int max_tx_latency = 0x00;
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50static int max_tx_gap = 0x00;
51static int min_tx_pkt = 0x30;
52
53/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
54 -Setting to > 1518 causes all frames to be copied
55 -Setting to 0 disables copies
56*/
57static int rx_copybreak;
58
59/* An override for the hardware detection of bus width.
60 Set to 1 to force 32 bit PCI bus detection. Set to 4 to force 64 bit.
61 Add 2 to disable parity detection.
62*/
63static int force32;
64
65
66/* Used to pass the media type, etc.
67 These exist for driver interoperability.
68 No media types are currently defined.
69 - The lower 4 bits are reserved for the media type.
70 - The next three bits may be set to one of the following:
71 0x00000000 : Autodetect PCI bus
72 0x00000010 : Force 32 bit PCI bus
73 0x00000020 : Disable parity detection
74 0x00000040 : Force 64 bit PCI bus
75 Default is autodetect
76 - The next bit can be used to force half-duplex. This is a bad
77 idea since no known implementations implement half-duplex, and,
78 in general, half-duplex for gigabit ethernet is a bad idea.
6aa20a22 79 0x00000080 : Force half-duplex
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80 Default is full-duplex.
81 - In the original driver, the ninth bit could be used to force
82 full-duplex. Maintain that for compatibility
83 0x00000200 : Force full-duplex
84*/
85#define MAX_UNITS 8 /* More are supported, limit only on options */
86static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
87static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
88/* The Hamachi chipset supports 3 parameters each for Rx and Tx
89 * interruput management. Parameters will be loaded as specified into
6aa20a22 90 * the TxIntControl and RxIntControl registers.
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91 *
92 * The registers are arranged as follows:
93 * 23 - 16 15 - 8 7 - 0
94 * _________________________________
95 * | min_pkt | max_gap | max_latency |
96 * ---------------------------------
97 * min_pkt : The minimum number of packets processed between
6aa20a22 98 * interrupts.
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99 * max_gap : The maximum inter-packet gap in units of 8.192 us
100 * max_latency : The absolute time between interrupts in units of 8.192 us
6aa20a22 101 *
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102 */
103static int rx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
104static int tx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
105
106/* Operational parameters that are set at compile time. */
107
108/* Keep the ring sizes a power of two for compile efficiency.
109 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
110 Making the Tx ring too large decreases the effectiveness of channel
111 bonding and packet priority.
112 There are no ill effects from too-large receive rings, except for
113 excessive memory usage */
114/* Empirically it appears that the Tx ring needs to be a little bigger
115 for these Gbit adapters or you get into an overrun condition really
116 easily. Also, things appear to work a bit better in back-to-back
117 configurations if the Rx ring is 8 times the size of the Tx ring
118*/
119#define TX_RING_SIZE 64
120#define RX_RING_SIZE 512
121#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct hamachi_desc)
122#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct hamachi_desc)
123
124/*
125 * Enable netdev_ioctl. Added interrupt coalescing parameter adjustment.
126 * 2/19/99 Pete Wyckoff <wyckoff@ca.sandia.gov>
127 */
128
129/* play with 64-bit addrlen; seems to be a teensy bit slower --pw */
130/* #define ADDRLEN 64 */
131
132/*
133 * RX_CHECKSUM turns on card-generated receive checksum generation for
134 * TCP and UDP packets. Otherwise the upper layers do the calculation.
135 * TX_CHECKSUM won't do anything too useful, even if it works. There's no
136 * easy mechanism by which to tell the TCP/UDP stack that it need not
137 * generate checksums for this device. But if somebody can find a way
138 * to get that to work, most of the card work is in here already.
139 * 3/10/1999 Pete Wyckoff <wyckoff@ca.sandia.gov>
140 */
141#undef TX_CHECKSUM
142#define RX_CHECKSUM
143
144/* Operational parameters that usually are not changed. */
145/* Time in jiffies before concluding the transmitter is hung. */
146#define TX_TIMEOUT (5*HZ)
147
148#include <linux/module.h>
149#include <linux/kernel.h>
150#include <linux/string.h>
151#include <linux/timer.h>
152#include <linux/time.h>
153#include <linux/errno.h>
154#include <linux/ioport.h>
155#include <linux/slab.h>
156#include <linux/interrupt.h>
157#include <linux/pci.h>
158#include <linux/init.h>
159#include <linux/ethtool.h>
160#include <linux/mii.h>
161#include <linux/netdevice.h>
162#include <linux/etherdevice.h>
163#include <linux/skbuff.h>
164#include <linux/ip.h>
165#include <linux/delay.h>
166#include <linux/bitops.h>
167
168#include <asm/uaccess.h>
169#include <asm/processor.h> /* Processor type for cache alignment. */
170#include <asm/io.h>
171#include <asm/unaligned.h>
172#include <asm/cache.h>
173
98683956 174static const char version[] __devinitconst =
1da177e4 175KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n"
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176" Some modifications by Eric kasten <kasten@nscl.msu.edu>\n"
177" Further modifications by Keith Underwood <keithu@parl.clemson.edu>\n";
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178
179
180/* IP_MF appears to be only defined in <netinet/ip.h>, however,
181 we need it for hardware checksumming support. FYI... some of
182 the definitions in <netinet/ip.h> conflict/duplicate those in
183 other linux headers causing many compiler warnings.
184*/
185#ifndef IP_MF
6aa20a22 186 #define IP_MF 0x2000 /* IP more frags from <netinet/ip.h> */
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187#endif
188
189/* Define IP_OFFSET to be IPOPT_OFFSET */
190#ifndef IP_OFFSET
191 #ifdef IPOPT_OFFSET
192 #define IP_OFFSET IPOPT_OFFSET
193 #else
194 #define IP_OFFSET 2
195 #endif
196#endif
197
198#define RUN_AT(x) (jiffies + (x))
199
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200#ifndef ADDRLEN
201#define ADDRLEN 32
202#endif
203
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204/* Condensed bus+endian portability operations. */
205#if ADDRLEN == 64
206#define cpu_to_leXX(addr) cpu_to_le64(addr)
8e985918 207#define leXX_to_cpu(addr) le64_to_cpu(addr)
6aa20a22 208#else
1da177e4 209#define cpu_to_leXX(addr) cpu_to_le32(addr)
8e985918 210#define leXX_to_cpu(addr) le32_to_cpu(addr)
6aa20a22 211#endif
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212
213
214/*
215 Theory of Operation
216
217I. Board Compatibility
218
219This device driver is designed for the Packet Engines "Hamachi"
220Gigabit Ethernet chip. The only PCA currently supported is the GNIC-II 64-bit
22166Mhz PCI card.
222
223II. Board-specific settings
224
225No jumpers exist on the board. The chip supports software correction of
226various motherboard wiring errors, however this driver does not support
227that feature.
228
229III. Driver operation
230
231IIIa. Ring buffers
232
233The Hamachi uses a typical descriptor based bus-master architecture.
234The descriptor list is similar to that used by the Digital Tulip.
235This driver uses two statically allocated fixed-size descriptor lists
236formed into rings by a branch from the final descriptor to the beginning of
237the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
238
239This driver uses a zero-copy receive and transmit scheme similar my other
240network drivers.
241The driver allocates full frame size skbuffs for the Rx ring buffers at
242open() time and passes the skb->data field to the Hamachi as receive data
243buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
244a fresh skbuff is allocated and the frame is copied to the new skbuff.
245When the incoming frame is larger, the skbuff is passed directly up the
246protocol stack and replaced by a newly allocated skbuff.
247
248The RX_COPYBREAK value is chosen to trade-off the memory wasted by
249using a full-sized skbuff for small frames vs. the copying costs of larger
250frames. Gigabit cards are typically used on generously configured machines
251and the underfilled buffers have negligible impact compared to the benefit of
252a single allocation size, so the default value of zero results in never
253copying packets.
254
255IIIb/c. Transmit/Receive Structure
256
257The Rx and Tx descriptor structure are straight-forward, with no historical
258baggage that must be explained. Unlike the awkward DBDMA structure, there
259are no unused fields or option bits that had only one allowable setting.
260
261Two details should be noted about the descriptors: The chip supports both 32
262bit and 64 bit address structures, and the length field is overwritten on
263the receive descriptors. The descriptor length is set in the control word
264for each channel. The development driver uses 32 bit addresses only, however
26564 bit addresses may be enabled for 64 bit architectures e.g. the Alpha.
266
267IIId. Synchronization
268
269This driver is very similar to my other network drivers.
270The driver runs as two independent, single-threaded flows of control. One
271is the send-packet routine, which enforces single-threaded use by the
272dev->tbusy flag. The other thread is the interrupt handler, which is single
273threaded by the hardware and other software.
274
275The send packet thread has partial control over the Tx ring and 'dev->tbusy'
276flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
277queue slot is empty, it clears the tbusy flag when finished otherwise it sets
278the 'hmp->tx_full' flag.
279
280The interrupt handler has exclusive control over the Rx ring and records stats
281from the Tx ring. After reaping the stats, it marks the Tx queue entry as
282empty by incrementing the dirty_tx mark. Iff the 'hmp->tx_full' flag is set, it
283clears both the tx_full and tbusy flags.
284
285IV. Notes
286
287Thanks to Kim Stearns of Packet Engines for providing a pair of GNIC-II boards.
288
289IVb. References
290
291Hamachi Engineering Design Specification, 5/15/97
292(Note: This version was marked "Confidential".)
293
294IVc. Errata
295
6aa20a22 296None noted.
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297
298V. Recent Changes
299
6aa20a22 30001/15/1999 EPK Enlargement of the TX and RX ring sizes. This appears
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301 to help avoid some stall conditions -- this needs further research.
302
6aa20a22 30301/15/1999 EPK Creation of the hamachi_tx function. This function cleans
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304 the Tx ring and is called from hamachi_start_xmit (this used to be
305 called from hamachi_interrupt but it tends to delay execution of the
306 interrupt handler and thus reduce bandwidth by reducing the latency
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307 between hamachi_rx()'s). Notably, some modification has been made so
308 that the cleaning loop checks only to make sure that the DescOwn bit
309 isn't set in the status flag since the card is not required
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310 to set the entire flag to zero after processing.
311
6aa20a22 31201/15/1999 EPK In the hamachi_start_tx function, the Tx ring full flag is
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313 checked before attempting to add a buffer to the ring. If the ring is full
314 an attempt is made to free any dirty buffers and thus find space for
315 the new buffer or the function returns non-zero which should case the
316 scheduler to reschedule the buffer later.
317
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31801/15/1999 EPK Some adjustments were made to the chip initialization.
319 End-to-end flow control should now be fully active and the interrupt
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320 algorithm vars have been changed. These could probably use further tuning.
321
32201/15/1999 EPK Added the max_{rx,tx}_latency options. These are used to
323 set the rx and tx latencies for the Hamachi interrupts. If you're having
324 problems with network stalls, try setting these to higher values.
325 Valid values are 0x00 through 0xff.
326
6aa20a22 32701/15/1999 EPK In general, the overall bandwidth has increased and
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328 latencies are better (sometimes by a factor of 2). Stalls are rare at
329 this point, however there still appears to be a bug somewhere between the
330 hardware and driver. TCP checksum errors under load also appear to be
331 eliminated at this point.
332
33301/18/1999 EPK Ensured that the DescEndRing bit was being set on both the
334 Rx and Tx rings. This appears to have been affecting whether a particular
335 peer-to-peer connection would hang under high load. I believe the Rx
336 rings was typically getting set correctly, but the Tx ring wasn't getting
337 the DescEndRing bit set during initialization. ??? Does this mean the
338 hamachi card is using the DescEndRing in processing even if a particular
6aa20a22 339 slot isn't in use -- hypothetically, the card might be searching the
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340 entire Tx ring for slots with the DescOwn bit set and then processing
341 them. If the DescEndRing bit isn't set, then it might just wander off
342 through memory until it hits a chunk of data with that bit set
343 and then looping back.
344
6aa20a22 34502/09/1999 EPK Added Michel Mueller's TxDMA Interrupt and Tx-timeout
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346 problem (TxCmd and RxCmd need only to be set when idle or stopped.
347
34802/09/1999 EPK Added code to check/reset dev->tbusy in hamachi_interrupt.
6aa20a22 349 (Michel Mueller pointed out the ``permanently busy'' potential
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350 problem here).
351
6aa20a22 35202/22/1999 EPK Added Pete Wyckoff's ioctl to control the Tx/Rx latencies.
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353
35402/23/1999 EPK Verified that the interrupt status field bits for Tx were
355 incorrectly defined and corrected (as per Michel Mueller).
356
35702/23/1999 EPK Corrected the Tx full check to check that at least 4 slots
358 were available before reseting the tbusy and tx_full flags
359 (as per Michel Mueller).
360
36103/11/1999 EPK Added Pete Wyckoff's hardware checksumming support.
362
36312/31/1999 KDU Cleaned up assorted things and added Don's code to force
36432 bit.
365
36602/20/2000 KDU Some of the control was just plain odd. Cleaned up the
367hamachi_start_xmit() and hamachi_interrupt() code. There is still some
6aa20a22 368re-structuring I would like to do.
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369
37003/01/2000 KDU Experimenting with a WIDE range of interrupt mitigation
371parameters on a dual P3-450 setup yielded the new default interrupt
372mitigation parameters. Tx should interrupt VERY infrequently due to
373Eric's scheme. Rx should be more often...
374
37503/13/2000 KDU Added a patch to make the Rx Checksum code interact
6aa20a22 376nicely with non-linux machines.
1da177e4 377
6aa20a22 37803/13/2000 KDU Experimented with some of the configuration values:
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379
380 -It seems that enabling PCI performance commands for descriptors
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381 (changing RxDMACtrl and TxDMACtrl lower nibble from 5 to D) has minimal
382 performance impact for any of my tests. (ttcp, netpipe, netperf) I will
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383 leave them that way until I hear further feedback.
384
6aa20a22 385 -Increasing the PCI_LATENCY_TIMER to 130
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386 (2 + (burst size of 128 * (0 wait states + 1))) seems to slightly
387 degrade performance. Leaving default at 64 pending further information.
388
6aa20a22 38903/14/2000 KDU Further tuning:
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390
391 -adjusted boguscnt in hamachi_rx() to depend on interrupt
392 mitigation parameters chosen.
393
6aa20a22 394 -Selected a set of interrupt parameters based on some extensive testing.
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395 These may change with more testing.
396
397TO DO:
398
399-Consider borrowing from the acenic driver code to check PCI_COMMAND for
400PCI_COMMAND_INVALIDATE. Set maximum burst size to cache line size in
401that case.
402
6aa20a22 403-fix the reset procedure. It doesn't quite work.
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404*/
405
406/* A few values that may be tweaked. */
407/* Size of each temporary Rx buffer, calculated as:
408 * 1518 bytes (ethernet packet) + 2 bytes (to get 8 byte alignment for
409 * the card) + 8 bytes of status info + 8 bytes for the Rx Checksum +
6aa20a22 410 * 2 more because we use skb_reserve.
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411 */
412#define PKT_BUF_SZ 1538
413
414/* For now, this is going to be set to the maximum size of an ethernet
415 * packet. Eventually, we may want to make it a variable that is
416 * related to the MTU
417 */
418#define MAX_FRAME_SIZE 1518
419
420/* The rest of these values should never change. */
421
422static void hamachi_timer(unsigned long data);
423
424enum capability_flags {CanHaveMII=1, };
f71e1309 425static const struct chip_info {
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426 u16 vendor_id, device_id, device_id_mask, pad;
427 const char *name;
428 void (*media_timer)(unsigned long data);
429 int flags;
430} chip_tbl[] = {
431 {0x1318, 0x0911, 0xffff, 0, "Hamachi GNIC-II", hamachi_timer, 0},
432 {0,},
433};
434
435/* Offsets to the Hamachi registers. Various sizes. */
436enum hamachi_offsets {
437 TxDMACtrl=0x00, TxCmd=0x04, TxStatus=0x06, TxPtr=0x08, TxCurPtr=0x10,
438 RxDMACtrl=0x20, RxCmd=0x24, RxStatus=0x26, RxPtr=0x28, RxCurPtr=0x30,
439 PCIClkMeas=0x060, MiscStatus=0x066, ChipRev=0x68, ChipReset=0x06B,
440 LEDCtrl=0x06C, VirtualJumpers=0x06D, GPIO=0x6E,
441 TxChecksum=0x074, RxChecksum=0x076,
442 TxIntrCtrl=0x078, RxIntrCtrl=0x07C,
443 InterruptEnable=0x080, InterruptClear=0x084, IntrStatus=0x088,
444 EventStatus=0x08C,
445 MACCnfg=0x0A0, FrameGap0=0x0A2, FrameGap1=0x0A4,
446 /* See enum MII_offsets below. */
447 MACCnfg2=0x0B0, RxDepth=0x0B8, FlowCtrl=0x0BC, MaxFrameSize=0x0CE,
448 AddrMode=0x0D0, StationAddr=0x0D2,
449 /* Gigabit AutoNegotiation. */
450 ANCtrl=0x0E0, ANStatus=0x0E2, ANXchngCtrl=0x0E4, ANAdvertise=0x0E8,
451 ANLinkPartnerAbility=0x0EA,
452 EECmdStatus=0x0F0, EEData=0x0F1, EEAddr=0x0F2,
453 FIFOcfg=0x0F8,
454};
455
456/* Offsets to the MII-mode registers. */
457enum MII_offsets {
458 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
459 MII_Status=0xAE,
460};
461
462/* Bits in the interrupt status/mask registers. */
463enum intr_status_bits {
464 IntrRxDone=0x01, IntrRxPCIFault=0x02, IntrRxPCIErr=0x04,
465 IntrTxDone=0x100, IntrTxPCIFault=0x200, IntrTxPCIErr=0x400,
466 LinkChange=0x10000, NegotiationChange=0x20000, StatsMax=0x40000, };
467
468/* The Hamachi Rx and Tx buffer descriptors. */
469struct hamachi_desc {
8e985918 470 __le32 status_n_length;
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471#if ADDRLEN == 64
472 u32 pad;
8e985918 473 __le64 addr;
1da177e4 474#else
8e985918 475 __le32 addr;
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476#endif
477};
478
479/* Bits in hamachi_desc.status_n_length */
480enum desc_status_bits {
6aa20a22 481 DescOwn=0x80000000, DescEndPacket=0x40000000, DescEndRing=0x20000000,
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482 DescIntr=0x10000000,
483};
484
485#define PRIV_ALIGN 15 /* Required alignment mask */
486#define MII_CNT 4
487struct hamachi_private {
488 /* Descriptor rings first for alignment. Tx requires a second descriptor
489 for status. */
490 struct hamachi_desc *rx_ring;
491 struct hamachi_desc *tx_ring;
492 struct sk_buff* rx_skbuff[RX_RING_SIZE];
493 struct sk_buff* tx_skbuff[TX_RING_SIZE];
494 dma_addr_t tx_ring_dma;
495 dma_addr_t rx_ring_dma;
496 struct net_device_stats stats;
497 struct timer_list timer; /* Media selection timer. */
498 /* Frequently used and paired value: keep adjacent for cache effect. */
499 spinlock_t lock;
500 int chip_id;
501 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
502 unsigned int cur_tx, dirty_tx;
503 unsigned int rx_buf_sz; /* Based on MTU+slack. */
504 unsigned int tx_full:1; /* The Tx queue is full. */
505 unsigned int duplex_lock:1;
506 unsigned int default_port:4; /* Last dev->if_port value. */
507 /* MII transceiver section. */
508 int mii_cnt; /* MII device addresses. */
509 struct mii_if_info mii_if; /* MII lib hooks/info */
510 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
511 u32 rx_int_var, tx_int_var; /* interrupt control variables */
512 u32 option; /* Hold on to a copy of the options */
513 struct pci_dev *pci_dev;
514 void __iomem *base;
515};
516
517MODULE_AUTHOR("Donald Becker <becker@scyld.com>, Eric Kasten <kasten@nscl.msu.edu>, Keith Underwood <keithu@parl.clemson.edu>");
518MODULE_DESCRIPTION("Packet Engines 'Hamachi' GNIC-II Gigabit Ethernet driver");
519MODULE_LICENSE("GPL");
520
521module_param(max_interrupt_work, int, 0);
522module_param(mtu, int, 0);
523module_param(debug, int, 0);
524module_param(min_rx_pkt, int, 0);
525module_param(max_rx_gap, int, 0);
526module_param(max_rx_latency, int, 0);
527module_param(min_tx_pkt, int, 0);
528module_param(max_tx_gap, int, 0);
529module_param(max_tx_latency, int, 0);
530module_param(rx_copybreak, int, 0);
531module_param_array(rx_params, int, NULL, 0);
532module_param_array(tx_params, int, NULL, 0);
533module_param_array(options, int, NULL, 0);
534module_param_array(full_duplex, int, NULL, 0);
535module_param(force32, int, 0);
536MODULE_PARM_DESC(max_interrupt_work, "GNIC-II maximum events handled per interrupt");
537MODULE_PARM_DESC(mtu, "GNIC-II MTU (all boards)");
538MODULE_PARM_DESC(debug, "GNIC-II debug level (0-7)");
539MODULE_PARM_DESC(min_rx_pkt, "GNIC-II minimum Rx packets processed between interrupts");
540MODULE_PARM_DESC(max_rx_gap, "GNIC-II maximum Rx inter-packet gap in 8.192 microsecond units");
541MODULE_PARM_DESC(max_rx_latency, "GNIC-II time between Rx interrupts in 8.192 microsecond units");
542MODULE_PARM_DESC(min_tx_pkt, "GNIC-II minimum Tx packets processed between interrupts");
543MODULE_PARM_DESC(max_tx_gap, "GNIC-II maximum Tx inter-packet gap in 8.192 microsecond units");
544MODULE_PARM_DESC(max_tx_latency, "GNIC-II time between Tx interrupts in 8.192 microsecond units");
545MODULE_PARM_DESC(rx_copybreak, "GNIC-II copy breakpoint for copy-only-tiny-frames");
546MODULE_PARM_DESC(rx_params, "GNIC-II min_rx_pkt+max_rx_gap+max_rx_latency");
547MODULE_PARM_DESC(tx_params, "GNIC-II min_tx_pkt+max_tx_gap+max_tx_latency");
548MODULE_PARM_DESC(options, "GNIC-II Bits 0-3: media type, bits 4-6: as force32, bit 7: half duplex, bit 9 full duplex");
549MODULE_PARM_DESC(full_duplex, "GNIC-II full duplex setting(s) (1)");
550MODULE_PARM_DESC(force32, "GNIC-II: Bit 0: 32 bit PCI, bit 1: disable parity, bit 2: 64 bit PCI (all boards)");
6aa20a22 551
1da177e4
LT
552static int read_eeprom(void __iomem *ioaddr, int location);
553static int mdio_read(struct net_device *dev, int phy_id, int location);
554static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
555static int hamachi_open(struct net_device *dev);
556static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
557static void hamachi_timer(unsigned long data);
558static void hamachi_tx_timeout(struct net_device *dev);
559static void hamachi_init_ring(struct net_device *dev);
61357325
SH
560static netdev_tx_t hamachi_start_xmit(struct sk_buff *skb,
561 struct net_device *dev);
7d12e780 562static irqreturn_t hamachi_interrupt(int irq, void *dev_instance);
1da177e4
LT
563static int hamachi_rx(struct net_device *dev);
564static inline int hamachi_tx(struct net_device *dev);
565static void hamachi_error(struct net_device *dev, int intr_status);
566static int hamachi_close(struct net_device *dev);
567static struct net_device_stats *hamachi_get_stats(struct net_device *dev);
568static void set_rx_mode(struct net_device *dev);
7282d491
JG
569static const struct ethtool_ops ethtool_ops;
570static const struct ethtool_ops ethtool_ops_no_mii;
1da177e4 571
a8652d23
SH
572static const struct net_device_ops hamachi_netdev_ops = {
573 .ndo_open = hamachi_open,
574 .ndo_stop = hamachi_close,
575 .ndo_start_xmit = hamachi_start_xmit,
576 .ndo_get_stats = hamachi_get_stats,
577 .ndo_set_multicast_list = set_rx_mode,
578 .ndo_change_mtu = eth_change_mtu,
579 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 580 .ndo_set_mac_address = eth_mac_addr,
a8652d23
SH
581 .ndo_tx_timeout = hamachi_tx_timeout,
582 .ndo_do_ioctl = netdev_ioctl,
583};
584
585
1da177e4
LT
586static int __devinit hamachi_init_one (struct pci_dev *pdev,
587 const struct pci_device_id *ent)
588{
589 struct hamachi_private *hmp;
590 int option, i, rx_int_var, tx_int_var, boguscnt;
591 int chip_id = ent->driver_data;
592 int irq;
593 void __iomem *ioaddr;
594 unsigned long base;
595 static int card_idx;
596 struct net_device *dev;
597 void *ring_space;
598 dma_addr_t ring_dma;
599 int ret = -ENOMEM;
600
601/* when built into the kernel, we only print version if device is found */
602#ifndef MODULE
603 static int printed_version;
604 if (!printed_version++)
605 printk(version);
606#endif
607
608 if (pci_enable_device(pdev)) {
609 ret = -EIO;
610 goto err_out;
611 }
612
613 base = pci_resource_start(pdev, 0);
614#ifdef __alpha__ /* Really "64 bit addrs" */
615 base |= (pci_resource_start(pdev, 1) << 32);
616#endif
617
618 pci_set_master(pdev);
619
620 i = pci_request_regions(pdev, DRV_NAME);
2e8a538d
JG
621 if (i)
622 return i;
1da177e4
LT
623
624 irq = pdev->irq;
625 ioaddr = ioremap(base, 0x400);
626 if (!ioaddr)
627 goto err_out_release;
628
629 dev = alloc_etherdev(sizeof(struct hamachi_private));
630 if (!dev)
631 goto err_out_iounmap;
632
1da177e4
LT
633 SET_NETDEV_DEV(dev, &pdev->dev);
634
635#ifdef TX_CHECKSUM
636 printk("check that skbcopy in ip_queue_xmit isn't happening\n");
637 dev->hard_header_len += 8; /* for cksum tag */
638#endif
639
640 for (i = 0; i < 6; i++)
641 dev->dev_addr[i] = 1 ? read_eeprom(ioaddr, 4 + i)
642 : readb(ioaddr + StationAddr + i);
643
644#if ! defined(final_version)
645 if (hamachi_debug > 4)
646 for (i = 0; i < 0x10; i++)
647 printk("%2.2x%s",
648 read_eeprom(ioaddr, i), i % 16 != 15 ? " " : "\n");
649#endif
650
651 hmp = netdev_priv(dev);
652 spin_lock_init(&hmp->lock);
653
654 hmp->mii_if.dev = dev;
655 hmp->mii_if.mdio_read = mdio_read;
656 hmp->mii_if.mdio_write = mdio_write;
657 hmp->mii_if.phy_id_mask = 0x1f;
658 hmp->mii_if.reg_num_mask = 0x1f;
659
660 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
661 if (!ring_space)
662 goto err_out_cleardev;
663 hmp->tx_ring = (struct hamachi_desc *)ring_space;
664 hmp->tx_ring_dma = ring_dma;
665
666 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
667 if (!ring_space)
668 goto err_out_unmap_tx;
669 hmp->rx_ring = (struct hamachi_desc *)ring_space;
670 hmp->rx_ring_dma = ring_dma;
671
672 /* Check for options being passed in */
673 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
674 if (dev->mem_start)
675 option = dev->mem_start;
676
677 /* If the bus size is misidentified, do the following. */
6aa20a22 678 force32 = force32 ? force32 :
1da177e4
LT
679 ((option >= 0) ? ((option & 0x00000070) >> 4) : 0 );
680 if (force32)
681 writeb(force32, ioaddr + VirtualJumpers);
682
683 /* Hmmm, do we really need to reset the chip???. */
684 writeb(0x01, ioaddr + ChipReset);
685
686 /* After a reset, the clock speed measurement of the PCI bus will not
687 * be valid for a moment. Wait for a little while until it is. If
688 * it takes more than 10ms, forget it.
689 */
6aa20a22 690 udelay(10);
1da177e4
LT
691 i = readb(ioaddr + PCIClkMeas);
692 for (boguscnt = 0; (!(i & 0x080)) && boguscnt < 1000; boguscnt++){
6aa20a22
JG
693 udelay(10);
694 i = readb(ioaddr + PCIClkMeas);
1da177e4
LT
695 }
696
697 hmp->base = ioaddr;
698 dev->base_addr = (unsigned long)ioaddr;
699 dev->irq = irq;
700 pci_set_drvdata(pdev, dev);
701
702 hmp->chip_id = chip_id;
703 hmp->pci_dev = pdev;
704
705 /* The lower four bits are the media type. */
706 if (option > 0) {
707 hmp->option = option;
708 if (option & 0x200)
709 hmp->mii_if.full_duplex = 1;
710 else if (option & 0x080)
711 hmp->mii_if.full_duplex = 0;
712 hmp->default_port = option & 15;
713 if (hmp->default_port)
714 hmp->mii_if.force_media = 1;
715 }
716 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
717 hmp->mii_if.full_duplex = 1;
718
719 /* lock the duplex mode if someone specified a value */
720 if (hmp->mii_if.full_duplex || (option & 0x080))
721 hmp->duplex_lock = 1;
722
723 /* Set interrupt tuning parameters */
724 max_rx_latency = max_rx_latency & 0x00ff;
725 max_rx_gap = max_rx_gap & 0x00ff;
726 min_rx_pkt = min_rx_pkt & 0x00ff;
727 max_tx_latency = max_tx_latency & 0x00ff;
728 max_tx_gap = max_tx_gap & 0x00ff;
729 min_tx_pkt = min_tx_pkt & 0x00ff;
730
731 rx_int_var = card_idx < MAX_UNITS ? rx_params[card_idx] : -1;
732 tx_int_var = card_idx < MAX_UNITS ? tx_params[card_idx] : -1;
6aa20a22 733 hmp->rx_int_var = rx_int_var >= 0 ? rx_int_var :
1da177e4 734 (min_rx_pkt << 16 | max_rx_gap << 8 | max_rx_latency);
6aa20a22 735 hmp->tx_int_var = tx_int_var >= 0 ? tx_int_var :
1da177e4
LT
736 (min_tx_pkt << 16 | max_tx_gap << 8 | max_tx_latency);
737
738
739 /* The Hamachi-specific entries in the device structure. */
a8652d23 740 dev->netdev_ops = &hamachi_netdev_ops;
1da177e4
LT
741 if (chip_tbl[hmp->chip_id].flags & CanHaveMII)
742 SET_ETHTOOL_OPS(dev, &ethtool_ops);
743 else
744 SET_ETHTOOL_OPS(dev, &ethtool_ops_no_mii);
1da177e4
LT
745 dev->watchdog_timeo = TX_TIMEOUT;
746 if (mtu)
747 dev->mtu = mtu;
748
749 i = register_netdev(dev);
750 if (i) {
751 ret = i;
752 goto err_out_unmap_rx;
753 }
754
e174961c 755 printk(KERN_INFO "%s: %s type %x at %p, %pM, IRQ %d.\n",
1da177e4 756 dev->name, chip_tbl[chip_id].name, readl(ioaddr + ChipRev),
e174961c 757 ioaddr, dev->dev_addr, irq);
1da177e4
LT
758 i = readb(ioaddr + PCIClkMeas);
759 printk(KERN_INFO "%s: %d-bit %d Mhz PCI bus (%d), Virtual Jumpers "
760 "%2.2x, LPA %4.4x.\n",
761 dev->name, readw(ioaddr + MiscStatus) & 1 ? 64 : 32,
762 i ? 2000/(i&0x7f) : 0, i&0x7f, (int)readb(ioaddr + VirtualJumpers),
763 readw(ioaddr + ANLinkPartnerAbility));
764
765 if (chip_tbl[hmp->chip_id].flags & CanHaveMII) {
766 int phy, phy_idx = 0;
767 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
768 int mii_status = mdio_read(dev, phy, MII_BMSR);
769 if (mii_status != 0xffff &&
770 mii_status != 0x0000) {
771 hmp->phys[phy_idx++] = phy;
772 hmp->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
773 printk(KERN_INFO "%s: MII PHY found at address %d, status "
774 "0x%4.4x advertising %4.4x.\n",
775 dev->name, phy, mii_status, hmp->mii_if.advertising);
776 }
777 }
778 hmp->mii_cnt = phy_idx;
779 if (hmp->mii_cnt > 0)
780 hmp->mii_if.phy_id = hmp->phys[0];
781 else
782 memset(&hmp->mii_if, 0, sizeof(hmp->mii_if));
783 }
784 /* Configure gigabit autonegotiation. */
785 writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */
786 writew(0x08e0, ioaddr + ANAdvertise); /* Set our advertise word. */
787 writew(0x1000, ioaddr + ANCtrl); /* Enable negotiation */
788
789 card_idx++;
790 return 0;
791
792err_out_unmap_rx:
6aa20a22 793 pci_free_consistent(pdev, RX_TOTAL_SIZE, hmp->rx_ring,
1da177e4
LT
794 hmp->rx_ring_dma);
795err_out_unmap_tx:
6aa20a22 796 pci_free_consistent(pdev, TX_TOTAL_SIZE, hmp->tx_ring,
1da177e4
LT
797 hmp->tx_ring_dma);
798err_out_cleardev:
799 free_netdev (dev);
800err_out_iounmap:
801 iounmap(ioaddr);
802err_out_release:
803 pci_release_regions(pdev);
804err_out:
805 return ret;
806}
807
808static int __devinit read_eeprom(void __iomem *ioaddr, int location)
809{
810 int bogus_cnt = 1000;
811
812 /* We should check busy first - per docs -KDU */
813 while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0);
814 writew(location, ioaddr + EEAddr);
815 writeb(0x02, ioaddr + EECmdStatus);
816 bogus_cnt = 1000;
817 while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0);
818 if (hamachi_debug > 5)
819 printk(" EEPROM status is %2.2x after %d ticks.\n",
820 (int)readb(ioaddr + EECmdStatus), 1000- bogus_cnt);
821 return readb(ioaddr + EEData);
822}
823
824/* MII Managemen Data I/O accesses.
825 These routines assume the MDIO controller is idle, and do not exit until
826 the command is finished. */
827
828static int mdio_read(struct net_device *dev, int phy_id, int location)
829{
830 struct hamachi_private *hmp = netdev_priv(dev);
831 void __iomem *ioaddr = hmp->base;
832 int i;
833
834 /* We should check busy first - per docs -KDU */
835 for (i = 10000; i >= 0; i--)
836 if ((readw(ioaddr + MII_Status) & 1) == 0)
837 break;
838 writew((phy_id<<8) + location, ioaddr + MII_Addr);
839 writew(0x0001, ioaddr + MII_Cmd);
840 for (i = 10000; i >= 0; i--)
841 if ((readw(ioaddr + MII_Status) & 1) == 0)
842 break;
843 return readw(ioaddr + MII_Rd_Data);
844}
845
846static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
847{
848 struct hamachi_private *hmp = netdev_priv(dev);
849 void __iomem *ioaddr = hmp->base;
850 int i;
851
852 /* We should check busy first - per docs -KDU */
853 for (i = 10000; i >= 0; i--)
854 if ((readw(ioaddr + MII_Status) & 1) == 0)
855 break;
856 writew((phy_id<<8) + location, ioaddr + MII_Addr);
857 writew(value, ioaddr + MII_Wr_Data);
858
859 /* Wait for the command to finish. */
860 for (i = 10000; i >= 0; i--)
861 if ((readw(ioaddr + MII_Status) & 1) == 0)
862 break;
863 return;
864}
865
6aa20a22 866
1da177e4
LT
867static int hamachi_open(struct net_device *dev)
868{
869 struct hamachi_private *hmp = netdev_priv(dev);
870 void __iomem *ioaddr = hmp->base;
871 int i;
872 u32 rx_int_var, tx_int_var;
873 u16 fifo_info;
874
1fb9df5d 875 i = request_irq(dev->irq, &hamachi_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT
876 if (i)
877 return i;
878
879 if (hamachi_debug > 1)
880 printk(KERN_DEBUG "%s: hamachi_open() irq %d.\n",
881 dev->name, dev->irq);
882
883 hamachi_init_ring(dev);
884
885#if ADDRLEN == 64
886 /* writellll anyone ? */
8e985918
AV
887 writel(hmp->rx_ring_dma, ioaddr + RxPtr);
888 writel(hmp->rx_ring_dma >> 32, ioaddr + RxPtr + 4);
889 writel(hmp->tx_ring_dma, ioaddr + TxPtr);
890 writel(hmp->tx_ring_dma >> 32, ioaddr + TxPtr + 4);
1da177e4 891#else
8e985918
AV
892 writel(hmp->rx_ring_dma, ioaddr + RxPtr);
893 writel(hmp->tx_ring_dma, ioaddr + TxPtr);
1da177e4
LT
894#endif
895
6aa20a22 896 /* TODO: It would make sense to organize this as words since the card
1da177e4
LT
897 * documentation does. -KDU
898 */
899 for (i = 0; i < 6; i++)
900 writeb(dev->dev_addr[i], ioaddr + StationAddr + i);
901
902 /* Initialize other registers: with so many this eventually this will
903 converted to an offset/value list. */
904
905 /* Configure the FIFO */
906 fifo_info = (readw(ioaddr + GPIO) & 0x00C0) >> 6;
907 switch (fifo_info){
6aa20a22 908 case 0 :
1da177e4
LT
909 /* No FIFO */
910 writew(0x0000, ioaddr + FIFOcfg);
911 break;
6aa20a22 912 case 1 :
1da177e4
LT
913 /* Configure the FIFO for 512K external, 16K used for Tx. */
914 writew(0x0028, ioaddr + FIFOcfg);
915 break;
6aa20a22 916 case 2 :
1da177e4
LT
917 /* Configure the FIFO for 1024 external, 32K used for Tx. */
918 writew(0x004C, ioaddr + FIFOcfg);
919 break;
6aa20a22 920 case 3 :
1da177e4
LT
921 /* Configure the FIFO for 2048 external, 32K used for Tx. */
922 writew(0x006C, ioaddr + FIFOcfg);
923 break;
6aa20a22 924 default :
1da177e4
LT
925 printk(KERN_WARNING "%s: Unsupported external memory config!\n",
926 dev->name);
927 /* Default to no FIFO */
928 writew(0x0000, ioaddr + FIFOcfg);
929 break;
930 }
6aa20a22 931
1da177e4
LT
932 if (dev->if_port == 0)
933 dev->if_port = hmp->default_port;
934
935
936 /* Setting the Rx mode will start the Rx process. */
6aa20a22 937 /* If someone didn't choose a duplex, default to full-duplex */
1da177e4
LT
938 if (hmp->duplex_lock != 1)
939 hmp->mii_if.full_duplex = 1;
940
941 /* always 1, takes no more time to do it */
942 writew(0x0001, ioaddr + RxChecksum);
943#ifdef TX_CHECKSUM
944 writew(0x0001, ioaddr + TxChecksum);
945#else
946 writew(0x0000, ioaddr + TxChecksum);
947#endif
948 writew(0x8000, ioaddr + MACCnfg); /* Soft reset the MAC */
949 writew(0x215F, ioaddr + MACCnfg);
6aa20a22 950 writew(0x000C, ioaddr + FrameGap0);
1da177e4
LT
951 /* WHAT?!?!? Why isn't this documented somewhere? -KDU */
952 writew(0x1018, ioaddr + FrameGap1);
953 /* Why do we enable receives/transmits here? -KDU */
954 writew(0x0780, ioaddr + MACCnfg2); /* Upper 16 bits control LEDs. */
955 /* Enable automatic generation of flow control frames, period 0xffff. */
956 writel(0x0030FFFF, ioaddr + FlowCtrl);
957 writew(MAX_FRAME_SIZE, ioaddr + MaxFrameSize); /* dev->mtu+14 ??? */
958
959 /* Enable legacy links. */
960 writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */
961 /* Initial Link LED to blinking red. */
962 writeb(0x03, ioaddr + LEDCtrl);
963
964 /* Configure interrupt mitigation. This has a great effect on
965 performance, so systems tuning should start here!. */
966
967 rx_int_var = hmp->rx_int_var;
968 tx_int_var = hmp->tx_int_var;
969
970 if (hamachi_debug > 1) {
971 printk("max_tx_latency: %d, max_tx_gap: %d, min_tx_pkt: %d\n",
6aa20a22 972 tx_int_var & 0x00ff, (tx_int_var & 0x00ff00) >> 8,
1da177e4
LT
973 (tx_int_var & 0x00ff0000) >> 16);
974 printk("max_rx_latency: %d, max_rx_gap: %d, min_rx_pkt: %d\n",
6aa20a22 975 rx_int_var & 0x00ff, (rx_int_var & 0x00ff00) >> 8,
1da177e4
LT
976 (rx_int_var & 0x00ff0000) >> 16);
977 printk("rx_int_var: %x, tx_int_var: %x\n", rx_int_var, tx_int_var);
978 }
979
6aa20a22
JG
980 writel(tx_int_var, ioaddr + TxIntrCtrl);
981 writel(rx_int_var, ioaddr + RxIntrCtrl);
1da177e4
LT
982
983 set_rx_mode(dev);
984
985 netif_start_queue(dev);
986
987 /* Enable interrupts by setting the interrupt mask. */
988 writel(0x80878787, ioaddr + InterruptEnable);
989 writew(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
990
991 /* Configure and start the DMA channels. */
992 /* Burst sizes are in the low three bits: size = 4<<(val&7) */
993#if ADDRLEN == 64
994 writew(0x005D, ioaddr + RxDMACtrl); /* 128 dword bursts */
995 writew(0x005D, ioaddr + TxDMACtrl);
996#else
997 writew(0x001D, ioaddr + RxDMACtrl);
998 writew(0x001D, ioaddr + TxDMACtrl);
999#endif
1000 writew(0x0001, ioaddr + RxCmd);
1001
1002 if (hamachi_debug > 2) {
1003 printk(KERN_DEBUG "%s: Done hamachi_open(), status: Rx %x Tx %x.\n",
1004 dev->name, readw(ioaddr + RxStatus), readw(ioaddr + TxStatus));
1005 }
1006 /* Set the timer to check for link beat. */
1007 init_timer(&hmp->timer);
1008 hmp->timer.expires = RUN_AT((24*HZ)/10); /* 2.4 sec. */
1009 hmp->timer.data = (unsigned long)dev;
1010 hmp->timer.function = &hamachi_timer; /* timer handler */
1011 add_timer(&hmp->timer);
1012
1013 return 0;
1014}
1015
1016static inline int hamachi_tx(struct net_device *dev)
1017{
1018 struct hamachi_private *hmp = netdev_priv(dev);
1019
1020 /* Update the dirty pointer until we find an entry that is
1021 still owned by the card */
1022 for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++) {
1023 int entry = hmp->dirty_tx % TX_RING_SIZE;
1024 struct sk_buff *skb;
1025
6aa20a22 1026 if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn))
1da177e4
LT
1027 break;
1028 /* Free the original skb. */
1029 skb = hmp->tx_skbuff[entry];
ddfce6bb 1030 if (skb) {
6aa20a22 1031 pci_unmap_single(hmp->pci_dev,
8e985918
AV
1032 leXX_to_cpu(hmp->tx_ring[entry].addr),
1033 skb->len, PCI_DMA_TODEVICE);
1da177e4
LT
1034 dev_kfree_skb(skb);
1035 hmp->tx_skbuff[entry] = NULL;
1036 }
1037 hmp->tx_ring[entry].status_n_length = 0;
6aa20a22 1038 if (entry >= TX_RING_SIZE-1)
1da177e4 1039 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |=
6aa20a22 1040 cpu_to_le32(DescEndRing);
1da177e4
LT
1041 hmp->stats.tx_packets++;
1042 }
1043
1044 return 0;
1045}
1046
1047static void hamachi_timer(unsigned long data)
1048{
1049 struct net_device *dev = (struct net_device *)data;
1050 struct hamachi_private *hmp = netdev_priv(dev);
1051 void __iomem *ioaddr = hmp->base;
1052 int next_tick = 10*HZ;
1053
1054 if (hamachi_debug > 2) {
1055 printk(KERN_INFO "%s: Hamachi Autonegotiation status %4.4x, LPA "
1056 "%4.4x.\n", dev->name, readw(ioaddr + ANStatus),
1057 readw(ioaddr + ANLinkPartnerAbility));
1058 printk(KERN_INFO "%s: Autonegotiation regs %4.4x %4.4x %4.4x "
1059 "%4.4x %4.4x %4.4x.\n", dev->name,
1060 readw(ioaddr + 0x0e0),
1061 readw(ioaddr + 0x0e2),
1062 readw(ioaddr + 0x0e4),
1063 readw(ioaddr + 0x0e6),
1064 readw(ioaddr + 0x0e8),
1065 readw(ioaddr + 0x0eA));
1066 }
1067 /* We could do something here... nah. */
1068 hmp->timer.expires = RUN_AT(next_tick);
1069 add_timer(&hmp->timer);
1070}
1071
1072static void hamachi_tx_timeout(struct net_device *dev)
1073{
1074 int i;
1075 struct hamachi_private *hmp = netdev_priv(dev);
1076 void __iomem *ioaddr = hmp->base;
1077
1078 printk(KERN_WARNING "%s: Hamachi transmit timed out, status %8.8x,"
1079 " resetting...\n", dev->name, (int)readw(ioaddr + TxStatus));
1080
1081 {
1da177e4
LT
1082 printk(KERN_DEBUG " Rx ring %p: ", hmp->rx_ring);
1083 for (i = 0; i < RX_RING_SIZE; i++)
ad361c98
JP
1084 printk(KERN_CONT " %8.8x",
1085 le32_to_cpu(hmp->rx_ring[i].status_n_length));
1086 printk(KERN_CONT "\n");
1087 printk(KERN_DEBUG" Tx ring %p: ", hmp->tx_ring);
1da177e4 1088 for (i = 0; i < TX_RING_SIZE; i++)
ad361c98
JP
1089 printk(KERN_CONT " %4.4x",
1090 le32_to_cpu(hmp->tx_ring[i].status_n_length));
1091 printk(KERN_CONT "\n");
1da177e4
LT
1092 }
1093
6aa20a22 1094 /* Reinit the hardware and make sure the Rx and Tx processes
1da177e4
LT
1095 are up and running.
1096 */
1097 dev->if_port = 0;
1098 /* The right way to do Reset. -KDU
1099 * -Clear OWN bit in all Rx/Tx descriptors
1100 * -Wait 50 uS for channels to go idle
1101 * -Turn off MAC receiver
1102 * -Issue Reset
1103 */
6aa20a22 1104
1da177e4
LT
1105 for (i = 0; i < RX_RING_SIZE; i++)
1106 hmp->rx_ring[i].status_n_length &= cpu_to_le32(~DescOwn);
1107
1108 /* Presume that all packets in the Tx queue are gone if we have to
1109 * re-init the hardware.
1110 */
1111 for (i = 0; i < TX_RING_SIZE; i++){
1112 struct sk_buff *skb;
1113
1114 if (i >= TX_RING_SIZE - 1)
8e985918
AV
1115 hmp->tx_ring[i].status_n_length =
1116 cpu_to_le32(DescEndRing) |
1117 (hmp->tx_ring[i].status_n_length &
1118 cpu_to_le32(0x0000ffff));
6aa20a22 1119 else
8e985918 1120 hmp->tx_ring[i].status_n_length &= cpu_to_le32(0x0000ffff);
1da177e4
LT
1121 skb = hmp->tx_skbuff[i];
1122 if (skb){
8e985918 1123 pci_unmap_single(hmp->pci_dev, leXX_to_cpu(hmp->tx_ring[i].addr),
1da177e4
LT
1124 skb->len, PCI_DMA_TODEVICE);
1125 dev_kfree_skb(skb);
1126 hmp->tx_skbuff[i] = NULL;
1127 }
1128 }
1129
1130 udelay(60); /* Sleep 60 us just for safety sake */
1131 writew(0x0002, ioaddr + RxCmd); /* STOP Rx */
6aa20a22
JG
1132
1133 writeb(0x01, ioaddr + ChipReset); /* Reinit the hardware */
1da177e4
LT
1134
1135 hmp->tx_full = 0;
1136 hmp->cur_rx = hmp->cur_tx = 0;
1137 hmp->dirty_rx = hmp->dirty_tx = 0;
1138 /* Rx packets are also presumed lost; however, we need to make sure a
1139 * ring of buffers is in tact. -KDU
6aa20a22 1140 */
1da177e4
LT
1141 for (i = 0; i < RX_RING_SIZE; i++){
1142 struct sk_buff *skb = hmp->rx_skbuff[i];
1143
1144 if (skb){
8e985918
AV
1145 pci_unmap_single(hmp->pci_dev,
1146 leXX_to_cpu(hmp->rx_ring[i].addr),
1da177e4
LT
1147 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1148 dev_kfree_skb(skb);
1149 hmp->rx_skbuff[i] = NULL;
1150 }
1151 }
1152 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1153 for (i = 0; i < RX_RING_SIZE; i++) {
8eb60131 1154 struct sk_buff *skb = netdev_alloc_skb(dev, hmp->rx_buf_sz);
1da177e4
LT
1155 hmp->rx_skbuff[i] = skb;
1156 if (skb == NULL)
1157 break;
8eb60131 1158
1da177e4 1159 skb_reserve(skb, 2); /* 16 byte align the IP header. */
6aa20a22 1160 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
689be439 1161 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
6aa20a22 1162 hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn |
1da177e4
LT
1163 DescEndPacket | DescIntr | (hmp->rx_buf_sz - 2));
1164 }
1165 hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1166 /* Mark the last entry as wrapping the ring. */
1167 hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1168
1169 /* Trigger an immediate transmit demand. */
cdd0db05 1170 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT
1171 hmp->stats.tx_errors++;
1172
1173 /* Restart the chip's Tx/Rx processes . */
1174 writew(0x0002, ioaddr + TxCmd); /* STOP Tx */
1175 writew(0x0001, ioaddr + TxCmd); /* START Tx */
1176 writew(0x0001, ioaddr + RxCmd); /* START Rx */
1177
1178 netif_wake_queue(dev);
1179}
1180
1181
1182/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1183static void hamachi_init_ring(struct net_device *dev)
1184{
1185 struct hamachi_private *hmp = netdev_priv(dev);
1186 int i;
1187
1188 hmp->tx_full = 0;
1189 hmp->cur_rx = hmp->cur_tx = 0;
1190 hmp->dirty_rx = hmp->dirty_tx = 0;
1191
1da177e4 1192 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
6aa20a22
JG
1193 * card needs room to do 8 byte alignment, +2 so we can reserve
1194 * the first 2 bytes, and +16 gets room for the status word from the
1da177e4
LT
1195 * card. -KDU
1196 */
6aa20a22 1197 hmp->rx_buf_sz = (dev->mtu <= 1492 ? PKT_BUF_SZ :
1da177e4
LT
1198 (((dev->mtu+26+7) & ~7) + 2 + 16));
1199
1200 /* Initialize all Rx descriptors. */
1201 for (i = 0; i < RX_RING_SIZE; i++) {
1202 hmp->rx_ring[i].status_n_length = 0;
1203 hmp->rx_skbuff[i] = NULL;
1204 }
1205 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1206 for (i = 0; i < RX_RING_SIZE; i++) {
1207 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz);
1208 hmp->rx_skbuff[i] = skb;
1209 if (skb == NULL)
1210 break;
1211 skb->dev = dev; /* Mark as being used by this device. */
1212 skb_reserve(skb, 2); /* 16 byte align the IP header. */
6aa20a22 1213 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
689be439 1214 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4 1215 /* -2 because it doesn't REALLY have that first 2 bytes -KDU */
6aa20a22 1216 hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn |
1da177e4
LT
1217 DescEndPacket | DescIntr | (hmp->rx_buf_sz -2));
1218 }
1219 hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1220 hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1221
1222 for (i = 0; i < TX_RING_SIZE; i++) {
1223 hmp->tx_skbuff[i] = NULL;
1224 hmp->tx_ring[i].status_n_length = 0;
1225 }
1226 /* Mark the last entry of the ring */
1227 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1228
1229 return;
1230}
1231
1232
1233#ifdef TX_CHECKSUM
1234#define csum_add(it, val) \
1235do { \
1236 it += (u16) (val); \
1237 if (it & 0xffff0000) { \
1238 it &= 0xffff; \
1239 ++it; \
1240 } \
1241} while (0)
1242 /* printk("add %04x --> %04x\n", val, it); \ */
1243
1244/* uh->len already network format, do not swap */
1245#define pseudo_csum_udp(sum,ih,uh) do { \
1246 sum = 0; \
1247 csum_add(sum, (ih)->saddr >> 16); \
1248 csum_add(sum, (ih)->saddr & 0xffff); \
1249 csum_add(sum, (ih)->daddr >> 16); \
1250 csum_add(sum, (ih)->daddr & 0xffff); \
09640e63 1251 csum_add(sum, cpu_to_be16(IPPROTO_UDP)); \
1da177e4
LT
1252 csum_add(sum, (uh)->len); \
1253} while (0)
1254
1255/* swap len */
1256#define pseudo_csum_tcp(sum,ih,len) do { \
1257 sum = 0; \
1258 csum_add(sum, (ih)->saddr >> 16); \
1259 csum_add(sum, (ih)->saddr & 0xffff); \
1260 csum_add(sum, (ih)->daddr >> 16); \
1261 csum_add(sum, (ih)->daddr & 0xffff); \
09640e63 1262 csum_add(sum, cpu_to_be16(IPPROTO_TCP)); \
1da177e4
LT
1263 csum_add(sum, htons(len)); \
1264} while (0)
1265#endif
1266
61357325
SH
1267static netdev_tx_t hamachi_start_xmit(struct sk_buff *skb,
1268 struct net_device *dev)
1da177e4
LT
1269{
1270 struct hamachi_private *hmp = netdev_priv(dev);
1271 unsigned entry;
1272 u16 status;
1273
6aa20a22 1274 /* Ok, now make sure that the queue has space before trying to
1da177e4
LT
1275 add another skbuff. if we return non-zero the scheduler
1276 should interpret this as a queue full and requeue the buffer
1277 for later.
1278 */
1279 if (hmp->tx_full) {
1280 /* We should NEVER reach this point -KDU */
1281 printk(KERN_WARNING "%s: Hamachi transmit queue full at slot %d.\n",dev->name, hmp->cur_tx);
1282
1283 /* Wake the potentially-idle transmit channel. */
1284 /* If we don't need to read status, DON'T -KDU */
1285 status=readw(hmp->base + TxStatus);
1286 if( !(status & 0x0001) || (status & 0x0002))
1287 writew(0x0001, hmp->base + TxCmd);
5b548140 1288 return NETDEV_TX_BUSY;
6aa20a22 1289 }
1da177e4
LT
1290
1291 /* Caution: the write order is important here, set the field
1292 with the "ownership" bits last. */
1293
1294 /* Calculate the next Tx descriptor entry. */
1295 entry = hmp->cur_tx % TX_RING_SIZE;
1296
1297 hmp->tx_skbuff[entry] = skb;
1298
1299#ifdef TX_CHECKSUM
1300 {
1301 /* tack on checksum tag */
1302 u32 tagval = 0;
1303 struct ethhdr *eh = (struct ethhdr *)skb->data;
09640e63 1304 if (eh->h_proto == cpu_to_be16(ETH_P_IP)) {
1da177e4
LT
1305 struct iphdr *ih = (struct iphdr *)((char *)eh + ETH_HLEN);
1306 if (ih->protocol == IPPROTO_UDP) {
1307 struct udphdr *uh
1308 = (struct udphdr *)((char *)ih + ih->ihl*4);
1309 u32 offset = ((unsigned char *)uh + 6) - skb->data;
1310 u32 pseudo;
1311 pseudo_csum_udp(pseudo, ih, uh);
1312 pseudo = htons(pseudo);
1313 printk("udp cksum was %04x, sending pseudo %04x\n",
1314 uh->check, pseudo);
1315 uh->check = 0; /* zero out uh->check before card calc */
1316 /*
1317 * start at 14 (skip ethhdr), store at offset (uh->check),
1318 * use pseudo value given.
1319 */
1320 tagval = (14 << 24) | (offset << 16) | pseudo;
1321 } else if (ih->protocol == IPPROTO_TCP) {
1322 printk("tcp, no auto cksum\n");
1323 }
1324 }
1325 *(u32 *)skb_push(skb, 8) = tagval;
1326 }
1327#endif
1328
6aa20a22 1329 hmp->tx_ring[entry].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
1da177e4 1330 skb->data, skb->len, PCI_DMA_TODEVICE));
6aa20a22 1331
1da177e4
LT
1332 /* Hmmmm, could probably put a DescIntr on these, but the way
1333 the driver is currently coded makes Tx interrupts unnecessary
1334 since the clearing of the Tx ring is handled by the start_xmit
1335 routine. This organization helps mitigate the interrupts a
1336 bit and probably renders the max_tx_latency param useless.
6aa20a22 1337
1da177e4
LT
1338 Update: Putting a DescIntr bit on all of the descriptors and
1339 mitigating interrupt frequency with the tx_min_pkt parameter. -KDU
1340 */
1341 if (entry >= TX_RING_SIZE-1) /* Wrap ring */
1342 hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn |
1343 DescEndPacket | DescEndRing | DescIntr | skb->len);
1344 else
1345 hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn |
1346 DescEndPacket | DescIntr | skb->len);
1347 hmp->cur_tx++;
1348
1349 /* Non-x86 Todo: explicitly flush cache lines here. */
1350
1351 /* Wake the potentially-idle transmit channel. */
1352 /* If we don't need to read status, DON'T -KDU */
1353 status=readw(hmp->base + TxStatus);
1354 if( !(status & 0x0001) || (status & 0x0002))
1355 writew(0x0001, hmp->base + TxCmd);
1356
1357 /* Immediately before returning, let's clear as many entries as we can. */
1358 hamachi_tx(dev);
1359
1360 /* We should kick the bottom half here, since we are not accepting
1361 * interrupts with every packet. i.e. realize that Gigabit ethernet
1362 * can transmit faster than ordinary machines can load packets;
1363 * hence, any packet that got put off because we were in the transmit
1364 * routine should IMMEDIATELY get a chance to be re-queued. -KDU
1365 */
6aa20a22 1366 if ((hmp->cur_tx - hmp->dirty_tx) < (TX_RING_SIZE - 4))
1da177e4
LT
1367 netif_wake_queue(dev); /* Typical path */
1368 else {
1369 hmp->tx_full = 1;
1370 netif_stop_queue(dev);
1371 }
1da177e4
LT
1372
1373 if (hamachi_debug > 4) {
1374 printk(KERN_DEBUG "%s: Hamachi transmit frame #%d queued in slot %d.\n",
1375 dev->name, hmp->cur_tx, entry);
1376 }
6ed10654 1377 return NETDEV_TX_OK;
1da177e4
LT
1378}
1379
1380/* The interrupt handler does all of the Rx thread work and cleans up
1381 after the Tx thread. */
7d12e780 1382static irqreturn_t hamachi_interrupt(int irq, void *dev_instance)
1da177e4
LT
1383{
1384 struct net_device *dev = dev_instance;
1385 struct hamachi_private *hmp = netdev_priv(dev);
1386 void __iomem *ioaddr = hmp->base;
1387 long boguscnt = max_interrupt_work;
1388 int handled = 0;
1389
1390#ifndef final_version /* Can never occur. */
1391 if (dev == NULL) {
1392 printk (KERN_ERR "hamachi_interrupt(): irq %d for unknown device.\n", irq);
1393 return IRQ_NONE;
1394 }
1395#endif
1396
1397 spin_lock(&hmp->lock);
1398
1399 do {
1400 u32 intr_status = readl(ioaddr + InterruptClear);
1401
1402 if (hamachi_debug > 4)
1403 printk(KERN_DEBUG "%s: Hamachi interrupt, status %4.4x.\n",
1404 dev->name, intr_status);
1405
1406 if (intr_status == 0)
1407 break;
1408
1409 handled = 1;
1410
1411 if (intr_status & IntrRxDone)
1412 hamachi_rx(dev);
1413
1414 if (intr_status & IntrTxDone){
1415 /* This code should RARELY need to execute. After all, this is
1416 * a gigabit link, it should consume packets as fast as we put
1417 * them in AND we clear the Tx ring in hamachi_start_xmit().
6aa20a22 1418 */
1da177e4
LT
1419 if (hmp->tx_full){
1420 for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++){
1421 int entry = hmp->dirty_tx % TX_RING_SIZE;
1422 struct sk_buff *skb;
1423
6aa20a22 1424 if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn))
1da177e4
LT
1425 break;
1426 skb = hmp->tx_skbuff[entry];
1427 /* Free the original skb. */
1428 if (skb){
6aa20a22 1429 pci_unmap_single(hmp->pci_dev,
8e985918 1430 leXX_to_cpu(hmp->tx_ring[entry].addr),
1da177e4
LT
1431 skb->len,
1432 PCI_DMA_TODEVICE);
1433 dev_kfree_skb_irq(skb);
1434 hmp->tx_skbuff[entry] = NULL;
1435 }
1436 hmp->tx_ring[entry].status_n_length = 0;
6aa20a22
JG
1437 if (entry >= TX_RING_SIZE-1)
1438 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |=
1da177e4
LT
1439 cpu_to_le32(DescEndRing);
1440 hmp->stats.tx_packets++;
1441 }
1442 if (hmp->cur_tx - hmp->dirty_tx < TX_RING_SIZE - 4){
1443 /* The ring is no longer full */
1444 hmp->tx_full = 0;
1445 netif_wake_queue(dev);
1446 }
1447 } else {
1448 netif_wake_queue(dev);
1449 }
1450 }
1451
1452
1453 /* Abnormal error summary/uncommon events handlers. */
1454 if (intr_status &
1455 (IntrTxPCIFault | IntrTxPCIErr | IntrRxPCIFault | IntrRxPCIErr |
1456 LinkChange | NegotiationChange | StatsMax))
1457 hamachi_error(dev, intr_status);
1458
1459 if (--boguscnt < 0) {
1460 printk(KERN_WARNING "%s: Too much work at interrupt, status=0x%4.4x.\n",
1461 dev->name, intr_status);
1462 break;
1463 }
1464 } while (1);
1465
1466 if (hamachi_debug > 3)
1467 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1468 dev->name, readl(ioaddr + IntrStatus));
1469
1470#ifndef final_version
1471 /* Code that should never be run! Perhaps remove after testing.. */
1472 {
1473 static int stopit = 10;
1474 if (dev->start == 0 && --stopit < 0) {
1475 printk(KERN_ERR "%s: Emergency stop, looping startup interrupt.\n",
1476 dev->name);
1477 free_irq(irq, dev);
1478 }
1479 }
1480#endif
1481
1482 spin_unlock(&hmp->lock);
1483 return IRQ_RETVAL(handled);
1484}
1485
1486/* This routine is logically part of the interrupt handler, but separated
1487 for clarity and better register allocation. */
1488static int hamachi_rx(struct net_device *dev)
1489{
1490 struct hamachi_private *hmp = netdev_priv(dev);
1491 int entry = hmp->cur_rx % RX_RING_SIZE;
1492 int boguscnt = (hmp->dirty_rx + RX_RING_SIZE) - hmp->cur_rx;
1493
1494 if (hamachi_debug > 4) {
1495 printk(KERN_DEBUG " In hamachi_rx(), entry %d status %4.4x.\n",
1496 entry, hmp->rx_ring[entry].status_n_length);
1497 }
1498
1499 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1500 while (1) {
1501 struct hamachi_desc *desc = &(hmp->rx_ring[entry]);
1502 u32 desc_status = le32_to_cpu(desc->status_n_length);
1503 u16 data_size = desc_status; /* Implicit truncate */
6aa20a22 1504 u8 *buf_addr;
1da177e4 1505 s32 frame_status;
6aa20a22 1506
1da177e4
LT
1507 if (desc_status & DescOwn)
1508 break;
1509 pci_dma_sync_single_for_cpu(hmp->pci_dev,
8e985918 1510 leXX_to_cpu(desc->addr),
1da177e4
LT
1511 hmp->rx_buf_sz,
1512 PCI_DMA_FROMDEVICE);
689be439 1513 buf_addr = (u8 *) hmp->rx_skbuff[entry]->data;
6caf52a4 1514 frame_status = get_unaligned_le32(&(buf_addr[data_size - 12]));
1da177e4
LT
1515 if (hamachi_debug > 4)
1516 printk(KERN_DEBUG " hamachi_rx() status was %8.8x.\n",
1517 frame_status);
1518 if (--boguscnt < 0)
1519 break;
1520 if ( ! (desc_status & DescEndPacket)) {
1521 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1522 "multiple buffers, entry %#x length %d status %4.4x!\n",
1523 dev->name, hmp->cur_rx, data_size, desc_status);
1524 printk(KERN_WARNING "%s: Oversized Ethernet frame %p vs %p.\n",
1525 dev->name, desc, &hmp->rx_ring[hmp->cur_rx % RX_RING_SIZE]);
1526 printk(KERN_WARNING "%s: Oversized Ethernet frame -- next status %x/%x last status %x.\n",
1527 dev->name,
8e985918
AV
1528 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length) & 0xffff0000,
1529 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length) & 0x0000ffff,
1530 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx-1) % RX_RING_SIZE].status_n_length));
1da177e4
LT
1531 hmp->stats.rx_length_errors++;
1532 } /* else Omit for prototype errata??? */
1533 if (frame_status & 0x00380000) {
1534 /* There was an error. */
1535 if (hamachi_debug > 2)
1536 printk(KERN_DEBUG " hamachi_rx() Rx error was %8.8x.\n",
1537 frame_status);
1538 hmp->stats.rx_errors++;
1539 if (frame_status & 0x00600000) hmp->stats.rx_length_errors++;
1540 if (frame_status & 0x00080000) hmp->stats.rx_frame_errors++;
1541 if (frame_status & 0x00100000) hmp->stats.rx_crc_errors++;
1542 if (frame_status < 0) hmp->stats.rx_dropped++;
1543 } else {
1544 struct sk_buff *skb;
1545 /* Omit CRC */
6aa20a22 1546 u16 pkt_len = (frame_status & 0x07ff) - 4;
1da177e4
LT
1547#ifdef RX_CHECKSUM
1548 u32 pfck = *(u32 *) &buf_addr[data_size - 8];
1549#endif
1550
1551
1552#ifndef final_version
1553 if (hamachi_debug > 4)
1554 printk(KERN_DEBUG " hamachi_rx() normal Rx pkt length %d"
1555 " of %d, bogus_cnt %d.\n",
1556 pkt_len, data_size, boguscnt);
1557 if (hamachi_debug > 5)
1558 printk(KERN_DEBUG"%s: rx status %8.8x %8.8x %8.8x %8.8x %8.8x.\n",
1559 dev->name,
1560 *(s32*)&(buf_addr[data_size - 20]),
1561 *(s32*)&(buf_addr[data_size - 16]),
1562 *(s32*)&(buf_addr[data_size - 12]),
1563 *(s32*)&(buf_addr[data_size - 8]),
1564 *(s32*)&(buf_addr[data_size - 4]));
1565#endif
1566 /* Check if the packet is long enough to accept without copying
1567 to a minimally-sized skbuff. */
1568 if (pkt_len < rx_copybreak
1569 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1570#ifdef RX_CHECKSUM
1571 printk(KERN_ERR "%s: rx_copybreak non-zero "
1572 "not good with RX_CHECKSUM\n", dev->name);
1573#endif
1da177e4
LT
1574 skb_reserve(skb, 2); /* 16 byte align the IP header */
1575 pci_dma_sync_single_for_cpu(hmp->pci_dev,
8e985918 1576 leXX_to_cpu(hmp->rx_ring[entry].addr),
1da177e4
LT
1577 hmp->rx_buf_sz,
1578 PCI_DMA_FROMDEVICE);
1579 /* Call copy + cksum if available. */
1580#if 1 || USE_IP_COPYSUM
8c7b7faa
DM
1581 skb_copy_to_linear_data(skb,
1582 hmp->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT
1583 skb_put(skb, pkt_len);
1584#else
1585 memcpy(skb_put(skb, pkt_len), hmp->rx_ring_dma
1586 + entry*sizeof(*desc), pkt_len);
1587#endif
1588 pci_dma_sync_single_for_device(hmp->pci_dev,
8e985918 1589 leXX_to_cpu(hmp->rx_ring[entry].addr),
1da177e4
LT
1590 hmp->rx_buf_sz,
1591 PCI_DMA_FROMDEVICE);
1592 } else {
6aa20a22 1593 pci_unmap_single(hmp->pci_dev,
8e985918 1594 leXX_to_cpu(hmp->rx_ring[entry].addr),
1da177e4
LT
1595 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1596 skb_put(skb = hmp->rx_skbuff[entry], pkt_len);
1597 hmp->rx_skbuff[entry] = NULL;
1598 }
1599 skb->protocol = eth_type_trans(skb, dev);
1600
1601
1602#ifdef RX_CHECKSUM
1603 /* TCP or UDP on ipv4, DIX encoding */
1604 if (pfck>>24 == 0x91 || pfck>>24 == 0x51) {
1605 struct iphdr *ih = (struct iphdr *) skb->data;
1606 /* Check that IP packet is at least 46 bytes, otherwise,
1607 * there may be pad bytes included in the hardware checksum.
1608 * This wouldn't happen if everyone padded with 0.
1609 */
1610 if (ntohs(ih->tot_len) >= 46){
1611 /* don't worry about frags */
09640e63 1612 if (!(ih->frag_off & cpu_to_be16(IP_MF|IP_OFFSET))) {
1da177e4
LT
1613 u32 inv = *(u32 *) &buf_addr[data_size - 16];
1614 u32 *p = (u32 *) &buf_addr[data_size - 20];
1615 register u32 crc, p_r, p_r1;
1616
1617 if (inv & 4) {
1618 inv &= ~4;
1619 --p;
1620 }
1621 p_r = *p;
1622 p_r1 = *(p-1);
1623 switch (inv) {
6aa20a22 1624 case 0:
1da177e4
LT
1625 crc = (p_r & 0xffff) + (p_r >> 16);
1626 break;
6aa20a22 1627 case 1:
1da177e4 1628 crc = (p_r >> 16) + (p_r & 0xffff)
6aa20a22 1629 + (p_r1 >> 16 & 0xff00);
1da177e4 1630 break;
6aa20a22
JG
1631 case 2:
1632 crc = p_r + (p_r1 >> 16);
1da177e4 1633 break;
6aa20a22
JG
1634 case 3:
1635 crc = p_r + (p_r1 & 0xff00) + (p_r1 >> 16);
1da177e4
LT
1636 break;
1637 default: /*NOTREACHED*/ crc = 0;
1638 }
1639 if (crc & 0xffff0000) {
1640 crc &= 0xffff;
1641 ++crc;
1642 }
1643 /* tcp/udp will add in pseudo */
1644 skb->csum = ntohs(pfck & 0xffff);
1645 if (skb->csum > crc)
1646 skb->csum -= crc;
1647 else
1648 skb->csum += (~crc & 0xffff);
1649 /*
1650 * could do the pseudo myself and return
1651 * CHECKSUM_UNNECESSARY
1652 */
84fa7933 1653 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4 1654 }
6aa20a22 1655 }
1da177e4
LT
1656 }
1657#endif /* RX_CHECKSUM */
1658
1659 netif_rx(skb);
1da177e4
LT
1660 hmp->stats.rx_packets++;
1661 }
1662 entry = (++hmp->cur_rx) % RX_RING_SIZE;
1663 }
1664
1665 /* Refill the Rx ring buffers. */
1666 for (; hmp->cur_rx - hmp->dirty_rx > 0; hmp->dirty_rx++) {
1667 struct hamachi_desc *desc;
1668
1669 entry = hmp->dirty_rx % RX_RING_SIZE;
1670 desc = &(hmp->rx_ring[entry]);
1671 if (hmp->rx_skbuff[entry] == NULL) {
1672 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz);
1673
1674 hmp->rx_skbuff[entry] = skb;
1675 if (skb == NULL)
1676 break; /* Better luck next round. */
1677 skb->dev = dev; /* Mark as being used by this device. */
1678 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
6aa20a22 1679 desc->addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
689be439 1680 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4
LT
1681 }
1682 desc->status_n_length = cpu_to_le32(hmp->rx_buf_sz);
1683 if (entry >= RX_RING_SIZE-1)
6aa20a22 1684 desc->status_n_length |= cpu_to_le32(DescOwn |
1da177e4
LT
1685 DescEndPacket | DescEndRing | DescIntr);
1686 else
6aa20a22 1687 desc->status_n_length |= cpu_to_le32(DescOwn |
1da177e4
LT
1688 DescEndPacket | DescIntr);
1689 }
1690
1691 /* Restart Rx engine if stopped. */
1692 /* If we don't need to check status, don't. -KDU */
1693 if (readw(hmp->base + RxStatus) & 0x0002)
1694 writew(0x0001, hmp->base + RxCmd);
1695
1696 return 0;
1697}
1698
1699/* This is more properly named "uncommon interrupt events", as it covers more
1700 than just errors. */
1701static void hamachi_error(struct net_device *dev, int intr_status)
1702{
1703 struct hamachi_private *hmp = netdev_priv(dev);
1704 void __iomem *ioaddr = hmp->base;
1705
1706 if (intr_status & (LinkChange|NegotiationChange)) {
1707 if (hamachi_debug > 1)
1708 printk(KERN_INFO "%s: Link changed: AutoNegotiation Ctrl"
1709 " %4.4x, Status %4.4x %4.4x Intr status %4.4x.\n",
1710 dev->name, readw(ioaddr + 0x0E0), readw(ioaddr + 0x0E2),
1711 readw(ioaddr + ANLinkPartnerAbility),
1712 readl(ioaddr + IntrStatus));
1713 if (readw(ioaddr + ANStatus) & 0x20)
1714 writeb(0x01, ioaddr + LEDCtrl);
1715 else
1716 writeb(0x03, ioaddr + LEDCtrl);
1717 }
1718 if (intr_status & StatsMax) {
1719 hamachi_get_stats(dev);
1720 /* Read the overflow bits to clear. */
1721 readl(ioaddr + 0x370);
1722 readl(ioaddr + 0x3F0);
1723 }
1724 if ((intr_status & ~(LinkChange|StatsMax|NegotiationChange|IntrRxDone|IntrTxDone))
1725 && hamachi_debug)
1726 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1727 dev->name, intr_status);
1728 /* Hmmmmm, it's not clear how to recover from PCI faults. */
1729 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1730 hmp->stats.tx_fifo_errors++;
1731 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1732 hmp->stats.rx_fifo_errors++;
1733}
1734
1735static int hamachi_close(struct net_device *dev)
1736{
1737 struct hamachi_private *hmp = netdev_priv(dev);
1738 void __iomem *ioaddr = hmp->base;
1739 struct sk_buff *skb;
1740 int i;
1741
1742 netif_stop_queue(dev);
1743
1744 if (hamachi_debug > 1) {
1745 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x Rx %4.4x Int %2.2x.\n",
1746 dev->name, readw(ioaddr + TxStatus),
1747 readw(ioaddr + RxStatus), readl(ioaddr + IntrStatus));
1748 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1749 dev->name, hmp->cur_tx, hmp->dirty_tx, hmp->cur_rx, hmp->dirty_rx);
1750 }
1751
1752 /* Disable interrupts by clearing the interrupt mask. */
1753 writel(0x0000, ioaddr + InterruptEnable);
1754
1755 /* Stop the chip's Tx and Rx processes. */
1756 writel(2, ioaddr + RxCmd);
1757 writew(2, ioaddr + TxCmd);
1758
1759#ifdef __i386__
1760 if (hamachi_debug > 2) {
ad361c98 1761 printk(KERN_DEBUG " Tx ring at %8.8x:\n",
1da177e4
LT
1762 (int)hmp->tx_ring_dma);
1763 for (i = 0; i < TX_RING_SIZE; i++)
ad361c98 1764 printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x.\n",
1da177e4
LT
1765 readl(ioaddr + TxCurPtr) == (long)&hmp->tx_ring[i] ? '>' : ' ',
1766 i, hmp->tx_ring[i].status_n_length, hmp->tx_ring[i].addr);
ad361c98 1767 printk(KERN_DEBUG " Rx ring %8.8x:\n",
1da177e4
LT
1768 (int)hmp->rx_ring_dma);
1769 for (i = 0; i < RX_RING_SIZE; i++) {
1770 printk(KERN_DEBUG " %c #%d desc. %4.4x %8.8x\n",
1771 readl(ioaddr + RxCurPtr) == (long)&hmp->rx_ring[i] ? '>' : ' ',
1772 i, hmp->rx_ring[i].status_n_length, hmp->rx_ring[i].addr);
1773 if (hamachi_debug > 6) {
689be439 1774 if (*(u8*)hmp->rx_skbuff[i]->data != 0x69) {
1da177e4 1775 u16 *addr = (u16 *)
689be439 1776 hmp->rx_skbuff[i]->data;
1da177e4 1777 int j;
ad361c98 1778 printk(KERN_DEBUG "Addr: ");
1da177e4
LT
1779 for (j = 0; j < 0x50; j++)
1780 printk(" %4.4x", addr[j]);
1781 printk("\n");
1782 }
1783 }
1784 }
1785 }
1786#endif /* __i386__ debugging only */
1787
1788 free_irq(dev->irq, dev);
1789
1790 del_timer_sync(&hmp->timer);
1791
1792 /* Free all the skbuffs in the Rx queue. */
1793 for (i = 0; i < RX_RING_SIZE; i++) {
1794 skb = hmp->rx_skbuff[i];
1795 hmp->rx_ring[i].status_n_length = 0;
1da177e4 1796 if (skb) {
6aa20a22 1797 pci_unmap_single(hmp->pci_dev,
8e985918
AV
1798 leXX_to_cpu(hmp->rx_ring[i].addr),
1799 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1da177e4
LT
1800 dev_kfree_skb(skb);
1801 hmp->rx_skbuff[i] = NULL;
1802 }
8e985918 1803 hmp->rx_ring[i].addr = cpu_to_leXX(0xBADF00D0); /* An invalid address. */
1da177e4
LT
1804 }
1805 for (i = 0; i < TX_RING_SIZE; i++) {
1806 skb = hmp->tx_skbuff[i];
1807 if (skb) {
6aa20a22 1808 pci_unmap_single(hmp->pci_dev,
8e985918
AV
1809 leXX_to_cpu(hmp->tx_ring[i].addr),
1810 skb->len, PCI_DMA_TODEVICE);
1da177e4
LT
1811 dev_kfree_skb(skb);
1812 hmp->tx_skbuff[i] = NULL;
1813 }
1814 }
1815
1816 writeb(0x00, ioaddr + LEDCtrl);
1817
1818 return 0;
1819}
1820
1821static struct net_device_stats *hamachi_get_stats(struct net_device *dev)
1822{
1823 struct hamachi_private *hmp = netdev_priv(dev);
1824 void __iomem *ioaddr = hmp->base;
1825
1826 /* We should lock this segment of code for SMP eventually, although
1827 the vulnerability window is very small and statistics are
1828 non-critical. */
1829 /* Ok, what goes here? This appears to be stuck at 21 packets
1830 according to ifconfig. It does get incremented in hamachi_tx(),
1831 so I think I'll comment it out here and see if better things
1832 happen.
6aa20a22 1833 */
1da177e4
LT
1834 /* hmp->stats.tx_packets = readl(ioaddr + 0x000); */
1835
1836 hmp->stats.rx_bytes = readl(ioaddr + 0x330); /* Total Uni+Brd+Multi */
1837 hmp->stats.tx_bytes = readl(ioaddr + 0x3B0); /* Total Uni+Brd+Multi */
1838 hmp->stats.multicast = readl(ioaddr + 0x320); /* Multicast Rx */
1839
1840 hmp->stats.rx_length_errors = readl(ioaddr + 0x368); /* Over+Undersized */
1841 hmp->stats.rx_over_errors = readl(ioaddr + 0x35C); /* Jabber */
1842 hmp->stats.rx_crc_errors = readl(ioaddr + 0x360); /* Jabber */
1843 hmp->stats.rx_frame_errors = readl(ioaddr + 0x364); /* Symbol Errs */
1844 hmp->stats.rx_missed_errors = readl(ioaddr + 0x36C); /* Dropped */
1845
1846 return &hmp->stats;
1847}
1848
1849static void set_rx_mode(struct net_device *dev)
1850{
1851 struct hamachi_private *hmp = netdev_priv(dev);
1852 void __iomem *ioaddr = hmp->base;
1853
1854 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT
1855 writew(0x000F, ioaddr + AddrMode);
1856 } else if ((dev->mc_count > 63) || (dev->flags & IFF_ALLMULTI)) {
1857 /* Too many to match, or accept all multicasts. */
1858 writew(0x000B, ioaddr + AddrMode);
1859 } else if (dev->mc_count > 0) { /* Must use the CAM filter. */
1860 struct dev_mc_list *mclist;
1861 int i;
1862 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1863 i++, mclist = mclist->next) {
1864 writel(*(u32*)(mclist->dmi_addr), ioaddr + 0x100 + i*8);
1865 writel(0x20000 | (*(u16*)&mclist->dmi_addr[4]),
1866 ioaddr + 0x104 + i*8);
1867 }
1868 /* Clear remaining entries. */
1869 for (; i < 64; i++)
1870 writel(0, ioaddr + 0x104 + i*8);
1871 writew(0x0003, ioaddr + AddrMode);
1872 } else { /* Normal, unicast/broadcast-only mode. */
1873 writew(0x0001, ioaddr + AddrMode);
1874 }
1875}
1876
1877static int check_if_running(struct net_device *dev)
1878{
1879 if (!netif_running(dev))
1880 return -EINVAL;
1881 return 0;
1882}
1883
1884static void hamachi_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1885{
1886 struct hamachi_private *np = netdev_priv(dev);
1887 strcpy(info->driver, DRV_NAME);
1888 strcpy(info->version, DRV_VERSION);
1889 strcpy(info->bus_info, pci_name(np->pci_dev));
1890}
1891
1892static int hamachi_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1893{
1894 struct hamachi_private *np = netdev_priv(dev);
1895 spin_lock_irq(&np->lock);
1896 mii_ethtool_gset(&np->mii_if, ecmd);
1897 spin_unlock_irq(&np->lock);
1898 return 0;
1899}
1900
1901static int hamachi_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1902{
1903 struct hamachi_private *np = netdev_priv(dev);
1904 int res;
1905 spin_lock_irq(&np->lock);
1906 res = mii_ethtool_sset(&np->mii_if, ecmd);
1907 spin_unlock_irq(&np->lock);
1908 return res;
1909}
1910
1911static int hamachi_nway_reset(struct net_device *dev)
1912{
1913 struct hamachi_private *np = netdev_priv(dev);
1914 return mii_nway_restart(&np->mii_if);
1915}
1916
1917static u32 hamachi_get_link(struct net_device *dev)
1918{
1919 struct hamachi_private *np = netdev_priv(dev);
1920 return mii_link_ok(&np->mii_if);
1921}
1922
7282d491 1923static const struct ethtool_ops ethtool_ops = {
1da177e4
LT
1924 .begin = check_if_running,
1925 .get_drvinfo = hamachi_get_drvinfo,
1926 .get_settings = hamachi_get_settings,
1927 .set_settings = hamachi_set_settings,
1928 .nway_reset = hamachi_nway_reset,
1929 .get_link = hamachi_get_link,
1930};
1931
7282d491 1932static const struct ethtool_ops ethtool_ops_no_mii = {
1da177e4
LT
1933 .begin = check_if_running,
1934 .get_drvinfo = hamachi_get_drvinfo,
1935};
1936
1937static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1938{
1939 struct hamachi_private *np = netdev_priv(dev);
1940 struct mii_ioctl_data *data = if_mii(rq);
1941 int rc;
1942
1943 if (!netif_running(dev))
1944 return -EINVAL;
1945
1946 if (cmd == (SIOCDEVPRIVATE+3)) { /* set rx,tx intr params */
1947 u32 *d = (u32 *)&rq->ifr_ifru;
1948 /* Should add this check here or an ordinary user can do nasty
1949 * things. -KDU
1950 *
1951 * TODO: Shut down the Rx and Tx engines while doing this.
1952 */
1953 if (!capable(CAP_NET_ADMIN))
1954 return -EPERM;
1955 writel(d[0], np->base + TxIntrCtrl);
1956 writel(d[1], np->base + RxIntrCtrl);
1957 printk(KERN_NOTICE "%s: tx %08x, rx %08x intr\n", dev->name,
1958 (u32) readl(np->base + TxIntrCtrl),
1959 (u32) readl(np->base + RxIntrCtrl));
1960 rc = 0;
1961 }
1962
1963 else {
1964 spin_lock_irq(&np->lock);
1965 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1966 spin_unlock_irq(&np->lock);
1967 }
1968
1969 return rc;
1970}
1971
1972
1973static void __devexit hamachi_remove_one (struct pci_dev *pdev)
1974{
1975 struct net_device *dev = pci_get_drvdata(pdev);
1976
1977 if (dev) {
1978 struct hamachi_private *hmp = netdev_priv(dev);
1979
6aa20a22 1980 pci_free_consistent(pdev, RX_TOTAL_SIZE, hmp->rx_ring,
1da177e4 1981 hmp->rx_ring_dma);
6aa20a22 1982 pci_free_consistent(pdev, TX_TOTAL_SIZE, hmp->tx_ring,
1da177e4
LT
1983 hmp->tx_ring_dma);
1984 unregister_netdev(dev);
1985 iounmap(hmp->base);
1986 free_netdev(dev);
1987 pci_release_regions(pdev);
1988 pci_set_drvdata(pdev, NULL);
1989 }
1990}
1991
1992static struct pci_device_id hamachi_pci_tbl[] = {
1993 { 0x1318, 0x0911, PCI_ANY_ID, PCI_ANY_ID, },
1994 { 0, }
1995};
1996MODULE_DEVICE_TABLE(pci, hamachi_pci_tbl);
1997
1998static struct pci_driver hamachi_driver = {
1999 .name = DRV_NAME,
2000 .id_table = hamachi_pci_tbl,
2001 .probe = hamachi_init_one,
2002 .remove = __devexit_p(hamachi_remove_one),
2003};
2004
2005static int __init hamachi_init (void)
2006{
2007/* when a module, this is printed whether or not devices are found in probe */
2008#ifdef MODULE
2009 printk(version);
2010#endif
2011 return pci_register_driver(&hamachi_driver);
2012}
2013
2014static void __exit hamachi_exit (void)
2015{
2016 pci_unregister_driver(&hamachi_driver);
2017}
2018
2019
2020module_init(hamachi_init);
2021module_exit(hamachi_exit);
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