Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #ifndef _IBM_EMAC_MAL_H |
2 | #define _IBM_EMAC_MAL_H | |
3 | ||
4 | #include <linux/list.h> | |
5 | ||
6 | #define MAL_DT_ALIGN (4096) /* Alignment for each channel's descriptor table */ | |
7 | ||
8 | #define MAL_CHAN_MASK(chan) (0x80000000 >> (chan)) | |
9 | ||
10 | /* MAL Buffer Descriptor structure */ | |
11 | struct mal_descriptor { | |
12 | unsigned short ctrl; /* MAL / Commac status control bits */ | |
13 | short data_len; /* Max length is 4K-1 (12 bits) */ | |
14 | unsigned char *data_ptr; /* pointer to actual data buffer */ | |
15 | } __attribute__ ((packed)); | |
16 | ||
17 | /* the following defines are for the MadMAL status and control registers. */ | |
18 | /* MADMAL transmit and receive status/control bits */ | |
19 | #define MAL_RX_CTRL_EMPTY 0x8000 | |
20 | #define MAL_RX_CTRL_WRAP 0x4000 | |
21 | #define MAL_RX_CTRL_CM 0x2000 | |
22 | #define MAL_RX_CTRL_LAST 0x1000 | |
23 | #define MAL_RX_CTRL_FIRST 0x0800 | |
24 | #define MAL_RX_CTRL_INTR 0x0400 | |
25 | ||
26 | #define MAL_TX_CTRL_READY 0x8000 | |
27 | #define MAL_TX_CTRL_WRAP 0x4000 | |
28 | #define MAL_TX_CTRL_CM 0x2000 | |
29 | #define MAL_TX_CTRL_LAST 0x1000 | |
30 | #define MAL_TX_CTRL_INTR 0x0400 | |
31 | ||
32 | struct mal_commac_ops { | |
33 | void (*txeob) (void *dev, u32 chanmask); | |
34 | void (*txde) (void *dev, u32 chanmask); | |
35 | void (*rxeob) (void *dev, u32 chanmask); | |
36 | void (*rxde) (void *dev, u32 chanmask); | |
37 | }; | |
38 | ||
39 | struct mal_commac { | |
40 | struct mal_commac_ops *ops; | |
41 | void *dev; | |
42 | u32 tx_chan_mask, rx_chan_mask; | |
43 | struct list_head list; | |
44 | }; | |
45 | ||
46 | struct ibm_ocp_mal { | |
47 | int dcrbase; | |
48 | ||
49 | struct list_head commac; | |
50 | u32 tx_chan_mask, rx_chan_mask; | |
51 | ||
52 | dma_addr_t tx_phys_addr; | |
53 | struct mal_descriptor *tx_virt_addr; | |
54 | ||
55 | dma_addr_t rx_phys_addr; | |
56 | struct mal_descriptor *rx_virt_addr; | |
57 | }; | |
58 | ||
59 | #define GET_MAL_STANZA(base,dcrn) \ | |
60 | case base: \ | |
61 | x = mfdcr(dcrn(base)); \ | |
62 | break; | |
63 | ||
64 | #define SET_MAL_STANZA(base,dcrn, val) \ | |
65 | case base: \ | |
66 | mtdcr(dcrn(base), (val)); \ | |
67 | break; | |
68 | ||
69 | #define GET_MAL0_STANZA(dcrn) GET_MAL_STANZA(DCRN_MAL_BASE,dcrn) | |
70 | #define SET_MAL0_STANZA(dcrn,val) SET_MAL_STANZA(DCRN_MAL_BASE,dcrn,val) | |
71 | ||
72 | #ifdef DCRN_MAL1_BASE | |
73 | #define GET_MAL1_STANZA(dcrn) GET_MAL_STANZA(DCRN_MAL1_BASE,dcrn) | |
74 | #define SET_MAL1_STANZA(dcrn,val) SET_MAL_STANZA(DCRN_MAL1_BASE,dcrn,val) | |
75 | #else /* ! DCRN_MAL1_BASE */ | |
76 | #define GET_MAL1_STANZA(dcrn) | |
77 | #define SET_MAL1_STANZA(dcrn,val) | |
78 | #endif | |
79 | ||
80 | #define get_mal_dcrn(mal, dcrn) ({ \ | |
81 | u32 x; \ | |
82 | switch ((mal)->dcrbase) { \ | |
83 | GET_MAL0_STANZA(dcrn) \ | |
84 | GET_MAL1_STANZA(dcrn) \ | |
85 | default: \ | |
86 | x = 0; \ | |
87 | BUG(); \ | |
88 | } \ | |
89 | x; }) | |
90 | ||
91 | #define set_mal_dcrn(mal, dcrn, val) do { \ | |
92 | switch ((mal)->dcrbase) { \ | |
93 | SET_MAL0_STANZA(dcrn,val) \ | |
94 | SET_MAL1_STANZA(dcrn,val) \ | |
95 | default: \ | |
96 | BUG(); \ | |
97 | } } while (0) | |
98 | ||
99 | static inline void mal_enable_tx_channels(struct ibm_ocp_mal *mal, u32 chanmask) | |
100 | { | |
101 | set_mal_dcrn(mal, DCRN_MALTXCASR, | |
102 | get_mal_dcrn(mal, DCRN_MALTXCASR) | chanmask); | |
103 | } | |
104 | ||
105 | static inline void mal_disable_tx_channels(struct ibm_ocp_mal *mal, | |
106 | u32 chanmask) | |
107 | { | |
108 | set_mal_dcrn(mal, DCRN_MALTXCARR, chanmask); | |
109 | } | |
110 | ||
111 | static inline void mal_enable_rx_channels(struct ibm_ocp_mal *mal, u32 chanmask) | |
112 | { | |
113 | set_mal_dcrn(mal, DCRN_MALRXCASR, | |
114 | get_mal_dcrn(mal, DCRN_MALRXCASR) | chanmask); | |
115 | } | |
116 | ||
117 | static inline void mal_disable_rx_channels(struct ibm_ocp_mal *mal, | |
118 | u32 chanmask) | |
119 | { | |
120 | set_mal_dcrn(mal, DCRN_MALRXCARR, chanmask); | |
121 | } | |
122 | ||
123 | extern int mal_register_commac(struct ibm_ocp_mal *mal, | |
124 | struct mal_commac *commac); | |
125 | extern int mal_unregister_commac(struct ibm_ocp_mal *mal, | |
126 | struct mal_commac *commac); | |
127 | ||
128 | extern int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, | |
129 | unsigned long size); | |
130 | ||
131 | #endif /* _IBM_EMAC_MAL_H */ |