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7302b9d9 MH |
1 | /* |
2 | * Analog Devices ADF7242 Low-Power IEEE 802.15.4 Transceiver | |
3 | * | |
4 | * Copyright 2009-2015 Analog Devices Inc. | |
5 | * | |
6 | * Licensed under the GPL-2 or later. | |
7 | * | |
8 | * http://www.analog.com/ADF7242 | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/mutex.h> | |
16 | #include <linux/workqueue.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/firmware.h> | |
19 | #include <linux/spi/spi.h> | |
20 | #include <linux/skbuff.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/bitops.h> | |
26 | #include <linux/ieee802154.h> | |
27 | #include <net/mac802154.h> | |
28 | #include <net/cfg802154.h> | |
29 | ||
30 | #define FIRMWARE "adf7242_firmware.bin" | |
31 | #define MAX_POLL_LOOPS 200 | |
32 | ||
33 | /* All Registers */ | |
34 | ||
35 | #define REG_EXT_CTRL 0x100 /* RW External LNA/PA and internal PA control */ | |
36 | #define REG_TX_FSK_TEST 0x101 /* RW TX FSK test mode configuration */ | |
37 | #define REG_CCA1 0x105 /* RW RSSI threshold for CCA */ | |
38 | #define REG_CCA2 0x106 /* RW CCA mode configuration */ | |
39 | #define REG_BUFFERCFG 0x107 /* RW RX_BUFFER overwrite control */ | |
40 | #define REG_PKT_CFG 0x108 /* RW FCS evaluation configuration */ | |
41 | #define REG_DELAYCFG0 0x109 /* RW RC_RX command to SFD or sync word delay */ | |
42 | #define REG_DELAYCFG1 0x10A /* RW RC_TX command to TX state */ | |
43 | #define REG_DELAYCFG2 0x10B /* RW Mac delay extension */ | |
44 | #define REG_SYNC_WORD0 0x10C /* RW sync word bits [7:0] of [23:0] */ | |
45 | #define REG_SYNC_WORD1 0x10D /* RW sync word bits [15:8] of [23:0] */ | |
46 | #define REG_SYNC_WORD2 0x10E /* RW sync word bits [23:16] of [23:0] */ | |
47 | #define REG_SYNC_CONFIG 0x10F /* RW sync word configuration */ | |
48 | #define REG_RC_CFG 0x13E /* RW RX / TX packet configuration */ | |
49 | #define REG_RC_VAR44 0x13F /* RW RESERVED */ | |
50 | #define REG_CH_FREQ0 0x300 /* RW Channel Frequency Settings - Low */ | |
51 | #define REG_CH_FREQ1 0x301 /* RW Channel Frequency Settings - Middle */ | |
52 | #define REG_CH_FREQ2 0x302 /* RW Channel Frequency Settings - High */ | |
53 | #define REG_TX_FD 0x304 /* RW TX Frequency Deviation Register */ | |
54 | #define REG_DM_CFG0 0x305 /* RW RX Discriminator BW Register */ | |
55 | #define REG_TX_M 0x306 /* RW TX Mode Register */ | |
56 | #define REG_RX_M 0x307 /* RW RX Mode Register */ | |
57 | #define REG_RRB 0x30C /* R RSSI Readback Register */ | |
58 | #define REG_LRB 0x30D /* R Link Quality Readback Register */ | |
59 | #define REG_DR0 0x30E /* RW bits [15:8] of [15:0] data rate setting */ | |
60 | #define REG_DR1 0x30F /* RW bits [7:0] of [15:0] data rate setting */ | |
61 | #define REG_PRAMPG 0x313 /* RW RESERVED */ | |
62 | #define REG_TXPB 0x314 /* RW TX Packet Storage Base Address */ | |
63 | #define REG_RXPB 0x315 /* RW RX Packet Storage Base Address */ | |
64 | #define REG_TMR_CFG0 0x316 /* RW Wake up Timer Conf Register - High */ | |
65 | #define REG_TMR_CFG1 0x317 /* RW Wake up Timer Conf Register - Low */ | |
66 | #define REG_TMR_RLD0 0x318 /* RW Wake up Timer Value Register - High */ | |
67 | #define REG_TMR_RLD1 0x319 /* RW Wake up Timer Value Register - Low */ | |
68 | #define REG_TMR_CTRL 0x31A /* RW Wake up Timer Timeout flag */ | |
69 | #define REG_PD_AUX 0x31E /* RW Battmon enable */ | |
70 | #define REG_GP_CFG 0x32C /* RW GPIO Configuration */ | |
71 | #define REG_GP_OUT 0x32D /* RW GPIO Configuration */ | |
72 | #define REG_GP_IN 0x32E /* R GPIO Configuration */ | |
73 | #define REG_SYNT 0x335 /* RW bandwidth calibration timers */ | |
74 | #define REG_CAL_CFG 0x33D /* RW Calibration Settings */ | |
75 | #define REG_PA_BIAS 0x36E /* RW PA BIAS */ | |
76 | #define REG_SYNT_CAL 0x371 /* RW Oscillator and Doubler Configuration */ | |
77 | #define REG_IIRF_CFG 0x389 /* RW BB Filter Decimation Rate */ | |
78 | #define REG_CDR_CFG 0x38A /* RW CDR kVCO */ | |
79 | #define REG_DM_CFG1 0x38B /* RW Postdemodulator Filter */ | |
80 | #define REG_AGCSTAT 0x38E /* R RXBB Ref Osc Calibration Engine Readback */ | |
81 | #define REG_RXCAL0 0x395 /* RW RX BB filter tuning, LSB */ | |
82 | #define REG_RXCAL1 0x396 /* RW RX BB filter tuning, MSB */ | |
83 | #define REG_RXFE_CFG 0x39B /* RW RXBB Ref Osc & RXFE Calibration */ | |
84 | #define REG_PA_RR 0x3A7 /* RW Set PA ramp rate */ | |
85 | #define REG_PA_CFG 0x3A8 /* RW PA enable */ | |
86 | #define REG_EXTPA_CFG 0x3A9 /* RW External PA BIAS DAC */ | |
87 | #define REG_EXTPA_MSC 0x3AA /* RW PA Bias Mode */ | |
88 | #define REG_ADC_RBK 0x3AE /* R Readback temp */ | |
89 | #define REG_AGC_CFG1 0x3B2 /* RW GC Parameters */ | |
90 | #define REG_AGC_MAX 0x3B4 /* RW Slew rate */ | |
91 | #define REG_AGC_CFG2 0x3B6 /* RW RSSI Parameters */ | |
92 | #define REG_AGC_CFG3 0x3B7 /* RW RSSI Parameters */ | |
93 | #define REG_AGC_CFG4 0x3B8 /* RW RSSI Parameters */ | |
94 | #define REG_AGC_CFG5 0x3B9 /* RW RSSI & NDEC Parameters */ | |
95 | #define REG_AGC_CFG6 0x3BA /* RW NDEC Parameters */ | |
96 | #define REG_OCL_CFG1 0x3C4 /* RW OCL System Parameters */ | |
97 | #define REG_IRQ1_EN0 0x3C7 /* RW Interrupt Mask set bits for IRQ1 */ | |
98 | #define REG_IRQ1_EN1 0x3C8 /* RW Interrupt Mask set bits for IRQ1 */ | |
99 | #define REG_IRQ2_EN0 0x3C9 /* RW Interrupt Mask set bits for IRQ2 */ | |
100 | #define REG_IRQ2_EN1 0x3CA /* RW Interrupt Mask set bits for IRQ2 */ | |
101 | #define REG_IRQ1_SRC0 0x3CB /* RW Interrupt Source bits for IRQ */ | |
102 | #define REG_IRQ1_SRC1 0x3CC /* RW Interrupt Source bits for IRQ */ | |
103 | #define REG_OCL_BW0 0x3D2 /* RW OCL System Parameters */ | |
104 | #define REG_OCL_BW1 0x3D3 /* RW OCL System Parameters */ | |
105 | #define REG_OCL_BW2 0x3D4 /* RW OCL System Parameters */ | |
106 | #define REG_OCL_BW3 0x3D5 /* RW OCL System Parameters */ | |
107 | #define REG_OCL_BW4 0x3D6 /* RW OCL System Parameters */ | |
108 | #define REG_OCL_BWS 0x3D7 /* RW OCL System Parameters */ | |
109 | #define REG_OCL_CFG13 0x3E0 /* RW OCL System Parameters */ | |
110 | #define REG_GP_DRV 0x3E3 /* RW I/O pads Configuration and bg trim */ | |
111 | #define REG_BM_CFG 0x3E6 /* RW Batt. Monitor Threshold Voltage setting */ | |
112 | #define REG_SFD_15_4 0x3F4 /* RW Option to set non standard SFD */ | |
113 | #define REG_AFC_CFG 0x3F7 /* RW AFC mode and polarity */ | |
114 | #define REG_AFC_KI_KP 0x3F8 /* RW AFC ki and kp */ | |
115 | #define REG_AFC_RANGE 0x3F9 /* RW AFC range */ | |
116 | #define REG_AFC_READ 0x3FA /* RW Readback frequency error */ | |
117 | ||
118 | /* REG_EXTPA_MSC */ | |
119 | #define PA_PWR(x) (((x) & 0xF) << 4) | |
120 | #define EXTPA_BIAS_SRC BIT(3) | |
121 | #define EXTPA_BIAS_MODE(x) (((x) & 0x7) << 0) | |
122 | ||
123 | /* REG_PA_CFG */ | |
124 | #define PA_BRIDGE_DBIAS(x) (((x) & 0x1F) << 0) | |
125 | #define PA_DBIAS_HIGH_POWER 21 | |
126 | #define PA_DBIAS_LOW_POWER 13 | |
127 | ||
128 | /* REG_PA_BIAS */ | |
129 | #define PA_BIAS_CTRL(x) (((x) & 0x1F) << 1) | |
130 | #define REG_PA_BIAS_DFL BIT(0) | |
131 | #define PA_BIAS_HIGH_POWER 63 | |
132 | #define PA_BIAS_LOW_POWER 55 | |
133 | ||
134 | #define REG_PAN_ID0 0x112 | |
135 | #define REG_PAN_ID1 0x113 | |
136 | #define REG_SHORT_ADDR_0 0x114 | |
137 | #define REG_SHORT_ADDR_1 0x115 | |
138 | #define REG_IEEE_ADDR_0 0x116 | |
139 | #define REG_IEEE_ADDR_1 0x117 | |
140 | #define REG_IEEE_ADDR_2 0x118 | |
141 | #define REG_IEEE_ADDR_3 0x119 | |
142 | #define REG_IEEE_ADDR_4 0x11A | |
143 | #define REG_IEEE_ADDR_5 0x11B | |
144 | #define REG_IEEE_ADDR_6 0x11C | |
145 | #define REG_IEEE_ADDR_7 0x11D | |
146 | #define REG_FFILT_CFG 0x11E | |
147 | #define REG_AUTO_CFG 0x11F | |
148 | #define REG_AUTO_TX1 0x120 | |
149 | #define REG_AUTO_TX2 0x121 | |
150 | #define REG_AUTO_STATUS 0x122 | |
151 | ||
152 | /* REG_FFILT_CFG */ | |
153 | #define ACCEPT_BEACON_FRAMES BIT(0) | |
154 | #define ACCEPT_DATA_FRAMES BIT(1) | |
155 | #define ACCEPT_ACK_FRAMES BIT(2) | |
156 | #define ACCEPT_MACCMD_FRAMES BIT(3) | |
157 | #define ACCEPT_RESERVED_FRAMES BIT(4) | |
158 | #define ACCEPT_ALL_ADDRESS BIT(5) | |
159 | ||
160 | /* REG_AUTO_CFG */ | |
161 | #define AUTO_ACK_FRAMEPEND BIT(0) | |
162 | #define IS_PANCOORD BIT(1) | |
163 | #define RX_AUTO_ACK_EN BIT(3) | |
164 | #define CSMA_CA_RX_TURNAROUND BIT(4) | |
165 | ||
166 | /* REG_AUTO_TX1 */ | |
167 | #define MAX_FRAME_RETRIES(x) ((x) & 0xF) | |
168 | #define MAX_CCA_RETRIES(x) (((x) & 0x7) << 4) | |
169 | ||
170 | /* REG_AUTO_TX2 */ | |
171 | #define CSMA_MAX_BE(x) ((x) & 0xF) | |
172 | #define CSMA_MIN_BE(x) (((x) & 0xF) << 4) | |
173 | ||
174 | #define CMD_SPI_NOP 0xFF /* No operation. Use for dummy writes */ | |
175 | #define CMD_SPI_PKT_WR 0x10 /* Write telegram to the Packet RAM | |
176 | * starting from the TX packet base address | |
177 | * pointer tx_packet_base | |
178 | */ | |
179 | #define CMD_SPI_PKT_RD 0x30 /* Read telegram from the Packet RAM | |
180 | * starting from RX packet base address | |
181 | * pointer rxpb.rx_packet_base | |
182 | */ | |
183 | #define CMD_SPI_MEM_WR(x) (0x18 + (x >> 8)) /* Write data to MCR or | |
184 | * Packet RAM sequentially | |
185 | */ | |
186 | #define CMD_SPI_MEM_RD(x) (0x38 + (x >> 8)) /* Read data from MCR or | |
187 | * Packet RAM sequentially | |
188 | */ | |
189 | #define CMD_SPI_MEMR_WR(x) (0x08 + (x >> 8)) /* Write data to MCR or Packet | |
190 | * RAM as random block | |
191 | */ | |
192 | #define CMD_SPI_MEMR_RD(x) (0x28 + (x >> 8)) /* Read data from MCR or | |
193 | * Packet RAM random block | |
194 | */ | |
195 | #define CMD_SPI_PRAM_WR 0x1E /* Write data sequentially to current | |
196 | * PRAM page selected | |
197 | */ | |
198 | #define CMD_SPI_PRAM_RD 0x3E /* Read data sequentially from current | |
199 | * PRAM page selected | |
200 | */ | |
201 | #define CMD_RC_SLEEP 0xB1 /* Invoke transition of radio controller | |
202 | * into SLEEP state | |
203 | */ | |
204 | #define CMD_RC_IDLE 0xB2 /* Invoke transition of radio controller | |
205 | * into IDLE state | |
206 | */ | |
207 | #define CMD_RC_PHY_RDY 0xB3 /* Invoke transition of radio controller | |
208 | * into PHY_RDY state | |
209 | */ | |
210 | #define CMD_RC_RX 0xB4 /* Invoke transition of radio controller | |
211 | * into RX state | |
212 | */ | |
213 | #define CMD_RC_TX 0xB5 /* Invoke transition of radio controller | |
214 | * into TX state | |
215 | */ | |
216 | #define CMD_RC_MEAS 0xB6 /* Invoke transition of radio controller | |
217 | * into MEAS state | |
218 | */ | |
219 | #define CMD_RC_CCA 0xB7 /* Invoke Clear channel assessment */ | |
220 | #define CMD_RC_CSMACA 0xC1 /* initiates CSMA-CA channel access | |
221 | * sequence and frame transmission | |
222 | */ | |
223 | #define CMD_RC_PC_RESET 0xC7 /* Program counter reset */ | |
224 | #define CMD_RC_RESET 0xC8 /* Resets the ADF7242 and puts it in | |
225 | * the sleep state | |
226 | */ | |
227 | #define CMD_RC_PC_RESET_NO_WAIT (CMD_RC_PC_RESET | BIT(31)) | |
228 | ||
229 | /* STATUS */ | |
230 | ||
231 | #define STAT_SPI_READY BIT(7) | |
232 | #define STAT_IRQ_STATUS BIT(6) | |
233 | #define STAT_RC_READY BIT(5) | |
234 | #define STAT_CCA_RESULT BIT(4) | |
235 | #define RC_STATUS_IDLE 1 | |
236 | #define RC_STATUS_MEAS 2 | |
237 | #define RC_STATUS_PHY_RDY 3 | |
238 | #define RC_STATUS_RX 4 | |
239 | #define RC_STATUS_TX 5 | |
240 | #define RC_STATUS_MASK 0xF | |
241 | ||
242 | /* AUTO_STATUS */ | |
243 | ||
244 | #define SUCCESS 0 | |
245 | #define SUCCESS_DATPEND 1 | |
246 | #define FAILURE_CSMACA 2 | |
247 | #define FAILURE_NOACK 3 | |
248 | #define AUTO_STATUS_MASK 0x3 | |
249 | ||
250 | #define PRAM_PAGESIZE 256 | |
251 | ||
252 | /* IRQ1 */ | |
253 | ||
254 | #define IRQ_CCA_COMPLETE BIT(0) | |
255 | #define IRQ_SFD_RX BIT(1) | |
256 | #define IRQ_SFD_TX BIT(2) | |
257 | #define IRQ_RX_PKT_RCVD BIT(3) | |
258 | #define IRQ_TX_PKT_SENT BIT(4) | |
259 | #define IRQ_FRAME_VALID BIT(5) | |
260 | #define IRQ_ADDRESS_VALID BIT(6) | |
261 | #define IRQ_CSMA_CA BIT(7) | |
262 | ||
263 | #define AUTO_TX_TURNAROUND BIT(3) | |
264 | #define ADDON_EN BIT(4) | |
265 | ||
266 | #define FLAG_XMIT 0 | |
267 | #define FLAG_START 1 | |
268 | ||
269 | #define ADF7242_REPORT_CSMA_CA_STAT 0 /* framework doesn't handle yet */ | |
270 | ||
271 | struct adf7242_local { | |
272 | struct spi_device *spi; | |
273 | struct completion tx_complete; | |
274 | struct ieee802154_hw *hw; | |
275 | struct mutex bmux; /* protect SPI messages */ | |
276 | struct spi_message stat_msg; | |
277 | struct spi_transfer stat_xfer; | |
278 | struct dentry *debugfs_root; | |
279 | unsigned long flags; | |
280 | int tx_stat; | |
281 | bool promiscuous; | |
282 | s8 rssi; | |
283 | u8 max_frame_retries; | |
284 | u8 max_cca_retries; | |
285 | u8 max_be; | |
286 | u8 min_be; | |
287 | ||
288 | /* DMA (thus cache coherency maintenance) requires the | |
289 | * transfer buffers to live in their own cache lines. | |
290 | */ | |
291 | ||
292 | u8 buf[3] ____cacheline_aligned; | |
293 | u8 buf_reg_tx[3]; | |
294 | u8 buf_read_tx[4]; | |
295 | u8 buf_read_rx[4]; | |
296 | u8 buf_stat_rx; | |
297 | u8 buf_stat_tx; | |
298 | u8 buf_cmd; | |
299 | }; | |
300 | ||
301 | static int adf7242_soft_reset(struct adf7242_local *lp, int line); | |
302 | ||
303 | static int adf7242_status(struct adf7242_local *lp, u8 *stat) | |
304 | { | |
305 | int status; | |
306 | ||
307 | mutex_lock(&lp->bmux); | |
308 | status = spi_sync(lp->spi, &lp->stat_msg); | |
309 | *stat = lp->buf_stat_rx; | |
310 | mutex_unlock(&lp->bmux); | |
311 | ||
312 | return status; | |
313 | } | |
314 | ||
315 | static int adf7242_wait_status(struct adf7242_local *lp, unsigned status, | |
316 | unsigned mask, int line) | |
317 | { | |
318 | int cnt = 0, ret = 0; | |
319 | u8 stat; | |
320 | ||
321 | do { | |
322 | adf7242_status(lp, &stat); | |
323 | cnt++; | |
324 | } while (((stat & mask) != status) && (cnt < MAX_POLL_LOOPS)); | |
325 | ||
326 | if (cnt >= MAX_POLL_LOOPS) { | |
327 | ret = -ETIMEDOUT; | |
328 | ||
329 | if (!(stat & STAT_RC_READY)) { | |
330 | adf7242_soft_reset(lp, line); | |
331 | adf7242_status(lp, &stat); | |
332 | ||
333 | if ((stat & mask) == status) | |
334 | ret = 0; | |
335 | } | |
336 | ||
337 | if (ret < 0) | |
338 | dev_warn(&lp->spi->dev, | |
339 | "%s:line %d Timeout status 0x%x (%d)\n", | |
340 | __func__, line, stat, cnt); | |
341 | } | |
342 | ||
343 | dev_vdbg(&lp->spi->dev, "%s : loops=%d line %d\n", __func__, cnt, line); | |
344 | ||
345 | return ret; | |
346 | } | |
347 | ||
348 | static int adf7242_wait_ready(struct adf7242_local *lp, int line) | |
349 | { | |
350 | return adf7242_wait_status(lp, STAT_RC_READY | STAT_SPI_READY, | |
351 | STAT_RC_READY | STAT_SPI_READY, line); | |
352 | } | |
353 | ||
354 | static int adf7242_write_fbuf(struct adf7242_local *lp, u8 *data, u8 len) | |
355 | { | |
356 | u8 *buf = lp->buf; | |
357 | int status; | |
358 | struct spi_message msg; | |
359 | struct spi_transfer xfer_head = { | |
360 | .len = 2, | |
361 | .tx_buf = buf, | |
362 | ||
363 | }; | |
364 | struct spi_transfer xfer_buf = { | |
365 | .len = len, | |
366 | .tx_buf = data, | |
367 | }; | |
368 | ||
369 | spi_message_init(&msg); | |
370 | spi_message_add_tail(&xfer_head, &msg); | |
371 | spi_message_add_tail(&xfer_buf, &msg); | |
372 | ||
373 | adf7242_wait_ready(lp, __LINE__); | |
374 | ||
375 | mutex_lock(&lp->bmux); | |
376 | buf[0] = CMD_SPI_PKT_WR; | |
377 | buf[1] = len + 2; | |
378 | ||
379 | status = spi_sync(lp->spi, &msg); | |
380 | mutex_unlock(&lp->bmux); | |
381 | ||
382 | return status; | |
383 | } | |
384 | ||
385 | static int adf7242_read_fbuf(struct adf7242_local *lp, | |
386 | u8 *data, size_t len, bool packet_read) | |
387 | { | |
388 | u8 *buf = lp->buf; | |
389 | int status; | |
390 | struct spi_message msg; | |
391 | struct spi_transfer xfer_head = { | |
392 | .len = 3, | |
393 | .tx_buf = buf, | |
394 | .rx_buf = buf, | |
395 | }; | |
396 | struct spi_transfer xfer_buf = { | |
397 | .len = len, | |
398 | .rx_buf = data, | |
399 | }; | |
400 | ||
401 | spi_message_init(&msg); | |
402 | spi_message_add_tail(&xfer_head, &msg); | |
403 | spi_message_add_tail(&xfer_buf, &msg); | |
404 | ||
405 | adf7242_wait_ready(lp, __LINE__); | |
406 | ||
407 | mutex_lock(&lp->bmux); | |
408 | if (packet_read) { | |
409 | buf[0] = CMD_SPI_PKT_RD; | |
410 | buf[1] = CMD_SPI_NOP; | |
411 | buf[2] = 0; /* PHR */ | |
412 | } else { | |
413 | buf[0] = CMD_SPI_PRAM_RD; | |
414 | buf[1] = 0; | |
415 | buf[2] = CMD_SPI_NOP; | |
416 | } | |
417 | ||
418 | status = spi_sync(lp->spi, &msg); | |
419 | ||
420 | mutex_unlock(&lp->bmux); | |
421 | ||
422 | return status; | |
423 | } | |
424 | ||
425 | static int adf7242_read_reg(struct adf7242_local *lp, u16 addr, u8 *data) | |
426 | { | |
427 | int status; | |
428 | struct spi_message msg; | |
429 | ||
430 | struct spi_transfer xfer = { | |
431 | .len = 4, | |
432 | .tx_buf = lp->buf_read_tx, | |
433 | .rx_buf = lp->buf_read_rx, | |
434 | }; | |
435 | ||
436 | adf7242_wait_ready(lp, __LINE__); | |
437 | ||
438 | mutex_lock(&lp->bmux); | |
439 | lp->buf_read_tx[0] = CMD_SPI_MEM_RD(addr); | |
440 | lp->buf_read_tx[1] = addr; | |
441 | lp->buf_read_tx[2] = CMD_SPI_NOP; | |
442 | lp->buf_read_tx[3] = CMD_SPI_NOP; | |
443 | ||
444 | spi_message_init(&msg); | |
445 | spi_message_add_tail(&xfer, &msg); | |
446 | ||
447 | status = spi_sync(lp->spi, &msg); | |
448 | if (msg.status) | |
449 | status = msg.status; | |
450 | ||
451 | if (!status) | |
452 | *data = lp->buf_read_rx[3]; | |
453 | ||
454 | mutex_unlock(&lp->bmux); | |
455 | ||
456 | dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n", __func__, | |
457 | addr, *data); | |
458 | ||
459 | return status; | |
460 | } | |
461 | ||
462 | static int adf7242_write_reg(struct adf7242_local *lp, u16 addr, u8 data) | |
463 | { | |
464 | int status; | |
465 | ||
466 | adf7242_wait_ready(lp, __LINE__); | |
467 | ||
468 | mutex_lock(&lp->bmux); | |
469 | lp->buf_reg_tx[0] = CMD_SPI_MEM_WR(addr); | |
470 | lp->buf_reg_tx[1] = addr; | |
471 | lp->buf_reg_tx[2] = data; | |
472 | status = spi_write(lp->spi, lp->buf_reg_tx, 3); | |
473 | mutex_unlock(&lp->bmux); | |
474 | ||
475 | dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n", | |
476 | __func__, addr, data); | |
477 | ||
478 | return status; | |
479 | } | |
480 | ||
481 | static int adf7242_cmd(struct adf7242_local *lp, unsigned cmd) | |
482 | { | |
483 | int status; | |
484 | ||
485 | dev_vdbg(&lp->spi->dev, "%s : CMD=0x%X\n", __func__, cmd); | |
486 | ||
487 | if (cmd != CMD_RC_PC_RESET_NO_WAIT) | |
488 | adf7242_wait_ready(lp, __LINE__); | |
489 | ||
490 | mutex_lock(&lp->bmux); | |
491 | lp->buf_cmd = cmd; | |
492 | status = spi_write(lp->spi, &lp->buf_cmd, 1); | |
493 | mutex_unlock(&lp->bmux); | |
494 | ||
495 | return status; | |
496 | } | |
497 | ||
498 | static int adf7242_upload_firmware(struct adf7242_local *lp, u8 *data, u16 len) | |
499 | { | |
500 | struct spi_message msg; | |
501 | struct spi_transfer xfer_buf = { }; | |
502 | int status, i, page = 0; | |
503 | u8 *buf = lp->buf; | |
504 | ||
505 | struct spi_transfer xfer_head = { | |
506 | .len = 2, | |
507 | .tx_buf = buf, | |
508 | }; | |
509 | ||
510 | buf[0] = CMD_SPI_PRAM_WR; | |
511 | buf[1] = 0; | |
512 | ||
513 | spi_message_init(&msg); | |
514 | spi_message_add_tail(&xfer_head, &msg); | |
515 | spi_message_add_tail(&xfer_buf, &msg); | |
516 | ||
517 | for (i = len; i >= 0; i -= PRAM_PAGESIZE) { | |
518 | adf7242_write_reg(lp, REG_PRAMPG, page); | |
519 | ||
520 | xfer_buf.len = (i >= PRAM_PAGESIZE) ? PRAM_PAGESIZE : i; | |
521 | xfer_buf.tx_buf = &data[page * PRAM_PAGESIZE]; | |
522 | ||
523 | mutex_lock(&lp->bmux); | |
524 | status = spi_sync(lp->spi, &msg); | |
525 | mutex_unlock(&lp->bmux); | |
526 | page++; | |
527 | } | |
528 | ||
529 | return status; | |
530 | } | |
531 | ||
532 | static int adf7242_verify_firmware(struct adf7242_local *lp, | |
533 | const u8 *data, size_t len) | |
534 | { | |
535 | #ifdef DEBUG | |
536 | int i, j; | |
537 | unsigned int page; | |
538 | u8 *buf = kmalloc(PRAM_PAGESIZE, GFP_KERNEL); | |
539 | ||
540 | if (!buf) | |
541 | return -ENOMEM; | |
542 | ||
543 | for (page = 0, i = len; i >= 0; i -= PRAM_PAGESIZE, page++) { | |
544 | size_t nb = (i >= PRAM_PAGESIZE) ? PRAM_PAGESIZE : i; | |
545 | ||
546 | adf7242_write_reg(lp, REG_PRAMPG, page); | |
547 | adf7242_read_fbuf(lp, buf, nb, false); | |
548 | ||
549 | for (j = 0; j < nb; j++) { | |
550 | if (buf[j] != data[page * PRAM_PAGESIZE + j]) { | |
551 | kfree(buf); | |
552 | return -EIO; | |
553 | } | |
554 | } | |
555 | } | |
556 | kfree(buf); | |
557 | #endif | |
558 | return 0; | |
559 | } | |
560 | ||
561 | static int adf7242_set_txpower(struct ieee802154_hw *hw, int mbm) | |
562 | { | |
563 | struct adf7242_local *lp = hw->priv; | |
564 | u8 pwr, bias_ctrl, dbias, tmp; | |
565 | int db = mbm / 100; | |
566 | ||
567 | dev_vdbg(&lp->spi->dev, "%s : Power %d dB\n", __func__, db); | |
568 | ||
569 | if (db > 5 || db < -26) | |
570 | return -EINVAL; | |
571 | ||
572 | db = DIV_ROUND_CLOSEST(db + 29, 2); | |
573 | ||
574 | if (db > 15) { | |
575 | dbias = PA_DBIAS_HIGH_POWER; | |
576 | bias_ctrl = PA_BIAS_HIGH_POWER; | |
577 | } else { | |
578 | dbias = PA_DBIAS_LOW_POWER; | |
579 | bias_ctrl = PA_BIAS_LOW_POWER; | |
580 | } | |
581 | ||
582 | pwr = clamp_t(u8, db, 3, 15); | |
583 | ||
584 | adf7242_read_reg(lp, REG_PA_CFG, &tmp); | |
585 | tmp &= ~PA_BRIDGE_DBIAS(~0); | |
586 | tmp |= PA_BRIDGE_DBIAS(dbias); | |
587 | adf7242_write_reg(lp, REG_PA_CFG, tmp); | |
588 | ||
589 | adf7242_read_reg(lp, REG_PA_BIAS, &tmp); | |
590 | tmp &= ~PA_BIAS_CTRL(~0); | |
591 | tmp |= PA_BIAS_CTRL(bias_ctrl); | |
592 | adf7242_write_reg(lp, REG_PA_BIAS, tmp); | |
593 | ||
594 | adf7242_read_reg(lp, REG_EXTPA_MSC, &tmp); | |
595 | tmp &= ~PA_PWR(~0); | |
596 | tmp |= PA_PWR(pwr); | |
597 | ||
598 | return adf7242_write_reg(lp, REG_EXTPA_MSC, tmp); | |
599 | } | |
600 | ||
601 | static int adf7242_set_csma_params(struct ieee802154_hw *hw, u8 min_be, | |
602 | u8 max_be, u8 retries) | |
603 | { | |
604 | struct adf7242_local *lp = hw->priv; | |
605 | int ret; | |
606 | ||
607 | dev_vdbg(&lp->spi->dev, "%s : min_be=%d max_be=%d retries=%d\n", | |
608 | __func__, min_be, max_be, retries); | |
609 | ||
610 | if (min_be > max_be || max_be > 8 || retries > 5) | |
611 | return -EINVAL; | |
612 | ||
613 | ret = adf7242_write_reg(lp, REG_AUTO_TX1, | |
614 | MAX_FRAME_RETRIES(lp->max_frame_retries) | | |
615 | MAX_CCA_RETRIES(retries)); | |
616 | if (ret) | |
617 | return ret; | |
618 | ||
619 | lp->max_cca_retries = retries; | |
620 | lp->max_be = max_be; | |
621 | lp->min_be = min_be; | |
622 | ||
623 | return adf7242_write_reg(lp, REG_AUTO_TX2, CSMA_MAX_BE(max_be) | | |
624 | CSMA_MIN_BE(min_be)); | |
625 | } | |
626 | ||
627 | static int adf7242_set_frame_retries(struct ieee802154_hw *hw, s8 retries) | |
628 | { | |
629 | struct adf7242_local *lp = hw->priv; | |
630 | int ret = 0; | |
631 | ||
632 | dev_vdbg(&lp->spi->dev, "%s : Retries = %d\n", __func__, retries); | |
633 | ||
634 | if (retries < -1 || retries > 15) | |
635 | return -EINVAL; | |
636 | ||
637 | if (retries >= 0) | |
638 | ret = adf7242_write_reg(lp, REG_AUTO_TX1, | |
639 | MAX_FRAME_RETRIES(retries) | | |
640 | MAX_CCA_RETRIES(lp->max_cca_retries)); | |
641 | ||
642 | lp->max_frame_retries = retries; | |
643 | ||
644 | return ret; | |
645 | } | |
646 | ||
647 | static int adf7242_ed(struct ieee802154_hw *hw, u8 *level) | |
648 | { | |
649 | struct adf7242_local *lp = hw->priv; | |
650 | ||
651 | *level = lp->rssi; | |
652 | ||
653 | dev_vdbg(&lp->spi->dev, "%s :Exit level=%d\n", | |
654 | __func__, *level); | |
655 | ||
656 | return 0; | |
657 | } | |
658 | ||
659 | static int adf7242_start(struct ieee802154_hw *hw) | |
660 | { | |
661 | struct adf7242_local *lp = hw->priv; | |
662 | ||
663 | adf7242_cmd(lp, CMD_RC_PHY_RDY); | |
664 | adf7242_write_reg(lp, REG_IRQ1_SRC1, 0xFF); | |
665 | enable_irq(lp->spi->irq); | |
666 | set_bit(FLAG_START, &lp->flags); | |
667 | ||
668 | return adf7242_cmd(lp, CMD_RC_RX); | |
669 | } | |
670 | ||
671 | static void adf7242_stop(struct ieee802154_hw *hw) | |
672 | { | |
673 | struct adf7242_local *lp = hw->priv; | |
674 | ||
675 | adf7242_cmd(lp, CMD_RC_IDLE); | |
676 | clear_bit(FLAG_START, &lp->flags); | |
677 | disable_irq(lp->spi->irq); | |
678 | adf7242_write_reg(lp, REG_IRQ1_SRC1, 0xFF); | |
679 | } | |
680 | ||
681 | static int adf7242_channel(struct ieee802154_hw *hw, u8 page, u8 channel) | |
682 | { | |
683 | struct adf7242_local *lp = hw->priv; | |
684 | unsigned long freq; | |
685 | ||
686 | dev_dbg(&lp->spi->dev, "%s :Channel=%d\n", __func__, channel); | |
687 | ||
688 | might_sleep(); | |
689 | ||
690 | WARN_ON(page != 0); | |
691 | WARN_ON(channel < 11); | |
692 | WARN_ON(channel > 26); | |
693 | ||
694 | freq = (2405 + 5 * (channel - 11)) * 100; | |
695 | adf7242_cmd(lp, CMD_RC_PHY_RDY); | |
696 | ||
697 | adf7242_write_reg(lp, REG_CH_FREQ0, freq); | |
698 | adf7242_write_reg(lp, REG_CH_FREQ1, freq >> 8); | |
699 | adf7242_write_reg(lp, REG_CH_FREQ2, freq >> 16); | |
700 | ||
701 | return adf7242_cmd(lp, CMD_RC_RX); | |
702 | } | |
703 | ||
704 | static int adf7242_set_hw_addr_filt(struct ieee802154_hw *hw, | |
705 | struct ieee802154_hw_addr_filt *filt, | |
706 | unsigned long changed) | |
707 | { | |
708 | struct adf7242_local *lp = hw->priv; | |
709 | u8 reg; | |
710 | ||
711 | dev_dbg(&lp->spi->dev, "%s :Changed=0x%lX\n", __func__, changed); | |
712 | ||
713 | might_sleep(); | |
714 | ||
715 | if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) { | |
716 | u8 addr[8], i; | |
717 | ||
718 | memcpy(addr, &filt->ieee_addr, 8); | |
719 | ||
720 | for (i = 0; i < 8; i++) | |
721 | adf7242_write_reg(lp, REG_IEEE_ADDR_0 + i, addr[i]); | |
722 | } | |
723 | ||
724 | if (changed & IEEE802154_AFILT_SADDR_CHANGED) { | |
725 | u16 saddr = le16_to_cpu(filt->short_addr); | |
726 | ||
727 | adf7242_write_reg(lp, REG_SHORT_ADDR_0, saddr); | |
728 | adf7242_write_reg(lp, REG_SHORT_ADDR_1, saddr >> 8); | |
729 | } | |
730 | ||
731 | if (changed & IEEE802154_AFILT_PANID_CHANGED) { | |
732 | u16 pan_id = le16_to_cpu(filt->pan_id); | |
733 | ||
734 | adf7242_write_reg(lp, REG_PAN_ID0, pan_id); | |
735 | adf7242_write_reg(lp, REG_PAN_ID1, pan_id >> 8); | |
736 | } | |
737 | ||
738 | if (changed & IEEE802154_AFILT_PANC_CHANGED) { | |
739 | adf7242_read_reg(lp, REG_AUTO_CFG, ®); | |
740 | if (filt->pan_coord) | |
741 | reg |= IS_PANCOORD; | |
742 | else | |
743 | reg &= ~IS_PANCOORD; | |
744 | adf7242_write_reg(lp, REG_AUTO_CFG, reg); | |
745 | } | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
750 | static int adf7242_set_promiscuous_mode(struct ieee802154_hw *hw, bool on) | |
751 | { | |
752 | struct adf7242_local *lp = hw->priv; | |
753 | ||
754 | dev_dbg(&lp->spi->dev, "%s : mode %d\n", __func__, on); | |
755 | ||
756 | lp->promiscuous = on; | |
757 | ||
758 | if (on) { | |
759 | adf7242_write_reg(lp, REG_AUTO_CFG, 0); | |
760 | return adf7242_write_reg(lp, REG_FFILT_CFG, | |
761 | ACCEPT_BEACON_FRAMES | | |
762 | ACCEPT_DATA_FRAMES | | |
763 | ACCEPT_MACCMD_FRAMES | | |
764 | ACCEPT_ALL_ADDRESS | | |
765 | ACCEPT_ACK_FRAMES | | |
766 | ACCEPT_RESERVED_FRAMES); | |
767 | } else { | |
768 | adf7242_write_reg(lp, REG_FFILT_CFG, | |
769 | ACCEPT_BEACON_FRAMES | | |
770 | ACCEPT_DATA_FRAMES | | |
771 | ACCEPT_MACCMD_FRAMES | | |
772 | ACCEPT_RESERVED_FRAMES); | |
773 | ||
774 | return adf7242_write_reg(lp, REG_AUTO_CFG, RX_AUTO_ACK_EN); | |
775 | } | |
776 | } | |
777 | ||
778 | static int adf7242_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm) | |
779 | { | |
780 | struct adf7242_local *lp = hw->priv; | |
781 | s8 level = clamp_t(s8, mbm / 100, S8_MIN, S8_MAX); | |
782 | ||
783 | dev_dbg(&lp->spi->dev, "%s : level %d\n", __func__, level); | |
784 | ||
785 | return adf7242_write_reg(lp, REG_CCA1, level); | |
786 | } | |
787 | ||
788 | static int adf7242_xmit(struct ieee802154_hw *hw, struct sk_buff *skb) | |
789 | { | |
790 | struct adf7242_local *lp = hw->priv; | |
791 | int ret; | |
792 | ||
793 | set_bit(FLAG_XMIT, &lp->flags); | |
794 | reinit_completion(&lp->tx_complete); | |
795 | adf7242_cmd(lp, CMD_RC_PHY_RDY); | |
796 | ||
797 | ret = adf7242_write_fbuf(lp, skb->data, skb->len); | |
798 | if (ret) | |
799 | goto err; | |
800 | ||
801 | ret = adf7242_cmd(lp, CMD_RC_CSMACA); | |
802 | if (ret) | |
803 | goto err; | |
804 | ||
805 | ret = wait_for_completion_interruptible_timeout(&lp->tx_complete, | |
806 | HZ / 10); | |
807 | if (ret < 0) | |
808 | goto err; | |
809 | if (ret == 0) { | |
810 | dev_dbg(&lp->spi->dev, "Timeout waiting for TX interrupt\n"); | |
811 | ret = -ETIMEDOUT; | |
812 | goto err; | |
813 | } | |
814 | ||
815 | if (lp->tx_stat != SUCCESS) { | |
816 | dev_dbg(&lp->spi->dev, | |
817 | "Error xmit: Retry count exceeded Status=0x%x\n", | |
818 | lp->tx_stat); | |
819 | ret = -ECOMM; | |
820 | } else { | |
821 | ret = 0; | |
822 | } | |
823 | ||
824 | err: | |
825 | clear_bit(FLAG_XMIT, &lp->flags); | |
826 | adf7242_cmd(lp, CMD_RC_RX); | |
827 | ||
828 | return ret; | |
829 | } | |
830 | ||
831 | static int adf7242_rx(struct adf7242_local *lp) | |
832 | { | |
833 | struct sk_buff *skb; | |
834 | size_t len; | |
835 | int ret; | |
836 | u8 lqi, len_u8, *data; | |
837 | ||
838 | adf7242_read_reg(lp, 0, &len_u8); | |
839 | ||
840 | len = len_u8; | |
841 | ||
842 | if (!ieee802154_is_valid_psdu_len(len)) { | |
843 | dev_dbg(&lp->spi->dev, | |
844 | "corrupted frame received len %d\n", (int)len); | |
845 | len = IEEE802154_MTU; | |
846 | } | |
847 | ||
848 | skb = dev_alloc_skb(len); | |
849 | if (!skb) { | |
850 | adf7242_cmd(lp, CMD_RC_RX); | |
851 | return -ENOMEM; | |
852 | } | |
853 | ||
854 | data = skb_put(skb, len); | |
855 | ret = adf7242_read_fbuf(lp, data, len, true); | |
856 | if (ret < 0) { | |
857 | kfree_skb(skb); | |
858 | adf7242_cmd(lp, CMD_RC_RX); | |
859 | return ret; | |
860 | } | |
861 | ||
862 | lqi = data[len - 2]; | |
863 | lp->rssi = data[len - 1]; | |
864 | ||
865 | adf7242_cmd(lp, CMD_RC_RX); | |
866 | ||
867 | skb_trim(skb, len - 2); /* Don't put RSSI/LQI or CRC into the frame */ | |
868 | ||
869 | ieee802154_rx_irqsafe(lp->hw, skb, lqi); | |
870 | ||
871 | dev_dbg(&lp->spi->dev, "%s: ret=%d len=%d lqi=%d rssi=%d\n", | |
872 | __func__, ret, (int)len, (int)lqi, lp->rssi); | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
877 | static struct ieee802154_ops adf7242_ops = { | |
878 | .owner = THIS_MODULE, | |
879 | .xmit_sync = adf7242_xmit, | |
880 | .ed = adf7242_ed, | |
881 | .set_channel = adf7242_channel, | |
882 | .set_hw_addr_filt = adf7242_set_hw_addr_filt, | |
883 | .start = adf7242_start, | |
884 | .stop = adf7242_stop, | |
885 | .set_csma_params = adf7242_set_csma_params, | |
886 | .set_frame_retries = adf7242_set_frame_retries, | |
887 | .set_txpower = adf7242_set_txpower, | |
888 | .set_promiscuous_mode = adf7242_set_promiscuous_mode, | |
889 | .set_cca_ed_level = adf7242_set_cca_ed_level, | |
890 | }; | |
891 | ||
892 | static void adf7242_debug(u8 irq1) | |
893 | { | |
894 | #ifdef DEBUG | |
895 | u8 stat; | |
896 | ||
897 | adf7242_status(lp, &stat); | |
898 | ||
899 | dev_dbg(&lp->spi->dev, "%s IRQ1 = %X:\n%s%s%s%s%s%s%s%s\n", | |
900 | __func__, irq1, | |
901 | irq1 & IRQ_CCA_COMPLETE ? "IRQ_CCA_COMPLETE\n" : "", | |
902 | irq1 & IRQ_SFD_RX ? "IRQ_SFD_RX\n" : "", | |
903 | irq1 & IRQ_SFD_TX ? "IRQ_SFD_TX\n" : "", | |
904 | irq1 & IRQ_RX_PKT_RCVD ? "IRQ_RX_PKT_RCVD\n" : "", | |
905 | irq1 & IRQ_TX_PKT_SENT ? "IRQ_TX_PKT_SENT\n" : "", | |
906 | irq1 & IRQ_CSMA_CA ? "IRQ_CSMA_CA\n" : "", | |
907 | irq1 & IRQ_FRAME_VALID ? "IRQ_FRAME_VALID\n" : "", | |
908 | irq1 & IRQ_ADDRESS_VALID ? "IRQ_ADDRESS_VALID\n" : ""); | |
909 | ||
910 | dev_dbg(&lp->spi->dev, "%s STATUS = %X:\n%s\n%s%s%s%s%s\n", | |
911 | __func__, stat, | |
912 | stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY", | |
913 | (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "", | |
914 | (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "", | |
915 | (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "", | |
916 | (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "", | |
917 | (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : ""); | |
918 | } | |
919 | #endif | |
920 | } | |
921 | ||
922 | static irqreturn_t adf7242_isr(int irq, void *data) | |
923 | { | |
924 | struct adf7242_local *lp = data; | |
925 | unsigned xmit; | |
926 | u8 irq1; | |
927 | ||
928 | adf7242_wait_status(lp, RC_STATUS_PHY_RDY, RC_STATUS_MASK, __LINE__); | |
929 | ||
930 | adf7242_read_reg(lp, REG_IRQ1_SRC1, &irq1); | |
931 | adf7242_write_reg(lp, REG_IRQ1_SRC1, irq1); | |
932 | ||
933 | if (!(irq1 & (IRQ_RX_PKT_RCVD | IRQ_CSMA_CA))) | |
934 | dev_err(&lp->spi->dev, "%s :ERROR IRQ1 = 0x%X\n", | |
935 | __func__, irq1); | |
936 | ||
937 | adf7242_debug(irq1); | |
938 | ||
939 | xmit = test_bit(FLAG_XMIT, &lp->flags); | |
940 | ||
941 | if (xmit && (irq1 & IRQ_CSMA_CA)) { | |
942 | if (ADF7242_REPORT_CSMA_CA_STAT) { | |
943 | u8 astat; | |
944 | ||
945 | adf7242_read_reg(lp, REG_AUTO_STATUS, &astat); | |
946 | astat &= AUTO_STATUS_MASK; | |
947 | ||
948 | dev_dbg(&lp->spi->dev, "AUTO_STATUS = %X:\n%s%s%s%s\n", | |
949 | astat, | |
950 | astat == SUCCESS ? "SUCCESS" : "", | |
951 | astat == | |
952 | SUCCESS_DATPEND ? "SUCCESS_DATPEND" : "", | |
953 | astat == FAILURE_CSMACA ? "FAILURE_CSMACA" : "", | |
954 | astat == FAILURE_NOACK ? "FAILURE_NOACK" : ""); | |
955 | ||
956 | /* save CSMA-CA completion status */ | |
957 | lp->tx_stat = astat; | |
958 | } else { | |
959 | lp->tx_stat = SUCCESS; | |
960 | } | |
961 | complete(&lp->tx_complete); | |
962 | } else if (!xmit && (irq1 & IRQ_RX_PKT_RCVD) && | |
963 | (irq1 & IRQ_FRAME_VALID)) { | |
964 | adf7242_rx(lp); | |
965 | } else if (!xmit && test_bit(FLAG_START, &lp->flags)) { | |
966 | /* Invalid packet received - drop it and restart */ | |
967 | dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X\n", | |
968 | __func__, __LINE__, irq1); | |
969 | adf7242_cmd(lp, CMD_RC_PHY_RDY); | |
970 | adf7242_write_reg(lp, REG_IRQ1_SRC1, 0xFF); | |
971 | adf7242_cmd(lp, CMD_RC_RX); | |
972 | } else { | |
973 | /* This can only be xmit without IRQ, likely a RX packet. | |
974 | * we get an TX IRQ shortly - do nothing or let the xmit | |
975 | * timeout handle this | |
976 | */ | |
977 | dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X, xmit %d\n", | |
978 | __func__, __LINE__, irq1, xmit); | |
979 | complete(&lp->tx_complete); | |
980 | } | |
981 | ||
982 | return IRQ_HANDLED; | |
983 | } | |
984 | ||
985 | static int adf7242_soft_reset(struct adf7242_local *lp, int line) | |
986 | { | |
987 | dev_warn(&lp->spi->dev, "%s (line %d)\n", __func__, line); | |
988 | ||
989 | if (test_bit(FLAG_START, &lp->flags)) | |
990 | disable_irq_nosync(lp->spi->irq); | |
991 | ||
992 | adf7242_cmd(lp, CMD_RC_PC_RESET_NO_WAIT); | |
993 | usleep_range(200, 250); | |
994 | adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2)); | |
995 | adf7242_cmd(lp, CMD_RC_PHY_RDY); | |
996 | adf7242_set_promiscuous_mode(lp->hw, lp->promiscuous); | |
997 | adf7242_set_csma_params(lp->hw, lp->min_be, lp->max_be, | |
998 | lp->max_cca_retries); | |
999 | adf7242_write_reg(lp, REG_IRQ1_SRC1, 0xFF); | |
1000 | ||
1001 | if (test_bit(FLAG_START, &lp->flags)) { | |
1002 | enable_irq(lp->spi->irq); | |
1003 | return adf7242_cmd(lp, CMD_RC_RX); | |
1004 | } | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | static int adf7242_hw_init(struct adf7242_local *lp) | |
1010 | { | |
1011 | int ret; | |
1012 | const struct firmware *fw; | |
1013 | ||
1014 | adf7242_cmd(lp, CMD_RC_RESET); | |
1015 | adf7242_cmd(lp, CMD_RC_IDLE); | |
1016 | ||
1017 | /* get ADF7242 addon firmware | |
1018 | * build this driver as module | |
1019 | * and place under /lib/firmware/adf7242_firmware.bin | |
1020 | * or compile firmware into the kernel. | |
1021 | */ | |
1022 | ret = request_firmware(&fw, FIRMWARE, &lp->spi->dev); | |
1023 | if (ret) { | |
1024 | dev_err(&lp->spi->dev, | |
1025 | "request_firmware() failed with %d\n", ret); | |
1026 | return ret; | |
1027 | } | |
1028 | ||
1029 | ret = adf7242_upload_firmware(lp, (u8 *)fw->data, fw->size); | |
1030 | if (ret) { | |
1031 | dev_err(&lp->spi->dev, | |
1032 | "upload firmware failed with %d\n", ret); | |
cd9d7213 | 1033 | release_firmware(fw); |
7302b9d9 MH |
1034 | return ret; |
1035 | } | |
1036 | ||
1037 | ret = adf7242_verify_firmware(lp, (u8 *)fw->data, fw->size); | |
1038 | if (ret) { | |
1039 | dev_err(&lp->spi->dev, | |
1040 | "verify firmware failed with %d\n", ret); | |
cd9d7213 | 1041 | release_firmware(fw); |
7302b9d9 MH |
1042 | return ret; |
1043 | } | |
1044 | ||
1045 | adf7242_cmd(lp, CMD_RC_PC_RESET); | |
1046 | ||
1047 | release_firmware(fw); | |
1048 | ||
1049 | adf7242_write_reg(lp, REG_FFILT_CFG, | |
1050 | ACCEPT_BEACON_FRAMES | | |
1051 | ACCEPT_DATA_FRAMES | | |
1052 | ACCEPT_MACCMD_FRAMES | | |
1053 | ACCEPT_RESERVED_FRAMES); | |
1054 | ||
1055 | adf7242_write_reg(lp, REG_AUTO_CFG, RX_AUTO_ACK_EN); | |
1056 | ||
1057 | adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2)); | |
1058 | ||
1059 | adf7242_write_reg(lp, REG_EXTPA_MSC, 0xF1); | |
1060 | adf7242_write_reg(lp, REG_RXFE_CFG, 0x1D); | |
1061 | ||
1062 | adf7242_write_reg(lp, REG_IRQ1_EN0, 0); | |
1063 | adf7242_write_reg(lp, REG_IRQ1_EN1, IRQ_RX_PKT_RCVD | IRQ_CSMA_CA); | |
1064 | ||
1065 | adf7242_write_reg(lp, REG_IRQ1_SRC1, 0xFF); | |
1066 | adf7242_write_reg(lp, REG_IRQ1_SRC0, 0xFF); | |
1067 | ||
1068 | adf7242_cmd(lp, CMD_RC_IDLE); | |
1069 | ||
1070 | return 0; | |
1071 | } | |
1072 | ||
1073 | static int adf7242_stats_show(struct seq_file *file, void *offset) | |
1074 | { | |
1075 | struct adf7242_local *lp = spi_get_drvdata(file->private); | |
1076 | u8 stat, irq1; | |
1077 | ||
1078 | adf7242_status(lp, &stat); | |
1079 | adf7242_read_reg(lp, REG_IRQ1_SRC1, &irq1); | |
1080 | ||
1081 | seq_printf(file, "IRQ1 = %X:\n%s%s%s%s%s%s%s%s\n", irq1, | |
1082 | irq1 & IRQ_CCA_COMPLETE ? "IRQ_CCA_COMPLETE\n" : "", | |
1083 | irq1 & IRQ_SFD_RX ? "IRQ_SFD_RX\n" : "", | |
1084 | irq1 & IRQ_SFD_TX ? "IRQ_SFD_TX\n" : "", | |
1085 | irq1 & IRQ_RX_PKT_RCVD ? "IRQ_RX_PKT_RCVD\n" : "", | |
1086 | irq1 & IRQ_TX_PKT_SENT ? "IRQ_TX_PKT_SENT\n" : "", | |
1087 | irq1 & IRQ_CSMA_CA ? "IRQ_CSMA_CA\n" : "", | |
1088 | irq1 & IRQ_FRAME_VALID ? "IRQ_FRAME_VALID\n" : "", | |
1089 | irq1 & IRQ_ADDRESS_VALID ? "IRQ_ADDRESS_VALID\n" : ""); | |
1090 | ||
1091 | seq_printf(file, "STATUS = %X:\n%s\n%s%s%s%s%s\n", stat, | |
1092 | stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY", | |
1093 | (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "", | |
1094 | (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "", | |
1095 | (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "", | |
1096 | (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "", | |
1097 | (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : ""); | |
1098 | ||
1099 | seq_printf(file, "RSSI = %d\n", lp->rssi); | |
1100 | ||
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | static int adf7242_debugfs_init(struct adf7242_local *lp) | |
1105 | { | |
1106 | char debugfs_dir_name[DNAME_INLINE_LEN + 1] = "adf7242-"; | |
1107 | struct dentry *stats; | |
1108 | ||
1109 | strncat(debugfs_dir_name, dev_name(&lp->spi->dev), DNAME_INLINE_LEN); | |
1110 | ||
1111 | lp->debugfs_root = debugfs_create_dir(debugfs_dir_name, NULL); | |
1112 | if (IS_ERR_OR_NULL(lp->debugfs_root)) | |
1113 | return PTR_ERR_OR_ZERO(lp->debugfs_root); | |
1114 | ||
1115 | stats = debugfs_create_devm_seqfile(&lp->spi->dev, "status", | |
1116 | lp->debugfs_root, | |
1117 | adf7242_stats_show); | |
1118 | return PTR_ERR_OR_ZERO(stats); | |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | static const s32 adf7242_powers[] = { | |
1124 | 500, 400, 300, 200, 100, 0, -100, -200, -300, -400, -500, -600, -700, | |
1125 | -800, -900, -1000, -1100, -1200, -1300, -1400, -1500, -1600, -1700, | |
1126 | -1800, -1900, -2000, -2100, -2200, -2300, -2400, -2500, -2600, | |
1127 | }; | |
1128 | ||
1129 | static const s32 adf7242_ed_levels[] = { | |
1130 | -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100, | |
1131 | -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100, | |
1132 | -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100, | |
1133 | -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100, | |
1134 | -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100, | |
1135 | -4000, -3900, -3800, -3700, -3600, -3500, -3400, -3200, -3100, -3000 | |
1136 | }; | |
1137 | ||
1138 | static int adf7242_probe(struct spi_device *spi) | |
1139 | { | |
1140 | struct ieee802154_hw *hw; | |
1141 | struct adf7242_local *lp; | |
1142 | int ret, irq_type; | |
1143 | ||
1144 | if (!spi->irq) { | |
1145 | dev_err(&spi->dev, "no IRQ specified\n"); | |
1146 | return -EINVAL; | |
1147 | } | |
1148 | ||
1149 | hw = ieee802154_alloc_hw(sizeof(*lp), &adf7242_ops); | |
1150 | if (!hw) | |
1151 | return -ENOMEM; | |
1152 | ||
1153 | lp = hw->priv; | |
1154 | lp->hw = hw; | |
1155 | lp->spi = spi; | |
1156 | ||
1157 | hw->priv = lp; | |
1158 | hw->parent = &spi->dev; | |
1159 | hw->extra_tx_headroom = 0; | |
1160 | ||
1161 | /* We support only 2.4 Ghz */ | |
1162 | hw->phy->supported.channels[0] = 0x7FFF800; | |
1163 | ||
1164 | hw->flags = IEEE802154_HW_OMIT_CKSUM | | |
1165 | IEEE802154_HW_CSMA_PARAMS | | |
1166 | IEEE802154_HW_FRAME_RETRIES | IEEE802154_HW_AFILT | | |
1167 | IEEE802154_HW_PROMISCUOUS; | |
1168 | ||
1169 | hw->phy->flags = WPAN_PHY_FLAG_TXPOWER | | |
1170 | WPAN_PHY_FLAG_CCA_ED_LEVEL | | |
1171 | WPAN_PHY_FLAG_CCA_MODE; | |
1172 | ||
1173 | hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY); | |
1174 | ||
1175 | hw->phy->supported.cca_ed_levels = adf7242_ed_levels; | |
1176 | hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(adf7242_ed_levels); | |
1177 | ||
1178 | hw->phy->cca.mode = NL802154_CCA_ENERGY; | |
1179 | ||
1180 | hw->phy->supported.tx_powers = adf7242_powers; | |
1181 | hw->phy->supported.tx_powers_size = ARRAY_SIZE(adf7242_powers); | |
1182 | ||
1183 | hw->phy->supported.min_minbe = 0; | |
1184 | hw->phy->supported.max_minbe = 8; | |
1185 | ||
1186 | hw->phy->supported.min_maxbe = 3; | |
1187 | hw->phy->supported.max_maxbe = 8; | |
1188 | ||
1189 | hw->phy->supported.min_frame_retries = 0; | |
1190 | hw->phy->supported.max_frame_retries = 15; | |
1191 | ||
1192 | hw->phy->supported.min_csma_backoffs = 0; | |
1193 | hw->phy->supported.max_csma_backoffs = 5; | |
1194 | ||
1195 | ieee802154_random_extended_addr(&hw->phy->perm_extended_addr); | |
1196 | ||
1197 | mutex_init(&lp->bmux); | |
1198 | init_completion(&lp->tx_complete); | |
1199 | ||
1200 | /* Setup Status Message */ | |
1201 | lp->stat_xfer.len = 1; | |
1202 | lp->stat_xfer.tx_buf = &lp->buf_stat_tx; | |
1203 | lp->stat_xfer.rx_buf = &lp->buf_stat_rx; | |
1204 | lp->buf_stat_tx = CMD_SPI_NOP; | |
1205 | ||
1206 | spi_message_init(&lp->stat_msg); | |
1207 | spi_message_add_tail(&lp->stat_xfer, &lp->stat_msg); | |
1208 | ||
1209 | spi_set_drvdata(spi, lp); | |
1210 | ||
1211 | ret = adf7242_hw_init(lp); | |
1212 | if (ret) | |
1213 | goto err_hw_init; | |
1214 | ||
1215 | irq_type = irq_get_trigger_type(spi->irq); | |
1216 | if (!irq_type) | |
1217 | irq_type = IRQF_TRIGGER_HIGH; | |
1218 | ||
1219 | ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, adf7242_isr, | |
1220 | irq_type | IRQF_ONESHOT, | |
1221 | dev_name(&spi->dev), lp); | |
1222 | if (ret) | |
1223 | goto err_hw_init; | |
1224 | ||
1225 | disable_irq(spi->irq); | |
1226 | ||
1227 | ret = ieee802154_register_hw(lp->hw); | |
1228 | if (ret) | |
1229 | goto err_hw_init; | |
1230 | ||
1231 | dev_set_drvdata(&spi->dev, lp); | |
1232 | ||
1233 | adf7242_debugfs_init(lp); | |
1234 | ||
1235 | dev_info(&spi->dev, "mac802154 IRQ-%d registered\n", spi->irq); | |
1236 | ||
1237 | return ret; | |
1238 | ||
1239 | err_hw_init: | |
1240 | mutex_destroy(&lp->bmux); | |
1241 | ieee802154_free_hw(lp->hw); | |
1242 | ||
1243 | return ret; | |
1244 | } | |
1245 | ||
1246 | static int adf7242_remove(struct spi_device *spi) | |
1247 | { | |
1248 | struct adf7242_local *lp = spi_get_drvdata(spi); | |
1249 | ||
1250 | if (!IS_ERR_OR_NULL(lp->debugfs_root)) | |
1251 | debugfs_remove_recursive(lp->debugfs_root); | |
1252 | ||
1253 | ieee802154_unregister_hw(lp->hw); | |
1254 | mutex_destroy(&lp->bmux); | |
1255 | ieee802154_free_hw(lp->hw); | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | ||
1260 | static const struct of_device_id adf7242_of_match[] = { | |
1261 | { .compatible = "adi,adf7242", }, | |
1262 | { }, | |
1263 | }; | |
1264 | MODULE_DEVICE_TABLE(of, adf7242_of_match); | |
1265 | ||
1266 | static const struct spi_device_id adf7242_device_id[] = { | |
1267 | { .name = "adf7242", }, | |
1268 | { }, | |
1269 | }; | |
1270 | MODULE_DEVICE_TABLE(spi, adf7242_device_id); | |
1271 | ||
1272 | static struct spi_driver adf7242_driver = { | |
1273 | .id_table = adf7242_device_id, | |
1274 | .driver = { | |
1275 | .of_match_table = of_match_ptr(adf7242_of_match), | |
1276 | .name = "adf7242", | |
1277 | .owner = THIS_MODULE, | |
1278 | }, | |
1279 | .probe = adf7242_probe, | |
1280 | .remove = adf7242_remove, | |
1281 | }; | |
1282 | ||
1283 | module_spi_driver(adf7242_driver); | |
1284 | ||
1285 | MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); | |
1286 | MODULE_DESCRIPTION("ADF7242 IEEE802.15.4 Transceiver Driver"); | |
1287 | MODULE_LICENSE("GPL"); |