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0da6bc8c VB |
1 | /* Driver for TI CC2520 802.15.4 Wireless-PAN Networking controller |
2 | * | |
3 | * Copyright (C) 2014 Varka Bhadram <varkab@cdac.in> | |
4 | * Md.Jamal Mohiuddin <mjmohiuddin@cdac.in> | |
5 | * P Sowjanya <sowjanyap@cdac.in> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/gpio.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/spi/spi.h> | |
18 | #include <linux/spi/cc2520.h> | |
19 | #include <linux/workqueue.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/skbuff.h> | |
0da6bc8c | 22 | #include <linux/of_gpio.h> |
4ca24aca | 23 | #include <linux/ieee802154.h> |
59869ebf BC |
24 | #include <linux/crc-ccitt.h> |
25 | #include <asm/unaligned.h> | |
0da6bc8c VB |
26 | |
27 | #include <net/mac802154.h> | |
5ad60d36 | 28 | #include <net/cfg802154.h> |
0da6bc8c VB |
29 | |
30 | #define SPI_COMMAND_BUFFER 3 | |
31 | #define HIGH 1 | |
32 | #define LOW 0 | |
33 | #define STATE_IDLE 0 | |
34 | #define RSSI_VALID 0 | |
35 | #define RSSI_OFFSET 78 | |
36 | ||
37 | #define CC2520_RAM_SIZE 640 | |
38 | #define CC2520_FIFO_SIZE 128 | |
39 | ||
40 | #define CC2520RAM_TXFIFO 0x100 | |
41 | #define CC2520RAM_RXFIFO 0x180 | |
42 | #define CC2520RAM_IEEEADDR 0x3EA | |
43 | #define CC2520RAM_PANID 0x3F2 | |
44 | #define CC2520RAM_SHORTADDR 0x3F4 | |
45 | ||
46 | #define CC2520_FREG_MASK 0x3F | |
47 | ||
48 | /* status byte values */ | |
908edc54 MJ |
49 | #define CC2520_STATUS_XOSC32M_STABLE BIT(7) |
50 | #define CC2520_STATUS_RSSI_VALID BIT(6) | |
51 | #define CC2520_STATUS_TX_UNDERFLOW BIT(3) | |
0da6bc8c VB |
52 | |
53 | /* IEEE-802.15.4 defined constants (2.4 GHz logical channels) */ | |
54 | #define CC2520_MINCHANNEL 11 | |
55 | #define CC2520_MAXCHANNEL 26 | |
56 | #define CC2520_CHANNEL_SPACING 5 | |
57 | ||
58 | /* command strobes */ | |
59 | #define CC2520_CMD_SNOP 0x00 | |
60 | #define CC2520_CMD_IBUFLD 0x02 | |
61 | #define CC2520_CMD_SIBUFEX 0x03 | |
62 | #define CC2520_CMD_SSAMPLECCA 0x04 | |
63 | #define CC2520_CMD_SRES 0x0f | |
64 | #define CC2520_CMD_MEMORY_MASK 0x0f | |
65 | #define CC2520_CMD_MEMORY_READ 0x10 | |
66 | #define CC2520_CMD_MEMORY_WRITE 0x20 | |
67 | #define CC2520_CMD_RXBUF 0x30 | |
68 | #define CC2520_CMD_RXBUFCP 0x38 | |
69 | #define CC2520_CMD_RXBUFMOV 0x32 | |
70 | #define CC2520_CMD_TXBUF 0x3A | |
71 | #define CC2520_CMD_TXBUFCP 0x3E | |
72 | #define CC2520_CMD_RANDOM 0x3C | |
73 | #define CC2520_CMD_SXOSCON 0x40 | |
74 | #define CC2520_CMD_STXCAL 0x41 | |
75 | #define CC2520_CMD_SRXON 0x42 | |
76 | #define CC2520_CMD_STXON 0x43 | |
77 | #define CC2520_CMD_STXONCCA 0x44 | |
78 | #define CC2520_CMD_SRFOFF 0x45 | |
79 | #define CC2520_CMD_SXOSCOFF 0x46 | |
80 | #define CC2520_CMD_SFLUSHRX 0x47 | |
81 | #define CC2520_CMD_SFLUSHTX 0x48 | |
82 | #define CC2520_CMD_SACK 0x49 | |
83 | #define CC2520_CMD_SACKPEND 0x4A | |
84 | #define CC2520_CMD_SNACK 0x4B | |
85 | #define CC2520_CMD_SRXMASKBITSET 0x4C | |
86 | #define CC2520_CMD_SRXMASKBITCLR 0x4D | |
87 | #define CC2520_CMD_RXMASKAND 0x4E | |
88 | #define CC2520_CMD_RXMASKOR 0x4F | |
89 | #define CC2520_CMD_MEMCP 0x50 | |
90 | #define CC2520_CMD_MEMCPR 0x52 | |
91 | #define CC2520_CMD_MEMXCP 0x54 | |
92 | #define CC2520_CMD_MEMXWR 0x56 | |
93 | #define CC2520_CMD_BCLR 0x58 | |
94 | #define CC2520_CMD_BSET 0x59 | |
95 | #define CC2520_CMD_CTR_UCTR 0x60 | |
96 | #define CC2520_CMD_CBCMAC 0x64 | |
97 | #define CC2520_CMD_UCBCMAC 0x66 | |
98 | #define CC2520_CMD_CCM 0x68 | |
99 | #define CC2520_CMD_UCCM 0x6A | |
100 | #define CC2520_CMD_ECB 0x70 | |
101 | #define CC2520_CMD_ECBO 0x72 | |
102 | #define CC2520_CMD_ECBX 0x74 | |
103 | #define CC2520_CMD_INC 0x78 | |
104 | #define CC2520_CMD_ABORT 0x7F | |
105 | #define CC2520_CMD_REGISTER_READ 0x80 | |
106 | #define CC2520_CMD_REGISTER_WRITE 0xC0 | |
107 | ||
108 | /* status registers */ | |
109 | #define CC2520_CHIPID 0x40 | |
110 | #define CC2520_VERSION 0x42 | |
111 | #define CC2520_EXTCLOCK 0x44 | |
112 | #define CC2520_MDMCTRL0 0x46 | |
113 | #define CC2520_MDMCTRL1 0x47 | |
114 | #define CC2520_FREQEST 0x48 | |
115 | #define CC2520_RXCTRL 0x4A | |
116 | #define CC2520_FSCTRL 0x4C | |
117 | #define CC2520_FSCAL0 0x4E | |
118 | #define CC2520_FSCAL1 0x4F | |
119 | #define CC2520_FSCAL2 0x50 | |
120 | #define CC2520_FSCAL3 0x51 | |
121 | #define CC2520_AGCCTRL0 0x52 | |
122 | #define CC2520_AGCCTRL1 0x53 | |
123 | #define CC2520_AGCCTRL2 0x54 | |
124 | #define CC2520_AGCCTRL3 0x55 | |
125 | #define CC2520_ADCTEST0 0x56 | |
126 | #define CC2520_ADCTEST1 0x57 | |
127 | #define CC2520_ADCTEST2 0x58 | |
128 | #define CC2520_MDMTEST0 0x5A | |
129 | #define CC2520_MDMTEST1 0x5B | |
130 | #define CC2520_DACTEST0 0x5C | |
131 | #define CC2520_DACTEST1 0x5D | |
132 | #define CC2520_ATEST 0x5E | |
133 | #define CC2520_DACTEST2 0x5F | |
134 | #define CC2520_PTEST0 0x60 | |
135 | #define CC2520_PTEST1 0x61 | |
136 | #define CC2520_RESERVED 0x62 | |
137 | #define CC2520_DPUBIST 0x7A | |
138 | #define CC2520_ACTBIST 0x7C | |
139 | #define CC2520_RAMBIST 0x7E | |
140 | ||
141 | /* frame registers */ | |
142 | #define CC2520_FRMFILT0 0x00 | |
143 | #define CC2520_FRMFILT1 0x01 | |
144 | #define CC2520_SRCMATCH 0x02 | |
145 | #define CC2520_SRCSHORTEN0 0x04 | |
146 | #define CC2520_SRCSHORTEN1 0x05 | |
147 | #define CC2520_SRCSHORTEN2 0x06 | |
148 | #define CC2520_SRCEXTEN0 0x08 | |
149 | #define CC2520_SRCEXTEN1 0x09 | |
150 | #define CC2520_SRCEXTEN2 0x0A | |
151 | #define CC2520_FRMCTRL0 0x0C | |
152 | #define CC2520_FRMCTRL1 0x0D | |
153 | #define CC2520_RXENABLE0 0x0E | |
154 | #define CC2520_RXENABLE1 0x0F | |
155 | #define CC2520_EXCFLAG0 0x10 | |
156 | #define CC2520_EXCFLAG1 0x11 | |
157 | #define CC2520_EXCFLAG2 0x12 | |
158 | #define CC2520_EXCMASKA0 0x14 | |
159 | #define CC2520_EXCMASKA1 0x15 | |
160 | #define CC2520_EXCMASKA2 0x16 | |
161 | #define CC2520_EXCMASKB0 0x18 | |
162 | #define CC2520_EXCMASKB1 0x19 | |
163 | #define CC2520_EXCMASKB2 0x1A | |
164 | #define CC2520_EXCBINDX0 0x1C | |
165 | #define CC2520_EXCBINDX1 0x1D | |
166 | #define CC2520_EXCBINDY0 0x1E | |
167 | #define CC2520_EXCBINDY1 0x1F | |
168 | #define CC2520_GPIOCTRL0 0x20 | |
169 | #define CC2520_GPIOCTRL1 0x21 | |
170 | #define CC2520_GPIOCTRL2 0x22 | |
171 | #define CC2520_GPIOCTRL3 0x23 | |
172 | #define CC2520_GPIOCTRL4 0x24 | |
173 | #define CC2520_GPIOCTRL5 0x25 | |
174 | #define CC2520_GPIOPOLARITY 0x26 | |
175 | #define CC2520_GPIOCTRL 0x28 | |
176 | #define CC2520_DPUCON 0x2A | |
177 | #define CC2520_DPUSTAT 0x2C | |
178 | #define CC2520_FREQCTRL 0x2E | |
179 | #define CC2520_FREQTUNE 0x2F | |
180 | #define CC2520_TXPOWER 0x30 | |
181 | #define CC2520_TXCTRL 0x31 | |
182 | #define CC2520_FSMSTAT0 0x32 | |
183 | #define CC2520_FSMSTAT1 0x33 | |
184 | #define CC2520_FIFOPCTRL 0x34 | |
185 | #define CC2520_FSMCTRL 0x35 | |
186 | #define CC2520_CCACTRL0 0x36 | |
187 | #define CC2520_CCACTRL1 0x37 | |
188 | #define CC2520_RSSI 0x38 | |
189 | #define CC2520_RSSISTAT 0x39 | |
190 | #define CC2520_RXFIRST 0x3C | |
191 | #define CC2520_RXFIFOCNT 0x3E | |
192 | #define CC2520_TXFIFOCNT 0x3F | |
193 | ||
59869ebf BC |
194 | /* CC2520_FRMFILT0 */ |
195 | #define FRMFILT0_FRAME_FILTER_EN BIT(0) | |
196 | #define FRMFILT0_PAN_COORDINATOR BIT(1) | |
197 | ||
198 | /* CC2520_FRMCTRL0 */ | |
199 | #define FRMCTRL0_AUTOACK BIT(5) | |
200 | #define FRMCTRL0_AUTOCRC BIT(6) | |
201 | ||
202 | /* CC2520_FRMCTRL1 */ | |
203 | #define FRMCTRL1_SET_RXENMASK_ON_TX BIT(0) | |
204 | #define FRMCTRL1_IGNORE_TX_UNDERF BIT(1) | |
205 | ||
0da6bc8c VB |
206 | /* Driver private information */ |
207 | struct cc2520_private { | |
208 | struct spi_device *spi; /* SPI device structure */ | |
5a504397 | 209 | struct ieee802154_hw *hw; /* IEEE-802.15.4 device */ |
0da6bc8c VB |
210 | u8 *buf; /* SPI TX/Rx data buffer */ |
211 | struct mutex buffer_mutex; /* SPI buffer mutex */ | |
212 | bool is_tx; /* Flag for sync b/w Tx and Rx */ | |
1a1bc59c | 213 | bool amplified; /* Flag for CC2591 */ |
0da6bc8c VB |
214 | int fifo_pin; /* FIFO GPIO pin number */ |
215 | struct work_struct fifop_irqwork;/* Workqueue for FIFOP */ | |
216 | spinlock_t lock; /* Lock for is_tx*/ | |
217 | struct completion tx_complete; /* Work completion for Tx */ | |
59869ebf | 218 | bool promiscuous; /* Flag for promiscuous mode */ |
0da6bc8c VB |
219 | }; |
220 | ||
221 | /* Generic Functions */ | |
222 | static int | |
223 | cc2520_cmd_strobe(struct cc2520_private *priv, u8 cmd) | |
224 | { | |
225 | int ret; | |
226 | u8 status = 0xff; | |
227 | struct spi_message msg; | |
228 | struct spi_transfer xfer = { | |
229 | .len = 0, | |
230 | .tx_buf = priv->buf, | |
231 | .rx_buf = priv->buf, | |
232 | }; | |
233 | ||
234 | spi_message_init(&msg); | |
235 | spi_message_add_tail(&xfer, &msg); | |
236 | ||
237 | mutex_lock(&priv->buffer_mutex); | |
238 | priv->buf[xfer.len++] = cmd; | |
239 | dev_vdbg(&priv->spi->dev, | |
240 | "command strobe buf[0] = %02x\n", | |
241 | priv->buf[0]); | |
242 | ||
243 | ret = spi_sync(priv->spi, &msg); | |
244 | if (!ret) | |
245 | status = priv->buf[0]; | |
246 | dev_vdbg(&priv->spi->dev, | |
247 | "buf[0] = %02x\n", priv->buf[0]); | |
248 | mutex_unlock(&priv->buffer_mutex); | |
249 | ||
250 | return ret; | |
251 | } | |
252 | ||
253 | static int | |
254 | cc2520_get_status(struct cc2520_private *priv, u8 *status) | |
255 | { | |
256 | int ret; | |
257 | struct spi_message msg; | |
258 | struct spi_transfer xfer = { | |
259 | .len = 0, | |
260 | .tx_buf = priv->buf, | |
261 | .rx_buf = priv->buf, | |
262 | }; | |
263 | ||
264 | spi_message_init(&msg); | |
265 | spi_message_add_tail(&xfer, &msg); | |
266 | ||
267 | mutex_lock(&priv->buffer_mutex); | |
268 | priv->buf[xfer.len++] = CC2520_CMD_SNOP; | |
269 | dev_vdbg(&priv->spi->dev, | |
270 | "get status command buf[0] = %02x\n", priv->buf[0]); | |
271 | ||
272 | ret = spi_sync(priv->spi, &msg); | |
273 | if (!ret) | |
274 | *status = priv->buf[0]; | |
275 | dev_vdbg(&priv->spi->dev, | |
276 | "buf[0] = %02x\n", priv->buf[0]); | |
277 | mutex_unlock(&priv->buffer_mutex); | |
278 | ||
279 | return ret; | |
280 | } | |
281 | ||
282 | static int | |
283 | cc2520_write_register(struct cc2520_private *priv, u8 reg, u8 value) | |
284 | { | |
285 | int status; | |
286 | struct spi_message msg; | |
287 | struct spi_transfer xfer = { | |
288 | .len = 0, | |
289 | .tx_buf = priv->buf, | |
290 | .rx_buf = priv->buf, | |
291 | }; | |
292 | ||
293 | spi_message_init(&msg); | |
294 | spi_message_add_tail(&xfer, &msg); | |
295 | ||
296 | mutex_lock(&priv->buffer_mutex); | |
297 | ||
298 | if (reg <= CC2520_FREG_MASK) { | |
299 | priv->buf[xfer.len++] = CC2520_CMD_REGISTER_WRITE | reg; | |
300 | priv->buf[xfer.len++] = value; | |
301 | } else { | |
302 | priv->buf[xfer.len++] = CC2520_CMD_MEMORY_WRITE; | |
303 | priv->buf[xfer.len++] = reg; | |
304 | priv->buf[xfer.len++] = value; | |
305 | } | |
306 | status = spi_sync(priv->spi, &msg); | |
307 | if (msg.status) | |
308 | status = msg.status; | |
309 | ||
310 | mutex_unlock(&priv->buffer_mutex); | |
311 | ||
312 | return status; | |
313 | } | |
314 | ||
315 | static int | |
316 | cc2520_write_ram(struct cc2520_private *priv, u16 reg, u8 len, u8 *data) | |
317 | { | |
318 | int status; | |
319 | struct spi_message msg; | |
320 | struct spi_transfer xfer_head = { | |
321 | .len = 0, | |
322 | .tx_buf = priv->buf, | |
323 | .rx_buf = priv->buf, | |
324 | }; | |
325 | ||
326 | struct spi_transfer xfer_buf = { | |
327 | .len = len, | |
328 | .tx_buf = data, | |
329 | }; | |
330 | ||
331 | mutex_lock(&priv->buffer_mutex); | |
332 | priv->buf[xfer_head.len++] = (CC2520_CMD_MEMORY_WRITE | | |
333 | ((reg >> 8) & 0xff)); | |
334 | priv->buf[xfer_head.len++] = reg & 0xff; | |
335 | ||
336 | spi_message_init(&msg); | |
337 | spi_message_add_tail(&xfer_head, &msg); | |
338 | spi_message_add_tail(&xfer_buf, &msg); | |
339 | ||
340 | status = spi_sync(priv->spi, &msg); | |
341 | dev_dbg(&priv->spi->dev, "spi status = %d\n", status); | |
342 | if (msg.status) | |
343 | status = msg.status; | |
344 | ||
345 | mutex_unlock(&priv->buffer_mutex); | |
346 | return status; | |
347 | } | |
348 | ||
349 | static int | |
350 | cc2520_read_register(struct cc2520_private *priv, u8 reg, u8 *data) | |
351 | { | |
352 | int status; | |
353 | struct spi_message msg; | |
354 | struct spi_transfer xfer1 = { | |
355 | .len = 0, | |
356 | .tx_buf = priv->buf, | |
357 | .rx_buf = priv->buf, | |
358 | }; | |
359 | ||
360 | struct spi_transfer xfer2 = { | |
361 | .len = 1, | |
362 | .rx_buf = data, | |
363 | }; | |
364 | ||
365 | spi_message_init(&msg); | |
366 | spi_message_add_tail(&xfer1, &msg); | |
367 | spi_message_add_tail(&xfer2, &msg); | |
368 | ||
369 | mutex_lock(&priv->buffer_mutex); | |
370 | priv->buf[xfer1.len++] = CC2520_CMD_MEMORY_READ; | |
371 | priv->buf[xfer1.len++] = reg; | |
372 | ||
373 | status = spi_sync(priv->spi, &msg); | |
374 | dev_dbg(&priv->spi->dev, | |
375 | "spi status = %d\n", status); | |
376 | if (msg.status) | |
377 | status = msg.status; | |
378 | ||
379 | mutex_unlock(&priv->buffer_mutex); | |
380 | ||
381 | return status; | |
382 | } | |
383 | ||
384 | static int | |
59869ebf | 385 | cc2520_write_txfifo(struct cc2520_private *priv, u8 pkt_len, u8 *data, u8 len) |
0da6bc8c VB |
386 | { |
387 | int status; | |
388 | ||
389 | /* length byte must include FCS even | |
390 | * if it is calculated in the hardware | |
391 | */ | |
59869ebf | 392 | int len_byte = pkt_len; |
0da6bc8c VB |
393 | |
394 | struct spi_message msg; | |
395 | ||
396 | struct spi_transfer xfer_head = { | |
397 | .len = 0, | |
398 | .tx_buf = priv->buf, | |
399 | .rx_buf = priv->buf, | |
400 | }; | |
401 | struct spi_transfer xfer_len = { | |
402 | .len = 1, | |
403 | .tx_buf = &len_byte, | |
404 | }; | |
405 | struct spi_transfer xfer_buf = { | |
406 | .len = len, | |
407 | .tx_buf = data, | |
408 | }; | |
409 | ||
410 | spi_message_init(&msg); | |
411 | spi_message_add_tail(&xfer_head, &msg); | |
412 | spi_message_add_tail(&xfer_len, &msg); | |
413 | spi_message_add_tail(&xfer_buf, &msg); | |
414 | ||
415 | mutex_lock(&priv->buffer_mutex); | |
416 | priv->buf[xfer_head.len++] = CC2520_CMD_TXBUF; | |
417 | dev_vdbg(&priv->spi->dev, | |
418 | "TX_FIFO cmd buf[0] = %02x\n", priv->buf[0]); | |
419 | ||
420 | status = spi_sync(priv->spi, &msg); | |
421 | dev_vdbg(&priv->spi->dev, "status = %d\n", status); | |
422 | if (msg.status) | |
423 | status = msg.status; | |
424 | dev_vdbg(&priv->spi->dev, "status = %d\n", status); | |
425 | dev_vdbg(&priv->spi->dev, "buf[0] = %02x\n", priv->buf[0]); | |
426 | mutex_unlock(&priv->buffer_mutex); | |
427 | ||
428 | return status; | |
429 | } | |
430 | ||
431 | static int | |
59869ebf | 432 | cc2520_read_rxfifo(struct cc2520_private *priv, u8 *data, u8 len) |
0da6bc8c VB |
433 | { |
434 | int status; | |
435 | struct spi_message msg; | |
436 | ||
437 | struct spi_transfer xfer_head = { | |
438 | .len = 0, | |
439 | .tx_buf = priv->buf, | |
440 | .rx_buf = priv->buf, | |
441 | }; | |
442 | struct spi_transfer xfer_buf = { | |
443 | .len = len, | |
444 | .rx_buf = data, | |
445 | }; | |
446 | ||
447 | spi_message_init(&msg); | |
448 | spi_message_add_tail(&xfer_head, &msg); | |
449 | spi_message_add_tail(&xfer_buf, &msg); | |
450 | ||
451 | mutex_lock(&priv->buffer_mutex); | |
452 | priv->buf[xfer_head.len++] = CC2520_CMD_RXBUF; | |
453 | ||
454 | dev_vdbg(&priv->spi->dev, "read rxfifo buf[0] = %02x\n", priv->buf[0]); | |
455 | dev_vdbg(&priv->spi->dev, "buf[1] = %02x\n", priv->buf[1]); | |
456 | ||
457 | status = spi_sync(priv->spi, &msg); | |
458 | dev_vdbg(&priv->spi->dev, "status = %d\n", status); | |
459 | if (msg.status) | |
460 | status = msg.status; | |
461 | dev_vdbg(&priv->spi->dev, "status = %d\n", status); | |
462 | dev_vdbg(&priv->spi->dev, | |
463 | "return status buf[0] = %02x\n", priv->buf[0]); | |
464 | dev_vdbg(&priv->spi->dev, "length buf[1] = %02x\n", priv->buf[1]); | |
465 | ||
466 | mutex_unlock(&priv->buffer_mutex); | |
467 | ||
468 | return status; | |
469 | } | |
470 | ||
5a504397 | 471 | static int cc2520_start(struct ieee802154_hw *hw) |
0da6bc8c | 472 | { |
5a504397 | 473 | return cc2520_cmd_strobe(hw->priv, CC2520_CMD_SRXON); |
0da6bc8c VB |
474 | } |
475 | ||
5a504397 | 476 | static void cc2520_stop(struct ieee802154_hw *hw) |
0da6bc8c | 477 | { |
5a504397 | 478 | cc2520_cmd_strobe(hw->priv, CC2520_CMD_SRFOFF); |
0da6bc8c VB |
479 | } |
480 | ||
481 | static int | |
5a504397 | 482 | cc2520_tx(struct ieee802154_hw *hw, struct sk_buff *skb) |
0da6bc8c | 483 | { |
5a504397 | 484 | struct cc2520_private *priv = hw->priv; |
0da6bc8c VB |
485 | unsigned long flags; |
486 | int rc; | |
487 | u8 status = 0; | |
59869ebf BC |
488 | u8 pkt_len; |
489 | ||
490 | /* In promiscuous mode we disable AUTOCRC so we can get the raw CRC | |
491 | * values on RX. This means we need to manually add the CRC on TX. | |
492 | */ | |
493 | if (priv->promiscuous) { | |
494 | u16 crc = crc_ccitt(0, skb->data, skb->len); | |
495 | ||
496 | put_unaligned_le16(crc, skb_put(skb, 2)); | |
497 | pkt_len = skb->len; | |
498 | } else { | |
499 | pkt_len = skb->len + 2; | |
500 | } | |
0da6bc8c VB |
501 | |
502 | rc = cc2520_cmd_strobe(priv, CC2520_CMD_SFLUSHTX); | |
503 | if (rc) | |
504 | goto err_tx; | |
505 | ||
59869ebf | 506 | rc = cc2520_write_txfifo(priv, pkt_len, skb->data, skb->len); |
0da6bc8c VB |
507 | if (rc) |
508 | goto err_tx; | |
509 | ||
510 | rc = cc2520_get_status(priv, &status); | |
511 | if (rc) | |
512 | goto err_tx; | |
513 | ||
514 | if (status & CC2520_STATUS_TX_UNDERFLOW) { | |
515 | dev_err(&priv->spi->dev, "cc2520 tx underflow exception\n"); | |
516 | goto err_tx; | |
517 | } | |
518 | ||
519 | spin_lock_irqsave(&priv->lock, flags); | |
520 | BUG_ON(priv->is_tx); | |
521 | priv->is_tx = 1; | |
522 | spin_unlock_irqrestore(&priv->lock, flags); | |
523 | ||
524 | rc = cc2520_cmd_strobe(priv, CC2520_CMD_STXONCCA); | |
525 | if (rc) | |
526 | goto err; | |
527 | ||
528 | rc = wait_for_completion_interruptible(&priv->tx_complete); | |
529 | if (rc < 0) | |
530 | goto err; | |
531 | ||
532 | cc2520_cmd_strobe(priv, CC2520_CMD_SFLUSHTX); | |
533 | cc2520_cmd_strobe(priv, CC2520_CMD_SRXON); | |
534 | ||
535 | return rc; | |
536 | err: | |
537 | spin_lock_irqsave(&priv->lock, flags); | |
538 | priv->is_tx = 0; | |
539 | spin_unlock_irqrestore(&priv->lock, flags); | |
540 | err_tx: | |
541 | return rc; | |
542 | } | |
543 | ||
0da6bc8c VB |
544 | static int cc2520_rx(struct cc2520_private *priv) |
545 | { | |
546 | u8 len = 0, lqi = 0, bytes = 1; | |
547 | struct sk_buff *skb; | |
548 | ||
59869ebf BC |
549 | /* Read single length byte from the radio. */ |
550 | cc2520_read_rxfifo(priv, &len, bytes); | |
0da6bc8c | 551 | |
59869ebf BC |
552 | if (!ieee802154_is_valid_psdu_len(len)) { |
553 | /* Corrupted frame received, clear frame buffer by | |
554 | * reading entire buffer. | |
555 | */ | |
556 | dev_dbg(&priv->spi->dev, "corrupted frame received\n"); | |
557 | len = IEEE802154_MTU; | |
558 | } | |
0da6bc8c | 559 | |
61a22814 | 560 | skb = dev_alloc_skb(len); |
0da6bc8c VB |
561 | if (!skb) |
562 | return -ENOMEM; | |
563 | ||
59869ebf | 564 | if (cc2520_read_rxfifo(priv, skb_put(skb, len), len)) { |
0da6bc8c VB |
565 | dev_dbg(&priv->spi->dev, "frame reception failed\n"); |
566 | kfree_skb(skb); | |
567 | return -EINVAL; | |
568 | } | |
569 | ||
59869ebf BC |
570 | /* In promiscuous mode, we configure the radio to include the |
571 | * CRC (AUTOCRC==0) and we pass on the packet unconditionally. If not | |
572 | * in promiscuous mode, we check the CRC here, but leave the | |
573 | * RSSI/LQI/CRC_OK bytes as they will get removed in the mac layer. | |
574 | */ | |
575 | if (!priv->promiscuous) { | |
576 | bool crc_ok; | |
577 | ||
578 | /* Check if the CRC is valid. With AUTOCRC set, the most | |
579 | * significant bit of the last byte returned from the CC2520 | |
580 | * is CRC_OK flag. See section 20.3.4 of the datasheet. | |
581 | */ | |
582 | crc_ok = skb->data[len - 1] & BIT(7); | |
583 | ||
584 | /* If we failed CRC drop the packet in the driver layer. */ | |
585 | if (!crc_ok) { | |
586 | dev_dbg(&priv->spi->dev, "CRC check failed\n"); | |
587 | kfree_skb(skb); | |
588 | return -EINVAL; | |
589 | } | |
590 | ||
591 | /* To calculate LQI, the lower 7 bits of the last byte (the | |
592 | * correlation value provided by the radio) must be scaled to | |
593 | * the range 0-255. According to section 20.6, the correlation | |
594 | * value ranges from 50-110. Ideally this would be calibrated | |
595 | * per hardware design, but we use roughly the datasheet values | |
596 | * to get close enough while avoiding floating point. | |
597 | */ | |
598 | lqi = skb->data[len - 1] & 0x7f; | |
599 | if (lqi < 50) | |
600 | lqi = 50; | |
601 | else if (lqi > 113) | |
602 | lqi = 113; | |
603 | lqi = (lqi - 50) * 4; | |
604 | } | |
0da6bc8c | 605 | |
5a504397 | 606 | ieee802154_rx_irqsafe(priv->hw, skb, lqi); |
0da6bc8c VB |
607 | |
608 | dev_vdbg(&priv->spi->dev, "RXFIFO: %x %x\n", len, lqi); | |
609 | ||
610 | return 0; | |
611 | } | |
612 | ||
613 | static int | |
5a504397 | 614 | cc2520_ed(struct ieee802154_hw *hw, u8 *level) |
0da6bc8c | 615 | { |
5a504397 | 616 | struct cc2520_private *priv = hw->priv; |
0da6bc8c VB |
617 | u8 status = 0xff; |
618 | u8 rssi; | |
619 | int ret; | |
620 | ||
3251ca33 | 621 | ret = cc2520_read_register(priv, CC2520_RSSISTAT, &status); |
0da6bc8c VB |
622 | if (ret) |
623 | return ret; | |
624 | ||
625 | if (status != RSSI_VALID) | |
626 | return -EINVAL; | |
627 | ||
3251ca33 | 628 | ret = cc2520_read_register(priv, CC2520_RSSI, &rssi); |
0da6bc8c VB |
629 | if (ret) |
630 | return ret; | |
631 | ||
632 | /* level = RSSI(rssi) - OFFSET [dBm] : offset is 76dBm */ | |
633 | *level = rssi - RSSI_OFFSET; | |
634 | ||
635 | return 0; | |
636 | } | |
637 | ||
638 | static int | |
e37d2ec8 | 639 | cc2520_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel) |
0da6bc8c | 640 | { |
5a504397 | 641 | struct cc2520_private *priv = hw->priv; |
0da6bc8c VB |
642 | int ret; |
643 | ||
0da6bc8c VB |
644 | dev_dbg(&priv->spi->dev, "trying to set channel\n"); |
645 | ||
646 | BUG_ON(page != 0); | |
647 | BUG_ON(channel < CC2520_MINCHANNEL); | |
648 | BUG_ON(channel > CC2520_MAXCHANNEL); | |
649 | ||
650 | ret = cc2520_write_register(priv, CC2520_FREQCTRL, | |
651 | 11 + 5*(channel - 11)); | |
652 | ||
653 | return ret; | |
654 | } | |
655 | ||
656 | static int | |
5a504397 | 657 | cc2520_filter(struct ieee802154_hw *hw, |
0da6bc8c VB |
658 | struct ieee802154_hw_addr_filt *filt, unsigned long changed) |
659 | { | |
5a504397 | 660 | struct cc2520_private *priv = hw->priv; |
c9d44203 | 661 | int ret = 0; |
0da6bc8c | 662 | |
57205c14 | 663 | if (changed & IEEE802154_AFILT_PANID_CHANGED) { |
0da6bc8c VB |
664 | u16 panid = le16_to_cpu(filt->pan_id); |
665 | ||
666 | dev_vdbg(&priv->spi->dev, | |
667 | "cc2520_filter called for pan id\n"); | |
c9d44203 SS |
668 | ret = cc2520_write_ram(priv, CC2520RAM_PANID, |
669 | sizeof(panid), (u8 *)&panid); | |
0da6bc8c VB |
670 | } |
671 | ||
57205c14 | 672 | if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) { |
0da6bc8c VB |
673 | dev_vdbg(&priv->spi->dev, |
674 | "cc2520_filter called for IEEE addr\n"); | |
c9d44203 SS |
675 | ret = cc2520_write_ram(priv, CC2520RAM_IEEEADDR, |
676 | sizeof(filt->ieee_addr), | |
677 | (u8 *)&filt->ieee_addr); | |
0da6bc8c VB |
678 | } |
679 | ||
57205c14 | 680 | if (changed & IEEE802154_AFILT_SADDR_CHANGED) { |
0da6bc8c VB |
681 | u16 addr = le16_to_cpu(filt->short_addr); |
682 | ||
683 | dev_vdbg(&priv->spi->dev, | |
684 | "cc2520_filter called for saddr\n"); | |
c9d44203 SS |
685 | ret = cc2520_write_ram(priv, CC2520RAM_SHORTADDR, |
686 | sizeof(addr), (u8 *)&addr); | |
0da6bc8c VB |
687 | } |
688 | ||
57205c14 | 689 | if (changed & IEEE802154_AFILT_PANC_CHANGED) { |
59869ebf BC |
690 | u8 frmfilt0; |
691 | ||
0da6bc8c VB |
692 | dev_vdbg(&priv->spi->dev, |
693 | "cc2520_filter called for panc change\n"); | |
59869ebf BC |
694 | |
695 | cc2520_read_register(priv, CC2520_FRMFILT0, &frmfilt0); | |
696 | ||
0da6bc8c | 697 | if (filt->pan_coord) |
59869ebf | 698 | frmfilt0 |= FRMFILT0_PAN_COORDINATOR; |
0da6bc8c | 699 | else |
59869ebf BC |
700 | frmfilt0 &= ~FRMFILT0_PAN_COORDINATOR; |
701 | ||
702 | ret = cc2520_write_register(priv, CC2520_FRMFILT0, frmfilt0); | |
0da6bc8c VB |
703 | } |
704 | ||
c9d44203 | 705 | return ret; |
0da6bc8c VB |
706 | } |
707 | ||
e10c1674 VB |
708 | static inline int cc2520_set_tx_power(struct cc2520_private *priv, s32 mbm) |
709 | { | |
710 | u8 power; | |
711 | ||
712 | switch (mbm) { | |
713 | case 500: | |
714 | power = 0xF7; | |
715 | break; | |
716 | case 300: | |
717 | power = 0xF2; | |
718 | break; | |
719 | case 200: | |
720 | power = 0xAB; | |
721 | break; | |
722 | case 100: | |
723 | power = 0x13; | |
724 | break; | |
725 | case 0: | |
726 | power = 0x32; | |
727 | break; | |
728 | case -200: | |
729 | power = 0x81; | |
730 | break; | |
731 | case -400: | |
732 | power = 0x88; | |
733 | break; | |
734 | case -700: | |
735 | power = 0x2C; | |
736 | break; | |
737 | case -1800: | |
738 | power = 0x03; | |
739 | break; | |
740 | default: | |
741 | return -EINVAL; | |
742 | } | |
743 | ||
744 | return cc2520_write_register(priv, CC2520_TXPOWER, power); | |
745 | } | |
746 | ||
747 | static inline int cc2520_cc2591_set_tx_power(struct cc2520_private *priv, | |
748 | s32 mbm) | |
749 | { | |
750 | u8 power; | |
751 | ||
752 | switch (mbm) { | |
753 | case 1700: | |
754 | power = 0xF9; | |
755 | break; | |
756 | case 1600: | |
757 | power = 0xF0; | |
758 | break; | |
759 | case 1400: | |
760 | power = 0xA0; | |
761 | break; | |
762 | case 1100: | |
763 | power = 0x2C; | |
764 | break; | |
765 | case -100: | |
766 | power = 0x03; | |
767 | break; | |
768 | case -800: | |
769 | power = 0x01; | |
770 | break; | |
771 | default: | |
772 | return -EINVAL; | |
773 | } | |
774 | ||
775 | return cc2520_write_register(priv, CC2520_TXPOWER, power); | |
776 | } | |
777 | ||
778 | #define CC2520_MAX_TX_POWERS 0x8 | |
779 | static const s32 cc2520_powers[CC2520_MAX_TX_POWERS + 1] = { | |
780 | 500, 300, 200, 100, 0, -200, -400, -700, -1800, | |
781 | }; | |
782 | ||
783 | #define CC2520_CC2591_MAX_TX_POWERS 0x5 | |
784 | static const s32 cc2520_cc2591_powers[CC2520_CC2591_MAX_TX_POWERS + 1] = { | |
785 | 1700, 1600, 1400, 1100, -100, -800, | |
786 | }; | |
787 | ||
788 | static int | |
789 | cc2520_set_txpower(struct ieee802154_hw *hw, s32 mbm) | |
790 | { | |
791 | struct cc2520_private *priv = hw->priv; | |
792 | ||
793 | if (!priv->amplified) | |
794 | return cc2520_set_tx_power(priv, mbm); | |
795 | ||
796 | return cc2520_cc2591_set_tx_power(priv, mbm); | |
797 | } | |
798 | ||
59869ebf BC |
799 | static int |
800 | cc2520_set_promiscuous_mode(struct ieee802154_hw *hw, bool on) | |
801 | { | |
802 | struct cc2520_private *priv = hw->priv; | |
803 | u8 frmfilt0; | |
804 | ||
805 | dev_dbg(&priv->spi->dev, "%s : mode %d\n", __func__, on); | |
806 | ||
807 | priv->promiscuous = on; | |
808 | ||
809 | cc2520_read_register(priv, CC2520_FRMFILT0, &frmfilt0); | |
810 | ||
811 | if (on) { | |
812 | /* Disable automatic ACK, automatic CRC, and frame filtering. */ | |
813 | cc2520_write_register(priv, CC2520_FRMCTRL0, 0); | |
814 | frmfilt0 &= ~FRMFILT0_FRAME_FILTER_EN; | |
815 | } else { | |
816 | cc2520_write_register(priv, CC2520_FRMCTRL0, FRMCTRL0_AUTOACK | | |
817 | FRMCTRL0_AUTOCRC); | |
818 | frmfilt0 |= FRMFILT0_FRAME_FILTER_EN; | |
819 | } | |
820 | return cc2520_write_register(priv, CC2520_FRMFILT0, frmfilt0); | |
821 | } | |
822 | ||
16301861 | 823 | static const struct ieee802154_ops cc2520_ops = { |
0da6bc8c VB |
824 | .owner = THIS_MODULE, |
825 | .start = cc2520_start, | |
826 | .stop = cc2520_stop, | |
ed0a5dce | 827 | .xmit_sync = cc2520_tx, |
0da6bc8c VB |
828 | .ed = cc2520_ed, |
829 | .set_channel = cc2520_set_channel, | |
830 | .set_hw_addr_filt = cc2520_filter, | |
e10c1674 | 831 | .set_txpower = cc2520_set_txpower, |
59869ebf | 832 | .set_promiscuous_mode = cc2520_set_promiscuous_mode, |
0da6bc8c VB |
833 | }; |
834 | ||
835 | static int cc2520_register(struct cc2520_private *priv) | |
836 | { | |
837 | int ret = -ENOMEM; | |
838 | ||
5a504397 AA |
839 | priv->hw = ieee802154_alloc_hw(sizeof(*priv), &cc2520_ops); |
840 | if (!priv->hw) | |
0da6bc8c VB |
841 | goto err_ret; |
842 | ||
5a504397 AA |
843 | priv->hw->priv = priv; |
844 | priv->hw->parent = &priv->spi->dev; | |
845 | priv->hw->extra_tx_headroom = 0; | |
7fc1b2d5 | 846 | ieee802154_random_extended_addr(&priv->hw->phy->perm_extended_addr); |
0da6bc8c VB |
847 | |
848 | /* We do support only 2.4 Ghz */ | |
72f655e4 | 849 | priv->hw->phy->supported.channels[0] = 0x7FFF800; |
59869ebf BC |
850 | priv->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT | |
851 | IEEE802154_HW_PROMISCUOUS; | |
0da6bc8c | 852 | |
e10c1674 VB |
853 | priv->hw->phy->flags = WPAN_PHY_FLAG_TXPOWER; |
854 | ||
855 | if (!priv->amplified) { | |
856 | priv->hw->phy->supported.tx_powers = cc2520_powers; | |
857 | priv->hw->phy->supported.tx_powers_size = ARRAY_SIZE(cc2520_powers); | |
322fe2d1 | 858 | priv->hw->phy->transmit_power = priv->hw->phy->supported.tx_powers[4]; |
e10c1674 VB |
859 | } else { |
860 | priv->hw->phy->supported.tx_powers = cc2520_cc2591_powers; | |
861 | priv->hw->phy->supported.tx_powers_size = ARRAY_SIZE(cc2520_cc2591_powers); | |
322fe2d1 | 862 | priv->hw->phy->transmit_power = priv->hw->phy->supported.tx_powers[0]; |
e10c1674 VB |
863 | } |
864 | ||
d6d244d4 VB |
865 | priv->hw->phy->current_channel = 11; |
866 | ||
0da6bc8c | 867 | dev_vdbg(&priv->spi->dev, "registered cc2520\n"); |
5a504397 | 868 | ret = ieee802154_register_hw(priv->hw); |
0da6bc8c VB |
869 | if (ret) |
870 | goto err_free_device; | |
871 | ||
872 | return 0; | |
873 | ||
874 | err_free_device: | |
5a504397 | 875 | ieee802154_free_hw(priv->hw); |
0da6bc8c VB |
876 | err_ret: |
877 | return ret; | |
878 | } | |
879 | ||
880 | static void cc2520_fifop_irqwork(struct work_struct *work) | |
881 | { | |
882 | struct cc2520_private *priv | |
883 | = container_of(work, struct cc2520_private, fifop_irqwork); | |
884 | ||
885 | dev_dbg(&priv->spi->dev, "fifop interrupt received\n"); | |
886 | ||
887 | if (gpio_get_value(priv->fifo_pin)) | |
888 | cc2520_rx(priv); | |
889 | else | |
890 | dev_dbg(&priv->spi->dev, "rxfifo overflow\n"); | |
891 | ||
892 | cc2520_cmd_strobe(priv, CC2520_CMD_SFLUSHRX); | |
893 | cc2520_cmd_strobe(priv, CC2520_CMD_SFLUSHRX); | |
894 | } | |
895 | ||
896 | static irqreturn_t cc2520_fifop_isr(int irq, void *data) | |
897 | { | |
898 | struct cc2520_private *priv = data; | |
899 | ||
900 | schedule_work(&priv->fifop_irqwork); | |
901 | ||
902 | return IRQ_HANDLED; | |
903 | } | |
904 | ||
905 | static irqreturn_t cc2520_sfd_isr(int irq, void *data) | |
906 | { | |
907 | struct cc2520_private *priv = data; | |
908 | unsigned long flags; | |
909 | ||
910 | spin_lock_irqsave(&priv->lock, flags); | |
911 | if (priv->is_tx) { | |
912 | priv->is_tx = 0; | |
913 | spin_unlock_irqrestore(&priv->lock, flags); | |
914 | dev_dbg(&priv->spi->dev, "SFD for TX\n"); | |
915 | complete(&priv->tx_complete); | |
916 | } else { | |
917 | spin_unlock_irqrestore(&priv->lock, flags); | |
918 | dev_dbg(&priv->spi->dev, "SFD for RX\n"); | |
919 | } | |
920 | ||
921 | return IRQ_HANDLED; | |
922 | } | |
923 | ||
0db055c9 BC |
924 | static int cc2520_get_platform_data(struct spi_device *spi, |
925 | struct cc2520_platform_data *pdata) | |
926 | { | |
927 | struct device_node *np = spi->dev.of_node; | |
928 | struct cc2520_private *priv = spi_get_drvdata(spi); | |
929 | ||
930 | if (!np) { | |
931 | struct cc2520_platform_data *spi_pdata = spi->dev.platform_data; | |
932 | if (!spi_pdata) | |
933 | return -ENOENT; | |
934 | *pdata = *spi_pdata; | |
85998229 | 935 | priv->fifo_pin = pdata->fifo; |
0db055c9 BC |
936 | return 0; |
937 | } | |
938 | ||
939 | pdata->fifo = of_get_named_gpio(np, "fifo-gpio", 0); | |
940 | priv->fifo_pin = pdata->fifo; | |
941 | ||
942 | pdata->fifop = of_get_named_gpio(np, "fifop-gpio", 0); | |
943 | ||
944 | pdata->sfd = of_get_named_gpio(np, "sfd-gpio", 0); | |
945 | pdata->cca = of_get_named_gpio(np, "cca-gpio", 0); | |
946 | pdata->vreg = of_get_named_gpio(np, "vreg-gpio", 0); | |
947 | pdata->reset = of_get_named_gpio(np, "reset-gpio", 0); | |
948 | ||
1a1bc59c VB |
949 | /* CC2591 front end for CC2520 */ |
950 | if (of_property_read_bool(np, "amplified")) | |
951 | priv->amplified = true; | |
f0b7d43c | 952 | |
0db055c9 BC |
953 | return 0; |
954 | } | |
955 | ||
0da6bc8c VB |
956 | static int cc2520_hw_init(struct cc2520_private *priv) |
957 | { | |
958 | u8 status = 0, state = 0xff; | |
959 | int ret; | |
960 | int timeout = 100; | |
f0b7d43c BC |
961 | struct cc2520_platform_data pdata; |
962 | ||
963 | ret = cc2520_get_platform_data(priv->spi, &pdata); | |
964 | if (ret) | |
965 | goto err_ret; | |
0da6bc8c VB |
966 | |
967 | ret = cc2520_read_register(priv, CC2520_FSMSTAT1, &state); | |
968 | if (ret) | |
969 | goto err_ret; | |
970 | ||
971 | if (state != STATE_IDLE) | |
972 | return -EINVAL; | |
973 | ||
974 | do { | |
975 | ret = cc2520_get_status(priv, &status); | |
976 | if (ret) | |
977 | goto err_ret; | |
978 | ||
979 | if (timeout-- <= 0) { | |
980 | dev_err(&priv->spi->dev, "oscillator start failed!\n"); | |
981 | return ret; | |
982 | } | |
983 | udelay(1); | |
984 | } while (!(status & CC2520_STATUS_XOSC32M_STABLE)); | |
985 | ||
986 | dev_vdbg(&priv->spi->dev, "oscillator brought up\n"); | |
987 | ||
f0b7d43c BC |
988 | /* If the CC2520 is connected to a CC2591 amplifier, we must both |
989 | * configure GPIOs on the CC2520 to correctly configure the CC2591 | |
990 | * and change a couple settings of the CC2520 to work with the | |
991 | * amplifier. See section 8 page 17 of TI application note AN065. | |
992 | * http://www.ti.com/lit/an/swra229a/swra229a.pdf | |
993 | */ | |
1a1bc59c | 994 | if (priv->amplified) { |
f0b7d43c BC |
995 | ret = cc2520_write_register(priv, CC2520_AGCCTRL1, 0x16); |
996 | if (ret) | |
997 | goto err_ret; | |
998 | ||
999 | ret = cc2520_write_register(priv, CC2520_GPIOCTRL0, 0x46); | |
1000 | if (ret) | |
1001 | goto err_ret; | |
1002 | ||
1003 | ret = cc2520_write_register(priv, CC2520_GPIOCTRL5, 0x47); | |
1004 | if (ret) | |
1005 | goto err_ret; | |
1006 | ||
1007 | ret = cc2520_write_register(priv, CC2520_GPIOPOLARITY, 0x1e); | |
1008 | if (ret) | |
1009 | goto err_ret; | |
1010 | ||
1011 | ret = cc2520_write_register(priv, CC2520_TXCTRL, 0xc1); | |
1012 | if (ret) | |
1013 | goto err_ret; | |
1014 | } else { | |
f0b7d43c BC |
1015 | ret = cc2520_write_register(priv, CC2520_AGCCTRL1, 0x11); |
1016 | if (ret) | |
1017 | goto err_ret; | |
1018 | } | |
0da6bc8c | 1019 | |
f0b7d43c | 1020 | /* Registers default value: section 28.1 in Datasheet */ |
59869ebf BC |
1021 | |
1022 | /* Set the CCA threshold to -50 dBm. This seems to have been copied | |
1023 | * from the TinyOS CC2520 driver and is much higher than the -84 dBm | |
1024 | * threshold suggested in the datasheet. | |
1025 | */ | |
0da6bc8c VB |
1026 | ret = cc2520_write_register(priv, CC2520_CCACTRL0, 0x1A); |
1027 | if (ret) | |
1028 | goto err_ret; | |
1029 | ||
1030 | ret = cc2520_write_register(priv, CC2520_MDMCTRL0, 0x85); | |
1031 | if (ret) | |
1032 | goto err_ret; | |
1033 | ||
1034 | ret = cc2520_write_register(priv, CC2520_MDMCTRL1, 0x14); | |
1035 | if (ret) | |
1036 | goto err_ret; | |
1037 | ||
1038 | ret = cc2520_write_register(priv, CC2520_RXCTRL, 0x3f); | |
1039 | if (ret) | |
1040 | goto err_ret; | |
1041 | ||
1042 | ret = cc2520_write_register(priv, CC2520_FSCTRL, 0x5a); | |
1043 | if (ret) | |
1044 | goto err_ret; | |
1045 | ||
1046 | ret = cc2520_write_register(priv, CC2520_FSCAL1, 0x2b); | |
1047 | if (ret) | |
1048 | goto err_ret; | |
1049 | ||
0da6bc8c VB |
1050 | ret = cc2520_write_register(priv, CC2520_ADCTEST0, 0x10); |
1051 | if (ret) | |
1052 | goto err_ret; | |
1053 | ||
1054 | ret = cc2520_write_register(priv, CC2520_ADCTEST1, 0x0e); | |
1055 | if (ret) | |
1056 | goto err_ret; | |
1057 | ||
1058 | ret = cc2520_write_register(priv, CC2520_ADCTEST2, 0x03); | |
1059 | if (ret) | |
1060 | goto err_ret; | |
1061 | ||
59869ebf BC |
1062 | /* Configure registers correctly for this driver. */ |
1063 | ret = cc2520_write_register(priv, CC2520_FRMCTRL1, | |
1064 | FRMCTRL1_SET_RXENMASK_ON_TX | | |
1065 | FRMCTRL1_IGNORE_TX_UNDERF); | |
0da6bc8c VB |
1066 | if (ret) |
1067 | goto err_ret; | |
1068 | ||
1069 | ret = cc2520_write_register(priv, CC2520_FIFOPCTRL, 127); | |
1070 | if (ret) | |
1071 | goto err_ret; | |
1072 | ||
1073 | return 0; | |
1074 | ||
1075 | err_ret: | |
1076 | return ret; | |
1077 | } | |
1078 | ||
0da6bc8c VB |
1079 | static int cc2520_probe(struct spi_device *spi) |
1080 | { | |
1081 | struct cc2520_private *priv; | |
0db055c9 | 1082 | struct cc2520_platform_data pdata; |
0da6bc8c VB |
1083 | int ret; |
1084 | ||
5eb9f8ca | 1085 | priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL); |
f50f1c37 VB |
1086 | if (!priv) |
1087 | return -ENOMEM; | |
0da6bc8c VB |
1088 | |
1089 | spi_set_drvdata(spi, priv); | |
1090 | ||
0db055c9 BC |
1091 | ret = cc2520_get_platform_data(spi, &pdata); |
1092 | if (ret < 0) { | |
0da6bc8c VB |
1093 | dev_err(&spi->dev, "no platform data\n"); |
1094 | return -EINVAL; | |
1095 | } | |
1096 | ||
1097 | priv->spi = spi; | |
1098 | ||
1099 | priv->buf = devm_kzalloc(&spi->dev, | |
1100 | SPI_COMMAND_BUFFER, GFP_KERNEL); | |
f50f1c37 VB |
1101 | if (!priv->buf) |
1102 | return -ENOMEM; | |
0da6bc8c VB |
1103 | |
1104 | mutex_init(&priv->buffer_mutex); | |
1105 | INIT_WORK(&priv->fifop_irqwork, cc2520_fifop_irqwork); | |
1106 | spin_lock_init(&priv->lock); | |
1107 | init_completion(&priv->tx_complete); | |
1108 | ||
1a1bc59c VB |
1109 | /* Assumption that CC2591 is not connected */ |
1110 | priv->amplified = false; | |
1111 | ||
0da6bc8c | 1112 | /* Request all the gpio's */ |
0db055c9 | 1113 | if (!gpio_is_valid(pdata.fifo)) { |
0da6bc8c VB |
1114 | dev_err(&spi->dev, "fifo gpio is not valid\n"); |
1115 | ret = -EINVAL; | |
1116 | goto err_hw_init; | |
1117 | } | |
1118 | ||
0db055c9 | 1119 | ret = devm_gpio_request_one(&spi->dev, pdata.fifo, |
0da6bc8c VB |
1120 | GPIOF_IN, "fifo"); |
1121 | if (ret) | |
1122 | goto err_hw_init; | |
1123 | ||
0db055c9 | 1124 | if (!gpio_is_valid(pdata.cca)) { |
0da6bc8c VB |
1125 | dev_err(&spi->dev, "cca gpio is not valid\n"); |
1126 | ret = -EINVAL; | |
1127 | goto err_hw_init; | |
1128 | } | |
1129 | ||
0db055c9 | 1130 | ret = devm_gpio_request_one(&spi->dev, pdata.cca, |
0da6bc8c VB |
1131 | GPIOF_IN, "cca"); |
1132 | if (ret) | |
1133 | goto err_hw_init; | |
1134 | ||
0db055c9 | 1135 | if (!gpio_is_valid(pdata.fifop)) { |
0da6bc8c VB |
1136 | dev_err(&spi->dev, "fifop gpio is not valid\n"); |
1137 | ret = -EINVAL; | |
1138 | goto err_hw_init; | |
1139 | } | |
1140 | ||
0db055c9 | 1141 | ret = devm_gpio_request_one(&spi->dev, pdata.fifop, |
0da6bc8c VB |
1142 | GPIOF_IN, "fifop"); |
1143 | if (ret) | |
1144 | goto err_hw_init; | |
1145 | ||
0db055c9 | 1146 | if (!gpio_is_valid(pdata.sfd)) { |
0da6bc8c VB |
1147 | dev_err(&spi->dev, "sfd gpio is not valid\n"); |
1148 | ret = -EINVAL; | |
1149 | goto err_hw_init; | |
1150 | } | |
1151 | ||
0db055c9 | 1152 | ret = devm_gpio_request_one(&spi->dev, pdata.sfd, |
0da6bc8c VB |
1153 | GPIOF_IN, "sfd"); |
1154 | if (ret) | |
1155 | goto err_hw_init; | |
1156 | ||
0db055c9 | 1157 | if (!gpio_is_valid(pdata.reset)) { |
0da6bc8c VB |
1158 | dev_err(&spi->dev, "reset gpio is not valid\n"); |
1159 | ret = -EINVAL; | |
1160 | goto err_hw_init; | |
1161 | } | |
1162 | ||
0db055c9 | 1163 | ret = devm_gpio_request_one(&spi->dev, pdata.reset, |
0da6bc8c VB |
1164 | GPIOF_OUT_INIT_LOW, "reset"); |
1165 | if (ret) | |
1166 | goto err_hw_init; | |
1167 | ||
0db055c9 | 1168 | if (!gpio_is_valid(pdata.vreg)) { |
0da6bc8c VB |
1169 | dev_err(&spi->dev, "vreg gpio is not valid\n"); |
1170 | ret = -EINVAL; | |
1171 | goto err_hw_init; | |
1172 | } | |
1173 | ||
0db055c9 | 1174 | ret = devm_gpio_request_one(&spi->dev, pdata.vreg, |
0da6bc8c VB |
1175 | GPIOF_OUT_INIT_LOW, "vreg"); |
1176 | if (ret) | |
1177 | goto err_hw_init; | |
1178 | ||
0db055c9 | 1179 | gpio_set_value(pdata.vreg, HIGH); |
0da6bc8c VB |
1180 | usleep_range(100, 150); |
1181 | ||
0db055c9 | 1182 | gpio_set_value(pdata.reset, HIGH); |
0da6bc8c VB |
1183 | usleep_range(200, 250); |
1184 | ||
1185 | ret = cc2520_hw_init(priv); | |
1186 | if (ret) | |
1187 | goto err_hw_init; | |
1188 | ||
1189 | /* Set up fifop interrupt */ | |
1190 | ret = devm_request_irq(&spi->dev, | |
0db055c9 | 1191 | gpio_to_irq(pdata.fifop), |
0da6bc8c VB |
1192 | cc2520_fifop_isr, |
1193 | IRQF_TRIGGER_RISING, | |
1194 | dev_name(&spi->dev), | |
1195 | priv); | |
1196 | if (ret) { | |
1197 | dev_err(&spi->dev, "could not get fifop irq\n"); | |
1198 | goto err_hw_init; | |
1199 | } | |
1200 | ||
1201 | /* Set up sfd interrupt */ | |
1202 | ret = devm_request_irq(&spi->dev, | |
0db055c9 | 1203 | gpio_to_irq(pdata.sfd), |
0da6bc8c VB |
1204 | cc2520_sfd_isr, |
1205 | IRQF_TRIGGER_FALLING, | |
1206 | dev_name(&spi->dev), | |
1207 | priv); | |
1208 | if (ret) { | |
1209 | dev_err(&spi->dev, "could not get sfd irq\n"); | |
1210 | goto err_hw_init; | |
1211 | } | |
1212 | ||
1213 | ret = cc2520_register(priv); | |
1214 | if (ret) | |
1215 | goto err_hw_init; | |
1216 | ||
1217 | return 0; | |
1218 | ||
1219 | err_hw_init: | |
1220 | mutex_destroy(&priv->buffer_mutex); | |
1221 | flush_work(&priv->fifop_irqwork); | |
0da6bc8c VB |
1222 | return ret; |
1223 | } | |
1224 | ||
1225 | static int cc2520_remove(struct spi_device *spi) | |
1226 | { | |
1227 | struct cc2520_private *priv = spi_get_drvdata(spi); | |
1228 | ||
1229 | mutex_destroy(&priv->buffer_mutex); | |
1230 | flush_work(&priv->fifop_irqwork); | |
1231 | ||
5a504397 AA |
1232 | ieee802154_unregister_hw(priv->hw); |
1233 | ieee802154_free_hw(priv->hw); | |
0da6bc8c VB |
1234 | |
1235 | return 0; | |
1236 | } | |
1237 | ||
1238 | static const struct spi_device_id cc2520_ids[] = { | |
1239 | {"cc2520", }, | |
1240 | {}, | |
1241 | }; | |
1242 | MODULE_DEVICE_TABLE(spi, cc2520_ids); | |
1243 | ||
1244 | static const struct of_device_id cc2520_of_ids[] = { | |
1245 | {.compatible = "ti,cc2520", }, | |
1246 | {}, | |
1247 | }; | |
1248 | MODULE_DEVICE_TABLE(of, cc2520_of_ids); | |
1249 | ||
1250 | /* SPI driver structure */ | |
1251 | static struct spi_driver cc2520_driver = { | |
1252 | .driver = { | |
1253 | .name = "cc2520", | |
0da6bc8c VB |
1254 | .of_match_table = of_match_ptr(cc2520_of_ids), |
1255 | }, | |
1256 | .id_table = cc2520_ids, | |
1257 | .probe = cc2520_probe, | |
1258 | .remove = cc2520_remove, | |
1259 | }; | |
1260 | module_spi_driver(cc2520_driver); | |
1261 | ||
1262 | MODULE_AUTHOR("Varka Bhadram <varkab@cdac.in>"); | |
1263 | MODULE_DESCRIPTION("CC2520 Transceiver Driver"); | |
1264 | MODULE_LICENSE("GPL v2"); |